* [PATCH] drm/display/dsc: Add YCbCr 4:2:2 and 4:2:0 computation for DSC 1.2 RC parameters
@ 2026-09-23 10:26 Chaoyi Chen
2026-09-23 10:34 ` sashiko-bot
0 siblings, 1 reply; 2+ messages in thread
From: Chaoyi Chen @ 2026-09-23 10:26 UTC (permalink / raw)
To: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Dmitry Baryshkov
Cc: Chaoyi Chen, dri-devel, linux-kernel, Chaoyi Chen
drm_dsc_compute_rc_parameters() still derives the rate control
parameters that depend on native 4:2:0/4:2:2 operation using the
DSC 1.1 model.
Bring the helper in line with the latest DSC 1.2 reference
implementation (C model 20211213, version 1.67):
- Compute second_line_bpg_offset, second_line_offset_adj and
nsl_bpg_offset for native 4:2:0.
- Compute rbsMin for DSC 1.2 native 4:2:0/4:2:2 using the optimized
method of the C model.
Signed-off-by: Chaoyi Chen <kernel@airkyi.com>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 114 ++++++++++++++++++++++-
1 file changed, 109 insertions(+), 5 deletions(-)
mode change 100644 => 100755 drivers/gpu/drm/display/drm_dsc_helper.c
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 05996c526a8a..90b088335997
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -1300,6 +1300,59 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params
}
EXPORT_SYMBOL(drm_dsc_setup_rc_params);
+/**
+ * __drm_dsc_compute_buffer_offset - Compute the rate buffer offset at a given
+ * group position within a slice, following the method of the DSC 1.2 C model.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ * @groups_per_line: number of groups used to code each line of a slice
+ * @grpcnt: group position to compute the offset for
+ *
+ * Return: the offset value for the group @grpcnt.
+ */
+static long
+__drm_dsc_compute_buffer_offset(const struct drm_dsc_config *vdsc_cfg,
+ unsigned long groups_per_line,
+ unsigned long grpcnt)
+{
+ unsigned long grpcnt_id = DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
+ DSC_RC_PIXELS_PER_GROUP);
+ long offset;
+
+ if (grpcnt <= grpcnt_id)
+ offset = DIV_ROUND_UP(grpcnt * DSC_RC_PIXELS_PER_GROUP *
+ vdsc_cfg->bits_per_pixel, 16);
+ else
+ offset = DIV_ROUND_UP(grpcnt_id * DSC_RC_PIXELS_PER_GROUP *
+ vdsc_cfg->bits_per_pixel, 16) -
+ (((grpcnt - grpcnt_id) *
+ vdsc_cfg->slice_bpg_offset) >> 11);
+
+ if (grpcnt <= groups_per_line)
+ offset += grpcnt * vdsc_cfg->first_line_bpg_offset;
+ else
+ offset += groups_per_line * vdsc_cfg->first_line_bpg_offset -
+ (((grpcnt - groups_per_line) *
+ vdsc_cfg->nfl_bpg_offset) >> 11);
+
+ if (vdsc_cfg->native_420) {
+ if (grpcnt <= groups_per_line)
+ offset -= (grpcnt * vdsc_cfg->nsl_bpg_offset) >> 11;
+ else if (grpcnt <= 2 * groups_per_line)
+ offset += (grpcnt - groups_per_line) *
+ vdsc_cfg->second_line_bpg_offset -
+ ((groups_per_line *
+ vdsc_cfg->nsl_bpg_offset) >> 11);
+ else
+ offset += (grpcnt - groups_per_line) *
+ vdsc_cfg->second_line_bpg_offset -
+ (((grpcnt - groups_per_line) *
+ vdsc_cfg->nsl_bpg_offset) >> 11);
+ }
+
+ return offset;
+}
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
@@ -1391,6 +1444,36 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
else
vdsc_cfg->nfl_bpg_offset = 0;
+ /*
+ * According to DSC 1.2 spec in Section 4.1 if native_420 is set:
+ * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
+ * height < 8.
+ * -second_line_offset_adj is 512 as shown by emperical values to yield best chroma
+ * preservation in second line.
+ * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
+ * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
+ * fractional bits.
+ */
+ if (vdsc_cfg->native_420) {
+ if (vdsc_cfg->slice_height >= 8)
+ vdsc_cfg->second_line_bpg_offset = 12;
+ else
+ vdsc_cfg->second_line_bpg_offset =
+ 2 * (vdsc_cfg->slice_height - 1);
+
+ vdsc_cfg->second_line_offset_adj = 512;
+ } else {
+ vdsc_cfg->second_line_bpg_offset = 0;
+ vdsc_cfg->second_line_offset_adj = 0;
+ }
+
+ if (vdsc_cfg->native_420 && vdsc_cfg->slice_height > 2)
+ vdsc_cfg->nsl_bpg_offset =
+ DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
+ (vdsc_cfg->slice_height - 1));
+ else
+ vdsc_cfg->nsl_bpg_offset = 0;
+
/* Number of groups used to code the entire slice */
groups_total = groups_per_line * vdsc_cfg->slice_height;
@@ -1410,7 +1493,9 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
vdsc_cfg->scale_increment_interval =
(vdsc_cfg->final_offset * (1 << 11)) /
((vdsc_cfg->nfl_bpg_offset +
- vdsc_cfg->slice_bpg_offset) *
+ vdsc_cfg->slice_bpg_offset +
+ (vdsc_cfg->native_420 ?
+ vdsc_cfg->nsl_bpg_offset : 0)) *
(final_scale - 9));
} else {
/*
@@ -1425,10 +1510,29 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
* bits/pixel (bpp) rate that is used by the encoder,
* in steps of 1/16 of a bit per pixel
*/
- rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
- DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
- vdsc_cfg->bits_per_pixel, 16) +
- groups_per_line * vdsc_cfg->first_line_bpg_offset;
+ if (vdsc_cfg->dsc_version_minor == 2 &&
+ (vdsc_cfg->native_420 || vdsc_cfg->native_422)) {
+ /* Optimized computation of rbsMin for DSC 1.2 */
+ unsigned long grpcnt_id =
+ DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
+ DSC_RC_PIXELS_PER_GROUP);
+ long max_offset;
+
+ max_offset = __drm_dsc_compute_buffer_offset(vdsc_cfg, groups_per_line, grpcnt_id);
+ max_offset = max(max_offset,
+ __drm_dsc_compute_buffer_offset(vdsc_cfg, groups_per_line,
+ groups_per_line));
+ max_offset = max(max_offset,
+ __drm_dsc_compute_buffer_offset(vdsc_cfg, groups_per_line,
+ 2 * groups_per_line));
+
+ rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + max_offset;
+ } else {
+ rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
+ DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
+ vdsc_cfg->bits_per_pixel, 16) +
+ groups_per_line * vdsc_cfg->first_line_bpg_offset;
+ }
hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
--
2.53.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/display/dsc: Add YCbCr 4:2:2 and 4:2:0 computation for DSC 1.2 RC parameters
2026-09-23 10:26 [PATCH] drm/display/dsc: Add YCbCr 4:2:2 and 4:2:0 computation for DSC 1.2 RC parameters Chaoyi Chen
@ 2026-09-23 10:34 ` sashiko-bot
0 siblings, 0 replies; 2+ messages in thread
From: sashiko-bot @ 2026-09-23 10:34 UTC (permalink / raw)
To: Chaoyi Chen; +Cc: dri-devel
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/dsc: incorrect second line BPG offset accumulation
--
commit b83356cde3094c64861089db4359f0b624aad6bd
Author: Chaoyi Chen <kernel@airkyi.com>
drm/display/dsc: Add YCbCr 4:2:2 and 4:2:0 computation for DSC 1.2 RC parameters
This commit updates drm_dsc_compute_rc_parameters() to compute rate control
parameters for DSC 1.2 in native 4:2:0 and 4:2:2 modes. It also introduces
__drm_dsc_compute_buffer_offset() to optimize the calculation of rbsMin
using the DSC 1.2 reference C model.
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -1300,6 +1300,59 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params
[ ... ]
> +static long
> +__drm_dsc_compute_buffer_offset(const struct drm_dsc_config *vdsc_cfg,
> + unsigned long groups_per_line,
> + unsigned long grpcnt)
> +{
[ ... ]
> + if (vdsc_cfg->native_420) {
> + if (grpcnt <= groups_per_line)
> + offset -= (grpcnt * vdsc_cfg->nsl_bpg_offset) >> 11;
> + else if (grpcnt <= 2 * groups_per_line)
> + offset += (grpcnt - groups_per_line) *
> + vdsc_cfg->second_line_bpg_offset -
> + ((groups_per_line *
> + vdsc_cfg->nsl_bpg_offset) >> 11);
> + else
> + offset += (grpcnt - groups_per_line) *
> + vdsc_cfg->second_line_bpg_offset -
> + (((grpcnt - groups_per_line) *
> + vdsc_cfg->nsl_bpg_offset) >> 11);
[Severity: High]
Does this code inflate the accumulated offset for groups beyond the second
line?
In the branch where grpcnt > 2 * groups_per_line, the calculation multiplies
(grpcnt - groups_per_line) by vdsc_cfg->second_line_bpg_offset. Should this
be capped to groups_per_line * vdsc_cfg->second_line_bpg_offset instead?
When grpcnt_id is large (which is common for narrow slices), this unbounded
linear growth could significantly inflate the rate buffer size minimum
(rbs_min). This might result in invalid rate control parameters (rc_bits,
initial_dec_delay) and cause display configuration failures or corrupted
output when a 4:2:0 DSC-capable sink is connected.
> + }
> +
> + return offset;
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260923102616.215-1-kernel@airkyi.com?part=1
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