* [PATCH v2 1/3] drm/amd/display: Fix implicit enum conversion
2023-02-17 18:14 [PATCH v2 0/3] Resolve warnings from AMDGPU Arthur Grillo
@ 2023-02-17 18:14 ` Arthur Grillo
2023-02-23 14:38 ` Alex Deucher
2023-02-17 18:14 ` [PATCH v2 2/3] drm/amd/display: Remove unused local variables Arthur Grillo
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Arthur Grillo @ 2023-02-17 18:14 UTC (permalink / raw)
To: amd-gfx, dri-devel
Cc: sunpeng.li, tales.aparecida, Xinhui.Pan, Rodrigo.Siqueira,
Arthur Grillo, mairacanal, alexander.deucher, andrealmeid,
christian.koenig
Make implicit enum conversion to avoid -Wenum-conversion warning, such
as:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c:4109:88: warning: implicit conversion from ‘enum <anonymous>’ to ‘enum odm_combine_mode’ [-Wenum-conversion]
4109 | locals->ODMCombineEnablePerState[i][k] = true;
| ^
Signed-off-by: Arthur Grillo <arthurgrillo@riseup.net>
---
.../amd/display/dc/dml/dcn20/display_mode_vba_20.c | 9 +++++----
.../amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 11 ++++++-----
.../amd/display/dc/dml/dcn21/display_mode_vba_21.c | 12 ++++++------
3 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index d3b5b6fedf04..1b47249f01d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -26,6 +26,7 @@
#include "../display_mode_lib.h"
#include "display_mode_vba_20.h"
#include "../dml_inline_defs.h"
+#include "dml/display_mode_enums.h"
/*
* NOTE:
@@ -3897,14 +3898,14 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
- locals->ODMCombineEnablePerState[i][k] = false;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
if (mode_lib->vba.ODMCapability) {
if (locals->PlaneRequiredDISPCLKWithoutODMCombine > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
- locals->ODMCombineEnablePerState[i][k] = true;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
} else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
- locals->ODMCombineEnablePerState[i][k] = true;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
}
}
@@ -3957,7 +3958,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
locals->RequiredDISPCLK[i][j] = 0.0;
locals->DISPCLK_DPPCLK_Support[i][j] = true;
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
- locals->ODMCombineEnablePerState[i][k] = false;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
locals->NoOfDPP[i][j][k] = 1;
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index edd098c7eb92..4781bf82eec6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -26,6 +26,7 @@
#include "../display_mode_lib.h"
#include "display_mode_vba_20v2.h"
#include "../dml_inline_defs.h"
+#include "dml/display_mode_enums.h"
/*
* NOTE:
@@ -4008,17 +4009,17 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
- locals->ODMCombineEnablePerState[i][k] = false;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
if (mode_lib->vba.ODMCapability) {
if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) {
- locals->ODMCombineEnablePerState[i][k] = true;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
} else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN20_MAX_DSC_IMAGE_WIDTH)) {
- locals->ODMCombineEnablePerState[i][k] = true;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
} else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
- locals->ODMCombineEnablePerState[i][k] = true;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
}
}
@@ -4071,7 +4072,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
locals->RequiredDISPCLK[i][j] = 0.0;
locals->DISPCLK_DPPCLK_Support[i][j] = true;
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
- locals->ODMCombineEnablePerState[i][k] = false;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
locals->NoOfDPP[i][j][k] = 1;
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 1d84ae50311d..b7c2844d0cbe 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -4102,17 +4102,17 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
- locals->ODMCombineEnablePerState[i][k] = false;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
if (mode_lib->vba.ODMCapability) {
if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) {
- locals->ODMCombineEnablePerState[i][k] = true;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
} else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN21_MAX_DSC_IMAGE_WIDTH)) {
- locals->ODMCombineEnablePerState[i][k] = true;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
} else if (locals->HActive[k] > DCN21_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
- locals->ODMCombineEnablePerState[i][k] = true;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
}
}
@@ -4165,7 +4165,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
locals->RequiredDISPCLK[i][j] = 0.0;
locals->DISPCLK_DPPCLK_Support[i][j] = true;
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
- locals->ODMCombineEnablePerState[i][k] = false;
+ locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
locals->NoOfDPP[i][j][k] = 1;
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
@@ -5230,7 +5230,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
mode_lib->vba.ODMCombineEnabled[k] =
locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
} else {
- mode_lib->vba.ODMCombineEnabled[k] = false;
+ mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled;
}
mode_lib->vba.DSCEnabled[k] =
locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/3] drm/amd/display: Fix implicit enum conversion
2023-02-17 18:14 ` [PATCH v2 1/3] drm/amd/display: Fix implicit enum conversion Arthur Grillo
@ 2023-02-23 14:38 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2023-02-23 14:38 UTC (permalink / raw)
To: Arthur Grillo
Cc: sunpeng.li, tales.aparecida, Xinhui.Pan, Rodrigo.Siqueira,
dri-devel, mairacanal, amd-gfx, alexander.deucher, andrealmeid,
christian.koenig
This patch doesn't apply. Please make sure you are using drm-next or
linux-next.
Alex
On Fri, Feb 17, 2023 at 1:15 PM Arthur Grillo <arthurgrillo@riseup.net> wrote:
>
> Make implicit enum conversion to avoid -Wenum-conversion warning, such
> as:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c:4109:88: warning: implicit conversion from ‘enum <anonymous>’ to ‘enum odm_combine_mode’ [-Wenum-conversion]
> 4109 | locals->ODMCombineEnablePerState[i][k] = true;
> | ^
>
> Signed-off-by: Arthur Grillo <arthurgrillo@riseup.net>
> ---
> .../amd/display/dc/dml/dcn20/display_mode_vba_20.c | 9 +++++----
> .../amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 11 ++++++-----
> .../amd/display/dc/dml/dcn21/display_mode_vba_21.c | 12 ++++++------
> 3 files changed, 17 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> index d3b5b6fedf04..1b47249f01d8 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> @@ -26,6 +26,7 @@
> #include "../display_mode_lib.h"
> #include "display_mode_vba_20.h"
> #include "../dml_inline_defs.h"
> +#include "dml/display_mode_enums.h"
>
> /*
> * NOTE:
> @@ -3897,14 +3898,14 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
> * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
> if (mode_lib->vba.ODMCapability) {
> if (locals->PlaneRequiredDISPCLKWithoutODMCombine > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> } else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> }
> }
> @@ -3957,7 +3958,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> locals->RequiredDISPCLK[i][j] = 0.0;
> locals->DISPCLK_DPPCLK_Support[i][j] = true;
> for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
> locals->NoOfDPP[i][j][k] = 1;
> locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> index edd098c7eb92..4781bf82eec6 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> @@ -26,6 +26,7 @@
> #include "../display_mode_lib.h"
> #include "display_mode_vba_20v2.h"
> #include "../dml_inline_defs.h"
> +#include "dml/display_mode_enums.h"
>
> /*
> * NOTE:
> @@ -4008,17 +4009,17 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
> * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
> if (mode_lib->vba.ODMCapability) {
> if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> } else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN20_MAX_DSC_IMAGE_WIDTH)) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> } else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> }
> }
> @@ -4071,7 +4072,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
> locals->RequiredDISPCLK[i][j] = 0.0;
> locals->DISPCLK_DPPCLK_Support[i][j] = true;
> for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
> locals->NoOfDPP[i][j][k] = 1;
> locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> index 1d84ae50311d..b7c2844d0cbe 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> @@ -4102,17 +4102,17 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
> * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
> if (mode_lib->vba.ODMCapability) {
> if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> } else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN21_MAX_DSC_IMAGE_WIDTH)) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> } else if (locals->HActive[k] > DCN21_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> }
> }
> @@ -4165,7 +4165,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> locals->RequiredDISPCLK[i][j] = 0.0;
> locals->DISPCLK_DPPCLK_Support[i][j] = true;
> for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
> locals->NoOfDPP[i][j][k] = 1;
> locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
> @@ -5230,7 +5230,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> mode_lib->vba.ODMCombineEnabled[k] =
> locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
> } else {
> - mode_lib->vba.ODMCombineEnabled[k] = false;
> + mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled;
> }
> mode_lib->vba.DSCEnabled[k] =
> locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] drm/amd/display: Remove unused local variables
2023-02-17 18:14 [PATCH v2 0/3] Resolve warnings from AMDGPU Arthur Grillo
2023-02-17 18:14 ` [PATCH v2 1/3] drm/amd/display: Fix implicit enum conversion Arthur Grillo
@ 2023-02-17 18:14 ` Arthur Grillo
2023-02-23 14:37 ` Alex Deucher
2023-02-17 18:14 ` [PATCH v2 3/3] drm/amd/display: Remove unused local variables and function Arthur Grillo
2023-02-20 8:11 ` [PATCH v2 0/3] Resolve warnings from AMDGPU Christian König
3 siblings, 1 reply; 8+ messages in thread
From: Arthur Grillo @ 2023-02-17 18:14 UTC (permalink / raw)
To: amd-gfx, dri-devel
Cc: sunpeng.li, tales.aparecida, Xinhui.Pan, Rodrigo.Siqueira,
Arthur Grillo, mairacanal, alexander.deucher, andrealmeid,
christian.koenig
Remove local variables that were just set but were never used. This
decrease the number of -Wunused-but-set-variable warnings.
Signed-off-by: Arthur Grillo <arthurgrillo@riseup.net>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 3 +--
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c | 7 -------
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c | 2 --
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c | 2 --
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 4 ----
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 3 ---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 5 +----
.../gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 4 ----
.../drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c | 2 --
.../drm/amd/display/dc/link/protocols/link_dp_capability.c | 4 ----
10 files changed, 2 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index c4287147b853..ee08b545aaea 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -1219,7 +1219,6 @@ void dcn10_link_encoder_update_mst_stream_allocation_table(
const struct link_mst_stream_allocation_table *table)
{
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
- uint32_t value0 = 0;
uint32_t value1 = 0;
uint32_t value2 = 0;
uint32_t slots = 0;
@@ -1321,7 +1320,7 @@ void dcn10_link_encoder_update_mst_stream_allocation_table(
do {
udelay(10);
- value0 = REG_READ(DP_MSE_SAT_UPDATE);
+ REG_READ(DP_MSE_SAT_UPDATE);
REG_GET(DP_MSE_SAT_UPDATE,
DP_MSE_SAT_UPDATE, &value1);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
index f50ab961bc17..a7268027a472 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
@@ -185,13 +185,6 @@ static bool dpp201_get_optimal_number_of_taps(
struct scaler_data *scl_data,
const struct scaling_taps *in_taps)
{
- uint32_t pixel_width;
-
- if (scl_data->viewport.width > scl_data->recout.width)
- pixel_width = scl_data->recout.width;
- else
- pixel_width = scl_data->viewport.width;
-
if (scl_data->viewport.width != scl_data->h_active &&
scl_data->viewport.height != scl_data->v_active &&
dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
index 61bcfa03c4e7..1aeb04fbd89d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
@@ -541,8 +541,6 @@ void dcn201_pipe_control_lock(
bool lock)
{
struct dce_hwseq *hws = dc->hwseq;
- struct hubp *hubp = NULL;
- hubp = dc->res_pool->hubps[pipe->pipe_idx];
/* use TG master update lock to lock everything on the TG
* therefore only top pipe need to lock
*/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
index 95528e5ef89e..55e388c4c98b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
@@ -123,7 +123,6 @@ void afmt3_se_audio_setup(
{
struct dcn30_afmt *afmt3 = DCN30_AFMT_FROM_AFMT(afmt);
- uint32_t speakers = 0;
uint32_t channels = 0;
ASSERT(audio_info);
@@ -131,7 +130,6 @@ void afmt3_se_audio_setup(
if (audio_info == NULL)
return;
- speakers = audio_info->flags.info.ALLSPEAKERS;
channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
/* setup the audio stream source select (audio -> dig mapping) */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
index dc3e8df706b3..e46bbe7ddcc9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
@@ -47,13 +47,9 @@ void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
- PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
- // The format of default addr is 48:12 of the 48 bit addr
- mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
-
// The format of high/low are 48:18 of the 48 bit addr
mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 444f9fad3de6..1d848d14508b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -322,13 +322,10 @@ void dcn30_enable_writeback(
{
struct dwbc *dwb;
struct mcif_wb *mcif_wb;
- struct timing_generator *optc;
dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
- /* set the OPTC source mux */
- optc = dc->res_pool->timing_generators[dwb->otg_inst];
DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
__func__, wb_info->dwb_pipe_inst,\
wb_info->mpcc_inst);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 74e50c09bb62..e997bb98b43d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1611,7 +1611,6 @@ bool dcn32_acquire_post_bldn_3dlut(
struct dc_transfer_func **shaper)
{
bool ret = false;
- union dc_3dlut_state *state;
ASSERT(*lut == NULL && *shaper == NULL);
*lut = NULL;
@@ -1620,7 +1619,6 @@ bool dcn32_acquire_post_bldn_3dlut(
if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
*lut = pool->mpc_lut[mpcc_id];
*shaper = pool->mpc_shaper[mpcc_id];
- state = &pool->mpc_lut[mpcc_id]->state;
res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
ret = true;
}
@@ -1913,7 +1911,6 @@ int dcn32_populate_dml_pipes_from_context(
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe;
bool subvp_in_use = false;
- uint8_t is_pipe_split_expected[MAX_PIPES] = {0};
struct dc_crtc_timing *timing;
dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
@@ -2002,7 +1999,7 @@ int dcn32_populate_dml_pipes_from_context(
}
DC_FP_START();
- is_pipe_split_expected[i] = dcn32_predict_pipe_split(context, &pipes[pipe_cnt]);
+ dcn32_predict_pipe_split(context, &pipes[pipe_cnt]);
DC_FP_END();
pipe_cnt++;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 3a2d7bcc4b6d..a616cf078cf4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -59,25 +59,21 @@ uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(
{
struct hubp *hubp = pipe_ctx->plane_res.hubp;
uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
- uint32_t cursor_bpp = 4;
uint32_t cursor_mall_size_bytes = 0;
switch (pipe_ctx->stream->cursor_attributes.color_format) {
case CURSOR_MODE_MONO:
cursor_size /= 2;
- cursor_bpp = 4;
break;
case CURSOR_MODE_COLOR_1BIT_AND:
case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
cursor_size *= 4;
- cursor_bpp = 4;
break;
case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
cursor_size *= 8;
- cursor_bpp = 8;
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
index 35d10b4d018b..2244e4fb8c96 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
@@ -902,7 +902,6 @@ static void dml_rq_dlg_get_dlg_params(
double hratio_c;
double vratio_l;
double vratio_c;
- bool scl_enable;
unsigned int swath_width_ub_l;
unsigned int dpte_groups_per_row_ub_l;
@@ -1020,7 +1019,6 @@ static void dml_rq_dlg_get_dlg_params(
hratio_c = scl->hscl_ratio_c;
vratio_l = scl->vscl_ratio;
vratio_c = scl->vscl_ratio_c;
- scl_enable = scl->scl_enable;
swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub;
dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub;
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 138e5684c7fd..1c2ce08bdece 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -276,7 +276,6 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
int length)
{
int retry = 0;
- union dp_downstream_port_present ds_port = { 0 };
if (!link->dpcd_caps.dpcd_rev.raw) {
do {
@@ -289,9 +288,6 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
} while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
}
- ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
- DP_DPCD_REV];
-
if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
switch (link->dpcd_caps.branch_dev_id) {
/* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/3] drm/amd/display: Remove unused local variables
2023-02-17 18:14 ` [PATCH v2 2/3] drm/amd/display: Remove unused local variables Arthur Grillo
@ 2023-02-23 14:37 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2023-02-23 14:37 UTC (permalink / raw)
To: Arthur Grillo
Cc: sunpeng.li, tales.aparecida, Xinhui.Pan, Rodrigo.Siqueira,
dri-devel, mairacanal, amd-gfx, alexander.deucher, andrealmeid,
christian.koenig
Applied. Thanks.
On Fri, Feb 17, 2023 at 1:15 PM Arthur Grillo <arthurgrillo@riseup.net> wrote:
>
> Remove local variables that were just set but were never used. This
> decrease the number of -Wunused-but-set-variable warnings.
>
> Signed-off-by: Arthur Grillo <arthurgrillo@riseup.net>
> ---
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 3 +--
> drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c | 7 -------
> drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c | 2 --
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c | 2 --
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 4 ----
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 3 ---
> drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 5 +----
> .../gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 4 ----
> .../drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c | 2 --
> .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 4 ----
> 10 files changed, 2 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
> index c4287147b853..ee08b545aaea 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
> @@ -1219,7 +1219,6 @@ void dcn10_link_encoder_update_mst_stream_allocation_table(
> const struct link_mst_stream_allocation_table *table)
> {
> struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
> - uint32_t value0 = 0;
> uint32_t value1 = 0;
> uint32_t value2 = 0;
> uint32_t slots = 0;
> @@ -1321,7 +1320,7 @@ void dcn10_link_encoder_update_mst_stream_allocation_table(
> do {
> udelay(10);
>
> - value0 = REG_READ(DP_MSE_SAT_UPDATE);
> + REG_READ(DP_MSE_SAT_UPDATE);
>
> REG_GET(DP_MSE_SAT_UPDATE,
> DP_MSE_SAT_UPDATE, &value1);
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
> index f50ab961bc17..a7268027a472 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
> @@ -185,13 +185,6 @@ static bool dpp201_get_optimal_number_of_taps(
> struct scaler_data *scl_data,
> const struct scaling_taps *in_taps)
> {
> - uint32_t pixel_width;
> -
> - if (scl_data->viewport.width > scl_data->recout.width)
> - pixel_width = scl_data->recout.width;
> - else
> - pixel_width = scl_data->viewport.width;
> -
> if (scl_data->viewport.width != scl_data->h_active &&
> scl_data->viewport.height != scl_data->v_active &&
> dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> index 61bcfa03c4e7..1aeb04fbd89d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> @@ -541,8 +541,6 @@ void dcn201_pipe_control_lock(
> bool lock)
> {
> struct dce_hwseq *hws = dc->hwseq;
> - struct hubp *hubp = NULL;
> - hubp = dc->res_pool->hubps[pipe->pipe_idx];
> /* use TG master update lock to lock everything on the TG
> * therefore only top pipe need to lock
> */
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
> index 95528e5ef89e..55e388c4c98b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
> @@ -123,7 +123,6 @@ void afmt3_se_audio_setup(
> {
> struct dcn30_afmt *afmt3 = DCN30_AFMT_FROM_AFMT(afmt);
>
> - uint32_t speakers = 0;
> uint32_t channels = 0;
>
> ASSERT(audio_info);
> @@ -131,7 +130,6 @@ void afmt3_se_audio_setup(
> if (audio_info == NULL)
> return;
>
> - speakers = audio_info->flags.info.ALLSPEAKERS;
> channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
>
> /* setup the audio stream source select (audio -> dig mapping) */
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
> index dc3e8df706b3..e46bbe7ddcc9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
> @@ -47,13 +47,9 @@ void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
> {
> struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>
> - PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
> PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
> PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
>
> - // The format of default addr is 48:12 of the 48 bit addr
> - mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
> -
> // The format of high/low are 48:18 of the 48 bit addr
> mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
> mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index 444f9fad3de6..1d848d14508b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -322,13 +322,10 @@ void dcn30_enable_writeback(
> {
> struct dwbc *dwb;
> struct mcif_wb *mcif_wb;
> - struct timing_generator *optc;
>
> dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
> mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
>
> - /* set the OPTC source mux */
> - optc = dc->res_pool->timing_generators[dwb->otg_inst];
> DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
> __func__, wb_info->dwb_pipe_inst,\
> wb_info->mpcc_inst);
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
> index 74e50c09bb62..e997bb98b43d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
> @@ -1611,7 +1611,6 @@ bool dcn32_acquire_post_bldn_3dlut(
> struct dc_transfer_func **shaper)
> {
> bool ret = false;
> - union dc_3dlut_state *state;
>
> ASSERT(*lut == NULL && *shaper == NULL);
> *lut = NULL;
> @@ -1620,7 +1619,6 @@ bool dcn32_acquire_post_bldn_3dlut(
> if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
> *lut = pool->mpc_lut[mpcc_id];
> *shaper = pool->mpc_shaper[mpcc_id];
> - state = &pool->mpc_lut[mpcc_id]->state;
> res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
> ret = true;
> }
> @@ -1913,7 +1911,6 @@ int dcn32_populate_dml_pipes_from_context(
> struct resource_context *res_ctx = &context->res_ctx;
> struct pipe_ctx *pipe;
> bool subvp_in_use = false;
> - uint8_t is_pipe_split_expected[MAX_PIPES] = {0};
> struct dc_crtc_timing *timing;
>
> dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
> @@ -2002,7 +1999,7 @@ int dcn32_populate_dml_pipes_from_context(
> }
>
> DC_FP_START();
> - is_pipe_split_expected[i] = dcn32_predict_pipe_split(context, &pipes[pipe_cnt]);
> + dcn32_predict_pipe_split(context, &pipes[pipe_cnt]);
> DC_FP_END();
>
> pipe_cnt++;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
> index 3a2d7bcc4b6d..a616cf078cf4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
> @@ -59,25 +59,21 @@ uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(
> {
> struct hubp *hubp = pipe_ctx->plane_res.hubp;
> uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
> - uint32_t cursor_bpp = 4;
> uint32_t cursor_mall_size_bytes = 0;
>
> switch (pipe_ctx->stream->cursor_attributes.color_format) {
> case CURSOR_MODE_MONO:
> cursor_size /= 2;
> - cursor_bpp = 4;
> break;
> case CURSOR_MODE_COLOR_1BIT_AND:
> case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
> case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
> cursor_size *= 4;
> - cursor_bpp = 4;
> break;
>
> case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
> case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
> cursor_size *= 8;
> - cursor_bpp = 8;
> break;
> }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> index 35d10b4d018b..2244e4fb8c96 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> @@ -902,7 +902,6 @@ static void dml_rq_dlg_get_dlg_params(
> double hratio_c;
> double vratio_l;
> double vratio_c;
> - bool scl_enable;
>
> unsigned int swath_width_ub_l;
> unsigned int dpte_groups_per_row_ub_l;
> @@ -1020,7 +1019,6 @@ static void dml_rq_dlg_get_dlg_params(
> hratio_c = scl->hscl_ratio_c;
> vratio_l = scl->vscl_ratio;
> vratio_c = scl->vscl_ratio_c;
> - scl_enable = scl->scl_enable;
>
> swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub;
> dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub;
> diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> index 138e5684c7fd..1c2ce08bdece 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> @@ -276,7 +276,6 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
> int length)
> {
> int retry = 0;
> - union dp_downstream_port_present ds_port = { 0 };
>
> if (!link->dpcd_caps.dpcd_rev.raw) {
> do {
> @@ -289,9 +288,6 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
> } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
> }
>
> - ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
> - DP_DPCD_REV];
> -
> if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
> switch (link->dpcd_caps.branch_dev_id) {
> /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] drm/amd/display: Remove unused local variables and function
2023-02-17 18:14 [PATCH v2 0/3] Resolve warnings from AMDGPU Arthur Grillo
2023-02-17 18:14 ` [PATCH v2 1/3] drm/amd/display: Fix implicit enum conversion Arthur Grillo
2023-02-17 18:14 ` [PATCH v2 2/3] drm/amd/display: Remove unused local variables Arthur Grillo
@ 2023-02-17 18:14 ` Arthur Grillo
2023-02-23 14:37 ` Alex Deucher
2023-02-20 8:11 ` [PATCH v2 0/3] Resolve warnings from AMDGPU Christian König
3 siblings, 1 reply; 8+ messages in thread
From: Arthur Grillo @ 2023-02-17 18:14 UTC (permalink / raw)
To: amd-gfx, dri-devel
Cc: sunpeng.li, tales.aparecida, Xinhui.Pan, Rodrigo.Siqueira,
Arthur Grillo, mairacanal, alexander.deucher, andrealmeid,
christian.koenig
Remove a couple of local variables that are only set but never used,
also remove an static utility function that is never used in consequence
of the variable removal.
This decrease the number of -Wunused-but-set-variable warnings.
Signed-off-by: Arthur Grillo <arthurgrillo@riseup.net>
---
.../gpu/drm/amd/display/dc/dcn31/dcn31_apg.c | 41 -------------------
1 file changed, 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
index 24e9ff65434d..05aac3e444b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
@@ -72,40 +72,6 @@ static void apg31_disable(
REG_UPDATE(APG_CONTROL2, APG_ENABLE, 0);
}
-static union audio_cea_channels speakers_to_channels(
- struct audio_speaker_flags speaker_flags)
-{
- union audio_cea_channels cea_channels = {0};
-
- /* these are one to one */
- cea_channels.channels.FL = speaker_flags.FL_FR;
- cea_channels.channels.FR = speaker_flags.FL_FR;
- cea_channels.channels.LFE = speaker_flags.LFE;
- cea_channels.channels.FC = speaker_flags.FC;
-
- /* if Rear Left and Right exist move RC speaker to channel 7
- * otherwise to channel 5
- */
- if (speaker_flags.RL_RR) {
- cea_channels.channels.RL_RC = speaker_flags.RL_RR;
- cea_channels.channels.RR = speaker_flags.RL_RR;
- cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
- } else {
- cea_channels.channels.RL_RC = speaker_flags.RC;
- }
-
- /* FRONT Left Right Center and REAR Left Right Center are exclusive */
- if (speaker_flags.FLC_FRC) {
- cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
- cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
- } else {
- cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
- cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
- }
-
- return cea_channels;
-}
-
static void apg31_se_audio_setup(
struct apg *apg,
unsigned int az_inst,
@@ -113,24 +79,17 @@ static void apg31_se_audio_setup(
{
struct dcn31_apg *apg31 = DCN31_APG_FROM_APG(apg);
- uint32_t speakers = 0;
- uint32_t channels = 0;
-
ASSERT(audio_info);
/* This should not happen.it does so we don't get BSOD*/
if (audio_info == NULL)
return;
- speakers = audio_info->flags.info.ALLSPEAKERS;
- channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
-
/* DisplayPort only allows for one audio stream with stream ID 0 */
REG_UPDATE(APG_CONTROL2, APG_DP_AUDIO_STREAM_ID, 0);
/* When running in "pair mode", pairs of audio channels have their own enable
* this is for really old audio drivers */
REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xFF);
- // REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, channels);
/* Disable forced mem power off */
REG_UPDATE(APG_MEM_PWR, APG_MEM_PWR_FORCE, 0);
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/3] drm/amd/display: Remove unused local variables and function
2023-02-17 18:14 ` [PATCH v2 3/3] drm/amd/display: Remove unused local variables and function Arthur Grillo
@ 2023-02-23 14:37 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2023-02-23 14:37 UTC (permalink / raw)
To: Arthur Grillo
Cc: sunpeng.li, tales.aparecida, Xinhui.Pan, Rodrigo.Siqueira,
dri-devel, mairacanal, amd-gfx, alexander.deucher, andrealmeid,
christian.koenig
Applied. Thanks.
On Fri, Feb 17, 2023 at 1:15 PM Arthur Grillo <arthurgrillo@riseup.net> wrote:
>
> Remove a couple of local variables that are only set but never used,
> also remove an static utility function that is never used in consequence
> of the variable removal.
>
> This decrease the number of -Wunused-but-set-variable warnings.
>
> Signed-off-by: Arthur Grillo <arthurgrillo@riseup.net>
> ---
> .../gpu/drm/amd/display/dc/dcn31/dcn31_apg.c | 41 -------------------
> 1 file changed, 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
> index 24e9ff65434d..05aac3e444b4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
> @@ -72,40 +72,6 @@ static void apg31_disable(
> REG_UPDATE(APG_CONTROL2, APG_ENABLE, 0);
> }
>
> -static union audio_cea_channels speakers_to_channels(
> - struct audio_speaker_flags speaker_flags)
> -{
> - union audio_cea_channels cea_channels = {0};
> -
> - /* these are one to one */
> - cea_channels.channels.FL = speaker_flags.FL_FR;
> - cea_channels.channels.FR = speaker_flags.FL_FR;
> - cea_channels.channels.LFE = speaker_flags.LFE;
> - cea_channels.channels.FC = speaker_flags.FC;
> -
> - /* if Rear Left and Right exist move RC speaker to channel 7
> - * otherwise to channel 5
> - */
> - if (speaker_flags.RL_RR) {
> - cea_channels.channels.RL_RC = speaker_flags.RL_RR;
> - cea_channels.channels.RR = speaker_flags.RL_RR;
> - cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
> - } else {
> - cea_channels.channels.RL_RC = speaker_flags.RC;
> - }
> -
> - /* FRONT Left Right Center and REAR Left Right Center are exclusive */
> - if (speaker_flags.FLC_FRC) {
> - cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
> - cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
> - } else {
> - cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
> - cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
> - }
> -
> - return cea_channels;
> -}
> -
> static void apg31_se_audio_setup(
> struct apg *apg,
> unsigned int az_inst,
> @@ -113,24 +79,17 @@ static void apg31_se_audio_setup(
> {
> struct dcn31_apg *apg31 = DCN31_APG_FROM_APG(apg);
>
> - uint32_t speakers = 0;
> - uint32_t channels = 0;
> -
> ASSERT(audio_info);
> /* This should not happen.it does so we don't get BSOD*/
> if (audio_info == NULL)
> return;
>
> - speakers = audio_info->flags.info.ALLSPEAKERS;
> - channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
> -
> /* DisplayPort only allows for one audio stream with stream ID 0 */
> REG_UPDATE(APG_CONTROL2, APG_DP_AUDIO_STREAM_ID, 0);
>
> /* When running in "pair mode", pairs of audio channels have their own enable
> * this is for really old audio drivers */
> REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xFF);
> - // REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, channels);
>
> /* Disable forced mem power off */
> REG_UPDATE(APG_MEM_PWR, APG_MEM_PWR_FORCE, 0);
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/3] Resolve warnings from AMDGPU
2023-02-17 18:14 [PATCH v2 0/3] Resolve warnings from AMDGPU Arthur Grillo
` (2 preceding siblings ...)
2023-02-17 18:14 ` [PATCH v2 3/3] drm/amd/display: Remove unused local variables and function Arthur Grillo
@ 2023-02-20 8:11 ` Christian König
3 siblings, 0 replies; 8+ messages in thread
From: Christian König @ 2023-02-20 8:11 UTC (permalink / raw)
To: Arthur Grillo, amd-gfx, dri-devel
Cc: sunpeng.li, tales.aparecida, Xinhui.Pan, Rodrigo.Siqueira,
mairacanal, alexander.deucher, andrealmeid
Acked-by: Christian König <christian.koenig@amd.com> for the whole series.
Am 17.02.23 um 19:14 schrieb Arthur Grillo:
> Hi,
>
> This series resolve some of the warnings that appear when compiling AMDGPU
> with W=1.
>
> Each patch is focused in a specific warning.
>
> This is my First Patch for the GSoC Project Idea about increasing code
> coverage of the DRM code[1].
>
> Thanks for reviewing!
>
> Best regards,
> Arthur Grillo
>
> [1]: https://www.x.org/wiki/DRMcoverage2023/#firstpatch
>
> ---
>
> v1 -> v2: https://lore.kernel.org/all/20230213204923.111948-1-arthurgrillo@riseup.net/
>
> - Use dm_odm_combine_mode_disabled dm_odm_combine_mode_2to1 instead of an enum casting
> - Maintain register read
>
> ---
>
> Arthur Grillo (3):
> drm/amd/display: Fix implicit enum conversion
> drm/amd/display: Remove unused local variables
> drm/amd/display: Remove unused local variables and function
>
> .../amd/display/dc/dcn10/dcn10_link_encoder.c | 3 +-
> .../drm/amd/display/dc/dcn201/dcn201_dpp.c | 7 ----
> .../drm/amd/display/dc/dcn201/dcn201_hwseq.c | 2 -
> .../gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c | 2 -
> .../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 4 --
> .../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 3 --
> .../gpu/drm/amd/display/dc/dcn31/dcn31_apg.c | 41 -------------------
> .../drm/amd/display/dc/dcn32/dcn32_resource.c | 5 +--
> .../display/dc/dcn32/dcn32_resource_helpers.c | 4 --
> .../dc/dml/dcn20/display_mode_vba_20.c | 9 ++--
> .../dc/dml/dcn20/display_mode_vba_20v2.c | 11 ++---
> .../dc/dml/dcn21/display_mode_vba_21.c | 12 +++---
> .../dc/dml/dcn31/display_rq_dlg_calc_31.c | 2 -
> .../dc/link/protocols/link_dp_capability.c | 4 --
> 14 files changed, 19 insertions(+), 90 deletions(-)
>
^ permalink raw reply [flat|nested] 8+ messages in thread