From: Grigori Goronzy <greg@chown.ath.cx>
To: "Michel Dänzer" <michel@daenzer.net>,
dri-devel@lists.freedesktop.org, mesa-dev@lists.freedesktop.org
Subject: Re: [PATCH 4/5] r600g, radeonsi: Use write-combined persistent GTT mappings
Date: Thu, 17 Jul 2014 12:56:58 +0200 [thread overview]
Message-ID: <53C7ABFA.6090804@chown.ath.cx> (raw)
In-Reply-To: <1405591275-14461-10-git-send-email-michel@daenzer.net>
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On 17.07.2014 12:01, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daenzer@amd.com>
>
> This is hopefully safe: The kernel makes sure writes to these mappings
> finish before the GPU might start reading from them, and the GPU caches
> are invalidated at the start of a command stream.
>
Aren't CPU reads from write-combined GTT memory extraordinarily slow,
because they're uncached? And don't you need the right access patterns
to make write combining perform well?
Grigori
> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
> ---
> src/gallium/drivers/radeon/r600_buffer_common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
> index 40917f0..c8a0723 100644
> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
> @@ -131,7 +131,7 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
> res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
> PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
> res->domains = RADEON_DOMAIN_GTT;
> - flags = 0;
> + flags = RADEON_FLAG_GTT_WC;
> }
>
> /* Tiled textures are unmappable. Always put them in VRAM. */
>
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next prev parent reply other threads:[~2014-07-17 10:56 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-17 10:01 [PATCH 0/5] radeon: Write-combined CPU mappings of BOs in GTT Michel Dänzer
2014-07-17 10:01 ` [PATCH 1/5] drm/radeon: Remove radeon_gart_restore() Michel Dänzer
2014-07-17 10:01 ` [PATCH 2/5] drm/radeon: Pass GART page flags to radeon_gart_set_page() explicitly Michel Dänzer
2014-07-17 10:01 ` [PATCH 3/5] drm/radeon: Allow write-combined CPU mappings of BOs in GTT Michel Dänzer
2014-07-17 10:01 ` [PATCH 4/5] drm/radeon: Use write-combined CPU mappings of rings and IBs on >= SI Michel Dänzer
2014-07-17 10:01 ` [PATCH 5/5] drm/radeon: Use VRAM for indirect buffers " Michel Dänzer
2014-07-17 10:01 ` [PATCH 1/5] winsys/radeon: Use separate caching buffer managers for VRAM and GTT Michel Dänzer
2014-07-17 10:01 ` [PATCH 2/5] r600g/radeonsi: Use write-combined CPU mappings of some BOs in GTT Michel Dänzer
2014-07-17 10:01 ` [PATCH 3/5] r600g/radeonsi: Prefer VRAM for CPU -> GPU streaming buffers Michel Dänzer
2014-07-17 10:01 ` [PATCH 4/5] r600g, radeonsi: Use write-combined persistent GTT mappings Michel Dänzer
2014-07-17 10:56 ` Grigori Goronzy [this message]
2014-07-17 12:00 ` Marek Olšák
2014-07-18 3:19 ` [Mesa-dev] " Michel Dänzer
2014-07-18 11:45 ` Marek Olšák
2014-07-18 19:50 ` [Mesa-dev] " Grigori Goronzy
2014-07-18 20:52 ` Marek Olšák
2014-07-23 6:32 ` Michel Dänzer
2014-07-23 11:52 ` Marek Olšák
2014-07-18 20:55 ` Marek Olšák
2014-07-17 10:01 ` [PATCH 5/5] r600g, radeonsi: Prefer VRAM for persistent mappings Michel Dänzer
2014-07-17 12:17 ` Marek Olšák
2014-07-17 10:09 ` [PATCH 0/5] radeon: Write-combined CPU mappings of BOs in GTT Christian König
2014-07-18 3:07 ` Michel Dänzer
2014-07-18 3:58 ` Dieter Nützel
2014-07-18 9:52 ` Michel Dänzer
2014-07-18 15:47 ` Christian König
2014-07-18 17:47 ` Marek Olšák
2014-07-18 22:03 ` Marek Olšák
2014-07-19 1:15 ` Michel Dänzer
2014-07-21 8:07 ` Christian König
2014-07-23 3:54 ` Michel Dänzer
2014-07-23 6:42 ` Christian König
2014-07-23 7:21 ` Michel Dänzer
2014-07-23 7:32 ` Christian König
2014-07-23 12:07 ` Marek Olšák
2014-07-23 13:59 ` Alex Deucher
2014-07-17 12:25 ` Marek Olšák
2014-07-17 13:35 ` Alex Deucher
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