From: "Michel Dänzer" <michel@daenzer.net>
To: "Alex Deucher" <alexdeucher@gmail.com>,
"Christian König" <deathsimple@vodafone.de>
Cc: Maling list - DRI developers <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH] drm/radeon: Sync ME and PFP after CP semaphore waits v2
Date: Tue, 19 Aug 2014 14:57:11 +0900 [thread overview]
Message-ID: <53F2E737.4020907@daenzer.net> (raw)
In-Reply-To: <CADnq5_PuoRLjZb2Tc-3VuCw+wns50E+0THcay75JoGyDpgxziw@mail.gmail.com>
On 19.08.2014 00:02, Alex Deucher wrote:
> On Mon, Aug 18, 2014 at 10:30 AM, Christian König
> <deathsimple@vodafone.de> wrote:
>> From: Christian König <christian.koenig@amd.com>
>>
>> Fixes lockups due to CP read GPUVM faults when running piglit on Cape
>> Verde.
>>
>> v2 (chk): apply the fix to R600+ as well, on CIK only the GFX CP has
>> a PFP, add more comments to R600 code, enable flushing again
>>
>> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>
> I just checked the ucode. This packet only exists on 7xx and newer.
> How about the attached change?
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Just survived 10 piglit runs in a row on my Cape Verde. :)
>> diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
>> index f94e7a9..1272c0d 100644
>> --- a/drivers/gpu/drm/radeon/r600d.h
>> +++ b/drivers/gpu/drm/radeon/r600d.h
>> @@ -1597,6 +1597,7 @@
>> */
>> # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
>> # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
>> +#define PACKET3_PFP_SYNC_ME 0x42
>> #define PACKET3_SURFACE_SYNC 0x43
>> # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
>> # define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */
The indentation doesn't seem to line up.
>> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
>> index 058f200..9c8358f 100644
>> --- a/drivers/gpu/drm/radeon/radeon_vm.c
>> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
>> @@ -238,9 +238,7 @@ void radeon_vm_flush(struct radeon_device *rdev,
>> uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
>>
>> /* if we can't remember our last VM flush then flush now! */
>> - /* XXX figure out why we have to flush all the time before CIK */
>> - if (rdev->family < CHIP_BONAIRE ||
>> - !vm->last_flush || pd_addr != vm->pd_gpu_addr) {
>> + if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
>> trace_radeon_vm_flush(pd_addr, ring, vm->id);
>> vm->pd_gpu_addr = pd_addr;
>> radeon_ring_vm_flush(rdev, ring, vm);
Might be better for this to be in a separate change.
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
next prev parent reply other threads:[~2014-08-19 5:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-18 14:30 [PATCH] drm/radeon: Sync ME and PFP after CP semaphore waits v2 Christian König
2014-08-18 15:02 ` Alex Deucher
2014-08-18 15:14 ` Christian König
2014-08-19 5:57 ` Michel Dänzer [this message]
2014-08-19 16:03 ` Alex Deucher
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