[PATCH 0/8] Enable DP2.1 alpm

[PATCH 0/8] Enable DP2.1 alpm

[Animesh Manna]

ALPM support added on DP2.1 and xe3p will support DP2.1 alpm.
This patch series extending alpm supoort for DP2.1.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (8):
  drm/i915/alpm: Add dpcd definition for DP2.1 alpm capability
  drm/i915/alpm: alpm_init() for DP2.1
  drm/i915/alpm: Replace is_edp() with alpm_is_possible()
  drm/i915/alpm: Enable debugfs for DP2.1
  drm/i915/alpm: Auxless wake time calculation for Xe3p
  drm/i915/alpm: Half LFPS cycle calculation
  drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf
  drm/i915/alpm: Program lttpr count for DP 2.1 alpm

 drivers/gpu/drm/i915/display/intel_alpm.c     | 141 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_alpm.h     |   1 +
 .../drm/i915/display/intel_display_types.h    |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   6 +-
 .../drm/i915/display/intel_dp_link_training.c |  12 ++
 drivers/gpu/drm/i915/display/intel_psr.c      |  23 ++-
 drivers/gpu/drm/i915/display/intel_psr.h      |   1 -
 include/drm/display/drm_dp.h                  |   4 +-
 8 files changed, 145 insertions(+), 45 deletions(-)

-- 
2.29.0

[PATCH 1/8] drm/i915/alpm: Add dpcd definition for DP2.1 alpm capability

[Animesh Manna]

Add required dpcd address which will be needed to enable DP2.1 alpm.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 include/drm/display/drm_dp.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e4eebabab975..b4bacbcf130e 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1512,6 +1512,8 @@
 /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
 #define DP_PHY_REPEATER_128B132B_RATES			    0xf0007 /* 2.0 */
 #define DP_PHY_REPEATER_EQ_DONE                             0xf0008 /* 2.0 E11 */
+#define DP_LTTPR_ALPM_CAPABILITIES                          0xf0009 /* 2.1 */
+#define DP_TOTAL_LTTPR_CNT                                  0xf000a /* 2.1 */
 
 enum drm_dp_phy {
 	DP_PHY_DPRX,
@@ -1691,7 +1693,7 @@ enum drm_dp_phy {
 #define DP_DSC_BRANCH_CAP_SIZE		3
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
 #define EDP_DISPLAY_CTL_CAP_SIZE	5
-#define DP_LTTPR_COMMON_CAP_SIZE	8
+#define DP_LTTPR_COMMON_CAP_SIZE	10
 #define DP_LTTPR_PHY_CAP_SIZE		3
 
 #define DP_SDP_AUDIO_TIMESTAMP		0x01
-- 
2.29.0

[PATCH 2/8] drm/i915/alpm: alpm_init() for DP2.1

[Animesh Manna]

Initialize mutex for DP2.1 alpm.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 475518b4048b..3f9cbeb215ed 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6073,8 +6073,12 @@ intel_dp_detect(struct drm_connector *_connector,
 	if (ret == 1)
 		connector->base.epoch_counter++;
 
-	if (!intel_dp_is_edp(intel_dp))
+	if (!intel_dp_is_edp(intel_dp)) {
+		if (DISPLAY_VER(display) >= 35)
+			intel_alpm_init(intel_dp);
+
 		intel_psr_init_dpcd(intel_dp);
+	}
 
 	intel_dp_detect_dsc_caps(intel_dp, connector);
 
-- 
2.29.0

[PATCH 3/8] drm/i915/alpm: Replace is_edp() with alpm_is_possible()

[Animesh Manna]

Add a separate alpm_is_possible() which will check for both edp and dp.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 16 +++++++++++++---
 drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 6372f533f65b..973791f8956c 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -41,6 +41,16 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
 }
 
+bool intel_alpm_is_possible(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	return (DISPLAY_VER(display) >= 12 && intel_dp->alpm_dpcd) ||
+	       (DISPLAY_VER(display) >= 35 &&
+		intel_dp->lttpr_common_caps[DP_LTTPR_ALPM_CAPABILITIES -
+					    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]);
+}
+
 void intel_alpm_init(struct intel_dp *intel_dp)
 {
 	u8 dpcd;
@@ -265,7 +275,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp->alpm.sink_alpm_error)
 		return;
 
-	if (!intel_dp_is_edp(intel_dp))
+	if (!intel_alpm_is_possible(intel_dp))
 		return;
 
 	if (DISPLAY_VER(display) < 20)
@@ -416,7 +426,7 @@ void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
 
 		intel_dp = enc_to_intel_dp(encoder);
 
-		if (!intel_dp_is_edp(intel_dp))
+		if (!intel_alpm_is_possible(intel_dp))
 			continue;
 
 		if (old_crtc_state->has_lobf) {
@@ -468,7 +478,7 @@ void intel_alpm_post_plane_update(struct intel_atomic_state *state,
 
 		intel_dp = enc_to_intel_dp(encoder);
 
-		if (intel_dp_is_edp(intel_dp)) {
+		if (intel_alpm_is_possible(intel_dp)) {
 			intel_alpm_enable_sink(intel_dp, crtc_state);
 			intel_alpm_configure(intel_dp, crtc_state);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 53599b464dea..0c9972faa2e0 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -15,6 +15,7 @@ struct intel_connector;
 struct intel_atomic_state;
 struct intel_crtc;
 
+bool intel_alpm_is_possible(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
-- 
2.29.0

[PATCH 4/8] drm/i915/alpm: Enable debugfs for DP2.1

[Animesh Manna]

Enable AlPM debug info through lobf debug info.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 973791f8956c..0f6b15bca3be 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -552,9 +552,15 @@ void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
 	struct intel_display *display = to_intel_display(connector);
 	struct dentry *root = connector->base.debugfs_entry;
 
-	if (DISPLAY_VER(display) < 20 ||
-	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
+	if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+		if (DISPLAY_VER(display) < 35)
+			return;
+	} else if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
+		if (DISPLAY_VER(display) < 20)
+			return;
+	} else {
 		return;
+	}
 
 	debugfs_create_file("i915_edp_lobf_debug", 0644, root,
 			    connector, &i915_edp_lobf_debug_fops);
-- 
2.29.0

[PATCH 5/8] drm/i915/alpm: Auxless wake time calculation for Xe3p

[Animesh Manna]

Add support for auxless waketime calculation for DP2.1 ALPM
as dependent parameter got changed.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 78 +++++++++++++++++++----
 1 file changed, 67 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 0f6b15bca3be..ee5b1e3d79d2 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -96,6 +96,66 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 		1000 / (2 * LFPS_CYCLE_COUNT);
 }
 
+static int get_tphy2_p2_to_p0(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	return DISPLAY_VER(display) >= 35 ? (40 * 1000) : (12 * 1000);
+}
+
+static int get_establishment_period(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state)
+{
+	int port_clock = crtc_state->port_clock;
+	int t1 = 50 * 1000;
+	int tps4 = (port_clock >= 1000000) ? (396 * 32) : (252 * 10);
+	int tml_phy_lock = 1000 * 1000 * tps4 / port_clock / 10;
+	int lttpr_count = 0;
+	int establishment_period;
+	int tcds;
+
+	if (!intel_dp_is_edp(intel_dp)) {
+		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+		tcds = 7 * tml_phy_lock;
+	} else {
+		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
+	}
+
+	if (lttpr_count) {
+		int tlw = 13000;
+		int tcs = 10000;
+		int tlfps_period = get_lfps_cycle_time(crtc_state);
+		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
+			    (lttpr_count - 1) * (tlw + tlfps_period));
+		int tacds = 70000;
+		int tds = (lttpr_count - 1) * 7 * tml_phy_lock;
+
+		/* tdrl is same as tcds*/
+		establishment_period = tlw + tlfps_period + tdcs + tacds + tds + tcds;
+	} else {
+		/* TODO: Add a check for data realign by DPCD 0x116[3] */
+
+		establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+	}
+
+	return establishment_period;
+}
+
+static int get_switch_to_active(int port_clock)
+{
+	int switch_to_active;
+
+	if (port_clock >= 1000000) {
+		int symbol_clock = port_clock / intel_dp_link_symbol_size(port_clock);
+
+		switch_to_active = 32 * DIV_ROUND_UP((396 + 3 + 64), symbol_clock);
+	} else {
+		switch_to_active = 0;
+	}
+
+	return switch_to_active;
+}
+
 /*
  * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
  * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -115,19 +175,15 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
  * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
  * TPS4 Length = 252 Symbols
  */
-static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
+static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state)
 {
-	int tphy2_p2_to_p0 = 12 * 1000;
-	int t1 = 50 * 1000;
-	int tps4 = 252;
-	/* port_clock is link rate in 10kbit/s units */
-	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
-	int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
-	int t2 = num_ml_phy_lock * tml_phy_lock;
-	int tcds = 1 * t2;
+	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(intel_dp);
+	int establishment_period = get_establishment_period(intel_dp, crtc_state);
+	int switch_to_active = get_switch_to_active(crtc_state->port_clock);
 
 	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
-			    SILENCE_PERIOD_TIME + t1 + tcds, 1000);
+			    establishment_period + switch_to_active, 1000);
 }
 
 static int
@@ -139,7 +195,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 		lfps_half_cycle;
 
 	aux_less_wake_time =
-		_lnl_compute_aux_less_wake_time(crtc_state);
+		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
 	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
 						       aux_less_wake_time);
 	silence_period = get_silence_period_symbols(crtc_state);
-- 
2.29.0

[PATCH 6/8] drm/i915/alpm: Half LFPS cycle calculation

[Animesh Manna]

Add support for half LFPS cycle calculation for DP2.1 ALPM as dependent
parameters got changed.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 32 ++++++++++++++++-------
 1 file changed, 22 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index ee5b1e3d79d2..f7803088f916 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -68,31 +68,43 @@ static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
 		1000 / 1000;
 }
 
-static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
+static void get_lfps_cycle_min_max_time(struct intel_dp *intel_dp,
+					const struct intel_crtc_state *crtc_state,
 					int *min, int *max)
 {
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	if (!intel_dp_is_edp(intel_dp)) {
+		*min = 320;
+		*max = 1600;
+		return;
+	}
+
 	if (crtc_state->port_clock < 540000) {
-		*min = 65 * LFPS_CYCLE_COUNT;
-		*max = 75 * LFPS_CYCLE_COUNT;
+		*min = DISPLAY_VER(display) < 35 ? 65 * LFPS_CYCLE_COUNT : 140;
+		*max = DISPLAY_VER(display) < 35 ? 75 * LFPS_CYCLE_COUNT : 800;
 	} else {
 		*min = 140;
 		*max = 800;
 	}
 }
 
-static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
+static int get_lfps_cycle_time(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
 {
 	int tlfps_cycle_min, tlfps_cycle_max;
 
-	get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
+	get_lfps_cycle_min_max_time(intel_dp, crtc_state, &tlfps_cycle_min,
 				    &tlfps_cycle_max);
 
 	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
 }
 
-static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
+static int get_lfps_half_cycle_clocks(struct intel_dp *intel_dp,
+				      const struct intel_crtc_state *crtc_state)
 {
-	return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 /
+	return get_lfps_cycle_time(intel_dp, crtc_state) *
+		crtc_state->port_clock / 1000 /
 		1000 / (2 * LFPS_CYCLE_COUNT);
 }
 
@@ -124,7 +136,7 @@ static int get_establishment_period(struct intel_dp *intel_dp,
 	if (lttpr_count) {
 		int tlw = 13000;
 		int tcs = 10000;
-		int tlfps_period = get_lfps_cycle_time(crtc_state);
+		int tlfps_period = get_lfps_cycle_time(intel_dp, crtc_state);
 		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
 			    (lttpr_count - 1) * (tlw + tlfps_period));
 		int tacds = 70000;
@@ -182,7 +194,7 @@ static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
 	int establishment_period = get_establishment_period(intel_dp, crtc_state);
 	int switch_to_active = get_switch_to_active(crtc_state->port_clock);
 
-	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
+	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(intel_dp, crtc_state) +
 			    establishment_period + switch_to_active, 1000);
 }
 
@@ -200,7 +212,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 						       aux_less_wake_time);
 	silence_period = get_silence_period_symbols(crtc_state);
 
-	lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);
+	lfps_half_cycle = get_lfps_half_cycle_clocks(intel_dp, crtc_state);
 
 	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
 	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
-- 
2.29.0

[PATCH 7/8] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[Animesh Manna]

For DP2.1, ALPM is optional and there can be scenario where panel replay
will be supported without ALPM. So decouple ALPM feaure by has_alpm flag
from related display features.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     |  7 +++---
 .../drm/i915/display/intel_display_types.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_psr.c      | 23 ++++++++-----------
 drivers/gpu/drm/i915/display/intel_psr.h      |  1 -
 4 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index f7803088f916..96966d9f3231 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -377,6 +377,8 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 
 	crtc_state->has_lobf = (context_latency + guardband) >
 		(first_sdp_position + waketime_in_lines);
+
+	crtc_state->has_alpm = crtc_state->has_lobf;
 }
 
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
@@ -386,8 +388,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 alpm_ctl;
 
-	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
-					  !crtc_state->has_lobf))
+	if (!crtc_state->has_alpm)
 		return;
 
 	mutex_lock(&intel_dp->alpm.lock);
@@ -511,7 +512,7 @@ void intel_alpm_enable_sink(struct intel_dp *intel_dp,
 {
 	u8 val;
 
-	if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)
+	if (!crtc_state->has_alpm)
 		return;
 
 	val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5ae66b7444b6..b5eec21b8a43 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1377,6 +1377,8 @@ struct intel_crtc_state {
 		u8 silence_period_sym_clocks;
 		u8 lfps_half_cycle_num_of_syms;
 	} alpm_state;
+
+	bool has_alpm;
 };
 
 enum intel_pipe_crc_source {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index cfc8b04f98fa..90d43196d35e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1680,6 +1680,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 	crtc_state->enable_psr2_su_region_et =
 		psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay);
 
+	crtc_state->has_alpm = intel_alpm_is_possible(intel_dp);
+
 	return true;
 
 unsupported:
@@ -1749,11 +1751,17 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	if (intel_alpm_is_possible(intel_dp))
+		crtc_state->has_alpm = alpm_config_valid(intel_dp, crtc_state, true, true, false);
+
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
 
 	/* Remaining checks are for eDP only */
 
+	if (!crtc_state->has_alpm)
+		return false;
+
 	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
 	    to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
 		return false;
@@ -1776,9 +1784,6 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))
-		return false;
-
 	return true;
 }
 
@@ -4444,16 +4449,6 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector)
 				    connector, &i915_psr_status_fops);
 }
 
-bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)
-{
-	/*
-	 * eDP Panel Replay uses always ALPM
-	 * PSR2 uses ALPM but PSR1 doesn't
-	 */
-	return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
-					     crtc_state->has_panel_replay);
-}
-
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state)
 {
@@ -4469,7 +4464,7 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 
 	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
 		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
-	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
+	else if (crtc_state->has_alpm)
 		wake_lines = DISPLAY_VER(display) < 20 ?
 			     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
 						    crtc_state->alpm_state.fast_wake_lines) :
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 620b35928832..3cb4fa20e427 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -80,7 +80,6 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state);
 void intel_psr_connector_debugfs_add(struct intel_connector *connector);
 void intel_psr_debugfs_register(struct intel_display *display);
-bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state);
 void intel_psr_compute_config_late(struct intel_dp *intel_dp,
-- 
2.29.0

[PATCH 8/8] drm/i915/alpm: Program lttpr count for DP 2.1 alpm

[Animesh Manna]

Issue a aux write transaction to dpcd 0xf000a with total number of lttpr
before link traning.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 27f3716bdc1f..b1e3ab3f8efc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1623,6 +1623,16 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
 	return passed;
 }
 
+static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp,
+					int lttpr_count)
+{
+	if (!intel_dp_is_edp(intel_dp) ||
+	    intel_dp->lttpr_common_caps[0] <= 0x20)
+		return;
+
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TOTAL_LTTPR_CNT, lttpr_count);
+}
+
 /**
  * intel_dp_start_link_train - start link training
  * @state: Atomic state
@@ -1659,6 +1669,8 @@ void intel_dp_start_link_train(struct intel_atomic_state *state,
 
 	intel_dp_prepare_link_train(intel_dp, crtc_state);
 
+	intel_dp_update_lttpr_count(intel_dp, lttpr_count);
+
 	if (intel_dp_is_uhbr(crtc_state))
 		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
 	else
-- 
2.29.0

Re: [PATCH 2/8] drm/i915/alpm: alpm_init() for DP2.1

[Jani Nikula]

On Thu, 23 Oct 2025, Animesh Manna <animesh.manna@intel.com> wrote:
> Initialize mutex for DP2.1 alpm.

Let's not do that for every detect cycle.

Perhaps intel_alpm_init() needs to be split to one-time init and sink
specific init.

BR,
Jani.


>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 475518b4048b..3f9cbeb215ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6073,8 +6073,12 @@ intel_dp_detect(struct drm_connector *_connector,
>  	if (ret == 1)
>  		connector->base.epoch_counter++;
>  
> -	if (!intel_dp_is_edp(intel_dp))
> +	if (!intel_dp_is_edp(intel_dp)) {
> +		if (DISPLAY_VER(display) >= 35)
> +			intel_alpm_init(intel_dp);
> +
>  		intel_psr_init_dpcd(intel_dp);
> +	}
>  
>  	intel_dp_detect_dsc_caps(intel_dp, connector);

-- 
Jani Nikula, Intel

Re: [PATCH 3/8] drm/i915/alpm: Replace is_edp() with alpm_is_possible()

[Jani Nikula]

On Thu, 23 Oct 2025, Animesh Manna <animesh.manna@intel.com> wrote:
> Add a separate alpm_is_possible() which will check for both edp and dp.

AFAICT you're not ready to actually do ALPM for non-eDP at this point. I
presume things will go bonkers if you run this commit.

You can add the helper, but keep the functionality unchanged until
you've actually implemented ALPM for DP.

BR,
Jani.

>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 16 +++++++++++++---
>  drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
>  2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 6372f533f65b..973791f8956c 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -41,6 +41,16 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
>  		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
>  }
>  
> +bool intel_alpm_is_possible(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	return (DISPLAY_VER(display) >= 12 && intel_dp->alpm_dpcd) ||
> +	       (DISPLAY_VER(display) >= 35 &&
> +		intel_dp->lttpr_common_caps[DP_LTTPR_ALPM_CAPABILITIES -
> +					    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]);
> +}
> +
>  void intel_alpm_init(struct intel_dp *intel_dp)
>  {
>  	u8 dpcd;
> @@ -265,7 +275,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
>  	if (intel_dp->alpm.sink_alpm_error)
>  		return;
>  
> -	if (!intel_dp_is_edp(intel_dp))
> +	if (!intel_alpm_is_possible(intel_dp))
>  		return;
>  
>  	if (DISPLAY_VER(display) < 20)
> @@ -416,7 +426,7 @@ void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
>  
>  		intel_dp = enc_to_intel_dp(encoder);
>  
> -		if (!intel_dp_is_edp(intel_dp))
> +		if (!intel_alpm_is_possible(intel_dp))
>  			continue;
>  
>  		if (old_crtc_state->has_lobf) {
> @@ -468,7 +478,7 @@ void intel_alpm_post_plane_update(struct intel_atomic_state *state,
>  
>  		intel_dp = enc_to_intel_dp(encoder);
>  
> -		if (intel_dp_is_edp(intel_dp)) {
> +		if (intel_alpm_is_possible(intel_dp)) {
>  			intel_alpm_enable_sink(intel_dp, crtc_state);
>  			intel_alpm_configure(intel_dp, crtc_state);
>  		}
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 53599b464dea..0c9972faa2e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -15,6 +15,7 @@ struct intel_connector;
>  struct intel_atomic_state;
>  struct intel_crtc;
>  
> +bool intel_alpm_is_possible(struct intel_dp *intel_dp);
>  void intel_alpm_init(struct intel_dp *intel_dp);
>  bool intel_alpm_compute_params(struct intel_dp *intel_dp,
>  			       struct intel_crtc_state *crtc_state);

-- 
Jani Nikula, Intel

Re: [PATCH 5/8] drm/i915/alpm: Auxless wake time calculation for Xe3p

[Jani Nikula]

On Thu, 23 Oct 2025, Animesh Manna <animesh.manna@intel.com> wrote:
> Add support for auxless waketime calculation for DP2.1 ALPM
> as dependent parameter got changed.
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 78 +++++++++++++++++++----
>  1 file changed, 67 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 0f6b15bca3be..ee5b1e3d79d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -96,6 +96,66 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
>  		1000 / (2 * LFPS_CYCLE_COUNT);
>  }
>  
> +static int get_tphy2_p2_to_p0(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	return DISPLAY_VER(display) >= 35 ? (40 * 1000) : (12 * 1000);
> +}
> +
> +static int get_establishment_period(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state *crtc_state)
> +{
> +	int port_clock = crtc_state->port_clock;
> +	int t1 = 50 * 1000;
> +	int tps4 = (port_clock >= 1000000) ? (396 * 32) : (252 * 10);

intel_dp_is_uhbr()

> +	int tml_phy_lock = 1000 * 1000 * tps4 / port_clock / 10;

That would overflow 32 bits.

> +	int lttpr_count = 0;
> +	int establishment_period;
> +	int tcds;
> +
> +	if (!intel_dp_is_edp(intel_dp)) {

Please turn the branches around to not have the !.

> +		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
> +		tcds = 7 * tml_phy_lock;
> +	} else {
> +		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
> +	}
> +
> +	if (lttpr_count) {
> +		int tlw = 13000;
> +		int tcs = 10000;
> +		int tlfps_period = get_lfps_cycle_time(crtc_state);
> +		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
> +			    (lttpr_count - 1) * (tlw + tlfps_period));
> +		int tacds = 70000;
> +		int tds = (lttpr_count - 1) * 7 * tml_phy_lock;
> +
> +		/* tdrl is same as tcds*/
> +		establishment_period = tlw + tlfps_period + tdcs + tacds + tds + tcds;
> +	} else {
> +		/* TODO: Add a check for data realign by DPCD 0x116[3] */
> +
> +		establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
> +	}
> +
> +	return establishment_period;
> +}
> +
> +static int get_switch_to_active(int port_clock)
> +{
> +	int switch_to_active;
> +
> +	if (port_clock >= 1000000) {

Again, there are uhbr helpers.

> +		int symbol_clock = port_clock / intel_dp_link_symbol_size(port_clock);
> +
> +		switch_to_active = 32 * DIV_ROUND_UP((396 + 3 + 64), symbol_clock);
> +	} else {
> +		switch_to_active = 0;
> +	}
> +
> +	return switch_to_active;
> +}
> +
>  /*
>   * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
>   * tSilence, Max+ tPHY Establishment + tCDS) / tline)
> @@ -115,19 +175,15 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
>   * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
>   * TPS4 Length = 252 Symbols
>   */
> -static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
> +static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
> +					   const struct intel_crtc_state *crtc_state)
>  {
> -	int tphy2_p2_to_p0 = 12 * 1000;
> -	int t1 = 50 * 1000;
> -	int tps4 = 252;
> -	/* port_clock is link rate in 10kbit/s units */
> -	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
> -	int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
> -	int t2 = num_ml_phy_lock * tml_phy_lock;
> -	int tcds = 1 * t2;
> +	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(intel_dp);
> +	int establishment_period = get_establishment_period(intel_dp, crtc_state);
> +	int switch_to_active = get_switch_to_active(crtc_state->port_clock);
>  
>  	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
> -			    SILENCE_PERIOD_TIME + t1 + tcds, 1000);
> +			    establishment_period + switch_to_active, 1000);

Looks like you should *first* refactor this to separate functions,
before adding functionality.

>  }
>  
>  static int
> @@ -139,7 +195,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
>  		lfps_half_cycle;
>  
>  	aux_less_wake_time =
> -		_lnl_compute_aux_less_wake_time(crtc_state);
> +		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
>  	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
>  						       aux_less_wake_time);
>  	silence_period = get_silence_period_symbols(crtc_state);

-- 
Jani Nikula, Intel

Re: [PATCH 6/8] drm/i915/alpm: Half LFPS cycle calculation

[Jani Nikula]

On Thu, 23 Oct 2025, Animesh Manna <animesh.manna@intel.com> wrote:
> Add support for half LFPS cycle calculation for DP2.1 ALPM as dependent
> parameters got changed.
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 32 ++++++++++++++++-------
>  1 file changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index ee5b1e3d79d2..f7803088f916 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -68,31 +68,43 @@ static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
>  		1000 / 1000;
>  }
>  
> -static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
> +static void get_lfps_cycle_min_max_time(struct intel_dp *intel_dp,
> +					const struct intel_crtc_state *crtc_state,
>  					int *min, int *max)
>  {
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	if (!intel_dp_is_edp(intel_dp)) {
> +		*min = 320;
> +		*max = 1600;
> +		return;

You already have an if ladder, make this part of it instead of returning
early.

> +	}
> +
>  	if (crtc_state->port_clock < 540000) {
> -		*min = 65 * LFPS_CYCLE_COUNT;
> -		*max = 75 * LFPS_CYCLE_COUNT;
> +		*min = DISPLAY_VER(display) < 35 ? 65 * LFPS_CYCLE_COUNT : 140;
> +		*max = DISPLAY_VER(display) < 35 ? 75 * LFPS_CYCLE_COUNT : 800;
>  	} else {
>  		*min = 140;
>  		*max = 800;
>  	}
>  }
>  
> -static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
> +static int get_lfps_cycle_time(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state)
>  {
>  	int tlfps_cycle_min, tlfps_cycle_max;
>  
> -	get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
> +	get_lfps_cycle_min_max_time(intel_dp, crtc_state, &tlfps_cycle_min,
>  				    &tlfps_cycle_max);
>  
>  	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
>  }
>  
> -static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
> +static int get_lfps_half_cycle_clocks(struct intel_dp *intel_dp,
> +				      const struct intel_crtc_state *crtc_state)
>  {
> -	return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 /
> +	return get_lfps_cycle_time(intel_dp, crtc_state) *
> +		crtc_state->port_clock / 1000 /
>  		1000 / (2 * LFPS_CYCLE_COUNT);
>  }
>  
> @@ -124,7 +136,7 @@ static int get_establishment_period(struct intel_dp *intel_dp,
>  	if (lttpr_count) {
>  		int tlw = 13000;
>  		int tcs = 10000;
> -		int tlfps_period = get_lfps_cycle_time(crtc_state);
> +		int tlfps_period = get_lfps_cycle_time(intel_dp, crtc_state);
>  		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
>  			    (lttpr_count - 1) * (tlw + tlfps_period));
>  		int tacds = 70000;
> @@ -182,7 +194,7 @@ static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
>  	int establishment_period = get_establishment_period(intel_dp, crtc_state);
>  	int switch_to_active = get_switch_to_active(crtc_state->port_clock);
>  
> -	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
> +	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(intel_dp, crtc_state) +
>  			    establishment_period + switch_to_active, 1000);
>  }
>  
> @@ -200,7 +212,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
>  						       aux_less_wake_time);
>  	silence_period = get_silence_period_symbols(crtc_state);
>  
> -	lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);
> +	lfps_half_cycle = get_lfps_half_cycle_clocks(intel_dp, crtc_state);
>  
>  	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
>  	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||

-- 
Jani Nikula, Intel