* [PATCH 1/2] drm/dp: Move DPCD_REV_XX to drm_dp_helper
@ 2018-03-27 21:56 matthew.s.atwood
2018-03-27 21:56 ` [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 matthew.s.atwood
2018-03-28 6:06 ` [PATCH 1/2] drm/dp: Move DPCD_REV_XX to drm_dp_helper Jani Nikula
0 siblings, 2 replies; 3+ messages in thread
From: matthew.s.atwood @ 2018-03-27 21:56 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: alexander.deucher, Matt Atwood
From: Matt Atwood <matthew.s.atwood@intel.com>
As more differentation occurs between DP spec. Its useful to have these
as macros in a drm_dp_helper.
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/amd/display/include/dpcd_defs.h | 8 --------
include/drm/drm_dp_helper.h | 5 +++++
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
index d8e52e3..d13e0f4 100644
--- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h
+++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
@@ -28,14 +28,6 @@
#include <drm/drm_dp_helper.h>
-enum dpcd_revision {
- DPCD_REV_10 = 0x10,
- DPCD_REV_11 = 0x11,
- DPCD_REV_12 = 0x12,
- DPCD_REV_13 = 0x13,
- DPCD_REV_14 = 0x14
-};
-
/* these are the types stored at DOWNSTREAMPORT_PRESENT */
enum dpcd_downstream_port_type {
DOWNSTREAM_DP = 0,
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 4de97e9..f77746e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -64,6 +64,11 @@
/* AUX CH addresses */
/* DPCD */
#define DP_DPCD_REV 0x000
+# define DPCD_REV_10 0x10
+# define DPCD_REV_11 0x11
+# define DPCD_REV_12 0x12
+# define DPCD_REV_13 0x13
+# define DPCD_REV_14 0x14
#define DP_MAX_LINK_RATE 0x001
--
2.7.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4
2018-03-27 21:56 [PATCH 1/2] drm/dp: Move DPCD_REV_XX to drm_dp_helper matthew.s.atwood
@ 2018-03-27 21:56 ` matthew.s.atwood
2018-03-28 6:06 ` [PATCH 1/2] drm/dp: Move DPCD_REV_XX to drm_dp_helper Jani Nikula
1 sibling, 0 replies; 3+ messages in thread
From: matthew.s.atwood @ 2018-03-27 21:56 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: alexander.deucher, harry.wentland
From: Matt Atwood <matthew.s.atwood@intel.com>
DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8
bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
receiver capabilities. For panels that use this new feature wait interval
would be increased by 512 ms, when spec is max 16 ms. This behavior is
described in table 2-158 of DP 1.4 spec address 0000eh.
With the introduction of DP 1.4 spec main link clock recovery was
standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value.
To avoid breaking panels that are not spec compiant we now warn on
invalid values.
V2: commit title/message, masking all 7 bits, warn on out of spec values.
V3: commit message, make link train clock recovery follow DP 1.4 spec.
V4: style changes
V5: typo
V6: print statement revisions, DP_REV to DPCD_REV, comment correction
V7: typo
V8: Style
V9: Strip out DPCD_REV_XX into seperate patch
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 22 ++++++++++++++++++----
include/drm/drm_dp_helper.h | 1 +
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ffe14ec..f9a8bf9 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -119,18 +119,32 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
- if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+ int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ DP_TRAINING_AUX_RD_MASK;
+
+ if (rd_interval > 4)
+ DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
+ rd_interval);
+
+ if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DPCD_REV_14)
udelay(100);
else
- mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+ mdelay(rd_interval * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
- if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+ int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ DP_TRAINING_AUX_RD_MASK;
+
+ if (rd_interval > 4)
+ DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
+ rd_interval);
+
+ if (rd_interval == 0)
udelay(400);
else
- mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+ mdelay(rd_interval * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f77746e..c1ba415 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -124,6 +124,7 @@
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
+# define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */
#define DP_ADAPTER_CAP 0x00f /* 1.2 */
# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
--
2.7.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] drm/dp: Move DPCD_REV_XX to drm_dp_helper
2018-03-27 21:56 [PATCH 1/2] drm/dp: Move DPCD_REV_XX to drm_dp_helper matthew.s.atwood
2018-03-27 21:56 ` [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 matthew.s.atwood
@ 2018-03-28 6:06 ` Jani Nikula
1 sibling, 0 replies; 3+ messages in thread
From: Jani Nikula @ 2018-03-28 6:06 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: alexander.deucher, Matt Atwood
On Tue, 27 Mar 2018, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
>
> As more differentation occurs between DP spec. Its useful to have these
> as macros in a drm_dp_helper.
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/amd/display/include/dpcd_defs.h | 8 --------
> include/drm/drm_dp_helper.h | 5 +++++
> 2 files changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
> index d8e52e3..d13e0f4 100644
> --- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h
> +++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
> @@ -28,14 +28,6 @@
>
> #include <drm/drm_dp_helper.h>
>
> -enum dpcd_revision {
> - DPCD_REV_10 = 0x10,
> - DPCD_REV_11 = 0x11,
> - DPCD_REV_12 = 0x12,
> - DPCD_REV_13 = 0x13,
> - DPCD_REV_14 = 0x14
> -};
> -
> /* these are the types stored at DOWNSTREAMPORT_PRESENT */
> enum dpcd_downstream_port_type {
> DOWNSTREAM_DP = 0,
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 4de97e9..f77746e 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -64,6 +64,11 @@
> /* AUX CH addresses */
> /* DPCD */
> #define DP_DPCD_REV 0x000
> +# define DPCD_REV_10 0x10
> +# define DPCD_REV_11 0x11
> +# define DPCD_REV_12 0x12
> +# define DPCD_REV_13 0x13
> +# define DPCD_REV_14 0x14
I'm not really sure what these buy us... but no harm done I
guess. Please prefix with DP_ though.
BR,
Jani.
>
> #define DP_MAX_LINK_RATE 0x001
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-03-28 6:06 ` [PATCH 1/2] drm/dp: Move DPCD_REV_XX to drm_dp_helper Jani Nikula
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