* [PATCH v5 0/2] HDMI2.1 PCON Misc Fixes
@ 2021-03-23 11:24 Ankit Nautiyal
2021-03-23 11:24 ` [PATCH v5 1/2] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal
2021-03-23 11:24 ` [PATCH v5 2/2] drm/i915/display: Configure HDMI2.1 Pcon for FRL only if Src-Ctl mode is available Ankit Nautiyal
0 siblings, 2 replies; 6+ messages in thread
From: Ankit Nautiyal @ 2021-03-23 11:24 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Patch1: Tweaks the drm_helpers for PCON configuration.
Patch2: Removes unwanted code not applicable for older platforms.
[Merged]
Patch3: Fixes condition for starting FRL link training.
rev3: Patch-1 from rev2 [Read PCON DSC ENC caps only for DPCD
rev >= 1.4] is dropped as it mixes DPCD and DP revisions.
rev4: Rebased
Ankit Nautiyal (2):
drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
drm/i915/display: Configure HDMI2.1 Pcon for FRL only if Src-Ctl mode
is available
drivers/gpu/drm/drm_dp_helper.c | 24 ++++++++++++++----------
drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++--------
include/drm/drm_dp_helper.h | 6 ++++--
3 files changed, 29 insertions(+), 20 deletions(-)
base-commit: 8e469260b87ff08620181d86570f7ec4e41c0ef7
--
2.29.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v5 1/2] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON 2021-03-23 11:24 [PATCH v5 0/2] HDMI2.1 PCON Misc Fixes Ankit Nautiyal @ 2021-03-23 11:24 ` Ankit Nautiyal 2021-03-26 9:47 ` [Intel-gfx] " Jani Nikula 2021-03-23 11:24 ` [PATCH v5 2/2] drm/i915/display: Configure HDMI2.1 Pcon for FRL only if Src-Ctl mode is available Ankit Nautiyal 1 sibling, 1 reply; 6+ messages in thread From: Ankit Nautiyal @ 2021-03-23 11:24 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Currently the FRL training mode (Concurrent, Sequential) and training type (Normal, Extended) are not defined properly and are passed as bool values in drm_helpers for pcon configuration for FRL training. This patch: -Add register masks for Sequential and Normal FRL training options. -Fixes the drm_helpers for FRL Training configuration to use the appropriate masks. -Modifies the calls to the above drm_helpers in i915/intel_dp as per the above change. v2: Re-used the register masks for these options, instead of enum. (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 24 ++++++++++++++---------- drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++------ include/drm/drm_dp_helper.h | 6 ++++-- 3 files changed, 22 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index eedbb48815b7..cb2f53e56685 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -2635,14 +2635,16 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 * @aux: DisplayPort AUX channel * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink - * @concurrent_mode: true if concurrent mode or operation is required, - * false otherwise. + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. + * In Concurrent Mode, the FRL link bring up can be done along with + * DP Link training. In Sequential mode, the FRL link bring up is done prior to + * the DP Link training. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode) + u8 frl_mode) { int ret; u8 buf; @@ -2651,7 +2653,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, if (ret < 0) return ret; - if (concurrent_mode) + if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK) buf |= DP_PCON_ENABLE_CONCURRENT_LINK; else buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; @@ -2694,21 +2696,23 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 * @aux: DisplayPort AUX channel * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink - * @extended_train_mode : true for Extended Mode, false for Normal Mode. - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting - * from min, and stops when link training is successful. In Extended mode, all - * frl bw selected in the mask are trained by the PCON. + * @frl_type : FRL training type, can be Extended, or Normal. + * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask + * starting from min, and stops when link training is successful. In Extended + * FRL training, all frl bw selected in the mask are trained by the PCON. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode) + u8 frl_type) { int ret; u8 buf = max_frl_mask; - if (extended_train_mode) + if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED) buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; + else + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); if (ret < 0) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1400c5b44c83..1f6f4d0c8e2d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2073,10 +2073,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) { -#define PCON_EXTENDED_TRAIN_MODE (1 > 0) -#define PCON_CONCURRENT_MODE (1 > 0) -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE #define TIMEOUT_FRL_READY_MS 500 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 @@ -2110,10 +2106,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) return -ETIMEDOUT; max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE); + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, + DP_PCON_ENABLE_SEQUENTIAL_LINK); if (ret < 0) return ret; - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE); + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, + DP_PCON_FRL_LINK_TRAIN_NORMAL); if (ret < 0) return ret; ret = drm_dp_pcon_frl_enable(&intel_dp->aux); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 632ad7faa006..85d728f4aad0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1176,6 +1176,7 @@ struct drm_device; # define DP_PCON_ENABLE_MAX_BW_48GBPS 6 # define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) # define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) +# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) # define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) # define DP_PCON_ENABLE_HPD_READY (1 << 6) # define DP_PCON_ENABLE_HDMI_LINK (1 << 7) @@ -1190,6 +1191,7 @@ struct drm_device; # define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) # define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) # define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) +# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) /* PCON HDMI LINK STATUS */ #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B @@ -2154,9 +2156,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode); + u8 frl_mode); int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode); + u8 frl_type); int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); -- 2.29.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v5 1/2] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON 2021-03-23 11:24 ` [PATCH v5 1/2] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal @ 2021-03-26 9:47 ` Jani Nikula 2021-03-26 14:59 ` Maxime Ripard 0 siblings, 1 reply; 6+ messages in thread From: Jani Nikula @ 2021-03-26 9:47 UTC (permalink / raw) To: Ankit Nautiyal, intel-gfx; +Cc: Thomas Zimmermann, dri-devel On Tue, 23 Mar 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote: > Currently the FRL training mode (Concurrent, Sequential) and > training type (Normal, Extended) are not defined properly and > are passed as bool values in drm_helpers for pcon > configuration for FRL training. > > This patch: > -Add register masks for Sequential and Normal FRL training options. > -Fixes the drm_helpers for FRL Training configuration to use the > appropriate masks. > -Modifies the calls to the above drm_helpers in i915/intel_dp as per > the above change. > > v2: Re-used the register masks for these options, instead of enum. (Ville) > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Maarten, Maxime, Thomas - Can I get an ack for merging this via drm-intel-next, please? BR, Jani. > --- > drivers/gpu/drm/drm_dp_helper.c | 24 ++++++++++++++---------- > drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++------ > include/drm/drm_dp_helper.h | 6 ++++-- > 3 files changed, 22 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index eedbb48815b7..cb2f53e56685 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -2635,14 +2635,16 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); > * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 > * @aux: DisplayPort AUX channel > * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink > - * @concurrent_mode: true if concurrent mode or operation is required, > - * false otherwise. > + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. > + * In Concurrent Mode, the FRL link bring up can be done along with > + * DP Link training. In Sequential mode, the FRL link bring up is done prior to > + * the DP Link training. > * > * Returns 0 if success, else returns negative error code. > */ > > int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, > - bool concurrent_mode) > + u8 frl_mode) > { > int ret; > u8 buf; > @@ -2651,7 +2653,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, > if (ret < 0) > return ret; > > - if (concurrent_mode) > + if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK) > buf |= DP_PCON_ENABLE_CONCURRENT_LINK; > else > buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; > @@ -2694,21 +2696,23 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); > * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 > * @aux: DisplayPort AUX channel > * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink > - * @extended_train_mode : true for Extended Mode, false for Normal Mode. > - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting > - * from min, and stops when link training is successful. In Extended mode, all > - * frl bw selected in the mask are trained by the PCON. > + * @frl_type : FRL training type, can be Extended, or Normal. > + * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask > + * starting from min, and stops when link training is successful. In Extended > + * FRL training, all frl bw selected in the mask are trained by the PCON. > * > * Returns 0 if success, else returns negative error code. > */ > int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, > - bool extended_train_mode) > + u8 frl_type) > { > int ret; > u8 buf = max_frl_mask; > > - if (extended_train_mode) > + if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED) > buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; > + else > + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; > > ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); > if (ret < 0) > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 1400c5b44c83..1f6f4d0c8e2d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2073,10 +2073,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) > > static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) > { > -#define PCON_EXTENDED_TRAIN_MODE (1 > 0) > -#define PCON_CONCURRENT_MODE (1 > 0) > -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE > -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE > #define TIMEOUT_FRL_READY_MS 500 > #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 > > @@ -2110,10 +2106,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) > return -ETIMEDOUT; > > max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); > - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE); > + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, > + DP_PCON_ENABLE_SEQUENTIAL_LINK); > if (ret < 0) > return ret; > - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE); > + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, > + DP_PCON_FRL_LINK_TRAIN_NORMAL); > if (ret < 0) > return ret; > ret = drm_dp_pcon_frl_enable(&intel_dp->aux); > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 632ad7faa006..85d728f4aad0 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1176,6 +1176,7 @@ struct drm_device; > # define DP_PCON_ENABLE_MAX_BW_48GBPS 6 > # define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) > # define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) > +# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) > # define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) > # define DP_PCON_ENABLE_HPD_READY (1 << 6) > # define DP_PCON_ENABLE_HDMI_LINK (1 << 7) > @@ -1190,6 +1191,7 @@ struct drm_device; > # define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) > # define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) > # define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) > +# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) > > /* PCON HDMI LINK STATUS */ > #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B > @@ -2154,9 +2156,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], > int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); > bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); > int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, > - bool concurrent_mode); > + u8 frl_mode); > int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, > - bool extended_train_mode); > + u8 frl_type); > int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); > int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v5 1/2] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON 2021-03-26 9:47 ` [Intel-gfx] " Jani Nikula @ 2021-03-26 14:59 ` Maxime Ripard 2021-03-31 10:21 ` Jani Nikula 0 siblings, 1 reply; 6+ messages in thread From: Maxime Ripard @ 2021-03-26 14:59 UTC (permalink / raw) To: Jani Nikula; +Cc: Thomas Zimmermann, Ankit Nautiyal, intel-gfx, dri-devel [-- Attachment #1.1: Type: text/plain, Size: 1125 bytes --] Hi, On Fri, Mar 26, 2021 at 11:47:58AM +0200, Jani Nikula wrote: > On Tue, 23 Mar 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote: > > Currently the FRL training mode (Concurrent, Sequential) and > > training type (Normal, Extended) are not defined properly and > > are passed as bool values in drm_helpers for pcon > > configuration for FRL training. > > > > This patch: > > -Add register masks for Sequential and Normal FRL training options. > > -Fixes the drm_helpers for FRL Training configuration to use the > > appropriate masks. > > -Modifies the calls to the above drm_helpers in i915/intel_dp as per > > the above change. > > > > v2: Re-used the register masks for these options, instead of enum. (Ville) > > > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Maarten, Maxime, Thomas - > > Can I get an ack for merging this via drm-intel-next, please? I was hoping that someone with either i915 or DP knowledge would comment, but the patch looks fine to me, you can go ahead I guess :) Maxime [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v5 1/2] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON 2021-03-26 14:59 ` Maxime Ripard @ 2021-03-31 10:21 ` Jani Nikula 0 siblings, 0 replies; 6+ messages in thread From: Jani Nikula @ 2021-03-31 10:21 UTC (permalink / raw) To: Maxime Ripard; +Cc: Thomas Zimmermann, Ankit Nautiyal, intel-gfx, dri-devel On Fri, 26 Mar 2021, Maxime Ripard <maxime@cerno.tech> wrote: > Hi, > > On Fri, Mar 26, 2021 at 11:47:58AM +0200, Jani Nikula wrote: >> On Tue, 23 Mar 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote: >> > Currently the FRL training mode (Concurrent, Sequential) and >> > training type (Normal, Extended) are not defined properly and >> > are passed as bool values in drm_helpers for pcon >> > configuration for FRL training. >> > >> > This patch: >> > -Add register masks for Sequential and Normal FRL training options. >> > -Fixes the drm_helpers for FRL Training configuration to use the >> > appropriate masks. >> > -Modifies the calls to the above drm_helpers in i915/intel_dp as per >> > the above change. >> > >> > v2: Re-used the register masks for these options, instead of enum. (Ville) >> > >> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >> >> Maarten, Maxime, Thomas - >> >> Can I get an ack for merging this via drm-intel-next, please? > > I was hoping that someone with either i915 or DP knowledge would > comment, but the patch looks fine to me, you can go ahead I guess :) Thanks for the patch, review, and ack, pushed the lot to drm-intel-next. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 2/2] drm/i915/display: Configure HDMI2.1 Pcon for FRL only if Src-Ctl mode is available 2021-03-23 11:24 [PATCH v5 0/2] HDMI2.1 PCON Misc Fixes Ankit Nautiyal 2021-03-23 11:24 ` [PATCH v5 1/2] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal @ 2021-03-23 11:24 ` Ankit Nautiyal 1 sibling, 0 replies; 6+ messages in thread From: Ankit Nautiyal @ 2021-03-23 11:24 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Add the check if source control mode is supported by the PCON, before starting configuring PCON for FRL training, as per spec VESA DP2.0-HDMI2.1 PCON Draft-1 Sec-7. v2: Added spec details for the change. (Uma) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1f6f4d0c8e2d..76024452e434 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2155,8 +2155,13 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - /* Always go for FRL training if supported */ - if (!intel_dp_is_hdmi_2_1_sink(intel_dp) || + /* + * Always go for FRL training if: + * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) + * -sink is HDMI2.1 + */ + if (!(intel_dp->dpcd[2] & DP_PCON_SOURCE_CTL_MODE) || + !intel_dp_is_hdmi_2_1_sink(intel_dp) || intel_dp->frl.is_trained) return; -- 2.29.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-03-31 10:21 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-03-23 11:24 [PATCH v5 0/2] HDMI2.1 PCON Misc Fixes Ankit Nautiyal 2021-03-23 11:24 ` [PATCH v5 1/2] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal 2021-03-26 9:47 ` [Intel-gfx] " Jani Nikula 2021-03-26 14:59 ` Maxime Ripard 2021-03-31 10:21 ` Jani Nikula 2021-03-23 11:24 ` [PATCH v5 2/2] drm/i915/display: Configure HDMI2.1 Pcon for FRL only if Src-Ctl mode is available Ankit Nautiyal
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox