[PATCH 0/2] eDP DSC fixes

[PATCH 0/2] eDP DSC fixes

[Ankit Nautiyal]

Assume 8bpc is supported if Sink claims DSC support.
Also consider bpc constraint coming from EDID while computing
input BPC for DSC.

Ankit Nautiyal (2):
  drm/display/dp: Default 8 bpc support when DSC is supported
  drivers/drm/i915: Honor limits->max_bpp while computing DSC max input
    bpp

 drivers/gpu/drm/display/drm_dp_helper.c | 9 +++++++--
 drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
 2 files changed, 10 insertions(+), 3 deletions(-)

-- 
2.40.1

[PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported

[Ankit Nautiyal]

As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
Apparently some panels that do support DSC, are not setting the bit for
8bpc.

So always assume 8bpc support by DSC decoder, when DSC is claimed to be
supported.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index e6a78fd32380..0aa4ce17420c 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2447,14 +2447,19 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 					 u8 dsc_bpc[3])
 {
 	int num_bpc = 0;
+
+	if (!dsc_dpcd[DP_DSC_SUPPORT] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
+		return 0;
+
 	u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
 
 	if (color_depth & DP_DSC_12_BPC)
 		dsc_bpc[num_bpc++] = 12;
 	if (color_depth & DP_DSC_10_BPC)
 		dsc_bpc[num_bpc++] = 10;
-	if (color_depth & DP_DSC_8_BPC)
-		dsc_bpc[num_bpc++] = 8;
+
+	/* A DP DSC Sink devices shall support 8 bpc. */
+	dsc_bpc[num_bpc++] = 8;
 
 	return num_bpc;
 }
-- 
2.40.1

Re: [PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported

[kernel test robot]

Hi Ankit,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on linus/master v6.5-rc7 next-20230823]
[cannot apply to drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-misc/drm-misc-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ankit-Nautiyal/drm-display-dp-Default-8-bpc-support-when-DSC-is-supported/20230823-195946
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230823115425.715644-2-ankit.k.nautiyal%40intel.com
patch subject: [PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported
config: i386-randconfig-r036-20230823 (https://download.01.org/0day-ci/archive/20230824/202308240007.1edS9XsL-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce: (https://download.01.org/0day-ci/archive/20230824/202308240007.1edS9XsL-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202308240007.1edS9XsL-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/display/drm_dp_helper.c:2451:6: warning: logical not is only applied to the left hand side of this bitwise operator [-Wlogical-not-parentheses]
           if (!dsc_dpcd[DP_DSC_SUPPORT] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
               ^                         ~
   drivers/gpu/drm/display/drm_dp_helper.c:2451:6: note: add parentheses after the '!' to evaluate the bitwise operator first
           if (!dsc_dpcd[DP_DSC_SUPPORT] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
               ^
                (                                                           )
   drivers/gpu/drm/display/drm_dp_helper.c:2451:6: note: add parentheses around left hand side expression to silence this warning
           if (!dsc_dpcd[DP_DSC_SUPPORT] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
               ^
               (                        )
   1 warning generated.


vim +2451 drivers/gpu/drm/display/drm_dp_helper.c

  2428	
  2429	/**
  2430	 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
  2431	 * values supported by the DSC sink.
  2432	 * @dsc_dpcd: DSC capabilities from DPCD
  2433	 * @dsc_bpc: An array to be filled by this helper with supported
  2434	 *           input bpcs.
  2435	 *
  2436	 * Read the DSC DPCD from the sink device to parse the supported bits per
  2437	 * component values. This is used to populate the DSC parameters
  2438	 * in the &struct drm_dsc_config by the driver.
  2439	 * Driver creates an infoframe using these parameters to populate
  2440	 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
  2441	 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
  2442	 *
  2443	 * Returns:
  2444	 * Number of input BPC values parsed from the DPCD
  2445	 */
  2446	int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
  2447						 u8 dsc_bpc[3])
  2448	{
  2449		int num_bpc = 0;
  2450	
> 2451		if (!dsc_dpcd[DP_DSC_SUPPORT] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
  2452			return 0;
  2453	
  2454		u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
  2455	
  2456		if (color_depth & DP_DSC_12_BPC)
  2457			dsc_bpc[num_bpc++] = 12;
  2458		if (color_depth & DP_DSC_10_BPC)
  2459			dsc_bpc[num_bpc++] = 10;
  2460	
  2461		/* A DP DSC Sink devices shall support 8 bpc. */
  2462		dsc_bpc[num_bpc++] = 8;
  2463	
  2464		return num_bpc;
  2465	}
  2466	EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
  2467	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported

[Ankit Nautiyal]

As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
Apparently some panels that do support DSC, are not setting the bit for
8bpc.

So always assume 8bpc support by DSC decoder, when DSC is claimed to be
supported.

v2: Use helper to check dsc support. (Ankit)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index e6a78fd32380..309fc10cde78 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2447,14 +2447,19 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 					 u8 dsc_bpc[3])
 {
 	int num_bpc = 0;
+
+	if(!drm_dp_sink_supports_dsc(dsc_dpcd))
+		return 0;
+
 	u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
 
 	if (color_depth & DP_DSC_12_BPC)
 		dsc_bpc[num_bpc++] = 12;
 	if (color_depth & DP_DSC_10_BPC)
 		dsc_bpc[num_bpc++] = 10;
-	if (color_depth & DP_DSC_8_BPC)
-		dsc_bpc[num_bpc++] = 8;
+
+	/* A DP DSC Sink devices shall support 8 bpc. */
+	dsc_bpc[num_bpc++] = 8;
 
 	return num_bpc;
 }
-- 
2.40.1

Re: [PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported

[Jani Nikula]

On Thu, 24 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
> Apparently some panels that do support DSC, are not setting the bit for
> 8bpc.
>
> So always assume 8bpc support by DSC decoder, when DSC is claimed to be
> supported.
>
> v2: Use helper to check dsc support. (Ankit)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/display/drm_dp_helper.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index e6a78fd32380..309fc10cde78 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2447,14 +2447,19 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>  					 u8 dsc_bpc[3])
>  {
>  	int num_bpc = 0;
> +
> +     if(!drm_dp_sink_supports_dsc(dsc_dpcd))
          ^

Missing space.

> +		return 0;
> +
>  	u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];

All declarations should be before code.

>  
>  	if (color_depth & DP_DSC_12_BPC)
>  		dsc_bpc[num_bpc++] = 12;
>  	if (color_depth & DP_DSC_10_BPC)
>  		dsc_bpc[num_bpc++] = 10;
> -	if (color_depth & DP_DSC_8_BPC)
> -		dsc_bpc[num_bpc++] = 8;
> +
> +	/* A DP DSC Sink devices shall support 8 bpc. */

Mixed singular and plural, a ... devices.

> +	dsc_bpc[num_bpc++] = 8;
>  
>  	return num_bpc;
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported

[Nautiyal, Ankit K]

Thanks Jani for the corrections and suggestions.

I agree to them and will fix them in next version.

Now that I see the commit subject line also should have been "Assume 8 
bpc support when DSC is supported", will change that too.

Regards,

Ankit

On 8/24/2023 3:15 PM, Jani Nikula wrote:
> On Thu, 24 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
>> Apparently some panels that do support DSC, are not setting the bit for
>> 8bpc.
>>
>> So always assume 8bpc support by DSC decoder, when DSC is claimed to be
>> supported.
>>
>> v2: Use helper to check dsc support. (Ankit)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/display/drm_dp_helper.c | 9 +++++++--
>>   1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
>> index e6a78fd32380..309fc10cde78 100644
>> --- a/drivers/gpu/drm/display/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
>> @@ -2447,14 +2447,19 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>>   					 u8 dsc_bpc[3])
>>   {
>>   	int num_bpc = 0;
>> +
>> +     if(!drm_dp_sink_supports_dsc(dsc_dpcd))
>            ^
>
> Missing space.
>
>> +		return 0;
>> +
>>   	u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
> All declarations should be before code.
>
>>   
>>   	if (color_depth & DP_DSC_12_BPC)
>>   		dsc_bpc[num_bpc++] = 12;
>>   	if (color_depth & DP_DSC_10_BPC)
>>   		dsc_bpc[num_bpc++] = 10;
>> -	if (color_depth & DP_DSC_8_BPC)
>> -		dsc_bpc[num_bpc++] = 8;
>> +
>> +	/* A DP DSC Sink devices shall support 8 bpc. */
> Mixed singular and plural, a ... devices.
>
>> +	dsc_bpc[num_bpc++] = 8;
>>   
>>   	return num_bpc;
>>   }

[PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp

[Ankit Nautiyal]

Edid specific BPC constraints are stored in limits->max_bpp. Honor these
limits while computing the input bpp for DSC.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5b48bfe09d0e..2a7f6cfe2832 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2061,9 +2061,11 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	if (forced_bpp) {
 		pipe_bpp = forced_bpp;
 	} else {
+		u8 max_bpc = limits->max_bpp / 3;
+
 		/* For eDP use max bpp that can be supported with DSC. */
 		pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
-							conn_state->max_requested_bpc);
+							min(max_bpc, conn_state->max_requested_bpc));
 		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
 			drm_dbg_kms(&i915->drm,
 				    "Computed BPC is not in DSC BPC limits\n");
-- 
2.40.1

Re: [Intel-gfx] [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp

[Lisovskiy, Stanislav]

On Wed, Aug 23, 2023 at 05:24:25PM +0530, Ankit Nautiyal wrote:
> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
> limits while computing the input bpp for DSC.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

That is kind of funny, I can see this patch in my mails but can't
see the other one you had "Default 8 bpc support when DSC is supported",
which is visible from patchwork.
Anyways I give r-b for that one as well.

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5b48bfe09d0e..2a7f6cfe2832 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2061,9 +2061,11 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	if (forced_bpp) {
>  		pipe_bpp = forced_bpp;
>  	} else {
> +		u8 max_bpc = limits->max_bpp / 3;
> +
>  		/* For eDP use max bpp that can be supported with DSC. */
>  		pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
> -							conn_state->max_requested_bpc);
> +							min(max_bpc, conn_state->max_requested_bpc));
>  		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
>  			drm_dbg_kms(&i915->drm,
>  				    "Computed BPC is not in DSC BPC limits\n");
> -- 
> 2.40.1
> 

Re: [Intel-gfx] [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp

[Nautiyal, Ankit K]

Thanks Stan for the review.

Regards,

Ankit

On 8/24/2023 2:59 PM, Lisovskiy, Stanislav wrote:
> On Wed, Aug 23, 2023 at 05:24:25PM +0530, Ankit Nautiyal wrote:
>> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
>> limits while computing the input bpp for DSC.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> That is kind of funny, I can see this patch in my mails but can't
> see the other one you had "Default 8 bpc support when DSC is supported",
> which is visible from patchwork.
> Anyways I give r-b for that one as well.
>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>>   1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 5b48bfe09d0e..2a7f6cfe2832 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2061,9 +2061,11 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>   	if (forced_bpp) {
>>   		pipe_bpp = forced_bpp;
>>   	} else {
>> +		u8 max_bpc = limits->max_bpp / 3;
>> +
>>   		/* For eDP use max bpp that can be supported with DSC. */
>>   		pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
>> -							conn_state->max_requested_bpc);
>> +							min(max_bpc, conn_state->max_requested_bpc));
>>   		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
>>   			drm_dbg_kms(&i915->drm,
>>   				    "Computed BPC is not in DSC BPC limits\n");
>> -- 
>> 2.40.1
>>

Re: [Intel-gfx] [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp

[Jani Nikula]

On Wed, 23 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
> limits while computing the input bpp for DSC.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5b48bfe09d0e..2a7f6cfe2832 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2061,9 +2061,11 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	if (forced_bpp) {
>  		pipe_bpp = forced_bpp;
>  	} else {
> +		u8 max_bpc = limits->max_bpp / 3;
> +

		int max_bpc = min_t(int, limits->max_bpp / 3, conn_state->max_requested_bpc);

>  		/* For eDP use max bpp that can be supported with DSC. */
>  		pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, max_bbc);

Nitpick, IMO looks cleaner this way, as well as uses int instead of u8
for computations.

BR,
Jani.

>  		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
>  			drm_dbg_kms(&i915->drm,
>  				    "Computed BPC is not in DSC BPC limits\n");

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp

[Nautiyal, Ankit K]

On 8/24/2023 3:14 PM, Jani Nikula wrote:
> On Wed, 23 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
>> limits while computing the input bpp for DSC.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>>   1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 5b48bfe09d0e..2a7f6cfe2832 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2061,9 +2061,11 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>   	if (forced_bpp) {
>>   		pipe_bpp = forced_bpp;
>>   	} else {
>> +		u8 max_bpc = limits->max_bpp / 3;
>> +
> 		int max_bpc = min_t(int, limits->max_bpp / 3, conn_state->max_requested_bpc);
>
>>   		/* For eDP use max bpp that can be supported with DSC. */
>>   		pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, max_bbc);
> Nitpick, IMO looks cleaner this way, as well as uses int instead of u8
> for computations.
>
> BR,
> Jani.

Thanks Jani for the comments, it does makes sense. Will fix in next 
version shortly.

Regards,

Ankit

>>   		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
>>   			drm_dbg_kms(&i915->drm,
>>   				    "Computed BPC is not in DSC BPC limits\n");