Re: [PATCH 2/3] drm: Change limited M/N quirk to constant N quirk.

[Jani Nikula <jani.nikula@intel.com>]

On Mon, 10 Sep 2018, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
> Some DP dongles in particular seem to be fussy about too large
> link M/N values. Set specific value for N divider can resolve
> this issue per dongle vendor's comment. So configure N as
> constant value (0x8000) to instead of reduce M/N formula when
> specific DP dongle connected.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Lee, Shawn C <shawn.c.lee@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c      |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++---------------
>  drivers/gpu/drm/i915/intel_display.h |  2 +-
>  drivers/gpu/drm/i915/intel_dp.c      |  8 ++++----
>  drivers/gpu/drm/i915/intel_dp_mst.c  |  6 +++---
>  include/drm/drm_dp_helper.h          |  6 +++---
>  6 files changed, 23 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 22753928af41..d0c1250975ab 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1269,7 +1269,7 @@ struct dpcd_quirk {
>  
>  static const struct dpcd_quirk dpcd_quirk_list[] = {
>  	/* Analogix 7737 needs reduced M and N at HBR2 link rates */
> -	{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
> +	{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
>  };
>  
>  #undef OUI
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ec3e24f07486..b26f4ae60810 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6680,22 +6680,18 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
>  
>  static void compute_m_n(unsigned int m, unsigned int n,
>  			uint32_t *ret_m, uint32_t *ret_n,
> -			bool reduce_m_n)
> +			bool constant_n)
>  {
>  	/*
> -	 * Reduce M/N as much as possible without loss in precision. Several DP
> -	 * dongles in particular seem to be fussy about too large *link* M/N
> -	 * values. The passed in values are more likely to have the least
> -	 * significant bits zero than M after rounding below, so do this first.
> +	 * Several DP dongles in particular seem to be fussy about
> +	 * too large *link* M/N * values. Give N value as 0x8000
                                ^
Extra *.

> +	 * that should be acceptable by specific devices.

Please also add something like:

	0x8000 is the specified fixed N value for asynchronous clock
	mode, which the devices expect also in synchronous clock mode.


>  	 */
> -	if (reduce_m_n) {
> -		while ((m & 1) == 0 && (n & 1) == 0) {
> -			m >>= 1;
> -			n >>= 1;
> -		}
> -	}
> +	if (constant_n)
> +		*ret_n = 0x8000;
> +	else
> +		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
>  
> -	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
>  	*ret_m = div_u64((uint64_t) m * *ret_n, n);
>  	intel_reduce_m_n_ratio(ret_m, ret_n);
>  }
> @@ -6704,18 +6700,18 @@ void
>  intel_link_compute_m_n(int bits_per_pixel, int nlanes,
>  		       int pixel_clock, int link_clock,
>  		       struct intel_link_m_n *m_n,
> -		       bool reduce_m_n)
> +		       bool constant_n)
>  {
>  	m_n->tu = 64;
>  
>  	compute_m_n(bits_per_pixel * pixel_clock,
>  		    link_clock * nlanes * 8,
>  		    &m_n->gmch_m, &m_n->gmch_n,
> -		    reduce_m_n);
> +		    constant_n);
>  
>  	compute_m_n(pixel_clock, link_clock,
>  		    &m_n->link_m, &m_n->link_n,
> -		    reduce_m_n);
> +		    constant_n);
>  }
>  
>  static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 43f080c6538d..8e8bd5eed2c2 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -379,7 +379,7 @@ struct intel_link_m_n {
>  void intel_link_compute_m_n(int bpp, int nlanes,
>  			    int pixel_clock, int link_clock,
>  			    struct intel_link_m_n *m_n,
> -			    bool reduce_m_n);
> +			    bool constant_n);
>  
>  bool is_ccs_modifier(u64 modifier);
>  #endif
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 436c22de33b6..fce4be57ccc9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1998,8 +1998,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	struct intel_connector *intel_connector = intel_dp->attached_connector;
>  	struct intel_digital_connector_state *intel_conn_state =
>  		to_intel_digital_connector_state(conn_state);
> -	bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
> -					   DP_DPCD_QUIRK_LIMITED_M_N);
> +	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
> +					   DP_DPCD_QUIRK_CONSTANT_N);
>  
>  	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
>  		pipe_config->has_pch_encoder = true;
> @@ -2064,7 +2064,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  			       adjusted_mode->crtc_clock,
>  			       pipe_config->port_clock,
>  			       &pipe_config->dp_m_n,
> -			       reduce_m_n);
> +			       constant_n);
>  
>  	if (intel_connector->panel.downclock_mode != NULL &&
>  		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
> @@ -2074,7 +2074,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  					       intel_connector->panel.downclock_mode->clock,
>  					       pipe_config->port_clock,
>  					       &pipe_config->dp_m2_n2,
> -					       reduce_m_n);
> +					       costant_n);

Typo costant_n?

>  	}
>  
>  	if (!HAS_DDI(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 352e5216cc65..184023435b08 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -45,8 +45,8 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  	int lane_count, slots;
>  	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
>  	int mst_pbn;
> -	bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
> -					   DP_DPCD_QUIRK_LIMITED_M_N);
> +	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
> +					   DP_DPCD_QUIRK_CONSTANT_N);
>  
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return false;
> @@ -87,7 +87,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  			       adjusted_mode->crtc_clock,
>  			       pipe_config->port_clock,
>  			       &pipe_config->dp_m_n,
> -			       reduce_m_n);
> +			       constant_n);
>  
>  	pipe_config->dp_m_n.tu = slots;
>  
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 05cc31b5db16..ab0914ef5e38 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1260,12 +1260,12 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
>   */
>  enum drm_dp_quirk {
>  	/**
> -	 * @DP_DPCD_QUIRK_LIMITED_M_N:
> +	 * @DP_DPCD_QUIRK_CONSTANT_N:
>  	 *
>  	 * The device requires main link attributes Mvid and Nvid to be limited
> -	 * to 16 bits.
> +	 * to 16 bits.So will give a constant value (0x8000) for compatibility.
                      ^

Missing space.

With the minor issues fixed,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>



>  	 */
> -	DP_DPCD_QUIRK_LIMITED_M_N,
> +	DP_DPCD_QUIRK_CONSTANT_N,
>  };
>  
>  /**

-- 
Jani Nikula, Intel Open Source Graphics Center
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