[PATCH v2 0/1] gpu/drm: bridge: tc358768: Add delay after PLL setup

[PATCH v2 0/1] gpu/drm: bridge: tc358768: Add delay after PLL setup

[Svyatoslav Ryhel]

After tc358768_setup_pll() enables PLL_CKEN and the lock indicator comes
up, the DSI register sequence runs near immediately. On TF700T this
results in the bridge claiming PLL lock but producing no DSI video output:
the panel powers up, the backlight comes on, but the framebuffer is never
scanned out.

Insert a small settling delay between PLL setup and the rest of the
attach.

---
- switched sleep() > delay() since *_pre_enable() is atomic
---

Svyatoslav Ryhel (1):
  gpu/drm: bridge: tc358768: Add delay after PLL setup

 drivers/gpu/drm/bridge/tc358768.c | 3 +++
 1 file changed, 3 insertions(+)

-- 
2.53.0

[PATCH v2 1/1] gpu/drm: bridge: tc358768: Add delay after PLL setup

[Svyatoslav Ryhel]

After tc358768_setup_pll() enables PLL_CKEN and the lock indicator comes
up, the DSI register sequence runs near immediately. On TF700T this
results in the bridge claiming PLL lock but producing no DSI video output:
the panel powers up, the backlight comes on, but the framebuffer is never
scanned out.

Insert a small settling delay between PLL setup and the rest of the
attach.

Suggested-by: Michele Brocco <brocco@perceptos.de>
Tested-by: Michele Brocco <brocco@perceptos.de> # TF700T
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/gpu/drm/bridge/tc358768.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c
index 0f2820b37302..ea358c8da0e9 100644
--- a/drivers/gpu/drm/bridge/tc358768.c
+++ b/drivers/gpu/drm/bridge/tc358768.c
@@ -824,6 +824,9 @@ static void tc358768_bridge_atomic_pre_enable(struct drm_bridge *bridge,
 		return;
 	}
 
+	/* Allow the PLL to settle */
+	mdelay(20);
+
 	drm_display_mode_to_videomode(mode, &vm);
 
 	dsiclk = priv->dsiclk;
-- 
2.53.0

Re: [PATCH v2 1/1] gpu/drm: bridge: tc358768: Add delay after PLL setup

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Preexisting calls to sleeping functions in atomic context callback paths.
--

commit e9444612d599575c476a8af0ea940cddf9416e28
Author: Svyatoslav Ryhel <clamor95@gmail.com>

gpu/drm: bridge: tc358768: Add delay after PLL setup

This commit adds a 20ms delay after tc358768_setup_pll() in
tc358768_bridge_atomic_pre_enable() to allow the PLL to settle, fixing an
issue where the bridge claims PLL lock but produces no DSI video output.

> diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c
> index 0f2820b373029..ea358c8da0e99 100644
> --- a/drivers/gpu/drm/bridge/tc358768.c
> +++ b/drivers/gpu/drm/bridge/tc358768.c
> @@ -824,6 +824,9 @@ static void tc358768_bridge_atomic_pre_enable(struct drm_bridge *bridge,
>  		return;
>  	}

[Severity: High]
This isn't a bug introduced by this patch, but does calling
tc358768_setup_pll() and tc358768_hw_enable() from the atomic pre_enable
callback risk sleeping in atomic context?

Looking at tc358768_setup_pll() in drivers/gpu/drm/bridge/tc358768.c, it
calls usleep_range():

tc358768_setup_pll()
    /* wait for lock */
    usleep_range(1000, 2000);

Additionally, earlier in tc358768_bridge_atomic_pre_enable(), there is a
call to tc358768_hw_enable() which also contains sleeping functions:

tc358768_hw_enable()
    gpiod_set_value_cansleep(priv->reset_gpio, 0);

    /* wait for encoder clocks to stabilize */
    usleep_range(1000, 2000);

A similar issue exists in tc358768_bridge_atomic_disable(), which directly
calls msleep(50):

tc358768_bridge_atomic_disable()
    /* wait at least for one frame */
    msleep(50);

Since the drm bridge atomic pre_enable and disable callbacks run in atomic
context during non-blocking commits, can these sleeping calls cause kernel
warnings or deadlocks?

>  
> +	/* Allow the PLL to settle */
> +	mdelay(20);
> +
>  	drm_display_mode_to_videomode(mode, &vm);
>  
>  	dsiclk = priv->dsiclk;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260625082507.57703-2-clamor95@gmail.com?part=1

Re: [PATCH v2 1/1] gpu/drm: bridge: tc358768: Add delay after PLL setup

[Luca Ceresoli]

Hello Svyatoslav,

On Thu Jun 25, 2026 at 10:25 AM CEST, Svyatoslav Ryhel wrote:
> After tc358768_setup_pll() enables PLL_CKEN and the lock indicator comes
> up, the DSI register sequence runs near immediately. On TF700T this

Do you refer to the Asus Transformer Pad TF700T here? Please add the full
name of the device.

> results in the bridge claiming PLL lock but producing no DSI video output:
> the panel powers up, the backlight comes on, but the framebuffer is never
> scanned out.
>
> Insert a small settling delay between PLL setup and the rest of the
> attach.
>
> Suggested-by: Michele Brocco <brocco@perceptos.de>
> Tested-by: Michele Brocco <brocco@perceptos.de> # TF700T
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/gpu/drm/bridge/tc358768.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c
> index 0f2820b37302..ea358c8da0e9 100644
> --- a/drivers/gpu/drm/bridge/tc358768.c
> +++ b/drivers/gpu/drm/bridge/tc358768.c
> @@ -824,6 +824,9 @@ static void tc358768_bridge_atomic_pre_enable(struct drm_bridge *bridge,
>  		return;
>  	}
>
> +	/* Allow the PLL to settle */
> +	mdelay(20);

Why 20 ms, and not another amount? Is it backed by some datasheet? Or just
"it's what fixed my usecase"?

The extra delay is a panel requirement maybe, and definitely specific to
the specific hardware pipeline of the TF700T. Would it make sense to add a
DT property so only hardware needing a delay can add it, and add as much as
needed?

Luca

--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v2 0/1] gpu/drm: bridge: tc358768: Add delay after PLL setup

[Svyatoslav Ryhel]

чт, 25 черв. 2026 р. о 11:25 Svyatoslav Ryhel <clamor95@gmail.com> пише:
>
> After tc358768_setup_pll() enables PLL_CKEN and the lock indicator comes
> up, the DSI register sequence runs near immediately. On TF700T this
> results in the bridge claiming PLL lock but producing no DSI video output:
> the panel powers up, the backlight comes on, but the framebuffer is never
> scanned out.
>
> Insert a small settling delay between PLL setup and the rest of the
> attach.
>
> ---
> - switched sleep() > delay() since *_pre_enable() is atomic
> ---
>
> Svyatoslav Ryhel (1):
>   gpu/drm: bridge: tc358768: Add delay after PLL setup
>
>  drivers/gpu/drm/bridge/tc358768.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> --
> 2.53.0
>

Hello there! If no one objects, may this patch be applied? It is quite
important for ASUS TF700T to work properly. Thank you!