* [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum [not found] <20220113145111.29984-1-jami.kettunen@somainline.org> @ 2022-01-13 14:51 ` Jami Kettunen 2022-02-09 1:49 ` Dmitry Baryshkov 2022-01-13 14:51 ` [PATCH 2/3] drm/msm/dpu1: Add MSM8998 to hw catalog Jami Kettunen 2022-01-13 14:51 ` [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu Jami Kettunen 2 siblings, 1 reply; 10+ messages in thread From: Jami Kettunen @ 2022-01-13 14:51 UTC (permalink / raw) To: linux-arm-msm Cc: Kalyan Thota, Jeffrey Hugo, Jami Kettunen, freedreno, Konrad Dybcio, Abhinav Kumar, dri-devel, linux-kernel, David Airlie, Martin Botka, ~postmarketos/upstreaming, AngeloGioacchino Del Regno, Dmitry Baryshkov, Marijn Suijten, Sean Paul, Krishna Manikandan From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> The enum dpu_clk_ctrl_type misses DPU_CLK_CTRL_DMA{2,3} even though this driver does actually handle both, if present: add the two in preparation for adding support for SoCs having them. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 31af04afda7d..736f52c742fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -435,6 +435,8 @@ enum dpu_clk_ctrl_type { DPU_CLK_CTRL_RGB3, DPU_CLK_CTRL_DMA0, DPU_CLK_CTRL_DMA1, + DPU_CLK_CTRL_DMA2, + DPU_CLK_CTRL_DMA3, DPU_CLK_CTRL_CURSOR0, DPU_CLK_CTRL_CURSOR1, DPU_CLK_CTRL_INLINE_ROT0_SSPP, -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum 2022-01-13 14:51 ` [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum Jami Kettunen @ 2022-02-09 1:49 ` Dmitry Baryshkov 0 siblings, 0 replies; 10+ messages in thread From: Dmitry Baryshkov @ 2022-02-09 1:49 UTC (permalink / raw) To: Jami Kettunen, linux-arm-msm Cc: Kalyan Thota, Jeffrey Hugo, David Airlie, freedreno, Konrad Dybcio, Abhinav Kumar, dri-devel, linux-kernel, Martin Botka, ~postmarketos/upstreaming, AngeloGioacchino Del Regno, Marijn Suijten, Sean Paul, Krishna Manikandan On 13/01/2022 17:51, Jami Kettunen wrote: > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > The enum dpu_clk_ctrl_type misses DPU_CLK_CTRL_DMA{2,3} even though > this driver does actually handle both, if present: add the two in > preparation for adding support for SoCs having them. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 31af04afda7d..736f52c742fb 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -435,6 +435,8 @@ enum dpu_clk_ctrl_type { > DPU_CLK_CTRL_RGB3, > DPU_CLK_CTRL_DMA0, > DPU_CLK_CTRL_DMA1, > + DPU_CLK_CTRL_DMA2, > + DPU_CLK_CTRL_DMA3, > DPU_CLK_CTRL_CURSOR0, > DPU_CLK_CTRL_CURSOR1, > DPU_CLK_CTRL_INLINE_ROT0_SSPP, -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] drm/msm/dpu1: Add MSM8998 to hw catalog [not found] <20220113145111.29984-1-jami.kettunen@somainline.org> 2022-01-13 14:51 ` [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum Jami Kettunen @ 2022-01-13 14:51 ` Jami Kettunen 2022-02-09 21:57 ` Dmitry Baryshkov 2022-01-13 14:51 ` [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu Jami Kettunen 2 siblings, 1 reply; 10+ messages in thread From: Jami Kettunen @ 2022-01-13 14:51 UTC (permalink / raw) To: linux-arm-msm Cc: Jeffrey Hugo, Yangtao Li, Konrad Dybcio, dri-devel, Bjorn Andersson, Krishna Manikandan, AngeloGioacchino Del Regno, Marijn Suijten, David Airlie, Abhinav Kumar, Stephen Boyd, Martin Botka, ~postmarketos/upstreaming, Sean Paul, Kalyan Thota, Jami Kettunen, linux-kernel, Robert Foss, Dmitry Baryshkov, freedreno From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Bringup functionality for MSM8998 in the DPU, driver which is mostly the same as SDM845 (just a few variations). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org> --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 329 +++++++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_drv.c | 1 + 3 files changed, 320 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index aa75991903a6..2b662da31255 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -16,6 +16,9 @@ BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) +#define VIG_MSM8998_MASK \ + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) + #define VIG_SDM845_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) @@ -25,6 +28,11 @@ #define VIG_SM8250_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) +#define DMA_MSM8998_MASK \ + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ + BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) + #define DMA_SDM845_MASK \ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ @@ -33,6 +41,9 @@ #define DMA_CURSOR_SDM845_MASK \ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) +#define DMA_CURSOR_MSM8998_MASK \ + (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) + #define MIXER_SDM845_MASK \ (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) @@ -49,6 +60,8 @@ #define MERGE_3D_SM8150_MASK (0) +#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) + #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) #define INTF_SDM845_MASK (0) @@ -181,6 +194,22 @@ static const uint32_t plane_formats_yuv[] = { * DPU sub blocks config *************************************************************/ /* DPU top level caps */ +static const struct dpu_caps msm8998_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0x7, + .qseed_type = DPU_SSPP_SCALER_QSEED3, + .smart_dma_rev = DPU_SSPP_SMART_DMA_V1, + .ubwc_version = DPU_HW_UBWC_VER_10, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + static const struct dpu_caps sdm845_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, @@ -251,6 +280,35 @@ static const struct dpu_caps sc7280_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; +static const struct dpu_mdp_cfg msm8998_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x458, + .features = 0, + .highest_bank_bit = 0x2, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { + .reg_off = 0x2AC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { + .reg_off = 0x2B4, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { + .reg_off = 0x2BC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { + .reg_off = 0x2C4, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { + .reg_off = 0x2AC, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { + .reg_off = 0x2B4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { + .reg_off = 0x2C4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { + .reg_off = 0x2C4, .bit_off = 12}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .reg_off = 0x3A8, .bit_off = 15}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .reg_off = 0x3B0, .bit_off = 15}, + }, +}; + static const struct dpu_mdp_cfg sdm845_mdp[] = { { .name = "top_0", .id = MDP_TOP, @@ -339,6 +397,39 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = { /************************************************************* * CTL sub blocks config *************************************************************/ +static const struct dpu_ctl_cfg msm8998_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x94, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x94, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x94, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, +}; + static const struct dpu_ctl_cfg sdm845_ctl[] = { { .name = "ctl_0", .id = CTL_0, @@ -497,6 +588,15 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { .virt_num_formats = ARRAY_SIZE(plane_formats), \ } +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = + _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3); +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = + _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3); +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = + _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3); +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = + _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3); + static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = @@ -523,6 +623,25 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); .clk_ctrl = _clkctrl \ } +static const struct dpu_sspp_cfg msm8998_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK, + msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK, + msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK, + msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK, + msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_MSM8998_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_MSM8998_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_MSM8998_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_MSM8998_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), +}; + static const struct dpu_sspp_cfg sdm845_sspp[] = { SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), @@ -599,17 +718,6 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { * MIXER sub blocks config *************************************************************/ -/* SDM845 */ - -static const struct dpu_lm_sub_blks sdm845_lm_sblk = { - .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .maxblendstages = 11, /* excluding base layer */ - .blendstage_base = { /* offsets relative to mixer base */ - 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, - 0xb0, 0xc8, 0xe0, 0xf8, 0x110 - }, -}; - #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \ { \ .name = _name, .id = _id, \ @@ -621,6 +729,43 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = { .dspp = _dspp \ } +/* MSM8998 */ + +static const struct dpu_lm_sub_blks msm8998_lm_sblk = { + .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .maxblendstages = 7, /* excluding base layer */ + .blendstage_base = { /* offsets relative to mixer base */ + 0x20, 0x50, 0x80, 0xb0, 0x230, + 0x260, 0x290 + }, +}; + +static const struct dpu_lm_cfg msm8998_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), +}; + +/* SDM845 */ + +static const struct dpu_lm_sub_blks sdm845_lm_sblk = { + .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .maxblendstages = 11, /* excluding base layer */ + .blendstage_base = { /* offsets relative to mixer base */ + 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, + 0xb0, 0xc8, 0xe0, 0xf8, 0x110 + }, +}; + static const struct dpu_lm_cfg sdm845_lm[] = { LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), @@ -682,6 +827,13 @@ static const struct dpu_lm_cfg sc7280_lm[] = { /************************************************************* * DSPP sub blocks config *************************************************************/ +static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { + .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, + .len = 0x90, .version = 0x10007}, + .gc = { .id = DPU_DSPP_GC, .base = 0x17c0, + .len = 0x90, .version = 0x10007}, +}; + static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x10000}, @@ -700,6 +852,13 @@ static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { .sblk = _sblk \ } +static const struct dpu_dspp_cfg msm8998_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, + &msm8998_dspp_sblk), + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK, + &msm8998_dspp_sblk), +}; + static const struct dpu_dspp_cfg sc7180_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, &sc7180_dspp_sblk), @@ -836,6 +995,13 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \ } +static const struct dpu_intf_cfg msm8998_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + static const struct dpu_intf_cfg sdm845_intf[] = { INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), @@ -865,9 +1031,55 @@ static const struct dpu_intf_cfg sc7280_intf[] = { * VBIF sub blocks config *************************************************************/ /* VBIF QOS remap */ +static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; +static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; +static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { + { + .pps = 1088 * 1920 * 30, + .ot_limit = 2, + }, + { + .pps = 1088 * 1920 * 60, + .ot_limit = 6, + }, + { + .pps = 3840 * 2160 * 30, + .ot_limit = 16, + }, +}; + +static const struct dpu_vbif_cfg msm8998_vbif[] = { + { + .name = "vbif_0", .id = VBIF_0, + .base = 0, .len = 0x1040, + .default_ot_rd_limit = 32, + .default_ot_wr_limit = 32, + .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), + .xin_halt_timeout = 0x4000, + .dynamic_ot_rd_tbl = { + .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), + .cfg = msm8998_ot_rdwr_cfg, + }, + .dynamic_ot_wr_tbl = { + .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), + .cfg = msm8998_ot_rdwr_cfg, + }, + .qos_rt_tbl = { + .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), + .priority_lvl = msm8998_rt_pri_lvl, + }, + .qos_nrt_tbl = { + .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), + .priority_lvl = msm8998_nrt_pri_lvl, + }, + .memtype_count = 14, + .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, + }, +}; + static const struct dpu_vbif_cfg sdm845_vbif[] = { { .name = "vbif_0", .id = VBIF_0, @@ -908,6 +1120,22 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { *************************************************************/ /* SSPP QOS LUTs */ +static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { + {.fl = 4, .lut = 0x1b}, + {.fl = 5, .lut = 0x5b}, + {.fl = 6, .lut = 0x15b}, + {.fl = 7, .lut = 0x55b}, + {.fl = 8, .lut = 0x155b}, + {.fl = 9, .lut = 0x555b}, + {.fl = 10, .lut = 0x1555b}, + {.fl = 11, .lut = 0x5555b}, + {.fl = 12, .lut = 0x15555b}, + {.fl = 13, .lut = 0x55555b}, + {.fl = 14, .lut = 0}, + {.fl = 1, .lut = 0x1b}, + {.fl = 0, .lut = 0} +}; + static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { {.fl = 4, .lut = 0x357}, {.fl = 5, .lut = 0x3357}, @@ -923,6 +1151,15 @@ static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { {.fl = 0, .lut = 0x11222222223357} }; +static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { + {.fl = 10, .lut = 0x1aaff}, + {.fl = 11, .lut = 0x5aaff}, + {.fl = 12, .lut = 0x15aaff}, + {.fl = 13, .lut = 0x55aaff}, + {.fl = 1, .lut = 0x1aaff}, + {.fl = 0, .lut = 0}, +}; + static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { {.fl = 0, .lut = 0x0011222222335777}, }; @@ -944,6 +1181,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { {.fl = 0, .lut = 0x0011223344556677}, }; +static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { + {.fl = 0, .lut = 0x0}, +}; + static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { {.fl = 0, .lut = 0x0}, }; @@ -952,6 +1193,42 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { {.fl = 0, .lut = 0x0}, }; +static const struct dpu_perf_cfg msm8998_perf_data = { + .max_bw_low = 6700000, + .max_bw_high = 6700000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .undersized_prefill_lines = 2, + .xtra_prefill_lines = 2, + .dest_scale_prefill_lines = 3, + .macrotile_prefill_lines = 4, + .yuv_nv12_prefill_lines = 8, + .linear_prefill_lines = 1, + .downscaling_prefill_lines = 1, + .amortizable_threshold = 25, + .min_prefill_lines = 25, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(msm8998_qos_linear), + .entries = msm8998_qos_linear + }, + {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), + .entries = msm8998_qos_macrotile + }, + {.nentry = ARRAY_SIZE(msm8998_qos_nrt), + .entries = msm8998_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 200, + .bw_inefficiency_factor = 120, +}; + static const struct dpu_perf_cfg sdm845_perf_data = { .max_bw_low = 6800000, .max_bw_high = 6800000, @@ -1106,6 +1383,34 @@ static const struct dpu_perf_cfg sc7280_perf_data = { * Hardware catalog init *************************************************************/ +/* + * msm8998_cfg_init(): populate sdm845 dpu sub-blocks reg offsets + * and instance counts. + */ +static void msm8998_cfg_init(struct dpu_mdss_cfg *dpu_cfg) +{ + *dpu_cfg = (struct dpu_mdss_cfg){ + .caps = &msm8998_dpu_caps, + .mdp_count = ARRAY_SIZE(msm8998_mdp), + .mdp = msm8998_mdp, + .ctl_count = ARRAY_SIZE(msm8998_ctl), + .ctl = msm8998_ctl, + .sspp_count = ARRAY_SIZE(msm8998_sspp), + .sspp = msm8998_sspp, + .mixer_count = ARRAY_SIZE(msm8998_lm), + .mixer = msm8998_lm, + .pingpong_count = ARRAY_SIZE(sdm845_pp), + .pingpong = sdm845_pp, + .intf_count = ARRAY_SIZE(msm8998_intf), + .intf = msm8998_intf, + .vbif_count = ARRAY_SIZE(msm8998_vbif), + .vbif = msm8998_vbif, + .reg_dma_count = 0, + .perf = msm8998_perf_data, + .mdss_irqs = IRQ_SM8250_MASK, + }; +} + /* * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets * and instance counts. @@ -1256,6 +1561,8 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) } static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { + { .hw_rev = DPU_HW_VER_300, .cfg_init = msm8998_cfg_init}, + { .hw_rev = DPU_HW_VER_301, .cfg_init = msm8998_cfg_init}, { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init}, { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init}, { .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init}, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 47fe11a84a77..83a19bfe5f9c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1348,6 +1348,7 @@ static const struct dev_pm_ops dpu_pm_ops = { }; const struct of_device_id dpu_dt_match[] = { + { .compatible = "qcom,msm8998-dpu", }, { .compatible = "qcom,sdm845-dpu", }, { .compatible = "qcom,sc7180-dpu", }, { .compatible = "qcom,sc7280-dpu", }, diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index ad35a5d94053..7c8a57a1c0d8 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -1438,6 +1438,7 @@ static void msm_pdev_shutdown(struct platform_device *pdev) static const struct of_device_id dt_match[] = { { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 }, { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, + { .compatible = "qcom,msm8998-mdss", .data = (void *)KMS_DPU }, { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU }, { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU }, { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU }, -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] drm/msm/dpu1: Add MSM8998 to hw catalog 2022-01-13 14:51 ` [PATCH 2/3] drm/msm/dpu1: Add MSM8998 to hw catalog Jami Kettunen @ 2022-02-09 21:57 ` Dmitry Baryshkov 0 siblings, 0 replies; 10+ messages in thread From: Dmitry Baryshkov @ 2022-02-09 21:57 UTC (permalink / raw) To: Jami Kettunen, linux-arm-msm Cc: Kalyan Thota, linux-kernel, Jeffrey Hugo, David Airlie, freedreno, dri-devel, Konrad Dybcio, Abhinav Kumar, Robert Foss, Stephen Boyd, Yangtao Li, Martin Botka, ~postmarketos/upstreaming, AngeloGioacchino Del Regno, Marijn Suijten, Bjorn Andersson, Sean Paul, Krishna Manikandan On 13/01/2022 17:51, Jami Kettunen wrote: > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > Bringup functionality for MSM8998 in the DPU, driver which is mostly > the same as SDM845 (just a few variations). > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 329 +++++++++++++++++- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > drivers/gpu/drm/msm/msm_drv.c | 1 + > 3 files changed, 320 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index aa75991903a6..2b662da31255 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -16,6 +16,9 @@ > BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\ > BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) > > +#define VIG_MSM8998_MASK \ > + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) > + > #define VIG_SDM845_MASK \ > (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) > > @@ -25,6 +28,11 @@ > #define VIG_SM8250_MASK \ > (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) > > +#define DMA_MSM8998_MASK \ > + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ > + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ > + BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) > + > #define DMA_SDM845_MASK \ > (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ > BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ > @@ -33,6 +41,9 @@ > #define DMA_CURSOR_SDM845_MASK \ > (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) > > +#define DMA_CURSOR_MSM8998_MASK \ > + (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) > + > #define MIXER_SDM845_MASK \ > (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) > > @@ -49,6 +60,8 @@ > > #define MERGE_3D_SM8150_MASK (0) > > +#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) > + > #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) > > #define INTF_SDM845_MASK (0) > @@ -181,6 +194,22 @@ static const uint32_t plane_formats_yuv[] = { > * DPU sub blocks config > *************************************************************/ > /* DPU top level caps */ > +static const struct dpu_caps msm8998_dpu_caps = { > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .max_mixer_blendstages = 0x7, > + .qseed_type = DPU_SSPP_SCALER_QSEED3, > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V1, > + .ubwc_version = DPU_HW_UBWC_VER_10, > + .has_src_split = true, > + .has_dim_layer = true, > + .has_idle_pc = true, > + .has_3d_merge = true, > + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > + .max_hdeci_exp = MAX_HORZ_DECIMATION, > + .max_vdeci_exp = MAX_VERT_DECIMATION, > +}; > + > static const struct dpu_caps sdm845_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0xb, > @@ -251,6 +280,35 @@ static const struct dpu_caps sc7280_dpu_caps = { > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > > +static const struct dpu_mdp_cfg msm8998_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x458, > + .features = 0, > + .highest_bank_bit = 0x2, > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { > + .reg_off = 0x2AC, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { > + .reg_off = 0x2B4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { > + .reg_off = 0x2BC, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { > + .reg_off = 0x2C4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > + .reg_off = 0x2AC, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > + .reg_off = 0x2B4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { > + .reg_off = 0x2C4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { > + .reg_off = 0x2C4, .bit_off = 12}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .reg_off = 0x3A8, .bit_off = 15}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .reg_off = 0x3B0, .bit_off = 15}, > + }, > +}; > + > static const struct dpu_mdp_cfg sdm845_mdp[] = { > { > .name = "top_0", .id = MDP_TOP, > @@ -339,6 +397,39 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = { > /************************************************************* > * CTL sub blocks config > *************************************************************/ > +static const struct dpu_ctl_cfg msm8998_ctl[] = { > + { > + .name = "ctl_0", .id = CTL_0, > + .base = 0x1000, .len = 0x94, > + .features = BIT(DPU_CTL_SPLIT_DISPLAY), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > + }, > + { > + .name = "ctl_1", .id = CTL_1, > + .base = 0x1200, .len = 0x94, > + .features = 0, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > + }, > + { > + .name = "ctl_2", .id = CTL_2, > + .base = 0x1400, .len = 0x94, > + .features = BIT(DPU_CTL_SPLIT_DISPLAY), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > + }, > + { > + .name = "ctl_3", .id = CTL_3, > + .base = 0x1600, .len = 0x94, > + .features = 0, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > + }, > + { > + .name = "ctl_4", .id = CTL_4, > + .base = 0x1800, .len = 0x94, > + .features = 0, > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > + }, > +}; > + > static const struct dpu_ctl_cfg sdm845_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > @@ -497,6 +588,15 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { > .virt_num_formats = ARRAY_SIZE(plane_formats), \ > } > > +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = > + _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3); > +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = > + _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3); > +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = > + _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3); > +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = > + _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3); > + > static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = > _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); > static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = > @@ -523,6 +623,25 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); > .clk_ctrl = _clkctrl \ > } > > +static const struct dpu_sspp_cfg msm8998_sspp[] = { > + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK, > + msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK, > + msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), > + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK, > + msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), > + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK, > + msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_MSM8998_MASK, > + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_MSM8998_MASK, > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_MSM8998_MASK, > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_MSM8998_MASK, > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > +}; > + > static const struct dpu_sspp_cfg sdm845_sspp[] = { > SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, > sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > @@ -599,17 +718,6 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { > * MIXER sub blocks config > *************************************************************/ > > -/* SDM845 */ > - > -static const struct dpu_lm_sub_blks sdm845_lm_sblk = { > - .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > - .maxblendstages = 11, /* excluding base layer */ > - .blendstage_base = { /* offsets relative to mixer base */ > - 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, > - 0xb0, 0xc8, 0xe0, 0xf8, 0x110 > - }, > -}; > - > #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \ > { \ > .name = _name, .id = _id, \ > @@ -621,6 +729,43 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = { > .dspp = _dspp \ > } > > +/* MSM8998 */ > + > +static const struct dpu_lm_sub_blks msm8998_lm_sblk = { > + .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .maxblendstages = 7, /* excluding base layer */ > + .blendstage_base = { /* offsets relative to mixer base */ > + 0x20, 0x50, 0x80, 0xb0, 0x230, > + 0x260, 0x290 > + }, > +}; > + > +static const struct dpu_lm_cfg msm8998_lm[] = { > + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, > + &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), > + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, > + &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), > + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, > + &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), > + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, > + &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), > + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, > + &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), > + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, > + &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), > +}; > + > +/* SDM845 */ > + > +static const struct dpu_lm_sub_blks sdm845_lm_sblk = { > + .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .maxblendstages = 11, /* excluding base layer */ > + .blendstage_base = { /* offsets relative to mixer base */ > + 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, > + 0xb0, 0xc8, 0xe0, 0xf8, 0x110 > + }, > +}; > + > static const struct dpu_lm_cfg sdm845_lm[] = { > LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, > &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), > @@ -682,6 +827,13 @@ static const struct dpu_lm_cfg sc7280_lm[] = { > /************************************************************* > * DSPP sub blocks config > *************************************************************/ > +static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { > + .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, > + .len = 0x90, .version = 0x10007}, > + .gc = { .id = DPU_DSPP_GC, .base = 0x17c0, > + .len = 0x90, .version = 0x10007}, > +}; > + > static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { > .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, > .len = 0x90, .version = 0x10000}, > @@ -700,6 +852,13 @@ static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { > .sblk = _sblk \ > } > > +static const struct dpu_dspp_cfg msm8998_dspp[] = { > + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, > + &msm8998_dspp_sblk), > + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK, > + &msm8998_dspp_sblk), > +}; > + > static const struct dpu_dspp_cfg sc7180_dspp[] = { > DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, > &sc7180_dspp_sblk), > @@ -836,6 +995,13 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { > .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \ > } > > +static const struct dpu_intf_cfg msm8998_intf[] = { > + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), > + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), > +}; > + > static const struct dpu_intf_cfg sdm845_intf[] = { > INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > @@ -865,9 +1031,55 @@ static const struct dpu_intf_cfg sc7280_intf[] = { > * VBIF sub blocks config > *************************************************************/ > /* VBIF QOS remap */ > +static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; > +static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; > static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; > static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; > > +static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { > + { > + .pps = 1088 * 1920 * 30, > + .ot_limit = 2, > + }, > + { > + .pps = 1088 * 1920 * 60, > + .ot_limit = 6, > + }, > + { > + .pps = 3840 * 2160 * 30, > + .ot_limit = 16, > + }, > +}; > + > +static const struct dpu_vbif_cfg msm8998_vbif[] = { > + { > + .name = "vbif_0", .id = VBIF_0, > + .base = 0, .len = 0x1040, > + .default_ot_rd_limit = 32, > + .default_ot_wr_limit = 32, > + .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), > + .xin_halt_timeout = 0x4000, > + .dynamic_ot_rd_tbl = { > + .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), > + .cfg = msm8998_ot_rdwr_cfg, > + }, > + .dynamic_ot_wr_tbl = { > + .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), > + .cfg = msm8998_ot_rdwr_cfg, > + }, > + .qos_rt_tbl = { > + .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), > + .priority_lvl = msm8998_rt_pri_lvl, > + }, > + .qos_nrt_tbl = { > + .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), > + .priority_lvl = msm8998_nrt_pri_lvl, > + }, > + .memtype_count = 14, > + .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, > + }, > +}; > + > static const struct dpu_vbif_cfg sdm845_vbif[] = { > { > .name = "vbif_0", .id = VBIF_0, > @@ -908,6 +1120,22 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { > *************************************************************/ > > /* SSPP QOS LUTs */ > +static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { > + {.fl = 4, .lut = 0x1b}, > + {.fl = 5, .lut = 0x5b}, > + {.fl = 6, .lut = 0x15b}, > + {.fl = 7, .lut = 0x55b}, > + {.fl = 8, .lut = 0x155b}, > + {.fl = 9, .lut = 0x555b}, > + {.fl = 10, .lut = 0x1555b}, > + {.fl = 11, .lut = 0x5555b}, > + {.fl = 12, .lut = 0x15555b}, > + {.fl = 13, .lut = 0x55555b}, > + {.fl = 14, .lut = 0}, > + {.fl = 1, .lut = 0x1b}, > + {.fl = 0, .lut = 0} > +}; > + > static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { > {.fl = 4, .lut = 0x357}, > {.fl = 5, .lut = 0x3357}, > @@ -923,6 +1151,15 @@ static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { > {.fl = 0, .lut = 0x11222222223357} > }; > > +static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { > + {.fl = 10, .lut = 0x1aaff}, > + {.fl = 11, .lut = 0x5aaff}, > + {.fl = 12, .lut = 0x15aaff}, > + {.fl = 13, .lut = 0x55aaff}, > + {.fl = 1, .lut = 0x1aaff}, > + {.fl = 0, .lut = 0}, > +}; > + > static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { > {.fl = 0, .lut = 0x0011222222335777}, > }; > @@ -944,6 +1181,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { > {.fl = 0, .lut = 0x0011223344556677}, > }; > > +static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { > + {.fl = 0, .lut = 0x0}, > +}; > + > static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { > {.fl = 0, .lut = 0x0}, > }; > @@ -952,6 +1193,42 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { > {.fl = 0, .lut = 0x0}, > }; > > +static const struct dpu_perf_cfg msm8998_perf_data = { > + .max_bw_low = 6700000, > + .max_bw_high = 6700000, > + .min_core_ib = 2400000, > + .min_llcc_ib = 800000, > + .min_dram_ib = 800000, > + .undersized_prefill_lines = 2, > + .xtra_prefill_lines = 2, > + .dest_scale_prefill_lines = 3, > + .macrotile_prefill_lines = 4, > + .yuv_nv12_prefill_lines = 8, > + .linear_prefill_lines = 1, > + .downscaling_prefill_lines = 1, > + .amortizable_threshold = 25, > + .min_prefill_lines = 25, > + .danger_lut_tbl = {0xf, 0xffff, 0x0}, > + .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, > + .qos_lut_tbl = { > + {.nentry = ARRAY_SIZE(msm8998_qos_linear), > + .entries = msm8998_qos_linear > + }, > + {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), > + .entries = msm8998_qos_macrotile > + }, > + {.nentry = ARRAY_SIZE(msm8998_qos_nrt), > + .entries = msm8998_qos_nrt > + }, > + }, > + .cdp_cfg = { > + {.rd_enable = 1, .wr_enable = 1}, > + {.rd_enable = 1, .wr_enable = 0} > + }, > + .clk_inefficiency_factor = 200, > + .bw_inefficiency_factor = 120, > +}; > + > static const struct dpu_perf_cfg sdm845_perf_data = { > .max_bw_low = 6800000, > .max_bw_high = 6800000, > @@ -1106,6 +1383,34 @@ static const struct dpu_perf_cfg sc7280_perf_data = { > * Hardware catalog init > *************************************************************/ > > +/* > + * msm8998_cfg_init(): populate sdm845 dpu sub-blocks reg offsets > + * and instance counts. > + */ > +static void msm8998_cfg_init(struct dpu_mdss_cfg *dpu_cfg) > +{ > + *dpu_cfg = (struct dpu_mdss_cfg){ > + .caps = &msm8998_dpu_caps, > + .mdp_count = ARRAY_SIZE(msm8998_mdp), > + .mdp = msm8998_mdp, > + .ctl_count = ARRAY_SIZE(msm8998_ctl), > + .ctl = msm8998_ctl, > + .sspp_count = ARRAY_SIZE(msm8998_sspp), > + .sspp = msm8998_sspp, > + .mixer_count = ARRAY_SIZE(msm8998_lm), > + .mixer = msm8998_lm, > + .pingpong_count = ARRAY_SIZE(sdm845_pp), > + .pingpong = sdm845_pp, > + .intf_count = ARRAY_SIZE(msm8998_intf), > + .intf = msm8998_intf, > + .vbif_count = ARRAY_SIZE(msm8998_vbif), > + .vbif = msm8998_vbif, > + .reg_dma_count = 0, > + .perf = msm8998_perf_data, > + .mdss_irqs = IRQ_SM8250_MASK, > + }; > +} > + > /* > * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets > * and instance counts. > @@ -1256,6 +1561,8 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) > } > > static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { > + { .hw_rev = DPU_HW_VER_300, .cfg_init = msm8998_cfg_init}, > + { .hw_rev = DPU_HW_VER_301, .cfg_init = msm8998_cfg_init}, > { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init}, > { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init}, > { .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init}, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index 47fe11a84a77..83a19bfe5f9c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -1348,6 +1348,7 @@ static const struct dev_pm_ops dpu_pm_ops = { > }; > > const struct of_device_id dpu_dt_match[] = { > + { .compatible = "qcom,msm8998-dpu", }, > { .compatible = "qcom,sdm845-dpu", }, > { .compatible = "qcom,sc7180-dpu", }, > { .compatible = "qcom,sc7280-dpu", }, > diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c > index ad35a5d94053..7c8a57a1c0d8 100644 > --- a/drivers/gpu/drm/msm/msm_drv.c > +++ b/drivers/gpu/drm/msm/msm_drv.c > @@ -1438,6 +1438,7 @@ static void msm_pdev_shutdown(struct platform_device *pdev) > static const struct of_device_id dt_match[] = { > { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 }, > { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, > + { .compatible = "qcom,msm8998-mdss", .data = (void *)KMS_DPU }, > { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU }, > { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU }, > { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU }, -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu [not found] <20220113145111.29984-1-jami.kettunen@somainline.org> 2022-01-13 14:51 ` [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum Jami Kettunen 2022-01-13 14:51 ` [PATCH 2/3] drm/msm/dpu1: Add MSM8998 to hw catalog Jami Kettunen @ 2022-01-13 14:51 ` Jami Kettunen 2022-02-09 2:23 ` Rob Herring 2 siblings, 1 reply; 10+ messages in thread From: Jami Kettunen @ 2022-01-13 14:51 UTC (permalink / raw) To: linux-arm-msm Cc: devicetree, Jeffrey Hugo, Jami Kettunen, freedreno, Konrad Dybcio, Abhinav Kumar, dri-devel, linux-kernel, David Airlie, Rob Herring, Martin Botka, ~postmarketos/upstreaming, AngeloGioacchino Del Regno, Marijn Suijten, Sean Paul From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Add yaml binding for msm8998 dpu1 support. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org> --- .../bindings/display/msm/dpu-msm8998.yaml | 219 ++++++++++++++++++ 1 file changed, 219 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml new file mode 100644 index 000000000000..167bc48748d7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for MSM8998 target + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> + +description: | + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for MSM8998 target. + +properties: + compatible: + items: + - const: qcom,msm8998-mdss + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Display AHB clock + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#address-cells": true + + "#size-cells": true + + "#interrupt-cells": + const: 1 + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + + ranges: true + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,msm8998-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for regdma register set + - description: Address offset and size for vbif register set + - description: Address offset and size for non-realtime vbif register set + + reg-names: + items: + - const: mdp + - const: regdma + - const: vbif + - const: vbif_nrt + + clocks: + items: + - description: Display ahb clock + - description: Display axi clock + - description: Display mem-noc clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: mnoc + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + operating-points-v2: true + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF2 (DSI2) + + required: + - port@0 + - port@1 + + required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,mmcc-msm8998.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@c900000 { + compatible = "qcom,msm8998-mdss"; + reg = <0x0c900000 0x1000>; + reg-names = "mdss"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + #address-cells = <1>; + #interrupt-cells = <1>; + #size-cells = <1>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + iommus = <&mmss_smmu 0>; + + power-domains = <&mmcc MDSS_GDSC>; + ranges; + + display-controller@c901000 { + compatible = "qcom,msm8998-dpu"; + reg = <0x0c901000 0x8f000>, + <0x0c9a8e00 0xf0>, + <0x0c9b0000 0x2008>, + <0x0c9b8000 0x1040>; + reg-names = "mdp", "regdma", "vbif", "vbif_nrt"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "mnoc", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd MSM8998_VDDMX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + }; +... -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu 2022-01-13 14:51 ` [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu Jami Kettunen @ 2022-02-09 2:23 ` Rob Herring 0 siblings, 0 replies; 10+ messages in thread From: Rob Herring @ 2022-02-09 2:23 UTC (permalink / raw) To: Jami Kettunen Cc: Sean Paul, devicetree, Jeffrey Hugo, David Airlie, linux-arm-msm, Konrad Dybcio, Abhinav Kumar, dri-devel, linux-kernel, Rob Herring, Martin Botka, ~postmarketos/upstreaming, AngeloGioacchino Del Regno, Marijn Suijten, freedreno On Thu, 13 Jan 2022 16:51:11 +0200, Jami Kettunen wrote: > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > Add yaml binding for msm8998 dpu1 support. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org> > --- > .../bindings/display/msm/dpu-msm8998.yaml | 219 ++++++++++++++++++ > 1 file changed, 219 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum
@ 2021-09-01 18:11 AngeloGioacchino Del Regno
2021-09-01 18:11 ` [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu AngeloGioacchino Del Regno
0 siblings, 1 reply; 10+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-09-01 18:11 UTC (permalink / raw)
To: robdclark
Cc: sean, airlied, daniel, dmitry.baryshkov, abhinavk, robh+dt,
linux-arm-msm, dri-devel, freedreno, linux-kernel, konrad.dybcio,
marijn.suijten, martin.botka, ~postmarketos/upstreaming,
phone-devel, paul.bouchara, devicetree,
AngeloGioacchino Del Regno
The enum dpu_clk_ctrl_type misses DPU_CLK_CTRL_DMA{2,3} even though
this driver does actually handle both, if present: add the two in
preparation for adding support for SoCs having them.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index d2a945a27cfa..059e1402b7d0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -432,6 +432,8 @@ enum dpu_clk_ctrl_type {
DPU_CLK_CTRL_RGB3,
DPU_CLK_CTRL_DMA0,
DPU_CLK_CTRL_DMA1,
+ DPU_CLK_CTRL_DMA2,
+ DPU_CLK_CTRL_DMA3,
DPU_CLK_CTRL_CURSOR0,
DPU_CLK_CTRL_CURSOR1,
DPU_CLK_CTRL_INLINE_ROT0_SSPP,
--
2.32.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu 2021-09-01 18:11 [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum AngeloGioacchino Del Regno @ 2021-09-01 18:11 ` AngeloGioacchino Del Regno 2021-09-07 18:37 ` Rob Herring 0 siblings, 1 reply; 10+ messages in thread From: AngeloGioacchino Del Regno @ 2021-09-01 18:11 UTC (permalink / raw) To: robdclark Cc: sean, airlied, daniel, dmitry.baryshkov, abhinavk, robh+dt, linux-arm-msm, dri-devel, freedreno, linux-kernel, konrad.dybcio, marijn.suijten, martin.botka, ~postmarketos/upstreaming, phone-devel, paul.bouchara, devicetree, AngeloGioacchino Del Regno Add yaml binding for msm8998 dpu1 support. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> --- .../bindings/display/msm/dpu-msm8998.yaml | 220 ++++++++++++++++++ 1 file changed, 220 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml new file mode 100644 index 000000000000..db435342ecbf --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -0,0 +1,220 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for MSM8998 target + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> + +description: | + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for MSM8998 target. + +properties: + compatible: + items: + - const: qcom,msm8998-mdss + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Display AHB clock + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#address-cells": true + + "#size-cells": true + + "#interrupt-cells": + const: 1 + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + + ranges: true + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,msm8998-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for regdma register set + - description: Address offset and size for vbif register set + - description: Address offset and size for non-realtime vbif register set + + reg-names: + items: + - const: mdp + - const: regdma + - const: vbif + - const: vbif_nrt + + clocks: + items: + - description: Display ahb clock + - description: Display axi clock + - description: Display mem-noc clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: mnoc + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + operating-points-v2: true + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF2 (DSI2) + + required: + - port@0 + - port@1 + + required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,mmcc-msm8998.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@c900000 { + compatible = "qcom,msm8998-mdss"; + reg = <0x0c900000 0x1000>; + reg-names = "mdss"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + #address-cells = <1>; + #interrupt-cells = <1>; + #size-cells = <1>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + iommus = <&mmss_smmu 0>; + + power-domains = <&mmcc MDSS_GDSC>; + ranges; + status = "disabled"; + + display-controller@c901000 { + compatible = "qcom,msm8998-dpu"; + reg = <0x0c901000 0x8f000>, + <0x0c9a8e00 0xf0>, + <0x0c9b0000 0x2008>, + <0x0c9b8000 0x1040>; + reg-names = "mdp", "regdma", "vbif", "vbif_nrt"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "mnoc", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd MSM8998_VDDMX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + }; +... -- 2.32.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu 2021-09-01 18:11 ` [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu AngeloGioacchino Del Regno @ 2021-09-07 18:37 ` Rob Herring 2021-11-25 11:53 ` Dmitry Baryshkov 0 siblings, 1 reply; 10+ messages in thread From: Rob Herring @ 2021-09-07 18:37 UTC (permalink / raw) To: AngeloGioacchino Del Regno Cc: robdclark, sean, airlied, daniel, dmitry.baryshkov, abhinavk, linux-arm-msm, dri-devel, freedreno, linux-kernel, konrad.dybcio, marijn.suijten, martin.botka, ~postmarketos/upstreaming, phone-devel, paul.bouchara, devicetree On Wed, Sep 01, 2021 at 08:11:38PM +0200, AngeloGioacchino Del Regno wrote: > Add yaml binding for msm8998 dpu1 support. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > --- > .../bindings/display/msm/dpu-msm8998.yaml | 220 ++++++++++++++++++ > 1 file changed, 220 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml > > diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml > new file mode 100644 > index 000000000000..db435342ecbf > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml > @@ -0,0 +1,220 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display DPU dt properties for MSM8998 target > + > +maintainers: > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > + > +description: | > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates > + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree > + bindings of MDSS and DPU are mentioned for MSM8998 target. > + > +properties: > + compatible: > + items: > + - const: qcom,msm8998-mdss > + > + reg: > + maxItems: 1 > + > + reg-names: > + const: mdss > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Display AHB clock > + - description: Display AXI clock > + - description: Display core clock > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: core > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true > + > + "#address-cells": true > + > + "#size-cells": true > + > + "#interrupt-cells": > + const: 1 > + > + iommus: > + items: > + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 > + > + ranges: true > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + description: Node containing the properties of DPU. > + > + properties: > + compatible: > + items: > + - const: qcom,msm8998-dpu > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for regdma register set > + - description: Address offset and size for vbif register set > + - description: Address offset and size for non-realtime vbif register set > + > + reg-names: > + items: > + - const: mdp > + - const: regdma > + - const: vbif > + - const: vbif_nrt > + > + clocks: > + items: > + - description: Display ahb clock > + - description: Display axi clock > + - description: Display mem-noc clock > + - description: Display core clock > + - description: Display vsync clock > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: mnoc > + - const: core > + - const: vsync > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + operating-points-v2: true > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + description: | > + Contains the list of output ports from DPU device. These ports > + connect to interfaces that are external to the DPU hardware, > + such as DSI, DP etc. Each output port contains an endpoint that > + describes how it is connected to an external interface. > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: DPU_INTF1 (DSI1) > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: DPU_INTF2 (DSI2) > + > + required: > + - port@0 > + - port@1 > + > + required: > + - compatible > + - reg > + - reg-names > + - clocks > + - interrupts > + - power-domains > + - operating-points-v2 > + - ports > + > +required: > + - compatible > + - reg > + - reg-names > + - power-domains > + - clocks > + - interrupts > + - interrupt-controller > + - iommus > + - ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,mmcc-msm8998.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-subsystem@c900000 { > + compatible = "qcom,msm8998-mdss"; > + reg = <0x0c900000 0x1000>; > + reg-names = "mdss"; > + > + clocks = <&mmcc MDSS_AHB_CLK>, > + <&mmcc MDSS_AXI_CLK>, > + <&mmcc MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "core"; > + > + #address-cells = <1>; > + #interrupt-cells = <1>; > + #size-cells = <1>; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + iommus = <&mmss_smmu 0>; > + > + power-domains = <&mmcc MDSS_GDSC>; > + ranges; > + status = "disabled"; Drop. Why disable an example? > + > + display-controller@c901000 { > + compatible = "qcom,msm8998-dpu"; > + reg = <0x0c901000 0x8f000>, > + <0x0c9a8e00 0xf0>, > + <0x0c9b0000 0x2008>, > + <0x0c9b8000 0x1040>; > + reg-names = "mdp", "regdma", "vbif", "vbif_nrt"; > + > + clocks = <&mmcc MDSS_AHB_CLK>, > + <&mmcc MDSS_AXI_CLK>, > + <&mmcc MNOC_AHB_CLK>, > + <&mmcc MDSS_MDP_CLK>, > + <&mmcc MDSS_VSYNC_CLK>; > + clock-names = "iface", "bus", "mnoc", "core", "vsync"; > + > + interrupt-parent = <&mdss>; > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmpd MSM8998_VDDMX>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpu_intf2_out: endpoint { > + remote-endpoint = <&dsi1_in>; > + }; > + }; > + }; > + }; > + }; > +... > -- > 2.32.0 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu 2021-09-07 18:37 ` Rob Herring @ 2021-11-25 11:53 ` Dmitry Baryshkov 2021-11-25 15:26 ` AngeloGioacchino Del Regno 0 siblings, 1 reply; 10+ messages in thread From: Dmitry Baryshkov @ 2021-11-25 11:53 UTC (permalink / raw) To: Rob Herring, AngeloGioacchino Del Regno Cc: freedreno, devicetree, airlied, linux-arm-msm, konrad.dybcio, linux-kernel, abhinavk, paul.bouchara, martin.botka, dri-devel, marijn.suijten, phone-devel, sean, ~postmarketos/upstreaming On 07/09/2021 21:37, Rob Herring wrote: > On Wed, Sep 01, 2021 at 08:11:38PM +0200, AngeloGioacchino Del Regno wrote: >> Add yaml binding for msm8998 dpu1 support. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> >> --- >> .../bindings/display/msm/dpu-msm8998.yaml | 220 ++++++++++++++++++ >> 1 file changed, 220 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml >> >> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml >> new file mode 100644 >> index 000000000000..db435342ecbf >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml >> @@ -0,0 +1,220 @@ >> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Display DPU dt properties for MSM8998 target >> + >> +maintainers: >> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> >> + >> +description: | >> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates >> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree >> + bindings of MDSS and DPU are mentioned for MSM8998 target. >> + >> +properties: >> + compatible: >> + items: >> + - const: qcom,msm8998-mdss >> + >> + reg: >> + maxItems: 1 >> + >> + reg-names: >> + const: mdss >> + >> + power-domains: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Display AHB clock >> + - description: Display AXI clock >> + - description: Display core clock >> + >> + clock-names: >> + items: >> + - const: iface >> + - const: bus >> + - const: core >> + >> + interrupts: >> + maxItems: 1 >> + >> + interrupt-controller: true >> + >> + "#address-cells": true >> + >> + "#size-cells": true >> + >> + "#interrupt-cells": >> + const: 1 >> + >> + iommus: >> + items: >> + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 >> + >> + ranges: true >> + >> +patternProperties: >> + "^display-controller@[0-9a-f]+$": >> + type: object >> + description: Node containing the properties of DPU. >> + >> + properties: >> + compatible: >> + items: >> + - const: qcom,msm8998-dpu >> + >> + reg: >> + items: >> + - description: Address offset and size for mdp register set >> + - description: Address offset and size for regdma register set >> + - description: Address offset and size for vbif register set >> + - description: Address offset and size for non-realtime vbif register set >> + >> + reg-names: >> + items: >> + - const: mdp >> + - const: regdma >> + - const: vbif >> + - const: vbif_nrt >> + >> + clocks: >> + items: >> + - description: Display ahb clock >> + - description: Display axi clock >> + - description: Display mem-noc clock >> + - description: Display core clock >> + - description: Display vsync clock >> + >> + clock-names: >> + items: >> + - const: iface >> + - const: bus >> + - const: mnoc >> + - const: core >> + - const: vsync >> + >> + interrupts: >> + maxItems: 1 >> + >> + power-domains: >> + maxItems: 1 >> + >> + operating-points-v2: true >> + ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + description: | >> + Contains the list of output ports from DPU device. These ports >> + connect to interfaces that are external to the DPU hardware, >> + such as DSI, DP etc. Each output port contains an endpoint that >> + describes how it is connected to an external interface. >> + >> + properties: >> + port@0: >> + $ref: /schemas/graph.yaml#/properties/port >> + description: DPU_INTF1 (DSI1) >> + >> + port@1: >> + $ref: /schemas/graph.yaml#/properties/port >> + description: DPU_INTF2 (DSI2) >> + >> + required: >> + - port@0 >> + - port@1 >> + >> + required: >> + - compatible >> + - reg >> + - reg-names >> + - clocks >> + - interrupts >> + - power-domains >> + - operating-points-v2 >> + - ports >> + >> +required: >> + - compatible >> + - reg >> + - reg-names >> + - power-domains >> + - clocks >> + - interrupts >> + - interrupt-controller >> + - iommus >> + - ranges >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/qcom,mmcc-msm8998.h> >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + #include <dt-bindings/power/qcom-rpmpd.h> >> + >> + display-subsystem@c900000 { >> + compatible = "qcom,msm8998-mdss"; >> + reg = <0x0c900000 0x1000>; >> + reg-names = "mdss"; >> + >> + clocks = <&mmcc MDSS_AHB_CLK>, >> + <&mmcc MDSS_AXI_CLK>, >> + <&mmcc MDSS_MDP_CLK>; >> + clock-names = "iface", "bus", "core"; >> + >> + #address-cells = <1>; >> + #interrupt-cells = <1>; >> + #size-cells = <1>; >> + >> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-controller; >> + iommus = <&mmss_smmu 0>; >> + >> + power-domains = <&mmcc MDSS_GDSC>; >> + ranges; >> + status = "disabled"; > > Drop. Why disable an example? AngeloGioacchino, could you please update and repost this patch series? I'd like to get it merged. > >> + >> + display-controller@c901000 { >> + compatible = "qcom,msm8998-dpu"; >> + reg = <0x0c901000 0x8f000>, >> + <0x0c9a8e00 0xf0>, >> + <0x0c9b0000 0x2008>, >> + <0x0c9b8000 0x1040>; >> + reg-names = "mdp", "regdma", "vbif", "vbif_nrt"; >> + >> + clocks = <&mmcc MDSS_AHB_CLK>, >> + <&mmcc MDSS_AXI_CLK>, >> + <&mmcc MNOC_AHB_CLK>, >> + <&mmcc MDSS_MDP_CLK>, >> + <&mmcc MDSS_VSYNC_CLK>; >> + clock-names = "iface", "bus", "mnoc", "core", "vsync"; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; >> + operating-points-v2 = <&mdp_opp_table>; >> + power-domains = <&rpmpd MSM8998_VDDMX>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + dpu_intf1_out: endpoint { >> + remote-endpoint = <&dsi0_in>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + dpu_intf2_out: endpoint { >> + remote-endpoint = <&dsi1_in>; >> + }; >> + }; >> + }; >> + }; >> + }; >> +... >> -- >> 2.32.0 >> >> -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu 2021-11-25 11:53 ` Dmitry Baryshkov @ 2021-11-25 15:26 ` AngeloGioacchino Del Regno 0 siblings, 0 replies; 10+ messages in thread From: AngeloGioacchino Del Regno @ 2021-11-25 15:26 UTC (permalink / raw) To: Dmitry Baryshkov, Rob Herring Cc: freedreno, devicetree, airlied, linux-arm-msm, konrad.dybcio, linux-kernel, abhinavk, paul.bouchara, martin.botka, dri-devel, marijn.suijten, phone-devel, sean, ~postmarketos/upstreaming Il 25/11/21 12:53, Dmitry Baryshkov ha scritto: > On 07/09/2021 21:37, Rob Herring wrote: >> On Wed, Sep 01, 2021 at 08:11:38PM +0200, AngeloGioacchino Del Regno wrote: >>> Add yaml binding for msm8998 dpu1 support. >>> >>> Signed-off-by: AngeloGioacchino Del Regno >>> <angelogioacchino.delregno@somainline.org> >>> --- >>> .../bindings/display/msm/dpu-msm8998.yaml | 220 ++++++++++++++++++ >>> 1 file changed, 220 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml >>> b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml >>> new file mode 100644 >>> index 000000000000..db435342ecbf >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml >>> @@ -0,0 +1,220 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >>> +%YAML 1.2 >>> +--- <snip> >>> + >>> + power-domains = <&mmcc MDSS_GDSC>; >>> + ranges; >>> + status = "disabled"; >> >> Drop. Why disable an example? > > AngeloGioacchino, could you please update and repost this patch series? I'd like to > get it merged. > Hey Dmitry, Sure I can! Will update/rebase/fix as soon as I find some spare time around. Thanks, - Angelo ^ permalink raw reply [flat|nested] 10+ messages in thread
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2022-01-13 14:51 ` [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum Jami Kettunen
2022-02-09 1:49 ` Dmitry Baryshkov
2022-01-13 14:51 ` [PATCH 2/3] drm/msm/dpu1: Add MSM8998 to hw catalog Jami Kettunen
2022-02-09 21:57 ` Dmitry Baryshkov
2022-01-13 14:51 ` [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu Jami Kettunen
2022-02-09 2:23 ` Rob Herring
2021-09-01 18:11 [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum AngeloGioacchino Del Regno
2021-09-01 18:11 ` [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu AngeloGioacchino Del Regno
2021-09-07 18:37 ` Rob Herring
2021-11-25 11:53 ` Dmitry Baryshkov
2021-11-25 15:26 ` AngeloGioacchino Del Regno
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