[PATCH 0/2] Prune unsupported modes as per HDMI2.1 spec

[PATCH 0/2] Prune unsupported modes as per HDMI2.1 spec

[Ankit Nautiyal]

Modes like 4K100, 4K120, 8K50, 8K60 need FRL and/or DSC from source.
Since FRL and DSC are not currently supported natively by intel
platforms (are supported only via DP-HDMI2.1 PCONs), these modes must
be pruned as per spec.
Currently these modes are not getting pruned as we check the TMDS clock,
which passes some of these with YCbCr420 format and with lower bpc.
This causes failures during compliance test (e.g. HFR1-67).

This patch prunes the modes, if FRL, DSC not supported, or the support
requirement not met as per the spec.
Although the spec mentions 4K100, 4K120, 8K50, and 8K60 video timings,
I have used the check for clock >= 2376 MHz (or 1188 MHz with 420
format), instead of using individual VICs.

While at it, fix a bug while parsing the compressed bpc supported
from edid.

Ankit Nautiyal (2):
  drm/edid: Fix minimum bpc supported with DSC1.2 for HDMI sink
  drm/i915/hdmi: Prune unsupported modes as per HDMI2.1 spec

 drivers/gpu/drm/drm_edid.c                |  3 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c | 48 +++++++++++++++++++++++
 2 files changed, 50 insertions(+), 1 deletion(-)

-- 
2.25.1

[PATCH 1/2] drm/edid: Fix minimum bpc supported with DSC1.2 for HDMI sink

[Ankit Nautiyal]

HF-VSDB/SCDB has bits to advertise support for 16, 12 and 10 bpc.
If none of the bits are set, the minimum bpc supported with DSC is 8.

This patch corrects the min bpc supported to be 8, instead of 0.

Fixes: 76ee7b905678 ("drm/edid: Parse DSC1.2 cap fields from HFVSDB block")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/drm_edid.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 47d121e99201..ce5e23897c9e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5288,7 +5288,8 @@ static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
 			else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
 				hdmi_dsc->bpc_supported = 10;
 			else
-				hdmi_dsc->bpc_supported = 0;
+				/* Supports min 8 BPC if DSC1.2 is supported*/
+				hdmi_dsc->bpc_supported = 8;
 
 			dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
 			drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
-- 
2.25.1

[PATCH 2/2] drm/i915/hdmi: Prune unsupported modes as per HDMI2.1 spec

[Ankit Nautiyal]

As per Sec 7.8.1 of HDMI2.1 spec, sources that support modes:
4K100, 4K120, 8K50, 8K60 must support these modes in at least one of
the below formats:
i) uncompressed FRL, 420 format and min of 10 bpc, or
ii) compressed FRL, 444 format and min of 10 bpc.

Since FRL and DSC are not supported natively with HDMI, the above
modes must be pruned as per the spec, and is a requirement for the
HDMI2.1 compliance test.

This patch adds a condition to check for the modes with clock
requirement more than 2376 MHz (1188 MHz with 420 format),
and prune them if none of the above two formats are supported.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 48 +++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 1ae09431f53a..2ee1262f6427 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1940,6 +1940,44 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
 	}
 }
 
+/*
+ * HDMI2.1 Sec7.8.1
+ * Support requirement for 4K100, 4K120, 8K50, and 8K60.
+ *
+ * The modes with timings same as above modes are supported only with min of 10 bpc
+ * along with:
+ *
+ * i) 444 format only with FRL mode support with DSC
+ * ii) 420 format only with FRL mode without DSC.
+ */
+static bool
+intel_hdmi21_bpc_possible(struct drm_connector *connector,
+			  int clock, int bpc, bool ycbcr420_output,
+			  bool frl, bool dsc)
+{
+	const struct drm_display_info *info = &connector->display_info;
+	const struct drm_hdmi_info *hdmi = &info->hdmi;
+
+	int pixel_clock = ycbcr420_output ? clock * 2 : clock;
+
+	if (pixel_clock < 2376000)
+		return true;
+
+	if (!frl)
+		return false;
+
+	if (dsc && bpc > hdmi->dsc_cap.bpc_supported)
+		return false;
+
+	if (!ycbcr420_output && !dsc)
+		return false;
+
+	if (bpc < 10)
+		return false;
+
+	return true;
+}
+
 static enum drm_mode_status
 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
 			    bool has_hdmi_sink, bool ycbcr420_output)
@@ -1948,6 +1986,13 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
 	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
 	enum drm_mode_status status = MODE_OK;
 	int bpc;
+	bool frl, dsc;
+
+	/*
+	 * FRL and DSC not supported for HDMI from source as of now.
+	 */
+	frl = false;
+	dsc = false;
 
 	/*
 	 * Try all color depths since valid port clock range
@@ -1963,6 +2008,9 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
 		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
 			continue;
 
+		if (!intel_hdmi21_bpc_possible(connector, clock, bpc, ycbcr420_output, frl, dsc))
+			continue;
+
 		status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
 		if (status == MODE_OK)
 			return MODE_OK;
-- 
2.25.1

Re: [PATCH 2/2] drm/i915/hdmi: Prune unsupported modes as per HDMI2.1 spec

[Ville Syrjälä]

On Mon, May 09, 2022 at 03:01:30PM +0530, Ankit Nautiyal wrote:
> As per Sec 7.8.1 of HDMI2.1 spec, sources that support modes:
> 4K100, 4K120, 8K50, 8K60 must support these modes in at least one of
> the below formats:
> i) uncompressed FRL, 420 format and min of 10 bpc, or
> ii) compressed FRL, 444 format and min of 10 bpc.
> 
> Since FRL and DSC are not supported natively with HDMI, the above
> modes must be pruned as per the spec, and is a requirement for the
> HDMI2.1 compliance test.
> 
> This patch adds a condition to check for the modes with clock
> requirement more than 2376 MHz (1188 MHz with 420 format),
> and prune them if none of the above two formats are supported.

Wy are we trying to pass HDMI-2.1 tests on a device that
doesn't even support HDMI-2.1? 

> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 48 +++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 1ae09431f53a..2ee1262f6427 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1940,6 +1940,44 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
>  	}
>  }
>  
> +/*
> + * HDMI2.1 Sec7.8.1
> + * Support requirement for 4K100, 4K120, 8K50, and 8K60.
> + *
> + * The modes with timings same as above modes are supported only with min of 10 bpc
> + * along with:
> + *
> + * i) 444 format only with FRL mode support with DSC
> + * ii) 420 format only with FRL mode without DSC.
> + */
> +static bool
> +intel_hdmi21_bpc_possible(struct drm_connector *connector,
> +			  int clock, int bpc, bool ycbcr420_output,
> +			  bool frl, bool dsc)
> +{
> +	const struct drm_display_info *info = &connector->display_info;
> +	const struct drm_hdmi_info *hdmi = &info->hdmi;
> +
> +	int pixel_clock = ycbcr420_output ? clock * 2 : clock;
> +
> +	if (pixel_clock < 2376000)
> +		return true;
> +
> +	if (!frl)
> +		return false;
> +
> +	if (dsc && bpc > hdmi->dsc_cap.bpc_supported)
> +		return false;
> +
> +	if (!ycbcr420_output && !dsc)
> +		return false;
> +
> +	if (bpc < 10)
> +		return false;
> +
> +	return true;
> +}
> +
>  static enum drm_mode_status
>  intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
>  			    bool has_hdmi_sink, bool ycbcr420_output)
> @@ -1948,6 +1986,13 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
>  	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
>  	enum drm_mode_status status = MODE_OK;
>  	int bpc;
> +	bool frl, dsc;
> +
> +	/*
> +	 * FRL and DSC not supported for HDMI from source as of now.
> +	 */
> +	frl = false;
> +	dsc = false;
>  
>  	/*
>  	 * Try all color depths since valid port clock range
> @@ -1963,6 +2008,9 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
>  		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
>  			continue;
>  
> +		if (!intel_hdmi21_bpc_possible(connector, clock, bpc, ycbcr420_output, frl, dsc))
> +			continue;
> +
>  		status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
>  		if (status == MODE_OK)
>  			return MODE_OK;
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

Re: [PATCH 2/2] drm/i915/hdmi: Prune unsupported modes as per HDMI2.1 spec

[Nautiyal, Ankit K]

On 5/10/2022 12:31 PM, Ville Syrjälä wrote:
> On Mon, May 09, 2022 at 03:01:30PM +0530, Ankit Nautiyal wrote:
>> As per Sec 7.8.1 of HDMI2.1 spec, sources that support modes:
>> 4K100, 4K120, 8K50, 8K60 must support these modes in at least one of
>> the below formats:
>> i) uncompressed FRL, 420 format and min of 10 bpc, or
>> ii) compressed FRL, 444 format and min of 10 bpc.
>>
>> Since FRL and DSC are not supported natively with HDMI, the above
>> modes must be pruned as per the spec, and is a requirement for the
>> HDMI2.1 compliance test.
>>
>> This patch adds a condition to check for the modes with clock
>> requirement more than 2376 MHz (1188 MHz with 420 format),
>> and prune them if none of the above two formats are supported.
> Wy are we trying to pass HDMI-2.1 tests on a device that
> doesn't even support HDMI-2.1?

Hi Ville,

As I understand, the HDMI2.1a supersedes HDMI2.0b [1], and so these 
platforms must pass the HDMI2.1 CTS.
The HDMI2.1a spec introduces Marketing Feature names for 4K100, 4K120, 
8k@50, 8k@60 with suffix A, and B.
Suffix A meaning mode supported without compression, and B meaning, mode 
supported with compression.
e.g 4K@120AB marketing feature name means the device supports 4k@120 
both with and without compression.
But as per the spec, both variants of Marketing names require FRL to be 
supported along with other requirements.
There are tests that expect these modes not to be enumerated, if the 
source does support the given requirements.

[1] https://www.hdmi.org/spec/hdmi2_1

Regards,

Ankit

>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_hdmi.c | 48 +++++++++++++++++++++++
>>   1 file changed, 48 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> index 1ae09431f53a..2ee1262f6427 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> @@ -1940,6 +1940,44 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
>>   	}
>>   }
>>   
>> +/*
>> + * HDMI2.1 Sec7.8.1
>> + * Support requirement for 4K100, 4K120, 8K50, and 8K60.
>> + *
>> + * The modes with timings same as above modes are supported only with min of 10 bpc
>> + * along with:
>> + *
>> + * i) 444 format only with FRL mode support with DSC
>> + * ii) 420 format only with FRL mode without DSC.
>> + */
>> +static bool
>> +intel_hdmi21_bpc_possible(struct drm_connector *connector,
>> +			  int clock, int bpc, bool ycbcr420_output,
>> +			  bool frl, bool dsc)
>> +{
>> +	const struct drm_display_info *info = &connector->display_info;
>> +	const struct drm_hdmi_info *hdmi = &info->hdmi;
>> +
>> +	int pixel_clock = ycbcr420_output ? clock * 2 : clock;
>> +
>> +	if (pixel_clock < 2376000)
>> +		return true;
>> +
>> +	if (!frl)
>> +		return false;
>> +
>> +	if (dsc && bpc > hdmi->dsc_cap.bpc_supported)
>> +		return false;
>> +
>> +	if (!ycbcr420_output && !dsc)
>> +		return false;
>> +
>> +	if (bpc < 10)
>> +		return false;
>> +
>> +	return true;
>> +}
>> +
>>   static enum drm_mode_status
>>   intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
>>   			    bool has_hdmi_sink, bool ycbcr420_output)
>> @@ -1948,6 +1986,13 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
>>   	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
>>   	enum drm_mode_status status = MODE_OK;
>>   	int bpc;
>> +	bool frl, dsc;
>> +
>> +	/*
>> +	 * FRL and DSC not supported for HDMI from source as of now.
>> +	 */
>> +	frl = false;
>> +	dsc = false;
>>   
>>   	/*
>>   	 * Try all color depths since valid port clock range
>> @@ -1963,6 +2008,9 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
>>   		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
>>   			continue;
>>   
>> +		if (!intel_hdmi21_bpc_possible(connector, clock, bpc, ycbcr420_output, frl, dsc))
>> +			continue;
>> +
>>   		status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
>>   		if (status == MODE_OK)
>>   			return MODE_OK;
>> -- 
>> 2.25.1