* [PATCH 1/3] drm/i915: Remove redundant check for DG1
@ 2023-03-06 20:49 Lucas De Marchi
2023-03-06 20:49 ` [PATCH 2/3] drm/i915: Move DG2 tuning to the right function Lucas De Marchi
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Lucas De Marchi @ 2023-03-06 20:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
dg1_gt_workarounds_init() is only ever called for DG1, so there is no
point checking it again.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 32aa1647721a..eb6cc4867d67 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1472,21 +1472,15 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
static void
dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
- struct drm_i915_private *i915 = gt->i915;
-
gen12_gt_workarounds_init(gt, wal);
/* Wa_1409420604:dg1 */
- if (IS_DG1(i915))
- wa_mcr_write_or(wal,
- SUBSLICE_UNIT_LEVEL_CLKGATE2,
- CPSSUNIT_CLKGATE_DIS);
+ wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
/* Wa_1408615072:dg1 */
/* Empirical testing shows this register is unaffected by engine reset. */
- if (IS_DG1(i915))
- wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
- VSUNIT_CLKGATE_DIS_TGL);
+ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
}
static void
--
2.39.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] drm/i915: Move DG2 tuning to the right function
2023-03-06 20:49 [PATCH 1/3] drm/i915: Remove redundant check for DG1 Lucas De Marchi
@ 2023-03-06 20:49 ` Lucas De Marchi
2023-03-06 23:16 ` [Intel-gfx] " Matt Roper
2023-03-06 20:49 ` [PATCH 3/3] drm/i915/dg1: Move Wa_1806527549 " Lucas De Marchi
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Lucas De Marchi @ 2023-03-06 20:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Use gt_tuning_settings() for the recommended tunings rather than the one
for workarounds.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index eb6cc4867d67..389bfcd299af 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1653,13 +1653,6 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_14014830051:dg2 */
wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
- /*
- * The following are not actually "workarounds" but rather
- * recommended tuning settings documented in the bspec's
- * performance guide section.
- */
- wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
-
/* Wa_14015795083 */
wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
@@ -1752,8 +1745,10 @@ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
}
- if (IS_DG2(gt->i915))
+ if (IS_DG2(gt->i915)) {
wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+ wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
+ }
}
static void
--
2.39.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/3] drm/i915/dg1: Move Wa_1806527549 to the right function
2023-03-06 20:49 [PATCH 1/3] drm/i915: Remove redundant check for DG1 Lucas De Marchi
2023-03-06 20:49 ` [PATCH 2/3] drm/i915: Move DG2 tuning to the right function Lucas De Marchi
@ 2023-03-06 20:49 ` Lucas De Marchi
2023-03-06 23:17 ` [Intel-gfx] " Matt Roper
2023-03-06 23:15 ` [Intel-gfx] [PATCH 1/3] drm/i915: Remove redundant check for DG1 Matt Roper
2023-03-13 9:10 ` Ville Syrjälä
3 siblings, 1 reply; 10+ messages in thread
From: Lucas De Marchi @ 2023-03-06 20:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
dg1_ctx_workarounds_init() is DG1-only, while
gen12_ctx_workarounds_init() is shared with other platforms. Move the
workaround to the former so there is no additional platform check
needed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 389bfcd299af..f68fe64f63a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -707,8 +707,6 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
- struct drm_i915_private *i915 = engine->i915;
-
gen12_ctx_gt_tuning_init(engine, wal);
/*
@@ -742,10 +740,6 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
FF_MODE2_GS_TIMER_MASK,
FF_MODE2_GS_TIMER_224,
0, false);
-
- if (!IS_DG1(i915))
- /* Wa_1806527549 */
- wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
}
static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -760,6 +754,9 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
/* Wa_22010493298 */
wa_masked_en(wal, HIZ_CHICKEN,
DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
+
+ /* Wa_1806527549 */
+ wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
}
static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
--
2.39.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Remove redundant check for DG1
2023-03-06 20:49 [PATCH 1/3] drm/i915: Remove redundant check for DG1 Lucas De Marchi
2023-03-06 20:49 ` [PATCH 2/3] drm/i915: Move DG2 tuning to the right function Lucas De Marchi
2023-03-06 20:49 ` [PATCH 3/3] drm/i915/dg1: Move Wa_1806527549 " Lucas De Marchi
@ 2023-03-06 23:15 ` Matt Roper
2023-03-13 9:10 ` Ville Syrjälä
3 siblings, 0 replies; 10+ messages in thread
From: Matt Roper @ 2023-03-06 23:15 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Mon, Mar 06, 2023 at 12:49:52PM -0800, Lucas De Marchi wrote:
> dg1_gt_workarounds_init() is only ever called for DG1, so there is no
> point checking it again.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++---------
> 1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 32aa1647721a..eb6cc4867d67 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1472,21 +1472,15 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> static void
> dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> - struct drm_i915_private *i915 = gt->i915;
> -
> gen12_gt_workarounds_init(gt, wal);
>
> /* Wa_1409420604:dg1 */
> - if (IS_DG1(i915))
> - wa_mcr_write_or(wal,
> - SUBSLICE_UNIT_LEVEL_CLKGATE2,
> - CPSSUNIT_CLKGATE_DIS);
> + wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2,
> + CPSSUNIT_CLKGATE_DIS);
>
> /* Wa_1408615072:dg1 */
> /* Empirical testing shows this register is unaffected by engine reset. */
> - if (IS_DG1(i915))
> - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> - VSUNIT_CLKGATE_DIS_TGL);
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
> }
>
> static void
> --
> 2.39.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Move DG2 tuning to the right function
2023-03-06 20:49 ` [PATCH 2/3] drm/i915: Move DG2 tuning to the right function Lucas De Marchi
@ 2023-03-06 23:16 ` Matt Roper
0 siblings, 0 replies; 10+ messages in thread
From: Matt Roper @ 2023-03-06 23:16 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Mon, Mar 06, 2023 at 12:49:53PM -0800, Lucas De Marchi wrote:
> Use gt_tuning_settings() for the recommended tunings rather than the one
> for workarounds.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++--------
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index eb6cc4867d67..389bfcd299af 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1653,13 +1653,6 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> /* Wa_14014830051:dg2 */
> wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>
> - /*
> - * The following are not actually "workarounds" but rather
> - * recommended tuning settings documented in the bspec's
> - * performance guide section.
> - */
> - wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
> -
> /* Wa_14015795083 */
> wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
>
> @@ -1752,8 +1745,10 @@ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
> }
>
> - if (IS_DG2(gt->i915))
> + if (IS_DG2(gt->i915)) {
> wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> + wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
> + }
> }
>
> static void
> --
> 2.39.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/dg1: Move Wa_1806527549 to the right function
2023-03-06 20:49 ` [PATCH 3/3] drm/i915/dg1: Move Wa_1806527549 " Lucas De Marchi
@ 2023-03-06 23:17 ` Matt Roper
2023-03-06 23:53 ` Lucas De Marchi
0 siblings, 1 reply; 10+ messages in thread
From: Matt Roper @ 2023-03-06 23:17 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Mon, Mar 06, 2023 at 12:49:54PM -0800, Lucas De Marchi wrote:
> dg1_ctx_workarounds_init() is DG1-only, while
> gen12_ctx_workarounds_init() is shared with other platforms. Move the
> workaround to the former so there is no additional platform check
> needed.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++------
> 1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 389bfcd299af..f68fe64f63a6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -707,8 +707,6 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> - struct drm_i915_private *i915 = engine->i915;
> -
> gen12_ctx_gt_tuning_init(engine, wal);
>
> /*
> @@ -742,10 +740,6 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
> FF_MODE2_GS_TIMER_MASK,
> FF_MODE2_GS_TIMER_224,
> 0, false);
> -
> - if (!IS_DG1(i915))
I think you missed the "!" here. I.e., this workaround applies to all
the "gen12" platforms *except* DG1.
Matt
> - /* Wa_1806527549 */
> - wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
> }
>
> static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
> @@ -760,6 +754,9 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
> /* Wa_22010493298 */
> wa_masked_en(wal, HIZ_CHICKEN,
> DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
> +
> + /* Wa_1806527549 */
> + wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
> }
>
> static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> --
> 2.39.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/dg1: Move Wa_1806527549 to the right function
2023-03-06 23:17 ` [Intel-gfx] " Matt Roper
@ 2023-03-06 23:53 ` Lucas De Marchi
0 siblings, 0 replies; 10+ messages in thread
From: Lucas De Marchi @ 2023-03-06 23:53 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On Mon, Mar 06, 2023 at 03:17:50PM -0800, Matt Roper wrote:
>On Mon, Mar 06, 2023 at 12:49:54PM -0800, Lucas De Marchi wrote:
>> dg1_ctx_workarounds_init() is DG1-only, while
>> gen12_ctx_workarounds_init() is shared with other platforms. Move the
>> workaround to the former so there is no additional platform check
>> needed.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++------
>> 1 file changed, 3 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 389bfcd299af..f68fe64f63a6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -707,8 +707,6 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>> static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
>> struct i915_wa_list *wal)
>> {
>> - struct drm_i915_private *i915 = engine->i915;
>> -
>> gen12_ctx_gt_tuning_init(engine, wal);
>>
>> /*
>> @@ -742,10 +740,6 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
>> FF_MODE2_GS_TIMER_MASK,
>> FF_MODE2_GS_TIMER_224,
>> 0, false);
>> -
>> - if (!IS_DG1(i915))
>
>I think you missed the "!" here. I.e., this workaround applies to all
>the "gen12" platforms *except* DG1.
oops, thanks for catching that. I'll drop this last patch.
Lucas De Marchi
>
>
>Matt
>
>> - /* Wa_1806527549 */
>> - wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
>> }
>>
>> static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
>> @@ -760,6 +754,9 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
>> /* Wa_22010493298 */
>> wa_masked_en(wal, HIZ_CHICKEN,
>> DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
>> +
>> + /* Wa_1806527549 */
>> + wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
>> }
>>
>> static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>> --
>> 2.39.0
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Remove redundant check for DG1
2023-03-06 20:49 [PATCH 1/3] drm/i915: Remove redundant check for DG1 Lucas De Marchi
` (2 preceding siblings ...)
2023-03-06 23:15 ` [Intel-gfx] [PATCH 1/3] drm/i915: Remove redundant check for DG1 Matt Roper
@ 2023-03-13 9:10 ` Ville Syrjälä
2023-03-13 13:23 ` Lucas De Marchi
3 siblings, 1 reply; 10+ messages in thread
From: Ville Syrjälä @ 2023-03-13 9:10 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Mon, Mar 06, 2023 at 12:49:52PM -0800, Lucas De Marchi wrote:
> dg1_gt_workarounds_init() is only ever called for DG1, so there is no
> point checking it again.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++---------
> 1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 32aa1647721a..eb6cc4867d67 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1472,21 +1472,15 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> static void
> dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> - struct drm_i915_private *i915 = gt->i915;
> -
Looks like you pushed some stale version of this patch which
didn't remove this variable. Now the CONFIG_DRM_I915_WERROR=y
build is broken.
Did you lose that from your pre-push build .config?
> gen12_gt_workarounds_init(gt, wal);
>
> /* Wa_1409420604:dg1 */
> - if (IS_DG1(i915))
> - wa_mcr_write_or(wal,
> - SUBSLICE_UNIT_LEVEL_CLKGATE2,
> - CPSSUNIT_CLKGATE_DIS);
> + wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2,
> + CPSSUNIT_CLKGATE_DIS);
>
> /* Wa_1408615072:dg1 */
> /* Empirical testing shows this register is unaffected by engine reset. */
> - if (IS_DG1(i915))
> - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> - VSUNIT_CLKGATE_DIS_TGL);
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
> }
>
> static void
> --
> 2.39.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Remove redundant check for DG1
2023-03-13 9:10 ` Ville Syrjälä
@ 2023-03-13 13:23 ` Lucas De Marchi
2023-03-13 13:32 ` Ville Syrjälä
0 siblings, 1 reply; 10+ messages in thread
From: Lucas De Marchi @ 2023-03-13 13:23 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Mon, Mar 13, 2023 at 11:10:26AM +0200, Ville Syrjälä wrote:
>On Mon, Mar 06, 2023 at 12:49:52PM -0800, Lucas De Marchi wrote:
>> dg1_gt_workarounds_init() is only ever called for DG1, so there is no
>> point checking it again.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++---------
>> 1 file changed, 3 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 32aa1647721a..eb6cc4867d67 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -1472,21 +1472,15 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>> static void
>> dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>> {
>> - struct drm_i915_private *i915 = gt->i915;
>> -
>
>Looks like you pushed some stale version of this patch which
>didn't remove this variable. Now the CONFIG_DRM_I915_WERROR=y
>build is broken.
>
>Did you lose that from your pre-push build .config?
no, looks like a conflict between drm-intel-gt-next and drm-intel-next
69ea87e1591a ("drm/i915/dg1: Drop support for pre-production steppings")
merged in drm-intel-next dropped the only user.
This patch was merged in drm-intel-gt-next and I didn't realize the
race was with the other branch rather than with the same branch due to
taking a long time for me to apply. Let me rebuild drm-tip to fix it up.
Lucas De Marchi
>
>> gen12_gt_workarounds_init(gt, wal);
>>
>> /* Wa_1409420604:dg1 */
>> - if (IS_DG1(i915))
>> - wa_mcr_write_or(wal,
>> - SUBSLICE_UNIT_LEVEL_CLKGATE2,
>> - CPSSUNIT_CLKGATE_DIS);
>> + wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2,
>> + CPSSUNIT_CLKGATE_DIS);
>>
>> /* Wa_1408615072:dg1 */
>> /* Empirical testing shows this register is unaffected by engine reset. */
>> - if (IS_DG1(i915))
>> - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>> - VSUNIT_CLKGATE_DIS_TGL);
>> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
>> }
>>
>> static void
>> --
>> 2.39.0
>
>--
>Ville Syrjälä
>Intel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Remove redundant check for DG1
2023-03-13 13:23 ` Lucas De Marchi
@ 2023-03-13 13:32 ` Ville Syrjälä
0 siblings, 0 replies; 10+ messages in thread
From: Ville Syrjälä @ 2023-03-13 13:32 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Mon, Mar 13, 2023 at 06:23:59AM -0700, Lucas De Marchi wrote:
> On Mon, Mar 13, 2023 at 11:10:26AM +0200, Ville Syrjälä wrote:
> >On Mon, Mar 06, 2023 at 12:49:52PM -0800, Lucas De Marchi wrote:
> >> dg1_gt_workarounds_init() is only ever called for DG1, so there is no
> >> point checking it again.
> >>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++---------
> >> 1 file changed, 3 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> index 32aa1647721a..eb6cc4867d67 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> @@ -1472,21 +1472,15 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> >> static void
> >> dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> >> {
> >> - struct drm_i915_private *i915 = gt->i915;
> >> -
> >
> >Looks like you pushed some stale version of this patch which
> >didn't remove this variable. Now the CONFIG_DRM_I915_WERROR=y
> >build is broken.
> >
> >Did you lose that from your pre-push build .config?
>
> no, looks like a conflict between drm-intel-gt-next and drm-intel-next
>
> 69ea87e1591a ("drm/i915/dg1: Drop support for pre-production steppings")
> merged in drm-intel-next dropped the only user.
>
> This patch was merged in drm-intel-gt-next and I didn't realize the
> race was with the other branch rather than with the same branch due to
> taking a long time for me to apply. Let me rebuild drm-tip to fix it up.
I already fixed it. Just forgot to note that here.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-03-13 13:33 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-03-06 20:49 [PATCH 1/3] drm/i915: Remove redundant check for DG1 Lucas De Marchi
2023-03-06 20:49 ` [PATCH 2/3] drm/i915: Move DG2 tuning to the right function Lucas De Marchi
2023-03-06 23:16 ` [Intel-gfx] " Matt Roper
2023-03-06 20:49 ` [PATCH 3/3] drm/i915/dg1: Move Wa_1806527549 " Lucas De Marchi
2023-03-06 23:17 ` [Intel-gfx] " Matt Roper
2023-03-06 23:53 ` Lucas De Marchi
2023-03-06 23:15 ` [Intel-gfx] [PATCH 1/3] drm/i915: Remove redundant check for DG1 Matt Roper
2023-03-13 9:10 ` Ville Syrjälä
2023-03-13 13:23 ` Lucas De Marchi
2023-03-13 13:32 ` Ville Syrjälä
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