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From: Raag Jadav <raag.jadav@intel.com>
To: Riana Tauro <riana.tauro@intel.com>
Cc: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	aravind.iddamsetty@linux.intel.com, anshuman.gupta@intel.com,
	rodrigo.vivi@intel.com, joonas.lahtinen@linux.intel.com,
	simona.vetter@ffwll.ch, airlied@gmail.com, pratik.bari@intel.com,
	joshua.santosh.ranjan@intel.com, ashwin.kumar.kulkarni@intel.com,
	shubham.kumar@intel.com, ravi.kishore.koppuravuri@intel.com,
	Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Subject: Re: [PATCH v6 5/5] drm/xe/xe_hw_error: Add support for PVC SoC errors
Date: Mon, 16 Feb 2026 11:21:11 +0100	[thread overview]
Message-ID: <aZLvl7tinj9h-h-B@black.igk.intel.com> (raw)
In-Reply-To: <20260216064726.2542819-12-riana.tauro@intel.com>

On Mon, Feb 16, 2026 at 12:17:31PM +0530, Riana Tauro wrote:
> Report the SoC nonfatal/fatal hardware error and update the counters.

...

> +	/*
> +	 * Read the master global IEH error register, if BIT(1) is set then process
> +	 * the slave IEH first. If BIT(0) in global error register is set then process
> +	 * the corresponding local error registers.
> +	 */
> +	master_global_errstat = xe_mmio_read32(mmio, SOC_GLOBAL_ERR_STAT_REG(master, hw_err));
> +	if (master_global_errstat & SOC_SLAVE_IEH)
> +		soc_slave_ieh_handler(tile, hw_err, error_id);
> +
> +	if (master_global_errstat & SOC_IEH0_LOCAL_ERR_STATUS) {
> +		const char * const *reg_info = (hw_err == HARDWARE_ERROR_FATAL) ?
> +						pvc_master_local_fatal_err_reg :
> +						pvc_master_local_nonfatal_err_reg;

Nit: Ditto, with something like PVC_MASTER_LOCAL_REG_INFO() you won't
need a local pointer.

Reviewed-by: Raag Jadav <raag.jadav@intel.com>

> +		master_local_errstat = xe_mmio_read32(mmio, SOC_LOCAL_ERR_STAT_REG(master, hw_err));
> +
> +		for_each_set_bit(regbit, &master_local_errstat, XE_RAS_REG_SIZE)
> +			log_soc_error(tile, reg_info, severity, regbit, error_id);
> +
> +		xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(master, hw_err), master_local_errstat);
> +	}
> +
> +	for_each_set_bit(regbit, &master_global_errstat, XE_RAS_REG_SIZE)
> +		log_soc_error(tile, pvc_master_global_err_reg, severity, regbit, error_id);
> +
> +	xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(master, hw_err), master_global_errstat);
> +
> +unmask_gsysevtctl:
> +	for (i = 0; i < XE_SOC_NUM_IEH; i++)
> +		xe_mmio_write32(mmio, SOC_GSYSEVTCTL_REG(master, slave, i),
> +				(HARDWARE_ERROR_MAX << 1) + 1);
> +}

      reply	other threads:[~2026-02-16 10:21 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-16  6:47 [PATCH v6 0/5] Introduce DRM_RAS using generic netlink for RAS Riana Tauro
2026-02-16  6:47 ` [PATCH v6 1/5] drm/ras: Introduce the DRM RAS infrastructure over generic netlink Riana Tauro
2026-02-16  6:47 ` [PATCH v6 2/5] drm/xe/xe_drm_ras: Add support for XE DRM RAS Riana Tauro
2026-02-16  9:58   ` Raag Jadav
2026-02-16  6:47 ` [PATCH v6 3/5] drm/xe/xe_hw_error: Integrate DRM RAS with hardware error handling Riana Tauro
2026-02-16 10:00   ` Raag Jadav
2026-02-16  6:47 ` [PATCH v6 4/5] drm/xe/xe_hw_error: Add support for Core-Compute errors Riana Tauro
2026-02-16 10:14   ` Raag Jadav
2026-02-16  6:47 ` [PATCH v6 5/5] drm/xe/xe_hw_error: Add support for PVC SoC errors Riana Tauro
2026-02-16 10:21   ` Raag Jadav [this message]

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