[PATCH v2] drm/i915/dp: Only send AS SDP when VRR/CMRR is enabled or PR !async

[PATCH v2] drm/i915/dp: Only send AS SDP when VRR/CMRR is enabled or PR !async

[Xizhe Tang]

A Panther Lake eDP panel that advertises VRR in EDID but runs at a fixed
refresh rate has received an Adaptive-Sync SDP since commit 6a1712052859
("drm/i915/dp: Enable AS SDP whenever VRR is possible or PR !async").
On this panel the first modeset at boot is vertically streaked.

intel_vrr_possible() is only crtc_state->vrr.flipline != 0. Fixed-refresh
timings program flipline too:

	intel_vrr_compute_fixed_rr_timings():
		/* For fixed rr,  vmin = vmax = flipline */
		crtc_state->vrr.flipline = crtc_state->vrr.vmin;

intel_vrr_compute_config() takes that path when VRR is not actually
enabled (uapi.vrr_enabled is false, or vmin == vmax). Then
intel_dp_needs_as_sdp() is true with `vrr: no, fixed rr: yes`, and
intel_dp_compute_as_sdp() programs DP_AS_SDP_AVT_FIXED_VTOTAL.

Gate the terminal condition on the states that consume the SDP:
crtc_state->vrr.enable (VRR) or crtc_state->cmrr.enable (CMRR / FAVT).
Leave the Panel Replay aux-less-ALPM early-return from the same commit
unchanged.

CMRR is still hard-disabled (is_cmrr_frac_required() has "|| true"), so
cmrr.enable stays false today and the OR is a no-op versus v1 at fixed
refresh. intel_vrr_compute_cmrr_timings() sets cmrr.enable without
vrr.enable; the OR keeps the FAVT branch reachable when CMRR is re-enabled.

This is a no-op while VRR is actually active. It does not fix Adaptive
Sync = Always corruption, nor the non-atomic SDP update named by the
#FIXME above intel_dp_compute_as_sdp(). Trailer is Link:, not Closes:.

Tested on LENOVO 21VG (PTL eDP, 8086:b080), v7.2.6-200.fc44.x86_64,
rebuilding only xe.ko with this hunk:

  Adaptive Sync = Never (Tested-by): vrr: no, fixed rr: yes,
  infoframes enabled: 0x6 (no BIT(3)), zero Adaptive-Sync SDP, panel
  clean. This boot: six s2idle suspend/resume cycles, all clean.

  Adaptive Sync = Always (not Tested-by): vrr: yes, vmin 2016 / vmax 8064,
  infoframes enabled: 0xe, Adaptive-Sync SDP still sent. Panel
  appearance on Always is not claimed.

  CMRR / FAVT: not tested.

On the same panel, Adaptive Sync = Never, first modeset, drm.debug=0xe:

  7.1.13 (clean):     infoframes enabled: 0x4  (VSC only)
  7.2.4  (streaked):  infoframes enabled: 0xc  (VSC + AS SDP,
                      operation mode 1 = DP_AS_SDP_AVT_FIXED_VTOTAL)

  Later dumps of those boots are 0x6 vs 0xe; each non-zero bad mask is
  good | BIT(3).

Changes in v2:
- OR crtc_state->cmrr.enable so CMRR still gets AS SDP (v1 review).
  At fixed refresh v2 matches v1.
  v1: https://lore.kernel.org/r/20260923052937.22817-1-xizheTang2005@163.com

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9252
Fixes: 6a1712052859 ("drm/i915/dp: Enable AS SDP whenever VRR is possible or PR !async")
Cc: stable@vger.kernel.org # 7.2.x
Signed-off-by: Xizhe Tang <xizheTang2005@163.com>
Tested-by: Xizhe Tang <xizheTang2005@163.com> # v7.2.6, PTL eDP, Adaptive Sync=Never
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3115,8 +3115,9 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
 	    !intel_psr_pr_async_video_timing_supported(intel_dp))
 		return true;
 
-	return intel_vrr_possible(crtc_state);
+	return crtc_state->vrr.enable ||
+	       crtc_state->cmrr.enable;
 }
 
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
--
2.47.0

Re: [PATCH v2] drm/i915/dp: Only send AS SDP when VRR/CMRR is enabled or PR !async

[Jani Nikula]

On Thu, 24 Sep 2026, Xizhe Tang <xizheTang2005@163.com> wrote:
> A Panther Lake eDP panel that advertises VRR in EDID but runs at a fixed
> refresh rate has received an Adaptive-Sync SDP since commit 6a1712052859
> ("drm/i915/dp: Enable AS SDP whenever VRR is possible or PR !async").
> On this panel the first modeset at boot is vertically streaked.
>
> intel_vrr_possible() is only crtc_state->vrr.flipline != 0. Fixed-refresh
> timings program flipline too:
>
> 	intel_vrr_compute_fixed_rr_timings():
> 		/* For fixed rr,  vmin = vmax = flipline */
> 		crtc_state->vrr.flipline = crtc_state->vrr.vmin;
>
> intel_vrr_compute_config() takes that path when VRR is not actually
> enabled (uapi.vrr_enabled is false, or vmin == vmax). Then
> intel_dp_needs_as_sdp() is true with `vrr: no, fixed rr: yes`, and
> intel_dp_compute_as_sdp() programs DP_AS_SDP_AVT_FIXED_VTOTAL.
>
> Gate the terminal condition on the states that consume the SDP:
> crtc_state->vrr.enable (VRR) or crtc_state->cmrr.enable (CMRR / FAVT).
> Leave the Panel Replay aux-less-ALPM early-return from the same commit
> unchanged.
>
> CMRR is still hard-disabled (is_cmrr_frac_required() has "|| true"), so
> cmrr.enable stays false today and the OR is a no-op versus v1 at fixed
> refresh. intel_vrr_compute_cmrr_timings() sets cmrr.enable without
> vrr.enable; the OR keeps the FAVT branch reachable when CMRR is re-enabled.
>
> This is a no-op while VRR is actually active. It does not fix Adaptive
> Sync = Always corruption, nor the non-atomic SDP update named by the
> #FIXME above intel_dp_compute_as_sdp(). Trailer is Link:, not Closes:.
>
> Tested on LENOVO 21VG (PTL eDP, 8086:b080), v7.2.6-200.fc44.x86_64,
> rebuilding only xe.ko with this hunk:
>
>   Adaptive Sync = Never (Tested-by): vrr: no, fixed rr: yes,
>   infoframes enabled: 0x6 (no BIT(3)), zero Adaptive-Sync SDP, panel
>   clean. This boot: six s2idle suspend/resume cycles, all clean.
>
>   Adaptive Sync = Always (not Tested-by): vrr: yes, vmin 2016 / vmax 8064,
>   infoframes enabled: 0xe, Adaptive-Sync SDP still sent. Panel
>   appearance on Always is not claimed.
>
>   CMRR / FAVT: not tested.
>
> On the same panel, Adaptive Sync = Never, first modeset, drm.debug=0xe:
>
>   7.1.13 (clean):     infoframes enabled: 0x4  (VSC only)
>   7.2.4  (streaked):  infoframes enabled: 0xc  (VSC + AS SDP,
>                       operation mode 1 = DP_AS_SDP_AVT_FIXED_VTOTAL)
>
>   Later dumps of those boots are 0x6 vs 0xe; each non-zero bad mask is
>   good | BIT(3).
>
> Changes in v2:
> - OR crtc_state->cmrr.enable so CMRR still gets AS SDP (v1 review).
>   At fixed refresh v2 matches v1.
>   v1: https://lore.kernel.org/r/20260923052937.22817-1-xizheTang2005@163.com

I've received a bug report, patch v1, and four (!) copies of patch v2
within just hours.

Please have more patience.

The commit message appears to be a long-winded description of *what* the
code does, which is mostly uninteresting and frankly difficult to
understand, and lacks proper rationale of *why* the change is being made
and why it might help with the issue.


BR,
Jani.



>
> Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9252
> Fixes: 6a1712052859 ("drm/i915/dp: Enable AS SDP whenever VRR is possible or PR !async")
> Cc: stable@vger.kernel.org # 7.2.x
> Signed-off-by: Xizhe Tang <xizheTang2005@163.com>
> Tested-by: Xizhe Tang <xizheTang2005@163.com> # v7.2.6, PTL eDP, Adaptive Sync=Never
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3115,8 +3115,9 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>  	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
>  	    !intel_psr_pr_async_video_timing_supported(intel_dp))
>  		return true;
>  
> -	return intel_vrr_possible(crtc_state);
> +	return crtc_state->vrr.enable ||
> +	       crtc_state->cmrr.enable;
>  }
>  
>  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> --
> 2.47.0
>

-- 
Jani Nikula, Intel

Re: [PATCH v2] drm/i915/dp: Only send AS SDP when VRR/CMRR is enabled or PR !async

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] drm/i915: build failure due to missing vrr qualifier for cmrr
--

commit 040a3a223ae954dab43478f6da5edfc88f5ff693
Author: Xizhe Tang <xizheTang2005@163.com>

drm/i915/dp: Only send AS SDP when VRR/CMRR is enabled or PR !async

This commit alters the condition for sending the Adaptive-Sync SDP by checking
explicitly for VRR or CMRR enablement in the CRTC state. This prevents vertical
streaking on eDP panels that advertise VRR but run at fixed refresh rates.

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9252

> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0cd5e6b5034cf..612bc2846475b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3111,7 +3111,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>  	    !intel_psr_pr_async_video_timing_supported(intel_dp))
>  		return true;
>  
> -	return intel_vrr_possible(crtc_state);
> +	return crtc_state->vrr.enable ||
> +	       crtc_state->cmrr.enable;

[Severity: Low]
Does this cause a compilation error in intel_dp_needs_as_sdp()? 

Looking at the definition of intel_crtc_state in
drivers/gpu/drm/i915/display/intel_display_types.h, cmrr is nested inside vrr:

    struct intel_crtc_state {
        ...
        struct {
            ...
            /* Content Match Refresh Rate state */
            struct {
                bool enable;
                u64 cmrr_n, cmrr_m;
            } cmrr;
        } vrr;
        ...
    };

Because cmrr is nested, accessing it directly via crtc_state->cmrr.enable will
fail to compile. Should this be accessed as crtc_state->vrr.cmrr.enable
instead, similar to how it is checked in intel_dp_compute_as_sdp() further
down in this same file?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260923195200.21362-1-xizheTang2005@163.com?part=1

Re: [PATCH v2] drm/i915/dp: Only send AS SDP when VRR/CMRR is enabled or PR !async

[Ville Syrjälä]

On Thu, Sep 24, 2026 at 03:51:59AM +0800, Xizhe Tang wrote:
> A Panther Lake eDP panel that advertises VRR in EDID but runs at a fixed
> refresh rate has received an Adaptive-Sync SDP since commit 6a1712052859
> ("drm/i915/dp: Enable AS SDP whenever VRR is possible or PR !async").
> On this panel the first modeset at boot is vertically streaked.
> 
> intel_vrr_possible() is only crtc_state->vrr.flipline != 0. Fixed-refresh
> timings program flipline too:
> 
> 	intel_vrr_compute_fixed_rr_timings():
> 		/* For fixed rr,  vmin = vmax = flipline */
> 		crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> 
> intel_vrr_compute_config() takes that path when VRR is not actually
> enabled (uapi.vrr_enabled is false, or vmin == vmax). Then
> intel_dp_needs_as_sdp() is true with `vrr: no, fixed rr: yes`, and
> intel_dp_compute_as_sdp() programs DP_AS_SDP_AVT_FIXED_VTOTAL.
> 
> Gate the terminal condition on the states that consume the SDP:
> crtc_state->vrr.enable (VRR) or crtc_state->cmrr.enable (CMRR / FAVT).
> Leave the Panel Replay aux-less-ALPM early-return from the same commit
> unchanged.
> 
> CMRR is still hard-disabled (is_cmrr_frac_required() has "|| true"), so
> cmrr.enable stays false today and the OR is a no-op versus v1 at fixed
> refresh. intel_vrr_compute_cmrr_timings() sets cmrr.enable without
> vrr.enable; the OR keeps the FAVT branch reachable when CMRR is re-enabled.
> 
> This is a no-op while VRR is actually active. It does not fix Adaptive
> Sync = Always corruption, nor the non-atomic SDP update named by the
> #FIXME above intel_dp_compute_as_sdp(). Trailer is Link:, not Closes:.
> 
> Tested on LENOVO 21VG (PTL eDP, 8086:b080), v7.2.6-200.fc44.x86_64,
> rebuilding only xe.ko with this hunk:
> 
>   Adaptive Sync = Never (Tested-by): vrr: no, fixed rr: yes,
>   infoframes enabled: 0x6 (no BIT(3)), zero Adaptive-Sync SDP, panel
>   clean. This boot: six s2idle suspend/resume cycles, all clean.
> 
>   Adaptive Sync = Always (not Tested-by): vrr: yes, vmin 2016 / vmax 8064,
>   infoframes enabled: 0xe, Adaptive-Sync SDP still sent. Panel
>   appearance on Always is not claimed.
> 
>   CMRR / FAVT: not tested.
> 
> On the same panel, Adaptive Sync = Never, first modeset, drm.debug=0xe:
> 
>   7.1.13 (clean):     infoframes enabled: 0x4  (VSC only)
>   7.2.4  (streaked):  infoframes enabled: 0xc  (VSC + AS SDP,
>                       operation mode 1 = DP_AS_SDP_AVT_FIXED_VTOTAL)
> 
>   Later dumps of those boots are 0x6 vs 0xe; each non-zero bad mask is
>   good | BIT(3).
> 
> Changes in v2:
> - OR crtc_state->cmrr.enable so CMRR still gets AS SDP (v1 review).
>   At fixed refresh v2 matches v1.
>   v1: https://lore.kernel.org/r/20260923052937.22817-1-xizheTang2005@163.com
> 
> Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9252
> Fixes: 6a1712052859 ("drm/i915/dp: Enable AS SDP whenever VRR is possible or PR !async")
> Cc: stable@vger.kernel.org # 7.2.x
> Signed-off-by: Xizhe Tang <xizheTang2005@163.com>
> Tested-by: Xizhe Tang <xizheTang2005@163.com> # v7.2.6, PTL eDP, Adaptive Sync=Never
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3115,8 +3115,9 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>  	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
>  	    !intel_psr_pr_async_video_timing_supported(intel_dp))
>  		return true;
>  
> -	return intel_vrr_possible(crtc_state);
> +	return crtc_state->vrr.enable ||
> +	       crtc_state->cmrr.enable;

The real problem is that intel_vrr_possible() no longer does what
it says on the tin. I think we have three different things
intel_vrr_possible() gets used for currently:

- intel_dp_needs_as_sdp() actually wants to know whether variable VRR
  timings are possible or not, and it wants to know that without
  actually looking at uapi.vrr_enabled in order to avoid changes to
  the guardband when uapi.vrr_enabled changes
- _intel_psr_min_set_context_latency() might want to know whether we
  could end up using the VRR timing generator or not. Not 100% sure
  about this one though
- everything in intel_vrr.c just wants to know whether we should program
  the VRR timing generator registers or not. These are the only places
  where the current intel_vrr_possible() actually looks correct, albeit
  with a bad function name

>  }
>  
>  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> --
> 2.47.0

-- 
Ville Syrjälä
Intel

[PATCH v3 0/3] drm/i915: stop sending a fake Adaptive-Sync SDP

[Xizhe Tang]

v2 gated intel_dp_needs_as_sdp() on vrr.enable || cmrr.enable. Ville
pointed out that this function is also how we size the optimized VRR
guardband, and that looking at vrr.enable there forces a full modeset
when userspace toggles Adaptive Sync.

That coupling is the bug, not the send predicate. Split it:

  1/3  intel_dp_sdp_min_guardband(..., true) reserves AS SDP lines on
       HAS_AS_SDP platforms even when the packet is not enabled. After
       this, toggling vrr.enable does not change crtc_vblank_start.

  2/3  Send the packet only when VRR or CMRR is actually running.
       Predicate is vrr.enable || vrr.cmrr.enable to match drm-tip's
       nested cmrr (v2 used the older sibling cmrr.enable). Now safe
       because 1/3 already reserved the guardband. This is the 7.2
       regression: intel_vrr_possible() is flipline != 0, and fixed-RR
       timings program flipline, so we transmit DP_AS_SDP_AVT_FIXED_VTOTAL
       on a constant refresh. Panel Replay aux-less without async video
       timing still takes the early return in intel_dp_needs_as_sdp()
       from 6a1712052859 and still gets that packet; this machine does
       not hit that path. A 7.2 stable backport needs the sibling
       crtc_state->cmrr.enable spelling.

  3/3  On this panel, Adaptive Sync = Always still streaks on s2idle
       resume after 1+2 (operation mode 0, not the mode-1 packet). Write
       the SDP in intel_ddi_enable() after intel_vrr_transcoder_enable()
       and before intel_enable_transcoder(). Fastset still updates the
       packet from intel_ddi_update_pipe_dp() so a runtime Adaptive Sync
       toggle does not become a full modeset.

1+2 are the regression fix. 3/3 is the Always resume path on this eDP;
drop it if you want only the Never/Automatic half.

Why not vrr.in_range (series 174831 1/3): this panel's EDID range is
30-120 Hz. 60 Hz and 120 Hz with Adaptive Sync = Never stay in_range,
so that patch still sends AVT_FIXED_VTOTAL here. Reported at
https://lore.kernel.org/r/RxSA9gIRRBSaKwxlF7t96Q@163.com

Not Closes: #9252. 1+2 do not fix Always. 3/3 does.

These patches are against drm-tip, not 7.2.8.

Machine: Lenovo ThinkBook 14 G8+ IPH (21VG), PTL 8086:b080, eDP
3072x1920, EDID 30-120 Hz. Tested by rebuilding xe.ko on
7.2.8-200.fc44.x86_64, and on a full drm-tip kernel. Same results
on both:

  Never / Automatic, boot and lid s2idle: clean with 1+2 (and with 1+2+3).
  Always, lid s2idle: still streaks with 1+2; clean with 1+2+3.
  Runtime Never <-> Always on an already-lit panel: already clean.

Ville in_range, delayed send, and never-send were tried earlier; the
first two still streak, never-send is clean on both policies but is
not upstreamable.

v1: https://lore.kernel.org/r/20260923052937.22817-1-xizheTang2005@163.com
v2: https://lore.kernel.org/r/20260923195200.21362-1-xizheTang2005@163.com

Xizhe Tang (3):
  drm/i915/dp: Reserve AS SDP guardband even when VRR is off
  drm/i915/dp: Send AS SDP only when VRR or CMRR is enabled
  drm/i915/ddi: Program AS SDP before enabling the transcoder

 drivers/gpu/drm/i915/display/intel_ddi.c |  4 ++++
 drivers/gpu/drm/i915/display/intel_dp.c  | 35 ++++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_dp.h  |  2 ++
 3 files changed, 37 insertions(+), 4 deletions(-)

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9252

[PATCH v3 1/3] drm/i915/dp: Reserve AS SDP guardband even when VRR is off

[Xizhe Tang]

intel_vrr_compute_optimized_guardband() calls
intel_dp_sdp_min_guardband(crtc_state, true) so that enabling an SDP
later does not have to grow crtc_vblank_start and trigger a full
modeset.

The Adaptive-Sync clause ignores assume_all_enabled and only looks at
infoframes.enable. Toggling vrr.enable therefore changes the
guardband, which is why sending AS SDP cannot currently follow
vrr.enable.

Reserve the AS SDP lines whenever assume_all_enabled is set on a
HAS_AS_SDP platform, same as the other SDP types in this function.
The next patch can then gate transmission on vrr.enable without
moving vblank.

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9252
Cc: stable@vger.kernel.org # 7.2+
Signed-off-by: Xizhe Tang <xizheTang2005@163.com>
Tested-by: Xizhe Tang <xizheTang2005@163.com> # 7.2.8 xe.ko and drm-tip, PTL eDP; Never<->Always stays a fastset
---
Changes in v3:
- New patch. Addresses Ville's review of v2: needs_as_sdp is also
  how the optimized guardband is sized, so the send predicate must
  not be tied to vrr.enable until this reservation is independent.
- Hunks retargeted to drm-tip line numbers.

 drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d8c0d93..7bfe796 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7500,6 +7500,7 @@ int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 ty
 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 			       bool assume_all_enabled)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	int sdp_guardband = 0;
 
 	if (assume_all_enabled ||
@@ -7514,7 +7515,9 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS));
 
-	if (crtc_state->infoframes.enable &
+	/* Keep the VRR guardband independent of vrr.enable. */
+	if ((assume_all_enabled && HAS_AS_SDP(display)) ||
+	    crtc_state->infoframes.enable &
 	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));
-- 
2.55.0

[PATCH v3 2/3] drm/i915/dp: Send AS SDP only when VRR or CMRR is enabled

[Xizhe Tang]

intel_vrr_possible() is crtc_state->vrr.flipline != 0.
intel_vrr_compute_fixed_rr_timings() programs flipline even when VRR
is off, so commit 6a1712052859 sends an Adaptive-Sync SDP with
DP_AS_SDP_AVT_FIXED_VTOTAL on a constant refresh.

On a Panther Lake eDP that only advertises VRR in EDID, that packet
vertically streaks the first modeset (boot and s2idle resume) when
Adaptive Sync is Never or Automatic.

Send the SDP only while VRR or CMRR is actually enabled. Keep the
Panel Replay aux-less-ALPM early return from the same commit. The
previous patch already reserves the AS SDP guardband when
assume_all_enabled is set, so this does not move crtc_vblank_start
when userspace toggles Adaptive Sync.

vrr.in_range is not a substitute here: this panel's EDID range is
30-120 Hz, so 60 Hz and 120 Hz stay in_range with VRR off and still
get AVT_FIXED_VTOTAL.

This does not fix Adaptive Sync = Always. That path already has
vrr.enable set and is handled by the next patch.

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9252
Fixes: 6a1712052859 ("drm/i915/dp: Enable AS SDP whenever VRR is possible or PR !async")
Cc: stable@vger.kernel.org # 7.2+
Signed-off-by: Xizhe Tang <xizheTang2005@163.com>
Tested-by: Xizhe Tang <xizheTang2005@163.com> # 7.2.8 xe.ko and drm-tip, PTL eDP, Adaptive Sync=Never/Automatic
---
Changes in v3:
- Guardband reservation moved to 1/3 so this no longer changes
  crtc_vblank_start when vrr.enable toggles (Ville).
- Commit message rewritten around why, not the code path (Jani).
- Record that vrr.in_range still sends on this 30-120 Hz panel.
- Use vrr.cmrr.enable (nested under vrr on drm-tip). v2 used the
  older sibling cmrr.enable.

 drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7bfe796..95efc99 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3113,7 +3113,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	    !intel_psr_pr_async_video_timing_supported(intel_dp))
 		return true;
 
-	return intel_vrr_possible(crtc_state);
+	/* intel_vrr_possible() is also true for fixed RR. */
+	return crtc_state->vrr.enable || crtc_state->vrr.cmrr.enable;
 }
 
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
-- 
2.55.0

[PATCH v3 3/3] drm/i915/ddi: Program AS SDP before enabling the transcoder

[Xizhe Tang]

intel_vrr_set_transcoder_timings() already programs TRANS_VRR_VSYNC
and EMP_AS_SDP_TL after TRANS_DDI_FUNC_CTL and before TRANS_CONF.
The Adaptive-Sync SDP itself is still written from
intel_dp_set_infoframes() in intel_ddi_enable_dp(), after
intel_enable_transcoder().

On this Panther Lake eDP, Adaptive Sync = Always still streaks on
lid s2idle resume after the previous two patches. That path sends
AVT_DYNAMIC_VTOTAL (operation mode 0), not the fixed-RR mode-1
packet. The same policy is clean when userspace toggles Adaptive
Sync on an already-lit panel, so the sink can handle the SDP once
the pipe is up.

Write the SDP from intel_ddi_enable() immediately after
intel_vrr_transcoder_enable(), before intel_enable_transcoder().
intel_ddi_enable_dp() runs after TRANS_CONF and must not rewrite
it: keep intel_dp_set_infoframes() from clearing VIDEO_DIP_ENABLE_AS_ADL
on enable, and stop writing AS SDP from there.

Fastset still goes through intel_ddi_update_pipe_dp() on a live
pipe. Call intel_dp_set_as_sdp() there so a VRR toggle can keep
the stock fastset path: intel_crtc_check_fastset() will still
clear mode_changed when only the AS enable bit differs. When the
packet is not needed, the helper clears VIDEO_DIP_ENABLE_AS_ADL
instead of leaving a stale transmission.

The send path does not OR VIDEO_DIP_ENABLE_AS_ADL in the helper:
intel_write_dp_sdp() calls write_infoframe (hsw_write_infoframe on this
eDP), which sets the DIP enable bit after the payload, same as VSC.

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9252
Signed-off-by: Xizhe Tang <xizheTang2005@163.com>
Tested-by: Xizhe Tang <xizheTang2005@163.com> # 7.2.8 xe.ko and drm-tip, PTL eDP, Adaptive Sync=Always lid resume
---
Changes in v3:
- New. Needed on this panel for Always + s2idle; 1+2 alone are not
  enough there. Optional if you only want the Never/Automatic fix.
- Do not touch intel_pipe_config_compare(). Forcing as_sdp onto the
  fastset compare, or switching the AS enable-bit exclude from || to
  &&, turns a runtime Adaptive Sync toggle into a full modeset.
  Keep intel_ddi_update_pipe_dp() writing or clearing the packet.
- Comment that hsw_write_infoframe() sets VIDEO_DIP_ENABLE_AS_ADL
  after the payload; do not OR the HW bit again in the helper.
- Hunks retargeted to drm-tip line numbers.

 drivers/gpu/drm/i915/display/intel_ddi.c |  4 ++++
 drivers/gpu/drm/i915/display/intel_dp.c  | 27 ++++++++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h  |  2 ++
 3 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a46ab5d..c80e246 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3555,6 +3555,9 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 
 	intel_vrr_transcoder_enable(crtc_state);
 
+	if (!is_hdmi)
+		intel_dp_set_as_sdp(encoder, crtc_state);
+
 	/* 128b/132b SST */
 	if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -3651,6 +3654,7 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
 	intel_ddi_set_dp_msa(crtc_state, conn_state);
 
 	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+	intel_dp_set_as_sdp(encoder, crtc_state);
 
 	intel_backlight_update(state, encoder, crtc_state, conn_state);
 	drm_connector_update_privacy_screen(conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 95efc99..a8d1958 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5403,6 +5403,30 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
 	dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
 }
 
+void intel_dp_set_as_sdp(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
+
+	if (crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) {
+		/*
+		 * hsw_write_infoframe() sets VIDEO_DIP_ENABLE_AS_ADL
+		 * after the payload.
+		 */
+		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
+		return;
+	}
+
+	if (!HAS_AS_SDP(display))
+		return;
+
+	intel_de_write(display, reg,
+		       intel_de_read(display, reg) & ~VIDEO_DIP_ENABLE_AS_ADL);
+	intel_de_posting_read(display, reg);
+}
+
 void intel_dp_set_infoframes(struct intel_encoder *encoder,
 			     bool enable,
 			     const struct intel_crtc_state *crtc_state,
@@ -5414,7 +5438,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
 			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
 			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
 
-	if (HAS_AS_SDP(display))
+	if (!enable && HAS_AS_SDP(display))
 		dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
 
 	u32 val = intel_de_read(display, reg) & ~dip_enable;
@@ -5437,7 +5461,6 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
 		return;
 
 	intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
-	intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
 
 	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae20..342ed75 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -133,6 +133,8 @@ bool intel_dp_needs_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
+void intel_dp_set_as_sdp(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state);
 void intel_read_dp_sdp(struct intel_encoder *encoder,
 		       struct intel_crtc_state *crtc_state,
 		       unsigned int type);
-- 
2.55.0

[PATCH v2] drm/i915/dp: Only send AS SDP when VRR/CMRR is enabled or PR !async

[Xizhe Tang]

A Panther Lake eDP panel that advertises VRR in EDID but runs at a fixed
refresh rate has received an Adaptive-Sync SDP since commit 6a1712052859
("drm/i915/dp: Enable AS SDP whenever VRR is possible or PR !async").
On this panel the first modeset at boot is vertically streaked.

intel_vrr_possible() is only crtc_state->vrr.flipline != 0. Fixed-refresh
timings program flipline too:

	intel_vrr_compute_fixed_rr_timings():
		/* For fixed rr,  vmin = vmax = flipline */
		crtc_state->vrr.flipline = crtc_state->vrr.vmin;

intel_vrr_compute_config() takes that path when VRR is not actually
enabled (uapi.vrr_enabled is false, or vmin == vmax). Then
intel_dp_needs_as_sdp() is true with `vrr: no, fixed rr: yes`, and
intel_dp_compute_as_sdp() programs DP_AS_SDP_AVT_FIXED_VTOTAL.

Gate the terminal condition on the states that consume the SDP:
crtc_state->vrr.enable (VRR) or crtc_state->cmrr.enable (CMRR / FAVT).
Leave the Panel Replay aux-less-ALPM early-return from the same commit
unchanged.

CMRR is still hard-disabled (is_cmrr_frac_required() has "|| true"), so
cmrr.enable stays false today and the OR is a no-op versus v1 at fixed
refresh. intel_vrr_compute_cmrr_timings() sets cmrr.enable without
vrr.enable; the OR keeps the FAVT branch reachable when CMRR is re-enabled.

This is a no-op while VRR is actually active. It does not fix Adaptive
Sync = Always corruption, nor the non-atomic SDP update named by the
#FIXME above intel_dp_compute_as_sdp(). Trailer is Link:, not Closes:.

Tested on LENOVO 21VG (PTL eDP, 8086:b080), v7.2.6-200.fc44.x86_64,
rebuilding only xe.ko with this hunk:

  Adaptive Sync = Never (Tested-by): vrr: no, fixed rr: yes,
  infoframes enabled: 0x6 (no BIT(3)), zero Adaptive-Sync SDP, panel
  clean. This boot: six s2idle suspend/resume cycles, all clean.

  Adaptive Sync = Always (not Tested-by): vrr: yes, vmin 2016 / vmax 8064,
  infoframes enabled: 0xe, Adaptive-Sync SDP still sent. Panel
  appearance on Always is not claimed.

  CMRR / FAVT: not tested.

On the same panel, Adaptive Sync = Never, first modeset, drm.debug=0xe:

  7.1.13 (clean):     infoframes enabled: 0x4  (VSC only)
  7.2.4  (streaked):  infoframes enabled: 0xc  (VSC + AS SDP,
                      operation mode 1 = DP_AS_SDP_AVT_FIXED_VTOTAL)

  Later dumps of those boots are 0x6 vs 0xe; each non-zero bad mask is
  good | BIT(3).

Changes in v2:
- OR crtc_state->cmrr.enable so CMRR still gets AS SDP (v1 review).
  At fixed refresh v2 matches v1.
  v1: https://lore.kernel.org/r/20260923052937.22817-1-xizheTang2005@163.com

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9252
Fixes: 6a1712052859 ("drm/i915/dp: Enable AS SDP whenever VRR is possible or PR !async")
Cc: stable@vger.kernel.org # 7.2.x
Signed-off-by: Xizhe Tang <xizheTang2005@163.com>
Tested-by: Xizhe Tang <xizheTang2005@163.com> # v7.2.6, PTL eDP, Adaptive Sync=Never
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3115,8 +3115,9 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
 	    !intel_psr_pr_async_video_timing_supported(intel_dp))
 		return true;
 
-	return intel_vrr_possible(crtc_state);
+	return crtc_state->vrr.enable ||
+	       crtc_state->cmrr.enable;
 }
 
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
--
2.47.0

Re: [PATCH v2] drm/i915/dp: Only send AS SDP when VRR/CMRR is enabled or PR !async

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] drm/i915: missing vrr prefix for cmrr access in intel_dp_needs_as_sdp()
--

commit d1eecbeb3255f083df2a9a20caa676b6bc9c6e5e
Author: Xizhe Tang <xizheTang2005@163.com>

drm/i915/dp: Only send AS SDP when VRR/CMRR is enabled or PR !async

This commit modifies the Adaptive-Sync SDP terminal condition to gate on VRR
or CMRR enablement. This change resolves vertically streaked visuals during
the first modeset at boot on fixed refresh rate eDP panels.

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9252

> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3111,7 +3111,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>  	    !intel_psr_pr_async_video_timing_supported(intel_dp))
>  		return true;
>  
> -	return intel_vrr_possible(crtc_state);
> +	return crtc_state->vrr.enable ||
> +	       crtc_state->cmrr.enable;

[Severity: Low]
Will this cause a build failure when compiling intel_dp.c?

Looking at the intel_crtc_state structure in intel_dp_needs_as_sdp(), cmrr is
nested inside the vrr substructure, not directly under crtc_state.

Should this be accessed as crtc_state->vrr.cmrr.enable instead, similar to
how it is safely accessed slightly later in intel_dp_compute_as_sdp()?

>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260923195149.21329-1-xizheTang2005@163.com?part=1