[Bug 110671] Regression: DP outputs out of sync on dual-DP tiled 5k screen

[bugzilla-daemon@freedesktop.org]

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https://bugs.freedesktop.org/show_bug.cgi?id=110671

--- Comment #10 from Denys <d.budelkov@gmail.com> ---
Just added some debug to rc3 and tried to check what happens(in context of
5fc0cbfad4564856ee0f323d3f88a7cff19cc3f1).

So in program_timing_sync() there is preparing of groups of pipes for sync. 
And looks like(in my case) pipe_set[j]->plane_state is always true, 
and all elements > 0 is removed from the pipe_set in this case, 
hence group_size == 1 and dc->hwss.enable_timing_synchronization() newer
called.

Contrary with old check
!pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg) is
always false and we have our sync.

Maybe it should be !pipe_set[j]->plane_state instead of
pipe_set[j]->plane_state ?
I applied this change to my 5.3.0-rc3 build and so far everything looks ok.

I do not understand the purpose of is_blanked or plane_state, maybe with mst
hubs or other stuff it may be a different story, but in my simple config it
looks like just a typo.

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