* [PATCH V4 01/19] accel/amdxdna: Rename NPU3 firmware files
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-09 22:53 ` [PATCH V4 02/19] accel/amdxdna: Remove mmap for doorbell David Zhang
` (17 subsequent siblings)
18 siblings, 0 replies; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello
The NPU3 firmware files will be released as npu.sbin and cert.sbin.
Rename the current firmware names to match the firmware release names,
and add MODULE_FIRMWARE() declarations for the new 17f2_10 npu.sbin and
cert.sbin names.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
---
drivers/accel/amdxdna/amdxdna_pci_drv.c | 2 ++
drivers/accel/amdxdna/npu3_regs.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c
index bb339e641416..d9e2e71d3e05 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.c
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c
@@ -28,6 +28,8 @@ MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
MODULE_FIRMWARE("amdnpu/1502_00/npu_7.sbin");
MODULE_FIRMWARE("amdnpu/17f0_10/npu_7.sbin");
MODULE_FIRMWARE("amdnpu/17f0_11/npu_7.sbin");
+MODULE_FIRMWARE("amdnpu/17f2_10/npu.sbin");
+MODULE_FIRMWARE("amdnpu/17f2_10/cert.sbin");
/*
* 0.0: Initial version
diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
index d76b2e99c308..8d287ef32fff 100644
--- a/drivers/accel/amdxdna/npu3_regs.c
+++ b/drivers/accel/amdxdna/npu3_regs.c
@@ -43,8 +43,8 @@ static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
};
static const struct amdxdna_dev_priv npu3_dev_priv = {
- .npufw_path = "npu.dev.sbin",
- .certfw_path = "cert.dev.sbin",
+ .npufw_path = "npu.sbin",
+ .certfw_path = "cert.sbin",
.mbox_bar = NPU3_MBOX_BAR,
.mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR,
.mbox_info_off = NPU3_MBOX_INFO_OFF,
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH V4 02/19] accel/amdxdna: Remove mmap for doorbell
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
2026-10-09 22:53 ` [PATCH V4 01/19] accel/amdxdna: Rename NPU3 firmware files David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-12 20:37 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 03/19] accel/amdxdna: Add CERT firmware version support David Zhang
` (16 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello
Make kernel submission the default, so mapping the doorbell back to user
space is not needed:
- Remove .mmap handler and use standard drm_gem_mmap.
- Set hwctx->doorbell_offset to AMDXDNA_INVALID_DOORBELL_OFFSET on
context creation so userspace does not receive a valid-looking BAR
offset.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_ctx.c | 20 +--------------
drivers/accel/amdxdna/aie4_pci.c | 33 -------------------------
drivers/accel/amdxdna/aie4_pci.h | 1 -
drivers/accel/amdxdna/amdxdna_pci_drv.c | 17 +------------
drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 -
5 files changed, 2 insertions(+), 70 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
index 8408b0d2696f..8157f2a6fd10 100644
--- a/drivers/accel/amdxdna/aie4_ctx.c
+++ b/drivers/accel/amdxdna/aie4_ctx.c
@@ -158,7 +158,7 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
}
priv->hw_ctx_id = resp.hw_context_id;
- hwctx->doorbell_offset = resp.doorbell_offset;
+ hwctx->doorbell_offset = AMDXDNA_INVALID_DOORBELL_OFFSET;
return 0;
}
@@ -313,21 +313,3 @@ int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
return ret <= 0 ? ret : 0;
}
-
-int aie4_hwctx_valid_doorbell(struct amdxdna_client *client, u32 vm_pgoff)
-{
- struct amdxdna_hwctx *hwctx;
- unsigned long hwctx_id;
- int idx;
-
- idx = srcu_read_lock(&client->hwctx_srcu);
- amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
- if (vm_pgoff == (hwctx->doorbell_offset >> PAGE_SHIFT)) {
- srcu_read_unlock(&client->hwctx_srcu, idx);
- return 1;
- }
- }
- srcu_read_unlock(&client->hwctx_srcu, idx);
-
- return 0;
-}
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index e99ad35870ef..f81c43a1f884 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -524,38 +524,6 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
return 0;
}
-static int aie4_doorbell_mmap(struct amdxdna_client *client, struct vm_area_struct *vma)
-{
- struct amdxdna_dev *xdna = client->xdna;
- struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
- const struct amdxdna_dev_priv *npriv = xdna->dev_info->dev_priv;
- phys_addr_t res_start;
- unsigned long pfn;
- int ret;
-
- if (!aie4_hwctx_valid_doorbell(client, vma->vm_pgoff)) {
- XDNA_ERR(xdna, "Invalid doorbell page offset 0x%lx", vma->vm_pgoff);
- return -EINVAL;
- }
-
- if (vma_pages(vma) != 1) {
- XDNA_ERR(xdna, "can only map one page, got %ld", vma_pages(vma));
- return -EINVAL;
- }
-
- res_start = pci_resource_start(pdev, xdna->dev_info->doorbell_bar) + npriv->doorbell_off;
- pfn = PHYS_PFN(res_start) + vma->vm_pgoff;
- vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
- vm_flags_set(vma, VM_IO | VM_DONTEXPAND | VM_DONTDUMP);
- ret = io_remap_pfn_range(vma, vma->vm_start,
- pfn,
- PAGE_SIZE,
- vma->vm_page_prot);
-
- XDNA_DBG(xdna, "doorbell ret %d", ret);
- return ret;
-}
-
static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args)
{
struct amdxdna_dev *xdna = client->xdna;
@@ -667,7 +635,6 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
.fini = aie4_vf_fini,
.hwctx_init = aie4_hwctx_init,
.hwctx_fini = aie4_hwctx_fini,
- .mmap = aie4_doorbell_mmap,
.cmd_wait = aie4_cmd_wait,
.get_aie_info = aie4_get_info,
};
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 3fd5eace3ed7..c6219544dc0f 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -69,7 +69,6 @@ int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev);
int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx);
int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
-int aie4_hwctx_valid_doorbell(struct amdxdna_client *client, u32 vm_pgoff);
/* aie4_sriov.c */
#if IS_ENABLED(CONFIG_PCI_IOV)
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c
index d9e2e71d3e05..3140af69e29c 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.c
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c
@@ -250,21 +250,6 @@ static int amdxdna_drm_set_state_ioctl(struct drm_device *dev, void *data, struc
return ret;
}
-static int amdxdna_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
-{
- struct drm_file *drm_filp = filp->private_data;
- struct amdxdna_client *client = drm_filp->driver_priv;
- struct amdxdna_dev *xdna = client->xdna;
-
- if (likely(vma->vm_pgoff >= DRM_FILE_PAGE_OFFSET_START))
- return drm_gem_mmap(filp, vma);
-
- if (!xdna->dev_info->ops->mmap)
- return -EOPNOTSUPP;
-
- return xdna->dev_info->ops->mmap(client, vma);
-}
-
static const struct drm_ioctl_desc amdxdna_drm_ioctls[] = {
/* Context */
DRM_IOCTL_DEF_DRV(AMDXDNA_CREATE_HWCTX, amdxdna_drm_create_hwctx_ioctl, 0),
@@ -323,7 +308,7 @@ static const struct file_operations amdxdna_fops = {
.poll = drm_poll,
.read = drm_read,
.llseek = noop_llseek,
- .mmap = amdxdna_drm_gem_mmap,
+ .mmap = drm_gem_mmap,
.show_fdinfo = drm_show_fdinfo,
.fop_flags = FOP_UNSIGNED_OFFSET,
};
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
index a997d27a504d..84c8973e9197 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -57,7 +57,6 @@ struct amdxdna_dev_ops {
int (*resume)(struct amdxdna_dev *xdna);
int (*suspend)(struct amdxdna_dev *xdna);
int (*sriov_configure)(struct amdxdna_dev *xdna, int num_vfs);
- int (*mmap)(struct amdxdna_client *client, struct vm_area_struct *vma);
int (*hwctx_init)(struct amdxdna_hwctx *hwctx);
void (*hwctx_fini)(struct amdxdna_hwctx *hwctx);
int (*hwctx_config)(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 02/19] accel/amdxdna: Remove mmap for doorbell
2026-10-09 22:53 ` [PATCH V4 02/19] accel/amdxdna: Remove mmap for doorbell David Zhang
@ 2026-10-12 20:37 ` Lizhi Hou
0 siblings, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-12 20:37 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello
On 10/9/26 15:53, David Zhang wrote:
> Make kernel submission the default, so mapping the doorbell back to user
> space is not needed:
> - Remove .mmap handler and use standard drm_gem_mmap.
> - Set hwctx->doorbell_offset to AMDXDNA_INVALID_DOORBELL_OFFSET on
> context creation so userspace does not receive a valid-looking BAR
> offset.
>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie4_ctx.c | 20 +--------------
> drivers/accel/amdxdna/aie4_pci.c | 33 -------------------------
> drivers/accel/amdxdna/aie4_pci.h | 1 -
> drivers/accel/amdxdna/amdxdna_pci_drv.c | 17 +------------
> drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 -
> 5 files changed, 2 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
> index 8408b0d2696f..8157f2a6fd10 100644
> --- a/drivers/accel/amdxdna/aie4_ctx.c
> +++ b/drivers/accel/amdxdna/aie4_ctx.c
> @@ -158,7 +158,7 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
> }
>
> priv->hw_ctx_id = resp.hw_context_id;
> - hwctx->doorbell_offset = resp.doorbell_offset;
> + hwctx->doorbell_offset = AMDXDNA_INVALID_DOORBELL_OFFSET;
>
> return 0;
> }
> @@ -313,21 +313,3 @@ int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
>
> return ret <= 0 ? ret : 0;
> }
> -
> -int aie4_hwctx_valid_doorbell(struct amdxdna_client *client, u32 vm_pgoff)
> -{
> - struct amdxdna_hwctx *hwctx;
> - unsigned long hwctx_id;
> - int idx;
> -
> - idx = srcu_read_lock(&client->hwctx_srcu);
> - amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
> - if (vm_pgoff == (hwctx->doorbell_offset >> PAGE_SHIFT)) {
> - srcu_read_unlock(&client->hwctx_srcu, idx);
> - return 1;
> - }
> - }
> - srcu_read_unlock(&client->hwctx_srcu, idx);
> -
> - return 0;
> -}
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index e99ad35870ef..f81c43a1f884 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -524,38 +524,6 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
> return 0;
> }
>
> -static int aie4_doorbell_mmap(struct amdxdna_client *client, struct vm_area_struct *vma)
> -{
> - struct amdxdna_dev *xdna = client->xdna;
> - struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
> - const struct amdxdna_dev_priv *npriv = xdna->dev_info->dev_priv;
> - phys_addr_t res_start;
> - unsigned long pfn;
> - int ret;
> -
> - if (!aie4_hwctx_valid_doorbell(client, vma->vm_pgoff)) {
> - XDNA_ERR(xdna, "Invalid doorbell page offset 0x%lx", vma->vm_pgoff);
> - return -EINVAL;
> - }
> -
> - if (vma_pages(vma) != 1) {
> - XDNA_ERR(xdna, "can only map one page, got %ld", vma_pages(vma));
> - return -EINVAL;
> - }
> -
> - res_start = pci_resource_start(pdev, xdna->dev_info->doorbell_bar) + npriv->doorbell_off;
> - pfn = PHYS_PFN(res_start) + vma->vm_pgoff;
> - vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
> - vm_flags_set(vma, VM_IO | VM_DONTEXPAND | VM_DONTDUMP);
> - ret = io_remap_pfn_range(vma, vma->vm_start,
> - pfn,
> - PAGE_SIZE,
> - vma->vm_page_prot);
> -
> - XDNA_DBG(xdna, "doorbell ret %d", ret);
> - return ret;
> -}
> -
> static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args)
> {
> struct amdxdna_dev *xdna = client->xdna;
> @@ -667,7 +635,6 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
> .fini = aie4_vf_fini,
> .hwctx_init = aie4_hwctx_init,
> .hwctx_fini = aie4_hwctx_fini,
> - .mmap = aie4_doorbell_mmap,
> .cmd_wait = aie4_cmd_wait,
> .get_aie_info = aie4_get_info,
> };
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index 3fd5eace3ed7..c6219544dc0f 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -69,7 +69,6 @@ int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev);
> int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
> void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx);
> int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
> -int aie4_hwctx_valid_doorbell(struct amdxdna_client *client, u32 vm_pgoff);
>
> /* aie4_sriov.c */
> #if IS_ENABLED(CONFIG_PCI_IOV)
> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c
> index d9e2e71d3e05..3140af69e29c 100644
> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.c
> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c
> @@ -250,21 +250,6 @@ static int amdxdna_drm_set_state_ioctl(struct drm_device *dev, void *data, struc
> return ret;
> }
>
> -static int amdxdna_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> -{
> - struct drm_file *drm_filp = filp->private_data;
> - struct amdxdna_client *client = drm_filp->driver_priv;
> - struct amdxdna_dev *xdna = client->xdna;
> -
> - if (likely(vma->vm_pgoff >= DRM_FILE_PAGE_OFFSET_START))
> - return drm_gem_mmap(filp, vma);
> -
> - if (!xdna->dev_info->ops->mmap)
> - return -EOPNOTSUPP;
> -
> - return xdna->dev_info->ops->mmap(client, vma);
> -}
> -
> static const struct drm_ioctl_desc amdxdna_drm_ioctls[] = {
> /* Context */
> DRM_IOCTL_DEF_DRV(AMDXDNA_CREATE_HWCTX, amdxdna_drm_create_hwctx_ioctl, 0),
> @@ -323,7 +308,7 @@ static const struct file_operations amdxdna_fops = {
> .poll = drm_poll,
> .read = drm_read,
> .llseek = noop_llseek,
> - .mmap = amdxdna_drm_gem_mmap,
> + .mmap = drm_gem_mmap,
> .show_fdinfo = drm_show_fdinfo,
> .fop_flags = FOP_UNSIGNED_OFFSET,
> };
> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> index a997d27a504d..84c8973e9197 100644
> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> @@ -57,7 +57,6 @@ struct amdxdna_dev_ops {
> int (*resume)(struct amdxdna_dev *xdna);
> int (*suspend)(struct amdxdna_dev *xdna);
> int (*sriov_configure)(struct amdxdna_dev *xdna, int num_vfs);
> - int (*mmap)(struct amdxdna_client *client, struct vm_area_struct *vma);
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> int (*hwctx_init)(struct amdxdna_hwctx *hwctx);
> void (*hwctx_fini)(struct amdxdna_hwctx *hwctx);
> int (*hwctx_config)(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 03/19] accel/amdxdna: Add CERT firmware version support
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
2026-10-09 22:53 ` [PATCH V4 01/19] accel/amdxdna: Rename NPU3 firmware files David Zhang
2026-10-09 22:53 ` [PATCH V4 02/19] accel/amdxdna: Remove mmap for doorbell David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-12 20:39 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 04/19] accel/amdxdna: Support firmware 6.0 David Zhang
` (15 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello
Add support to query and validate CERT firmware version:
- Add mailbox opcodes and structs to query NPU firmware version (identify)
and CERT firmware version.
- Unify firmware version storage by using struct
amdxdna_drm_query_firmware_version across the driver.
- Pass the feature table to aie_check_protocol() and add
cert_feature_tbl to validate CERT firmware host queue protocol
compatibility against driver capabilities.
- Add helper functions amdxdna_get_firmware_version() and
amdxdna_get_aie_version() to share version query handling across
generations.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie.c | 33 ++++++++++++++--
drivers/accel/amdxdna/aie.h | 11 +++++-
drivers/accel/amdxdna/aie2_message.c | 4 +-
drivers/accel/amdxdna/aie2_pci.c | 50 ++++---------------------
drivers/accel/amdxdna/aie2_pci.h | 4 +-
drivers/accel/amdxdna/aie4_message.c | 46 +++++++++++++++++++++++
drivers/accel/amdxdna/aie4_msg_priv.h | 30 +++++++++++++++
drivers/accel/amdxdna/aie4_pci.c | 20 +++++++++-
drivers/accel/amdxdna/aie4_pci.h | 11 ++++++
drivers/accel/amdxdna/amdxdna_pci_drv.h | 10 +----
drivers/accel/amdxdna/amdxdna_sysfs.c | 2 +-
drivers/accel/amdxdna/npu3_regs.c | 7 ++++
12 files changed, 163 insertions(+), 65 deletions(-)
diff --git a/drivers/accel/amdxdna/aie.c b/drivers/accel/amdxdna/aie.c
index dd6f36f222c7..c328ce2f19af 100644
--- a/drivers/accel/amdxdna/aie.c
+++ b/drivers/accel/amdxdna/aie.c
@@ -65,13 +65,12 @@ int aie_send_mgmt_msg_wait(struct aie_device *aie, struct xdna_mailbox_msg *msg)
return ret;
}
-int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor)
+int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor,
+ const struct amdxdna_fw_feature_tbl *feature)
{
- const struct amdxdna_fw_feature_tbl *feature;
bool found = false;
- for (feature = aie->xdna->dev_info->fw_feature_tbl;
- feature->major; feature++) {
+ for (; feature && feature->major; feature++) {
if (feature->major != fw_major)
continue;
if (fw_minor < feature->min_minor)
@@ -88,6 +87,32 @@ int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor)
return found ? 0 : -EOPNOTSUPP;
}
+int amdxdna_get_aie_version(struct amdxdna_client *client,
+ struct amdxdna_drm_get_info *args,
+ struct amdxdna_drm_query_aie_version *version)
+{
+ u32 buf_sz;
+
+ buf_sz = min_t(u32, args->buffer_size, sizeof(*version));
+ if (copy_to_user(u64_to_user_ptr(args->buffer), version, buf_sz))
+ return -EFAULT;
+
+ return 0;
+}
+
+int amdxdna_get_firmware_version(struct amdxdna_client *client,
+ struct amdxdna_drm_get_info *args,
+ struct amdxdna_drm_query_firmware_version *version)
+{
+ u32 buf_sz;
+
+ buf_sz = min_t(u32, args->buffer_size, sizeof(*version));
+ if (copy_to_user(u64_to_user_ptr(args->buffer), version, buf_sz))
+ return -EFAULT;
+
+ return 0;
+}
+
static void amdxdna_update_vbnv(struct amdxdna_dev *xdna,
const struct amdxdna_rev_vbnv *tbl,
u32 rev)
diff --git a/drivers/accel/amdxdna/aie.h b/drivers/accel/amdxdna/aie.h
index 0483d582b7f8..229b3cfa2361 100644
--- a/drivers/accel/amdxdna/aie.h
+++ b/drivers/accel/amdxdna/aie.h
@@ -28,6 +28,7 @@ struct aie_device {
struct psp_device *psp_hdl;
struct smu_device *smu_hdl;
+ struct amdxdna_drm_query_aie_version version;
struct amdxdna_drm_query_aie_metadata metadata;
};
@@ -95,7 +96,8 @@ struct amdxdna_rev_vbnv {
void aie_dump_mgmt_chann_debug(struct aie_device *aie);
void aie_destroy_chann(struct aie_device *aie, struct mailbox_channel **chann);
int aie_send_mgmt_msg_wait(struct aie_device *aie, struct xdna_mailbox_msg *msg);
-int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor);
+int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor,
+ const struct amdxdna_fw_feature_tbl *feature);
void amdxdna_vbnv_init(struct amdxdna_dev *xdna);
int amdxdna_get_metadata(struct aie_device *aie, struct amdxdna_client *client,
struct amdxdna_drm_get_info *args);
@@ -103,7 +105,12 @@ void *amdxdna_alloc_msg_buffer(struct amdxdna_dev *xdna, u32 *size,
dma_addr_t *dma_addr);
void amdxdna_free_msg_buffer(struct amdxdna_dev *xdna, size_t size,
void *cpu_addr, dma_addr_t dma_addr);
-
+int amdxdna_get_aie_version(struct amdxdna_client *client,
+ struct amdxdna_drm_get_info *args,
+ struct amdxdna_drm_query_aie_version *version);
+int amdxdna_get_firmware_version(struct amdxdna_client *client,
+ struct amdxdna_drm_get_info *args,
+ struct amdxdna_drm_query_firmware_version *version);
/* aie_psp.c */
struct psp_device *aiem_psp_create(struct drm_device *ddev, struct psp_config *conf);
int aie_psp_start(struct psp_device *psp);
diff --git a/drivers/accel/amdxdna/aie2_message.c b/drivers/accel/amdxdna/aie2_message.c
index 56b919b350ac..d95a18af9b09 100644
--- a/drivers/accel/amdxdna/aie2_message.c
+++ b/drivers/accel/amdxdna/aie2_message.c
@@ -149,7 +149,7 @@ int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
}
int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
- struct amdxdna_fw_ver *fw_ver)
+ struct amdxdna_drm_query_firmware_version *fw_ver)
{
DECLARE_AIE_MSG(firmware_version, MSG_OP_GET_FIRMWARE_VERSION);
int ret;
@@ -160,7 +160,7 @@ int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
fw_ver->major = resp.major;
fw_ver->minor = resp.minor;
- fw_ver->sub = resp.sub;
+ fw_ver->patch = resp.sub;
fw_ver->build = resp.build;
return 0;
diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c
index d2fa46e4d3a4..6fa79698f9d8 100644
--- a/drivers/accel/amdxdna/aie2_pci.c
+++ b/drivers/accel/amdxdna/aie2_pci.c
@@ -115,7 +115,8 @@ static int aie2_get_mgmt_chann_info(struct amdxdna_dev_hdl *ndev)
ndev->aie.mgmt_prot_minor = info_regs.prot_minor;
ret = aie_check_protocol(&ndev->aie, ndev->aie.mgmt_prot_major,
- ndev->aie.mgmt_prot_minor);
+ ndev->aie.mgmt_prot_minor,
+ ndev->aie.xdna->dev_info->fw_feature_tbl);
done:
aie_dump_mgmt_chann_debug(&ndev->aie);
@@ -206,15 +207,16 @@ static int aie2_mgmt_fw_init(struct amdxdna_dev_hdl *ndev)
static int aie2_mgmt_fw_query(struct amdxdna_dev_hdl *ndev)
{
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
int ret;
- ret = aie2_query_firmware_version(ndev, &ndev->aie.xdna->fw_ver);
+ ret = aie2_query_firmware_version(ndev, &xdna->fw_ver);
if (ret) {
XDNA_ERR(ndev->aie.xdna, "query firmware version failed");
return ret;
}
- ret = aie2_query_aie_version(ndev, &ndev->version);
+ ret = aie2_query_aie_version(ndev, &ndev->aie.version);
if (ret) {
XDNA_ERR(ndev->aie.xdna, "Query AIE version failed");
return ret;
@@ -684,44 +686,6 @@ static int aie2_get_aie_status(struct amdxdna_client *client,
return 0;
}
-static int aie2_get_aie_version(struct amdxdna_client *client,
- struct amdxdna_drm_get_info *args)
-{
- struct amdxdna_drm_query_aie_version version;
- struct amdxdna_dev *xdna = client->xdna;
- struct amdxdna_dev_hdl *ndev;
- u32 buf_sz;
-
- ndev = xdna->dev_handle;
- version.major = ndev->version.major;
- version.minor = ndev->version.minor;
-
- buf_sz = min(args->buffer_size, sizeof(version));
- if (copy_to_user(u64_to_user_ptr(args->buffer), &version, buf_sz))
- return -EFAULT;
-
- return 0;
-}
-
-static int aie2_get_firmware_version(struct amdxdna_client *client,
- struct amdxdna_drm_get_info *args)
-{
- struct amdxdna_drm_query_firmware_version version;
- struct amdxdna_dev *xdna = client->xdna;
- u32 buf_sz;
-
- version.major = xdna->fw_ver.major;
- version.minor = xdna->fw_ver.minor;
- version.patch = xdna->fw_ver.sub;
- version.build = xdna->fw_ver.build;
-
- buf_sz = min(args->buffer_size, sizeof(version));
- if (copy_to_user(u64_to_user_ptr(args->buffer), &version, buf_sz))
- return -EFAULT;
-
- return 0;
-}
-
static int aie2_get_power_mode(struct amdxdna_client *client,
struct amdxdna_drm_get_info *args)
{
@@ -1036,7 +1000,7 @@ static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
ret = amdxdna_get_metadata(&ndev->aie, client, args);
break;
case DRM_AMDXDNA_QUERY_AIE_VERSION:
- ret = aie2_get_aie_version(client, args);
+ ret = amdxdna_get_aie_version(client, args, &ndev->aie.version);
break;
case DRM_AMDXDNA_QUERY_CLOCK_METADATA:
ret = aie2_get_clock_metadata(client, args);
@@ -1048,7 +1012,7 @@ static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
ret = aie2_get_hwctx_status(client, args);
break;
case DRM_AMDXDNA_QUERY_FIRMWARE_VERSION:
- ret = aie2_get_firmware_version(client, args);
+ ret = amdxdna_get_firmware_version(client, args, &xdna->fw_ver);
break;
case DRM_AMDXDNA_GET_POWER_MODE:
ret = aie2_get_power_mode(client, args);
diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h
index a5fd71329b93..b31f73082c17 100644
--- a/drivers/accel/amdxdna/aie2_pci.h
+++ b/drivers/accel/amdxdna/aie2_pci.h
@@ -74,7 +74,6 @@ enum aie2_sram_reg_idx {
};
struct amdxdna_client;
-struct amdxdna_fw_ver;
struct amdxdna_hwctx;
struct amdxdna_sched_job;
@@ -150,7 +149,6 @@ struct amdxdna_dev_hdl {
void __iomem *mbox_base;
u32 total_col;
- struct amdxdna_drm_query_aie_version version;
struct aie2_exec_msg_ops *exec_msg_ops;
struct drm_gpu_scheduler *hwctx_sched;
struct ida hwctx_sched_ida;
@@ -263,7 +261,7 @@ int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev,
int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_aie_metadata *metadata);
int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
- struct amdxdna_fw_ver *fw_ver);
+ struct amdxdna_drm_query_firmware_version *fw_ver);
int aie2_query_app_health(struct amdxdna_dev_hdl *ndev, u32 context_id,
struct app_health_report *report);
int aie2_get_dev_revision(struct amdxdna_dev_hdl *ndev, enum aie2_dev_revision *rev);
diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
index 88037edbb02a..53f8e366b66c 100644
--- a/drivers/accel/amdxdna/aie4_message.c
+++ b/drivers/accel/amdxdna/aie4_message.c
@@ -64,6 +64,52 @@ int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
return 0;
}
+int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
+ struct amdxdna_drm_query_firmware_version *fw_version)
+{
+ DECLARE_AIE_MSG(aie4_msg_identify, AIE4_MSG_OP_IDENTIFY);
+ int ret;
+
+ ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ if (ret)
+ return ret;
+
+ fw_version->major = resp.fw_major;
+ fw_version->minor = resp.fw_minor;
+ fw_version->patch = resp.fw_patch;
+ fw_version->build = resp.fw_build;
+
+ return 0;
+}
+
+int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
+ struct amdxdna_drm_query_firmware_version *cert_version)
+{
+ DECLARE_AIE_MSG(aie4_msg_query_cert_firmware_version,
+ AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION);
+ int ret;
+
+ ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ if (ret)
+ return ret;
+
+ ret = aie_check_protocol(&ndev->aie,
+ resp.host_queue_major, resp.host_queue_minor,
+ ndev->aie.xdna->dev_info->cert_feature_tbl);
+ if (ret) {
+ XDNA_ERR(ndev->aie.xdna, "host queue %d.%d is not supported",
+ resp.host_queue_major, resp.host_queue_minor);
+ return ret;
+ }
+
+ cert_version->major = resp.major_version;
+ cert_version->minor = resp.minor_version;
+ cert_version->patch = resp.hotfix;
+ cert_version->build = resp.build;
+
+ return 0;
+}
+
int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev)
{
DECLARE_AIE_MSG(aie4_msg_attach_work_buffer, AIE4_MSG_OP_ATTACH_WORK_BUFFER);
diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
index af0866045b91..5b97c8057de0 100644
--- a/drivers/accel/amdxdna/aie4_msg_priv.h
+++ b/drivers/accel/amdxdna/aie4_msg_priv.h
@@ -10,8 +10,10 @@
#include <linux/types.h>
enum aie4_msg_opcode {
+ AIE4_MSG_OP_IDENTIFY = 0x10002,
AIE4_MSG_OP_SUSPEND = 0x10003,
AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x1000D,
+ AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F,
AIE4_MSG_OP_CREATE_VFS = 0x20001,
AIE4_MSG_OP_DESTROY_VFS = 0x20002,
@@ -30,6 +32,18 @@ enum aie4_msg_status {
MAX_AIE4_MSG_STATUS_CODE = 0x4,
};
+struct aie4_msg_identify_req {
+ __u32 rsvd;
+} __packed;
+
+struct aie4_msg_identify_resp {
+ enum aie4_msg_status status;
+ __u32 fw_major;
+ __u32 fw_minor;
+ __u32 fw_patch;
+ __u32 fw_build;
+} __packed;
+
struct aie4_msg_suspend_req {
__u32 rsvd;
} __packed;
@@ -132,6 +146,22 @@ struct aie4_msg_aie4_tile_info_resp {
struct aie4_tile_info info;
} __packed;
+struct aie4_msg_query_cert_firmware_version_req {
+ __u32 resvd;
+} __packed;
+
+struct aie4_msg_query_cert_firmware_version_resp {
+ enum aie4_msg_status status;
+ __u8 major_version;
+ __u8 minor_version;
+ __u8 git_hash[41];
+ __u8 date[11];
+ __u8 hotfix;
+ __u8 build;
+ __u16 host_queue_major;
+ __u16 host_queue_minor;
+} __packed;
+
#define AIE4_WORK_BUFFER_MIN_SIZE SZ_4M
struct aie4_msg_attach_work_buffer_req {
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index f81c43a1f884..e9cd2af224d3 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -90,7 +90,8 @@ static int aie4_mailbox_info(struct amdxdna_dev *xdna,
ret = aie_check_protocol(&xdna->dev_handle->aie,
mbox_info->protocol_major,
- mbox_info->protocol_minor);
+ mbox_info->protocol_minor,
+ xdna->dev_info->fw_feature_tbl);
if (ret)
XDNA_ERR(xdna, "mailbox major.minor %d.%d is not supported",
mbox_info->protocol_major, mbox_info->protocol_minor);
@@ -277,7 +278,22 @@ static void aie4_partition_fini(struct amdxdna_dev_hdl *ndev)
static int aie4_query(struct amdxdna_dev_hdl *ndev)
{
- return aie4_query_aie_metadata(ndev, &ndev->aie.metadata);
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ int ret;
+
+ ret = aie4_query_npu_firmware_version(ndev, &xdna->fw_ver);
+ if (ret)
+ return ret;
+
+ ret = aie4_query_cert_firmware_version(ndev, &ndev->cert_version);
+ if (ret)
+ return ret;
+
+ ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata);
+ if (ret)
+ return ret;
+
+ return 0;
}
static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index c6219544dc0f..8c62ee6a9b23 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -57,6 +57,13 @@ struct amdxdna_dev_hdl {
void *work_buf;
dma_addr_t work_buf_addr;
u32 work_buf_size;
+
+ struct amdxdna_drm_query_firmware_version cert_version;
+};
+
+enum aie4_fw_feature {
+ AIE4_HSA_COMMAND = 5,
+ AIE4_FEATURE_MAX
};
/* aie4_message.c */
@@ -64,6 +71,10 @@ int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_aie_metadata *metadata);
int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev);
int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev);
+int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
+ struct amdxdna_drm_query_firmware_version *fw_version);
+int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
+ struct amdxdna_drm_query_firmware_version *cert_version);
/* aie4_ctx.c */
int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
index 84c8973e9197..0002e6ef32ba 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -99,16 +99,10 @@ struct amdxdna_dev_info {
size_t dev_heap_max_size;
const struct amdxdna_dev_priv *dev_priv;
const struct amdxdna_fw_feature_tbl *fw_feature_tbl;
+ const struct amdxdna_fw_feature_tbl *cert_feature_tbl;
const struct amdxdna_dev_ops *ops;
};
-struct amdxdna_fw_ver {
- u32 major;
- u32 minor;
- u32 sub;
- u32 build;
-};
-
struct amdxdna_carveout;
struct amdxdna_dev {
@@ -120,7 +114,7 @@ struct amdxdna_dev {
struct mutex dev_lock; /* per device lock */
struct list_head client_list;
struct mutex client_lock; /* client_list */
- struct amdxdna_fw_ver fw_ver;
+ struct amdxdna_drm_query_firmware_version fw_ver;
struct rw_semaphore notifier_lock; /* for mmu notifier*/
struct workqueue_struct *notifier_wq;
diff --git a/drivers/accel/amdxdna/amdxdna_sysfs.c b/drivers/accel/amdxdna/amdxdna_sysfs.c
index d9e359ee8182..e20b7fb1e5d1 100644
--- a/drivers/accel/amdxdna/amdxdna_sysfs.c
+++ b/drivers/accel/amdxdna/amdxdna_sysfs.c
@@ -37,7 +37,7 @@ static ssize_t fw_version_show(struct device *dev, struct device_attribute *attr
struct amdxdna_dev *xdna = dev_get_drvdata(dev);
return sprintf(buf, "%d.%d.%d.%d\n", xdna->fw_ver.major,
- xdna->fw_ver.minor, xdna->fw_ver.sub,
+ xdna->fw_ver.minor, xdna->fw_ver.patch,
xdna->fw_ver.build);
}
static DEVICE_ATTR_RO(fw_version);
diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
index 8d287ef32fff..e82bc0a4f597 100644
--- a/drivers/accel/amdxdna/npu3_regs.c
+++ b/drivers/accel/amdxdna/npu3_regs.c
@@ -42,6 +42,11 @@ static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
{ 0 }
};
+static const struct amdxdna_fw_feature_tbl npu3_cert_feature_table[] = {
+ { .features = BIT_U64(AIE4_HSA_COMMAND), .major = 1, .min_minor = 0 },
+ { 0 }
+};
+
static const struct amdxdna_dev_priv npu3_dev_priv = {
.npufw_path = "npu.sbin",
.certfw_path = "cert.sbin",
@@ -85,6 +90,7 @@ const struct amdxdna_dev_info dev_npu3_pf_info = {
.device_type = AMDXDNA_DEV_TYPE_PF,
.dev_priv = &npu3_dev_priv,
.fw_feature_tbl = npu3_fw_feature_table,
+ .cert_feature_tbl = npu3_cert_feature_table,
.ops = &aie4_pf_ops,
};
@@ -96,5 +102,6 @@ const struct amdxdna_dev_info dev_npu3_vf_info = {
.device_type = AMDXDNA_DEV_TYPE_UMQ,
.dev_priv = &npu3_dev_vf_priv,
.fw_feature_tbl = npu3_fw_feature_table,
+ .cert_feature_tbl = npu3_cert_feature_table,
.ops = &aie4_vf_ops,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 03/19] accel/amdxdna: Add CERT firmware version support
2026-10-09 22:53 ` [PATCH V4 03/19] accel/amdxdna: Add CERT firmware version support David Zhang
@ 2026-10-12 20:39 ` Lizhi Hou
0 siblings, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-12 20:39 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello
On 10/9/26 15:53, David Zhang wrote:
> Add support to query and validate CERT firmware version:
> - Add mailbox opcodes and structs to query NPU firmware version (identify)
> and CERT firmware version.
> - Unify firmware version storage by using struct
> amdxdna_drm_query_firmware_version across the driver.
> - Pass the feature table to aie_check_protocol() and add
> cert_feature_tbl to validate CERT firmware host queue protocol
> compatibility against driver capabilities.
> - Add helper functions amdxdna_get_firmware_version() and
> amdxdna_get_aie_version() to share version query handling across
> generations.
>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie.c | 33 ++++++++++++++--
> drivers/accel/amdxdna/aie.h | 11 +++++-
> drivers/accel/amdxdna/aie2_message.c | 4 +-
> drivers/accel/amdxdna/aie2_pci.c | 50 ++++---------------------
> drivers/accel/amdxdna/aie2_pci.h | 4 +-
> drivers/accel/amdxdna/aie4_message.c | 46 +++++++++++++++++++++++
> drivers/accel/amdxdna/aie4_msg_priv.h | 30 +++++++++++++++
> drivers/accel/amdxdna/aie4_pci.c | 20 +++++++++-
> drivers/accel/amdxdna/aie4_pci.h | 11 ++++++
> drivers/accel/amdxdna/amdxdna_pci_drv.h | 10 +----
> drivers/accel/amdxdna/amdxdna_sysfs.c | 2 +-
> drivers/accel/amdxdna/npu3_regs.c | 7 ++++
> 12 files changed, 163 insertions(+), 65 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie.c b/drivers/accel/amdxdna/aie.c
> index dd6f36f222c7..c328ce2f19af 100644
> --- a/drivers/accel/amdxdna/aie.c
> +++ b/drivers/accel/amdxdna/aie.c
> @@ -65,13 +65,12 @@ int aie_send_mgmt_msg_wait(struct aie_device *aie, struct xdna_mailbox_msg *msg)
> return ret;
> }
>
> -int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor)
> +int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor,
> + const struct amdxdna_fw_feature_tbl *feature)
> {
> - const struct amdxdna_fw_feature_tbl *feature;
> bool found = false;
>
> - for (feature = aie->xdna->dev_info->fw_feature_tbl;
> - feature->major; feature++) {
> + for (; feature && feature->major; feature++) {
> if (feature->major != fw_major)
> continue;
> if (fw_minor < feature->min_minor)
> @@ -88,6 +87,32 @@ int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor)
> return found ? 0 : -EOPNOTSUPP;
> }
>
> +int amdxdna_get_aie_version(struct amdxdna_client *client,
> + struct amdxdna_drm_get_info *args,
> + struct amdxdna_drm_query_aie_version *version)
> +{
> + u32 buf_sz;
> +
> + buf_sz = min_t(u32, args->buffer_size, sizeof(*version));
> + if (copy_to_user(u64_to_user_ptr(args->buffer), version, buf_sz))
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> +int amdxdna_get_firmware_version(struct amdxdna_client *client,
> + struct amdxdna_drm_get_info *args,
> + struct amdxdna_drm_query_firmware_version *version)
> +{
> + u32 buf_sz;
> +
> + buf_sz = min_t(u32, args->buffer_size, sizeof(*version));
> + if (copy_to_user(u64_to_user_ptr(args->buffer), version, buf_sz))
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> static void amdxdna_update_vbnv(struct amdxdna_dev *xdna,
> const struct amdxdna_rev_vbnv *tbl,
> u32 rev)
> diff --git a/drivers/accel/amdxdna/aie.h b/drivers/accel/amdxdna/aie.h
> index 0483d582b7f8..229b3cfa2361 100644
> --- a/drivers/accel/amdxdna/aie.h
> +++ b/drivers/accel/amdxdna/aie.h
> @@ -28,6 +28,7 @@ struct aie_device {
> struct psp_device *psp_hdl;
> struct smu_device *smu_hdl;
>
> + struct amdxdna_drm_query_aie_version version;
> struct amdxdna_drm_query_aie_metadata metadata;
> };
>
> @@ -95,7 +96,8 @@ struct amdxdna_rev_vbnv {
> void aie_dump_mgmt_chann_debug(struct aie_device *aie);
> void aie_destroy_chann(struct aie_device *aie, struct mailbox_channel **chann);
> int aie_send_mgmt_msg_wait(struct aie_device *aie, struct xdna_mailbox_msg *msg);
> -int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor);
> +int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor,
> + const struct amdxdna_fw_feature_tbl *feature);
> void amdxdna_vbnv_init(struct amdxdna_dev *xdna);
> int amdxdna_get_metadata(struct aie_device *aie, struct amdxdna_client *client,
> struct amdxdna_drm_get_info *args);
> @@ -103,7 +105,12 @@ void *amdxdna_alloc_msg_buffer(struct amdxdna_dev *xdna, u32 *size,
> dma_addr_t *dma_addr);
> void amdxdna_free_msg_buffer(struct amdxdna_dev *xdna, size_t size,
> void *cpu_addr, dma_addr_t dma_addr);
> -
> +int amdxdna_get_aie_version(struct amdxdna_client *client,
> + struct amdxdna_drm_get_info *args,
> + struct amdxdna_drm_query_aie_version *version);
> +int amdxdna_get_firmware_version(struct amdxdna_client *client,
> + struct amdxdna_drm_get_info *args,
> + struct amdxdna_drm_query_firmware_version *version);
> /* aie_psp.c */
> struct psp_device *aiem_psp_create(struct drm_device *ddev, struct psp_config *conf);
> int aie_psp_start(struct psp_device *psp);
> diff --git a/drivers/accel/amdxdna/aie2_message.c b/drivers/accel/amdxdna/aie2_message.c
> index 56b919b350ac..d95a18af9b09 100644
> --- a/drivers/accel/amdxdna/aie2_message.c
> +++ b/drivers/accel/amdxdna/aie2_message.c
> @@ -149,7 +149,7 @@ int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
> }
>
> int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
> - struct amdxdna_fw_ver *fw_ver)
> + struct amdxdna_drm_query_firmware_version *fw_ver)
> {
> DECLARE_AIE_MSG(firmware_version, MSG_OP_GET_FIRMWARE_VERSION);
> int ret;
> @@ -160,7 +160,7 @@ int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
>
> fw_ver->major = resp.major;
> fw_ver->minor = resp.minor;
> - fw_ver->sub = resp.sub;
> + fw_ver->patch = resp.sub;
> fw_ver->build = resp.build;
>
> return 0;
> diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c
> index d2fa46e4d3a4..6fa79698f9d8 100644
> --- a/drivers/accel/amdxdna/aie2_pci.c
> +++ b/drivers/accel/amdxdna/aie2_pci.c
> @@ -115,7 +115,8 @@ static int aie2_get_mgmt_chann_info(struct amdxdna_dev_hdl *ndev)
> ndev->aie.mgmt_prot_minor = info_regs.prot_minor;
>
> ret = aie_check_protocol(&ndev->aie, ndev->aie.mgmt_prot_major,
> - ndev->aie.mgmt_prot_minor);
> + ndev->aie.mgmt_prot_minor,
> + ndev->aie.xdna->dev_info->fw_feature_tbl);
>
> done:
> aie_dump_mgmt_chann_debug(&ndev->aie);
> @@ -206,15 +207,16 @@ static int aie2_mgmt_fw_init(struct amdxdna_dev_hdl *ndev)
>
> static int aie2_mgmt_fw_query(struct amdxdna_dev_hdl *ndev)
> {
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> int ret;
>
> - ret = aie2_query_firmware_version(ndev, &ndev->aie.xdna->fw_ver);
> + ret = aie2_query_firmware_version(ndev, &xdna->fw_ver);
> if (ret) {
> XDNA_ERR(ndev->aie.xdna, "query firmware version failed");
> return ret;
> }
>
> - ret = aie2_query_aie_version(ndev, &ndev->version);
> + ret = aie2_query_aie_version(ndev, &ndev->aie.version);
> if (ret) {
> XDNA_ERR(ndev->aie.xdna, "Query AIE version failed");
> return ret;
> @@ -684,44 +686,6 @@ static int aie2_get_aie_status(struct amdxdna_client *client,
> return 0;
> }
>
> -static int aie2_get_aie_version(struct amdxdna_client *client,
> - struct amdxdna_drm_get_info *args)
> -{
> - struct amdxdna_drm_query_aie_version version;
> - struct amdxdna_dev *xdna = client->xdna;
> - struct amdxdna_dev_hdl *ndev;
> - u32 buf_sz;
> -
> - ndev = xdna->dev_handle;
> - version.major = ndev->version.major;
> - version.minor = ndev->version.minor;
> -
> - buf_sz = min(args->buffer_size, sizeof(version));
> - if (copy_to_user(u64_to_user_ptr(args->buffer), &version, buf_sz))
> - return -EFAULT;
> -
> - return 0;
> -}
> -
> -static int aie2_get_firmware_version(struct amdxdna_client *client,
> - struct amdxdna_drm_get_info *args)
> -{
> - struct amdxdna_drm_query_firmware_version version;
> - struct amdxdna_dev *xdna = client->xdna;
> - u32 buf_sz;
> -
> - version.major = xdna->fw_ver.major;
> - version.minor = xdna->fw_ver.minor;
> - version.patch = xdna->fw_ver.sub;
> - version.build = xdna->fw_ver.build;
> -
> - buf_sz = min(args->buffer_size, sizeof(version));
> - if (copy_to_user(u64_to_user_ptr(args->buffer), &version, buf_sz))
> - return -EFAULT;
> -
> - return 0;
> -}
> -
> static int aie2_get_power_mode(struct amdxdna_client *client,
> struct amdxdna_drm_get_info *args)
> {
> @@ -1036,7 +1000,7 @@ static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
> ret = amdxdna_get_metadata(&ndev->aie, client, args);
> break;
> case DRM_AMDXDNA_QUERY_AIE_VERSION:
> - ret = aie2_get_aie_version(client, args);
> + ret = amdxdna_get_aie_version(client, args, &ndev->aie.version);
> break;
> case DRM_AMDXDNA_QUERY_CLOCK_METADATA:
> ret = aie2_get_clock_metadata(client, args);
> @@ -1048,7 +1012,7 @@ static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
> ret = aie2_get_hwctx_status(client, args);
> break;
> case DRM_AMDXDNA_QUERY_FIRMWARE_VERSION:
> - ret = aie2_get_firmware_version(client, args);
> + ret = amdxdna_get_firmware_version(client, args, &xdna->fw_ver);
> break;
> case DRM_AMDXDNA_GET_POWER_MODE:
> ret = aie2_get_power_mode(client, args);
> diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h
> index a5fd71329b93..b31f73082c17 100644
> --- a/drivers/accel/amdxdna/aie2_pci.h
> +++ b/drivers/accel/amdxdna/aie2_pci.h
> @@ -74,7 +74,6 @@ enum aie2_sram_reg_idx {
> };
>
> struct amdxdna_client;
> -struct amdxdna_fw_ver;
> struct amdxdna_hwctx;
> struct amdxdna_sched_job;
>
> @@ -150,7 +149,6 @@ struct amdxdna_dev_hdl {
> void __iomem *mbox_base;
>
> u32 total_col;
> - struct amdxdna_drm_query_aie_version version;
> struct aie2_exec_msg_ops *exec_msg_ops;
> struct drm_gpu_scheduler *hwctx_sched;
> struct ida hwctx_sched_ida;
> @@ -263,7 +261,7 @@ int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev,
> int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_aie_metadata *metadata);
> int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
> - struct amdxdna_fw_ver *fw_ver);
> + struct amdxdna_drm_query_firmware_version *fw_ver);
> int aie2_query_app_health(struct amdxdna_dev_hdl *ndev, u32 context_id,
> struct app_health_report *report);
> int aie2_get_dev_revision(struct amdxdna_dev_hdl *ndev, enum aie2_dev_revision *rev);
> diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
> index 88037edbb02a..53f8e366b66c 100644
> --- a/drivers/accel/amdxdna/aie4_message.c
> +++ b/drivers/accel/amdxdna/aie4_message.c
> @@ -64,6 +64,52 @@ int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
> return 0;
> }
>
> +int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
> + struct amdxdna_drm_query_firmware_version *fw_version)
> +{
> + DECLARE_AIE_MSG(aie4_msg_identify, AIE4_MSG_OP_IDENTIFY);
> + int ret;
> +
> + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> + if (ret)
> + return ret;
> +
> + fw_version->major = resp.fw_major;
> + fw_version->minor = resp.fw_minor;
> + fw_version->patch = resp.fw_patch;
> + fw_version->build = resp.fw_build;
> +
> + return 0;
> +}
> +
> +int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
> + struct amdxdna_drm_query_firmware_version *cert_version)
> +{
> + DECLARE_AIE_MSG(aie4_msg_query_cert_firmware_version,
> + AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION);
> + int ret;
> +
> + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> + if (ret)
> + return ret;
> +
> + ret = aie_check_protocol(&ndev->aie,
> + resp.host_queue_major, resp.host_queue_minor,
> + ndev->aie.xdna->dev_info->cert_feature_tbl);
> + if (ret) {
> + XDNA_ERR(ndev->aie.xdna, "host queue %d.%d is not supported",
> + resp.host_queue_major, resp.host_queue_minor);
> + return ret;
> + }
> +
> + cert_version->major = resp.major_version;
> + cert_version->minor = resp.minor_version;
> + cert_version->patch = resp.hotfix;
> + cert_version->build = resp.build;
> +
> + return 0;
> +}
> +
> int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev)
> {
> DECLARE_AIE_MSG(aie4_msg_attach_work_buffer, AIE4_MSG_OP_ATTACH_WORK_BUFFER);
> diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
> index af0866045b91..5b97c8057de0 100644
> --- a/drivers/accel/amdxdna/aie4_msg_priv.h
> +++ b/drivers/accel/amdxdna/aie4_msg_priv.h
> @@ -10,8 +10,10 @@
> #include <linux/types.h>
>
> enum aie4_msg_opcode {
> + AIE4_MSG_OP_IDENTIFY = 0x10002,
> AIE4_MSG_OP_SUSPEND = 0x10003,
> AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x1000D,
> + AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F,
>
> AIE4_MSG_OP_CREATE_VFS = 0x20001,
> AIE4_MSG_OP_DESTROY_VFS = 0x20002,
> @@ -30,6 +32,18 @@ enum aie4_msg_status {
> MAX_AIE4_MSG_STATUS_CODE = 0x4,
> };
>
> +struct aie4_msg_identify_req {
> + __u32 rsvd;
> +} __packed;
> +
> +struct aie4_msg_identify_resp {
> + enum aie4_msg_status status;
> + __u32 fw_major;
> + __u32 fw_minor;
> + __u32 fw_patch;
> + __u32 fw_build;
> +} __packed;
> +
> struct aie4_msg_suspend_req {
> __u32 rsvd;
> } __packed;
> @@ -132,6 +146,22 @@ struct aie4_msg_aie4_tile_info_resp {
> struct aie4_tile_info info;
> } __packed;
>
> +struct aie4_msg_query_cert_firmware_version_req {
> + __u32 resvd;
> +} __packed;
> +
> +struct aie4_msg_query_cert_firmware_version_resp {
> + enum aie4_msg_status status;
> + __u8 major_version;
> + __u8 minor_version;
> + __u8 git_hash[41];
> + __u8 date[11];
> + __u8 hotfix;
> + __u8 build;
> + __u16 host_queue_major;
> + __u16 host_queue_minor;
> +} __packed;
> +
> #define AIE4_WORK_BUFFER_MIN_SIZE SZ_4M
>
> struct aie4_msg_attach_work_buffer_req {
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index f81c43a1f884..e9cd2af224d3 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -90,7 +90,8 @@ static int aie4_mailbox_info(struct amdxdna_dev *xdna,
>
> ret = aie_check_protocol(&xdna->dev_handle->aie,
> mbox_info->protocol_major,
> - mbox_info->protocol_minor);
> + mbox_info->protocol_minor,
> + xdna->dev_info->fw_feature_tbl);
> if (ret)
> XDNA_ERR(xdna, "mailbox major.minor %d.%d is not supported",
> mbox_info->protocol_major, mbox_info->protocol_minor);
> @@ -277,7 +278,22 @@ static void aie4_partition_fini(struct amdxdna_dev_hdl *ndev)
>
> static int aie4_query(struct amdxdna_dev_hdl *ndev)
> {
> - return aie4_query_aie_metadata(ndev, &ndev->aie.metadata);
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> + int ret;
> +
> + ret = aie4_query_npu_firmware_version(ndev, &xdna->fw_ver);
> + if (ret)
> + return ret;
> +
> + ret = aie4_query_cert_firmware_version(ndev, &ndev->cert_version);
> + if (ret)
> + return ret;
> +
> + ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata);
> + if (ret)
> + return ret;
> +
> + return 0;
> }
>
> static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index c6219544dc0f..8c62ee6a9b23 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -57,6 +57,13 @@ struct amdxdna_dev_hdl {
> void *work_buf;
> dma_addr_t work_buf_addr;
> u32 work_buf_size;
> +
> + struct amdxdna_drm_query_firmware_version cert_version;
> +};
> +
> +enum aie4_fw_feature {
> + AIE4_HSA_COMMAND = 5,
> + AIE4_FEATURE_MAX
> };
>
> /* aie4_message.c */
> @@ -64,6 +71,10 @@ int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_aie_metadata *metadata);
> int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev);
> int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev);
> +int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
> + struct amdxdna_drm_query_firmware_version *fw_version);
> +int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
> + struct amdxdna_drm_query_firmware_version *cert_version);
>
> /* aie4_ctx.c */
> int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> index 84c8973e9197..0002e6ef32ba 100644
> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> @@ -99,16 +99,10 @@ struct amdxdna_dev_info {
> size_t dev_heap_max_size;
> const struct amdxdna_dev_priv *dev_priv;
> const struct amdxdna_fw_feature_tbl *fw_feature_tbl;
> + const struct amdxdna_fw_feature_tbl *cert_feature_tbl;
> const struct amdxdna_dev_ops *ops;
> };
>
> -struct amdxdna_fw_ver {
> - u32 major;
> - u32 minor;
> - u32 sub;
> - u32 build;
> -};
> -
> struct amdxdna_carveout;
>
> struct amdxdna_dev {
> @@ -120,7 +114,7 @@ struct amdxdna_dev {
> struct mutex dev_lock; /* per device lock */
> struct list_head client_list;
> struct mutex client_lock; /* client_list */
> - struct amdxdna_fw_ver fw_ver;
> + struct amdxdna_drm_query_firmware_version fw_ver;
> struct rw_semaphore notifier_lock; /* for mmu notifier*/
> struct workqueue_struct *notifier_wq;
>
> diff --git a/drivers/accel/amdxdna/amdxdna_sysfs.c b/drivers/accel/amdxdna/amdxdna_sysfs.c
> index d9e359ee8182..e20b7fb1e5d1 100644
> --- a/drivers/accel/amdxdna/amdxdna_sysfs.c
> +++ b/drivers/accel/amdxdna/amdxdna_sysfs.c
> @@ -37,7 +37,7 @@ static ssize_t fw_version_show(struct device *dev, struct device_attribute *attr
> struct amdxdna_dev *xdna = dev_get_drvdata(dev);
>
> return sprintf(buf, "%d.%d.%d.%d\n", xdna->fw_ver.major,
> - xdna->fw_ver.minor, xdna->fw_ver.sub,
> + xdna->fw_ver.minor, xdna->fw_ver.patch,
> xdna->fw_ver.build);
> }
> static DEVICE_ATTR_RO(fw_version);
> diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
> index 8d287ef32fff..e82bc0a4f597 100644
> --- a/drivers/accel/amdxdna/npu3_regs.c
> +++ b/drivers/accel/amdxdna/npu3_regs.c
> @@ -42,6 +42,11 @@ static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
> { 0 }
> };
>
> +static const struct amdxdna_fw_feature_tbl npu3_cert_feature_table[] = {
> + { .features = BIT_U64(AIE4_HSA_COMMAND), .major = 1, .min_minor = 0 },
> + { 0 }
> +};
> +
> static const struct amdxdna_dev_priv npu3_dev_priv = {
> .npufw_path = "npu.sbin",
> .certfw_path = "cert.sbin",
> @@ -85,6 +90,7 @@ const struct amdxdna_dev_info dev_npu3_pf_info = {
> .device_type = AMDXDNA_DEV_TYPE_PF,
> .dev_priv = &npu3_dev_priv,
> .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
> .ops = &aie4_pf_ops,
> };
>
> @@ -96,5 +102,6 @@ const struct amdxdna_dev_info dev_npu3_vf_info = {
> .device_type = AMDXDNA_DEV_TYPE_UMQ,
> .dev_priv = &npu3_dev_vf_priv,
> .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> .ops = &aie4_vf_ops,
> };
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 04/19] accel/amdxdna: Support firmware 6.0
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (2 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 03/19] accel/amdxdna: Add CERT firmware version support David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-09 23:08 ` sashiko-bot
2026-10-12 20:41 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 05/19] accel/amdxdna: Add NPU3 classic device support David Zhang
` (14 subsequent siblings)
18 siblings, 2 replies; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello
Support firmware interface version 6.0. Update host queue layout,
opcode definitions, and context creation/destruction request structures.
Parse priority band and PASID for hardware context creation. Protocol
compatibility for this queue layout is validated against the CERT
firmware protocol version.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_ctx.c | 23 ++++++++++++++++++++---
drivers/accel/amdxdna/aie4_host_queue.h | 7 +++++--
drivers/accel/amdxdna/aie4_message.c | 11 +++++++++++
drivers/accel/amdxdna/aie4_msg_priv.h | 20 +++++++++++++++++---
drivers/accel/amdxdna/aie4_pci.h | 1 +
drivers/accel/amdxdna/npu3_regs.c | 2 +-
6 files changed, 55 insertions(+), 9 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
index 8157f2a6fd10..5eb918e1d58c 100644
--- a/drivers/accel/amdxdna/aie4_ctx.c
+++ b/drivers/accel/amdxdna/aie4_ctx.c
@@ -9,6 +9,7 @@
#include <drm/drm_gem_shmem_helper.h>
#include <drm/drm_print.h>
#include <drm/gpu_scheduler.h>
+#include <linux/iommu.h>
#include <linux/types.h>
#include "aie.h"
@@ -110,6 +111,22 @@ static int aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context
return aie_send_mgmt_msg_wait(&ndev->aie, &msg);
}
+static u8 aie4_parse_priority_to_dev(u32 priority)
+{
+ switch (priority) {
+ case AMDXDNA_QOS_LOW_PRIORITY:
+ return AIE4_CONTEXT_PRIORITY_BAND_IDLE;
+ case AMDXDNA_QOS_NORMAL_PRIORITY:
+ return AIE4_CONTEXT_PRIORITY_BAND_NORMAL;
+ case AMDXDNA_QOS_HIGH_PRIORITY:
+ return AIE4_CONTEXT_PRIORITY_BAND_FOCUS;
+ case AMDXDNA_QOS_REALTIME_PRIORITY:
+ return AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME;
+ default:
+ return AIE4_CONTEXT_PRIORITY_BAND_NORMAL;
+ }
+}
+
static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
{
DECLARE_AIE_MSG(aie4_msg_create_hw_context, AIE4_MSG_OP_CREATE_HW_CONTEXT);
@@ -129,9 +146,9 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
req.partition_id = ndev->partition_id;
req.request_num_tiles = hwctx->num_tiles;
- req.pasid = FIELD_PREP(AIE4_MSG_PASID, client->pasid) |
- FIELD_PREP(AIE4_MSG_PASID_VLD, 1);
- req.priority_band = hwctx->qos.priority;
+ req.pasid = aie4_msg_pasid(client);
+ req.pasid = req.pasid == IOMMU_PASID_INVALID ? 0 : req.pasid;
+ req.priority_band = aie4_parse_priority_to_dev(hwctx->qos.priority);
req.hsa_addr_high = upper_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
req.hsa_addr_low = lower_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
diff --git a/drivers/accel/amdxdna/aie4_host_queue.h b/drivers/accel/amdxdna/aie4_host_queue.h
index 1b33eda3f727..95ebbb714c6f 100644
--- a/drivers/accel/amdxdna/aie4_host_queue.h
+++ b/drivers/accel/amdxdna/aie4_host_queue.h
@@ -10,6 +10,7 @@
#define CTX_MAX_CMDS 32
+/* Host queue header layout. */
struct host_queue_header {
__u64 read_index;
struct {
@@ -17,8 +18,10 @@ struct host_queue_header {
__u16 minor;
} version;
__u32 capacity; /* Queue capacity, must be power of two. */
- __u64 write_index;
+ __u64 padding0[6];
+ __u64 write_index; /* different cacheline from read_index to avoid false sharing */
+ __u64 padding1[6];
__u64 data_address; /* The xdna dev addr for payload. */
-};
+} __packed;
#endif /* _AIE4_HOST_QUEUE_H_ */
diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
index 53f8e366b66c..f67aa8ba943c 100644
--- a/drivers/accel/amdxdna/aie4_message.c
+++ b/drivers/accel/amdxdna/aie4_message.c
@@ -5,6 +5,8 @@
#include <drm/amdxdna_accel.h>
#include <drm/drm_print.h>
+#include <linux/bitfield.h>
+#include <linux/iommu.h>
#include <linux/mutex.h>
#include "aie.h"
@@ -14,6 +16,15 @@
#include "amdxdna_mailbox_helper.h"
#include "amdxdna_pci_drv.h"
+u32 aie4_msg_pasid(struct amdxdna_client *client)
+{
+ if (!amdxdna_pasid_on(client))
+ return IOMMU_PASID_INVALID;
+
+ return FIELD_PREP(AIE4_MSG_PASID, client->pasid) |
+ FIELD_PREP(AIE4_MSG_PASID_VLD, 1);
+}
+
int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev)
{
DECLARE_AIE_MSG(aie4_msg_suspend, AIE4_MSG_OP_SUSPEND);
diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
index 5b97c8057de0..b9f7c61f36e3 100644
--- a/drivers/accel/amdxdna/aie4_msg_priv.h
+++ b/drivers/accel/amdxdna/aie4_msg_priv.h
@@ -12,7 +12,6 @@
enum aie4_msg_opcode {
AIE4_MSG_OP_IDENTIFY = 0x10002,
AIE4_MSG_OP_SUSPEND = 0x10003,
- AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x1000D,
AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F,
AIE4_MSG_OP_CREATE_VFS = 0x20001,
@@ -23,6 +22,8 @@ enum aie4_msg_opcode {
AIE4_MSG_OP_CREATE_HW_CONTEXT = 0x30003,
AIE4_MSG_OP_DESTROY_HW_CONTEXT = 0x30004,
AIE4_MSG_OP_AIE_TILE_INFO = 0x30006,
+
+ AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
};
enum aie4_msg_status {
@@ -32,6 +33,14 @@ enum aie4_msg_status {
MAX_AIE4_MSG_STATUS_CODE = 0x4,
};
+enum aie4_msg_context_priority_band {
+ AIE4_CONTEXT_PRIORITY_BAND_IDLE = 0,
+ AIE4_CONTEXT_PRIORITY_BAND_NORMAL,
+ AIE4_CONTEXT_PRIORITY_BAND_FOCUS,
+ AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME,
+ AIE4_CONTEXT_PRIORITY_BAND_COUNT
+};
+
struct aie4_msg_identify_req {
__u32 rsvd;
} __packed;
@@ -94,7 +103,9 @@ struct aie4_msg_create_hw_context_req {
#define AIE4_MSG_PASID GENMASK(19, 0)
#define AIE4_MSG_PASID_VLD GENMASK(31, 31)
__u32 pasid;
- __u32 priority_band;
+ __u8 priority_band;
+ __u8 priority_level;
+ __u16 restore_id;
} __packed;
struct aie4_msg_create_hw_context_resp {
@@ -106,11 +117,14 @@ struct aie4_msg_create_hw_context_resp {
struct aie4_msg_destroy_hw_context_req {
__u32 hw_context_id;
- __u32 resvd1;
+#define AIE4_MSG_GRACEFUL_FLAG GENMASK(0, 0)
+ __u32 graceful_flag;
} __packed;
struct aie4_msg_destroy_hw_context_resp {
enum aie4_msg_status status;
+ __u16 restore_id;
+ __u16 resvd;
} __packed;
struct aie4_tile_info {
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 8c62ee6a9b23..bdbb2d7cf0e7 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -75,6 +75,7 @@ int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_firmware_version *fw_version);
int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_firmware_version *cert_version);
+u32 aie4_msg_pasid(struct amdxdna_client *client);
/* aie4_ctx.c */
int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
index e82bc0a4f597..93f749acb5d5 100644
--- a/drivers/accel/amdxdna/npu3_regs.c
+++ b/drivers/accel/amdxdna/npu3_regs.c
@@ -38,7 +38,7 @@
#define MP1_C2PMSG_60_ALT_1 0x3B109F0
static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
- { .major = 5, .min_minor = 10 },
+ { .major = 6, .min_minor = 0 },
{ 0 }
};
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 04/19] accel/amdxdna: Support firmware 6.0
2026-10-09 22:53 ` [PATCH V4 04/19] accel/amdxdna: Support firmware 6.0 David Zhang
@ 2026-10-09 23:08 ` sashiko-bot
2026-10-12 20:41 ` Lizhi Hou
1 sibling, 0 replies; 39+ messages in thread
From: sashiko-bot @ 2026-10-09 23:08 UTC (permalink / raw)
To: David Zhang; +Cc: dri-devel
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] accel/amdxdna: missing capability check for REALTIME priority allows DoS
--
commit 33aba925e30324fed055cc90f6f20b1a9826f931
Author: David Zhang <yidong.zhang@amd.com>
accel/amdxdna: Support firmware 6.0
This commit supports firmware interface version 6.0 by updating the host queue
layout, opcode definitions, and context creation/destruction request structures.
It also parses priority band and PASID for hardware context creation.
> diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
> index 8157f2a6fd10a..5eb918e1d58c7 100644
> --- a/drivers/accel/amdxdna/aie4_ctx.c
> +++ b/drivers/accel/amdxdna/aie4_ctx.c
[ ... ]
> @@ -110,6 +111,22 @@ static int aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context
> return aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> }
>
> +static u8 aie4_parse_priority_to_dev(u32 priority)
> +{
> + switch (priority) {
> + case AMDXDNA_QOS_LOW_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_IDLE;
> + case AMDXDNA_QOS_NORMAL_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_NORMAL;
> + case AMDXDNA_QOS_HIGH_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_FOCUS;
> + case AMDXDNA_QOS_REALTIME_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME;
[Severity: Medium]
Could this allow an unprivileged user to monopolize the NPU?
In aie4_parse_priority_to_dev() in drivers/accel/amdxdna/aie4_ctx.c, when a
user calls the AMDXDNA_CREATE_HWCTX ioctl and passes
AMDXDNA_QOS_REALTIME_PRIORITY in qos.priority, this maps directly to
AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME during context creation and is sent to
the firmware.
Since there doesn't appear to be a capability check (such as verifying if the
caller possesses CAP_SYS_NICE or similar privileges), could any local user
with access to the DRM node create an NPU hardware context with REALTIME
priority and starve other workloads, causing a denial of service?
> + default:
> + return AIE4_CONTEXT_PRIORITY_BAND_NORMAL;
> + }
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009225343.3079074-1-yidong.zhang@amd.com?part=4
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V4 04/19] accel/amdxdna: Support firmware 6.0
2026-10-09 22:53 ` [PATCH V4 04/19] accel/amdxdna: Support firmware 6.0 David Zhang
2026-10-09 23:08 ` sashiko-bot
@ 2026-10-12 20:41 ` Lizhi Hou
1 sibling, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-12 20:41 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello
On 10/9/26 15:53, David Zhang wrote:
> Support firmware interface version 6.0. Update host queue layout,
> opcode definitions, and context creation/destruction request structures.
> Parse priority band and PASID for hardware context creation. Protocol
> compatibility for this queue layout is validated against the CERT
> firmware protocol version.
>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> ---
> drivers/accel/amdxdna/aie4_ctx.c | 23 ++++++++++++++++++++---
> drivers/accel/amdxdna/aie4_host_queue.h | 7 +++++--
> drivers/accel/amdxdna/aie4_message.c | 11 +++++++++++
> drivers/accel/amdxdna/aie4_msg_priv.h | 20 +++++++++++++++++---
> drivers/accel/amdxdna/aie4_pci.h | 1 +
> drivers/accel/amdxdna/npu3_regs.c | 2 +-
> 6 files changed, 55 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
> index 8157f2a6fd10..5eb918e1d58c 100644
> --- a/drivers/accel/amdxdna/aie4_ctx.c
> +++ b/drivers/accel/amdxdna/aie4_ctx.c
> @@ -9,6 +9,7 @@
> #include <drm/drm_gem_shmem_helper.h>
> #include <drm/drm_print.h>
> #include <drm/gpu_scheduler.h>
> +#include <linux/iommu.h>
> #include <linux/types.h>
>
> #include "aie.h"
> @@ -110,6 +111,22 @@ static int aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context
> return aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> }
>
> +static u8 aie4_parse_priority_to_dev(u32 priority)
> +{
> + switch (priority) {
> + case AMDXDNA_QOS_LOW_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_IDLE;
> + case AMDXDNA_QOS_NORMAL_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_NORMAL;
> + case AMDXDNA_QOS_HIGH_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_FOCUS;
> + case AMDXDNA_QOS_REALTIME_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME;
> + default:
> + return AIE4_CONTEXT_PRIORITY_BAND_NORMAL;
> + }
> +}
> +
> static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
> {
> DECLARE_AIE_MSG(aie4_msg_create_hw_context, AIE4_MSG_OP_CREATE_HW_CONTEXT);
> @@ -129,9 +146,9 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
>
> req.partition_id = ndev->partition_id;
> req.request_num_tiles = hwctx->num_tiles;
> - req.pasid = FIELD_PREP(AIE4_MSG_PASID, client->pasid) |
> - FIELD_PREP(AIE4_MSG_PASID_VLD, 1);
> - req.priority_band = hwctx->qos.priority;
> + req.pasid = aie4_msg_pasid(client);
> + req.pasid = req.pasid == IOMMU_PASID_INVALID ? 0 : req.pasid;
> + req.priority_band = aie4_parse_priority_to_dev(hwctx->qos.priority);
>
> req.hsa_addr_high = upper_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
> req.hsa_addr_low = lower_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
> diff --git a/drivers/accel/amdxdna/aie4_host_queue.h b/drivers/accel/amdxdna/aie4_host_queue.h
> index 1b33eda3f727..95ebbb714c6f 100644
> --- a/drivers/accel/amdxdna/aie4_host_queue.h
> +++ b/drivers/accel/amdxdna/aie4_host_queue.h
> @@ -10,6 +10,7 @@
>
> #define CTX_MAX_CMDS 32
>
> +/* Host queue header layout. */
> struct host_queue_header {
> __u64 read_index;
> struct {
> @@ -17,8 +18,10 @@ struct host_queue_header {
> __u16 minor;
> } version;
> __u32 capacity; /* Queue capacity, must be power of two. */
> - __u64 write_index;
> + __u64 padding0[6];
> + __u64 write_index; /* different cacheline from read_index to avoid false sharing */
> + __u64 padding1[6];
> __u64 data_address; /* The xdna dev addr for payload. */
> -};
> +} __packed;
>
> #endif /* _AIE4_HOST_QUEUE_H_ */
> diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
> index 53f8e366b66c..f67aa8ba943c 100644
> --- a/drivers/accel/amdxdna/aie4_message.c
> +++ b/drivers/accel/amdxdna/aie4_message.c
> @@ -5,6 +5,8 @@
>
> #include <drm/amdxdna_accel.h>
> #include <drm/drm_print.h>
> +#include <linux/bitfield.h>
> +#include <linux/iommu.h>
> #include <linux/mutex.h>
>
> #include "aie.h"
> @@ -14,6 +16,15 @@
> #include "amdxdna_mailbox_helper.h"
> #include "amdxdna_pci_drv.h"
>
> +u32 aie4_msg_pasid(struct amdxdna_client *client)
> +{
> + if (!amdxdna_pasid_on(client))
> + return IOMMU_PASID_INVALID;
> +
> + return FIELD_PREP(AIE4_MSG_PASID, client->pasid) |
> + FIELD_PREP(AIE4_MSG_PASID_VLD, 1);
> +}
> +
> int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev)
> {
> DECLARE_AIE_MSG(aie4_msg_suspend, AIE4_MSG_OP_SUSPEND);
> diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
> index 5b97c8057de0..b9f7c61f36e3 100644
> --- a/drivers/accel/amdxdna/aie4_msg_priv.h
> +++ b/drivers/accel/amdxdna/aie4_msg_priv.h
> @@ -12,7 +12,6 @@
> enum aie4_msg_opcode {
> AIE4_MSG_OP_IDENTIFY = 0x10002,
> AIE4_MSG_OP_SUSPEND = 0x10003,
> - AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x1000D,
> AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F,
>
> AIE4_MSG_OP_CREATE_VFS = 0x20001,
> @@ -23,6 +22,8 @@ enum aie4_msg_opcode {
> AIE4_MSG_OP_CREATE_HW_CONTEXT = 0x30003,
> AIE4_MSG_OP_DESTROY_HW_CONTEXT = 0x30004,
> AIE4_MSG_OP_AIE_TILE_INFO = 0x30006,
> +
> + AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
> };
>
> enum aie4_msg_status {
> @@ -32,6 +33,14 @@ enum aie4_msg_status {
> MAX_AIE4_MSG_STATUS_CODE = 0x4,
> };
>
> +enum aie4_msg_context_priority_band {
> + AIE4_CONTEXT_PRIORITY_BAND_IDLE = 0,
> + AIE4_CONTEXT_PRIORITY_BAND_NORMAL,
> + AIE4_CONTEXT_PRIORITY_BAND_FOCUS,
> + AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME,
> + AIE4_CONTEXT_PRIORITY_BAND_COUNT
> +};
> +
> struct aie4_msg_identify_req {
> __u32 rsvd;
> } __packed;
> @@ -94,7 +103,9 @@ struct aie4_msg_create_hw_context_req {
> #define AIE4_MSG_PASID GENMASK(19, 0)
> #define AIE4_MSG_PASID_VLD GENMASK(31, 31)
> __u32 pasid;
> - __u32 priority_band;
> + __u8 priority_band;
> + __u8 priority_level;
> + __u16 restore_id;
> } __packed;
>
> struct aie4_msg_create_hw_context_resp {
> @@ -106,11 +117,14 @@ struct aie4_msg_create_hw_context_resp {
>
> struct aie4_msg_destroy_hw_context_req {
> __u32 hw_context_id;
> - __u32 resvd1;
> +#define AIE4_MSG_GRACEFUL_FLAG GENMASK(0, 0)
> + __u32 graceful_flag;
> } __packed;
>
> struct aie4_msg_destroy_hw_context_resp {
> enum aie4_msg_status status;
> + __u16 restore_id;
> + __u16 resvd;
> } __packed;
>
> struct aie4_tile_info {
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index 8c62ee6a9b23..bdbb2d7cf0e7 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -75,6 +75,7 @@ int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_firmware_version *fw_version);
> int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_firmware_version *cert_version);
> +u32 aie4_msg_pasid(struct amdxdna_client *client);
>
> /* aie4_ctx.c */
> int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
> diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
> index e82bc0a4f597..93f749acb5d5 100644
> --- a/drivers/accel/amdxdna/npu3_regs.c
> +++ b/drivers/accel/amdxdna/npu3_regs.c
> @@ -38,7 +38,7 @@
> #define MP1_C2PMSG_60_ALT_1 0x3B109F0
>
> static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
> - { .major = 5, .min_minor = 10 },
> + { .major = 6, .min_minor = 0 },
> { 0 }
> };
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 05/19] accel/amdxdna: Add NPU3 classic device support
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (3 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 04/19] accel/amdxdna: Support firmware 6.0 David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-09 23:08 ` sashiko-bot
2026-10-12 20:41 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 06/19] accel/amdxdna: Add AIE version query to aie4_get_info David Zhang
` (13 subsequent siblings)
18 siblings, 2 replies; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello
Add NPU3 classic device operations (aie4_classic_ops) and register
definitions, as well as the PCI device ID and firmware declarations for
NPU3 classic devices. Remove device IDs 0x1B0B and 0x1B0C because those
devices will not be released.
Suspend and resume support is added in a later patch, once the
kernel-mode queue (KMQ) can drain in-flight commands.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_pci.c | 83 +++++++++++++++++++++++++
drivers/accel/amdxdna/aie4_pci.h | 1 +
drivers/accel/amdxdna/amdxdna_pci_drv.c | 23 ++++---
drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 +
drivers/accel/amdxdna/npu3_regs.c | 14 +++++
5 files changed, 115 insertions(+), 7 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index e9cd2af224d3..1eeb1cb73b27 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -366,6 +366,51 @@ static void aie4_vf_hw_stop(struct amdxdna_dev_hdl *ndev)
aie4_mailbox_fini(ndev);
}
+static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
+{
+ int ret;
+
+ ret = aie4_fw_start(ndev);
+ if (ret)
+ return ret;
+
+ ret = aie4_mailbox_init(ndev);
+ if (ret)
+ goto stop_fw;
+
+ ret = aie4_query(ndev);
+ if (ret)
+ goto mailbox_fini;
+
+ ret = aie4_attach_work_buffer(ndev);
+ if (ret)
+ goto mailbox_fini;
+
+ ret = aie4_partition_init(ndev);
+ if (ret)
+ goto mailbox_fini;
+
+ return 0;
+
+mailbox_fini:
+ aie4_mailbox_fini(ndev);
+stop_fw:
+ aie4_fw_stop(ndev);
+ return ret;
+}
+
+static void aie4_classic_hw_stop(struct amdxdna_dev_hdl *ndev)
+{
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+
+ drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+ aie4_partition_fini(ndev);
+ aie4_suspend_fw(ndev);
+ aie4_mailbox_fini(ndev);
+ aie4_fw_stop(ndev);
+}
+
static int aie4_request_firmware(struct amdxdna_dev_hdl *ndev,
const struct firmware **npufw,
const struct firmware **certfw)
@@ -628,6 +673,29 @@ static int aie4_vf_init(struct amdxdna_dev *xdna)
return aie4_vf_hw_start(xdna->dev_handle);
}
+static int aie4_classic_init(struct amdxdna_dev *xdna)
+{
+ int ret;
+
+ ret = aie4m_pcidev_init(xdna);
+ if (ret)
+ return ret;
+
+ ret = aie4_alloc_work_buffer(xdna->dev_handle);
+ if (ret)
+ return ret;
+
+ ret = aie4_classic_hw_start(xdna->dev_handle);
+ if (ret)
+ goto free_work_buf;
+
+ return 0;
+
+free_work_buf:
+ aie4_free_work_buffer(xdna->dev_handle);
+ return ret;
+}
+
static void aie4_pf_fini(struct amdxdna_dev *xdna)
{
aie4_sriov_stop(xdna->dev_handle);
@@ -640,6 +708,12 @@ static void aie4_vf_fini(struct amdxdna_dev *xdna)
aie4_vf_hw_stop(xdna->dev_handle);
}
+static void aie4_classic_fini(struct amdxdna_dev *xdna)
+{
+ aie4_classic_hw_stop(xdna->dev_handle);
+ aie4_free_work_buffer(xdna->dev_handle);
+}
+
const struct amdxdna_dev_ops aie4_pf_ops = {
.init = aie4_pf_init,
.fini = aie4_pf_fini,
@@ -654,3 +728,12 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
.cmd_wait = aie4_cmd_wait,
.get_aie_info = aie4_get_info,
};
+
+const struct amdxdna_dev_ops aie4_classic_ops = {
+ .init = aie4_classic_init,
+ .fini = aie4_classic_fini,
+ .hwctx_init = aie4_hwctx_init,
+ .hwctx_fini = aie4_hwctx_fini,
+ .cmd_wait = aie4_cmd_wait,
+ .get_aie_info = aie4_get_info,
+};
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index bdbb2d7cf0e7..940e67347d74 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -96,5 +96,6 @@ static inline int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev)
extern const struct amdxdna_dev_ops aie4_pf_ops;
extern const struct amdxdna_dev_ops aie4_vf_ops;
+extern const struct amdxdna_dev_ops aie4_classic_ops;
#endif /* _AIE4_PCI_H_ */
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c
index 3140af69e29c..f5f7831c4e80 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.c
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c
@@ -28,8 +28,14 @@ MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
MODULE_FIRMWARE("amdnpu/1502_00/npu_7.sbin");
MODULE_FIRMWARE("amdnpu/17f0_10/npu_7.sbin");
MODULE_FIRMWARE("amdnpu/17f0_11/npu_7.sbin");
+MODULE_FIRMWARE("amdnpu/17f1_10/npu.sbin");
+MODULE_FIRMWARE("amdnpu/17f1_10/cert.sbin");
MODULE_FIRMWARE("amdnpu/17f2_10/npu.sbin");
MODULE_FIRMWARE("amdnpu/17f2_10/cert.sbin");
+MODULE_FIRMWARE("amdnpu/17f1_13/npu.sbin");
+MODULE_FIRMWARE("amdnpu/17f1_13/cert.sbin");
+MODULE_FIRMWARE("amdnpu/17f2_13/npu.sbin");
+MODULE_FIRMWARE("amdnpu/17f2_13/cert.sbin");
/*
* 0.0: Initial version
@@ -55,10 +61,9 @@ MODULE_FIRMWARE("amdnpu/17f2_10/cert.sbin");
static const struct pci_device_id pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1502) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f0) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f1) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f2) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f3) },
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1B0B) },
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1B0C) },
{0}
};
@@ -69,10 +74,12 @@ static const struct amdxdna_device_id amdxdna_ids[] = {
{ 0x17f0, 0x10, &dev_npu4_info },
{ 0x17f0, 0x11, &dev_npu5_info },
{ 0x17f0, 0x20, &dev_npu6_info },
+ { 0x17f1, 0x10, &dev_npu3_classic_info },
{ 0x17f2, 0x10, &dev_npu3_pf_info },
{ 0x17f3, 0x10, &dev_npu3_vf_info },
- { 0x1B0B, 0x10, &dev_npu3_pf_info },
- { 0x1B0C, 0x10, &dev_npu3_vf_info },
+ { 0x17f1, 0x13, &dev_npu3_classic_info },
+ { 0x17f2, 0x13, &dev_npu3_pf_info },
+ { 0x17f3, 0x13, &dev_npu3_vf_info },
{0}
};
@@ -140,8 +147,9 @@ static int amdxdna_drm_open(struct drm_device *ddev, struct drm_file *filp)
mmgrab(client->mm);
xa_init_flags(&client->hwctx_xa, XA_FLAGS_ALLOC);
xa_init_flags(&client->dev_heap_xa, XA_FLAGS_ALLOC);
- drm_mm_init(&client->dev_heap_mm, xdna->dev_info->dev_mem_base,
- xdna->dev_info->dev_heap_max_size);
+ if (xdna->dev_info->dev_heap_max_size)
+ drm_mm_init(&client->dev_heap_mm, xdna->dev_info->dev_mem_base,
+ xdna->dev_info->dev_heap_max_size);
mutex_init(&client->mm_lock);
mutex_lock(&xdna->client_lock);
@@ -176,7 +184,8 @@ static void amdxdna_client_cleanup(struct amdxdna_client *client)
xa_for_each(&client->dev_heap_xa, heap_id, heap)
drm_gem_object_put(to_gobj(heap));
xa_destroy(&client->dev_heap_xa);
- drm_mm_takedown(&client->dev_heap_mm);
+ if (client->xdna->dev_info->dev_heap_max_size)
+ drm_mm_takedown(&client->dev_heap_mm);
mutex_destroy(&client->mm_lock);
mmdrop(client->mm);
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
index 0002e6ef32ba..953bf783b3f7 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -169,6 +169,7 @@ struct amdxdna_client {
/* Add device info below */
extern const struct amdxdna_dev_info dev_npu1_info;
+extern const struct amdxdna_dev_info dev_npu3_classic_info;
extern const struct amdxdna_dev_info dev_npu3_pf_info;
extern const struct amdxdna_dev_info dev_npu3_vf_info;
extern const struct amdxdna_dev_info dev_npu4_info;
diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
index 93f749acb5d5..c82433d62901 100644
--- a/drivers/accel/amdxdna/npu3_regs.c
+++ b/drivers/accel/amdxdna/npu3_regs.c
@@ -105,3 +105,17 @@ const struct amdxdna_dev_info dev_npu3_vf_info = {
.cert_feature_tbl = npu3_cert_feature_table,
.ops = &aie4_vf_ops,
};
+
+const struct amdxdna_dev_info dev_npu3_classic_info = {
+ .mbox_bar = NPU3_MBOX_BAR,
+ .sram_bar = NPU3_MBOX_BUFFER_BAR,
+ .psp_bar = NPU3_PSP_BAR_INDEX,
+ .smu_bar = NPU3_SMU_BAR_INDEX,
+ .doorbell_bar = NPU3_DOORBELL_BAR,
+ .default_vbnv = "RyzenAI-npu3",
+ .device_type = AMDXDNA_DEV_TYPE_UMQ,
+ .dev_priv = &npu3_dev_priv,
+ .fw_feature_tbl = npu3_fw_feature_table,
+ .cert_feature_tbl = npu3_cert_feature_table,
+ .ops = &aie4_classic_ops,
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 05/19] accel/amdxdna: Add NPU3 classic device support
2026-10-09 22:53 ` [PATCH V4 05/19] accel/amdxdna: Add NPU3 classic device support David Zhang
@ 2026-10-09 23:08 ` sashiko-bot
2026-10-12 20:41 ` Lizhi Hou
1 sibling, 0 replies; 39+ messages in thread
From: sashiko-bot @ 2026-10-09 23:08 UTC (permalink / raw)
To: David Zhang; +Cc: dri-devel
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] amdxdna: user-triggerable WARN_ON via AMDXDNA_BO_DEV_HEAP on NPU3 classic
--
commit 9daa4537d3513c6a4bc057f8afd01b65162be2b6
Author: David Zhang <yidong.zhang@amd.com>
accel/amdxdna: Add NPU3 classic device support
Add NPU3 classic device operations (aie4_classic_ops) and register
definitions, as well as the PCI device ID and firmware declarations for
NPU3 classic devices. Remove device IDs 0x1B0B and 0x1B0C because those
devices will not be released.
> diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
> index 93f749acb5d5d..c82433d629012 100644
> --- a/drivers/accel/amdxdna/npu3_regs.c
> +++ b/drivers/accel/amdxdna/npu3_regs.c
> @@ -105,3 +105,17 @@ const struct amdxdna_dev_info dev_npu3_vf_info = {
> .cert_feature_tbl = npu3_cert_feature_table,
> .ops = &aie4_vf_ops,
> };
> +
> +const struct amdxdna_dev_info dev_npu3_classic_info = {
> + .mbox_bar = NPU3_MBOX_BAR,
> + .sram_bar = NPU3_MBOX_BUFFER_BAR,
> + .psp_bar = NPU3_PSP_BAR_INDEX,
> + .smu_bar = NPU3_SMU_BAR_INDEX,
> + .doorbell_bar = NPU3_DOORBELL_BAR,
> + .default_vbnv = "RyzenAI-npu3",
> + .device_type = AMDXDNA_DEV_TYPE_UMQ,
> + .dev_priv = &npu3_dev_priv,
> + .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
> + .ops = &aie4_classic_ops,
> +};
[Severity: Medium]
Since dev_mem_size is omitted here, it defaults to 0. Does this cause a
kernel warning when creating a device heap BO?
If an unprivileged user opens the accelerator device and requests a BO with
type AMDXDNA_BO_DEV_HEAP, the ioctl dispatcher calls
amdxdna_drm_create_dev_heap_bo() which unconditionally evaluates:
WARN_ON(!is_power_of_2(xdna->dev_info->dev_mem_size));
Since dev_mem_size is 0, this will evaluate to true and trigger a warning,
potentially causing a local denial of service if panic_on_warn is enabled.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009225343.3079074-1-yidong.zhang@amd.com?part=5
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V4 05/19] accel/amdxdna: Add NPU3 classic device support
2026-10-09 22:53 ` [PATCH V4 05/19] accel/amdxdna: Add NPU3 classic device support David Zhang
2026-10-09 23:08 ` sashiko-bot
@ 2026-10-12 20:41 ` Lizhi Hou
1 sibling, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-12 20:41 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello
On 10/9/26 15:53, David Zhang wrote:
> Add NPU3 classic device operations (aie4_classic_ops) and register
> definitions, as well as the PCI device ID and firmware declarations for
> NPU3 classic devices. Remove device IDs 0x1B0B and 0x1B0C because those
> devices will not be released.
>
> Suspend and resume support is added in a later patch, once the
> kernel-mode queue (KMQ) can drain in-flight commands.
>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> ---
> drivers/accel/amdxdna/aie4_pci.c | 83 +++++++++++++++++++++++++
> drivers/accel/amdxdna/aie4_pci.h | 1 +
> drivers/accel/amdxdna/amdxdna_pci_drv.c | 23 ++++---
> drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 +
> drivers/accel/amdxdna/npu3_regs.c | 14 +++++
> 5 files changed, 115 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index e9cd2af224d3..1eeb1cb73b27 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -366,6 +366,51 @@ static void aie4_vf_hw_stop(struct amdxdna_dev_hdl *ndev)
> aie4_mailbox_fini(ndev);
> }
>
> +static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
> +{
> + int ret;
> +
> + ret = aie4_fw_start(ndev);
> + if (ret)
> + return ret;
> +
> + ret = aie4_mailbox_init(ndev);
> + if (ret)
> + goto stop_fw;
> +
> + ret = aie4_query(ndev);
> + if (ret)
> + goto mailbox_fini;
> +
> + ret = aie4_attach_work_buffer(ndev);
> + if (ret)
> + goto mailbox_fini;
> +
> + ret = aie4_partition_init(ndev);
> + if (ret)
> + goto mailbox_fini;
> +
> + return 0;
> +
> +mailbox_fini:
> + aie4_mailbox_fini(ndev);
> +stop_fw:
> + aie4_fw_stop(ndev);
> + return ret;
> +}
> +
> +static void aie4_classic_hw_stop(struct amdxdna_dev_hdl *ndev)
> +{
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> +
> + drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
> +
> + aie4_partition_fini(ndev);
> + aie4_suspend_fw(ndev);
> + aie4_mailbox_fini(ndev);
> + aie4_fw_stop(ndev);
> +}
> +
> static int aie4_request_firmware(struct amdxdna_dev_hdl *ndev,
> const struct firmware **npufw,
> const struct firmware **certfw)
> @@ -628,6 +673,29 @@ static int aie4_vf_init(struct amdxdna_dev *xdna)
> return aie4_vf_hw_start(xdna->dev_handle);
> }
>
> +static int aie4_classic_init(struct amdxdna_dev *xdna)
> +{
> + int ret;
> +
> + ret = aie4m_pcidev_init(xdna);
> + if (ret)
> + return ret;
> +
> + ret = aie4_alloc_work_buffer(xdna->dev_handle);
> + if (ret)
> + return ret;
> +
> + ret = aie4_classic_hw_start(xdna->dev_handle);
> + if (ret)
> + goto free_work_buf;
> +
> + return 0;
> +
> +free_work_buf:
> + aie4_free_work_buffer(xdna->dev_handle);
> + return ret;
> +}
> +
> static void aie4_pf_fini(struct amdxdna_dev *xdna)
> {
> aie4_sriov_stop(xdna->dev_handle);
> @@ -640,6 +708,12 @@ static void aie4_vf_fini(struct amdxdna_dev *xdna)
> aie4_vf_hw_stop(xdna->dev_handle);
> }
>
> +static void aie4_classic_fini(struct amdxdna_dev *xdna)
> +{
> + aie4_classic_hw_stop(xdna->dev_handle);
> + aie4_free_work_buffer(xdna->dev_handle);
> +}
> +
> const struct amdxdna_dev_ops aie4_pf_ops = {
> .init = aie4_pf_init,
> .fini = aie4_pf_fini,
> @@ -654,3 +728,12 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
> .cmd_wait = aie4_cmd_wait,
> .get_aie_info = aie4_get_info,
> };
> +
> +const struct amdxdna_dev_ops aie4_classic_ops = {
> + .init = aie4_classic_init,
> + .fini = aie4_classic_fini,
> + .hwctx_init = aie4_hwctx_init,
> + .hwctx_fini = aie4_hwctx_fini,
> + .cmd_wait = aie4_cmd_wait,
> + .get_aie_info = aie4_get_info,
> +};
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index bdbb2d7cf0e7..940e67347d74 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -96,5 +96,6 @@ static inline int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev)
>
> extern const struct amdxdna_dev_ops aie4_pf_ops;
> extern const struct amdxdna_dev_ops aie4_vf_ops;
> +extern const struct amdxdna_dev_ops aie4_classic_ops;
>
> #endif /* _AIE4_PCI_H_ */
> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c
> index 3140af69e29c..f5f7831c4e80 100644
> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.c
> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c
> @@ -28,8 +28,14 @@ MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
> MODULE_FIRMWARE("amdnpu/1502_00/npu_7.sbin");
> MODULE_FIRMWARE("amdnpu/17f0_10/npu_7.sbin");
> MODULE_FIRMWARE("amdnpu/17f0_11/npu_7.sbin");
> +MODULE_FIRMWARE("amdnpu/17f1_10/npu.sbin");
> +MODULE_FIRMWARE("amdnpu/17f1_10/cert.sbin");
> MODULE_FIRMWARE("amdnpu/17f2_10/npu.sbin");
> MODULE_FIRMWARE("amdnpu/17f2_10/cert.sbin");
> +MODULE_FIRMWARE("amdnpu/17f1_13/npu.sbin");
> +MODULE_FIRMWARE("amdnpu/17f1_13/cert.sbin");
> +MODULE_FIRMWARE("amdnpu/17f2_13/npu.sbin");
> +MODULE_FIRMWARE("amdnpu/17f2_13/cert.sbin");
>
> /*
> * 0.0: Initial version
> @@ -55,10 +61,9 @@ MODULE_FIRMWARE("amdnpu/17f2_10/cert.sbin");
> static const struct pci_device_id pci_ids[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1502) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f0) },
> + { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f1) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f2) },
> { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f3) },
> - { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1B0B) },
> - { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1B0C) },
> {0}
> };
>
> @@ -69,10 +74,12 @@ static const struct amdxdna_device_id amdxdna_ids[] = {
> { 0x17f0, 0x10, &dev_npu4_info },
> { 0x17f0, 0x11, &dev_npu5_info },
> { 0x17f0, 0x20, &dev_npu6_info },
> + { 0x17f1, 0x10, &dev_npu3_classic_info },
> { 0x17f2, 0x10, &dev_npu3_pf_info },
> { 0x17f3, 0x10, &dev_npu3_vf_info },
> - { 0x1B0B, 0x10, &dev_npu3_pf_info },
> - { 0x1B0C, 0x10, &dev_npu3_vf_info },
> + { 0x17f1, 0x13, &dev_npu3_classic_info },
> + { 0x17f2, 0x13, &dev_npu3_pf_info },
> + { 0x17f3, 0x13, &dev_npu3_vf_info },
> {0}
> };
>
> @@ -140,8 +147,9 @@ static int amdxdna_drm_open(struct drm_device *ddev, struct drm_file *filp)
> mmgrab(client->mm);
> xa_init_flags(&client->hwctx_xa, XA_FLAGS_ALLOC);
> xa_init_flags(&client->dev_heap_xa, XA_FLAGS_ALLOC);
> - drm_mm_init(&client->dev_heap_mm, xdna->dev_info->dev_mem_base,
> - xdna->dev_info->dev_heap_max_size);
> + if (xdna->dev_info->dev_heap_max_size)
> + drm_mm_init(&client->dev_heap_mm, xdna->dev_info->dev_mem_base,
> + xdna->dev_info->dev_heap_max_size);
> mutex_init(&client->mm_lock);
>
> mutex_lock(&xdna->client_lock);
> @@ -176,7 +184,8 @@ static void amdxdna_client_cleanup(struct amdxdna_client *client)
> xa_for_each(&client->dev_heap_xa, heap_id, heap)
> drm_gem_object_put(to_gobj(heap));
> xa_destroy(&client->dev_heap_xa);
> - drm_mm_takedown(&client->dev_heap_mm);
> + if (client->xdna->dev_info->dev_heap_max_size)
> + drm_mm_takedown(&client->dev_heap_mm);
>
> mutex_destroy(&client->mm_lock);
> mmdrop(client->mm);
> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> index 0002e6ef32ba..953bf783b3f7 100644
> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> @@ -169,6 +169,7 @@ struct amdxdna_client {
>
> /* Add device info below */
> extern const struct amdxdna_dev_info dev_npu1_info;
> +extern const struct amdxdna_dev_info dev_npu3_classic_info;
> extern const struct amdxdna_dev_info dev_npu3_pf_info;
> extern const struct amdxdna_dev_info dev_npu3_vf_info;
> extern const struct amdxdna_dev_info dev_npu4_info;
> diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
> index 93f749acb5d5..c82433d62901 100644
> --- a/drivers/accel/amdxdna/npu3_regs.c
> +++ b/drivers/accel/amdxdna/npu3_regs.c
> @@ -105,3 +105,17 @@ const struct amdxdna_dev_info dev_npu3_vf_info = {
> .cert_feature_tbl = npu3_cert_feature_table,
> .ops = &aie4_vf_ops,
> };
> +
> +const struct amdxdna_dev_info dev_npu3_classic_info = {
> + .mbox_bar = NPU3_MBOX_BAR,
> + .sram_bar = NPU3_MBOX_BUFFER_BAR,
> + .psp_bar = NPU3_PSP_BAR_INDEX,
> + .smu_bar = NPU3_SMU_BAR_INDEX,
> + .doorbell_bar = NPU3_DOORBELL_BAR,
> + .default_vbnv = "RyzenAI-npu3",
> + .device_type = AMDXDNA_DEV_TYPE_UMQ,
> + .dev_priv = &npu3_dev_priv,
> + .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
> + .ops = &aie4_classic_ops,
> +};
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 06/19] accel/amdxdna: Add AIE version query to aie4_get_info
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (4 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 05/19] accel/amdxdna: Add NPU3 classic device support David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-12 20:55 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 07/19] accel/amdxdna: Add get and set power_mode for AIE4 David Zhang
` (12 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello, Hayden Laccabue
Add AIE version query via DRM_AMDXDNA_GET_INFO. The NPU firmware
version query already existed internally; it is now also exposed
through this ioctl alongside the new AIE version query.
These versions are mandatory once released, the firmware management
interfaces must support those queries in their stable version.
Propagating any failure to abort device initialization is intentional.
Co-developed-by: Hayden Laccabue <hayden.laccabue@amd.com>
Signed-off-by: Hayden Laccabue <hayden.laccabue@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_message.c | 20 ++++++++++++++++++++
drivers/accel/amdxdna/aie4_msg_priv.h | 11 +++++++++++
drivers/accel/amdxdna/aie4_pci.c | 10 ++++++++++
drivers/accel/amdxdna/aie4_pci.h | 2 ++
4 files changed, 43 insertions(+)
diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
index f67aa8ba943c..c83f81a0e65b 100644
--- a/drivers/accel/amdxdna/aie4_message.c
+++ b/drivers/accel/amdxdna/aie4_message.c
@@ -75,6 +75,26 @@ int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
return 0;
}
+int aie4_query_aie_version(struct amdxdna_dev_hdl *ndev,
+ struct amdxdna_drm_query_aie_version *version)
+{
+ DECLARE_AIE_MSG(aie4_msg_aie4_version_info, AIE4_MSG_OP_AIE_VERSION_INFO);
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ int ret;
+
+ ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ if (ret)
+ return ret;
+
+ XDNA_DBG(xdna, "Query AIE version - major: %u minor: %u",
+ resp.major, resp.minor);
+
+ version->major = resp.major;
+ version->minor = resp.minor;
+
+ return 0;
+}
+
int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_firmware_version *fw_version)
{
diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
index b9f7c61f36e3..81842fa1d6ce 100644
--- a/drivers/accel/amdxdna/aie4_msg_priv.h
+++ b/drivers/accel/amdxdna/aie4_msg_priv.h
@@ -22,6 +22,7 @@ enum aie4_msg_opcode {
AIE4_MSG_OP_CREATE_HW_CONTEXT = 0x30003,
AIE4_MSG_OP_DESTROY_HW_CONTEXT = 0x30004,
AIE4_MSG_OP_AIE_TILE_INFO = 0x30006,
+ AIE4_MSG_OP_AIE_VERSION_INFO = 0x30007,
AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
};
@@ -160,6 +161,16 @@ struct aie4_msg_aie4_tile_info_resp {
struct aie4_tile_info info;
} __packed;
+struct aie4_msg_aie4_version_info_req {
+ __u32 resvd;
+} __packed;
+
+struct aie4_msg_aie4_version_info_resp {
+ enum aie4_msg_status status;
+ __u16 major;
+ __u16 minor;
+} __packed;
+
struct aie4_msg_query_cert_firmware_version_req {
__u32 resvd;
} __packed;
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index 1eeb1cb73b27..1cbd1665a28f 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -289,6 +289,10 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev)
if (ret)
return ret;
+ ret = aie4_query_aie_version(ndev, &ndev->aie.version);
+ if (ret)
+ return ret;
+
ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata);
if (ret)
return ret;
@@ -595,6 +599,12 @@ static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
case DRM_AMDXDNA_QUERY_AIE_METADATA:
ret = amdxdna_get_metadata(&ndev->aie, client, args);
break;
+ case DRM_AMDXDNA_QUERY_AIE_VERSION:
+ ret = amdxdna_get_aie_version(client, args, &ndev->aie.version);
+ break;
+ case DRM_AMDXDNA_QUERY_FIRMWARE_VERSION:
+ ret = amdxdna_get_firmware_version(client, args, &xdna->fw_ver);
+ break;
default:
XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
ret = -EOPNOTSUPP;
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 940e67347d74..5ae5e8427a3b 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -69,6 +69,8 @@ enum aie4_fw_feature {
/* aie4_message.c */
int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_aie_metadata *metadata);
+int aie4_query_aie_version(struct amdxdna_dev_hdl *ndev,
+ struct amdxdna_drm_query_aie_version *version);
int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev);
int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev);
int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 06/19] accel/amdxdna: Add AIE version query to aie4_get_info
2026-10-09 22:53 ` [PATCH V4 06/19] accel/amdxdna: Add AIE version query to aie4_get_info David Zhang
@ 2026-10-12 20:55 ` Lizhi Hou
0 siblings, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-12 20:55 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello, Hayden Laccabue
On 10/9/26 15:53, David Zhang wrote:
> Add AIE version query via DRM_AMDXDNA_GET_INFO. The NPU firmware
> version query already existed internally; it is now also exposed
> through this ioctl alongside the new AIE version query.
>
> These versions are mandatory once released, the firmware management
> interfaces must support those queries in their stable version.
> Propagating any failure to abort device initialization is intentional.
>
> Co-developed-by: Hayden Laccabue <hayden.laccabue@amd.com>
> Signed-off-by: Hayden Laccabue <hayden.laccabue@amd.com>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> ---
> drivers/accel/amdxdna/aie4_message.c | 20 ++++++++++++++++++++
> drivers/accel/amdxdna/aie4_msg_priv.h | 11 +++++++++++
> drivers/accel/amdxdna/aie4_pci.c | 10 ++++++++++
> drivers/accel/amdxdna/aie4_pci.h | 2 ++
> 4 files changed, 43 insertions(+)
>
> diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
> index f67aa8ba943c..c83f81a0e65b 100644
> --- a/drivers/accel/amdxdna/aie4_message.c
> +++ b/drivers/accel/amdxdna/aie4_message.c
> @@ -75,6 +75,26 @@ int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
> return 0;
> }
>
> +int aie4_query_aie_version(struct amdxdna_dev_hdl *ndev,
> + struct amdxdna_drm_query_aie_version *version)
> +{
> + DECLARE_AIE_MSG(aie4_msg_aie4_version_info, AIE4_MSG_OP_AIE_VERSION_INFO);
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> + int ret;
> +
> + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> + if (ret)
> + return ret;
> +
> + XDNA_DBG(xdna, "Query AIE version - major: %u minor: %u",
> + resp.major, resp.minor);
> +
> + version->major = resp.major;
> + version->minor = resp.minor;
> +
> + return 0;
> +}
> +
> int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_firmware_version *fw_version)
> {
> diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
> index b9f7c61f36e3..81842fa1d6ce 100644
> --- a/drivers/accel/amdxdna/aie4_msg_priv.h
> +++ b/drivers/accel/amdxdna/aie4_msg_priv.h
> @@ -22,6 +22,7 @@ enum aie4_msg_opcode {
> AIE4_MSG_OP_CREATE_HW_CONTEXT = 0x30003,
> AIE4_MSG_OP_DESTROY_HW_CONTEXT = 0x30004,
> AIE4_MSG_OP_AIE_TILE_INFO = 0x30006,
> + AIE4_MSG_OP_AIE_VERSION_INFO = 0x30007,
>
> AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
> };
> @@ -160,6 +161,16 @@ struct aie4_msg_aie4_tile_info_resp {
> struct aie4_tile_info info;
> } __packed;
>
> +struct aie4_msg_aie4_version_info_req {
> + __u32 resvd;
> +} __packed;
> +
> +struct aie4_msg_aie4_version_info_resp {
> + enum aie4_msg_status status;
> + __u16 major;
> + __u16 minor;
> +} __packed;
> +
> struct aie4_msg_query_cert_firmware_version_req {
> __u32 resvd;
> } __packed;
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index 1eeb1cb73b27..1cbd1665a28f 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -289,6 +289,10 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev)
> if (ret)
> return ret;
>
> + ret = aie4_query_aie_version(ndev, &ndev->aie.version);
> + if (ret)
> + return ret;
> +
> ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata);
> if (ret)
> return ret;
> @@ -595,6 +599,12 @@ static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
> case DRM_AMDXDNA_QUERY_AIE_METADATA:
> ret = amdxdna_get_metadata(&ndev->aie, client, args);
> break;
> + case DRM_AMDXDNA_QUERY_AIE_VERSION:
> + ret = amdxdna_get_aie_version(client, args, &ndev->aie.version);
> + break;
> + case DRM_AMDXDNA_QUERY_FIRMWARE_VERSION:
> + ret = amdxdna_get_firmware_version(client, args, &xdna->fw_ver);
> + break;
> default:
> XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
> ret = -EOPNOTSUPP;
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index 940e67347d74..5ae5e8427a3b 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -69,6 +69,8 @@ enum aie4_fw_feature {
> /* aie4_message.c */
> int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_aie_metadata *metadata);
> +int aie4_query_aie_version(struct amdxdna_dev_hdl *ndev,
> + struct amdxdna_drm_query_aie_version *version);
> int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev);
> int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev);
> int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 07/19] accel/amdxdna: Add get and set power_mode for AIE4
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (5 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 06/19] accel/amdxdna: Add AIE version query to aie4_get_info David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-12 21:29 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 08/19] accel/amdxdna: Add clock, DPM frequency, and resource info queries " David Zhang
` (11 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello, Soham Donwalkar,
Nishad Saraf
Add power mode support for AIE4 devices via DRM_AMDXDNA_GET_INFO and
DRM_AMDXDNA_SET_STATE:
- Add AIE4_MSG_OP_POWER_OVERRIDE mailbox support
- Add DRM_AMDXDNA_GET_POWER_MODE support
- Implement aie4_set_power_mode() and wire .set_aie_state
Firmware boots in POWER_MODE_DEFAULT after a reload, so re-send the
cached user power mode override whenever the hardware starts via
aie4_restore_power_mode(). On a fresh probe, pw_mode is
POWER_MODE_DEFAULT.
Co-developed-by: Soham Donwalkar <soham.donwalkar@amd.com>
Signed-off-by: Soham Donwalkar <soham.donwalkar@amd.com>
Co-developed-by: Nishad Saraf <nishad.saraf@amd.com>
Signed-off-by: Nishad Saraf <nishad.saraf@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_message.c | 17 ++++
drivers/accel/amdxdna/aie4_msg_priv.h | 9 ++
drivers/accel/amdxdna/aie4_pci.c | 116 ++++++++++++++++++++++++++
drivers/accel/amdxdna/aie4_pci.h | 6 ++
4 files changed, 148 insertions(+)
diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
index c83f81a0e65b..8d1cad50cbab 100644
--- a/drivers/accel/amdxdna/aie4_message.c
+++ b/drivers/accel/amdxdna/aie4_message.c
@@ -158,3 +158,20 @@ int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev)
return ret;
}
+
+int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode)
+{
+ DECLARE_AIE_MSG(aie4_msg_power_override, AIE4_MSG_OP_POWER_OVERRIDE);
+ int ret;
+
+ req.power_mode = power_mode;
+
+ ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ if (ret)
+ XDNA_WARN(ndev->aie.xdna,
+ "Failed to set power mode %u, ret %d", (u32)power_mode, ret);
+ else
+ XDNA_DBG(ndev->aie.xdna, "Power mode set to %u", (u32)power_mode);
+
+ return ret;
+}
diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
index 81842fa1d6ce..4c06792df1bd 100644
--- a/drivers/accel/amdxdna/aie4_msg_priv.h
+++ b/drivers/accel/amdxdna/aie4_msg_priv.h
@@ -23,6 +23,7 @@ enum aie4_msg_opcode {
AIE4_MSG_OP_DESTROY_HW_CONTEXT = 0x30004,
AIE4_MSG_OP_AIE_TILE_INFO = 0x30006,
AIE4_MSG_OP_AIE_VERSION_INFO = 0x30007,
+ AIE4_MSG_OP_POWER_OVERRIDE = 0x3000B,
AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
};
@@ -187,6 +188,14 @@ struct aie4_msg_query_cert_firmware_version_resp {
__u16 host_queue_minor;
} __packed;
+struct aie4_msg_power_override_req {
+ __u32 power_mode;
+} __packed;
+
+struct aie4_msg_power_override_resp {
+ enum aie4_msg_status status;
+} __packed;
+
#define AIE4_WORK_BUFFER_MIN_SIZE SZ_4M
struct aie4_msg_attach_work_buffer_req {
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index 1cbd1665a28f..6eacdc026ec7 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -4,6 +4,7 @@
*/
#include <drm/amdxdna_accel.h>
+#include <drm/drm_drv.h>
#include <drm/drm_managed.h>
#include <drm/drm_print.h>
#include <linux/firmware.h>
@@ -16,6 +17,7 @@
#include "amdxdna_mailbox.h"
#include "amdxdna_mailbox_helper.h"
#include "amdxdna_pci_drv.h"
+#include "amdxdna_pm.h"
#define NO_IOHUB 0
#define PSP_NOTIFY_INTR 0xD007BE11
@@ -300,6 +302,15 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev)
return 0;
}
+/* Restore cached power mode override across hardware start. */
+int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev)
+{
+ if (ndev->pw_mode == POWER_MODE_DEFAULT)
+ return 0;
+
+ return aie4_msg_set_power_mode(ndev, ndev->pw_mode);
+}
+
static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
{
int ret;
@@ -316,6 +327,10 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
if (ret)
goto mbox_fini;
+ ret = aie4_restore_power_mode(ndev);
+ if (ret)
+ goto mbox_fini;
+
return 0;
mbox_fini:
@@ -353,8 +368,14 @@ static int aie4_vf_hw_start(struct amdxdna_dev_hdl *ndev)
if (ret)
goto mailbox_fini;
+ ret = aie4_restore_power_mode(ndev);
+ if (ret)
+ goto partition_fini;
+
return 0;
+partition_fini:
+ aie4_partition_fini(ndev);
mailbox_fini:
aie4_mailbox_fini(ndev);
return ret;
@@ -394,8 +415,14 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
if (ret)
goto mailbox_fini;
+ ret = aie4_restore_power_mode(ndev);
+ if (ret)
+ goto partition_fini;
+
return 0;
+partition_fini:
+ aie4_partition_fini(ndev);
mailbox_fini:
aie4_mailbox_fini(ndev);
stop_fw:
@@ -535,6 +562,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
ndev->priv = xdna->dev_info->dev_priv;
ndev->aie.xdna = xdna;
+ ndev->pw_mode = POWER_MODE_DEFAULT;
xdna->dev_handle = ndev;
xa_init_flags(&ndev->cert_comp_xa, XA_FLAGS_ALLOC);
@@ -589,6 +617,24 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
return 0;
}
+static int aie4_get_power_mode(struct amdxdna_client *client,
+ struct amdxdna_drm_get_info *args)
+{
+ struct amdxdna_drm_get_power_mode mode = {};
+ struct amdxdna_dev *xdna = client->xdna;
+ struct amdxdna_dev_hdl *ndev;
+ u32 buf_sz;
+
+ ndev = xdna->dev_handle;
+ mode.power_mode = ndev->pw_mode;
+
+ buf_sz = min_t(u32, args->buffer_size, sizeof(mode));
+ if (copy_to_user(u64_to_user_ptr(args->buffer), &mode, buf_sz))
+ return -EFAULT;
+
+ return 0;
+}
+
static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args)
{
struct amdxdna_dev *xdna = client->xdna;
@@ -605,6 +651,9 @@ static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
case DRM_AMDXDNA_QUERY_FIRMWARE_VERSION:
ret = amdxdna_get_firmware_version(client, args, &xdna->fw_ver);
break;
+ case DRM_AMDXDNA_GET_POWER_MODE:
+ ret = aie4_get_power_mode(client, args);
+ break;
default:
XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
ret = -EOPNOTSUPP;
@@ -615,6 +664,71 @@ static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
return ret;
}
+static int aie4_set_power_mode(struct amdxdna_client *client,
+ struct amdxdna_drm_set_state *args)
+{
+ struct amdxdna_drm_set_power_mode power_state = { 0 };
+ struct amdxdna_dev *xdna = client->xdna;
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ u8 power_mode;
+ int ret;
+
+ if (args->buffer_size < sizeof(power_state))
+ return -EINVAL;
+
+ if (copy_from_user(&power_state, u64_to_user_ptr(args->buffer),
+ sizeof(power_state))) {
+ XDNA_ERR(xdna, "Failed to copy power mode request into kernel");
+ return -EFAULT;
+ }
+
+ if (XDNA_MBZ_DBG(xdna, power_state.pad, sizeof(power_state.pad)))
+ return -EINVAL;
+
+ power_mode = power_state.power_mode;
+ if (power_mode > POWER_MODE_TURBO) {
+ XDNA_ERR(xdna, "Invalid power mode %d", power_mode);
+ return -EINVAL;
+ }
+
+ ret = aie4_msg_set_power_mode(xdna->dev_handle, power_mode);
+ if (ret)
+ return ret;
+
+ ndev->pw_mode = power_mode;
+ return 0;
+}
+
+static int aie4_set_state(struct amdxdna_client *client,
+ struct amdxdna_drm_set_state *args)
+{
+ struct amdxdna_dev *xdna = client->xdna;
+ int ret, idx;
+
+ if (!drm_dev_enter(&xdna->ddev, &idx))
+ return -ENODEV;
+
+ ret = amdxdna_pm_resume_get_locked(xdna);
+ if (ret)
+ goto dev_exit;
+
+ switch (args->param) {
+ case DRM_AMDXDNA_SET_POWER_MODE:
+ ret = aie4_set_power_mode(client, args);
+ break;
+ default:
+ XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
+ ret = -EOPNOTSUPP;
+ break;
+ }
+
+ amdxdna_pm_suspend_put(xdna);
+
+dev_exit:
+ drm_dev_exit(idx);
+ return ret;
+}
+
static int aie4_alloc_work_buffer(struct amdxdna_dev_hdl *ndev)
{
struct amdxdna_dev *xdna = ndev->aie.xdna;
@@ -737,6 +851,7 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
.hwctx_fini = aie4_hwctx_fini,
.cmd_wait = aie4_cmd_wait,
.get_aie_info = aie4_get_info,
+ .set_aie_state = aie4_set_state,
};
const struct amdxdna_dev_ops aie4_classic_ops = {
@@ -746,4 +861,5 @@ const struct amdxdna_dev_ops aie4_classic_ops = {
.hwctx_fini = aie4_hwctx_fini,
.cmd_wait = aie4_cmd_wait,
.get_aie_info = aie4_get_info,
+ .set_aie_state = aie4_set_state,
};
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 5ae5e8427a3b..fd2c50dc8080 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -58,6 +58,8 @@ struct amdxdna_dev_hdl {
dma_addr_t work_buf_addr;
u32 work_buf_size;
+ u8 pw_mode;
+
struct amdxdna_drm_query_firmware_version cert_version;
};
@@ -77,6 +79,7 @@ int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_firmware_version *fw_version);
int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_firmware_version *cert_version);
+int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode);
u32 aie4_msg_pasid(struct amdxdna_client *client);
/* aie4_ctx.c */
@@ -84,6 +87,9 @@ int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx);
int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
+/* aie4_pci.c */
+int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev);
+
/* aie4_sriov.c */
#if IS_ENABLED(CONFIG_PCI_IOV)
int aie4_sriov_configure(struct amdxdna_dev *xdna, int num_vfs);
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 07/19] accel/amdxdna: Add get and set power_mode for AIE4
2026-10-09 22:53 ` [PATCH V4 07/19] accel/amdxdna: Add get and set power_mode for AIE4 David Zhang
@ 2026-10-12 21:29 ` Lizhi Hou
0 siblings, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-12 21:29 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello, Soham Donwalkar, Nishad Saraf
On 10/9/26 15:53, David Zhang wrote:
> Add power mode support for AIE4 devices via DRM_AMDXDNA_GET_INFO and
> DRM_AMDXDNA_SET_STATE:
> - Add AIE4_MSG_OP_POWER_OVERRIDE mailbox support
> - Add DRM_AMDXDNA_GET_POWER_MODE support
> - Implement aie4_set_power_mode() and wire .set_aie_state
>
> Firmware boots in POWER_MODE_DEFAULT after a reload, so re-send the
> cached user power mode override whenever the hardware starts via
> aie4_restore_power_mode(). On a fresh probe, pw_mode is
> POWER_MODE_DEFAULT.
>
> Co-developed-by: Soham Donwalkar <soham.donwalkar@amd.com>
> Signed-off-by: Soham Donwalkar <soham.donwalkar@amd.com>
> Co-developed-by: Nishad Saraf <nishad.saraf@amd.com>
> Signed-off-by: Nishad Saraf <nishad.saraf@amd.com>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie4_message.c | 17 ++++
> drivers/accel/amdxdna/aie4_msg_priv.h | 9 ++
> drivers/accel/amdxdna/aie4_pci.c | 116 ++++++++++++++++++++++++++
> drivers/accel/amdxdna/aie4_pci.h | 6 ++
> 4 files changed, 148 insertions(+)
>
> diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
> index c83f81a0e65b..8d1cad50cbab 100644
> --- a/drivers/accel/amdxdna/aie4_message.c
> +++ b/drivers/accel/amdxdna/aie4_message.c
> @@ -158,3 +158,20 @@ int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev)
>
> return ret;
> }
> +
> +int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode)
> +{
> + DECLARE_AIE_MSG(aie4_msg_power_override, AIE4_MSG_OP_POWER_OVERRIDE);
> + int ret;
> +
> + req.power_mode = power_mode;
> +
> + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> + if (ret)
> + XDNA_WARN(ndev->aie.xdna,
Should be XDNA_ERR().
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> + "Failed to set power mode %u, ret %d", (u32)power_mode, ret);
> + else
> + XDNA_DBG(ndev->aie.xdna, "Power mode set to %u", (u32)power_mode);
> +
> + return ret;
> +}
> diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
> index 81842fa1d6ce..4c06792df1bd 100644
> --- a/drivers/accel/amdxdna/aie4_msg_priv.h
> +++ b/drivers/accel/amdxdna/aie4_msg_priv.h
> @@ -23,6 +23,7 @@ enum aie4_msg_opcode {
> AIE4_MSG_OP_DESTROY_HW_CONTEXT = 0x30004,
> AIE4_MSG_OP_AIE_TILE_INFO = 0x30006,
> AIE4_MSG_OP_AIE_VERSION_INFO = 0x30007,
> + AIE4_MSG_OP_POWER_OVERRIDE = 0x3000B,
>
> AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
> };
> @@ -187,6 +188,14 @@ struct aie4_msg_query_cert_firmware_version_resp {
> __u16 host_queue_minor;
> } __packed;
>
> +struct aie4_msg_power_override_req {
> + __u32 power_mode;
> +} __packed;
> +
> +struct aie4_msg_power_override_resp {
> + enum aie4_msg_status status;
> +} __packed;
> +
> #define AIE4_WORK_BUFFER_MIN_SIZE SZ_4M
>
> struct aie4_msg_attach_work_buffer_req {
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index 1cbd1665a28f..6eacdc026ec7 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -4,6 +4,7 @@
> */
>
> #include <drm/amdxdna_accel.h>
> +#include <drm/drm_drv.h>
> #include <drm/drm_managed.h>
> #include <drm/drm_print.h>
> #include <linux/firmware.h>
> @@ -16,6 +17,7 @@
> #include "amdxdna_mailbox.h"
> #include "amdxdna_mailbox_helper.h"
> #include "amdxdna_pci_drv.h"
> +#include "amdxdna_pm.h"
>
> #define NO_IOHUB 0
> #define PSP_NOTIFY_INTR 0xD007BE11
> @@ -300,6 +302,15 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev)
> return 0;
> }
>
> +/* Restore cached power mode override across hardware start. */
> +int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev)
> +{
> + if (ndev->pw_mode == POWER_MODE_DEFAULT)
> + return 0;
> +
> + return aie4_msg_set_power_mode(ndev, ndev->pw_mode);
> +}
> +
> static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
> {
> int ret;
> @@ -316,6 +327,10 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
> if (ret)
> goto mbox_fini;
>
> + ret = aie4_restore_power_mode(ndev);
> + if (ret)
> + goto mbox_fini;
> +
> return 0;
>
> mbox_fini:
> @@ -353,8 +368,14 @@ static int aie4_vf_hw_start(struct amdxdna_dev_hdl *ndev)
> if (ret)
> goto mailbox_fini;
>
> + ret = aie4_restore_power_mode(ndev);
> + if (ret)
> + goto partition_fini;
> +
> return 0;
>
> +partition_fini:
> + aie4_partition_fini(ndev);
> mailbox_fini:
> aie4_mailbox_fini(ndev);
> return ret;
> @@ -394,8 +415,14 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
> if (ret)
> goto mailbox_fini;
>
> + ret = aie4_restore_power_mode(ndev);
> + if (ret)
> + goto partition_fini;
> +
> return 0;
>
> +partition_fini:
> + aie4_partition_fini(ndev);
> mailbox_fini:
> aie4_mailbox_fini(ndev);
> stop_fw:
> @@ -535,6 +562,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
>
> ndev->priv = xdna->dev_info->dev_priv;
> ndev->aie.xdna = xdna;
> + ndev->pw_mode = POWER_MODE_DEFAULT;
> xdna->dev_handle = ndev;
>
> xa_init_flags(&ndev->cert_comp_xa, XA_FLAGS_ALLOC);
> @@ -589,6 +617,24 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
> return 0;
> }
>
> +static int aie4_get_power_mode(struct amdxdna_client *client,
> + struct amdxdna_drm_get_info *args)
> +{
> + struct amdxdna_drm_get_power_mode mode = {};
> + struct amdxdna_dev *xdna = client->xdna;
> + struct amdxdna_dev_hdl *ndev;
> + u32 buf_sz;
> +
> + ndev = xdna->dev_handle;
> + mode.power_mode = ndev->pw_mode;
> +
> + buf_sz = min_t(u32, args->buffer_size, sizeof(mode));
> + if (copy_to_user(u64_to_user_ptr(args->buffer), &mode, buf_sz))
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args)
> {
> struct amdxdna_dev *xdna = client->xdna;
> @@ -605,6 +651,9 @@ static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
> case DRM_AMDXDNA_QUERY_FIRMWARE_VERSION:
> ret = amdxdna_get_firmware_version(client, args, &xdna->fw_ver);
> break;
> + case DRM_AMDXDNA_GET_POWER_MODE:
> + ret = aie4_get_power_mode(client, args);
> + break;
> default:
> XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
> ret = -EOPNOTSUPP;
> @@ -615,6 +664,71 @@ static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
> return ret;
> }
>
> +static int aie4_set_power_mode(struct amdxdna_client *client,
> + struct amdxdna_drm_set_state *args)
> +{
> + struct amdxdna_drm_set_power_mode power_state = { 0 };
> + struct amdxdna_dev *xdna = client->xdna;
> + struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
> + u8 power_mode;
> + int ret;
> +
> + if (args->buffer_size < sizeof(power_state))
> + return -EINVAL;
> +
> + if (copy_from_user(&power_state, u64_to_user_ptr(args->buffer),
> + sizeof(power_state))) {
> + XDNA_ERR(xdna, "Failed to copy power mode request into kernel");
> + return -EFAULT;
> + }
> +
> + if (XDNA_MBZ_DBG(xdna, power_state.pad, sizeof(power_state.pad)))
> + return -EINVAL;
> +
> + power_mode = power_state.power_mode;
> + if (power_mode > POWER_MODE_TURBO) {
> + XDNA_ERR(xdna, "Invalid power mode %d", power_mode);
> + return -EINVAL;
> + }
> +
> + ret = aie4_msg_set_power_mode(xdna->dev_handle, power_mode);
> + if (ret)
> + return ret;
> +
> + ndev->pw_mode = power_mode;
> + return 0;
> +}
> +
> +static int aie4_set_state(struct amdxdna_client *client,
> + struct amdxdna_drm_set_state *args)
> +{
> + struct amdxdna_dev *xdna = client->xdna;
> + int ret, idx;
> +
> + if (!drm_dev_enter(&xdna->ddev, &idx))
> + return -ENODEV;
> +
> + ret = amdxdna_pm_resume_get_locked(xdna);
> + if (ret)
> + goto dev_exit;
> +
> + switch (args->param) {
> + case DRM_AMDXDNA_SET_POWER_MODE:
> + ret = aie4_set_power_mode(client, args);
> + break;
> + default:
> + XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
> + ret = -EOPNOTSUPP;
> + break;
> + }
> +
> + amdxdna_pm_suspend_put(xdna);
> +
> +dev_exit:
> + drm_dev_exit(idx);
> + return ret;
> +}
> +
> static int aie4_alloc_work_buffer(struct amdxdna_dev_hdl *ndev)
> {
> struct amdxdna_dev *xdna = ndev->aie.xdna;
> @@ -737,6 +851,7 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
> .hwctx_fini = aie4_hwctx_fini,
> .cmd_wait = aie4_cmd_wait,
> .get_aie_info = aie4_get_info,
> + .set_aie_state = aie4_set_state,
> };
>
> const struct amdxdna_dev_ops aie4_classic_ops = {
> @@ -746,4 +861,5 @@ const struct amdxdna_dev_ops aie4_classic_ops = {
> .hwctx_fini = aie4_hwctx_fini,
> .cmd_wait = aie4_cmd_wait,
> .get_aie_info = aie4_get_info,
> + .set_aie_state = aie4_set_state,
> };
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index 5ae5e8427a3b..fd2c50dc8080 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -58,6 +58,8 @@ struct amdxdna_dev_hdl {
> dma_addr_t work_buf_addr;
> u32 work_buf_size;
>
> + u8 pw_mode;
> +
> struct amdxdna_drm_query_firmware_version cert_version;
> };
>
> @@ -77,6 +79,7 @@ int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_firmware_version *fw_version);
> int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_firmware_version *cert_version);
> +int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode);
> u32 aie4_msg_pasid(struct amdxdna_client *client);
>
> /* aie4_ctx.c */
> @@ -84,6 +87,9 @@ int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
> void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx);
> int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
>
> +/* aie4_pci.c */
> +int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev);
> +
> /* aie4_sriov.c */
> #if IS_ENABLED(CONFIG_PCI_IOV)
> int aie4_sriov_configure(struct amdxdna_dev *xdna, int num_vfs);
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 08/19] accel/amdxdna: Add clock, DPM frequency, and resource info queries for AIE4
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (6 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 07/19] accel/amdxdna: Add get and set power_mode for AIE4 David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-09 23:12 ` sashiko-bot
2026-10-12 22:58 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 09/19] accel/amdxdna: Add context switch hysteresis with debugfs control David Zhang
` (10 subsequent siblings)
18 siblings, 2 replies; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello, Soham Donwalkar
Add support for querying clock metadata, DPM frequency table, and
hardware resource information for AIE4/NPU3 devices:
- Move struct dpm_clk_freq and common clock/TOPS counters into struct
aie_device.
- Add NPU3 DPM clock table, DPM control, and counter updates by querying
active DPM levels via AIE4_MSG_OP_GET_CURRENT_DPM_LEVEL.
- Query AIE4 DPM frequency table from firmware via
AIE4_MSG_OP_GET_DPM_FREQ_TABLE.
Co-developed-by: Soham Donwalkar <soham.donwalkar@amd.com>
Signed-off-by: Soham Donwalkar <soham.donwalkar@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie.h | 36 +++++++++++
drivers/accel/amdxdna/aie2_pci.c | 14 ++---
drivers/accel/amdxdna/aie2_pci.h | 35 +----------
drivers/accel/amdxdna/aie2_pm.c | 10 +--
drivers/accel/amdxdna/aie4_message.c | 88 +++++++++++++++++++++++++++
drivers/accel/amdxdna/aie4_msg_priv.h | 31 ++++++++++
drivers/accel/amdxdna/aie4_pci.c | 82 ++++++++++++++++++++++++-
drivers/accel/amdxdna/aie4_pci.h | 12 ++++
drivers/accel/amdxdna/npu1_regs.c | 19 +++---
drivers/accel/amdxdna/npu3_regs.c | 78 ++++++++++++++++++++++++
drivers/accel/amdxdna/npu4_regs.c | 30 ++++-----
11 files changed, 367 insertions(+), 68 deletions(-)
diff --git a/drivers/accel/amdxdna/aie.h b/drivers/accel/amdxdna/aie.h
index 229b3cfa2361..a7276c25844f 100644
--- a/drivers/accel/amdxdna/aie.h
+++ b/drivers/accel/amdxdna/aie.h
@@ -30,8 +30,44 @@ struct aie_device {
struct amdxdna_drm_query_aie_version version;
struct amdxdna_drm_query_aie_metadata metadata;
+
+ u32 clk_gating;
+ u32 npuclk_freq;
+ u32 hclk_freq;
+ u32 max_tops;
+ u32 curr_tops;
+};
+
+struct aie_hw_ops {
+ int (*set_dpm)(struct aie_device *aie, u32 dpm_level);
+ int (*update_counters)(struct aie_device *aie);
};
+#define aie_update_counters(ndev) \
+({ \
+ typeof(ndev) _ndev = ndev; \
+ if ((_ndev)->priv->hw_ops && (_ndev)->priv->hw_ops->update_counters) \
+ (_ndev)->priv->hw_ops->update_counters(&(_ndev)->aie); \
+})
+
+struct dpm_clk_freq {
+ u32 npuclk;
+ u32 hclk;
+};
+
+#include <linux/amd-pmf-io.h>
+
+#if IS_ENABLED(CONFIG_AMD_PMF)
+#define AIE_GET_PMF_NPU_METRICS(metrics) amd_pmf_get_npu_data(metrics)
+#else
+#define AIE_GET_PMF_NPU_METRICS(metrics) \
+({ \
+ typeof(metrics) _m = metrics; \
+ memset(_m, 0xff, sizeof(*_m)); \
+ (-EOPNOTSUPP); \
+})
+#endif
+
#define DECLARE_AIE_MSG(name, op) \
DECLARE_XDNA_MSG_COMMON(name, op, -1)
#define AIE_FEATURE_ON(aie, feature) test_bit(feature, &(aie)->feature_mask)
diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c
index 6fa79698f9d8..1b029d33a24b 100644
--- a/drivers/accel/amdxdna/aie2_pci.c
+++ b/drivers/accel/amdxdna/aie2_pci.c
@@ -296,7 +296,7 @@ static struct xrs_action_ops aie2_xrs_actions = {
static void aie2_smu_fini(struct amdxdna_dev_hdl *ndev)
{
- ndev->priv->hw_ops->set_dpm(ndev, 0);
+ ndev->priv->hw_ops->set_dpm(&ndev->aie, 0);
aie_smu_fini(ndev->aie.smu_hdl);
}
@@ -718,12 +718,12 @@ static int aie2_get_clock_metadata(struct amdxdna_client *client,
if (!clock)
return -ENOMEM;
- aie2_update_counters(ndev);
+ aie_update_counters(ndev);
snprintf(clock->mp_npu_clock.name, sizeof(clock->mp_npu_clock.name),
"MP-NPU Clock");
- clock->mp_npu_clock.freq_mhz = ndev->npuclk_freq;
+ clock->mp_npu_clock.freq_mhz = ndev->aie.npuclk_freq;
snprintf(clock->h_clock.name, sizeof(clock->h_clock.name), "H Clock");
- clock->h_clock.freq_mhz = ndev->hclk_freq;
+ clock->h_clock.freq_mhz = ndev->aie.hclk_freq;
buf_sz = min(args->buffer_size, sizeof(*clock));
if (copy_to_user(u64_to_user_ptr(args->buffer), clock, buf_sz))
@@ -879,11 +879,11 @@ static int aie2_query_resource_info(struct amdxdna_client *client,
ndev = xdna->dev_handle;
priv = ndev->priv;
- aie2_update_counters(ndev);
+ aie_update_counters(ndev);
res_info.npu_clk_max = priv->dpm_clk_tbl[ndev->max_dpm_level].hclk;
- res_info.npu_tops_max = ndev->max_tops;
+ res_info.npu_tops_max = ndev->aie.max_tops;
res_info.npu_task_max = priv->hwctx_limit;
- res_info.npu_tops_curr = ndev->curr_tops;
+ res_info.npu_tops_curr = ndev->aie.curr_tops;
res_info.npu_task_curr = ndev->hwctx_num;
buf_sz = min(args->buffer_size, sizeof(res_info));
diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h
index b31f73082c17..709e7545c65f 100644
--- a/drivers/accel/amdxdna/aie2_pci.h
+++ b/drivers/accel/amdxdna/aie2_pci.h
@@ -40,8 +40,8 @@
pci_resource_len(NDEV2PDEV(_ndev), (_ndev)->aie.xdna->dev_info->mbox_bar); \
})
+#define AIE2_GET_PMF_NPU_METRICS(metrics) AIE_GET_PMF_NPU_METRICS(metrics)
#if IS_ENABLED(CONFIG_AMD_PMF)
-#define AIE2_GET_PMF_NPU_METRICS(metrics) amd_pmf_get_npu_data(metrics)
#define AIE2_GET_PMF_NPU_DATA(field, val) \
({ \
struct amd_pmf_npu_metrics _npu_metrics; \
@@ -52,13 +52,6 @@
(_ret); \
})
#else
-#define AIE2_GET_PMF_NPU_METRICS(metrics) \
-({ \
- typeof(metrics) _m = metrics; \
- memset(_m, 0xff, sizeof(*_m)); \
- (-EOPNOTSUPP); \
-})
-
#define SENSOR_DEFAULT_npu_power U32_MAX
#define AIE2_GET_PMF_NPU_DATA(field, val) \
({ \
@@ -91,11 +84,6 @@ struct rt_config {
unsigned long feature_mask;
};
-struct dpm_clk_freq {
- u32 npuclk;
- u32 hclk;
-};
-
/*
* Define the maximum number of pending commands in a hardware context.
* Must be power of 2!
@@ -158,11 +146,6 @@ struct amdxdna_dev_hdl {
u32 dpm_level;
u32 dft_dpm_level;
u32 max_dpm_level;
- u32 clk_gating;
- u32 npuclk_freq;
- u32 hclk_freq;
- u32 max_tops;
- u32 curr_tops;
u32 force_preempt_enabled;
u32 frame_boundary_preempt;
@@ -177,18 +160,6 @@ struct amdxdna_dev_hdl {
unsigned long last_signal_ts;
};
-struct aie2_hw_ops {
- int (*set_dpm)(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
- int (*update_counters)(struct amdxdna_dev_hdl *ndev);
-};
-
-#define aie2_update_counters(ndev) \
-({ \
- typeof(ndev) _ndev = ndev; \
- if (_ndev->priv->hw_ops->update_counters) \
- _ndev->priv->hw_ops->update_counters(_ndev); \
-})
-
enum aie2_fw_feature {
AIE2_NPU_COMMAND,
AIE2_PREEMPT,
@@ -219,7 +190,7 @@ struct amdxdna_dev_priv {
struct aie_bar_off_pair sram_offs[SRAM_MAX_INDEX];
struct aie_bar_off_pair psp_regs_off[PSP_MAX_REGS];
struct aie_bar_off_pair smu_regs_off[SMU_MAX_REGS];
- const struct aie2_hw_ops *hw_ops;
+ const struct aie_hw_ops *hw_ops;
};
extern const struct amdxdna_dev_ops aie2_ops;
@@ -234,7 +205,7 @@ extern const struct rt_config npu1_default_rt_cfg[];
extern const struct rt_config npu4_default_rt_cfg[];
extern const struct amdxdna_fw_feature_tbl npu4_fw_feature_table[];
extern const struct amdxdna_rev_vbnv npu4_rev_vbnv_tbl[];
-extern const struct aie2_hw_ops npu4_hw_ops;
+extern const struct aie_hw_ops npu4_hw_ops;
/* aie2_pm.c */
int aie2_pm_init(struct amdxdna_dev_hdl *ndev);
diff --git a/drivers/accel/amdxdna/aie2_pm.c b/drivers/accel/amdxdna/aie2_pm.c
index 4fe6030d2c41..f4ced7b67c25 100644
--- a/drivers/accel/amdxdna/aie2_pm.c
+++ b/drivers/accel/amdxdna/aie2_pm.c
@@ -23,7 +23,7 @@ static int aie2_pm_set_clk_gating(struct amdxdna_dev_hdl *ndev, u32 val)
if (ret)
return ret;
- ndev->clk_gating = val;
+ ndev->aie.clk_gating = val;
return 0;
}
@@ -35,7 +35,7 @@ int aie2_pm_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
if (ret)
return ret;
- ret = ndev->priv->hw_ops->set_dpm(ndev, dpm_level);
+ ret = ndev->priv->hw_ops->set_dpm(&ndev->aie, dpm_level);
if (!ret)
ndev->dpm_level = dpm_level;
amdxdna_pm_suspend_put(ndev->aie.xdna);
@@ -49,11 +49,11 @@ int aie2_pm_init(struct amdxdna_dev_hdl *ndev)
if (ndev->dev_status != AIE2_DEV_UNINIT) {
/* Resume device */
- ret = ndev->priv->hw_ops->set_dpm(ndev, ndev->dpm_level);
+ ret = ndev->priv->hw_ops->set_dpm(&ndev->aie, ndev->dpm_level);
if (ret)
return ret;
- ret = aie2_pm_set_clk_gating(ndev, ndev->clk_gating);
+ ret = aie2_pm_set_clk_gating(ndev, ndev->aie.clk_gating);
if (ret)
return ret;
@@ -64,7 +64,7 @@ int aie2_pm_init(struct amdxdna_dev_hdl *ndev)
ndev->max_dpm_level++;
ndev->max_dpm_level--;
- ret = ndev->priv->hw_ops->set_dpm(ndev, ndev->max_dpm_level);
+ ret = ndev->priv->hw_ops->set_dpm(&ndev->aie, ndev->max_dpm_level);
if (ret)
return ret;
ndev->dpm_level = ndev->max_dpm_level;
diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
index 8d1cad50cbab..263e23aff69f 100644
--- a/drivers/accel/amdxdna/aie4_message.c
+++ b/drivers/accel/amdxdna/aie4_message.c
@@ -141,6 +141,94 @@ int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
return 0;
}
+int aie4_init_dpm_freq_table(struct amdxdna_dev_hdl *ndev)
+{
+ DECLARE_AIE_MSG(aie4_msg_get_dpm_freq_table, AIE4_MSG_OP_GET_DPM_FREQ_TABLE);
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ u32 aie_levels, npu_levels, i;
+ int ret;
+
+ for (i = 0; i < AIE4_MAX_DPM_LEVEL_COUNT && ndev->priv->dpm_clk_tbl &&
+ ndev->priv->dpm_clk_tbl[i].hclk; i++)
+ ndev->dpm_clk_tbl[i] = ndev->priv->dpm_clk_tbl[i];
+ ndev->max_aieclk_level = i ? i - 1 : 0;
+ ndev->max_npuhclk_level = i ? i - 1 : 0;
+
+ ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ if (ret) {
+ XDNA_WARN(xdna, "Get DPM freq table failed, ret %d status 0x%x",
+ ret, resp.status);
+ return ret;
+ }
+
+ aie_levels = resp.aieclk_table.num_levels;
+ npu_levels = resp.npuhclk_table.num_levels;
+
+ if (!aie_levels || !npu_levels ||
+ aie_levels > AIE4_MAX_DPM_LEVEL_COUNT ||
+ npu_levels > AIE4_MAX_DPM_LEVEL_COUNT) {
+ XDNA_ERR(xdna, "invalid dpm levels, aieclk: %u, npuhclk: %u",
+ aie_levels, npu_levels);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < aie_levels; i++) {
+ if (!resp.aieclk_table.values[i]) {
+ XDNA_ERR(xdna, "invalid dpm aieclk frequency 0 at level %u", i);
+ return -EINVAL;
+ }
+ }
+
+ for (i = 0; i < npu_levels; i++) {
+ if (!resp.npuhclk_table.values[i]) {
+ XDNA_ERR(xdna, "invalid dpm npuhclk frequency 0 at level %u", i);
+ return -EINVAL;
+ }
+ }
+
+ memset(ndev->dpm_clk_tbl, 0, sizeof(ndev->dpm_clk_tbl));
+ for (i = 0; i < aie_levels; i++)
+ ndev->dpm_clk_tbl[i].npuclk = resp.aieclk_table.values[i];
+
+ for (i = 0; i < npu_levels; i++)
+ ndev->dpm_clk_tbl[i].hclk = resp.npuhclk_table.values[i];
+
+ ndev->max_aieclk_level = aie_levels - 1;
+ ndev->max_npuhclk_level = npu_levels - 1;
+
+ return 0;
+}
+
+int aie4_query_dpm_level(struct amdxdna_dev_hdl *ndev,
+ u32 *aieclk_dpm_level, u32 *npuhclk_dpm_level)
+{
+ DECLARE_AIE_MSG(aie4_msg_get_dpm_level, AIE4_MSG_OP_GET_CURRENT_DPM_LEVEL);
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ int ret;
+
+ ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ if (ret)
+ return ret;
+
+ /*
+ * Validate against ndev->max_aieclk_level and ndev->max_npuhclk_level
+ * to ensure reported levels index into populated entries in dpm_clk_tbl.
+ */
+ if (resp.aieclk_dpm_level > ndev->max_aieclk_level ||
+ resp.npuhclk_dpm_level > ndev->max_npuhclk_level) {
+ XDNA_ERR(xdna,
+ "invalid dpm level, aie: %u/%u, npu: %u/%u",
+ resp.aieclk_dpm_level, ndev->max_aieclk_level,
+ resp.npuhclk_dpm_level, ndev->max_npuhclk_level);
+ return -EINVAL;
+ }
+
+ *aieclk_dpm_level = resp.aieclk_dpm_level;
+ *npuhclk_dpm_level = resp.npuhclk_dpm_level;
+
+ return 0;
+}
+
int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev)
{
DECLARE_AIE_MSG(aie4_msg_attach_work_buffer, AIE4_MSG_OP_ATTACH_WORK_BUFFER);
diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
index 4c06792df1bd..fe78df9e23c8 100644
--- a/drivers/accel/amdxdna/aie4_msg_priv.h
+++ b/drivers/accel/amdxdna/aie4_msg_priv.h
@@ -24,6 +24,8 @@ enum aie4_msg_opcode {
AIE4_MSG_OP_AIE_TILE_INFO = 0x30006,
AIE4_MSG_OP_AIE_VERSION_INFO = 0x30007,
AIE4_MSG_OP_POWER_OVERRIDE = 0x3000B,
+ AIE4_MSG_OP_GET_DPM_FREQ_TABLE = 0x30012,
+ AIE4_MSG_OP_GET_CURRENT_DPM_LEVEL = 0x30013,
AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
};
@@ -196,6 +198,35 @@ struct aie4_msg_power_override_resp {
enum aie4_msg_status status;
} __packed;
+#define AIE4_MAX_DPM_LEVEL_COUNT 10
+
+struct aie4_dpm_table {
+ __u32 num_levels;
+ __u32 values[AIE4_MAX_DPM_LEVEL_COUNT];
+} __packed;
+
+/* AIE4_MSG_OP_GET_DPM_FREQ_TABLE */
+struct aie4_msg_get_dpm_freq_table_req {
+ __u32 rsvd;
+} __packed;
+
+struct aie4_msg_get_dpm_freq_table_resp {
+ enum aie4_msg_status status;
+ struct aie4_dpm_table aieclk_table;
+ struct aie4_dpm_table npuhclk_table;
+} __packed;
+
+/* AIE4_MSG_OP_GET_CURRENT_DPM_LEVEL */
+struct aie4_msg_get_dpm_level_req {
+ __u32 rsvd;
+} __packed;
+
+struct aie4_msg_get_dpm_level_resp {
+ enum aie4_msg_status status;
+ __u32 aieclk_dpm_level;
+ __u32 npuhclk_dpm_level;
+} __packed;
+
#define AIE4_WORK_BUFFER_MIN_SIZE SZ_4M
struct aie4_msg_attach_work_buffer_req {
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index 6eacdc026ec7..5593dfb6c7ed 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -299,6 +299,17 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev)
if (ret)
return ret;
+ ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols);
+
+ ret = aie4_init_dpm_freq_table(ndev);
+ if (ret) {
+ if (ret == -ETIME)
+ return ret;
+ /* if query dpm from fw failed, using default value */
+ if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm)
+ (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0);
+ }
+
return 0;
}
@@ -635,11 +646,71 @@ static int aie4_get_power_mode(struct amdxdna_client *client,
return 0;
}
+static int aie4_query_clock_metadata(struct amdxdna_client *client,
+ struct amdxdna_drm_get_info *args)
+{
+ struct amdxdna_drm_query_clock_metadata *clock;
+ struct amdxdna_dev *xdna = client->xdna;
+ struct amdxdna_dev_hdl *ndev;
+ int ret = 0;
+ u32 buf_sz;
+
+ ndev = xdna->dev_handle;
+ clock = kzalloc_obj(*clock);
+ if (!clock)
+ return -ENOMEM;
+
+ aie_update_counters(ndev);
+ snprintf(clock->mp_npu_clock.name, sizeof(clock->mp_npu_clock.name),
+ "MP-NPU Clock");
+ clock->mp_npu_clock.freq_mhz = ndev->aie.npuclk_freq;
+ snprintf(clock->h_clock.name, sizeof(clock->h_clock.name), "H Clock");
+ clock->h_clock.freq_mhz = ndev->aie.hclk_freq;
+
+ buf_sz = min_t(u32, args->buffer_size, sizeof(*clock));
+ if (copy_to_user(u64_to_user_ptr(args->buffer), clock, buf_sz))
+ ret = -EFAULT;
+
+ kfree(clock);
+ return ret;
+}
+
+static int aie4_query_resource_info(struct amdxdna_client *client,
+ struct amdxdna_drm_get_info *args)
+{
+ struct amdxdna_drm_get_resource_info res_info = {};
+ struct amdxdna_dev_hdl *ndev;
+ struct amdxdna_dev *xdna;
+ u32 buf_sz;
+
+ xdna = client->xdna;
+ ndev = xdna->dev_handle;
+
+ aie_update_counters(ndev);
+ res_info.npu_clk_max = ndev->dpm_clk_tbl[ndev->max_npuhclk_level].hclk;
+ res_info.npu_tops_max = ndev->aie.max_tops;
+ res_info.npu_tops_curr = ndev->aie.curr_tops;
+ /* Context accounting is populated in later patches in the series. */
+
+ buf_sz = min_t(u32, args->buffer_size, sizeof(res_info));
+ if (copy_to_user(u64_to_user_ptr(args->buffer), &res_info, buf_sz))
+ return -EFAULT;
+
+ return 0;
+}
+
static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args)
{
struct amdxdna_dev *xdna = client->xdna;
struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
- int ret;
+ int ret, idx;
+
+ if (!drm_dev_enter(&xdna->ddev, &idx))
+ return -ENODEV;
+
+ ret = amdxdna_pm_resume_get_locked(xdna);
+ if (ret)
+ goto dev_exit;
switch (args->param) {
case DRM_AMDXDNA_QUERY_AIE_METADATA:
@@ -648,19 +719,28 @@ static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
case DRM_AMDXDNA_QUERY_AIE_VERSION:
ret = amdxdna_get_aie_version(client, args, &ndev->aie.version);
break;
+ case DRM_AMDXDNA_QUERY_CLOCK_METADATA:
+ ret = aie4_query_clock_metadata(client, args);
+ break;
case DRM_AMDXDNA_QUERY_FIRMWARE_VERSION:
ret = amdxdna_get_firmware_version(client, args, &xdna->fw_ver);
break;
case DRM_AMDXDNA_GET_POWER_MODE:
ret = aie4_get_power_mode(client, args);
break;
+ case DRM_AMDXDNA_QUERY_RESOURCE_INFO:
+ ret = aie4_query_resource_info(client, args);
+ break;
default:
XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
ret = -EOPNOTSUPP;
}
+ amdxdna_pm_suspend_put(xdna);
XDNA_DBG(xdna, "Got param %d", args->param);
+dev_exit:
+ drm_dev_exit(idx);
return ret;
}
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index fd2c50dc8080..6e9e7f874a44 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -11,6 +11,7 @@
#include <linux/pci.h>
#include "aie.h"
+#include "aie4_msg_priv.h"
#include "amdxdna_mailbox.h"
struct cert_comp {
@@ -40,6 +41,9 @@ struct amdxdna_dev_priv {
struct aie_bar_off_pair psp_regs_off[PSP_MAX_REGS];
struct aie_bar_off_pair smu_regs_off[SMU_MAX_REGS];
+
+ const struct dpm_clk_freq *dpm_clk_tbl;
+ const struct aie_hw_ops *hw_ops;
};
struct amdxdna_dev_hdl {
@@ -50,6 +54,11 @@ struct amdxdna_dev_hdl {
struct mailbox *mbox;
u32 partition_id;
+ u32 total_col;
+ u32 max_aieclk_level;
+ u32 max_npuhclk_level;
+
+ struct dpm_clk_freq dpm_clk_tbl[AIE4_MAX_DPM_LEVEL_COUNT];
struct xarray cert_comp_xa; /* device level indexed by msix id */
struct mutex cert_comp_lock; /* protects cert_comp operations*/
@@ -79,6 +88,9 @@ int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_firmware_version *fw_version);
int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_firmware_version *cert_version);
+int aie4_init_dpm_freq_table(struct amdxdna_dev_hdl *ndev);
+int aie4_query_dpm_level(struct amdxdna_dev_hdl *ndev,
+ u32 *aieclk_dpm_level, u32 *npuhclk_dpm_level);
int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode);
u32 aie4_msg_pasid(struct amdxdna_client *client);
diff --git a/drivers/accel/amdxdna/npu1_regs.c b/drivers/accel/amdxdna/npu1_regs.c
index ca779674017a..b4a0ede636f0 100644
--- a/drivers/accel/amdxdna/npu1_regs.c
+++ b/drivers/accel/amdxdna/npu1_regs.c
@@ -71,24 +71,25 @@ static const struct amdxdna_fw_feature_tbl npu1_fw_feature_table[] = {
{ 0 }
};
-static int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
+static int npu1_set_dpm(struct aie_device *aie, u32 dpm_level)
{
+ struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
u32 npuclk, hclk;
int ret;
npuclk = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
hclk = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
- ret = aie_smu_set_clocks(ndev->aie.smu_hdl, &npuclk, &hclk);
+ ret = aie_smu_set_clocks(aie->smu_hdl, &npuclk, &hclk);
if (ret)
return ret;
- ndev->npuclk_freq = npuclk;
- ndev->hclk_freq = hclk;
- ndev->max_tops = 2 * ndev->total_col;
- ndev->curr_tops = ndev->max_tops * hclk / 1028;
+ aie->npuclk_freq = npuclk;
+ aie->hclk_freq = hclk;
+ aie->max_tops = 2 * ndev->total_col;
+ aie->curr_tops = aie->max_tops * hclk / 1028;
- XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n",
- ndev->npuclk_freq, ndev->hclk_freq);
+ XDNA_DBG(aie->xdna, "MP-NPU clock %d, H clock %d\n",
+ aie->npuclk_freq, aie->hclk_freq);
return 0;
}
@@ -123,7 +124,7 @@ static const struct amdxdna_dev_priv npu1_dev_priv = {
DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU1_SMU, MPNPU_PUB_SCRATCH6),
DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU1_SMU, MPNPU_PUB_SCRATCH7),
},
- .hw_ops = &(const struct aie2_hw_ops) {
+ .hw_ops = &(const struct aie_hw_ops) {
.set_dpm = npu1_set_dpm,
},
};
diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
index c82433d62901..cff99ddd3a55 100644
--- a/drivers/accel/amdxdna/npu3_regs.c
+++ b/drivers/accel/amdxdna/npu3_regs.c
@@ -37,6 +37,8 @@
#define MP1_C2PMSG_61_ALT_1 0x3B109F4
#define MP1_C2PMSG_60_ALT_1 0x3B109F0
+#define NPU3_DPM_TOPS(ndev, hclk) (4096 * (ndev)->total_col * (hclk) / 1000000)
+
static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
{ .major = 6, .min_minor = 0 },
{ 0 }
@@ -47,9 +49,82 @@ static const struct amdxdna_fw_feature_tbl npu3_cert_feature_table[] = {
{ 0 }
};
+static const struct dpm_clk_freq npu3_dpm_clk_table[] = {
+ { 400, 400 },
+ { 960, 576 },
+ { 1108, 576 },
+ { 1200, 847 },
+ { 1200, 1200 },
+ { 1200, 1200 },
+ { 1200, 1200 },
+ { 1200, 1200 },
+ { 0 }
+};
+
+static int npu3_set_dpm(struct aie_device *aie, u32 dpm_level)
+{
+ struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
+ u32 aie_lvl, npu_lvl;
+
+ if (dpm_level > max(ndev->max_aieclk_level, ndev->max_npuhclk_level)) {
+ XDNA_ERR(aie->xdna, "Invalid dpm level %u (max aie %u, npu %u)",
+ dpm_level, ndev->max_aieclk_level, ndev->max_npuhclk_level);
+ return -EINVAL;
+ }
+
+ aie_lvl = min(dpm_level, ndev->max_aieclk_level);
+ npu_lvl = min(dpm_level, ndev->max_npuhclk_level);
+
+ aie->npuclk_freq = ndev->dpm_clk_tbl[aie_lvl].npuclk;
+ aie->hclk_freq = ndev->dpm_clk_tbl[npu_lvl].hclk;
+ aie->max_tops = NPU3_DPM_TOPS(ndev, ndev->dpm_clk_tbl[ndev->max_npuhclk_level].hclk);
+ aie->curr_tops = NPU3_DPM_TOPS(ndev, aie->hclk_freq);
+
+ XDNA_DBG(aie->xdna, "MP-NPU clock %d, H clock %d\n",
+ aie->npuclk_freq, aie->hclk_freq);
+
+ return 0;
+}
+
+static int npu3_update_counters(struct aie_device *aie)
+{
+ struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
+ u32 aieclk_level, npuhclk_level;
+ int ret;
+
+ /* Use firmware DPM table or pre-defined table, never mixed. */
+ ret = aie4_query_dpm_level(ndev, &aieclk_level, &npuhclk_level);
+ if (ret) {
+ XDNA_WARN(aie->xdna, "Failed to get DPM level from fw: %d", ret);
+ return ret;
+ }
+
+ if (aieclk_level > ndev->max_aieclk_level ||
+ npuhclk_level > ndev->max_npuhclk_level) {
+ XDNA_ERR(aie->xdna, "DPM level exceeds max: aie %u/%u, npu %u/%u",
+ aieclk_level, ndev->max_aieclk_level,
+ npuhclk_level, ndev->max_npuhclk_level);
+ return -EINVAL;
+ }
+
+ aie->npuclk_freq = ndev->dpm_clk_tbl[aieclk_level].npuclk;
+ aie->hclk_freq = ndev->dpm_clk_tbl[npuhclk_level].hclk;
+ aie->max_tops = NPU3_DPM_TOPS(ndev,
+ ndev->dpm_clk_tbl[ndev->max_npuhclk_level].hclk);
+ aie->curr_tops = NPU3_DPM_TOPS(ndev, aie->hclk_freq);
+
+ return 0;
+}
+
+static const struct aie_hw_ops npu3_hw_ops = {
+ .set_dpm = npu3_set_dpm,
+ .update_counters = npu3_update_counters,
+};
+
static const struct amdxdna_dev_priv npu3_dev_priv = {
.npufw_path = "npu.sbin",
.certfw_path = "cert.sbin",
+ .dpm_clk_tbl = npu3_dpm_clk_table,
.mbox_bar = NPU3_MBOX_BAR,
.mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR,
.mbox_info_off = NPU3_MBOX_INFO_OFF,
@@ -71,14 +146,17 @@ static const struct amdxdna_dev_priv npu3_dev_priv = {
DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU3_SMU, MP1_C2PMSG_60_ALT_1),
DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU3_SMU, MP1_C2PMSG_61_ALT_1),
},
+ .hw_ops = &npu3_hw_ops,
};
static const struct amdxdna_dev_priv npu3_dev_vf_priv = {
/* vf device does not load firmware */
+ .dpm_clk_tbl = npu3_dpm_clk_table,
.mbox_bar = NPU3_MBOX_BAR,
.mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR,
.mbox_info_off = NPU3_MBOX_INFO_OFF,
/* vf device does not have smu and psp */
+ .hw_ops = &npu3_hw_ops,
};
const struct amdxdna_dev_info dev_npu3_pf_info = {
diff --git a/drivers/accel/amdxdna/npu4_regs.c b/drivers/accel/amdxdna/npu4_regs.c
index c9648c8032ec..624c1babdff8 100644
--- a/drivers/accel/amdxdna/npu4_regs.c
+++ b/drivers/accel/amdxdna/npu4_regs.c
@@ -104,42 +104,44 @@ const struct amdxdna_fw_feature_tbl npu4_fw_feature_table[] = {
{ 0 }
};
-static int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
+static int npu4_set_dpm(struct aie_device *aie, u32 dpm_level)
{
+ struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
int ret;
- ret = aie_smu_set_dpm(ndev->aie.smu_hdl, dpm_level);
+ ret = aie_smu_set_dpm(aie->smu_hdl, dpm_level);
if (ret)
return ret;
- ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
- ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
- ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk);
- ndev->curr_tops = NPU4_DPM_TOPS(ndev, ndev->hclk_freq);
+ aie->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
+ aie->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
+ aie->max_tops = NPU4_DPM_TOPS(ndev, ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk);
+ aie->curr_tops = NPU4_DPM_TOPS(ndev, aie->hclk_freq);
- XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n",
- ndev->npuclk_freq, ndev->hclk_freq);
+ XDNA_DBG(aie->xdna, "MP-NPU clock %d, H clock %d\n",
+ aie->npuclk_freq, aie->hclk_freq);
return 0;
}
-static int npu4_update_counters(struct amdxdna_dev_hdl *ndev)
+static int npu4_update_counters(struct aie_device *aie)
{
+ struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
struct amd_pmf_npu_metrics npu_metrics;
int ret;
- ret = AIE2_GET_PMF_NPU_METRICS(&npu_metrics);
+ ret = AIE_GET_PMF_NPU_METRICS(&npu_metrics);
if (ret)
return ret;
- ndev->npuclk_freq = npu_metrics.mpnpuclk_freq;
- ndev->hclk_freq = npu_metrics.npuclk_freq;
- ndev->curr_tops = NPU4_DPM_TOPS(ndev, ndev->hclk_freq);
+ aie->npuclk_freq = npu_metrics.mpnpuclk_freq;
+ aie->hclk_freq = npu_metrics.npuclk_freq;
+ aie->curr_tops = NPU4_DPM_TOPS(ndev, aie->hclk_freq);
return 0;
}
-const struct aie2_hw_ops npu4_hw_ops = {
+const struct aie_hw_ops npu4_hw_ops = {
.set_dpm = npu4_set_dpm,
.update_counters = npu4_update_counters,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 08/19] accel/amdxdna: Add clock, DPM frequency, and resource info queries for AIE4
2026-10-09 22:53 ` [PATCH V4 08/19] accel/amdxdna: Add clock, DPM frequency, and resource info queries " David Zhang
@ 2026-10-09 23:12 ` sashiko-bot
2026-10-12 22:58 ` Lizhi Hou
1 sibling, 0 replies; 39+ messages in thread
From: sashiko-bot @ 2026-10-09 23:12 UTC (permalink / raw)
To: David Zhang; +Cc: dri-devel
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] amdxdna: user-triggerable log spam in aie_update_counters ioctl path
- [Medium] amdxdna: uninitialized max_tops returned to userspace on telemetry failure
--
commit 9f91f5ba98bc4ba5e1f461f3136872d989e22936
Author: David Zhang <yidong.zhang@amd.com>
accel/amdxdna: Add clock, DPM frequency, and resource info queries for AIE4
This commit adds support for querying clock metadata, DPM frequency tables,
and hardware resource information for AIE4/NPU3 devices. It moves the DPM
frequency table to the device structure and queries active DPM levels via
messages to the firmware.
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index 6eacdc026ec7f..5593dfb6c7ed5 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -299,6 +299,17 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev)
> if (ret)
> return ret;
>
> + ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols);
> +
> + ret = aie4_init_dpm_freq_table(ndev);
> + if (ret) {
> + if (ret == -ETIME)
> + return ret;
> + /* if query dpm from fw failed, using default value */
> + if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm)
> + (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0);
> + }
[Severity: Medium]
When aie4_init_dpm_freq_table() successfully queries the DPM table from
firmware, the fallback call to set_dpm() is skipped. Doesn't this leave
aie->max_tops and aie->curr_tops uninitialized (0) at startup?
[ ... ]
> @@ -635,11 +646,71 @@ static int aie4_get_power_mode(struct amdxdna_client *client,
> return 0;
> }
>
> +static int aie4_query_clock_metadata(struct amdxdna_client *client,
> + struct amdxdna_drm_get_info *args)
> +{
> + struct amdxdna_drm_query_clock_metadata *clock;
> + struct amdxdna_dev *xdna = client->xdna;
> + struct amdxdna_dev_hdl *ndev;
> + int ret = 0;
> + u32 buf_sz;
> +
> + ndev = xdna->dev_handle;
> + clock = kzalloc_obj(*clock);
> + if (!clock)
> + return -ENOMEM;
> +
> + aie_update_counters(ndev);
[Severity: Medium]
Because this ioctl can be polled rapidly by unprivileged userspace monitoring
tools, does calling aie_update_counters() without checking its return value
provide a vector for local denial of service via kernel log spam if the
telemetry query in npu3_update_counters() fails?
[ ... ]
> +static int aie4_query_resource_info(struct amdxdna_client *client,
> + struct amdxdna_drm_get_info *args)
> +{
> + struct amdxdna_drm_get_resource_info res_info = {};
> + struct amdxdna_dev_hdl *ndev;
> + struct amdxdna_dev *xdna;
> + u32 buf_sz;
> +
> + xdna = client->xdna;
> + ndev = xdna->dev_handle;
> +
> + aie_update_counters(ndev);
> + res_info.npu_clk_max = ndev->dpm_clk_tbl[ndev->max_npuhclk_level].hclk;
> + res_info.npu_tops_max = ndev->aie.max_tops;
> + res_info.npu_tops_curr = ndev->aie.curr_tops;
[Severity: Medium]
Here we ignore the return value of aie_update_counters() as well. If the
underlying telemetry query fails and returns early without populating
aie->max_tops, will this copy the uninitialized 0 values to userspace?
Userspace might receive 0 for static hardware limits and clock frequencies,
causing incorrect statistics in clients that rely on accurate resource bounds.
> diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
> index c82433d629012..cff99ddd3a552 100644
> --- a/drivers/accel/amdxdna/npu3_regs.c
> +++ b/drivers/accel/amdxdna/npu3_regs.c
[ ... ]
> +static int npu3_update_counters(struct aie_device *aie)
> +{
> + struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
> + u32 aieclk_level, npuhclk_level;
> + int ret;
> +
> + /* Use firmware DPM table or pre-defined table, never mixed. */
> + ret = aie4_query_dpm_level(ndev, &aieclk_level, &npuhclk_level);
> + if (ret) {
> + XDNA_WARN(aie->xdna, "Failed to get DPM level from fw: %d", ret);
> + return ret;
> + }
[Severity: Medium]
This is where the un-ratelimited warning is printed upon a telemetry failure in
the ioctl path. If the firmware is older and lacks support for
AIE4_MSG_OP_GET_CURRENT_DPM_LEVEL, or the management channel times out, could
this result in unbounded kernel log spam?
If this telemetry query fails, max_tops is never computed. Combined with the
uninitialized state from aie4_query() during probe, does this ensure 0 is
propagated to the caller?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009225343.3079074-1-yidong.zhang@amd.com?part=8
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V4 08/19] accel/amdxdna: Add clock, DPM frequency, and resource info queries for AIE4
2026-10-09 22:53 ` [PATCH V4 08/19] accel/amdxdna: Add clock, DPM frequency, and resource info queries " David Zhang
2026-10-09 23:12 ` sashiko-bot
@ 2026-10-12 22:58 ` Lizhi Hou
1 sibling, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-12 22:58 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello, Soham Donwalkar
On 10/9/26 15:53, David Zhang wrote:
> Add support for querying clock metadata, DPM frequency table, and
> hardware resource information for AIE4/NPU3 devices:
> - Move struct dpm_clk_freq and common clock/TOPS counters into struct
> aie_device.
> - Add NPU3 DPM clock table, DPM control, and counter updates by querying
> active DPM levels via AIE4_MSG_OP_GET_CURRENT_DPM_LEVEL.
> - Query AIE4 DPM frequency table from firmware via
> AIE4_MSG_OP_GET_DPM_FREQ_TABLE.
>
> Co-developed-by: Soham Donwalkar <soham.donwalkar@amd.com>
> Signed-off-by: Soham Donwalkar <soham.donwalkar@amd.com>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> ---
> drivers/accel/amdxdna/aie.h | 36 +++++++++++
> drivers/accel/amdxdna/aie2_pci.c | 14 ++---
> drivers/accel/amdxdna/aie2_pci.h | 35 +----------
> drivers/accel/amdxdna/aie2_pm.c | 10 +--
> drivers/accel/amdxdna/aie4_message.c | 88 +++++++++++++++++++++++++++
> drivers/accel/amdxdna/aie4_msg_priv.h | 31 ++++++++++
> drivers/accel/amdxdna/aie4_pci.c | 82 ++++++++++++++++++++++++-
> drivers/accel/amdxdna/aie4_pci.h | 12 ++++
> drivers/accel/amdxdna/npu1_regs.c | 19 +++---
> drivers/accel/amdxdna/npu3_regs.c | 78 ++++++++++++++++++++++++
> drivers/accel/amdxdna/npu4_regs.c | 30 ++++-----
> 11 files changed, 367 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie.h b/drivers/accel/amdxdna/aie.h
> index 229b3cfa2361..a7276c25844f 100644
> --- a/drivers/accel/amdxdna/aie.h
> +++ b/drivers/accel/amdxdna/aie.h
> @@ -30,8 +30,44 @@ struct aie_device {
>
> struct amdxdna_drm_query_aie_version version;
> struct amdxdna_drm_query_aie_metadata metadata;
> +
> + u32 clk_gating;
> + u32 npuclk_freq;
> + u32 hclk_freq;
> + u32 max_tops;
> + u32 curr_tops;
> +};
> +
> +struct aie_hw_ops {
> + int (*set_dpm)(struct aie_device *aie, u32 dpm_level);
> + int (*update_counters)(struct aie_device *aie);
> };
>
> +#define aie_update_counters(ndev) \
> +({ \
> + typeof(ndev) _ndev = ndev; \
> + if ((_ndev)->priv->hw_ops && (_ndev)->priv->hw_ops->update_counters) \
> + (_ndev)->priv->hw_ops->update_counters(&(_ndev)->aie); \
> +})
> +
> +struct dpm_clk_freq {
> + u32 npuclk;
> + u32 hclk;
> +};
> +
> +#include <linux/amd-pmf-io.h>
> +
> +#if IS_ENABLED(CONFIG_AMD_PMF)
> +#define AIE_GET_PMF_NPU_METRICS(metrics) amd_pmf_get_npu_data(metrics)
> +#else
> +#define AIE_GET_PMF_NPU_METRICS(metrics) \
> +({ \
> + typeof(metrics) _m = metrics; \
> + memset(_m, 0xff, sizeof(*_m)); \
> + (-EOPNOTSUPP); \
> +})
> +#endif
> +
> #define DECLARE_AIE_MSG(name, op) \
> DECLARE_XDNA_MSG_COMMON(name, op, -1)
> #define AIE_FEATURE_ON(aie, feature) test_bit(feature, &(aie)->feature_mask)
> diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c
> index 6fa79698f9d8..1b029d33a24b 100644
> --- a/drivers/accel/amdxdna/aie2_pci.c
> +++ b/drivers/accel/amdxdna/aie2_pci.c
> @@ -296,7 +296,7 @@ static struct xrs_action_ops aie2_xrs_actions = {
>
> static void aie2_smu_fini(struct amdxdna_dev_hdl *ndev)
> {
> - ndev->priv->hw_ops->set_dpm(ndev, 0);
> + ndev->priv->hw_ops->set_dpm(&ndev->aie, 0);
> aie_smu_fini(ndev->aie.smu_hdl);
> }
>
> @@ -718,12 +718,12 @@ static int aie2_get_clock_metadata(struct amdxdna_client *client,
> if (!clock)
> return -ENOMEM;
>
> - aie2_update_counters(ndev);
> + aie_update_counters(ndev);
> snprintf(clock->mp_npu_clock.name, sizeof(clock->mp_npu_clock.name),
> "MP-NPU Clock");
> - clock->mp_npu_clock.freq_mhz = ndev->npuclk_freq;
> + clock->mp_npu_clock.freq_mhz = ndev->aie.npuclk_freq;
> snprintf(clock->h_clock.name, sizeof(clock->h_clock.name), "H Clock");
> - clock->h_clock.freq_mhz = ndev->hclk_freq;
> + clock->h_clock.freq_mhz = ndev->aie.hclk_freq;
>
> buf_sz = min(args->buffer_size, sizeof(*clock));
> if (copy_to_user(u64_to_user_ptr(args->buffer), clock, buf_sz))
> @@ -879,11 +879,11 @@ static int aie2_query_resource_info(struct amdxdna_client *client,
> ndev = xdna->dev_handle;
> priv = ndev->priv;
>
> - aie2_update_counters(ndev);
> + aie_update_counters(ndev);
> res_info.npu_clk_max = priv->dpm_clk_tbl[ndev->max_dpm_level].hclk;
> - res_info.npu_tops_max = ndev->max_tops;
> + res_info.npu_tops_max = ndev->aie.max_tops;
> res_info.npu_task_max = priv->hwctx_limit;
> - res_info.npu_tops_curr = ndev->curr_tops;
> + res_info.npu_tops_curr = ndev->aie.curr_tops;
> res_info.npu_task_curr = ndev->hwctx_num;
>
> buf_sz = min(args->buffer_size, sizeof(res_info));
> diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h
> index b31f73082c17..709e7545c65f 100644
> --- a/drivers/accel/amdxdna/aie2_pci.h
> +++ b/drivers/accel/amdxdna/aie2_pci.h
> @@ -40,8 +40,8 @@
> pci_resource_len(NDEV2PDEV(_ndev), (_ndev)->aie.xdna->dev_info->mbox_bar); \
> })
>
> +#define AIE2_GET_PMF_NPU_METRICS(metrics) AIE_GET_PMF_NPU_METRICS(metrics)
> #if IS_ENABLED(CONFIG_AMD_PMF)
> -#define AIE2_GET_PMF_NPU_METRICS(metrics) amd_pmf_get_npu_data(metrics)
> #define AIE2_GET_PMF_NPU_DATA(field, val) \
> ({ \
> struct amd_pmf_npu_metrics _npu_metrics; \
> @@ -52,13 +52,6 @@
> (_ret); \
> })
> #else
> -#define AIE2_GET_PMF_NPU_METRICS(metrics) \
> -({ \
> - typeof(metrics) _m = metrics; \
> - memset(_m, 0xff, sizeof(*_m)); \
> - (-EOPNOTSUPP); \
> -})
> -
> #define SENSOR_DEFAULT_npu_power U32_MAX
> #define AIE2_GET_PMF_NPU_DATA(field, val) \
> ({ \
> @@ -91,11 +84,6 @@ struct rt_config {
> unsigned long feature_mask;
> };
>
> -struct dpm_clk_freq {
> - u32 npuclk;
> - u32 hclk;
> -};
> -
> /*
> * Define the maximum number of pending commands in a hardware context.
> * Must be power of 2!
> @@ -158,11 +146,6 @@ struct amdxdna_dev_hdl {
> u32 dpm_level;
> u32 dft_dpm_level;
> u32 max_dpm_level;
> - u32 clk_gating;
> - u32 npuclk_freq;
> - u32 hclk_freq;
> - u32 max_tops;
> - u32 curr_tops;
> u32 force_preempt_enabled;
> u32 frame_boundary_preempt;
>
> @@ -177,18 +160,6 @@ struct amdxdna_dev_hdl {
> unsigned long last_signal_ts;
> };
>
> -struct aie2_hw_ops {
> - int (*set_dpm)(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
> - int (*update_counters)(struct amdxdna_dev_hdl *ndev);
> -};
> -
> -#define aie2_update_counters(ndev) \
> -({ \
> - typeof(ndev) _ndev = ndev; \
> - if (_ndev->priv->hw_ops->update_counters) \
> - _ndev->priv->hw_ops->update_counters(_ndev); \
> -})
> -
> enum aie2_fw_feature {
> AIE2_NPU_COMMAND,
> AIE2_PREEMPT,
> @@ -219,7 +190,7 @@ struct amdxdna_dev_priv {
> struct aie_bar_off_pair sram_offs[SRAM_MAX_INDEX];
> struct aie_bar_off_pair psp_regs_off[PSP_MAX_REGS];
> struct aie_bar_off_pair smu_regs_off[SMU_MAX_REGS];
> - const struct aie2_hw_ops *hw_ops;
> + const struct aie_hw_ops *hw_ops;
> };
>
> extern const struct amdxdna_dev_ops aie2_ops;
> @@ -234,7 +205,7 @@ extern const struct rt_config npu1_default_rt_cfg[];
> extern const struct rt_config npu4_default_rt_cfg[];
> extern const struct amdxdna_fw_feature_tbl npu4_fw_feature_table[];
> extern const struct amdxdna_rev_vbnv npu4_rev_vbnv_tbl[];
> -extern const struct aie2_hw_ops npu4_hw_ops;
> +extern const struct aie_hw_ops npu4_hw_ops;
>
> /* aie2_pm.c */
> int aie2_pm_init(struct amdxdna_dev_hdl *ndev);
> diff --git a/drivers/accel/amdxdna/aie2_pm.c b/drivers/accel/amdxdna/aie2_pm.c
> index 4fe6030d2c41..f4ced7b67c25 100644
> --- a/drivers/accel/amdxdna/aie2_pm.c
> +++ b/drivers/accel/amdxdna/aie2_pm.c
> @@ -23,7 +23,7 @@ static int aie2_pm_set_clk_gating(struct amdxdna_dev_hdl *ndev, u32 val)
> if (ret)
> return ret;
>
> - ndev->clk_gating = val;
> + ndev->aie.clk_gating = val;
> return 0;
> }
>
> @@ -35,7 +35,7 @@ int aie2_pm_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
> if (ret)
> return ret;
>
> - ret = ndev->priv->hw_ops->set_dpm(ndev, dpm_level);
> + ret = ndev->priv->hw_ops->set_dpm(&ndev->aie, dpm_level);
> if (!ret)
> ndev->dpm_level = dpm_level;
> amdxdna_pm_suspend_put(ndev->aie.xdna);
> @@ -49,11 +49,11 @@ int aie2_pm_init(struct amdxdna_dev_hdl *ndev)
>
> if (ndev->dev_status != AIE2_DEV_UNINIT) {
> /* Resume device */
> - ret = ndev->priv->hw_ops->set_dpm(ndev, ndev->dpm_level);
> + ret = ndev->priv->hw_ops->set_dpm(&ndev->aie, ndev->dpm_level);
> if (ret)
> return ret;
>
> - ret = aie2_pm_set_clk_gating(ndev, ndev->clk_gating);
> + ret = aie2_pm_set_clk_gating(ndev, ndev->aie.clk_gating);
> if (ret)
> return ret;
>
> @@ -64,7 +64,7 @@ int aie2_pm_init(struct amdxdna_dev_hdl *ndev)
> ndev->max_dpm_level++;
> ndev->max_dpm_level--;
>
> - ret = ndev->priv->hw_ops->set_dpm(ndev, ndev->max_dpm_level);
> + ret = ndev->priv->hw_ops->set_dpm(&ndev->aie, ndev->max_dpm_level);
> if (ret)
> return ret;
> ndev->dpm_level = ndev->max_dpm_level;
> diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
> index 8d1cad50cbab..263e23aff69f 100644
> --- a/drivers/accel/amdxdna/aie4_message.c
> +++ b/drivers/accel/amdxdna/aie4_message.c
> @@ -141,6 +141,94 @@ int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
> return 0;
> }
>
> +int aie4_init_dpm_freq_table(struct amdxdna_dev_hdl *ndev)
> +{
> + DECLARE_AIE_MSG(aie4_msg_get_dpm_freq_table, AIE4_MSG_OP_GET_DPM_FREQ_TABLE);
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> + u32 aie_levels, npu_levels, i;
> + int ret;
> +
> + for (i = 0; i < AIE4_MAX_DPM_LEVEL_COUNT && ndev->priv->dpm_clk_tbl &&
> + ndev->priv->dpm_clk_tbl[i].hclk; i++)
> + ndev->dpm_clk_tbl[i] = ndev->priv->dpm_clk_tbl[i];
> + ndev->max_aieclk_level = i ? i - 1 : 0;
> + ndev->max_npuhclk_level = i ? i - 1 : 0;
> +
> + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> + if (ret) {
> + XDNA_WARN(xdna, "Get DPM freq table failed, ret %d status 0x%x",
> + ret, resp.status);
> + return ret;
> + }
> +
> + aie_levels = resp.aieclk_table.num_levels;
> + npu_levels = resp.npuhclk_table.num_levels;
> +
> + if (!aie_levels || !npu_levels ||
> + aie_levels > AIE4_MAX_DPM_LEVEL_COUNT ||
> + npu_levels > AIE4_MAX_DPM_LEVEL_COUNT) {
> + XDNA_ERR(xdna, "invalid dpm levels, aieclk: %u, npuhclk: %u",
> + aie_levels, npu_levels);
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < aie_levels; i++) {
> + if (!resp.aieclk_table.values[i]) {
> + XDNA_ERR(xdna, "invalid dpm aieclk frequency 0 at level %u", i);
> + return -EINVAL;
> + }
> + }
> +
> + for (i = 0; i < npu_levels; i++) {
> + if (!resp.npuhclk_table.values[i]) {
> + XDNA_ERR(xdna, "invalid dpm npuhclk frequency 0 at level %u", i);
> + return -EINVAL;
> + }
> + }
> +
> + memset(ndev->dpm_clk_tbl, 0, sizeof(ndev->dpm_clk_tbl));
> + for (i = 0; i < aie_levels; i++)
> + ndev->dpm_clk_tbl[i].npuclk = resp.aieclk_table.values[i];
> +
> + for (i = 0; i < npu_levels; i++)
> + ndev->dpm_clk_tbl[i].hclk = resp.npuhclk_table.values[i];
> +
> + ndev->max_aieclk_level = aie_levels - 1;
> + ndev->max_npuhclk_level = npu_levels - 1;
> +
> + return 0;
> +}
> +
> +int aie4_query_dpm_level(struct amdxdna_dev_hdl *ndev,
> + u32 *aieclk_dpm_level, u32 *npuhclk_dpm_level)
> +{
> + DECLARE_AIE_MSG(aie4_msg_get_dpm_level, AIE4_MSG_OP_GET_CURRENT_DPM_LEVEL);
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> + int ret;
> +
> + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> + if (ret)
> + return ret;
> +
> + /*
> + * Validate against ndev->max_aieclk_level and ndev->max_npuhclk_level
> + * to ensure reported levels index into populated entries in dpm_clk_tbl.
> + */
> + if (resp.aieclk_dpm_level > ndev->max_aieclk_level ||
> + resp.npuhclk_dpm_level > ndev->max_npuhclk_level) {
> + XDNA_ERR(xdna,
> + "invalid dpm level, aie: %u/%u, npu: %u/%u",
> + resp.aieclk_dpm_level, ndev->max_aieclk_level,
> + resp.npuhclk_dpm_level, ndev->max_npuhclk_level);
> + return -EINVAL;
> + }
> +
> + *aieclk_dpm_level = resp.aieclk_dpm_level;
> + *npuhclk_dpm_level = resp.npuhclk_dpm_level;
> +
> + return 0;
> +}
> +
> int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev)
> {
> DECLARE_AIE_MSG(aie4_msg_attach_work_buffer, AIE4_MSG_OP_ATTACH_WORK_BUFFER);
> diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
> index 4c06792df1bd..fe78df9e23c8 100644
> --- a/drivers/accel/amdxdna/aie4_msg_priv.h
> +++ b/drivers/accel/amdxdna/aie4_msg_priv.h
> @@ -24,6 +24,8 @@ enum aie4_msg_opcode {
> AIE4_MSG_OP_AIE_TILE_INFO = 0x30006,
> AIE4_MSG_OP_AIE_VERSION_INFO = 0x30007,
> AIE4_MSG_OP_POWER_OVERRIDE = 0x3000B,
> + AIE4_MSG_OP_GET_DPM_FREQ_TABLE = 0x30012,
> + AIE4_MSG_OP_GET_CURRENT_DPM_LEVEL = 0x30013,
>
> AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
> };
> @@ -196,6 +198,35 @@ struct aie4_msg_power_override_resp {
> enum aie4_msg_status status;
> } __packed;
>
> +#define AIE4_MAX_DPM_LEVEL_COUNT 10
> +
> +struct aie4_dpm_table {
> + __u32 num_levels;
> + __u32 values[AIE4_MAX_DPM_LEVEL_COUNT];
> +} __packed;
> +
> +/* AIE4_MSG_OP_GET_DPM_FREQ_TABLE */
> +struct aie4_msg_get_dpm_freq_table_req {
> + __u32 rsvd;
> +} __packed;
> +
> +struct aie4_msg_get_dpm_freq_table_resp {
> + enum aie4_msg_status status;
> + struct aie4_dpm_table aieclk_table;
> + struct aie4_dpm_table npuhclk_table;
> +} __packed;
> +
> +/* AIE4_MSG_OP_GET_CURRENT_DPM_LEVEL */
> +struct aie4_msg_get_dpm_level_req {
> + __u32 rsvd;
> +} __packed;
> +
> +struct aie4_msg_get_dpm_level_resp {
> + enum aie4_msg_status status;
> + __u32 aieclk_dpm_level;
> + __u32 npuhclk_dpm_level;
> +} __packed;
> +
> #define AIE4_WORK_BUFFER_MIN_SIZE SZ_4M
>
> struct aie4_msg_attach_work_buffer_req {
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index 6eacdc026ec7..5593dfb6c7ed 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -299,6 +299,17 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev)
> if (ret)
> return ret;
>
> + ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols);
> +
> + ret = aie4_init_dpm_freq_table(ndev);
> + if (ret) {
> + if (ret == -ETIME)
> + return ret;
> + /* if query dpm from fw failed, using default value */
> + if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm)
> + (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0);
> + }
> +
> return 0;
> }
>
> @@ -635,11 +646,71 @@ static int aie4_get_power_mode(struct amdxdna_client *client,
> return 0;
> }
>
> +static int aie4_query_clock_metadata(struct amdxdna_client *client,
> + struct amdxdna_drm_get_info *args)
> +{
> + struct amdxdna_drm_query_clock_metadata *clock;
> + struct amdxdna_dev *xdna = client->xdna;
> + struct amdxdna_dev_hdl *ndev;
> + int ret = 0;
> + u32 buf_sz;
> +
> + ndev = xdna->dev_handle;
> + clock = kzalloc_obj(*clock);
> + if (!clock)
> + return -ENOMEM;
> +
> + aie_update_counters(ndev);
> + snprintf(clock->mp_npu_clock.name, sizeof(clock->mp_npu_clock.name),
> + "MP-NPU Clock");
> + clock->mp_npu_clock.freq_mhz = ndev->aie.npuclk_freq;
> + snprintf(clock->h_clock.name, sizeof(clock->h_clock.name), "H Clock");
> + clock->h_clock.freq_mhz = ndev->aie.hclk_freq;
> +
> + buf_sz = min_t(u32, args->buffer_size, sizeof(*clock));
> + if (copy_to_user(u64_to_user_ptr(args->buffer), clock, buf_sz))
> + ret = -EFAULT;
> +
> + kfree(clock);
> + return ret;
> +}
> +
> +static int aie4_query_resource_info(struct amdxdna_client *client,
> + struct amdxdna_drm_get_info *args)
> +{
> + struct amdxdna_drm_get_resource_info res_info = {};
> + struct amdxdna_dev_hdl *ndev;
> + struct amdxdna_dev *xdna;
> + u32 buf_sz;
> +
> + xdna = client->xdna;
> + ndev = xdna->dev_handle;
> +
> + aie_update_counters(ndev);
> + res_info.npu_clk_max = ndev->dpm_clk_tbl[ndev->max_npuhclk_level].hclk;
> + res_info.npu_tops_max = ndev->aie.max_tops;
> + res_info.npu_tops_curr = ndev->aie.curr_tops;
> + /* Context accounting is populated in later patches in the series. */
> +
> + buf_sz = min_t(u32, args->buffer_size, sizeof(res_info));
> + if (copy_to_user(u64_to_user_ptr(args->buffer), &res_info, buf_sz))
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args)
> {
> struct amdxdna_dev *xdna = client->xdna;
> struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
> - int ret;
> + int ret, idx;
> +
> + if (!drm_dev_enter(&xdna->ddev, &idx))
> + return -ENODEV;
> +
> + ret = amdxdna_pm_resume_get_locked(xdna);
> + if (ret)
> + goto dev_exit;
>
> switch (args->param) {
> case DRM_AMDXDNA_QUERY_AIE_METADATA:
> @@ -648,19 +719,28 @@ static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
> case DRM_AMDXDNA_QUERY_AIE_VERSION:
> ret = amdxdna_get_aie_version(client, args, &ndev->aie.version);
> break;
> + case DRM_AMDXDNA_QUERY_CLOCK_METADATA:
> + ret = aie4_query_clock_metadata(client, args);
> + break;
> case DRM_AMDXDNA_QUERY_FIRMWARE_VERSION:
> ret = amdxdna_get_firmware_version(client, args, &xdna->fw_ver);
> break;
> case DRM_AMDXDNA_GET_POWER_MODE:
> ret = aie4_get_power_mode(client, args);
> break;
> + case DRM_AMDXDNA_QUERY_RESOURCE_INFO:
> + ret = aie4_query_resource_info(client, args);
> + break;
> default:
> XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
> ret = -EOPNOTSUPP;
> }
>
> + amdxdna_pm_suspend_put(xdna);
> XDNA_DBG(xdna, "Got param %d", args->param);
>
> +dev_exit:
> + drm_dev_exit(idx);
> return ret;
> }
>
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index fd2c50dc8080..6e9e7f874a44 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -11,6 +11,7 @@
> #include <linux/pci.h>
>
> #include "aie.h"
> +#include "aie4_msg_priv.h"
> #include "amdxdna_mailbox.h"
>
> struct cert_comp {
> @@ -40,6 +41,9 @@ struct amdxdna_dev_priv {
>
> struct aie_bar_off_pair psp_regs_off[PSP_MAX_REGS];
> struct aie_bar_off_pair smu_regs_off[SMU_MAX_REGS];
> +
> + const struct dpm_clk_freq *dpm_clk_tbl;
> + const struct aie_hw_ops *hw_ops;
> };
>
> struct amdxdna_dev_hdl {
> @@ -50,6 +54,11 @@ struct amdxdna_dev_hdl {
>
> struct mailbox *mbox;
> u32 partition_id;
> + u32 total_col;
> + u32 max_aieclk_level;
> + u32 max_npuhclk_level;
> +
> + struct dpm_clk_freq dpm_clk_tbl[AIE4_MAX_DPM_LEVEL_COUNT];
>
> struct xarray cert_comp_xa; /* device level indexed by msix id */
> struct mutex cert_comp_lock; /* protects cert_comp operations*/
> @@ -79,6 +88,9 @@ int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_firmware_version *fw_version);
> int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_firmware_version *cert_version);
> +int aie4_init_dpm_freq_table(struct amdxdna_dev_hdl *ndev);
> +int aie4_query_dpm_level(struct amdxdna_dev_hdl *ndev,
> + u32 *aieclk_dpm_level, u32 *npuhclk_dpm_level);
> int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode);
> u32 aie4_msg_pasid(struct amdxdna_client *client);
>
> diff --git a/drivers/accel/amdxdna/npu1_regs.c b/drivers/accel/amdxdna/npu1_regs.c
> index ca779674017a..b4a0ede636f0 100644
> --- a/drivers/accel/amdxdna/npu1_regs.c
> +++ b/drivers/accel/amdxdna/npu1_regs.c
> @@ -71,24 +71,25 @@ static const struct amdxdna_fw_feature_tbl npu1_fw_feature_table[] = {
> { 0 }
> };
>
> -static int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
> +static int npu1_set_dpm(struct aie_device *aie, u32 dpm_level)
> {
> + struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
> u32 npuclk, hclk;
> int ret;
>
> npuclk = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
> hclk = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
> - ret = aie_smu_set_clocks(ndev->aie.smu_hdl, &npuclk, &hclk);
> + ret = aie_smu_set_clocks(aie->smu_hdl, &npuclk, &hclk);
> if (ret)
> return ret;
>
> - ndev->npuclk_freq = npuclk;
> - ndev->hclk_freq = hclk;
> - ndev->max_tops = 2 * ndev->total_col;
> - ndev->curr_tops = ndev->max_tops * hclk / 1028;
> + aie->npuclk_freq = npuclk;
> + aie->hclk_freq = hclk;
> + aie->max_tops = 2 * ndev->total_col;
> + aie->curr_tops = aie->max_tops * hclk / 1028;
>
> - XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n",
> - ndev->npuclk_freq, ndev->hclk_freq);
> + XDNA_DBG(aie->xdna, "MP-NPU clock %d, H clock %d\n",
> + aie->npuclk_freq, aie->hclk_freq);
> return 0;
> }
>
> @@ -123,7 +124,7 @@ static const struct amdxdna_dev_priv npu1_dev_priv = {
> DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU1_SMU, MPNPU_PUB_SCRATCH6),
> DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU1_SMU, MPNPU_PUB_SCRATCH7),
> },
> - .hw_ops = &(const struct aie2_hw_ops) {
> + .hw_ops = &(const struct aie_hw_ops) {
> .set_dpm = npu1_set_dpm,
> },
> };
> diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
> index c82433d62901..cff99ddd3a55 100644
> --- a/drivers/accel/amdxdna/npu3_regs.c
> +++ b/drivers/accel/amdxdna/npu3_regs.c
> @@ -37,6 +37,8 @@
> #define MP1_C2PMSG_61_ALT_1 0x3B109F4
> #define MP1_C2PMSG_60_ALT_1 0x3B109F0
>
> +#define NPU3_DPM_TOPS(ndev, hclk) (4096 * (ndev)->total_col * (hclk) / 1000000)
> +
> static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
> { .major = 6, .min_minor = 0 },
> { 0 }
> @@ -47,9 +49,82 @@ static const struct amdxdna_fw_feature_tbl npu3_cert_feature_table[] = {
> { 0 }
> };
>
> +static const struct dpm_clk_freq npu3_dpm_clk_table[] = {
> + { 400, 400 },
> + { 960, 576 },
> + { 1108, 576 },
> + { 1200, 847 },
> + { 1200, 1200 },
> + { 1200, 1200 },
> + { 1200, 1200 },
> + { 1200, 1200 },
> + { 0 }
> +};
> +
> +static int npu3_set_dpm(struct aie_device *aie, u32 dpm_level)
> +{
> + struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
> + u32 aie_lvl, npu_lvl;
> +
> + if (dpm_level > max(ndev->max_aieclk_level, ndev->max_npuhclk_level)) {
> + XDNA_ERR(aie->xdna, "Invalid dpm level %u (max aie %u, npu %u)",
> + dpm_level, ndev->max_aieclk_level, ndev->max_npuhclk_level);
> + return -EINVAL;
> + }
> +
> + aie_lvl = min(dpm_level, ndev->max_aieclk_level);
> + npu_lvl = min(dpm_level, ndev->max_npuhclk_level);
> +
> + aie->npuclk_freq = ndev->dpm_clk_tbl[aie_lvl].npuclk;
> + aie->hclk_freq = ndev->dpm_clk_tbl[npu_lvl].hclk;
> + aie->max_tops = NPU3_DPM_TOPS(ndev, ndev->dpm_clk_tbl[ndev->max_npuhclk_level].hclk);
> + aie->curr_tops = NPU3_DPM_TOPS(ndev, aie->hclk_freq);
> +
> + XDNA_DBG(aie->xdna, "MP-NPU clock %d, H clock %d\n",
> + aie->npuclk_freq, aie->hclk_freq);
> +
> + return 0;
> +}
> +
> +static int npu3_update_counters(struct aie_device *aie)
> +{
> + struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
> + u32 aieclk_level, npuhclk_level;
> + int ret;
> +
> + /* Use firmware DPM table or pre-defined table, never mixed. */
> + ret = aie4_query_dpm_level(ndev, &aieclk_level, &npuhclk_level);
> + if (ret) {
> + XDNA_WARN(aie->xdna, "Failed to get DPM level from fw: %d", ret);
> + return ret;
> + }
> +
> + if (aieclk_level > ndev->max_aieclk_level ||
> + npuhclk_level > ndev->max_npuhclk_level) {
> + XDNA_ERR(aie->xdna, "DPM level exceeds max: aie %u/%u, npu %u/%u",
> + aieclk_level, ndev->max_aieclk_level,
> + npuhclk_level, ndev->max_npuhclk_level);
> + return -EINVAL;
> + }
> +
> + aie->npuclk_freq = ndev->dpm_clk_tbl[aieclk_level].npuclk;
> + aie->hclk_freq = ndev->dpm_clk_tbl[npuhclk_level].hclk;
> + aie->max_tops = NPU3_DPM_TOPS(ndev,
> + ndev->dpm_clk_tbl[ndev->max_npuhclk_level].hclk);
> + aie->curr_tops = NPU3_DPM_TOPS(ndev, aie->hclk_freq);
> +
> + return 0;
> +}
> +
> +static const struct aie_hw_ops npu3_hw_ops = {
> + .set_dpm = npu3_set_dpm,
> + .update_counters = npu3_update_counters,
> +};
> +
> static const struct amdxdna_dev_priv npu3_dev_priv = {
> .npufw_path = "npu.sbin",
> .certfw_path = "cert.sbin",
> + .dpm_clk_tbl = npu3_dpm_clk_table,
> .mbox_bar = NPU3_MBOX_BAR,
> .mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR,
> .mbox_info_off = NPU3_MBOX_INFO_OFF,
> @@ -71,14 +146,17 @@ static const struct amdxdna_dev_priv npu3_dev_priv = {
> DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU3_SMU, MP1_C2PMSG_60_ALT_1),
> DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU3_SMU, MP1_C2PMSG_61_ALT_1),
> },
> + .hw_ops = &npu3_hw_ops,
> };
>
> static const struct amdxdna_dev_priv npu3_dev_vf_priv = {
> /* vf device does not load firmware */
> + .dpm_clk_tbl = npu3_dpm_clk_table,
> .mbox_bar = NPU3_MBOX_BAR,
> .mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR,
> .mbox_info_off = NPU3_MBOX_INFO_OFF,
> /* vf device does not have smu and psp */
> + .hw_ops = &npu3_hw_ops,
> };
>
> const struct amdxdna_dev_info dev_npu3_pf_info = {
> diff --git a/drivers/accel/amdxdna/npu4_regs.c b/drivers/accel/amdxdna/npu4_regs.c
> index c9648c8032ec..624c1babdff8 100644
> --- a/drivers/accel/amdxdna/npu4_regs.c
> +++ b/drivers/accel/amdxdna/npu4_regs.c
> @@ -104,42 +104,44 @@ const struct amdxdna_fw_feature_tbl npu4_fw_feature_table[] = {
> { 0 }
> };
>
> -static int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
> +static int npu4_set_dpm(struct aie_device *aie, u32 dpm_level)
> {
> + struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
> int ret;
>
> - ret = aie_smu_set_dpm(ndev->aie.smu_hdl, dpm_level);
> + ret = aie_smu_set_dpm(aie->smu_hdl, dpm_level);
> if (ret)
> return ret;
>
> - ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
> - ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
> - ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk);
> - ndev->curr_tops = NPU4_DPM_TOPS(ndev, ndev->hclk_freq);
> + aie->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
> + aie->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
> + aie->max_tops = NPU4_DPM_TOPS(ndev, ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk);
> + aie->curr_tops = NPU4_DPM_TOPS(ndev, aie->hclk_freq);
>
> - XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n",
> - ndev->npuclk_freq, ndev->hclk_freq);
> + XDNA_DBG(aie->xdna, "MP-NPU clock %d, H clock %d\n",
> + aie->npuclk_freq, aie->hclk_freq);
>
> return 0;
> }
>
> -static int npu4_update_counters(struct amdxdna_dev_hdl *ndev)
> +static int npu4_update_counters(struct aie_device *aie)
> {
> + struct amdxdna_dev_hdl *ndev = aie->xdna->dev_handle;
> struct amd_pmf_npu_metrics npu_metrics;
> int ret;
>
> - ret = AIE2_GET_PMF_NPU_METRICS(&npu_metrics);
> + ret = AIE_GET_PMF_NPU_METRICS(&npu_metrics);
> if (ret)
> return ret;
>
> - ndev->npuclk_freq = npu_metrics.mpnpuclk_freq;
> - ndev->hclk_freq = npu_metrics.npuclk_freq;
> - ndev->curr_tops = NPU4_DPM_TOPS(ndev, ndev->hclk_freq);
> + aie->npuclk_freq = npu_metrics.mpnpuclk_freq;
> + aie->hclk_freq = npu_metrics.npuclk_freq;
> + aie->curr_tops = NPU4_DPM_TOPS(ndev, aie->hclk_freq);
>
> return 0;
> }
>
> -const struct aie2_hw_ops npu4_hw_ops = {
> +const struct aie_hw_ops npu4_hw_ops = {
> .set_dpm = npu4_set_dpm,
> .update_counters = npu4_update_counters,
> };
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 09/19] accel/amdxdna: Add context switch hysteresis with debugfs control
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (7 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 08/19] accel/amdxdna: Add clock, DPM frequency, and resource info queries " David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-13 18:29 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 10/19] accel/amdxdna: Refactor AIE4 hardware initialization sequence David Zhang
` (9 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello, Nishad Saraf
Add aie4_set_ctx_hysteresis() to configure the AIE4 context switch
hysteresis timeout via the SET_RUNTIME_CONFIG message, applied at hw
start (PF and classic paths) with a default of 1000 us.
Expose a debugfs node 'ctx_switch_hysteresis_us' to change the timeout
at runtime (0 disables hysteresis). The stored value is re-applied on
every hw start so it survives runtime suspend/resume.
Co-developed-by: Nishad Saraf <nishads@amd.com>
Signed-off-by: Nishad Saraf <nishads@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_message.c | 43 +++++++++++++
drivers/accel/amdxdna/aie4_msg_priv.h | 24 +++++++
drivers/accel/amdxdna/aie4_pci.c | 83 ++++++++++++++++++++++++-
drivers/accel/amdxdna/aie4_pci.h | 9 +++
drivers/accel/amdxdna/amdxdna_debugfs.c | 3 +
drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 +
6 files changed, 161 insertions(+), 2 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
index 263e23aff69f..2820cfb6f9ed 100644
--- a/drivers/accel/amdxdna/aie4_message.c
+++ b/drivers/accel/amdxdna/aie4_message.c
@@ -263,3 +263,46 @@ int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode)
return ret;
}
+
+int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type,
+ const void *data, size_t size)
+{
+ DECLARE_AIE_MSG(aie4_msg_set_runtime_cfg, AIE4_MSG_OP_SET_RUNTIME_CONFIG);
+ u8 buf[sizeof(req.type) + AIE4_RUNTIME_CFG_MAX_DATA_SIZE] __aligned(4) = { 0 };
+ int ret;
+
+ if (size > AIE4_RUNTIME_CFG_MAX_DATA_SIZE)
+ return -EINVAL;
+
+ /* Stage runtime config type and payload for firmware mailbox message. */
+ req.type = type;
+ memcpy(buf, &req.type, sizeof(req.type));
+ memcpy(buf + sizeof(req.type), data, size);
+
+ msg.send_data = buf;
+ msg.send_size = sizeof(req.type) + size;
+
+ ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ if (ret)
+ XDNA_ERR(ndev->aie.xdna, "Failed to set runtime cfg %u: %d", type, ret);
+ return ret;
+}
+
+int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us)
+{
+ struct aie4_msg_runtime_config_ctx_switch_hysteresis cfg = {
+ .timeout_us = timeout_us,
+ };
+ int ret;
+
+ ret = aie4_set_runtime_cfg(ndev, AIE4_RUNTIME_CONFIG_CTX_SWITCH_HYSTERESIS,
+ &cfg, sizeof(cfg));
+ if (ret)
+ XDNA_WARN(ndev->aie.xdna,
+ "Failed to set ctx switch hysteresis to %u us (%d), using fw default",
+ timeout_us, ret);
+ else
+ XDNA_DBG(ndev->aie.xdna, "Context switch hysteresis set to %u us", timeout_us);
+
+ return ret;
+}
diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
index fe78df9e23c8..636bf8d04c76 100644
--- a/drivers/accel/amdxdna/aie4_msg_priv.h
+++ b/drivers/accel/amdxdna/aie4_msg_priv.h
@@ -12,6 +12,7 @@
enum aie4_msg_opcode {
AIE4_MSG_OP_IDENTIFY = 0x10002,
AIE4_MSG_OP_SUSPEND = 0x10003,
+ AIE4_MSG_OP_SET_RUNTIME_CONFIG = 0x10007,
AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F,
AIE4_MSG_OP_CREATE_VFS = 0x20001,
@@ -65,6 +66,29 @@ struct aie4_msg_suspend_resp {
enum aie4_msg_status status;
} __packed;
+/* Type selector for AIE4_MSG_OP_SET_RUNTIME_CONFIG. */
+enum aie4_msg_runtime_config_type {
+ AIE4_RUNTIME_CONFIG_CTX_SWITCH_HYSTERESIS = 0xD,
+ AIE4_MAX_RUNTIME_CONFIG
+};
+
+struct aie4_msg_set_runtime_cfg_req {
+ __u32 type;
+ __u8 data[4];
+} __packed;
+
+struct aie4_msg_set_runtime_cfg_resp {
+ enum aie4_msg_status status;
+} __packed;
+
+/* Maximum payload for runtime config firmware message. */
+#define AIE4_RUNTIME_CFG_MAX_DATA_SIZE 16
+
+/* Context switch hysteresis timeout in microseconds (0 disables). */
+struct aie4_msg_runtime_config_ctx_switch_hysteresis {
+ __u32 timeout_us;
+} __packed;
+
struct aie4_msg_create_vfs_req {
__u32 vf_cnt;
} __packed;
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index 5593dfb6c7ed..446ab2f47c7d 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -5,8 +5,10 @@
#include <drm/amdxdna_accel.h>
#include <drm/drm_drv.h>
+#include <drm/drm_file.h>
#include <drm/drm_managed.h>
#include <drm/drm_print.h>
+#include <linux/debugfs.h>
#include <linux/firmware.h>
#include <linux/sizes.h>
@@ -322,6 +324,22 @@ int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev)
return aie4_msg_set_power_mode(ndev, ndev->pw_mode);
}
+static int aie4_config_fw(struct amdxdna_dev_hdl *ndev)
+{
+ int ret;
+
+ ret = aie4_attach_work_buffer(ndev);
+ if (ret)
+ return ret;
+
+ /* Best-effort tuning knob; failure is warned inside and does not fail hw start */
+ ret = aie4_set_ctx_hysteresis(ndev, ndev->ctx_switch_hysteresis_us);
+ if (ret == -ETIME)
+ return ret;
+
+ return 0;
+}
+
static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
{
int ret;
@@ -334,7 +352,7 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
if (ret)
goto stop_fw;
- ret = aie4_attach_work_buffer(ndev);
+ ret = aie4_config_fw(ndev);
if (ret)
goto mbox_fini;
@@ -418,7 +436,7 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
if (ret)
goto mailbox_fini;
- ret = aie4_attach_work_buffer(ndev);
+ ret = aie4_config_fw(ndev);
if (ret)
goto mailbox_fini;
@@ -573,6 +591,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
ndev->priv = xdna->dev_info->dev_priv;
ndev->aie.xdna = xdna;
+ ndev->ctx_switch_hysteresis_us = AIE4_CTX_HYSTERESIS_US;
ndev->pw_mode = POWER_MODE_DEFAULT;
xdna->dev_handle = ndev;
@@ -918,15 +937,74 @@ static void aie4_classic_fini(struct amdxdna_dev *xdna)
aie4_free_work_buffer(xdna->dev_handle);
}
+static int aie4_ctx_hysteresis_get(void *data, u64 *val)
+{
+ struct amdxdna_dev_hdl *ndev = data;
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+
+ guard(mutex)(&xdna->dev_lock);
+ *val = ndev->ctx_switch_hysteresis_us;
+
+ return 0;
+}
+
+static int aie4_ctx_hysteresis_set(void *data, u64 val)
+{
+ struct amdxdna_dev_hdl *ndev = data;
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ int ret, idx;
+
+ if (val > U32_MAX)
+ return -EINVAL;
+
+ if (!drm_dev_enter(&xdna->ddev, &idx))
+ return -ENODEV;
+
+ mutex_lock(&xdna->dev_lock);
+
+ ret = amdxdna_pm_resume_get_locked(xdna);
+ if (ret)
+ goto unlock;
+
+ ret = aie4_set_ctx_hysteresis(ndev, (u32)val);
+ if (!ret)
+ ndev->ctx_switch_hysteresis_us = (u32)val;
+
+ amdxdna_pm_suspend_put(xdna);
+
+unlock:
+ mutex_unlock(&xdna->dev_lock);
+ drm_dev_exit(idx);
+
+ return ret;
+}
+
+/* Context switch hysteresis timeout in microseconds; 0 disables hysteresis. */
+DEFINE_DEBUGFS_ATTRIBUTE(aie4_ctx_hysteresis_fops, aie4_ctx_hysteresis_get,
+ aie4_ctx_hysteresis_set, "%llu\n");
+
+static void aie4_debugfs_init(struct amdxdna_dev *xdna)
+{
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+
+ /* Context switch hysteresis is only supported on PF and classic devices. */
+ if (!to_pci_dev(xdna->ddev.dev)->is_virtfn)
+ debugfs_create_file_unsafe("ctx_switch_hysteresis_us", 0600,
+ xdna->ddev.accel->debugfs_root, ndev,
+ &aie4_ctx_hysteresis_fops);
+}
+
const struct amdxdna_dev_ops aie4_pf_ops = {
.init = aie4_pf_init,
.fini = aie4_pf_fini,
+ .debugfs_init = aie4_debugfs_init,
.sriov_configure = aie4_sriov_configure,
};
const struct amdxdna_dev_ops aie4_vf_ops = {
.init = aie4_vf_init,
.fini = aie4_vf_fini,
+ .debugfs_init = aie4_debugfs_init,
.hwctx_init = aie4_hwctx_init,
.hwctx_fini = aie4_hwctx_fini,
.cmd_wait = aie4_cmd_wait,
@@ -937,6 +1015,7 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
const struct amdxdna_dev_ops aie4_classic_ops = {
.init = aie4_classic_init,
.fini = aie4_classic_fini,
+ .debugfs_init = aie4_debugfs_init,
.hwctx_init = aie4_hwctx_init,
.hwctx_fini = aie4_hwctx_fini,
.cmd_wait = aie4_cmd_wait,
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 6e9e7f874a44..959ef3695813 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -14,6 +14,9 @@
#include "aie4_msg_priv.h"
#include "amdxdna_mailbox.h"
+/* Default context switch hysteresis timeout in microseconds. */
+#define AIE4_CTX_HYSTERESIS_US 1000
+
struct cert_comp {
struct amdxdna_dev_hdl *ndev;
u32 msix_idx;
@@ -69,6 +72,9 @@ struct amdxdna_dev_hdl {
u8 pw_mode;
+ /* Context switch hysteresis timeout in microseconds. */
+ u32 ctx_switch_hysteresis_us;
+
struct amdxdna_drm_query_firmware_version cert_version;
};
@@ -92,6 +98,9 @@ int aie4_init_dpm_freq_table(struct amdxdna_dev_hdl *ndev);
int aie4_query_dpm_level(struct amdxdna_dev_hdl *ndev,
u32 *aieclk_dpm_level, u32 *npuhclk_dpm_level);
int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode);
+int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type,
+ const void *data, size_t size);
+int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us);
u32 aie4_msg_pasid(struct amdxdna_client *client);
/* aie4_ctx.c */
diff --git a/drivers/accel/amdxdna/amdxdna_debugfs.c b/drivers/accel/amdxdna/amdxdna_debugfs.c
index a6ec17c63629..1f63cc91b168 100644
--- a/drivers/accel/amdxdna/amdxdna_debugfs.c
+++ b/drivers/accel/amdxdna/amdxdna_debugfs.c
@@ -126,4 +126,7 @@ void amdxdna_debugfs_init(struct amdxdna_dev *xdna)
xdna,
amdxdna_dbgfs_files[i].fops);
}
+
+ if (xdna->dev_info->ops->debugfs_init)
+ xdna->dev_info->ops->debugfs_init(xdna);
}
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
index 953bf783b3f7..11f46ec738d7 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -54,6 +54,7 @@ struct amdxdna_sched_job;
struct amdxdna_dev_ops {
int (*init)(struct amdxdna_dev *xdna);
void (*fini)(struct amdxdna_dev *xdna);
+ void (*debugfs_init)(struct amdxdna_dev *xdna);
int (*resume)(struct amdxdna_dev *xdna);
int (*suspend)(struct amdxdna_dev *xdna);
int (*sriov_configure)(struct amdxdna_dev *xdna, int num_vfs);
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 09/19] accel/amdxdna: Add context switch hysteresis with debugfs control
2026-10-09 22:53 ` [PATCH V4 09/19] accel/amdxdna: Add context switch hysteresis with debugfs control David Zhang
@ 2026-10-13 18:29 ` Lizhi Hou
0 siblings, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-13 18:29 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello, Nishad Saraf
On 10/9/26 15:53, David Zhang wrote:
> Add aie4_set_ctx_hysteresis() to configure the AIE4 context switch
> hysteresis timeout via the SET_RUNTIME_CONFIG message, applied at hw
> start (PF and classic paths) with a default of 1000 us.
>
> Expose a debugfs node 'ctx_switch_hysteresis_us' to change the timeout
> at runtime (0 disables hysteresis). The stored value is re-applied on
> every hw start so it survives runtime suspend/resume.
>
> Co-developed-by: Nishad Saraf <nishads@amd.com>
> Signed-off-by: Nishad Saraf <nishads@amd.com>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie4_message.c | 43 +++++++++++++
> drivers/accel/amdxdna/aie4_msg_priv.h | 24 +++++++
> drivers/accel/amdxdna/aie4_pci.c | 83 ++++++++++++++++++++++++-
> drivers/accel/amdxdna/aie4_pci.h | 9 +++
> drivers/accel/amdxdna/amdxdna_debugfs.c | 3 +
> drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 +
> 6 files changed, 161 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
> index 263e23aff69f..2820cfb6f9ed 100644
> --- a/drivers/accel/amdxdna/aie4_message.c
> +++ b/drivers/accel/amdxdna/aie4_message.c
> @@ -263,3 +263,46 @@ int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode)
>
> return ret;
> }
> +
> +int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type,
> + const void *data, size_t size)
> +{
> + DECLARE_AIE_MSG(aie4_msg_set_runtime_cfg, AIE4_MSG_OP_SET_RUNTIME_CONFIG);
> + u8 buf[sizeof(req.type) + AIE4_RUNTIME_CFG_MAX_DATA_SIZE] __aligned(4) = { 0 };
> + int ret;
> +
> + if (size > AIE4_RUNTIME_CFG_MAX_DATA_SIZE)
> + return -EINVAL;
> +
> + /* Stage runtime config type and payload for firmware mailbox message. */
> + req.type = type;
> + memcpy(buf, &req.type, sizeof(req.type));
> + memcpy(buf + sizeof(req.type), data, size);
> +
> + msg.send_data = buf;
> + msg.send_size = sizeof(req.type) + size;
> +
> + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> + if (ret)
> + XDNA_ERR(ndev->aie.xdna, "Failed to set runtime cfg %u: %d", type, ret);
> + return ret;
> +}
> +
> +int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us)
> +{
> + struct aie4_msg_runtime_config_ctx_switch_hysteresis cfg = {
> + .timeout_us = timeout_us,
> + };
> + int ret;
> +
> + ret = aie4_set_runtime_cfg(ndev, AIE4_RUNTIME_CONFIG_CTX_SWITCH_HYSTERESIS,
> + &cfg, sizeof(cfg));
> + if (ret)
> + XDNA_WARN(ndev->aie.xdna,
> + "Failed to set ctx switch hysteresis to %u us (%d), using fw default",
> + timeout_us, ret);
> + else
> + XDNA_DBG(ndev->aie.xdna, "Context switch hysteresis set to %u us", timeout_us);
> +
> + return ret;
> +}
> diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
> index fe78df9e23c8..636bf8d04c76 100644
> --- a/drivers/accel/amdxdna/aie4_msg_priv.h
> +++ b/drivers/accel/amdxdna/aie4_msg_priv.h
> @@ -12,6 +12,7 @@
> enum aie4_msg_opcode {
> AIE4_MSG_OP_IDENTIFY = 0x10002,
> AIE4_MSG_OP_SUSPEND = 0x10003,
> + AIE4_MSG_OP_SET_RUNTIME_CONFIG = 0x10007,
> AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F,
>
> AIE4_MSG_OP_CREATE_VFS = 0x20001,
> @@ -65,6 +66,29 @@ struct aie4_msg_suspend_resp {
> enum aie4_msg_status status;
> } __packed;
>
> +/* Type selector for AIE4_MSG_OP_SET_RUNTIME_CONFIG. */
> +enum aie4_msg_runtime_config_type {
> + AIE4_RUNTIME_CONFIG_CTX_SWITCH_HYSTERESIS = 0xD,
> + AIE4_MAX_RUNTIME_CONFIG
> +};
> +
> +struct aie4_msg_set_runtime_cfg_req {
> + __u32 type;
> + __u8 data[4];
> +} __packed;
> +
> +struct aie4_msg_set_runtime_cfg_resp {
> + enum aie4_msg_status status;
> +} __packed;
> +
> +/* Maximum payload for runtime config firmware message. */
> +#define AIE4_RUNTIME_CFG_MAX_DATA_SIZE 16
> +
> +/* Context switch hysteresis timeout in microseconds (0 disables). */
> +struct aie4_msg_runtime_config_ctx_switch_hysteresis {
> + __u32 timeout_us;
> +} __packed;
> +
> struct aie4_msg_create_vfs_req {
> __u32 vf_cnt;
> } __packed;
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index 5593dfb6c7ed..446ab2f47c7d 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -5,8 +5,10 @@
>
> #include <drm/amdxdna_accel.h>
> #include <drm/drm_drv.h>
> +#include <drm/drm_file.h>
> #include <drm/drm_managed.h>
> #include <drm/drm_print.h>
> +#include <linux/debugfs.h>
> #include <linux/firmware.h>
> #include <linux/sizes.h>
>
> @@ -322,6 +324,22 @@ int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev)
> return aie4_msg_set_power_mode(ndev, ndev->pw_mode);
> }
>
> +static int aie4_config_fw(struct amdxdna_dev_hdl *ndev)
> +{
> + int ret;
> +
> + ret = aie4_attach_work_buffer(ndev);
> + if (ret)
> + return ret;
> +
> + /* Best-effort tuning knob; failure is warned inside and does not fail hw start */
> + ret = aie4_set_ctx_hysteresis(ndev, ndev->ctx_switch_hysteresis_us);
> + if (ret == -ETIME)
> + return ret;
> +
> + return 0;
> +}
> +
> static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
> {
> int ret;
> @@ -334,7 +352,7 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
> if (ret)
> goto stop_fw;
>
> - ret = aie4_attach_work_buffer(ndev);
> + ret = aie4_config_fw(ndev);
> if (ret)
> goto mbox_fini;
>
> @@ -418,7 +436,7 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
> if (ret)
> goto mailbox_fini;
>
> - ret = aie4_attach_work_buffer(ndev);
> + ret = aie4_config_fw(ndev);
> if (ret)
> goto mailbox_fini;
>
> @@ -573,6 +591,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
>
> ndev->priv = xdna->dev_info->dev_priv;
> ndev->aie.xdna = xdna;
> + ndev->ctx_switch_hysteresis_us = AIE4_CTX_HYSTERESIS_US;
> ndev->pw_mode = POWER_MODE_DEFAULT;
> xdna->dev_handle = ndev;
>
> @@ -918,15 +937,74 @@ static void aie4_classic_fini(struct amdxdna_dev *xdna)
> aie4_free_work_buffer(xdna->dev_handle);
> }
>
> +static int aie4_ctx_hysteresis_get(void *data, u64 *val)
> +{
> + struct amdxdna_dev_hdl *ndev = data;
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> +
> + guard(mutex)(&xdna->dev_lock);
> + *val = ndev->ctx_switch_hysteresis_us;
> +
> + return 0;
> +}
> +
> +static int aie4_ctx_hysteresis_set(void *data, u64 val)
> +{
> + struct amdxdna_dev_hdl *ndev = data;
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> + int ret, idx;
> +
> + if (val > U32_MAX)
> + return -EINVAL;
> +
> + if (!drm_dev_enter(&xdna->ddev, &idx))
> + return -ENODEV;
> +
> + mutex_lock(&xdna->dev_lock);
> +
> + ret = amdxdna_pm_resume_get_locked(xdna);
> + if (ret)
> + goto unlock;
> +
> + ret = aie4_set_ctx_hysteresis(ndev, (u32)val);
> + if (!ret)
> + ndev->ctx_switch_hysteresis_us = (u32)val;
> +
> + amdxdna_pm_suspend_put(xdna);
> +
> +unlock:
> + mutex_unlock(&xdna->dev_lock);
> + drm_dev_exit(idx);
> +
> + return ret;
> +}
> +
> +/* Context switch hysteresis timeout in microseconds; 0 disables hysteresis. */
> +DEFINE_DEBUGFS_ATTRIBUTE(aie4_ctx_hysteresis_fops, aie4_ctx_hysteresis_get,
> + aie4_ctx_hysteresis_set, "%llu\n");
> +
> +static void aie4_debugfs_init(struct amdxdna_dev *xdna)
> +{
> + struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
> +
> + /* Context switch hysteresis is only supported on PF and classic devices. */
> + if (!to_pci_dev(xdna->ddev.dev)->is_virtfn)
> + debugfs_create_file_unsafe("ctx_switch_hysteresis_us", 0600,
> + xdna->ddev.accel->debugfs_root, ndev,
> + &aie4_ctx_hysteresis_fops);
> +}
> +
> const struct amdxdna_dev_ops aie4_pf_ops = {
> .init = aie4_pf_init,
> .fini = aie4_pf_fini,
> + .debugfs_init = aie4_debugfs_init,
> .sriov_configure = aie4_sriov_configure,
> };
>
> const struct amdxdna_dev_ops aie4_vf_ops = {
> .init = aie4_vf_init,
> .fini = aie4_vf_fini,
> + .debugfs_init = aie4_debugfs_init,
> .hwctx_init = aie4_hwctx_init,
> .hwctx_fini = aie4_hwctx_fini,
> .cmd_wait = aie4_cmd_wait,
> @@ -937,6 +1015,7 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
> const struct amdxdna_dev_ops aie4_classic_ops = {
> .init = aie4_classic_init,
> .fini = aie4_classic_fini,
> + .debugfs_init = aie4_debugfs_init,
> .hwctx_init = aie4_hwctx_init,
> .hwctx_fini = aie4_hwctx_fini,
> .cmd_wait = aie4_cmd_wait,
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index 6e9e7f874a44..959ef3695813 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -14,6 +14,9 @@
> #include "aie4_msg_priv.h"
> #include "amdxdna_mailbox.h"
>
> +/* Default context switch hysteresis timeout in microseconds. */
> +#define AIE4_CTX_HYSTERESIS_US 1000
> +
> struct cert_comp {
> struct amdxdna_dev_hdl *ndev;
> u32 msix_idx;
> @@ -69,6 +72,9 @@ struct amdxdna_dev_hdl {
>
> u8 pw_mode;
>
> + /* Context switch hysteresis timeout in microseconds. */
> + u32 ctx_switch_hysteresis_us;
> +
> struct amdxdna_drm_query_firmware_version cert_version;
> };
>
> @@ -92,6 +98,9 @@ int aie4_init_dpm_freq_table(struct amdxdna_dev_hdl *ndev);
> int aie4_query_dpm_level(struct amdxdna_dev_hdl *ndev,
> u32 *aieclk_dpm_level, u32 *npuhclk_dpm_level);
> int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode);
> +int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type,
> + const void *data, size_t size);
> +int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us);
> u32 aie4_msg_pasid(struct amdxdna_client *client);
>
> /* aie4_ctx.c */
> diff --git a/drivers/accel/amdxdna/amdxdna_debugfs.c b/drivers/accel/amdxdna/amdxdna_debugfs.c
> index a6ec17c63629..1f63cc91b168 100644
> --- a/drivers/accel/amdxdna/amdxdna_debugfs.c
> +++ b/drivers/accel/amdxdna/amdxdna_debugfs.c
> @@ -126,4 +126,7 @@ void amdxdna_debugfs_init(struct amdxdna_dev *xdna)
> xdna,
> amdxdna_dbgfs_files[i].fops);
> }
> +
> + if (xdna->dev_info->ops->debugfs_init)
> + xdna->dev_info->ops->debugfs_init(xdna);
> }
> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> index 953bf783b3f7..11f46ec738d7 100644
> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> @@ -54,6 +54,7 @@ struct amdxdna_sched_job;
> struct amdxdna_dev_ops {
> int (*init)(struct amdxdna_dev *xdna);
> void (*fini)(struct amdxdna_dev *xdna);
> + void (*debugfs_init)(struct amdxdna_dev *xdna);
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> int (*resume)(struct amdxdna_dev *xdna);
> int (*suspend)(struct amdxdna_dev *xdna);
> int (*sriov_configure)(struct amdxdna_dev *xdna, int num_vfs);
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 10/19] accel/amdxdna: Refactor AIE4 hardware initialization sequence
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (8 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 09/19] accel/amdxdna: Add context switch hysteresis with debugfs control David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-13 18:33 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 11/19] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notify transport hooks David Zhang
` (8 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello
Reorganize AIE4 hardware initialization into distinct phases, next to
the existing aie4_config_fw():
- aie4_query_fw(): Query NPU and CERT firmware versions.
- aie4_setup_aie(): Query AIE version, metadata, initialize DPM frequency
table, and initialize partitions.
Update aie4_pf_hw_start(), aie4_vf_hw_start(), and aie4_classic_hw_start()
to use these phases and unify error unwinding labels. As part of this,
aie4_pf_hw_start() now also calls aie4_query_fw(), which it previously
did not do.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_pci.c | 79 +++++++++++++++++++-------------
1 file changed, 46 insertions(+), 33 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index 446ab2f47c7d..ffe78c0c4e8b 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -50,7 +50,7 @@ static int aie4_fw_is_alive(struct amdxdna_dev *xdna)
{
const struct amdxdna_dev_priv *npriv = xdna->dev_info->dev_priv;
struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
- u32 __iomem *src;
+ void __iomem *src;
u32 fw_is_valid;
int ret;
@@ -280,7 +280,8 @@ static void aie4_partition_fini(struct amdxdna_dev_hdl *ndev)
XDNA_ERR(xdna, "partition fini failed: %d", ret);
}
-static int aie4_query(struct amdxdna_dev_hdl *ndev)
+/* Verify CERT protocol compatibility before starting hardware. */
+static int aie4_query_fw(struct amdxdna_dev_hdl *ndev)
{
struct amdxdna_dev *xdna = ndev->aie.xdna;
int ret;
@@ -293,25 +294,6 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev)
if (ret)
return ret;
- ret = aie4_query_aie_version(ndev, &ndev->aie.version);
- if (ret)
- return ret;
-
- ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata);
- if (ret)
- return ret;
-
- ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols);
-
- ret = aie4_init_dpm_freq_table(ndev);
- if (ret) {
- if (ret == -ETIME)
- return ret;
- /* if query dpm from fw failed, using default value */
- if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm)
- (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0);
- }
-
return 0;
}
@@ -340,6 +322,32 @@ static int aie4_config_fw(struct amdxdna_dev_hdl *ndev)
return 0;
}
+static int aie4_setup_aie(struct amdxdna_dev_hdl *ndev)
+{
+ int ret;
+
+ ret = aie4_query_aie_version(ndev, &ndev->aie.version);
+ if (ret)
+ return ret;
+
+ ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata);
+ if (ret)
+ return ret;
+
+ ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols);
+
+ ret = aie4_init_dpm_freq_table(ndev);
+ if (ret) {
+ if (ret == -ETIME)
+ return ret;
+ /* if query dpm from fw failed, using default value */
+ if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm)
+ (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0);
+ }
+
+ return aie4_partition_init(ndev);
+}
+
static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
{
int ret;
@@ -352,6 +360,10 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
if (ret)
goto stop_fw;
+ ret = aie4_query_fw(ndev);
+ if (ret)
+ goto mbox_fini;
+
ret = aie4_config_fw(ndev);
if (ret)
goto mbox_fini;
@@ -389,13 +401,13 @@ static int aie4_vf_hw_start(struct amdxdna_dev_hdl *ndev)
if (ret)
return ret;
- ret = aie4_query(ndev);
+ ret = aie4_query_fw(ndev);
if (ret)
- goto mailbox_fini;
+ goto mbox_fini;
- ret = aie4_partition_init(ndev);
+ ret = aie4_setup_aie(ndev);
if (ret)
- goto mailbox_fini;
+ goto mbox_fini;
ret = aie4_restore_power_mode(ndev);
if (ret)
@@ -405,7 +417,7 @@ static int aie4_vf_hw_start(struct amdxdna_dev_hdl *ndev)
partition_fini:
aie4_partition_fini(ndev);
-mailbox_fini:
+mbox_fini:
aie4_mailbox_fini(ndev);
return ret;
}
@@ -432,17 +444,17 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
if (ret)
goto stop_fw;
- ret = aie4_query(ndev);
+ ret = aie4_query_fw(ndev);
if (ret)
- goto mailbox_fini;
+ goto mbox_fini;
ret = aie4_config_fw(ndev);
if (ret)
- goto mailbox_fini;
+ goto mbox_fini;
- ret = aie4_partition_init(ndev);
+ ret = aie4_setup_aie(ndev);
if (ret)
- goto mailbox_fini;
+ goto mbox_fini;
ret = aie4_restore_power_mode(ndev);
if (ret)
@@ -452,10 +464,11 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
partition_fini:
aie4_partition_fini(ndev);
-mailbox_fini:
+mbox_fini:
aie4_mailbox_fini(ndev);
stop_fw:
aie4_fw_stop(ndev);
+
return ret;
}
@@ -529,8 +542,8 @@ static int aie4_prepare_firmware(struct amdxdna_dev_hdl *ndev,
void __iomem *tbl[PCI_NUM_RESOURCES])
{
struct amdxdna_dev *xdna = ndev->aie.xdna;
+ struct smu_config smu_conf = {};
struct psp_config psp_conf;
- struct smu_config smu_conf;
int i;
psp_conf.fw_size = npufw->size;
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 10/19] accel/amdxdna: Refactor AIE4 hardware initialization sequence
2026-10-09 22:53 ` [PATCH V4 10/19] accel/amdxdna: Refactor AIE4 hardware initialization sequence David Zhang
@ 2026-10-13 18:33 ` Lizhi Hou
0 siblings, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-13 18:33 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello
On 10/9/26 15:53, David Zhang wrote:
> Reorganize AIE4 hardware initialization into distinct phases, next to
> the existing aie4_config_fw():
> - aie4_query_fw(): Query NPU and CERT firmware versions.
> - aie4_setup_aie(): Query AIE version, metadata, initialize DPM frequency
> table, and initialize partitions.
>
> Update aie4_pf_hw_start(), aie4_vf_hw_start(), and aie4_classic_hw_start()
> to use these phases and unify error unwinding labels. As part of this,
> aie4_pf_hw_start() now also calls aie4_query_fw(), which it previously
> did not do.
>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie4_pci.c | 79 +++++++++++++++++++-------------
> 1 file changed, 46 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index 446ab2f47c7d..ffe78c0c4e8b 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -50,7 +50,7 @@ static int aie4_fw_is_alive(struct amdxdna_dev *xdna)
> {
> const struct amdxdna_dev_priv *npriv = xdna->dev_info->dev_priv;
> struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
> - u32 __iomem *src;
> + void __iomem *src;
> u32 fw_is_valid;
> int ret;
>
> @@ -280,7 +280,8 @@ static void aie4_partition_fini(struct amdxdna_dev_hdl *ndev)
> XDNA_ERR(xdna, "partition fini failed: %d", ret);
> }
>
> -static int aie4_query(struct amdxdna_dev_hdl *ndev)
> +/* Verify CERT protocol compatibility before starting hardware. */
> +static int aie4_query_fw(struct amdxdna_dev_hdl *ndev)
> {
> struct amdxdna_dev *xdna = ndev->aie.xdna;
> int ret;
> @@ -293,25 +294,6 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev)
> if (ret)
> return ret;
>
> - ret = aie4_query_aie_version(ndev, &ndev->aie.version);
> - if (ret)
> - return ret;
> -
> - ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata);
> - if (ret)
> - return ret;
> -
> - ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols);
> -
> - ret = aie4_init_dpm_freq_table(ndev);
> - if (ret) {
> - if (ret == -ETIME)
> - return ret;
> - /* if query dpm from fw failed, using default value */
> - if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm)
> - (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0);
> - }
> -
> return 0;
> }
>
> @@ -340,6 +322,32 @@ static int aie4_config_fw(struct amdxdna_dev_hdl *ndev)
> return 0;
> }
>
> +static int aie4_setup_aie(struct amdxdna_dev_hdl *ndev)
> +{
> + int ret;
> +
> + ret = aie4_query_aie_version(ndev, &ndev->aie.version);
> + if (ret)
> + return ret;
> +
> + ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata);
> + if (ret)
> + return ret;
> +
> + ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols);
> +
> + ret = aie4_init_dpm_freq_table(ndev);
> + if (ret) {
> + if (ret == -ETIME)
> + return ret;
> + /* if query dpm from fw failed, using default value */
> + if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm)
> + (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0);
> + }
> +
> + return aie4_partition_init(ndev);
> +}
> +
> static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
> {
> int ret;
> @@ -352,6 +360,10 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
> if (ret)
> goto stop_fw;
>
> + ret = aie4_query_fw(ndev);
> + if (ret)
> + goto mbox_fini;
> +
> ret = aie4_config_fw(ndev);
> if (ret)
> goto mbox_fini;
> @@ -389,13 +401,13 @@ static int aie4_vf_hw_start(struct amdxdna_dev_hdl *ndev)
> if (ret)
> return ret;
>
> - ret = aie4_query(ndev);
> + ret = aie4_query_fw(ndev);
> if (ret)
> - goto mailbox_fini;
> + goto mbox_fini;
>
> - ret = aie4_partition_init(ndev);
> + ret = aie4_setup_aie(ndev);
> if (ret)
> - goto mailbox_fini;
> + goto mbox_fini;
>
> ret = aie4_restore_power_mode(ndev);
> if (ret)
> @@ -405,7 +417,7 @@ static int aie4_vf_hw_start(struct amdxdna_dev_hdl *ndev)
>
> partition_fini:
> aie4_partition_fini(ndev);
> -mailbox_fini:
> +mbox_fini:
> aie4_mailbox_fini(ndev);
> return ret;
> }
> @@ -432,17 +444,17 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
> if (ret)
> goto stop_fw;
>
> - ret = aie4_query(ndev);
> + ret = aie4_query_fw(ndev);
> if (ret)
> - goto mailbox_fini;
> + goto mbox_fini;
>
> ret = aie4_config_fw(ndev);
> if (ret)
> - goto mailbox_fini;
> + goto mbox_fini;
>
> - ret = aie4_partition_init(ndev);
> + ret = aie4_setup_aie(ndev);
> if (ret)
> - goto mailbox_fini;
> + goto mbox_fini;
>
> ret = aie4_restore_power_mode(ndev);
> if (ret)
> @@ -452,10 +464,11 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
>
> partition_fini:
> aie4_partition_fini(ndev);
> -mailbox_fini:
> +mbox_fini:
> aie4_mailbox_fini(ndev);
> stop_fw:
> aie4_fw_stop(ndev);
> +
> return ret;
> }
>
> @@ -529,8 +542,8 @@ static int aie4_prepare_firmware(struct amdxdna_dev_hdl *ndev,
> void __iomem *tbl[PCI_NUM_RESOURCES])
> {
> struct amdxdna_dev *xdna = ndev->aie.xdna;
> + struct smu_config smu_conf = {};
> struct psp_config psp_conf;
> - struct smu_config smu_conf;
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> int i;
>
> psp_conf.fw_size = npufw->size;
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 11/19] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notify transport hooks
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (9 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 10/19] accel/amdxdna: Refactor AIE4 hardware initialization sequence David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-13 18:38 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 12/19] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout David Zhang
` (7 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello, Wendy Liang
Separate PCI-specific doorbell and interrupt notification handling from
the transport-neutral context code.
The new transport functions are wired in later patches in this series.
Doorbell ringing is not invoked until full context setup and BAR
validation are done, so no NULL dereference or BAR boundary bypass can
occur.
Co-developed-by: Wendy Liang <wendy.liang@amd.com>
Signed-off-by: Wendy Liang <wendy.liang@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_ctx.c | 38 ++++++-----------
drivers/accel/amdxdna/aie4_pci.c | 66 +++++++++++++++++++++++++++++
drivers/accel/amdxdna/aie4_pci.h | 14 ++++++
drivers/accel/amdxdna/amdxdna_ctx.h | 2 +
4 files changed, 96 insertions(+), 24 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
index 5eb918e1d58c..20b725de6ab7 100644
--- a/drivers/accel/amdxdna/aie4_ctx.c
+++ b/drivers/accel/amdxdna/aie4_ctx.c
@@ -22,63 +22,52 @@
#include "amdxdna_mailbox_helper.h"
#include "amdxdna_pci_drv.h"
-static irqreturn_t cert_comp_isr(int irq, void *p)
-{
- struct cert_comp *cert_comp = p;
-
- wake_up_all(&cert_comp->waitq);
- return IRQ_HANDLED;
-}
-
static struct cert_comp *aie4_lookup_cert_comp(struct amdxdna_dev_hdl *ndev, u32 msix_idx)
{
struct amdxdna_dev *xdna = ndev->aie.xdna;
- struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
struct cert_comp *cert_comp;
int ret;
- guard(mutex)(&ndev->cert_comp_lock);
-
+ mutex_lock(&ndev->cert_comp_lock);
cert_comp = xa_load(&ndev->cert_comp_xa, msix_idx);
if (cert_comp) {
kref_get(&cert_comp->kref);
+ mutex_unlock(&ndev->cert_comp_lock);
return cert_comp;
}
cert_comp = kzalloc_obj(*cert_comp);
if (!cert_comp)
- return NULL;
+ goto unlock;
cert_comp->ndev = ndev;
cert_comp->msix_idx = msix_idx;
+ cert_comp->irq = -ENOENT;
init_waitqueue_head(&cert_comp->waitq);
kref_init(&cert_comp->kref);
- ret = pci_irq_vector(pdev, cert_comp->msix_idx);
- if (ret < 0) {
- XDNA_ERR(xdna, "MSI-X idx %u is invalid, ret:%d", msix_idx, ret);
- goto free_cert_comp;
- }
- cert_comp->irq = ret;
-
- ret = request_irq(cert_comp->irq, cert_comp_isr, 0, "xdna_hsa", cert_comp);
+ /* Transport-specific: PCI wires an MSI-X irq, platform an IPI callback. */
+ ret = aie4_request_notification(cert_comp);
if (ret) {
- XDNA_ERR(xdna, "request irq %d failed %d", cert_comp->irq, ret);
+ XDNA_ERR(xdna, "request notification for msix idx %u failed %d", msix_idx, ret);
goto free_cert_comp;
}
ret = xa_err(xa_store(&ndev->cert_comp_xa, msix_idx, cert_comp, GFP_KERNEL));
if (ret) {
- XDNA_ERR(xdna, "store cert_comp for msix idx %d failed %d", msix_idx, ret);
+ XDNA_ERR(xdna, "store cert_comp for msix idx %u failed %d", msix_idx, ret);
goto free_irq;
}
+ mutex_unlock(&ndev->cert_comp_lock);
return cert_comp;
free_irq:
- free_irq(cert_comp->irq, cert_comp);
+ aie4_free_notification(cert_comp);
free_cert_comp:
kfree(cert_comp);
+unlock:
+ mutex_unlock(&ndev->cert_comp_lock);
return NULL;
}
@@ -90,7 +79,7 @@ static void cert_comp_release(struct kref *kref)
drm_WARN_ON(&ndev->aie.xdna->ddev, !mutex_is_locked(&ndev->cert_comp_lock));
xa_erase(&ndev->cert_comp_xa, cert_comp->msix_idx);
- free_irq(cert_comp->irq, cert_comp);
+ aie4_free_notification(cert_comp);
kfree(cert_comp);
}
@@ -100,6 +89,7 @@ static void aie4_put_cert_comp(struct cert_comp *cert_comp)
ndev = cert_comp->ndev;
guard(mutex)(&ndev->cert_comp_lock);
+
kref_put(&cert_comp->kref, cert_comp_release);
}
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index ffe78c0c4e8b..93594211c169 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -14,6 +14,7 @@
#include "aie.h"
#include "aie4_msg_priv.h"
+#include "amdxdna_ctx.h"
#include "aie4_pci.h"
#include "amdxdna_error.h"
#include "amdxdna_mailbox.h"
@@ -112,6 +113,69 @@ static void aie4_mailbox_fini(struct amdxdna_dev_hdl *ndev)
ndev->mbox = NULL;
}
+static irqreturn_t cert_comp_isr(int irq, void *p)
+{
+ struct cert_comp *cert_comp = p;
+
+ wake_up_all(&cert_comp->waitq);
+ return IRQ_HANDLED;
+}
+
+/* Wire per-cert completion notification interrupt. */
+int aie4_request_notification(struct cert_comp *comp)
+{
+ struct pci_dev *pdev = to_pci_dev(comp->ndev->aie.xdna->ddev.dev);
+ int ret;
+
+ ret = pci_irq_vector(pdev, comp->msix_idx);
+ if (ret < 0)
+ return ret;
+ comp->irq = ret;
+
+ ret = request_irq(comp->irq, cert_comp_isr, 0, "xdna_hsa", comp);
+ if (ret) {
+ comp->irq = -ENOENT;
+ return ret;
+ }
+
+ return 0;
+}
+
+/* Tear down per-cert completion notification interrupt. */
+void aie4_free_notification(struct cert_comp *comp)
+{
+ if (comp->irq >= 0)
+ free_irq(comp->irq, comp);
+}
+
+/* Validate and configure hardware context doorbell target. */
+int aie4_doorbell_setup(struct amdxdna_hwctx *hwctx,
+ const struct aie4_msg_create_hw_context_resp *resp)
+{
+ struct amdxdna_dev *xdna = hwctx->client->xdna;
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+ struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+ u64 db_off = (u64)ndev->priv->doorbell_off + resp->doorbell_offset;
+
+ /* Validate doorbell offset against mapped BAR bounds. */
+ if (db_off + sizeof(u32) >
+ pci_resource_len(pdev, xdna->dev_info->doorbell_bar)) {
+ XDNA_ERR(xdna, "doorbell offset 0x%llx out of BAR", db_off);
+ return -EINVAL;
+ }
+
+ priv->doorbell_addr = ndev->doorbell_base + ndev->priv->doorbell_off +
+ resp->doorbell_offset;
+ return 0;
+}
+
+/* Ring context doorbell to notify CERT. */
+void aie4_doorbell_ring(struct amdxdna_hwctx *hwctx)
+{
+ writel(0, hwctx->priv->doorbell_addr);
+}
+
static int aie4_irq_init(struct amdxdna_dev *xdna)
{
struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
@@ -630,6 +694,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
set_bit(SMU_REG_BAR(ndev, i), &bars);
set_bit(xdna->dev_info->mbox_bar, &bars);
set_bit(xdna->dev_info->sram_bar, &bars);
+ set_bit(xdna->dev_info->doorbell_bar, &bars);
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
if (!test_bit(i, &bars))
@@ -643,6 +708,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
ndev->mbox_base = tbl[xdna->dev_info->mbox_bar];
ndev->rbuf_base = tbl[xdna->dev_info->sram_bar];
+ ndev->doorbell_base = tbl[xdna->dev_info->doorbell_bar];
pci_set_master(pdev);
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 959ef3695813..9fcdfcc5a15f 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -32,6 +32,8 @@ struct amdxdna_hwctx_priv {
struct cert_comp *cert_comp;
u32 hw_ctx_id;
+
+ void __iomem *doorbell_addr;
};
struct amdxdna_dev_priv {
@@ -54,6 +56,7 @@ struct amdxdna_dev_hdl {
const struct amdxdna_dev_priv *priv;
void __iomem *mbox_base;
void __iomem *rbuf_base;
+ void __iomem *doorbell_base;
struct mailbox *mbox;
u32 partition_id;
@@ -111,6 +114,17 @@ int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
/* aie4_pci.c */
int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev);
+/*
+ * Transport hooks implemented by PCI backend. Doorbell hooks are wired during
+ * kernel queue creation and command submission in later patches in the series.
+ */
+struct aie4_msg_create_hw_context_resp;
+int aie4_doorbell_setup(struct amdxdna_hwctx *hwctx,
+ const struct aie4_msg_create_hw_context_resp *resp);
+void aie4_doorbell_ring(struct amdxdna_hwctx *hwctx);
+int aie4_request_notification(struct cert_comp *comp);
+void aie4_free_notification(struct cert_comp *comp);
+
/* aie4_sriov.c */
#if IS_ENABLED(CONFIG_PCI_IOV)
int aie4_sriov_configure(struct amdxdna_dev *xdna, int num_vfs);
diff --git a/drivers/accel/amdxdna/amdxdna_ctx.h b/drivers/accel/amdxdna/amdxdna_ctx.h
index 6e78bab8a02c..9bbc3db4ebde 100644
--- a/drivers/accel/amdxdna/amdxdna_ctx.h
+++ b/drivers/accel/amdxdna/amdxdna_ctx.h
@@ -6,6 +6,8 @@
#ifndef _AMDXDNA_CTX_H_
#define _AMDXDNA_CTX_H_
+#include <drm/amdxdna_accel.h>
+#include <drm/gpu_scheduler.h>
#include <linux/bitfield.h>
#include "amdxdna_gem.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 11/19] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notify transport hooks
2026-10-09 22:53 ` [PATCH V4 11/19] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notify transport hooks David Zhang
@ 2026-10-13 18:38 ` Lizhi Hou
0 siblings, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-13 18:38 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello, Wendy Liang
On 10/9/26 15:53, David Zhang wrote:
> Separate PCI-specific doorbell and interrupt notification handling from
> the transport-neutral context code.
>
> The new transport functions are wired in later patches in this series.
> Doorbell ringing is not invoked until full context setup and BAR
> validation are done, so no NULL dereference or BAR boundary bypass can
> occur.
>
> Co-developed-by: Wendy Liang <wendy.liang@amd.com>
> Signed-off-by: Wendy Liang <wendy.liang@amd.com>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie4_ctx.c | 38 ++++++-----------
> drivers/accel/amdxdna/aie4_pci.c | 66 +++++++++++++++++++++++++++++
> drivers/accel/amdxdna/aie4_pci.h | 14 ++++++
> drivers/accel/amdxdna/amdxdna_ctx.h | 2 +
> 4 files changed, 96 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
> index 5eb918e1d58c..20b725de6ab7 100644
> --- a/drivers/accel/amdxdna/aie4_ctx.c
> +++ b/drivers/accel/amdxdna/aie4_ctx.c
> @@ -22,63 +22,52 @@
> #include "amdxdna_mailbox_helper.h"
> #include "amdxdna_pci_drv.h"
>
> -static irqreturn_t cert_comp_isr(int irq, void *p)
> -{
> - struct cert_comp *cert_comp = p;
> -
> - wake_up_all(&cert_comp->waitq);
> - return IRQ_HANDLED;
> -}
> -
> static struct cert_comp *aie4_lookup_cert_comp(struct amdxdna_dev_hdl *ndev, u32 msix_idx)
> {
> struct amdxdna_dev *xdna = ndev->aie.xdna;
> - struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
> struct cert_comp *cert_comp;
> int ret;
>
> - guard(mutex)(&ndev->cert_comp_lock);
> -
> + mutex_lock(&ndev->cert_comp_lock);
> cert_comp = xa_load(&ndev->cert_comp_xa, msix_idx);
> if (cert_comp) {
> kref_get(&cert_comp->kref);
> + mutex_unlock(&ndev->cert_comp_lock);
> return cert_comp;
> }
>
> cert_comp = kzalloc_obj(*cert_comp);
> if (!cert_comp)
> - return NULL;
> + goto unlock;
>
> cert_comp->ndev = ndev;
> cert_comp->msix_idx = msix_idx;
> + cert_comp->irq = -ENOENT;
> init_waitqueue_head(&cert_comp->waitq);
> kref_init(&cert_comp->kref);
>
> - ret = pci_irq_vector(pdev, cert_comp->msix_idx);
> - if (ret < 0) {
> - XDNA_ERR(xdna, "MSI-X idx %u is invalid, ret:%d", msix_idx, ret);
> - goto free_cert_comp;
> - }
> - cert_comp->irq = ret;
> -
> - ret = request_irq(cert_comp->irq, cert_comp_isr, 0, "xdna_hsa", cert_comp);
> + /* Transport-specific: PCI wires an MSI-X irq, platform an IPI callback. */
> + ret = aie4_request_notification(cert_comp);
> if (ret) {
> - XDNA_ERR(xdna, "request irq %d failed %d", cert_comp->irq, ret);
> + XDNA_ERR(xdna, "request notification for msix idx %u failed %d", msix_idx, ret);
> goto free_cert_comp;
> }
>
> ret = xa_err(xa_store(&ndev->cert_comp_xa, msix_idx, cert_comp, GFP_KERNEL));
> if (ret) {
> - XDNA_ERR(xdna, "store cert_comp for msix idx %d failed %d", msix_idx, ret);
> + XDNA_ERR(xdna, "store cert_comp for msix idx %u failed %d", msix_idx, ret);
> goto free_irq;
> }
> + mutex_unlock(&ndev->cert_comp_lock);
>
> return cert_comp;
>
> free_irq:
> - free_irq(cert_comp->irq, cert_comp);
> + aie4_free_notification(cert_comp);
> free_cert_comp:
> kfree(cert_comp);
> +unlock:
> + mutex_unlock(&ndev->cert_comp_lock);
> return NULL;
> }
>
> @@ -90,7 +79,7 @@ static void cert_comp_release(struct kref *kref)
> drm_WARN_ON(&ndev->aie.xdna->ddev, !mutex_is_locked(&ndev->cert_comp_lock));
>
> xa_erase(&ndev->cert_comp_xa, cert_comp->msix_idx);
> - free_irq(cert_comp->irq, cert_comp);
> + aie4_free_notification(cert_comp);
> kfree(cert_comp);
> }
>
> @@ -100,6 +89,7 @@ static void aie4_put_cert_comp(struct cert_comp *cert_comp)
>
> ndev = cert_comp->ndev;
> guard(mutex)(&ndev->cert_comp_lock);
> +
> kref_put(&cert_comp->kref, cert_comp_release);
> }
>
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index ffe78c0c4e8b..93594211c169 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -14,6 +14,7 @@
>
> #include "aie.h"
> #include "aie4_msg_priv.h"
> +#include "amdxdna_ctx.h"
Dictionary order please.
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> #include "aie4_pci.h"
> #include "amdxdna_error.h"
> #include "amdxdna_mailbox.h"
> @@ -112,6 +113,69 @@ static void aie4_mailbox_fini(struct amdxdna_dev_hdl *ndev)
> ndev->mbox = NULL;
> }
>
> +static irqreturn_t cert_comp_isr(int irq, void *p)
> +{
> + struct cert_comp *cert_comp = p;
> +
> + wake_up_all(&cert_comp->waitq);
> + return IRQ_HANDLED;
> +}
> +
> +/* Wire per-cert completion notification interrupt. */
> +int aie4_request_notification(struct cert_comp *comp)
> +{
> + struct pci_dev *pdev = to_pci_dev(comp->ndev->aie.xdna->ddev.dev);
> + int ret;
> +
> + ret = pci_irq_vector(pdev, comp->msix_idx);
> + if (ret < 0)
> + return ret;
> + comp->irq = ret;
> +
> + ret = request_irq(comp->irq, cert_comp_isr, 0, "xdna_hsa", comp);
> + if (ret) {
> + comp->irq = -ENOENT;
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +/* Tear down per-cert completion notification interrupt. */
> +void aie4_free_notification(struct cert_comp *comp)
> +{
> + if (comp->irq >= 0)
> + free_irq(comp->irq, comp);
> +}
> +
> +/* Validate and configure hardware context doorbell target. */
> +int aie4_doorbell_setup(struct amdxdna_hwctx *hwctx,
> + const struct aie4_msg_create_hw_context_resp *resp)
> +{
> + struct amdxdna_dev *xdna = hwctx->client->xdna;
> + struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
> + struct amdxdna_hwctx_priv *priv = hwctx->priv;
> + struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
> + u64 db_off = (u64)ndev->priv->doorbell_off + resp->doorbell_offset;
> +
> + /* Validate doorbell offset against mapped BAR bounds. */
> + if (db_off + sizeof(u32) >
> + pci_resource_len(pdev, xdna->dev_info->doorbell_bar)) {
> + XDNA_ERR(xdna, "doorbell offset 0x%llx out of BAR", db_off);
> + return -EINVAL;
> + }
> +
> + priv->doorbell_addr = ndev->doorbell_base + ndev->priv->doorbell_off +
> + resp->doorbell_offset;
> + return 0;
> +}
> +
> +/* Ring context doorbell to notify CERT. */
> +void aie4_doorbell_ring(struct amdxdna_hwctx *hwctx)
> +{
> + writel(0, hwctx->priv->doorbell_addr);
> +}
> +
> static int aie4_irq_init(struct amdxdna_dev *xdna)
> {
> struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
> @@ -630,6 +694,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
> set_bit(SMU_REG_BAR(ndev, i), &bars);
> set_bit(xdna->dev_info->mbox_bar, &bars);
> set_bit(xdna->dev_info->sram_bar, &bars);
> + set_bit(xdna->dev_info->doorbell_bar, &bars);
>
> for (i = 0; i < PCI_NUM_RESOURCES; i++) {
> if (!test_bit(i, &bars))
> @@ -643,6 +708,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
>
> ndev->mbox_base = tbl[xdna->dev_info->mbox_bar];
> ndev->rbuf_base = tbl[xdna->dev_info->sram_bar];
> + ndev->doorbell_base = tbl[xdna->dev_info->doorbell_bar];
>
> pci_set_master(pdev);
>
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index 959ef3695813..9fcdfcc5a15f 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -32,6 +32,8 @@ struct amdxdna_hwctx_priv {
>
> struct cert_comp *cert_comp;
> u32 hw_ctx_id;
> +
> + void __iomem *doorbell_addr;
> };
>
> struct amdxdna_dev_priv {
> @@ -54,6 +56,7 @@ struct amdxdna_dev_hdl {
> const struct amdxdna_dev_priv *priv;
> void __iomem *mbox_base;
> void __iomem *rbuf_base;
> + void __iomem *doorbell_base;
>
> struct mailbox *mbox;
> u32 partition_id;
> @@ -111,6 +114,17 @@ int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
> /* aie4_pci.c */
> int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev);
>
> +/*
> + * Transport hooks implemented by PCI backend. Doorbell hooks are wired during
> + * kernel queue creation and command submission in later patches in the series.
> + */
> +struct aie4_msg_create_hw_context_resp;
> +int aie4_doorbell_setup(struct amdxdna_hwctx *hwctx,
> + const struct aie4_msg_create_hw_context_resp *resp);
> +void aie4_doorbell_ring(struct amdxdna_hwctx *hwctx);
> +int aie4_request_notification(struct cert_comp *comp);
> +void aie4_free_notification(struct cert_comp *comp);
> +
> /* aie4_sriov.c */
> #if IS_ENABLED(CONFIG_PCI_IOV)
> int aie4_sriov_configure(struct amdxdna_dev *xdna, int num_vfs);
> diff --git a/drivers/accel/amdxdna/amdxdna_ctx.h b/drivers/accel/amdxdna/amdxdna_ctx.h
> index 6e78bab8a02c..9bbc3db4ebde 100644
> --- a/drivers/accel/amdxdna/amdxdna_ctx.h
> +++ b/drivers/accel/amdxdna/amdxdna_ctx.h
> @@ -6,6 +6,8 @@
> #ifndef _AMDXDNA_CTX_H_
> #define _AMDXDNA_CTX_H_
>
> +#include <drm/amdxdna_accel.h>
> +#include <drm/gpu_scheduler.h>
> #include <linux/bitfield.h>
>
> #include "amdxdna_gem.h"
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 12/19] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (10 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 11/19] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notify transport hooks David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-13 18:41 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 13/19] accel/amdxdna: Prepare for AIE4 command submission David Zhang
` (6 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello, Wendy Liang
Initialize kernel-mode submission required buffers, workqueue, and
hardware contexts:
- Update queue definition that is being used to send requests.
- Add job workqueue for pending and running jobs.
- Add mutex protection for each io.
- Initialize queue with direct and indirect packet, format queue header.
- Add kernel-mode submission required steps in hwctx create/destroy.
- Add aie4_get_cert_comp() to safely acquire a reference to the
per-hwctx completion tracker under io_lock in aie4_cmd_wait() before
waiting on the queue, preventing race conditions with
aie4_hwctx_destroy().
Co-developed-by: Max Zhen <max.zhen@amd.com>
Signed-off-by: Max Zhen <max.zhen@amd.com>
Co-developed-by: Wendy Liang <wendy.liang@amd.com>
Signed-off-by: Wendy Liang <wendy.liang@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_ctx.c | 198 ++++++++++++++++++++----
drivers/accel/amdxdna/aie4_host_queue.h | 65 ++++++++
drivers/accel/amdxdna/aie4_pci.h | 40 +++++
3 files changed, 270 insertions(+), 33 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
index 20b725de6ab7..767ba6ecbfc6 100644
--- a/drivers/accel/amdxdna/aie4_ctx.c
+++ b/drivers/accel/amdxdna/aie4_ctx.c
@@ -22,6 +22,13 @@
#include "amdxdna_mailbox_helper.h"
#include "amdxdna_pci_drv.h"
+#define CTX_INVALID_ID (~0U)
+#define CTX_INVALID_DOORBELL AMDXDNA_INVALID_DOORBELL_OFFSET
+
+static void job_worker(struct work_struct *work)
+{
+}
+
static struct cert_comp *aie4_lookup_cert_comp(struct amdxdna_dev_hdl *ndev, u32 msix_idx)
{
struct amdxdna_dev *xdna = ndev->aie.xdna;
@@ -37,8 +44,10 @@ static struct cert_comp *aie4_lookup_cert_comp(struct amdxdna_dev_hdl *ndev, u32
}
cert_comp = kzalloc_obj(*cert_comp);
- if (!cert_comp)
+ if (!cert_comp) {
+ ret = -ENOMEM;
goto unlock;
+ }
cert_comp->ndev = ndev;
cert_comp->msix_idx = msix_idx;
@@ -68,7 +77,7 @@ static struct cert_comp *aie4_lookup_cert_comp(struct amdxdna_dev_hdl *ndev, u32
kfree(cert_comp);
unlock:
mutex_unlock(&ndev->cert_comp_lock);
- return NULL;
+ return ERR_PTR(ret);
}
static void cert_comp_release(struct kref *kref)
@@ -76,8 +85,6 @@ static void cert_comp_release(struct kref *kref)
struct cert_comp *cert_comp = container_of(kref, struct cert_comp, kref);
struct amdxdna_dev_hdl *ndev = cert_comp->ndev;
- drm_WARN_ON(&ndev->aie.xdna->ddev, !mutex_is_locked(&ndev->cert_comp_lock));
-
xa_erase(&ndev->cert_comp_xa, cert_comp->msix_idx);
aie4_free_notification(cert_comp);
kfree(cert_comp);
@@ -85,20 +92,41 @@ static void cert_comp_release(struct kref *kref)
static void aie4_put_cert_comp(struct cert_comp *cert_comp)
{
- struct amdxdna_dev_hdl *ndev;
+ struct amdxdna_dev_hdl *ndev = cert_comp->ndev;
- ndev = cert_comp->ndev;
guard(mutex)(&ndev->cert_comp_lock);
kref_put(&cert_comp->kref, cert_comp_release);
}
-static int aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context_id)
+static struct cert_comp *aie4_get_cert_comp(struct amdxdna_hwctx *hwctx)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+ struct cert_comp *cert_comp;
+
+ /* Take io_lock to serialize against cert_comp link/unlink. */
+ guard(mutex)(&priv->io_lock);
+
+ cert_comp = READ_ONCE(priv->cert_comp);
+ if (cert_comp)
+ kref_get(&cert_comp->kref);
+
+ return cert_comp;
+}
+
+static void aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context_id)
{
DECLARE_AIE_MSG(aie4_msg_destroy_hw_context, AIE4_MSG_OP_DESTROY_HW_CONTEXT);
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ int ret;
+
+ if (hw_context_id == CTX_INVALID_ID)
+ return;
req.hw_context_id = hw_context_id;
- return aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ if (ret)
+ XDNA_WARN(xdna, "destroy ctx id %d failed %d", hw_context_id, ret);
}
static u8 aie4_parse_priority_to_dev(u32 priority)
@@ -117,19 +145,20 @@ static u8 aie4_parse_priority_to_dev(u32 priority)
}
}
-static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
+int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
{
DECLARE_AIE_MSG(aie4_msg_create_hw_context, AIE4_MSG_OP_CREATE_HW_CONTEXT);
struct amdxdna_client *client = hwctx->client;
struct amdxdna_hwctx_priv *priv = hwctx->priv;
- struct amdxdna_dev *xdna = hwctx->client->xdna;
+ struct amdxdna_dev *xdna = client->xdna;
struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ struct cert_comp *cert_comp;
int ret;
drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
if (!ndev->partition_id || !hwctx->num_tiles) {
- XDNA_ERR(xdna, "invalid request partition_id %d, num_tiles %d",
+ XDNA_ERR(xdna, "invalid request partition_id %u, num_tiles %d",
ndev->partition_id, hwctx->num_tiles);
return -EINVAL;
}
@@ -139,7 +168,6 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
req.pasid = aie4_msg_pasid(client);
req.pasid = req.pasid == IOMMU_PASID_INVALID ? 0 : req.pasid;
req.priority_band = aie4_parse_priority_to_dev(hwctx->qos.priority);
-
req.hsa_addr_high = upper_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
req.hsa_addr_low = lower_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
@@ -153,72 +181,142 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
}
XDNA_DBG(xdna, "resp msix: %d, ctx id: %d, doorbell: %d",
- resp.job_complete_msix_idx,
- resp.hw_context_id,
+ resp.job_complete_msix_idx, resp.hw_context_id,
resp.doorbell_offset);
/* setup interrupt completion per msix index */
- priv->cert_comp = aie4_lookup_cert_comp(ndev, resp.job_complete_msix_idx);
- if (!priv->cert_comp) {
+ cert_comp = aie4_lookup_cert_comp(ndev, resp.job_complete_msix_idx);
+ if (IS_ERR(cert_comp)) {
aie4_msg_destroy_context(ndev, resp.hw_context_id);
- return -EINVAL;
+ return PTR_ERR(cert_comp);
}
priv->hw_ctx_id = resp.hw_context_id;
- hwctx->doorbell_offset = AMDXDNA_INVALID_DOORBELL_OFFSET;
+
+ hwctx->fw_ctx_id = resp.hw_context_id;
+ hwctx->start_col = 0;
+ hwctx->num_col = ndev->total_col;
+
+ /* Set up driver doorbell and return invalid offset to userspace. */
+ mutex_lock(&priv->io_lock);
+ ret = aie4_doorbell_setup(hwctx, &resp);
+ if (ret) {
+ mutex_unlock(&priv->io_lock);
+ aie4_msg_destroy_context(ndev, resp.hw_context_id);
+ aie4_put_cert_comp(cert_comp);
+ priv->hw_ctx_id = CTX_INVALID_ID;
+ hwctx->fw_ctx_id = -1;
+ return ret;
+ }
+ WRITE_ONCE(priv->cert_comp, cert_comp);
+ mutex_unlock(&priv->io_lock);
+ hwctx->doorbell_offset = CTX_INVALID_DOORBELL;
+ wake_up_all(&priv->job_list_wq);
return 0;
}
-static void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx)
+void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags flags)
{
struct amdxdna_client *client = hwctx->client;
struct amdxdna_hwctx_priv *priv = hwctx->priv;
struct amdxdna_dev *xdna = client->xdna;
struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ struct cert_comp *cert_comp;
drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
- aie4_msg_destroy_context(ndev, priv->hw_ctx_id);
- aie4_put_cert_comp(priv->cert_comp);
+ mutex_lock(&priv->io_lock);
+ cert_comp = priv->cert_comp;
+ WRITE_ONCE(priv->cert_comp, NULL);
+ mutex_unlock(&priv->io_lock);
+
+ if (cert_comp)
+ wake_up_all(&cert_comp->waitq);
+
+ if (flags != AIE4_HWCTX_DISCONNECT)
+ aie4_msg_destroy_context(ndev, priv->hw_ctx_id);
+
+ if (cert_comp)
+ aie4_put_cert_comp(cert_comp);
+
+ priv->hw_ctx_id = CTX_INVALID_ID;
+ hwctx->fw_ctx_id = -1;
+ hwctx->doorbell_offset = CTX_INVALID_DOORBELL;
+
+ cancel_work_sync(&priv->job_work);
}
static void aie4_hwctx_umq_fini(struct amdxdna_hwctx *hwctx)
{
if (hwctx->priv && hwctx->priv->umq_bo)
- amdxdna_gem_put_obj(hwctx->priv->umq_bo);
+ drm_gem_object_put(to_gobj(hwctx->priv->umq_bo));
}
static int aie4_hwctx_umq_init(struct amdxdna_hwctx *hwctx)
{
+ const size_t indir_pkts_sz = CTX_MAX_CMDS * HSA_MAX_LEVEL1_INDIRECT_ENTRIES *
+ sizeof(struct host_indirect_packet_data);
+ const size_t pkts_sz = CTX_MAX_CMDS * sizeof(struct host_queue_packet);
struct amdxdna_hwctx_priv *priv = hwctx->priv;
struct amdxdna_dev *xdna = hwctx->client->xdna;
struct amdxdna_gem_obj *umq_bo;
struct host_queue_header *qhdr;
+ u64 data_dev_addr;
+ void *umq_va;
int ret;
+ int i;
+ /* Queue lives in user-allocated BO so device can access it under PASID. */
umq_bo = amdxdna_gem_get_obj(hwctx->client, hwctx->umq_bo_hdl, AMDXDNA_BO_SHARE);
if (!umq_bo) {
XDNA_ERR(xdna, "cannot find umq_bo handle %d", hwctx->umq_bo_hdl);
return -ENOENT;
}
- if (umq_bo->mem.size < sizeof(*qhdr)) {
- XDNA_ERR(xdna, "umq_bo size is too small");
+
+ /* Ensure user BO can hold queue header and direct/indirect packet arrays. */
+ if (umq_bo->mem.size < sizeof(*qhdr) ||
+ (umq_bo->mem.size < sizeof(*qhdr) + pkts_sz + indir_pkts_sz)) {
+ XDNA_ERR(xdna, "umq_bo size %zu is too small",
+ (size_t)umq_bo->mem.size);
ret = -EINVAL;
goto put_umq_bo;
}
- /* get kva address for host queue read index and write index */
- qhdr = amdxdna_gem_vmap(umq_bo);
- if (!qhdr) {
+ umq_va = amdxdna_gem_vmap(umq_bo);
+ if (!umq_va) {
ret = -ENOMEM;
goto put_umq_bo;
}
+ qhdr = umq_va;
priv->umq_bo = umq_bo;
priv->umq_read_index = &qhdr->read_index;
priv->umq_write_index = &qhdr->write_index;
+ /* Lay out direct packets after header, followed by indirect packets. */
+ data_dev_addr = amdxdna_gem_dev_addr(umq_bo) + sizeof(*qhdr);
+ priv->umq_pkts = umq_va + sizeof(*qhdr);
+ priv->umq_indirect_pkts = umq_va + sizeof(*qhdr) + pkts_sz;
+ priv->umq_indirect_pkts_dev_addr = data_dev_addr + pkts_sz;
+
+ /* Clear only the driver-managed header and packet regions. */
+ memset(umq_va, 0, sizeof(*qhdr) + pkts_sz + indir_pkts_sz);
+ priv->write_index = QUEUE_INDEX_START;
+ qhdr->read_index = QUEUE_INDEX_START;
+ qhdr->write_index = QUEUE_INDEX_START;
+ qhdr->version.major = HOST_QUEUE_MAJOR_VERSION;
+ qhdr->version.minor = HOST_QUEUE_MINOR_VERSION;
+ qhdr->capacity = CTX_MAX_CMDS;
+ qhdr->data_address = data_dev_addr;
+ for (i = 0; i < CTX_MAX_CMDS; i++)
+ priv->umq_pkts[i].pkt_header.common_header.opcode = OPCODE_EXEC_BUF;
+ for (i = 0; i < CTX_MAX_CMDS * HSA_MAX_LEVEL1_INDIRECT_ENTRIES; i++) {
+ priv->umq_indirect_pkts[i].header.opcode = OPCODE_EXEC_BUF;
+ priv->umq_indirect_pkts[i].header.count = sizeof(struct exec_buf);
+ priv->umq_indirect_pkts[i].header.distribute = 1;
+ }
+
return 0;
put_umq_bo:
@@ -230,28 +328,52 @@ int aie4_hwctx_init(struct amdxdna_hwctx *hwctx)
{
struct amdxdna_client *client = hwctx->client;
struct amdxdna_dev *xdna = client->xdna;
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
struct amdxdna_hwctx_priv *priv;
int ret;
+ if (!AIE_FEATURE_ON(&ndev->aie, AIE4_HSA_COMMAND))
+ return -EOPNOTSUPP;
+
priv = kzalloc_obj(*priv);
if (!priv)
return -ENOMEM;
hwctx->priv = priv;
+ priv->hwctx = hwctx;
+
+ /* Initialize io_lock guarding cert_comp binding. */
+ mutex_init(&priv->io_lock);
+
+ INIT_LIST_HEAD(&priv->pending_job_list);
+ INIT_LIST_HEAD(&priv->running_job_list);
+ init_waitqueue_head(&priv->job_list_wq);
+ INIT_WORK(&priv->job_work, job_worker);
ret = aie4_hwctx_umq_init(hwctx);
if (ret)
- goto free_priv;
+ goto destroy_lock;
ret = aie4_hwctx_create(hwctx);
if (ret)
goto umq_fini;
- XDNA_DBG(xdna, "hwctx %s init completed", hwctx->name);
+ priv->job_work_q = alloc_ordered_workqueue("aie4_job_%d_%d", 0,
+ client->pid, hwctx->fw_ctx_id);
+ if (!priv->job_work_q) {
+ XDNA_ERR(xdna, "Create job_work_q failed");
+ ret = -ENOMEM;
+ goto destroy_ctx;
+ }
+
+ XDNA_DBG(xdna, "hwctx %d.%d init completed", client->pid, hwctx->fw_ctx_id);
return 0;
+destroy_ctx:
+ aie4_hwctx_destroy(hwctx, AIE4_HWCTX_NORMAL);
umq_fini:
aie4_hwctx_umq_fini(hwctx);
-free_priv:
+destroy_lock:
+ mutex_destroy(&priv->io_lock);
kfree(priv);
hwctx->priv = NULL;
return ret;
@@ -259,8 +381,14 @@ int aie4_hwctx_init(struct amdxdna_hwctx *hwctx)
void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx)
{
- aie4_hwctx_destroy(hwctx);
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+
+ aie4_hwctx_destroy(hwctx, AIE4_HWCTX_ERROR);
+ cancel_work_sync(&priv->job_work);
+ if (priv->job_work_q)
+ destroy_workqueue(priv->job_work_q);
aie4_hwctx_umq_fini(hwctx);
+ mutex_destroy(&priv->io_lock);
kfree(hwctx->priv);
}
@@ -304,10 +432,12 @@ static inline bool check_cmd_done(struct amdxdna_hwctx *hwctx, u64 seq)
int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
{
unsigned long wait_jifs = MAX_SCHEDULE_TIMEOUT;
- struct amdxdna_hwctx_priv *priv = hwctx->priv;
- struct cert_comp *cert_comp = priv->cert_comp;
+ struct cert_comp *cert_comp = aie4_get_cert_comp(hwctx);
long ret;
+ if (!cert_comp)
+ return -EAGAIN;
+
if (timeout)
wait_jifs = msecs_to_jiffies(timeout);
@@ -318,5 +448,7 @@ int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
if (!ret)
ret = -ETIME;
+ aie4_put_cert_comp(cert_comp);
+
return ret <= 0 ? ret : 0;
}
diff --git a/drivers/accel/amdxdna/aie4_host_queue.h b/drivers/accel/amdxdna/aie4_host_queue.h
index 95ebbb714c6f..d2ed2fd65fb1 100644
--- a/drivers/accel/amdxdna/aie4_host_queue.h
+++ b/drivers/accel/amdxdna/aie4_host_queue.h
@@ -6,9 +6,14 @@
#ifndef _AIE4_HOST_QUEUE_H_
#define _AIE4_HOST_QUEUE_H_
+#include <linux/bits.h>
#include <linux/types.h>
#define CTX_MAX_CMDS 32
+#define HSA_MAX_LEVEL1_INDIRECT_ENTRIES 6
+#define QUEUE_INDEX_START 0
+#define HOST_QUEUE_MAJOR_VERSION 1
+#define HOST_QUEUE_MINOR_VERSION 0
/* Host queue header layout. */
struct host_queue_header {
@@ -24,4 +29,64 @@ struct host_queue_header {
__u64 data_address; /* The xdna dev addr for payload. */
} __packed;
+/* Payload for an OPCODE_EXEC_BUF host-queue packet (single command). */
+struct exec_buf {
+ u32 dtrace_buf_host_addr_low;
+ u32 dpu_control_code_host_addr_low;
+ u32 dpu_control_code_host_addr_high;
+ u16 args_len;
+ u16 dtrace_buf_host_addr_high;
+ u32 args_host_addr_low;
+ u32 args_host_addr_high;
+} __packed;
+
+#define OPCODE_EXEC_BUF 1
+#define CHAIN_FLG_LAST_CMD 0
+#define CHAIN_FLG_NOT_LAST_CMD 1
+struct common_header {
+ u16 reserved; /* MBZ. */
+ u8 opcode;
+ u8 chain_flag;
+ u16 count;
+ u8 distribute;
+ u8 indirect;
+} __packed;
+
+struct host_queue_packet_header {
+ struct common_header common_header;
+ u64 completion_signal;
+} __packed;
+
+struct host_queue_packet {
+ struct host_queue_packet_header pkt_header;
+ u32 data[12]; /* total 64-byte packet */
+} __packed;
+
+struct host_indirect_packet_entry {
+ u32 host_addr_low;
+ u32 host_addr_high_uc_index;
+} __packed;
+
+#define HIPE_HOST_ADDR_HIGH_SHIFT 0
+#define HIPE_HOST_ADDR_HIGH_MASK GENMASK(24, 0)
+#define HIPE_UC_INDEX_SHIFT 25
+#define HIPE_UC_INDEX_MASK GENMASK(31, 25)
+
+static inline void hipe_set_host_addr_high(u32 *val, u32 addr_hi)
+{
+ *val &= ~HIPE_HOST_ADDR_HIGH_MASK;
+ *val |= (addr_hi << HIPE_HOST_ADDR_HIGH_SHIFT) & HIPE_HOST_ADDR_HIGH_MASK;
+}
+
+static inline void hipe_set_uc_index(u32 *val, u32 uc_idx)
+{
+ *val &= ~HIPE_UC_INDEX_MASK;
+ *val |= (uc_idx << HIPE_UC_INDEX_SHIFT) & HIPE_UC_INDEX_MASK;
+}
+
+struct host_indirect_packet_data {
+ struct common_header header;
+ struct exec_buf payload;
+} __packed;
+
#endif /* _AIE4_HOST_QUEUE_H_ */
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 9fcdfcc5a15f..3d3301ce11ae 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -8,7 +8,10 @@
#include <linux/device.h>
#include <linux/iopoll.h>
+#include <linux/list.h>
#include <linux/pci.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
#include "aie.h"
#include "aie4_msg_priv.h"
@@ -25,7 +28,20 @@ struct cert_comp {
wait_queue_head_t waitq;
};
+/*
+ * aie4 kernel-submission job states (stored in amdxdna_sched_job priv.aie4.state).
+ * Anonymous enum - the aie4_job_state identifier is already a field-access macro.
+ */
+enum {
+ AIE4_JOB_STATE_INIT,
+ AIE4_JOB_STATE_PENDING,
+ AIE4_JOB_STATE_SUBMITTING,
+ AIE4_JOB_STATE_SUBMITTED,
+ AIE4_JOB_STATE_DONE,
+};
+
struct amdxdna_hwctx_priv {
+ struct amdxdna_hwctx *hwctx;
struct amdxdna_gem_obj *umq_bo;
u64 *umq_read_index;
u64 *umq_write_index;
@@ -33,7 +49,22 @@ struct amdxdna_hwctx_priv {
struct cert_comp *cert_comp;
u32 hw_ctx_id;
+ /* Direct and indirect packet storage aliasing umq_bo. */
+ u64 write_index;
+ struct host_queue_packet *umq_pkts;
+ struct host_indirect_packet_data *umq_indirect_pkts;
+ u64 umq_indirect_pkts_dev_addr;
+ /* Transport doorbell target set by aie4_doorbell_setup(). */
void __iomem *doorbell_addr;
+
+ struct mutex io_lock; /* serialize submit, protect job lists */
+ struct list_head pending_job_list;
+ /* Head of pending_job_list, read locklessly by wait conditions. */
+ struct amdxdna_sched_job *pending_head;
+ struct list_head running_job_list;
+ wait_queue_head_t job_list_wq;
+ struct work_struct job_work;
+ struct workqueue_struct *job_work_q;
};
struct amdxdna_dev_priv {
@@ -107,9 +138,18 @@ int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us);
u32 aie4_msg_pasid(struct amdxdna_client *client);
/* aie4_ctx.c */
+enum aie4_hwctx_flags {
+ AIE4_HWCTX_NORMAL = 0,
+ AIE4_HWCTX_GRACEFUL,
+ AIE4_HWCTX_DISCONNECT, /* sets has_error, do not destroy context */
+ AIE4_HWCTX_ERROR, /* sets has_error, destroy context */
+};
+
int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx);
int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
+int aie4_hwctx_create(struct amdxdna_hwctx *hwctx);
+void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags);
/* aie4_pci.c */
int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev);
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 12/19] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout
2026-10-09 22:53 ` [PATCH V4 12/19] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout David Zhang
@ 2026-10-13 18:41 ` Lizhi Hou
0 siblings, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-13 18:41 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello, Wendy Liang
On 10/9/26 15:53, David Zhang wrote:
> Initialize kernel-mode submission required buffers, workqueue, and
> hardware contexts:
> - Update queue definition that is being used to send requests.
> - Add job workqueue for pending and running jobs.
> - Add mutex protection for each io.
> - Initialize queue with direct and indirect packet, format queue header.
> - Add kernel-mode submission required steps in hwctx create/destroy.
> - Add aie4_get_cert_comp() to safely acquire a reference to the
> per-hwctx completion tracker under io_lock in aie4_cmd_wait() before
> waiting on the queue, preventing race conditions with
> aie4_hwctx_destroy().
>
> Co-developed-by: Max Zhen <max.zhen@amd.com>
> Signed-off-by: Max Zhen <max.zhen@amd.com>
> Co-developed-by: Wendy Liang <wendy.liang@amd.com>
> Signed-off-by: Wendy Liang <wendy.liang@amd.com>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie4_ctx.c | 198 ++++++++++++++++++++----
> drivers/accel/amdxdna/aie4_host_queue.h | 65 ++++++++
> drivers/accel/amdxdna/aie4_pci.h | 40 +++++
> 3 files changed, 270 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
> index 20b725de6ab7..767ba6ecbfc6 100644
> --- a/drivers/accel/amdxdna/aie4_ctx.c
> +++ b/drivers/accel/amdxdna/aie4_ctx.c
> @@ -22,6 +22,13 @@
> #include "amdxdna_mailbox_helper.h"
> #include "amdxdna_pci_drv.h"
>
> +#define CTX_INVALID_ID (~0U)
> +#define CTX_INVALID_DOORBELL AMDXDNA_INVALID_DOORBELL_OFFSET
> +
> +static void job_worker(struct work_struct *work)
> +{
> +}
> +
> static struct cert_comp *aie4_lookup_cert_comp(struct amdxdna_dev_hdl *ndev, u32 msix_idx)
> {
> struct amdxdna_dev *xdna = ndev->aie.xdna;
> @@ -37,8 +44,10 @@ static struct cert_comp *aie4_lookup_cert_comp(struct amdxdna_dev_hdl *ndev, u32
> }
>
> cert_comp = kzalloc_obj(*cert_comp);
> - if (!cert_comp)
> + if (!cert_comp) {
> + ret = -ENOMEM;
> goto unlock;
> + }
>
> cert_comp->ndev = ndev;
> cert_comp->msix_idx = msix_idx;
> @@ -68,7 +77,7 @@ static struct cert_comp *aie4_lookup_cert_comp(struct amdxdna_dev_hdl *ndev, u32
> kfree(cert_comp);
> unlock:
> mutex_unlock(&ndev->cert_comp_lock);
> - return NULL;
> + return ERR_PTR(ret);
> }
>
> static void cert_comp_release(struct kref *kref)
> @@ -76,8 +85,6 @@ static void cert_comp_release(struct kref *kref)
> struct cert_comp *cert_comp = container_of(kref, struct cert_comp, kref);
> struct amdxdna_dev_hdl *ndev = cert_comp->ndev;
>
> - drm_WARN_ON(&ndev->aie.xdna->ddev, !mutex_is_locked(&ndev->cert_comp_lock));
> -
> xa_erase(&ndev->cert_comp_xa, cert_comp->msix_idx);
> aie4_free_notification(cert_comp);
> kfree(cert_comp);
> @@ -85,20 +92,41 @@ static void cert_comp_release(struct kref *kref)
>
> static void aie4_put_cert_comp(struct cert_comp *cert_comp)
> {
> - struct amdxdna_dev_hdl *ndev;
> + struct amdxdna_dev_hdl *ndev = cert_comp->ndev;
>
> - ndev = cert_comp->ndev;
> guard(mutex)(&ndev->cert_comp_lock);
>
> kref_put(&cert_comp->kref, cert_comp_release);
> }
>
> -static int aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context_id)
> +static struct cert_comp *aie4_get_cert_comp(struct amdxdna_hwctx *hwctx)
> +{
> + struct amdxdna_hwctx_priv *priv = hwctx->priv;
> + struct cert_comp *cert_comp;
> +
> + /* Take io_lock to serialize against cert_comp link/unlink. */
> + guard(mutex)(&priv->io_lock);
> +
> + cert_comp = READ_ONCE(priv->cert_comp);
> + if (cert_comp)
> + kref_get(&cert_comp->kref);
> +
> + return cert_comp;
> +}
> +
> +static void aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context_id)
> {
> DECLARE_AIE_MSG(aie4_msg_destroy_hw_context, AIE4_MSG_OP_DESTROY_HW_CONTEXT);
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> + int ret;
> +
> + if (hw_context_id == CTX_INVALID_ID)
> + return;
>
> req.hw_context_id = hw_context_id;
> - return aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> + if (ret)
> + XDNA_WARN(xdna, "destroy ctx id %d failed %d", hw_context_id, ret);
> }
>
> static u8 aie4_parse_priority_to_dev(u32 priority)
> @@ -117,19 +145,20 @@ static u8 aie4_parse_priority_to_dev(u32 priority)
> }
> }
>
> -static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
> +int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
> {
> DECLARE_AIE_MSG(aie4_msg_create_hw_context, AIE4_MSG_OP_CREATE_HW_CONTEXT);
> struct amdxdna_client *client = hwctx->client;
> struct amdxdna_hwctx_priv *priv = hwctx->priv;
> - struct amdxdna_dev *xdna = hwctx->client->xdna;
> + struct amdxdna_dev *xdna = client->xdna;
> struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
> + struct cert_comp *cert_comp;
> int ret;
>
> drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
>
> if (!ndev->partition_id || !hwctx->num_tiles) {
> - XDNA_ERR(xdna, "invalid request partition_id %d, num_tiles %d",
> + XDNA_ERR(xdna, "invalid request partition_id %u, num_tiles %d",
> ndev->partition_id, hwctx->num_tiles);
> return -EINVAL;
> }
> @@ -139,7 +168,6 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
> req.pasid = aie4_msg_pasid(client);
> req.pasid = req.pasid == IOMMU_PASID_INVALID ? 0 : req.pasid;
> req.priority_band = aie4_parse_priority_to_dev(hwctx->qos.priority);
> -
> req.hsa_addr_high = upper_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
> req.hsa_addr_low = lower_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
>
> @@ -153,72 +181,142 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
> }
>
> XDNA_DBG(xdna, "resp msix: %d, ctx id: %d, doorbell: %d",
> - resp.job_complete_msix_idx,
> - resp.hw_context_id,
> + resp.job_complete_msix_idx, resp.hw_context_id,
> resp.doorbell_offset);
>
> /* setup interrupt completion per msix index */
> - priv->cert_comp = aie4_lookup_cert_comp(ndev, resp.job_complete_msix_idx);
> - if (!priv->cert_comp) {
> + cert_comp = aie4_lookup_cert_comp(ndev, resp.job_complete_msix_idx);
> + if (IS_ERR(cert_comp)) {
> aie4_msg_destroy_context(ndev, resp.hw_context_id);
> - return -EINVAL;
> + return PTR_ERR(cert_comp);
> }
>
> priv->hw_ctx_id = resp.hw_context_id;
> - hwctx->doorbell_offset = AMDXDNA_INVALID_DOORBELL_OFFSET;
> +
> + hwctx->fw_ctx_id = resp.hw_context_id;
> + hwctx->start_col = 0;
> + hwctx->num_col = ndev->total_col;
> +
> + /* Set up driver doorbell and return invalid offset to userspace. */
> + mutex_lock(&priv->io_lock);
> + ret = aie4_doorbell_setup(hwctx, &resp);
> + if (ret) {
> + mutex_unlock(&priv->io_lock);
> + aie4_msg_destroy_context(ndev, resp.hw_context_id);
> + aie4_put_cert_comp(cert_comp);
> + priv->hw_ctx_id = CTX_INVALID_ID;
> + hwctx->fw_ctx_id = -1;
> + return ret;
> + }
> + WRITE_ONCE(priv->cert_comp, cert_comp);
> + mutex_unlock(&priv->io_lock);
> + hwctx->doorbell_offset = CTX_INVALID_DOORBELL;
> + wake_up_all(&priv->job_list_wq);
>
> return 0;
> }
>
> -static void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx)
> +void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags flags)
> {
> struct amdxdna_client *client = hwctx->client;
> struct amdxdna_hwctx_priv *priv = hwctx->priv;
> struct amdxdna_dev *xdna = client->xdna;
> struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
> + struct cert_comp *cert_comp;
>
> drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
>
> - aie4_msg_destroy_context(ndev, priv->hw_ctx_id);
> - aie4_put_cert_comp(priv->cert_comp);
> + mutex_lock(&priv->io_lock);
> + cert_comp = priv->cert_comp;
> + WRITE_ONCE(priv->cert_comp, NULL);
> + mutex_unlock(&priv->io_lock);
> +
> + if (cert_comp)
> + wake_up_all(&cert_comp->waitq);
> +
> + if (flags != AIE4_HWCTX_DISCONNECT)
> + aie4_msg_destroy_context(ndev, priv->hw_ctx_id);
> +
> + if (cert_comp)
> + aie4_put_cert_comp(cert_comp);
> +
> + priv->hw_ctx_id = CTX_INVALID_ID;
> + hwctx->fw_ctx_id = -1;
> + hwctx->doorbell_offset = CTX_INVALID_DOORBELL;
> +
> + cancel_work_sync(&priv->job_work);
> }
>
> static void aie4_hwctx_umq_fini(struct amdxdna_hwctx *hwctx)
> {
> if (hwctx->priv && hwctx->priv->umq_bo)
> - amdxdna_gem_put_obj(hwctx->priv->umq_bo);
> + drm_gem_object_put(to_gobj(hwctx->priv->umq_bo));
> }
>
> static int aie4_hwctx_umq_init(struct amdxdna_hwctx *hwctx)
> {
> + const size_t indir_pkts_sz = CTX_MAX_CMDS * HSA_MAX_LEVEL1_INDIRECT_ENTRIES *
> + sizeof(struct host_indirect_packet_data);
> + const size_t pkts_sz = CTX_MAX_CMDS * sizeof(struct host_queue_packet);
> struct amdxdna_hwctx_priv *priv = hwctx->priv;
> struct amdxdna_dev *xdna = hwctx->client->xdna;
> struct amdxdna_gem_obj *umq_bo;
> struct host_queue_header *qhdr;
> + u64 data_dev_addr;
> + void *umq_va;
> int ret;
> + int i;
>
> + /* Queue lives in user-allocated BO so device can access it under PASID. */
> umq_bo = amdxdna_gem_get_obj(hwctx->client, hwctx->umq_bo_hdl, AMDXDNA_BO_SHARE);
> if (!umq_bo) {
> XDNA_ERR(xdna, "cannot find umq_bo handle %d", hwctx->umq_bo_hdl);
> return -ENOENT;
> }
> - if (umq_bo->mem.size < sizeof(*qhdr)) {
> - XDNA_ERR(xdna, "umq_bo size is too small");
> +
> + /* Ensure user BO can hold queue header and direct/indirect packet arrays. */
> + if (umq_bo->mem.size < sizeof(*qhdr) ||
> + (umq_bo->mem.size < sizeof(*qhdr) + pkts_sz + indir_pkts_sz)) {
> + XDNA_ERR(xdna, "umq_bo size %zu is too small",
> + (size_t)umq_bo->mem.size);
> ret = -EINVAL;
> goto put_umq_bo;
> }
>
> - /* get kva address for host queue read index and write index */
> - qhdr = amdxdna_gem_vmap(umq_bo);
> - if (!qhdr) {
> + umq_va = amdxdna_gem_vmap(umq_bo);
> + if (!umq_va) {
> ret = -ENOMEM;
> goto put_umq_bo;
> }
> + qhdr = umq_va;
>
> priv->umq_bo = umq_bo;
> priv->umq_read_index = &qhdr->read_index;
> priv->umq_write_index = &qhdr->write_index;
>
> + /* Lay out direct packets after header, followed by indirect packets. */
> + data_dev_addr = amdxdna_gem_dev_addr(umq_bo) + sizeof(*qhdr);
> + priv->umq_pkts = umq_va + sizeof(*qhdr);
> + priv->umq_indirect_pkts = umq_va + sizeof(*qhdr) + pkts_sz;
> + priv->umq_indirect_pkts_dev_addr = data_dev_addr + pkts_sz;
> +
> + /* Clear only the driver-managed header and packet regions. */
> + memset(umq_va, 0, sizeof(*qhdr) + pkts_sz + indir_pkts_sz);
> + priv->write_index = QUEUE_INDEX_START;
> + qhdr->read_index = QUEUE_INDEX_START;
> + qhdr->write_index = QUEUE_INDEX_START;
> + qhdr->version.major = HOST_QUEUE_MAJOR_VERSION;
> + qhdr->version.minor = HOST_QUEUE_MINOR_VERSION;
> + qhdr->capacity = CTX_MAX_CMDS;
> + qhdr->data_address = data_dev_addr;
> + for (i = 0; i < CTX_MAX_CMDS; i++)
> + priv->umq_pkts[i].pkt_header.common_header.opcode = OPCODE_EXEC_BUF;
> + for (i = 0; i < CTX_MAX_CMDS * HSA_MAX_LEVEL1_INDIRECT_ENTRIES; i++) {
> + priv->umq_indirect_pkts[i].header.opcode = OPCODE_EXEC_BUF;
> + priv->umq_indirect_pkts[i].header.count = sizeof(struct exec_buf);
> + priv->umq_indirect_pkts[i].header.distribute = 1;
> + }
> +
> return 0;
>
> put_umq_bo:
> @@ -230,28 +328,52 @@ int aie4_hwctx_init(struct amdxdna_hwctx *hwctx)
> {
> struct amdxdna_client *client = hwctx->client;
> struct amdxdna_dev *xdna = client->xdna;
> + struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
> struct amdxdna_hwctx_priv *priv;
> int ret;
>
> + if (!AIE_FEATURE_ON(&ndev->aie, AIE4_HSA_COMMAND))
> + return -EOPNOTSUPP;
> +
> priv = kzalloc_obj(*priv);
> if (!priv)
> return -ENOMEM;
> hwctx->priv = priv;
> + priv->hwctx = hwctx;
> +
> + /* Initialize io_lock guarding cert_comp binding. */
> + mutex_init(&priv->io_lock);
> +
> + INIT_LIST_HEAD(&priv->pending_job_list);
> + INIT_LIST_HEAD(&priv->running_job_list);
> + init_waitqueue_head(&priv->job_list_wq);
> + INIT_WORK(&priv->job_work, job_worker);
>
> ret = aie4_hwctx_umq_init(hwctx);
> if (ret)
> - goto free_priv;
> + goto destroy_lock;
>
> ret = aie4_hwctx_create(hwctx);
> if (ret)
> goto umq_fini;
>
> - XDNA_DBG(xdna, "hwctx %s init completed", hwctx->name);
> + priv->job_work_q = alloc_ordered_workqueue("aie4_job_%d_%d", 0,
> + client->pid, hwctx->fw_ctx_id);
> + if (!priv->job_work_q) {
> + XDNA_ERR(xdna, "Create job_work_q failed");
> + ret = -ENOMEM;
> + goto destroy_ctx;
> + }
> +
> + XDNA_DBG(xdna, "hwctx %d.%d init completed", client->pid, hwctx->fw_ctx_id);
> return 0;
>
> +destroy_ctx:
> + aie4_hwctx_destroy(hwctx, AIE4_HWCTX_NORMAL);
> umq_fini:
> aie4_hwctx_umq_fini(hwctx);
> -free_priv:
> +destroy_lock:
> + mutex_destroy(&priv->io_lock);
> kfree(priv);
> hwctx->priv = NULL;
> return ret;
> @@ -259,8 +381,14 @@ int aie4_hwctx_init(struct amdxdna_hwctx *hwctx)
>
> void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx)
> {
> - aie4_hwctx_destroy(hwctx);
> + struct amdxdna_hwctx_priv *priv = hwctx->priv;
> +
> + aie4_hwctx_destroy(hwctx, AIE4_HWCTX_ERROR);
> + cancel_work_sync(&priv->job_work);
> + if (priv->job_work_q)
> + destroy_workqueue(priv->job_work_q);
> aie4_hwctx_umq_fini(hwctx);
> + mutex_destroy(&priv->io_lock);
> kfree(hwctx->priv);
> }
>
> @@ -304,10 +432,12 @@ static inline bool check_cmd_done(struct amdxdna_hwctx *hwctx, u64 seq)
> int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
> {
> unsigned long wait_jifs = MAX_SCHEDULE_TIMEOUT;
> - struct amdxdna_hwctx_priv *priv = hwctx->priv;
> - struct cert_comp *cert_comp = priv->cert_comp;
> + struct cert_comp *cert_comp = aie4_get_cert_comp(hwctx);
> long ret;
>
> + if (!cert_comp)
> + return -EAGAIN;
> +
> if (timeout)
> wait_jifs = msecs_to_jiffies(timeout);
>
> @@ -318,5 +448,7 @@ int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
> if (!ret)
> ret = -ETIME;
>
> + aie4_put_cert_comp(cert_comp);
> +
> return ret <= 0 ? ret : 0;
> }
> diff --git a/drivers/accel/amdxdna/aie4_host_queue.h b/drivers/accel/amdxdna/aie4_host_queue.h
> index 95ebbb714c6f..d2ed2fd65fb1 100644
> --- a/drivers/accel/amdxdna/aie4_host_queue.h
> +++ b/drivers/accel/amdxdna/aie4_host_queue.h
> @@ -6,9 +6,14 @@
> #ifndef _AIE4_HOST_QUEUE_H_
> #define _AIE4_HOST_QUEUE_H_
>
> +#include <linux/bits.h>
> #include <linux/types.h>
>
> #define CTX_MAX_CMDS 32
> +#define HSA_MAX_LEVEL1_INDIRECT_ENTRIES 6
> +#define QUEUE_INDEX_START 0
> +#define HOST_QUEUE_MAJOR_VERSION 1
> +#define HOST_QUEUE_MINOR_VERSION 0
>
> /* Host queue header layout. */
> struct host_queue_header {
> @@ -24,4 +29,64 @@ struct host_queue_header {
> __u64 data_address; /* The xdna dev addr for payload. */
> } __packed;
>
> +/* Payload for an OPCODE_EXEC_BUF host-queue packet (single command). */
> +struct exec_buf {
> + u32 dtrace_buf_host_addr_low;
> + u32 dpu_control_code_host_addr_low;
> + u32 dpu_control_code_host_addr_high;
> + u16 args_len;
> + u16 dtrace_buf_host_addr_high;
> + u32 args_host_addr_low;
> + u32 args_host_addr_high;
> +} __packed;
> +
> +#define OPCODE_EXEC_BUF 1
> +#define CHAIN_FLG_LAST_CMD 0
> +#define CHAIN_FLG_NOT_LAST_CMD 1
> +struct common_header {
> + u16 reserved; /* MBZ. */
> + u8 opcode;
> + u8 chain_flag;
> + u16 count;
> + u8 distribute;
> + u8 indirect;
> +} __packed;
> +
> +struct host_queue_packet_header {
> + struct common_header common_header;
> + u64 completion_signal;
> +} __packed;
> +
> +struct host_queue_packet {
> + struct host_queue_packet_header pkt_header;
> + u32 data[12]; /* total 64-byte packet */
> +} __packed;
> +
> +struct host_indirect_packet_entry {
> + u32 host_addr_low;
> + u32 host_addr_high_uc_index;
> +} __packed;
> +
> +#define HIPE_HOST_ADDR_HIGH_SHIFT 0
> +#define HIPE_HOST_ADDR_HIGH_MASK GENMASK(24, 0)
> +#define HIPE_UC_INDEX_SHIFT 25
> +#define HIPE_UC_INDEX_MASK GENMASK(31, 25)
> +
> +static inline void hipe_set_host_addr_high(u32 *val, u32 addr_hi)
> +{
> + *val &= ~HIPE_HOST_ADDR_HIGH_MASK;
> + *val |= (addr_hi << HIPE_HOST_ADDR_HIGH_SHIFT) & HIPE_HOST_ADDR_HIGH_MASK;
> +}
> +
> +static inline void hipe_set_uc_index(u32 *val, u32 uc_idx)
> +{
> + *val &= ~HIPE_UC_INDEX_MASK;
> + *val |= (uc_idx << HIPE_UC_INDEX_SHIFT) & HIPE_UC_INDEX_MASK;
> +}
> +
> +struct host_indirect_packet_data {
> + struct common_header header;
> + struct exec_buf payload;
> +} __packed;
> +
> #endif /* _AIE4_HOST_QUEUE_H_ */
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index 9fcdfcc5a15f..3d3301ce11ae 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -8,7 +8,10 @@
>
> #include <linux/device.h>
> #include <linux/iopoll.h>
> +#include <linux/list.h>
> #include <linux/pci.h>
> +#include <linux/wait.h>
> +#include <linux/workqueue.h>
>
> #include "aie.h"
> #include "aie4_msg_priv.h"
> @@ -25,7 +28,20 @@ struct cert_comp {
> wait_queue_head_t waitq;
> };
>
> +/*
> + * aie4 kernel-submission job states (stored in amdxdna_sched_job priv.aie4.state).
> + * Anonymous enum - the aie4_job_state identifier is already a field-access macro.
> + */
> +enum {
> + AIE4_JOB_STATE_INIT,
> + AIE4_JOB_STATE_PENDING,
> + AIE4_JOB_STATE_SUBMITTING,
> + AIE4_JOB_STATE_SUBMITTED,
> + AIE4_JOB_STATE_DONE,
> +};
> +
> struct amdxdna_hwctx_priv {
> + struct amdxdna_hwctx *hwctx;
> struct amdxdna_gem_obj *umq_bo;
> u64 *umq_read_index;
> u64 *umq_write_index;
> @@ -33,7 +49,22 @@ struct amdxdna_hwctx_priv {
> struct cert_comp *cert_comp;
> u32 hw_ctx_id;
>
> + /* Direct and indirect packet storage aliasing umq_bo. */
> + u64 write_index;
> + struct host_queue_packet *umq_pkts;
> + struct host_indirect_packet_data *umq_indirect_pkts;
> + u64 umq_indirect_pkts_dev_addr;
> + /* Transport doorbell target set by aie4_doorbell_setup(). */
> void __iomem *doorbell_addr;
> +
> + struct mutex io_lock; /* serialize submit, protect job lists */
> + struct list_head pending_job_list;
> + /* Head of pending_job_list, read locklessly by wait conditions. */
> + struct amdxdna_sched_job *pending_head;
> + struct list_head running_job_list;
> + wait_queue_head_t job_list_wq;
> + struct work_struct job_work;
> + struct workqueue_struct *job_work_q;
> };
>
> struct amdxdna_dev_priv {
> @@ -107,9 +138,18 @@ int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us);
> u32 aie4_msg_pasid(struct amdxdna_client *client);
>
> /* aie4_ctx.c */
> +enum aie4_hwctx_flags {
> + AIE4_HWCTX_NORMAL = 0,
> + AIE4_HWCTX_GRACEFUL,
> + AIE4_HWCTX_DISCONNECT, /* sets has_error, do not destroy context */
> + AIE4_HWCTX_ERROR, /* sets has_error, destroy context */
> +};
> +
> int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
> void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx);
> int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
> +int aie4_hwctx_create(struct amdxdna_hwctx *hwctx);
> +void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags);
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
>
> /* aie4_pci.c */
> int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev);
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 13/19] accel/amdxdna: Prepare for AIE4 command submission
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (11 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 12/19] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-13 18:42 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 14/19] accel/amdxdna: Move HMM invalidate wait into common GEM code David Zhang
` (5 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello, Wendy Liang
Prepare the data structures and completion wait helpers required for
AIE4 command submission:
- Define struct amdxdna_cmd_start_dpu in amdxdna_ctx.h for the
ERT_START_DPU payload.
- Extend union amdxdna_job_priv with an aie4 member for queue list
linkage and job state tracking.
- Implement smp_rmb() ordering and non-sleeping retry in
get_read_index(), returning zero (no completion) when the sample
is still invalid after the retry.
- Add cmd_done_or_unlinked() to wake on completion or on asynchronous
device disconnect and reset, detected via check_cert_comp_linked(),
and record completion, so aie4_cmd_wait() does not re-read state
that can change after the wait.
read_index is written by firmware to host memory, so the wait path
handles these cases:
- A torn or invalid read_index is never reported as a completion.
- -EAGAIN is returned only when the context is disconnected before
completion is seen; the command state and fence are not affected.
- Completion is recorded inside the wait condition, so a context
unlinked and relinked during the wait cannot report a false
completion.
Co-developed-by: Max Zhen <max.zhen@amd.com>
Signed-off-by: Max Zhen <max.zhen@amd.com>
Co-developed-by: Wendy Liang <wendy.liang@amd.com>
Signed-off-by: Wendy Liang <wendy.liang@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_ctx.c | 73 ++++++++++++++++++++---------
drivers/accel/amdxdna/amdxdna_ctx.h | 20 ++++++++
2 files changed, 71 insertions(+), 22 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
index 767ba6ecbfc6..bb126fbae10d 100644
--- a/drivers/accel/amdxdna/aie4_ctx.c
+++ b/drivers/accel/amdxdna/aie4_ctx.c
@@ -399,56 +399,85 @@ static inline bool valid_queue_index(u64 read, u64 write, u32 capacity)
static u64 get_read_index(struct amdxdna_hwctx *hwctx)
{
- u64 wi = READ_ONCE(*hwctx->priv->umq_write_index);
- u64 ri = READ_ONCE(*hwctx->priv->umq_read_index);
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
struct amdxdna_dev *xdna = hwctx->client->xdna;
+ u64 ri, wi;
+
+ /* Sample read_index before write_index to guarantee wi >= ri. */
+ ri = READ_ONCE(*priv->umq_read_index);
+ /* Order the read_index sample before the write_index sample. */
+ smp_rmb();
+ wi = READ_ONCE(priv->write_index);
- /*
- * CERT cannot update read index as uint64 atomically. Driver may read
- * half-updated read index when it has bits in high 32bit. In case read
- * index is not valid, wait for some time and retry once. It should
- * allow CERT to complete the read index update.
- */
+ /* Non-atomic 64-bit counter update by CERT; re-sample once if invalid. */
if (!valid_queue_index(ri, wi, CTX_MAX_CMDS)) {
- XDNA_WARN(xdna, "Invalid index, ri %llu, wi %llu", ri, wi);
- usleep_range(100, 200);
- ri = READ_ONCE(*hwctx->priv->umq_read_index);
+ ri = READ_ONCE(*priv->umq_read_index);
+ /* Order the read_index sample before the write_index sample. */
+ smp_rmb();
+ wi = READ_ONCE(priv->write_index);
if (!valid_queue_index(ri, wi, CTX_MAX_CMDS)) {
- XDNA_ERR(xdna, "Invalid index after retry, ri %llu, wi %llu", ri, wi);
- ri = 0;
+ /* 0 <= any seq: callers always treat it as "not done" and retry. */
+ XDNA_DBG(xdna, "Invalid index, ri %llu, wi %llu", ri, wi);
+ return 0;
}
}
return ri;
}
-static inline bool check_cmd_done(struct amdxdna_hwctx *hwctx, u64 seq)
+/* Verify cert_comp remains linked to detect disconnect or reset. */
+static bool check_cert_comp_linked(struct amdxdna_hwctx *hwctx, struct cert_comp *comp)
{
- u64 read_idx = get_read_index(hwctx);
+ /* READ_ONCE pairs with the link/unlink WRITE_ONCE. */
+ return comp == READ_ONCE(hwctx->priv->cert_comp);
+}
- return read_idx > seq;
+/*
+ * Lockless wait condition: wake on completion or disconnect. Record
+ * completion, so callers do not re-read state that can change after the
+ * wait.
+ */
+static inline bool cmd_done_or_unlinked(struct amdxdna_hwctx *hwctx, u64 seq,
+ struct cert_comp *comp, bool *done)
+{
+ *done = get_read_index(hwctx) > seq;
+ return *done || !check_cert_comp_linked(hwctx, comp);
}
+/*
+ * Return 0 once seq completed, or -EAGAIN if the context is disconnected
+ * before seq completed.
+ */
int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
{
unsigned long wait_jifs = MAX_SCHEDULE_TIMEOUT;
struct cert_comp *cert_comp = aie4_get_cert_comp(hwctx);
+ bool done = false;
long ret;
- if (!cert_comp)
+ if (!cert_comp) {
+ /* Not connected: read_index in host memory is still valid. */
+ if (get_read_index(hwctx) > seq)
+ return 0;
return -EAGAIN;
+ }
if (timeout)
wait_jifs = msecs_to_jiffies(timeout);
ret = wait_event_interruptible_timeout(cert_comp->waitq,
- (check_cmd_done(hwctx, seq)),
+ cmd_done_or_unlinked(hwctx, seq, cert_comp,
+ &done),
wait_jifs);
+ aie4_put_cert_comp(cert_comp);
+ if (ret < 0)
+ return ret;
+ if (done)
+ return 0;
if (!ret)
- ret = -ETIME;
-
- aie4_put_cert_comp(cert_comp);
+ return -ETIME;
- return ret <= 0 ? ret : 0;
+ /* Woken by disconnect before seq completed. */
+ return -EAGAIN;
}
diff --git a/drivers/accel/amdxdna/amdxdna_ctx.h b/drivers/accel/amdxdna/amdxdna_ctx.h
index 9bbc3db4ebde..b3677851d1c5 100644
--- a/drivers/accel/amdxdna/amdxdna_ctx.h
+++ b/drivers/accel/amdxdna/amdxdna_ctx.h
@@ -48,6 +48,18 @@ struct amdxdna_cmd_start_npu {
u32 prop_args[]; /* properties and regular kernel arguments */
};
+/*
+ * struct amdxdna_cmd_start_dpu - interpretation of data payload for
+ * ERT_START_DPU in amdxdna_cmd.
+ */
+struct amdxdna_cmd_start_dpu {
+ u64 dtrace_buffer; /* dtrace buffer address 2 words */
+ u64 instruction_buffer; /* buffer address 2 words */
+ u32 instruction_buffer_size; /* size of buffer in bytes */
+ u16 uc_index; /* microblaze controller index */
+ u16 chained; /* number of following amdxdna_cmd_start_dpu elements */
+};
+
/*
* Interpretation of the beginning of data payload for ERT_CMD_CHAIN in
* amdxdna_cmd. The rest of the payload in amdxdna_cmd is cmd BO handles.
@@ -138,8 +150,14 @@ struct amdxdna_drv_cmd {
};
struct app_health_report;
+
union amdxdna_job_priv {
struct app_health_report *aie2_health;
+ /* aie4 kernel submission: queue linkage + job state */
+ struct {
+ struct list_head list;
+ u32 state;
+ } aie4;
};
struct amdxdna_sched_job {
@@ -162,6 +180,8 @@ struct amdxdna_sched_job {
};
#define aie2_job_health priv.aie2_health
+#define aie4_job_list priv.aie4.list
+#define aie4_job_state priv.aie4.state
static inline u32
amdxdna_cmd_get_op(struct amdxdna_gem_obj *abo)
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 13/19] accel/amdxdna: Prepare for AIE4 command submission
2026-10-09 22:53 ` [PATCH V4 13/19] accel/amdxdna: Prepare for AIE4 command submission David Zhang
@ 2026-10-13 18:42 ` Lizhi Hou
0 siblings, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-13 18:42 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello, Wendy Liang
On 10/9/26 15:53, David Zhang wrote:
> Prepare the data structures and completion wait helpers required for
> AIE4 command submission:
> - Define struct amdxdna_cmd_start_dpu in amdxdna_ctx.h for the
> ERT_START_DPU payload.
> - Extend union amdxdna_job_priv with an aie4 member for queue list
> linkage and job state tracking.
> - Implement smp_rmb() ordering and non-sleeping retry in
> get_read_index(), returning zero (no completion) when the sample
> is still invalid after the retry.
> - Add cmd_done_or_unlinked() to wake on completion or on asynchronous
> device disconnect and reset, detected via check_cert_comp_linked(),
> and record completion, so aie4_cmd_wait() does not re-read state
> that can change after the wait.
>
> read_index is written by firmware to host memory, so the wait path
> handles these cases:
> - A torn or invalid read_index is never reported as a completion.
> - -EAGAIN is returned only when the context is disconnected before
> completion is seen; the command state and fence are not affected.
> - Completion is recorded inside the wait condition, so a context
> unlinked and relinked during the wait cannot report a false
> completion.
>
> Co-developed-by: Max Zhen <max.zhen@amd.com>
> Signed-off-by: Max Zhen <max.zhen@amd.com>
> Co-developed-by: Wendy Liang <wendy.liang@amd.com>
> Signed-off-by: Wendy Liang <wendy.liang@amd.com>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie4_ctx.c | 73 ++++++++++++++++++++---------
> drivers/accel/amdxdna/amdxdna_ctx.h | 20 ++++++++
> 2 files changed, 71 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
> index 767ba6ecbfc6..bb126fbae10d 100644
> --- a/drivers/accel/amdxdna/aie4_ctx.c
> +++ b/drivers/accel/amdxdna/aie4_ctx.c
> @@ -399,56 +399,85 @@ static inline bool valid_queue_index(u64 read, u64 write, u32 capacity)
>
> static u64 get_read_index(struct amdxdna_hwctx *hwctx)
> {
> - u64 wi = READ_ONCE(*hwctx->priv->umq_write_index);
> - u64 ri = READ_ONCE(*hwctx->priv->umq_read_index);
> + struct amdxdna_hwctx_priv *priv = hwctx->priv;
> struct amdxdna_dev *xdna = hwctx->client->xdna;
> + u64 ri, wi;
> +
> + /* Sample read_index before write_index to guarantee wi >= ri. */
> + ri = READ_ONCE(*priv->umq_read_index);
> + /* Order the read_index sample before the write_index sample. */
> + smp_rmb();
> + wi = READ_ONCE(priv->write_index);
>
> - /*
> - * CERT cannot update read index as uint64 atomically. Driver may read
> - * half-updated read index when it has bits in high 32bit. In case read
> - * index is not valid, wait for some time and retry once. It should
> - * allow CERT to complete the read index update.
> - */
> + /* Non-atomic 64-bit counter update by CERT; re-sample once if invalid. */
> if (!valid_queue_index(ri, wi, CTX_MAX_CMDS)) {
> - XDNA_WARN(xdna, "Invalid index, ri %llu, wi %llu", ri, wi);
> - usleep_range(100, 200);
> - ri = READ_ONCE(*hwctx->priv->umq_read_index);
> + ri = READ_ONCE(*priv->umq_read_index);
> + /* Order the read_index sample before the write_index sample. */
> + smp_rmb();
> + wi = READ_ONCE(priv->write_index);
> if (!valid_queue_index(ri, wi, CTX_MAX_CMDS)) {
> - XDNA_ERR(xdna, "Invalid index after retry, ri %llu, wi %llu", ri, wi);
> - ri = 0;
> + /* 0 <= any seq: callers always treat it as "not done" and retry. */
> + XDNA_DBG(xdna, "Invalid index, ri %llu, wi %llu", ri, wi);
> + return 0;
> }
> }
>
> return ri;
> }
>
> -static inline bool check_cmd_done(struct amdxdna_hwctx *hwctx, u64 seq)
> +/* Verify cert_comp remains linked to detect disconnect or reset. */
> +static bool check_cert_comp_linked(struct amdxdna_hwctx *hwctx, struct cert_comp *comp)
> {
> - u64 read_idx = get_read_index(hwctx);
> + /* READ_ONCE pairs with the link/unlink WRITE_ONCE. */
> + return comp == READ_ONCE(hwctx->priv->cert_comp);
> +}
>
> - return read_idx > seq;
> +/*
> + * Lockless wait condition: wake on completion or disconnect. Record
> + * completion, so callers do not re-read state that can change after the
> + * wait.
> + */
> +static inline bool cmd_done_or_unlinked(struct amdxdna_hwctx *hwctx, u64 seq,
> + struct cert_comp *comp, bool *done)
> +{
> + *done = get_read_index(hwctx) > seq;
> + return *done || !check_cert_comp_linked(hwctx, comp);
> }
>
> +/*
> + * Return 0 once seq completed, or -EAGAIN if the context is disconnected
> + * before seq completed.
> + */
> int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
> {
> unsigned long wait_jifs = MAX_SCHEDULE_TIMEOUT;
> struct cert_comp *cert_comp = aie4_get_cert_comp(hwctx);
> + bool done = false;
> long ret;
>
> - if (!cert_comp)
> + if (!cert_comp) {
> + /* Not connected: read_index in host memory is still valid. */
> + if (get_read_index(hwctx) > seq)
> + return 0;
> return -EAGAIN;
> + }
>
> if (timeout)
> wait_jifs = msecs_to_jiffies(timeout);
>
> ret = wait_event_interruptible_timeout(cert_comp->waitq,
> - (check_cmd_done(hwctx, seq)),
> + cmd_done_or_unlinked(hwctx, seq, cert_comp,
> + &done),
> wait_jifs);
> + aie4_put_cert_comp(cert_comp);
>
> + if (ret < 0)
> + return ret;
> + if (done)
> + return 0;
> if (!ret)
> - ret = -ETIME;
> -
> - aie4_put_cert_comp(cert_comp);
> + return -ETIME;
>
> - return ret <= 0 ? ret : 0;
> + /* Woken by disconnect before seq completed. */
> + return -EAGAIN;
> }
> diff --git a/drivers/accel/amdxdna/amdxdna_ctx.h b/drivers/accel/amdxdna/amdxdna_ctx.h
> index 9bbc3db4ebde..b3677851d1c5 100644
> --- a/drivers/accel/amdxdna/amdxdna_ctx.h
> +++ b/drivers/accel/amdxdna/amdxdna_ctx.h
> @@ -48,6 +48,18 @@ struct amdxdna_cmd_start_npu {
> u32 prop_args[]; /* properties and regular kernel arguments */
> };
>
> +/*
> + * struct amdxdna_cmd_start_dpu - interpretation of data payload for
> + * ERT_START_DPU in amdxdna_cmd.
> + */
> +struct amdxdna_cmd_start_dpu {
> + u64 dtrace_buffer; /* dtrace buffer address 2 words */
> + u64 instruction_buffer; /* buffer address 2 words */
> + u32 instruction_buffer_size; /* size of buffer in bytes */
> + u16 uc_index; /* microblaze controller index */
> + u16 chained; /* number of following amdxdna_cmd_start_dpu elements */
> +};
> +
> /*
> * Interpretation of the beginning of data payload for ERT_CMD_CHAIN in
> * amdxdna_cmd. The rest of the payload in amdxdna_cmd is cmd BO handles.
> @@ -138,8 +150,14 @@ struct amdxdna_drv_cmd {
> };
>
> struct app_health_report;
> +
> union amdxdna_job_priv {
> struct app_health_report *aie2_health;
> + /* aie4 kernel submission: queue linkage + job state */
> + struct {
> + struct list_head list;
> + u32 state;
> + } aie4;
> };
>
> struct amdxdna_sched_job {
> @@ -162,6 +180,8 @@ struct amdxdna_sched_job {
> };
>
> #define aie2_job_health priv.aie2_health
> +#define aie4_job_list priv.aie4.list
> +#define aie4_job_state priv.aie4.state
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
>
> static inline u32
> amdxdna_cmd_get_op(struct amdxdna_gem_obj *abo)
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 14/19] accel/amdxdna: Move HMM invalidate wait into common GEM code
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (12 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 13/19] accel/amdxdna: Prepare for AIE4 command submission David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-13 18:45 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 15/19] accel/amdxdna: Make populate_range common for AIE2 and AIE4 David Zhang
` (4 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello, Hayden Laccabue
When a user mapping of a BO is invalidated, the driver must wait for
the BO's reservation fences before the pages are released. AIE2 does
this in aie2_hmm_invalidate() through the .hmm_invalidate callback,
and AIE4 needs the same wait.
Do the wait directly in amdxdna_hmm_invalidate() in amdxdna_gem.c and
remove the .hmm_invalidate callback and aie2_hmm_invalidate(). Devices
that do not attach fences to user BOs return from the wait at once.
Make the wait uninterruptible. With an interruptible wait, a pending
signal, such as SIGKILL during process exit, ends the wait early and
the pages can be freed while the NPU may still access them.
Co-developed-by: Hayden Laccabue <Hayden.Laccabue@amd.com>
Signed-off-by: Hayden Laccabue <Hayden.Laccabue@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie2_ctx.c | 15 ---------------
drivers/accel/amdxdna/aie2_pci.c | 1 -
drivers/accel/amdxdna/aie2_pci.h | 1 -
drivers/accel/amdxdna/amdxdna_gem.c | 14 ++++++++++++--
drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 -
5 files changed, 12 insertions(+), 20 deletions(-)
diff --git a/drivers/accel/amdxdna/aie2_ctx.c b/drivers/accel/amdxdna/aie2_ctx.c
index d927c8c9d557..8c1b29964f8f 100644
--- a/drivers/accel/amdxdna/aie2_ctx.c
+++ b/drivers/accel/amdxdna/aie2_ctx.c
@@ -1277,21 +1277,6 @@ int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
return ret;
}
-void aie2_hmm_invalidate(struct amdxdna_gem_obj *abo,
- unsigned long cur_seq)
-{
- struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
- struct drm_gem_object *gobj = to_gobj(abo);
- long ret;
-
- ret = dma_resv_wait_timeout(gobj->resv, DMA_RESV_USAGE_BOOKKEEP,
- true, MAX_SCHEDULE_TIMEOUT);
- if (!ret)
- XDNA_ERR(xdna, "Failed to wait for bo, ret %ld", ret);
- else if (ret == -ERESTARTSYS)
- XDNA_DBG(xdna, "Wait for bo interrupted by signal");
-}
-
int aie2_hwctx_heap_expand(struct amdxdna_hwctx *hwctx,
struct amdxdna_gem_obj *heap)
{
diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c
index 1b029d33a24b..690ad035463c 100644
--- a/drivers/accel/amdxdna/aie2_pci.c
+++ b/drivers/accel/amdxdna/aie2_pci.c
@@ -1228,7 +1228,6 @@ const struct amdxdna_dev_ops aie2_ops = {
.hwctx_config = aie2_hwctx_config,
.hwctx_sync_debug_bo = aie2_hwctx_sync_debug_bo,
.cmd_submit = aie2_cmd_submit,
- .hmm_invalidate = aie2_hmm_invalidate,
.get_array = aie2_get_array,
.get_dev_revision = aie2_get_dev_rev,
.hwctx_heap_expand = aie2_hwctx_heap_expand,
diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h
index 709e7545c65f..13391275df31 100644
--- a/drivers/accel/amdxdna/aie2_pci.h
+++ b/drivers/accel/amdxdna/aie2_pci.h
@@ -272,7 +272,6 @@ int aie2_hwctx_sync_debug_bo(struct amdxdna_hwctx *hwctx, u32 debug_bo_hdl);
void aie2_hwctx_suspend(struct amdxdna_client *client);
int aie2_hwctx_resume(struct amdxdna_client *client);
int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq);
-void aie2_hmm_invalidate(struct amdxdna_gem_obj *abo, unsigned long cur_seq);
int aie2_hwctx_heap_expand(struct amdxdna_hwctx *hwctx, struct amdxdna_gem_obj *heap);
#endif /* _AIE2_PCI_H_ */
diff --git a/drivers/accel/amdxdna/amdxdna_gem.c b/drivers/accel/amdxdna/amdxdna_gem.c
index f4832337ec31..e1b72cef51bd 100644
--- a/drivers/accel/amdxdna/amdxdna_gem.c
+++ b/drivers/accel/amdxdna/amdxdna_gem.c
@@ -12,6 +12,7 @@
#include <drm/gpu_scheduler.h>
#include <linux/dma-buf.h>
#include <linux/dma-direct.h>
+#include <linux/dma-resv.h>
#include <linux/iosys-map.h>
#include <linux/pagemap.h>
#include <linux/swap.h>
@@ -232,6 +233,7 @@ static bool amdxdna_hmm_invalidate(struct mmu_interval_notifier *mni,
struct amdxdna_umap *mapp = container_of(mni, struct amdxdna_umap, notifier);
struct amdxdna_gem_obj *abo = mapp->abo;
struct amdxdna_dev *xdna;
+ long ret;
if (!mmu_notifier_range_blockable(range))
return false;
@@ -249,8 +251,16 @@ static bool amdxdna_hmm_invalidate(struct mmu_interval_notifier *mni,
mmu_interval_set_seq(&mapp->notifier, cur_seq);
up_write(&xdna->notifier_lock);
- if (xdna->dev_info->ops->hmm_invalidate)
- xdna->dev_info->ops->hmm_invalidate(abo, cur_seq);
+ /*
+ * Wait uninterruptibly. Returning early on a signal would let the
+ * pages be freed while the NPU may still access them. This relies
+ * on job fences signaling in finite time; job timeout detection
+ * and recovery (TDR) for AIE4 will be added in a separate change.
+ */
+ ret = dma_resv_wait_timeout(to_gobj(abo)->resv, DMA_RESV_USAGE_BOOKKEEP,
+ false, MAX_SCHEDULE_TIMEOUT);
+ if (!ret)
+ XDNA_ERR(xdna, "Failed to wait for bo, ret %ld", ret);
if (range->event == MMU_NOTIFY_UNMAP) {
down_write(&xdna->notifier_lock);
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
index 11f46ec738d7..2a1d6b33363c 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -63,7 +63,6 @@ struct amdxdna_dev_ops {
int (*hwctx_config)(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
int (*hwctx_sync_debug_bo)(struct amdxdna_hwctx *hwctx, u32 debug_bo_hdl);
int (*hwctx_heap_expand)(struct amdxdna_hwctx *hwctx, struct amdxdna_gem_obj *heap);
- void (*hmm_invalidate)(struct amdxdna_gem_obj *abo, unsigned long cur_seq);
int (*cmd_submit)(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq);
int (*cmd_wait)(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
int (*get_aie_info)(struct amdxdna_client *client, struct amdxdna_drm_get_info *args);
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 14/19] accel/amdxdna: Move HMM invalidate wait into common GEM code
2026-10-09 22:53 ` [PATCH V4 14/19] accel/amdxdna: Move HMM invalidate wait into common GEM code David Zhang
@ 2026-10-13 18:45 ` Lizhi Hou
0 siblings, 0 replies; 39+ messages in thread
From: Lizhi Hou @ 2026-10-13 18:45 UTC (permalink / raw)
To: David Zhang, quic_jhugo, karol.wachowski, max.zhen, ogabbay,
dri-devel, linux-kernel
Cc: sonal.santan, mario.limonciello, Hayden Laccabue
On 10/9/26 15:53, David Zhang wrote:
> When a user mapping of a BO is invalidated, the driver must wait for
> the BO's reservation fences before the pages are released. AIE2 does
> this in aie2_hmm_invalidate() through the .hmm_invalidate callback,
> and AIE4 needs the same wait.
>
> Do the wait directly in amdxdna_hmm_invalidate() in amdxdna_gem.c and
> remove the .hmm_invalidate callback and aie2_hmm_invalidate(). Devices
> that do not attach fences to user BOs return from the wait at once.
>
> Make the wait uninterruptible. With an interruptible wait, a pending
> signal, such as SIGKILL during process exit, ends the wait early and
> the pages can be freed while the NPU may still access them.
This is a bug fix. Please add "Fixes" tag and change the title to
reflect the fix.
Lizhi
>
> Co-developed-by: Hayden Laccabue <Hayden.Laccabue@amd.com>
> Signed-off-by: Hayden Laccabue <Hayden.Laccabue@amd.com>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie2_ctx.c | 15 ---------------
> drivers/accel/amdxdna/aie2_pci.c | 1 -
> drivers/accel/amdxdna/aie2_pci.h | 1 -
> drivers/accel/amdxdna/amdxdna_gem.c | 14 ++++++++++++--
> drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 -
> 5 files changed, 12 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie2_ctx.c b/drivers/accel/amdxdna/aie2_ctx.c
> index d927c8c9d557..8c1b29964f8f 100644
> --- a/drivers/accel/amdxdna/aie2_ctx.c
> +++ b/drivers/accel/amdxdna/aie2_ctx.c
> @@ -1277,21 +1277,6 @@ int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
> return ret;
> }
>
> -void aie2_hmm_invalidate(struct amdxdna_gem_obj *abo,
> - unsigned long cur_seq)
> -{
> - struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
> - struct drm_gem_object *gobj = to_gobj(abo);
> - long ret;
> -
> - ret = dma_resv_wait_timeout(gobj->resv, DMA_RESV_USAGE_BOOKKEEP,
> - true, MAX_SCHEDULE_TIMEOUT);
> - if (!ret)
> - XDNA_ERR(xdna, "Failed to wait for bo, ret %ld", ret);
> - else if (ret == -ERESTARTSYS)
> - XDNA_DBG(xdna, "Wait for bo interrupted by signal");
> -}
> -
> int aie2_hwctx_heap_expand(struct amdxdna_hwctx *hwctx,
> struct amdxdna_gem_obj *heap)
> {
> diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c
> index 1b029d33a24b..690ad035463c 100644
> --- a/drivers/accel/amdxdna/aie2_pci.c
> +++ b/drivers/accel/amdxdna/aie2_pci.c
> @@ -1228,7 +1228,6 @@ const struct amdxdna_dev_ops aie2_ops = {
> .hwctx_config = aie2_hwctx_config,
> .hwctx_sync_debug_bo = aie2_hwctx_sync_debug_bo,
> .cmd_submit = aie2_cmd_submit,
> - .hmm_invalidate = aie2_hmm_invalidate,
> .get_array = aie2_get_array,
> .get_dev_revision = aie2_get_dev_rev,
> .hwctx_heap_expand = aie2_hwctx_heap_expand,
> diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h
> index 709e7545c65f..13391275df31 100644
> --- a/drivers/accel/amdxdna/aie2_pci.h
> +++ b/drivers/accel/amdxdna/aie2_pci.h
> @@ -272,7 +272,6 @@ int aie2_hwctx_sync_debug_bo(struct amdxdna_hwctx *hwctx, u32 debug_bo_hdl);
> void aie2_hwctx_suspend(struct amdxdna_client *client);
> int aie2_hwctx_resume(struct amdxdna_client *client);
> int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq);
> -void aie2_hmm_invalidate(struct amdxdna_gem_obj *abo, unsigned long cur_seq);
> int aie2_hwctx_heap_expand(struct amdxdna_hwctx *hwctx, struct amdxdna_gem_obj *heap);
>
> #endif /* _AIE2_PCI_H_ */
> diff --git a/drivers/accel/amdxdna/amdxdna_gem.c b/drivers/accel/amdxdna/amdxdna_gem.c
> index f4832337ec31..e1b72cef51bd 100644
> --- a/drivers/accel/amdxdna/amdxdna_gem.c
> +++ b/drivers/accel/amdxdna/amdxdna_gem.c
> @@ -12,6 +12,7 @@
> #include <drm/gpu_scheduler.h>
> #include <linux/dma-buf.h>
> #include <linux/dma-direct.h>
> +#include <linux/dma-resv.h>
> #include <linux/iosys-map.h>
> #include <linux/pagemap.h>
> #include <linux/swap.h>
> @@ -232,6 +233,7 @@ static bool amdxdna_hmm_invalidate(struct mmu_interval_notifier *mni,
> struct amdxdna_umap *mapp = container_of(mni, struct amdxdna_umap, notifier);
> struct amdxdna_gem_obj *abo = mapp->abo;
> struct amdxdna_dev *xdna;
> + long ret;
>
> if (!mmu_notifier_range_blockable(range))
> return false;
> @@ -249,8 +251,16 @@ static bool amdxdna_hmm_invalidate(struct mmu_interval_notifier *mni,
> mmu_interval_set_seq(&mapp->notifier, cur_seq);
> up_write(&xdna->notifier_lock);
>
> - if (xdna->dev_info->ops->hmm_invalidate)
> - xdna->dev_info->ops->hmm_invalidate(abo, cur_seq);
> + /*
> + * Wait uninterruptibly. Returning early on a signal would let the
> + * pages be freed while the NPU may still access them. This relies
> + * on job fences signaling in finite time; job timeout detection
> + * and recovery (TDR) for AIE4 will be added in a separate change.
> + */
> + ret = dma_resv_wait_timeout(to_gobj(abo)->resv, DMA_RESV_USAGE_BOOKKEEP,
> + false, MAX_SCHEDULE_TIMEOUT);
> + if (!ret)
> + XDNA_ERR(xdna, "Failed to wait for bo, ret %ld", ret);
>
> if (range->event == MMU_NOTIFY_UNMAP) {
> down_write(&xdna->notifier_lock);
> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> index 11f46ec738d7..2a1d6b33363c 100644
> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> @@ -63,7 +63,6 @@ struct amdxdna_dev_ops {
> int (*hwctx_config)(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
> int (*hwctx_sync_debug_bo)(struct amdxdna_hwctx *hwctx, u32 debug_bo_hdl);
> int (*hwctx_heap_expand)(struct amdxdna_hwctx *hwctx, struct amdxdna_gem_obj *heap);
> - void (*hmm_invalidate)(struct amdxdna_gem_obj *abo, unsigned long cur_seq);
> int (*cmd_submit)(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq);
> int (*cmd_wait)(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
> int (*get_aie_info)(struct amdxdna_client *client, struct amdxdna_drm_get_info *args);
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 15/19] accel/amdxdna: Make populate_range common for AIE2 and AIE4
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (13 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 14/19] accel/amdxdna: Move HMM invalidate wait into common GEM code David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-09 23:06 ` sashiko-bot
2026-10-09 22:53 ` [PATCH V4 16/19] accel/amdxdna: Implement AIE4 command packet building and submission David Zhang
` (3 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello
When a user mapping of a BO is invalidated, the MMU notifier sets
map_invalid and command submission must fault the range back in
before attaching the job fence. AIE2 does this in
aie2_populate_range(), which AIE4 command submission also needs.
Move aie2_populate_range() from aie2_ctx.c into amdxdna_gem.c as
amdxdna_populate_range(), next to the MMU notifier code, and declare
it in amdxdna_gem.h. No functional change for AIE2.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie2_ctx.c | 75 +----------------------------
drivers/accel/amdxdna/amdxdna_gem.c | 73 ++++++++++++++++++++++++++++
drivers/accel/amdxdna/amdxdna_gem.h | 1 +
3 files changed, 75 insertions(+), 74 deletions(-)
diff --git a/drivers/accel/amdxdna/aie2_ctx.c b/drivers/accel/amdxdna/aie2_ctx.c
index 8c1b29964f8f..05ed71e641c3 100644
--- a/drivers/accel/amdxdna/aie2_ctx.c
+++ b/drivers/accel/amdxdna/aie2_ctx.c
@@ -1105,79 +1105,6 @@ int aie2_hwctx_sync_debug_bo(struct amdxdna_hwctx *hwctx, u32 debug_bo_hdl)
return ret;
}
-static int aie2_populate_range(struct amdxdna_gem_obj *abo)
-{
- struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
- struct amdxdna_umap *mapp;
- unsigned long timeout;
- struct mm_struct *mm;
- bool found;
- int ret;
-
- timeout = msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
-again:
- found = false;
- down_write(&xdna->notifier_lock);
- list_for_each_entry(mapp, &abo->mem.umap_list, node) {
- /*
- * Skip entries that have already been unmapped.
- *
- * If userspace unmaps the address and later submits I/O using
- * it, the IOMMU will reject the access and report a fault.
- * Ignore such entries here.
- */
- if (mapp->unmapped)
- continue;
-
- if (mapp->invalid && kref_get_unless_zero(&mapp->refcnt)) {
- found = true;
- break;
- }
- }
-
- if (!found) {
- /*
- * This also covers the case where all mappings have been
- * removed. There are no invalid mappings left to process.
- * Any subsequent I/O using the unmapped address will be
- * rejected by the IOMMU.
- */
- abo->mem.map_invalid = false;
- up_write(&xdna->notifier_lock);
- return 0;
- }
-
- up_write(&xdna->notifier_lock);
-
- mm = mapp->notifier.mm;
- if (!mmget_not_zero(mm)) {
- amdxdna_umap_put(mapp);
- return -EFAULT;
- }
-
- ret = hmm_range_fault_unlocked_timeout(&mapp->range, timeout);
- if (ret)
- goto put_mm;
-
- down_write(&xdna->notifier_lock);
- if (mmu_interval_read_retry(&mapp->notifier, mapp->range.notifier_seq)) {
- up_write(&xdna->notifier_lock);
- amdxdna_umap_put(mapp);
- mmput(mm);
- goto again;
- }
- mapp->invalid = false;
- up_write(&xdna->notifier_lock);
- amdxdna_umap_put(mapp);
- mmput(mm);
- goto again;
-
-put_mm:
- amdxdna_umap_put(mapp);
- mmput(mm);
- return ret == -EBUSY ? -ETIME : ret;
-}
-
int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq)
{
struct amdxdna_dev *xdna = hwctx->client->xdna;
@@ -1237,7 +1164,7 @@ int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
goto cleanup_job;
}
- ret = aie2_populate_range(abo);
+ ret = amdxdna_populate_range(abo);
if (ret)
goto cleanup_job;
goto retry;
diff --git a/drivers/accel/amdxdna/amdxdna_gem.c b/drivers/accel/amdxdna/amdxdna_gem.c
index e1b72cef51bd..320604ec157f 100644
--- a/drivers/accel/amdxdna/amdxdna_gem.c
+++ b/drivers/accel/amdxdna/amdxdna_gem.c
@@ -337,6 +337,79 @@ void amdxdna_umap_put(struct amdxdna_umap *mapp)
kref_put(&mapp->refcnt, amdxdna_umap_release);
}
+int amdxdna_populate_range(struct amdxdna_gem_obj *abo)
+{
+ struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
+ struct amdxdna_umap *mapp;
+ unsigned long timeout;
+ struct mm_struct *mm;
+ bool found;
+ int ret;
+
+ timeout = msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
+again:
+ found = false;
+ down_write(&xdna->notifier_lock);
+ list_for_each_entry(mapp, &abo->mem.umap_list, node) {
+ /*
+ * Skip entries that have already been unmapped.
+ *
+ * If userspace unmaps the address and later submits I/O using
+ * it, the IOMMU will reject the access and report a fault.
+ * Ignore such entries here.
+ */
+ if (mapp->unmapped)
+ continue;
+
+ if (mapp->invalid && kref_get_unless_zero(&mapp->refcnt)) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found) {
+ /*
+ * This also covers the case where all mappings have been
+ * removed. There are no invalid mappings left to process.
+ * Any subsequent I/O using the unmapped address will be
+ * rejected by the IOMMU.
+ */
+ abo->mem.map_invalid = false;
+ up_write(&xdna->notifier_lock);
+ return 0;
+ }
+
+ up_write(&xdna->notifier_lock);
+
+ mm = mapp->notifier.mm;
+ if (!mmget_not_zero(mm)) {
+ amdxdna_umap_put(mapp);
+ return -EFAULT;
+ }
+
+ ret = hmm_range_fault_unlocked_timeout(&mapp->range, timeout);
+ if (ret)
+ goto put_mm;
+
+ down_write(&xdna->notifier_lock);
+ if (mmu_interval_read_retry(&mapp->notifier, mapp->range.notifier_seq)) {
+ up_write(&xdna->notifier_lock);
+ amdxdna_umap_put(mapp);
+ mmput(mm);
+ goto again;
+ }
+ mapp->invalid = false;
+ up_write(&xdna->notifier_lock);
+ amdxdna_umap_put(mapp);
+ mmput(mm);
+ goto again;
+
+put_mm:
+ amdxdna_umap_put(mapp);
+ mmput(mm);
+ return ret == -EBUSY ? -ETIME : ret;
+}
+
static void amdxdna_hmm_unreg_work(struct work_struct *work)
{
struct amdxdna_gem_obj *abo = container_of(work, struct amdxdna_gem_obj,
diff --git a/drivers/accel/amdxdna/amdxdna_gem.h b/drivers/accel/amdxdna/amdxdna_gem.h
index 9b4aa21a37c9..977548e19ae4 100644
--- a/drivers/accel/amdxdna/amdxdna_gem.h
+++ b/drivers/accel/amdxdna/amdxdna_gem.h
@@ -103,6 +103,7 @@ static inline u64 amdxdna_obj_dma_addr(struct amdxdna_gem_obj *abo)
}
void amdxdna_umap_put(struct amdxdna_umap *mapp);
+int amdxdna_populate_range(struct amdxdna_gem_obj *abo);
void amdxdna_gem_heap_free(struct amdxdna_client *client, struct amdxdna_gem_obj *abo);
struct drm_gem_object *
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 15/19] accel/amdxdna: Make populate_range common for AIE2 and AIE4
2026-10-09 22:53 ` [PATCH V4 15/19] accel/amdxdna: Make populate_range common for AIE2 and AIE4 David Zhang
@ 2026-10-09 23:06 ` sashiko-bot
0 siblings, 0 replies; 39+ messages in thread
From: sashiko-bot @ 2026-10-09 23:06 UTC (permalink / raw)
To: David Zhang; +Cc: dri-devel
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/amdxdna: data race on hmm_range during concurrent faulting
- [High] mm: cross-process mmap_lock dependency blocks NPU job submission
--
commit c2a130c1477d63bd08139e79291eca214fcf225a
Author: David Zhang <yidong.zhang@amd.com>
accel/amdxdna: Make populate_range common for AIE2 and AIE4
This commit moves aie2_populate_range() from aie2_ctx.c into amdxdna_gem.c
as amdxdna_populate_range(), making it common for both AIE2 and AIE4
command submissions.
> diff --git a/drivers/accel/amdxdna/amdxdna_gem.c b/drivers/accel/amdxdna/amdxdna_gem.c
> index e1b72cef51bdf..320604ec157f7 100644
> --- a/drivers/accel/amdxdna/amdxdna_gem.c
> +++ b/drivers/accel/amdxdna/amdxdna_gem.c
[ ... ]
> @@ -337,6 +337,79 @@ void amdxdna_umap_put(struct amdxdna_umap *mapp)
> kref_put(&mapp->refcnt, amdxdna_umap_release);
> }
>
> +int amdxdna_populate_range(struct amdxdna_gem_obj *abo)
> +{
> + struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
> + struct amdxdna_umap *mapp;
> + unsigned long timeout;
> + struct mm_struct *mm;
> + bool found;
> + int ret;
> +
> + timeout = msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
> +again:
> + found = false;
> + down_write(&xdna->notifier_lock);
> + list_for_each_entry(mapp, &abo->mem.umap_list, node) {
[Severity: High]
Does this code iterate over all mappings across all processes without
filtering by the current process?
If an unprivileged process imports a shared dmabuf, maps it, and holds its
mmap_write_lock indefinitely (e.g., via userfaultfd or FUSE), it could cause
this function to block indefinitely when attempting to acquire the
mmap_read_lock for that other process's mm.
Could this result in a denial of service by permanently blocking job
submission for the process that exported the dmabuf?
> + /*
> + * Skip entries that have already been unmapped.
> + *
> + * If userspace unmaps the address and later submits I/O using
> + * it, the IOMMU will reject the access and report a fault.
> + * Ignore such entries here.
> + */
> + if (mapp->unmapped)
> + continue;
> +
> + if (mapp->invalid && kref_get_unless_zero(&mapp->refcnt)) {
> + found = true;
> + break;
> + }
> + }
> +
> + if (!found) {
[ ... ]
> + if (!mmget_not_zero(mm)) {
> + amdxdna_umap_put(mapp);
> + return -EFAULT;
> + }
> +
> + ret = hmm_range_fault_unlocked_timeout(&mapp->range, timeout);
[Severity: High]
Can multiple concurrent job submissions on the same GEM object cause a data
race here?
When multiple hardware contexts submit jobs referencing the same GEM object
with invalidated memory mappings, aie2_cmd_submit() drops GEM reservations
and notifier_lock before calling amdxdna_populate_range(). Because
mapp->invalid remains true until the fault is completed, concurrent
submissions will find the exact same amdxdna_umap object and invoke
hmm_range_fault_unlocked_timeout() simultaneously on the identical
&mapp->range structure.
The HMM API requires struct hmm_range to be thread-local or synchronized by
the caller. The internal mmap_read_lock only protects the VMA, not the
hmm_range struct itself.
Could these unsynchronized writes to range->notifier_seq and the
range->hmm_pfns array break the mmu_interval_read_retry() logic, circumvent
MMU invalidations, or lead to memory corruption?
> + if (ret)
> + goto put_mm;
> +
> + down_write(&xdna->notifier_lock);
> + if (mmu_interval_read_retry(&mapp->notifier, mapp->range.notifier_seq)) {
> + up_write(&xdna->notifier_lock);
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009225343.3079074-1-yidong.zhang@amd.com?part=15
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 16/19] accel/amdxdna: Implement AIE4 command packet building and submission
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (14 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 15/19] accel/amdxdna: Make populate_range common for AIE2 and AIE4 David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-09 22:53 ` [PATCH V4 17/19] accel/amdxdna: Enable AIE4 firmware logging to DRAM David Zhang
` (2 subsequent siblings)
18 siblings, 0 replies; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello, Wendy Liang
Implement kernel-mode command submission and hardware queue packet
assembly for AIE4:
- Add aie4_cmd_submit() to validate incoming command buffers, reserve
GEM fences, serialize submissions via the context pending list, and
dispatch to the hardware queue.
- Build direct and indirect packets with fill_direct_pkt() and
fill_indirect_pkt().
- Allocate a unique fence timeline context per job, and return
KBUILD_MODNAME as the fence timeline name.
- Add .hwctx_stop callback to struct amdxdna_dev_ops and invoke it,
with dev_lock held, before synchronize_srcu() in
amdxdna_hwctx_destroy_rcu() and amdxdna_hwctx_remove_all().
- Return -ENODEV from aie4_cmd_wait() when the context is in error,
so waiters fail instead of retrying a lost context.
- Hold references to sub-command BOs in chained submissions until job
release to prevent use-after-free and DMA writeback to freed memory.
- Pre-validate all sub-command BOs and payloads before dispatching
packets to the hardware queue.
- Lock and fence command BOs, including chained sub-command BOs,
together with the argument BOs.
- Repopulate BOs with invalidated user mappings with
amdxdna_populate_range() before attaching the job fence, retrying
until all mappings are valid.
Stop the hardware context when a running job times out. The job and
the jobs queued behind it are aborted with -ECANCELED, so job fences
published to dma_resv are signaled in finite time.
Co-developed-by: Max Zhen <max.zhen@amd.com>
Signed-off-by: Max Zhen <max.zhen@amd.com>
Co-developed-by: Wendy Liang <wendy.liang@amd.com>
Signed-off-by: Wendy Liang <wendy.liang@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_ctx.c | 801 +++++++++++++++++++++++-
drivers/accel/amdxdna/aie4_pci.c | 4 +
drivers/accel/amdxdna/aie4_pci.h | 4 +
drivers/accel/amdxdna/amdxdna_ctx.c | 25 +-
drivers/accel/amdxdna/amdxdna_ctx.h | 6 +-
drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 +
6 files changed, 820 insertions(+), 21 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
index bb126fbae10d..43d26454be6c 100644
--- a/drivers/accel/amdxdna/aie4_ctx.c
+++ b/drivers/accel/amdxdna/aie4_ctx.c
@@ -9,6 +9,7 @@
#include <drm/drm_gem_shmem_helper.h>
#include <drm/drm_print.h>
#include <drm/gpu_scheduler.h>
+#include <linux/hmm.h>
#include <linux/iommu.h>
#include <linux/types.h>
@@ -24,10 +25,9 @@
#define CTX_INVALID_ID (~0U)
#define CTX_INVALID_DOORBELL AMDXDNA_INVALID_DOORBELL_OFFSET
+#define AIE4_JOB_TIMEOUT_MS 2000
-static void job_worker(struct work_struct *work)
-{
-}
+static void job_worker(struct work_struct *work);
static struct cert_comp *aie4_lookup_cert_comp(struct amdxdna_dev_hdl *ndev, u32 msix_idx)
{
@@ -208,6 +208,7 @@ int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
hwctx->fw_ctx_id = -1;
return ret;
}
+ WRITE_ONCE(priv->has_error, false);
WRITE_ONCE(priv->cert_comp, cert_comp);
mutex_unlock(&priv->io_lock);
hwctx->doorbell_offset = CTX_INVALID_DOORBELL;
@@ -216,6 +217,17 @@ int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
return 0;
}
+/* Linked cert_comp acts as connected sentinel for submit waiters. */
+static bool aie4_hwctx_connected(struct amdxdna_hwctx *hwctx)
+{
+ return !!READ_ONCE(hwctx->priv->cert_comp);
+}
+
+static bool aie4_hwctx_has_error(struct amdxdna_hwctx *hwctx)
+{
+ return READ_ONCE(hwctx->priv->has_error);
+}
+
void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags flags)
{
struct amdxdna_client *client = hwctx->client;
@@ -223,10 +235,16 @@ void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags flags
struct amdxdna_dev *xdna = client->xdna;
struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
struct cert_comp *cert_comp;
+ bool has_error = false;
drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+ if (flags == AIE4_HWCTX_DISCONNECT || flags == AIE4_HWCTX_ERROR)
+ has_error = true;
+
mutex_lock(&priv->io_lock);
+ if (has_error)
+ WRITE_ONCE(priv->has_error, true);
cert_comp = priv->cert_comp;
WRITE_ONCE(priv->cert_comp, NULL);
mutex_unlock(&priv->io_lock);
@@ -234,6 +252,9 @@ void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags flags
if (cert_comp)
wake_up_all(&cert_comp->waitq);
+ if (has_error)
+ wake_up_all(&priv->job_list_wq);
+
if (flags != AIE4_HWCTX_DISCONNECT)
aie4_msg_destroy_context(ndev, priv->hw_ctx_id);
@@ -244,7 +265,9 @@ void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags flags
hwctx->fw_ctx_id = -1;
hwctx->doorbell_offset = CTX_INVALID_DOORBELL;
- cancel_work_sync(&priv->job_work);
+ /* Skip cancel_work_sync on error so worker can abort in-flight jobs. */
+ if (!has_error)
+ cancel_work_sync(&priv->job_work);
}
static void aie4_hwctx_umq_fini(struct amdxdna_hwctx *hwctx)
@@ -379,14 +402,25 @@ int aie4_hwctx_init(struct amdxdna_hwctx *hwctx)
return ret;
}
-void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx)
+void aie4_hwctx_stop(struct amdxdna_hwctx *hwctx)
{
struct amdxdna_hwctx_priv *priv = hwctx->priv;
+ if (priv->hw_ctx_id == CTX_INVALID_ID)
+ return;
+
+ /* Mark error to drain running jobs and unlink cert_comp to wake waiters. */
aie4_hwctx_destroy(hwctx, AIE4_HWCTX_ERROR);
- cancel_work_sync(&priv->job_work);
- if (priv->job_work_q)
+}
+
+void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+
+ if (priv->job_work_q) {
+ aie4_hwctx_wait_for_running(hwctx);
destroy_workqueue(priv->job_work_q);
+ }
aie4_hwctx_umq_fini(hwctx);
mutex_destroy(&priv->io_lock);
kfree(hwctx->priv);
@@ -445,8 +479,8 @@ static inline bool cmd_done_or_unlinked(struct amdxdna_hwctx *hwctx, u64 seq,
}
/*
- * Return 0 once seq completed, or -EAGAIN if the context is disconnected
- * before seq completed.
+ * Return 0 once seq completed, -ENODEV if the context is lost, or -EAGAIN
+ * if it is suspended by power management before seq completed.
*/
int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
{
@@ -459,7 +493,7 @@ int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
/* Not connected: read_index in host memory is still valid. */
if (get_read_index(hwctx) > seq)
return 0;
- return -EAGAIN;
+ return aie4_hwctx_has_error(hwctx) ? -ENODEV : -EAGAIN;
}
if (timeout)
@@ -479,5 +513,750 @@ int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
return -ETIME;
/* Woken by disconnect before seq completed. */
- return -EAGAIN;
+ return aie4_hwctx_has_error(hwctx) ? -ENODEV : -EAGAIN;
+}
+
+/* ---- kernel-mode submission (driver fills the queue and rings doorbell) ---- */
+
+/* Publish a command to CERT and return the assigned command sequence (slot). */
+static u64 publish_cmd(struct amdxdna_hwctx *hwctx)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+ u64 wi = priv->write_index;
+
+ /* Paired with the lockless READ_ONCE() readers of write_index. */
+ WRITE_ONCE(priv->write_index, wi + 1);
+ /* Order the packet-slot writes before CERT sees the new write_index. */
+ wmb();
+ WRITE_ONCE(*priv->umq_write_index, wi + 1);
+ return wi;
+}
+
+/*
+ * Return 0 once seq completed, -EAGAIN on disconnect, -ETIME on timeout,
+ * -ERESTARTSYS on signal.
+ */
+static int wait_till_seq_completed(struct amdxdna_hwctx *hwctx, u64 seq,
+ unsigned long timeout)
+{
+ struct cert_comp *cert_comp;
+ bool done = false;
+ long ret;
+
+ /* Not connected: read_index in host memory is still valid. */
+ cert_comp = aie4_get_cert_comp(hwctx);
+ if (!cert_comp)
+ return get_read_index(hwctx) > seq ? 0 : -EAGAIN;
+
+ /* Wait for queue slot; freezable for suspend, interruptible for signals. */
+ ret = wait_event_freezable_timeout(cert_comp->waitq,
+ cmd_done_or_unlinked(hwctx, seq, cert_comp,
+ &done),
+ timeout);
+ aie4_put_cert_comp(cert_comp);
+ if (ret < 0)
+ return ret;
+ if (done)
+ return 0;
+
+ return ret ? -EAGAIN : -ETIME;
+}
+
+static int wait_till_connected_hsa_not_full(struct amdxdna_hwctx *hwctx)
+{
+ struct amdxdna_dev *xdna = hwctx->client->xdna;
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+ u64 wi = READ_ONCE(priv->write_index);
+ bool hsa_not_full = !!(wi < CTX_MAX_CMDS);
+ int ret;
+
+ do {
+ mutex_unlock(&priv->io_lock);
+ if (!hsa_not_full) {
+ ret = wait_till_seq_completed(hwctx, wi - CTX_MAX_CMDS,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret && ret != -EAGAIN) {
+ mutex_lock(&priv->io_lock);
+ return ret;
+ }
+ if (!ret)
+ hsa_not_full = true;
+ }
+ ret = wait_event_freezable(priv->job_list_wq,
+ aie4_hwctx_connected(hwctx) ||
+ aie4_hwctx_has_error(hwctx));
+ mutex_lock(&priv->io_lock);
+ if (ret)
+ return ret;
+ if (aie4_hwctx_has_error(hwctx)) {
+ XDNA_DBG(xdna, "ctx %s in error; unwinding -ENODEV",
+ hwctx->name);
+ return -ENODEV;
+ }
+ } while (!hsa_not_full || !aie4_hwctx_connected(hwctx));
+
+ return 0;
+}
+
+static int fill_indirect_pkt(struct amdxdna_hwctx_priv *priv, u64 slot_idx,
+ u32 total_slots, struct amdxdna_cmd_start_dpu *dpu,
+ u16 entries)
+{
+ struct host_queue_packet *pkt = &priv->umq_pkts[slot_idx];
+ struct host_indirect_packet_entry *hipe =
+ (struct host_indirect_packet_entry *)(pkt->data);
+ u16 i;
+
+ if (!entries || entries > HSA_MAX_LEVEL1_INDIRECT_ENTRIES) {
+ XDNA_ERR(priv->hwctx->client->xdna, "Invalid indirect entries %u", entries);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < entries; i++, dpu++, hipe++) {
+ struct host_indirect_packet_data *hipd;
+ u64 indirect_pkt_dev_addr;
+ u32 uci = READ_ONCE(dpu->uc_index);
+ u64 dtrace_buf = READ_ONCE(dpu->dtrace_buffer);
+ u64 inst_buf = READ_ONCE(dpu->instruction_buffer);
+ u32 idx;
+
+ /* Validate uc_index against indirect packet bounds before publication. */
+ if (uci >= HSA_MAX_LEVEL1_INDIRECT_ENTRIES) {
+ XDNA_ERR(priv->hwctx->client->xdna, "Invalid uc index %d", uci);
+ return -EINVAL;
+ }
+ if (upper_32_bits(dtrace_buf) > U16_MAX) {
+ XDNA_ERR(priv->hwctx->client->xdna,
+ "Invalid dtrace buffer address 0x%llx", dtrace_buf);
+ return -EINVAL;
+ }
+ idx = uci * total_slots + slot_idx;
+ hipd = &priv->umq_indirect_pkts[idx];
+ indirect_pkt_dev_addr = priv->umq_indirect_pkts_dev_addr +
+ sizeof(struct host_indirect_packet_data) * idx;
+
+ /* Point the indirect entry at the indirect packet. */
+ hipe->host_addr_low = lower_32_bits(indirect_pkt_dev_addr);
+ hipe_set_host_addr_high(&hipe->host_addr_high_uc_index,
+ upper_32_bits(indirect_pkt_dev_addr));
+ hipe_set_uc_index(&hipe->host_addr_high_uc_index, uci);
+
+ /* Fill in the indirect packet. */
+ hipd->payload.dpu_control_code_host_addr_low =
+ lower_32_bits(inst_buf);
+ hipd->payload.dpu_control_code_host_addr_high =
+ upper_32_bits(inst_buf);
+ hipd->payload.dtrace_buf_host_addr_low =
+ lower_32_bits(dtrace_buf);
+ hipd->payload.dtrace_buf_host_addr_high =
+ lower_16_bits(upper_32_bits(dtrace_buf));
+ }
+ pkt->pkt_header.common_header.distribute = 1;
+ pkt->pkt_header.common_header.indirect = 1;
+ pkt->pkt_header.common_header.count = entries * sizeof(*hipe);
+ return 0;
+}
+
+static int fill_direct_pkt(struct amdxdna_hwctx_priv *priv, u64 slot_idx,
+ struct amdxdna_cmd_start_dpu *dpu)
+{
+ struct host_queue_packet *pkt = &priv->umq_pkts[slot_idx];
+ struct exec_buf *ebuf = (struct exec_buf *)(pkt->data);
+ u64 dtrace_buf = READ_ONCE(dpu->dtrace_buffer);
+ u64 inst_buf = READ_ONCE(dpu->instruction_buffer);
+
+ if (upper_32_bits(dtrace_buf) > U16_MAX) {
+ XDNA_ERR(priv->hwctx->client->xdna,
+ "Invalid dtrace buffer address 0x%llx", dtrace_buf);
+ return -EINVAL;
+ }
+
+ memset(pkt->data, 0, sizeof(pkt->data));
+ ebuf->dpu_control_code_host_addr_low = lower_32_bits(inst_buf);
+ ebuf->dpu_control_code_host_addr_high = upper_32_bits(inst_buf);
+ ebuf->dtrace_buf_host_addr_low = lower_32_bits(dtrace_buf);
+ ebuf->dtrace_buf_host_addr_high = lower_16_bits(upper_32_bits(dtrace_buf));
+ pkt->pkt_header.common_header.distribute = 0;
+ pkt->pkt_header.common_header.indirect = 0;
+ pkt->pkt_header.common_header.count = sizeof(*ebuf);
+ return 0;
+}
+
+static int validate_cmd_abo(struct amdxdna_dev *xdna, struct amdxdna_gem_obj *cmd_abo,
+ struct amdxdna_cmd_start_dpu **dpu_out, u16 *chained_cnt)
+{
+ struct amdxdna_cmd_start_dpu *dpu;
+ u32 payload_size;
+ u16 chained;
+ u32 op;
+ u16 i;
+
+ op = amdxdna_cmd_get_op(cmd_abo);
+ if (op != ERT_START_DPU) {
+ XDNA_ERR(xdna, "Invalid exec buf op, %d", op);
+ return -EINVAL;
+ }
+
+ dpu = amdxdna_cmd_get_payload(cmd_abo, &payload_size);
+ if (!dpu || payload_size < sizeof(*dpu)) {
+ XDNA_ERR(xdna, "Invalid DPU payload, size %u", payload_size);
+ return -EINVAL;
+ }
+ chained = READ_ONCE(dpu->chained);
+ if (chained >= HSA_MAX_LEVEL1_INDIRECT_ENTRIES ||
+ payload_size < (u32)(chained + 1) * sizeof(*dpu)) {
+ XDNA_ERR(xdna, "Invalid DPU chained entries %u, payload %u",
+ chained, payload_size);
+ return -EINVAL;
+ }
+
+ if (!chained) {
+ u64 dtrace_buf = READ_ONCE(dpu->dtrace_buffer);
+
+ if (upper_32_bits(dtrace_buf) > U16_MAX) {
+ XDNA_ERR(xdna, "Invalid dtrace buffer address 0x%llx", dtrace_buf);
+ return -EINVAL;
+ }
+ } else {
+ for (i = 0; i <= chained; i++) {
+ u32 uci = READ_ONCE(dpu[i].uc_index);
+ u64 dtrace_buf = READ_ONCE(dpu[i].dtrace_buffer);
+
+ if (uci >= HSA_MAX_LEVEL1_INDIRECT_ENTRIES) {
+ XDNA_ERR(xdna, "Invalid uc index %u", uci);
+ return -EINVAL;
+ }
+ if (upper_32_bits(dtrace_buf) > U16_MAX) {
+ XDNA_ERR(xdna, "Invalid dtrace buffer address 0x%llx", dtrace_buf);
+ return -EINVAL;
+ }
+ }
+ }
+
+ if (dpu_out)
+ *dpu_out = dpu;
+ if (chained_cnt)
+ *chained_cnt = chained;
+
+ return 0;
+}
+
+/* Build and submit one HSA command into the user host queue. Holds io_lock. */
+static int submit_one_cmd(struct amdxdna_hwctx *hwctx,
+ struct amdxdna_gem_obj *cmd_abo, bool last_of_chain,
+ u64 *seq)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+ struct amdxdna_dev *xdna = hwctx->client->xdna;
+ struct amdxdna_cmd_start_dpu *dpu;
+ struct host_queue_packet *pkt;
+ u64 slot_idx;
+ u16 chained;
+ int ret;
+
+ /* Use the validated payload pointer; the header is user-writable. */
+ ret = validate_cmd_abo(xdna, cmd_abo, &dpu, &chained);
+ if (ret)
+ return ret;
+
+ /* Wait for queue slot and connected state. Drops and re-acquires io_lock. */
+ ret = wait_till_connected_hsa_not_full(hwctx);
+ if (ret) {
+ XDNA_DBG(xdna, "Wait for queue slot / ctx reconnect interrupted, ret %d", ret);
+ return ret;
+ }
+
+ slot_idx = priv->write_index & (CTX_MAX_CMDS - 1);
+ if (chained) {
+ ret = fill_indirect_pkt(priv, slot_idx, CTX_MAX_CMDS, dpu, chained + 1);
+ if (ret)
+ return ret;
+ } else {
+ ret = fill_direct_pkt(priv, slot_idx, dpu);
+ if (ret)
+ return ret;
+ }
+
+ pkt = &priv->umq_pkts[slot_idx];
+ pkt->pkt_header.common_header.opcode = OPCODE_EXEC_BUF;
+ pkt->pkt_header.common_header.chain_flag =
+ last_of_chain ? CHAIN_FLG_LAST_CMD : CHAIN_FLG_NOT_LAST_CMD;
+ pkt->pkt_header.common_header.reserved = 0x0;
+ pkt->pkt_header.completion_signal = amdxdna_gem_dev_addr(cmd_abo) +
+ offsetof(struct amdxdna_cmd, header);
+ *seq = publish_cmd(hwctx);
+ aie4_doorbell_ring(hwctx);
+ XDNA_DBG(xdna, "Submitted one cmd, %s seq %lld", hwctx->name, *seq);
+ return 0;
+}
+
+/* Peek head job without removing it from running list. */
+static struct amdxdna_sched_job *peek_running_job(struct amdxdna_hwctx *hwctx)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+ struct amdxdna_sched_job *job;
+
+ mutex_lock(&priv->io_lock);
+ job = list_first_entry_or_null(&priv->running_job_list,
+ struct amdxdna_sched_job, aie4_job_list);
+ mutex_unlock(&priv->io_lock);
+ return job;
+}
+
+/* Remove a job from the running list once it is completed or reaped. */
+static void dequeue_running_job(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+
+ mutex_lock(&priv->io_lock);
+ list_del(&job->aie4_job_list);
+ mutex_unlock(&priv->io_lock);
+}
+
+static void aie4_job_release(struct kref *ref)
+{
+ struct amdxdna_sched_job *job =
+ container_of(ref, struct amdxdna_sched_job, refcnt);
+ u32 i;
+
+ for (i = 0; i < job->aie4_cmd_bo_cnt; i++)
+ amdxdna_gem_put_obj(job->aie4_cmd_bos[i]);
+ kfree(job->aie4_cmd_bos);
+
+ amdxdna_sched_job_cleanup(job);
+ if (job->out_fence)
+ dma_fence_put(job->out_fence);
+ kfree(job);
+}
+
+static void job_done(struct amdxdna_sched_job *job)
+{
+ job->aie4_job_state = AIE4_JOB_STATE_DONE;
+ dma_fence_signal(job->fence);
+ /* Release submitter mm reference taken at submit. */
+ mmput_async(job->mm);
+ kref_put(&job->refcnt, aie4_job_release);
+}
+
+static void job_complete(struct amdxdna_sched_job *job)
+{
+ job_done(job);
+}
+
+/* Advance read_index when disconnected to unblock waiters. */
+static void update_read_index(struct amdxdna_hwctx *hwctx, u64 idx)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+
+ /* Order cmd-bo state write before the waiter observes completion. */
+ wmb();
+ WRITE_ONCE(*priv->umq_read_index, idx);
+}
+
+static void job_abort(struct amdxdna_sched_job *job)
+{
+ struct amdxdna_hwctx *hwctx = job->hwctx;
+ u32 i;
+
+ XDNA_WARN(hwctx->client->xdna, "aborting %s job %lld", hwctx->name, job->seq);
+ amdxdna_cmd_set_state(job->cmd_bo, ERT_CMD_STATE_ABORT);
+ for (i = 0; i < job->aie4_cmd_bo_cnt; i++)
+ amdxdna_cmd_set_state(job->aie4_cmd_bos[i], ERT_CMD_STATE_ABORT);
+ dma_fence_set_error(job->fence, -ECANCELED);
+ /* Advance read_index only if CERT has not already moved past this job. */
+ if (get_read_index(hwctx) <= job->seq)
+ update_read_index(hwctx, job->seq + 1);
+ job_done(job);
+}
+
+/*
+ * Stop a context whose running job timed out, so the NPU no longer
+ * accesses the job BOs before the worker aborts the jobs and signals
+ * their fences. Paths holding dev_lock flush this worker, so do not
+ * block on dev_lock; if it is busy, wait for another timeout period.
+ */
+static void job_timeout(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job)
+{
+ struct amdxdna_dev *xdna = hwctx->client->xdna;
+
+ if (!mutex_trylock(&xdna->dev_lock))
+ return;
+
+ /* The job may have completed or the context disconnected meanwhile. */
+ if (aie4_hwctx_connected(hwctx) && get_read_index(hwctx) <= job->seq) {
+ XDNA_ERR(xdna, "hwctx %s job %llu timed out", hwctx->name, job->seq);
+ aie4_hwctx_stop(hwctx);
+ }
+ mutex_unlock(&xdna->dev_lock);
+}
+
+static void job_worker(struct work_struct *work)
+{
+ struct amdxdna_hwctx_priv *priv =
+ container_of(work, struct amdxdna_hwctx_priv, job_work);
+ struct amdxdna_hwctx *hwctx = priv->hwctx;
+ struct amdxdna_sched_job *job;
+ int ret;
+
+ while ((job = peek_running_job(hwctx))) {
+ ret = wait_till_seq_completed(hwctx, job->seq,
+ msecs_to_jiffies(AIE4_JOB_TIMEOUT_MS));
+ if (ret == -ETIME) {
+ job_timeout(hwctx, job);
+ continue;
+ }
+ if (!ret) {
+ dequeue_running_job(hwctx, job);
+ /* Abort partially submitted jobs; complete fully submitted ones. */
+ if (job->aie4_job_state != AIE4_JOB_STATE_SUBMITTED)
+ job_abort(job);
+ else
+ job_complete(job);
+ } else if (aie4_hwctx_has_error(hwctx)) {
+ dequeue_running_job(hwctx, job);
+ job_abort(job);
+ } else {
+ /* Disconnected by suspend; resume requeues the worker. */
+ break;
+ }
+ }
+}
+
+int aie4_hwctx_wait_for_running(struct amdxdna_hwctx *hwctx)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+ struct amdxdna_dev *xdna = hwctx->client->xdna;
+ struct amdxdna_sched_job *job;
+ long error;
+ int ret = 0;
+
+ mutex_lock(&priv->io_lock);
+ job = READ_ONCE(priv->pending_head);
+ if (job && job->aie4_job_state == AIE4_JOB_STATE_SUBMITTING) {
+ mutex_unlock(&priv->io_lock);
+ error = wait_event_timeout(priv->job_list_wq,
+ READ_ONCE(priv->pending_head) != job,
+ msecs_to_jiffies(2000));
+ if (!error) {
+ XDNA_WARN(xdna, "hwctx %s wait for submitting job timed out",
+ hwctx->name);
+ ret = -ETIMEDOUT;
+ }
+ } else {
+ mutex_unlock(&priv->io_lock);
+ }
+
+ queue_work(priv->job_work_q, &priv->job_work);
+ flush_work(&priv->job_work);
+ return ret;
+}
+
+static void put_cmd_bos(struct amdxdna_sched_job *job)
+{
+ u32 i;
+
+ for (i = 0; i < job->aie4_cmd_bo_cnt; i++)
+ amdxdna_gem_put_obj(job->aie4_cmd_bos[i]);
+ kfree(job->aie4_cmd_bos);
+ job->aie4_cmd_bos = NULL;
+ job->aie4_cmd_bo_cnt = 0;
+}
+
+/* Look up and validate all sub-command BOs of a command chain. */
+static int get_cmd_bos(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job)
+{
+ struct amdxdna_dev *xdna = hwctx->client->xdna;
+ struct amdxdna_cmd_chain *payload;
+ struct amdxdna_gem_obj *abo;
+ u32 payload_len, ccnt;
+ int ret;
+ u32 i;
+
+ payload = amdxdna_cmd_get_payload(job->cmd_bo, &payload_len);
+ if (!payload) {
+ XDNA_ERR(xdna, "Invalid cmd payload for chained cmd");
+ return -EINVAL;
+ }
+ ccnt = READ_ONCE(payload->command_count);
+ /* A command chain cannot exceed queue capacity. */
+ if (!ccnt || ccnt > CTX_MAX_CMDS ||
+ payload_len < struct_size(payload, data, ccnt)) {
+ XDNA_ERR(xdna, "Invalid command count %u", ccnt);
+ return -EINVAL;
+ }
+
+ job->aie4_cmd_bos = kcalloc(ccnt, sizeof(*job->aie4_cmd_bos), GFP_KERNEL);
+ if (!job->aie4_cmd_bos)
+ return -ENOMEM;
+
+ for (i = 0; i < ccnt; i++) {
+ u32 boh = (u32)(payload->data[i]);
+
+ abo = amdxdna_gem_get_obj(hwctx->client, boh, AMDXDNA_BO_SHARE);
+ if (!abo) {
+ XDNA_ERR(xdna, "Failed to find cmd BO %u at index %u", boh, i);
+ ret = -ENOENT;
+ goto put_bos;
+ }
+ job->aie4_cmd_bos[job->aie4_cmd_bo_cnt++] = abo;
+
+ ret = validate_cmd_abo(xdna, abo, NULL, NULL);
+ if (ret)
+ goto put_bos;
+ }
+
+ return 0;
+
+put_bos:
+ put_cmd_bos(job);
+ return ret;
+}
+
+/* Append a GEM object to the lock list unless it is already there. */
+static void add_lock_obj(struct drm_gem_object **objs, u32 *cnt,
+ struct drm_gem_object *obj)
+{
+ u32 i;
+
+ for (i = 0; i < *cnt; i++) {
+ if (objs[i] == obj)
+ return;
+ }
+ objs[(*cnt)++] = obj;
+}
+
+/*
+ * Lock arg and command BOs, repopulate invalidated mappings and attach
+ * the job fence. The NPU writes completion to command BO headers, so
+ * they are fenced too. Duplicates are skipped as
+ * drm_gem_lock_reservations() fails on them.
+ */
+static int fence_job_bos(struct amdxdna_dev *xdna, struct amdxdna_sched_job *job)
+{
+ struct ww_acquire_ctx acquire_ctx;
+ struct drm_gem_object **objs;
+ struct amdxdna_gem_obj *abo;
+ unsigned long timeout = 0;
+ u32 cnt = 0;
+ int ret;
+ u32 i;
+
+ objs = kmalloc_array(job->bo_cnt + 1 + job->aie4_cmd_bo_cnt,
+ sizeof(*objs), GFP_KERNEL);
+ if (!objs)
+ return -ENOMEM;
+
+ for (i = 0; i < job->bo_cnt; i++)
+ add_lock_obj(objs, &cnt, job->bos[i]);
+ add_lock_obj(objs, &cnt, to_gobj(job->cmd_bo));
+ for (i = 0; i < job->aie4_cmd_bo_cnt; i++)
+ add_lock_obj(objs, &cnt, to_gobj(job->aie4_cmd_bos[i]));
+
+retry:
+ ret = drm_gem_lock_reservations(objs, cnt, &acquire_ctx);
+ if (ret) {
+ XDNA_WARN(xdna, "Failed to lock BOs, ret %d", ret);
+ goto free_objs;
+ }
+
+ for (i = 0; i < cnt; i++) {
+ ret = dma_resv_reserve_fences(objs[i]->resv, 1);
+ if (ret) {
+ XDNA_WARN(xdna, "Failed to reserve fences %d", ret);
+ goto unlock;
+ }
+ }
+
+ down_read(&xdna->notifier_lock);
+ for (i = 0; i < cnt; i++) {
+ abo = to_xdna_obj(objs[i]);
+ if (abo->mem.map_invalid) {
+ up_read(&xdna->notifier_lock);
+ drm_gem_unlock_reservations(objs, cnt, &acquire_ctx);
+ if (!timeout) {
+ timeout = jiffies +
+ msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
+ } else if (time_after(jiffies, timeout)) {
+ ret = -ETIME;
+ goto free_objs;
+ }
+
+ ret = amdxdna_populate_range(abo);
+ if (ret)
+ goto free_objs;
+ goto retry;
+ }
+ }
+
+ job->out_fence = dma_fence_get(job->fence);
+ for (i = 0; i < cnt; i++)
+ dma_resv_add_fence(objs[i]->resv, job->out_fence, DMA_RESV_USAGE_WRITE);
+ up_read(&xdna->notifier_lock);
+
+unlock:
+ drm_gem_unlock_reservations(objs, cnt, &acquire_ctx);
+free_objs:
+ kfree(objs);
+ return ret;
+}
+
+/*
+ * Submit job command(s) to host queue. Called with io_lock held.
+ * Returns 0 on success or if partial chain is queued for worker abort.
+ */
+static int submit_job_cmds(struct amdxdna_hwctx *hwctx,
+ struct amdxdna_sched_job *job, u32 op)
+{
+ int ret = 0;
+ u32 i;
+
+ /* Single cmd. */
+ if (op == ERT_START_DPU) {
+ ret = submit_one_cmd(hwctx, job->cmd_bo, true, &job->seq);
+ if (!ret)
+ job->aie4_job_state = AIE4_JOB_STATE_SUBMITTED;
+ return ret;
+ }
+
+ /* Cmd chain. Sub-command BOs were looked up and validated at submit. */
+ for (i = 0; i < job->aie4_cmd_bo_cnt; i++) {
+ ret = submit_one_cmd(hwctx, job->aie4_cmd_bos[i],
+ i + 1 == job->aie4_cmd_bo_cnt, &job->seq);
+ if (ret)
+ break;
+ job->aie4_job_state = AIE4_JOB_STATE_SUBMITTING;
+ }
+
+ if (!ret) {
+ job->aie4_job_state = AIE4_JOB_STATE_SUBMITTED;
+ return 0;
+ }
+
+ /*
+ * If partial submission occurred, return 0 so the job is queued to
+ * running_job_list. The worker will wait for hardware to finish the
+ * published packets (up to job->seq), then abort the job safely.
+ */
+ if (job->aie4_job_state == AIE4_JOB_STATE_SUBMITTING)
+ return 0;
+
+ return ret;
+}
+
+/* Pending list serializes job submissions on the hardware queue. */
+/* Publish current pending-list head for lockless submit wait condition. */
+static void update_pending_head(struct amdxdna_hwctx_priv *priv)
+{
+ WRITE_ONCE(priv->pending_head,
+ list_first_entry_or_null(&priv->pending_job_list,
+ struct amdxdna_sched_job, aie4_job_list));
+}
+
+static void enqueue_pending_job(struct amdxdna_hwctx *hwctx,
+ struct amdxdna_sched_job *job)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+
+ mutex_lock(&priv->io_lock);
+ list_add_tail(&job->aie4_job_list, &priv->pending_job_list);
+ job->aie4_job_state = AIE4_JOB_STATE_PENDING;
+ update_pending_head(priv);
+ mutex_unlock(&priv->io_lock);
+
+ /* Let the next pending submitter re-check whether it is now first. */
+ wake_up_all(&priv->job_list_wq);
+}
+
+static void cancel_pending_job(struct amdxdna_hwctx *hwctx,
+ struct amdxdna_sched_job *job)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+
+ mutex_lock(&priv->io_lock);
+ list_del(&job->aie4_job_list);
+ job->aie4_job_state = AIE4_JOB_STATE_INIT;
+ update_pending_head(priv);
+ mutex_unlock(&priv->io_lock);
+ /* Let the next pending submitter re-check whether it is now first. */
+ wake_up_all(&priv->job_list_wq);
+}
+
+int aie4_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+ struct amdxdna_dev *xdna = hwctx->client->xdna;
+ u32 op;
+ int ret;
+
+ XDNA_DBG(xdna, "ctx %s job %p received", hwctx->name, job);
+
+ if (!job->cmd_bo) {
+ XDNA_ERR(xdna, "No command BO in job");
+ return -EINVAL;
+ }
+
+ op = amdxdna_cmd_get_op(job->cmd_bo);
+ if (op != ERT_START_DPU && op != ERT_CMD_CHAIN) {
+ XDNA_ERR(xdna, "Invalid cmd opcode %d", op);
+ return -EINVAL;
+ }
+
+ INIT_LIST_HEAD(&job->aie4_job_list);
+
+ /* Pin submitter's address space until job completion. */
+ if (!mmget_not_zero(job->mm)) {
+ XDNA_ERR(xdna, "Failed to get mm reference");
+ return -ESRCH;
+ }
+
+ if (op == ERT_CMD_CHAIN) {
+ ret = get_cmd_bos(hwctx, job);
+ if (ret)
+ goto put_mm;
+ }
+
+ ret = fence_job_bos(xdna, job);
+ if (ret)
+ goto put_mm;
+
+ /* Wait until this job reaches head of pending list. */
+ enqueue_pending_job(hwctx, job);
+ ret = wait_event_freezable(priv->job_list_wq,
+ READ_ONCE(priv->pending_head) == job);
+ if (ret) {
+ cancel_pending_job(hwctx, job);
+ goto signal_fence;
+ }
+
+ mutex_lock(&priv->io_lock);
+ ret = submit_job_cmds(hwctx, job, op);
+ if (ret) {
+ /* No command was published; cancel pending job and signal fence error. */
+ mutex_unlock(&priv->io_lock);
+ cancel_pending_job(hwctx, job);
+ goto signal_fence;
+ }
+
+ /* Move in-flight or partial job to running list for worker completion. */
+ list_move_tail(&job->aie4_job_list, &priv->running_job_list);
+ update_pending_head(priv);
+ *seq = job->seq;
+ mutex_unlock(&priv->io_lock);
+
+ /* Release the next pending submitter and kick the reaper. */
+ wake_up_all(&priv->job_list_wq);
+ atomic64_inc(&hwctx->job_submit_cnt);
+ queue_work(priv->job_work_q, &priv->job_work);
+ return 0;
+
+signal_fence:
+ /* Map -ERESTARTSYS to -ECANCELED for exported fence error status. */
+ dma_fence_set_error(job->fence, ret == -ERESTARTSYS ? -ECANCELED : ret);
+ dma_fence_signal(job->fence);
+ dma_fence_put(job->out_fence);
+ job->out_fence = NULL;
+put_mm:
+ put_cmd_bos(job);
+ mmput(job->mm);
+ return ret;
}
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index 93594211c169..7f4238f76bc2 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -1085,7 +1085,9 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
.fini = aie4_vf_fini,
.debugfs_init = aie4_debugfs_init,
.hwctx_init = aie4_hwctx_init,
+ .hwctx_stop = aie4_hwctx_stop,
.hwctx_fini = aie4_hwctx_fini,
+ .cmd_submit = aie4_cmd_submit,
.cmd_wait = aie4_cmd_wait,
.get_aie_info = aie4_get_info,
.set_aie_state = aie4_set_state,
@@ -1096,7 +1098,9 @@ const struct amdxdna_dev_ops aie4_classic_ops = {
.fini = aie4_classic_fini,
.debugfs_init = aie4_debugfs_init,
.hwctx_init = aie4_hwctx_init,
+ .hwctx_stop = aie4_hwctx_stop,
.hwctx_fini = aie4_hwctx_fini,
+ .cmd_submit = aie4_cmd_submit,
.cmd_wait = aie4_cmd_wait,
.get_aie_info = aie4_get_info,
.set_aie_state = aie4_set_state,
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 3d3301ce11ae..da5aa57bc43f 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -48,6 +48,7 @@ struct amdxdna_hwctx_priv {
struct cert_comp *cert_comp;
u32 hw_ctx_id;
+ bool has_error;
/* Direct and indirect packet storage aliasing umq_bo. */
u64 write_index;
@@ -146,10 +147,13 @@ enum aie4_hwctx_flags {
};
int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
+void aie4_hwctx_stop(struct amdxdna_hwctx *hwctx);
void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx);
int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout);
+int aie4_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq);
int aie4_hwctx_create(struct amdxdna_hwctx *hwctx);
void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags);
+int aie4_hwctx_wait_for_running(struct amdxdna_hwctx *hwctx);
/* aie4_pci.c */
int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev);
diff --git a/drivers/accel/amdxdna/amdxdna_ctx.c b/drivers/accel/amdxdna/amdxdna_ctx.c
index 888e857ec558..608b86fe8f6b 100644
--- a/drivers/accel/amdxdna/amdxdna_ctx.c
+++ b/drivers/accel/amdxdna/amdxdna_ctx.c
@@ -25,7 +25,6 @@
struct amdxdna_fence {
struct dma_fence base;
spinlock_t lock; /* for base */
- struct amdxdna_hwctx *hwctx;
};
static const char *amdxdna_fence_get_driver_name(struct dma_fence *fence)
@@ -35,11 +34,8 @@ static const char *amdxdna_fence_get_driver_name(struct dma_fence *fence)
static const char *amdxdna_fence_get_timeline_name(struct dma_fence *fence)
{
- struct amdxdna_fence *xdna_fence;
-
- xdna_fence = container_of(fence, struct amdxdna_fence, base);
-
- return xdna_fence->hwctx->name;
+ /* Constant string ensures name remains valid if fence outlives device. */
+ return KBUILD_MODNAME;
}
static const struct dma_fence_ops fence_ops = {
@@ -55,9 +51,9 @@ static struct dma_fence *amdxdna_fence_create(struct amdxdna_hwctx *hwctx)
if (!fence)
return NULL;
- fence->hwctx = hwctx;
spin_lock_init(&fence->lock);
- dma_fence_init(&fence->base, &fence_ops, &fence->lock, hwctx->id, 0);
+ /* Unique timeline context prevents eviction from shared BO reservation. */
+ dma_fence_init(&fence->base, &fence_ops, &fence->lock, dma_fence_context_alloc(1), 0);
return &fence->base;
}
@@ -84,6 +80,9 @@ static void amdxdna_hwctx_destroy_rcu(struct amdxdna_hwctx *hwctx,
struct amdxdna_client *client = hwctx->client;
struct amdxdna_dev *xdna = client->xdna;
+ if (xdna->dev_info->ops->hwctx_stop)
+ xdna->dev_info->ops->hwctx_stop(hwctx);
+
synchronize_srcu(ss);
/* At this point, user is not able to submit new commands */
@@ -206,11 +205,17 @@ int amdxdna_cmd_set_error(struct amdxdna_gem_obj *abo,
*/
void amdxdna_hwctx_remove_all(struct amdxdna_client *client)
{
+ struct amdxdna_dev *xdna = client->xdna;
struct amdxdna_hwctx *hwctx;
unsigned long hwctx_id;
+ if (xdna->dev_info->ops->hwctx_stop) {
+ amdxdna_for_each_hwctx(client, hwctx_id, hwctx)
+ xdna->dev_info->ops->hwctx_stop(hwctx);
+ }
+
amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
- XDNA_DBG(client->xdna, "PID %d close HW context %d",
+ XDNA_DBG(xdna, "PID %d close HW context %d",
client->pid, hwctx->id);
xa_erase(&client->hwctx_xa, hwctx->id);
amdxdna_hwctx_destroy_rcu(hwctx, &client->hwctx_srcu);
@@ -289,6 +294,8 @@ int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct dr
free_name:
kfree(hwctx->name);
fini_hwctx:
+ if (xdna->dev_info->ops->hwctx_stop)
+ xdna->dev_info->ops->hwctx_stop(hwctx);
xdna->dev_info->ops->hwctx_fini(hwctx);
release_expanded_heap:
amdxdna_hwctx_release_expanded_heap(hwctx);
diff --git a/drivers/accel/amdxdna/amdxdna_ctx.h b/drivers/accel/amdxdna/amdxdna_ctx.h
index b3677851d1c5..2e6b300d652f 100644
--- a/drivers/accel/amdxdna/amdxdna_ctx.h
+++ b/drivers/accel/amdxdna/amdxdna_ctx.h
@@ -157,6 +157,8 @@ union amdxdna_job_priv {
struct {
struct list_head list;
u32 state;
+ u32 cmd_bo_cnt;
+ struct amdxdna_gem_obj **cmd_bos;
} aie4;
};
@@ -179,9 +181,11 @@ struct amdxdna_sched_job {
struct drm_gem_object *bos[] __counted_by(bo_cnt);
};
-#define aie2_job_health priv.aie2_health
+#define aie2_job_health priv.aie2_health
#define aie4_job_list priv.aie4.list
#define aie4_job_state priv.aie4.state
+#define aie4_cmd_bo_cnt priv.aie4.cmd_bo_cnt
+#define aie4_cmd_bos priv.aie4.cmd_bos
static inline u32
amdxdna_cmd_get_op(struct amdxdna_gem_obj *abo)
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
index 2a1d6b33363c..eccb461d32bc 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -59,6 +59,7 @@ struct amdxdna_dev_ops {
int (*suspend)(struct amdxdna_dev *xdna);
int (*sriov_configure)(struct amdxdna_dev *xdna, int num_vfs);
int (*hwctx_init)(struct amdxdna_hwctx *hwctx);
+ void (*hwctx_stop)(struct amdxdna_hwctx *hwctx);
void (*hwctx_fini)(struct amdxdna_hwctx *hwctx);
int (*hwctx_config)(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
int (*hwctx_sync_debug_bo)(struct amdxdna_hwctx *hwctx, u32 debug_bo_hdl);
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH V4 17/19] accel/amdxdna: Enable AIE4 firmware logging to DRAM
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (15 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 16/19] accel/amdxdna: Implement AIE4 command packet building and submission David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-09 23:14 ` sashiko-bot
2026-10-09 22:53 ` [PATCH V4 18/19] accel/amdxdna: Implement AIE4 suspend and resume David Zhang
2026-10-09 22:53 ` [PATCH V4 19/19] accel/amdxdna: Implement runtime suspend and resume support David Zhang
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello
Allocate a DRAM buffer for firmware logging, and also set the log level
to less verbose. This will give the best performance numbers.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_message.c | 20 ++++++++++
drivers/accel/amdxdna/aie4_msg_priv.h | 24 ++++++++++++
drivers/accel/amdxdna/aie4_pci.c | 53 +++++++++++++++++++++++++++
drivers/accel/amdxdna/aie4_pci.h | 5 +++
4 files changed, 102 insertions(+)
diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
index 2820cfb6f9ed..96ccc28e5360 100644
--- a/drivers/accel/amdxdna/aie4_message.c
+++ b/drivers/accel/amdxdna/aie4_message.c
@@ -247,6 +247,26 @@ int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev)
return ret;
}
+int aie4_start_fw_log(struct amdxdna_dev_hdl *ndev, u32 level)
+{
+ DECLARE_AIE_MSG(aie4_msg_start_fw_log, AIE4_MSG_OP_START_FW_LOG);
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ int ret;
+
+ req.buff_addr = ndev->fw_log_buf_addr;
+ req.buff_size = ndev->fw_log_buf_size;
+ req.log_level = level;
+
+ ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ if (ret)
+ XDNA_WARN(xdna, "Failed to start fw log, ret %d", ret);
+ else
+ XDNA_DBG(xdna, "Started fw log, level %u size 0x%x",
+ level, ndev->fw_log_buf_size);
+
+ return ret;
+}
+
int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode)
{
DECLARE_AIE_MSG(aie4_msg_power_override, AIE4_MSG_OP_POWER_OVERRIDE);
diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
index 636bf8d04c76..566f6abc9e2d 100644
--- a/drivers/accel/amdxdna/aie4_msg_priv.h
+++ b/drivers/accel/amdxdna/aie4_msg_priv.h
@@ -29,6 +29,7 @@ enum aie4_msg_opcode {
AIE4_MSG_OP_GET_CURRENT_DPM_LEVEL = 0x30013,
AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
+ AIE4_MSG_OP_START_FW_LOG = 0x40003,
};
enum aie4_msg_status {
@@ -263,4 +264,27 @@ struct aie4_msg_attach_work_buffer_resp {
enum aie4_msg_status status;
} __packed;
+/* Dynamic firmware log levels. */
+enum aie4_fw_log_level {
+ AIE4_FW_LOG_LEVEL_OFF,
+ AIE4_FW_LOG_LEVEL_ERR,
+ AIE4_FW_LOG_LEVEL_WRN,
+ AIE4_FW_LOG_LEVEL_INF,
+ AIE4_FW_LOG_LEVEL_DBG,
+ AIE4_FW_LOG_LEVEL_MAX,
+};
+
+#define AIE4_FW_LOG_BUF_SIZE SZ_1M
+
+struct aie4_msg_start_fw_log_req {
+ __u64 buff_addr;
+ __u32 buff_size;
+ __u32 log_level;
+ __u32 reserved;
+} __packed;
+
+struct aie4_msg_start_fw_log_resp {
+ enum aie4_msg_status status;
+} __packed;
+
#endif /* _AIE4_MSG_PRIV_H_ */
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index 7f4238f76bc2..e09d24d85cdf 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -383,6 +383,16 @@ static int aie4_config_fw(struct amdxdna_dev_hdl *ndev)
if (ret == -ETIME)
return ret;
+ /*
+ * Give the firmware high performance DRAM to log into with less
+ * verbose level.
+ */
+ if (ndev->fw_log_buf) {
+ ret = aie4_start_fw_log(ndev, AIE4_FW_LOG_LEVEL_ERR);
+ if (ret == -ETIME)
+ return ret;
+ }
+
return 0;
}
@@ -941,6 +951,41 @@ static void aie4_free_work_buffer(struct amdxdna_dev_hdl *ndev)
ndev->work_buf = NULL;
}
+/*
+ * Firmware logging is best effort: a device that cannot spare the buffer still
+ * runs, it just does not log. Never fail hw start or probe on this.
+ */
+static void aie4_alloc_fw_log_buffer(struct amdxdna_dev_hdl *ndev)
+{
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ u32 buf_size = AIE4_FW_LOG_BUF_SIZE;
+
+ ndev->fw_log_buf = amdxdna_alloc_msg_buffer(xdna, &buf_size,
+ &ndev->fw_log_buf_addr);
+ if (IS_ERR(ndev->fw_log_buf)) {
+ XDNA_WARN(xdna, "Failed to alloc fw log buffer, size 0x%x",
+ AIE4_FW_LOG_BUF_SIZE);
+ ndev->fw_log_buf = NULL;
+ return;
+ }
+
+ ndev->fw_log_buf_size = buf_size;
+ XDNA_DBG(xdna, "FW log buffer allocated: size 0x%x", buf_size);
+}
+
+/* Free logging buffer after firmware execution has stopped. */
+static void aie4_free_fw_log_buffer(struct amdxdna_dev_hdl *ndev)
+{
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+
+ if (!ndev->fw_log_buf)
+ return;
+
+ amdxdna_free_msg_buffer(xdna, ndev->fw_log_buf_size, ndev->fw_log_buf,
+ ndev->fw_log_buf_addr);
+ ndev->fw_log_buf = NULL;
+}
+
static int aie4_pf_init(struct amdxdna_dev *xdna)
{
int ret;
@@ -953,6 +998,8 @@ static int aie4_pf_init(struct amdxdna_dev *xdna)
if (ret)
return ret;
+ aie4_alloc_fw_log_buffer(xdna->dev_handle);
+
ret = aie4_pf_hw_start(xdna->dev_handle);
if (ret)
goto free_work_buf;
@@ -960,6 +1007,7 @@ static int aie4_pf_init(struct amdxdna_dev *xdna)
return 0;
free_work_buf:
+ aie4_free_fw_log_buffer(xdna->dev_handle);
aie4_free_work_buffer(xdna->dev_handle);
return ret;
}
@@ -987,6 +1035,8 @@ static int aie4_classic_init(struct amdxdna_dev *xdna)
if (ret)
return ret;
+ aie4_alloc_fw_log_buffer(xdna->dev_handle);
+
ret = aie4_classic_hw_start(xdna->dev_handle);
if (ret)
goto free_work_buf;
@@ -994,6 +1044,7 @@ static int aie4_classic_init(struct amdxdna_dev *xdna)
return 0;
free_work_buf:
+ aie4_free_fw_log_buffer(xdna->dev_handle);
aie4_free_work_buffer(xdna->dev_handle);
return ret;
}
@@ -1002,6 +1053,7 @@ static void aie4_pf_fini(struct amdxdna_dev *xdna)
{
aie4_sriov_stop(xdna->dev_handle);
aie4_pf_hw_stop(xdna->dev_handle);
+ aie4_free_fw_log_buffer(xdna->dev_handle);
aie4_free_work_buffer(xdna->dev_handle);
}
@@ -1013,6 +1065,7 @@ static void aie4_vf_fini(struct amdxdna_dev *xdna)
static void aie4_classic_fini(struct amdxdna_dev *xdna)
{
aie4_classic_hw_stop(xdna->dev_handle);
+ aie4_free_fw_log_buffer(xdna->dev_handle);
aie4_free_work_buffer(xdna->dev_handle);
}
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index da5aa57bc43f..4b7367af7cf1 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -105,6 +105,10 @@ struct amdxdna_dev_hdl {
dma_addr_t work_buf_addr;
u32 work_buf_size;
+ void *fw_log_buf;
+ dma_addr_t fw_log_buf_addr;
+ u32 fw_log_buf_size;
+
u8 pw_mode;
/* Context switch hysteresis timeout in microseconds. */
@@ -125,6 +129,7 @@ int aie4_query_aie_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_aie_version *version);
int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev);
int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev);
+int aie4_start_fw_log(struct amdxdna_dev_hdl *ndev, u32 level);
int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_firmware_version *fw_version);
int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 17/19] accel/amdxdna: Enable AIE4 firmware logging to DRAM
2026-10-09 22:53 ` [PATCH V4 17/19] accel/amdxdna: Enable AIE4 firmware logging to DRAM David Zhang
@ 2026-10-09 23:14 ` sashiko-bot
0 siblings, 0 replies; 39+ messages in thread
From: sashiko-bot @ 2026-10-09 23:14 UTC (permalink / raw)
To: David Zhang; +Cc: dri-devel
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] amdxdna: DMA Use-After-Free of fw_log_buf on hardware start failure
--
commit 399dd24d5b4823ad10e211886f1046c8d43ff630
Author: David Zhang <yidong.zhang@amd.com>
accel/amdxdna: Enable AIE4 firmware logging to DRAM
This commit allocates a DRAM buffer for firmware logging and configures the
device to use it with a less verbose log level.
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index 7f4238f76bc22..e09d24d85cdfa 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
[ ... ]
> @@ -953,6 +998,8 @@ static int aie4_pf_init(struct amdxdna_dev *xdna)
> if (ret)
> return ret;
>
> + aie4_alloc_fw_log_buffer(xdna->dev_handle);
> +
> ret = aie4_pf_hw_start(xdna->dev_handle);
> if (ret)
> goto free_work_buf;
> @@ -960,6 +1007,7 @@ static int aie4_pf_init(struct amdxdna_dev *xdna)
> return 0;
>
> free_work_buf:
> + aie4_free_fw_log_buffer(xdna->dev_handle);
[Severity: High]
Can this lead to a use-after-free of the DMA buffer if the hardware fails to
start?
During aie4_pf_hw_start(), aie4_config_fw() is called which instructs the
firmware to begin asynchronously DMA-ing logs into fw_log_buf.
If a subsequent step in aie4_pf_hw_start() fails (such as
aie4_restore_power_mode() timing out), the error path attempts to stop the
firmware via aie4_fw_stop().
However, if the PSP teardown inside aie_psp_stop() also times out:
aie_psp_stop() {
...
ret = psp_exec(psp, reg_vals);
if (ret)
drm_err(psp->ddev, "release tmr failed, ret %d", ret);
}
It returns without successfully halting the active firmware. We then reach
this error path in aie4_pf_init() and free fw_log_buf back to the page
allocator.
Does the active firmware continue writing logs into this freed memory?
> aie4_free_work_buffer(xdna->dev_handle);
> return ret;
> }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009225343.3079074-1-yidong.zhang@amd.com?part=17
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V4 18/19] accel/amdxdna: Implement AIE4 suspend and resume
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (16 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 17/19] accel/amdxdna: Enable AIE4 firmware logging to DRAM David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-09 22:53 ` [PATCH V4 19/19] accel/amdxdna: Implement runtime suspend and resume support David Zhang
18 siblings, 0 replies; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello
Implement suspend and resume callbacks for AIE4 Physical Function (PF),
Virtual Function (VF), and Classic device types:
- Implement aie4_hwctx_suspend_all() to destroy or drain contexts across
all registered clients and wait for in-flight jobs.
- Implement aie4_hwctx_resume_all() to recreate firmware contexts and
kick doorbells via aie4_hwctx_resume_jobs() to resume hardware queue
consumption.
- Guard firmware destroy message in aie4_hwctx_destroy() when context
ID is invalid.
- Restore SR-IOV virtual functions on PF resume via aie4_restore_sriov().
- Link each VF to the PF with a stateless device link when SR-IOV is
enabled, so system suspend handles VFs before the PF and resume
handles the PF before VFs. The link survives VF driver rebind and is
removed before SR-IOV is disabled.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_ctx.c | 18 +-
drivers/accel/amdxdna/aie4_pci.c | 251 ++++++++++++++++++++++++
drivers/accel/amdxdna/aie4_pci.h | 11 ++
drivers/accel/amdxdna/aie4_sriov.c | 66 ++++++-
drivers/accel/amdxdna/amdxdna_pci_drv.h | 3 +
5 files changed, 347 insertions(+), 2 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
index 43d26454be6c..a2b6b0fa2934 100644
--- a/drivers/accel/amdxdna/aie4_ctx.c
+++ b/drivers/accel/amdxdna/aie4_ctx.c
@@ -255,7 +255,7 @@ void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags flags
if (has_error)
wake_up_all(&priv->job_list_wq);
- if (flags != AIE4_HWCTX_DISCONNECT)
+ if (flags != AIE4_HWCTX_DISCONNECT && priv->hw_ctx_id != CTX_INVALID_ID)
aie4_msg_destroy_context(ndev, priv->hw_ctx_id);
if (cert_comp)
@@ -363,6 +363,7 @@ int aie4_hwctx_init(struct amdxdna_hwctx *hwctx)
return -ENOMEM;
hwctx->priv = priv;
priv->hwctx = hwctx;
+ priv->hw_ctx_id = CTX_INVALID_ID;
/* Initialize io_lock guarding cert_comp binding. */
mutex_init(&priv->io_lock);
@@ -951,6 +952,21 @@ int aie4_hwctx_wait_for_running(struct amdxdna_hwctx *hwctx)
return ret;
}
+void aie4_hwctx_resume_jobs(struct amdxdna_hwctx *hwctx)
+{
+ struct amdxdna_hwctx_priv *priv = hwctx->priv;
+
+ mutex_lock(&priv->io_lock);
+ if (list_empty(&priv->running_job_list)) {
+ mutex_unlock(&priv->io_lock);
+ return;
+ }
+ aie4_doorbell_ring(hwctx);
+ mutex_unlock(&priv->io_lock);
+
+ queue_work(priv->job_work_q, &priv->job_work);
+}
+
static void put_cmd_bos(struct amdxdna_sched_job *job)
{
u32 i;
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index e09d24d85cdf..70a052ab5f77 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -1126,11 +1126,258 @@ static void aie4_debugfs_init(struct amdxdna_dev *xdna)
&aie4_ctx_hysteresis_fops);
}
+void aie4_hwctx_suspend_all(struct amdxdna_dev_hdl *ndev, int clean_jobs)
+{
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ struct amdxdna_client *client;
+ struct amdxdna_hwctx *hwctx;
+ unsigned long hwctx_id;
+ int idx;
+
+ drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+ amdxdna_for_each_client(xdna, client) {
+ idx = srcu_read_lock(&client->hwctx_srcu);
+ amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
+ /* clean up workers and drain running jobs */
+ if (clean_jobs) {
+ int ret;
+
+ aie4_hwctx_destroy(hwctx, AIE4_HWCTX_ERROR);
+ ret = aie4_hwctx_wait_for_running(hwctx);
+ if (ret)
+ XDNA_WARN(xdna, "hwctx %s wait for running failed %d",
+ hwctx->name, ret);
+ } else {
+ aie4_hwctx_destroy(hwctx, AIE4_HWCTX_NORMAL);
+ }
+ }
+ srcu_read_unlock(&client->hwctx_srcu, idx);
+ }
+
+ XDNA_DBG(xdna, "Finished hwctx suspend");
+}
+
+int aie4_hwctx_resume_all(struct amdxdna_dev_hdl *ndev)
+{
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ struct amdxdna_client *client;
+ struct amdxdna_hwctx *hwctx;
+ unsigned long hwctx_id;
+ int ret, idx;
+
+ drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+ amdxdna_for_each_client(xdna, client) {
+ idx = srcu_read_lock(&client->hwctx_srcu);
+ amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
+ ret = aie4_hwctx_create(hwctx);
+ if (ret)
+ goto error;
+ aie4_hwctx_resume_jobs(hwctx);
+ }
+ srcu_read_unlock(&client->hwctx_srcu, idx);
+ }
+
+ XDNA_DBG(xdna, "Finished hwctx resume");
+ return 0;
+error:
+ srcu_read_unlock(&client->hwctx_srcu, idx);
+ XDNA_DBG(xdna, "Failed hwctx resume");
+ return ret;
+}
+
+static int aie4_restore_sriov(struct amdxdna_dev_hdl *ndev)
+{
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+ int ret;
+
+ if (ndev->num_vfs) {
+ if (pci_num_vf(pdev) != ndev->num_vfs) {
+ XDNA_ERR(xdna, "inconsistent vf number");
+ return -EINVAL;
+ }
+ ret = aie4_create_vfs(ndev, ndev->num_vfs);
+ if (ret) {
+ XDNA_ERR(xdna, "create vfs failed, %d", ret);
+ return ret;
+ }
+ XDNA_DBG(xdna, "restored num_vfs %d", ndev->num_vfs);
+ }
+
+ return 0;
+}
+
+static int aie4_pf_suspend(struct amdxdna_dev *xdna)
+{
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+
+ drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+ aie4_pf_hw_stop(ndev);
+ pci_disable_device(pdev);
+
+ XDNA_DBG(xdna, "pf suspend done");
+ return 0;
+}
+
+static int aie4_pf_resume(struct amdxdna_dev *xdna)
+{
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+ int ret;
+
+ drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ XDNA_ERR(xdna, "enable pci device failed %d", ret);
+ return ret;
+ }
+ pci_set_master(pdev);
+
+ ret = aie4_pf_hw_start(ndev);
+ if (ret) {
+ XDNA_ERR(xdna, "hw_start failed %d", ret);
+ goto pci_disable;
+ }
+
+ ret = aie4_restore_sriov(ndev);
+ if (ret)
+ goto hw_stop;
+
+ XDNA_DBG(xdna, "pf resume done");
+ return 0;
+hw_stop:
+ aie4_pf_hw_stop(ndev);
+pci_disable:
+ pci_disable_device(pdev);
+ return ret;
+}
+
+static int aie4_vf_suspend(struct amdxdna_dev *xdna)
+{
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+
+ drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+ aie4_hwctx_suspend_all(ndev, false);
+ /*
+ * partition_fini and mailbox messages should not be called here
+ * because PF suspend will do the cleanup for all VFs.
+ */
+ aie4_mailbox_fini(ndev);
+ pci_disable_device(pdev);
+
+ XDNA_DBG(xdna, "vf suspend done");
+ return 0;
+}
+
+static int aie4_vf_resume(struct amdxdna_dev *xdna)
+{
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+ int ret;
+
+ drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ XDNA_ERR(xdna, "enable pci device failed %d", ret);
+ /* Contexts cannot reconnect; fail waiters and abort running jobs. */
+ aie4_hwctx_suspend_all(ndev, true);
+ return ret;
+ }
+ pci_set_master(pdev);
+
+ ret = aie4_vf_hw_start(ndev);
+ if (ret) {
+ XDNA_ERR(xdna, "hw_start failed %d", ret);
+ /* Contexts cannot reconnect; fail waiters and abort running jobs. */
+ aie4_hwctx_suspend_all(ndev, true);
+ goto pci_disable;
+ }
+
+ ret = aie4_hwctx_resume_all(ndev);
+ if (ret) {
+ XDNA_ERR(xdna, "hwctx_resume failed %d", ret);
+ goto hw_clear;
+ }
+
+ XDNA_DBG(xdna, "vf resume done");
+ return 0;
+
+hw_clear:
+ aie4_hwctx_suspend_all(ndev, true);
+ aie4_vf_hw_stop(ndev);
+pci_disable:
+ pci_disable_device(pdev);
+ return ret;
+}
+
+static int aie4_classic_suspend(struct amdxdna_dev *xdna)
+{
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+
+ drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+ aie4_hwctx_suspend_all(ndev, false);
+ aie4_classic_hw_stop(ndev);
+ pci_disable_device(pdev);
+
+ XDNA_DBG(xdna, "classic suspend done");
+ return 0;
+}
+
+static int aie4_classic_resume(struct amdxdna_dev *xdna)
+{
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+ int ret;
+
+ drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ XDNA_ERR(xdna, "enable pci device failed %d", ret);
+ /* Contexts cannot reconnect; fail waiters and abort running jobs. */
+ aie4_hwctx_suspend_all(ndev, true);
+ return ret;
+ }
+ pci_set_master(pdev);
+
+ ret = aie4_classic_hw_start(ndev);
+ if (ret) {
+ XDNA_ERR(xdna, "hw_start failed %d", ret);
+ /* Contexts cannot reconnect; fail waiters and abort running jobs. */
+ aie4_hwctx_suspend_all(ndev, true);
+ goto pci_disable;
+ }
+
+ ret = aie4_hwctx_resume_all(ndev);
+ if (ret) {
+ XDNA_ERR(xdna, "hwctx_resume failed %d", ret);
+ goto hw_clear;
+ }
+
+ XDNA_DBG(xdna, "classic resume done");
+ return 0;
+hw_clear:
+ aie4_hwctx_suspend_all(ndev, true);
+ aie4_classic_hw_stop(ndev);
+pci_disable:
+ pci_disable_device(pdev);
+ return ret;
+}
+
const struct amdxdna_dev_ops aie4_pf_ops = {
.init = aie4_pf_init,
.fini = aie4_pf_fini,
.debugfs_init = aie4_debugfs_init,
.sriov_configure = aie4_sriov_configure,
+ .resume = pm_ptr(aie4_pf_resume),
+ .suspend = pm_ptr(aie4_pf_suspend),
};
const struct amdxdna_dev_ops aie4_vf_ops = {
@@ -1144,6 +1391,8 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
.cmd_wait = aie4_cmd_wait,
.get_aie_info = aie4_get_info,
.set_aie_state = aie4_set_state,
+ .resume = pm_ptr(aie4_vf_resume),
+ .suspend = pm_ptr(aie4_vf_suspend),
};
const struct amdxdna_dev_ops aie4_classic_ops = {
@@ -1157,4 +1406,6 @@ const struct amdxdna_dev_ops aie4_classic_ops = {
.cmd_wait = aie4_cmd_wait,
.get_aie_info = aie4_get_info,
.set_aie_state = aie4_set_state,
+ .resume = pm_ptr(aie4_classic_resume),
+ .suspend = pm_ptr(aie4_classic_suspend),
};
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 4b7367af7cf1..fdc55e498246 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -95,6 +95,7 @@ struct amdxdna_dev_hdl {
u32 total_col;
u32 max_aieclk_level;
u32 max_npuhclk_level;
+ u32 num_vfs;
struct dpm_clk_freq dpm_clk_tbl[AIE4_MAX_DPM_LEVEL_COUNT];
@@ -159,8 +160,11 @@ int aie4_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
int aie4_hwctx_create(struct amdxdna_hwctx *hwctx);
void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx, enum aie4_hwctx_flags);
int aie4_hwctx_wait_for_running(struct amdxdna_hwctx *hwctx);
+void aie4_hwctx_resume_jobs(struct amdxdna_hwctx *hwctx);
/* aie4_pci.c */
+void aie4_hwctx_suspend_all(struct amdxdna_dev_hdl *ndev, int clean_jobs);
+int aie4_hwctx_resume_all(struct amdxdna_dev_hdl *ndev);
int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev);
/*
@@ -176,10 +180,17 @@ void aie4_free_notification(struct cert_comp *comp);
/* aie4_sriov.c */
#if IS_ENABLED(CONFIG_PCI_IOV)
+int aie4_create_vfs(struct amdxdna_dev_hdl *ndev, int num_vfs);
int aie4_sriov_configure(struct amdxdna_dev *xdna, int num_vfs);
int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev);
#else
+static inline int aie4_create_vfs(struct amdxdna_dev_hdl *ndev, int num_vfs)
+{
+ return 0;
+}
+
#define aie4_sriov_configure NULL
+
static inline int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev)
{
return 0;
diff --git a/drivers/accel/amdxdna/aie4_sriov.c b/drivers/accel/amdxdna/aie4_sriov.c
index e1ce633768a5..d3df36644914 100644
--- a/drivers/accel/amdxdna/aie4_sriov.c
+++ b/drivers/accel/amdxdna/aie4_sriov.c
@@ -26,7 +26,7 @@ static int aie4_destroy_vfs(struct amdxdna_dev_hdl *ndev)
return ret;
}
-static int aie4_create_vfs(struct amdxdna_dev_hdl *ndev, int num_vfs)
+int aie4_create_vfs(struct amdxdna_dev_hdl *ndev, int num_vfs)
{
DECLARE_AIE_MSG(aie4_msg_create_vfs, AIE4_MSG_OP_CREATE_VFS);
int ret;
@@ -39,6 +39,59 @@ static int aie4_create_vfs(struct amdxdna_dev_hdl *ndev, int num_vfs)
return ret;
}
+static int aie4_for_each_vfs(struct amdxdna_dev *xdna,
+ int (*cb)(struct amdxdna_dev *, struct pci_dev *))
+{
+ struct pci_dev *pdev_pf = to_pci_dev(xdna->ddev.dev);
+ struct pci_dev *pdev_vf;
+ int pos, ret;
+ u16 vf_did;
+
+ pos = pci_find_ext_capability(pdev_pf, PCI_EXT_CAP_ID_SRIOV);
+ if (!pos)
+ return 0;
+ ret = pci_read_config_word(pdev_pf, pos + PCI_SRIOV_VF_DID, &vf_did);
+ if (ret) {
+ XDNA_ERR(xdna, "read VF Device ID failed %d", ret);
+ return -ENODEV;
+ }
+
+ for (pdev_vf = pci_get_device(pdev_pf->vendor, vf_did, NULL);
+ pdev_vf;
+ pdev_vf = pci_get_device(pdev_pf->vendor, vf_did, pdev_vf)) {
+ if (!pdev_vf->is_virtfn || pdev_vf->physfn != pdev_pf)
+ continue;
+
+ ret = cb(xdna, pdev_vf);
+ if (ret) {
+ /* Release reference on early return. */
+ pci_dev_put(pdev_vf);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int aie4_link_vf(struct amdxdna_dev *xdna, struct pci_dev *pdev_vf)
+{
+ struct pci_dev *pdev_pf = to_pci_dev(xdna->ddev.dev);
+
+ /* Stateless so the link survives VF driver rebind. */
+ if (!device_link_add(&pdev_vf->dev, &pdev_pf->dev, DL_FLAG_STATELESS)) {
+ XDNA_ERR(xdna, "Failed to link VF %s", pci_name(pdev_vf));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int aie4_unlink_vf(struct amdxdna_dev *xdna, struct pci_dev *pdev_vf)
+{
+ device_link_remove(&pdev_vf->dev, xdna->ddev.dev);
+ return 0;
+}
+
int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev)
{
struct amdxdna_dev *xdna = ndev->aie.xdna;
@@ -54,7 +107,9 @@ int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev)
return -EPERM;
}
+ aie4_for_each_vfs(xdna, aie4_unlink_vf);
pci_disable_sriov(pdev);
+ ndev->num_vfs = 0;
return aie4_destroy_vfs(ndev);
}
@@ -75,6 +130,15 @@ static int aie4_sriov_start(struct amdxdna_dev_hdl *ndev, int num_vfs)
return ret;
}
+ ret = aie4_for_each_vfs(xdna, aie4_link_vf);
+ if (ret) {
+ aie4_for_each_vfs(xdna, aie4_unlink_vf);
+ pci_disable_sriov(pdev);
+ aie4_destroy_vfs(ndev);
+ return ret;
+ }
+
+ ndev->num_vfs = num_vfs;
return num_vfs;
}
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
index eccb461d32bc..505477b4a292 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -168,6 +168,9 @@ struct amdxdna_client {
#define amdxdna_for_each_hwctx(client, hwctx_id, entry) \
xa_for_each(&(client)->hwctx_xa, hwctx_id, entry)
+#define amdxdna_for_each_client(xdna, client) \
+ list_for_each_entry(client, &(xdna)->client_list, node)
+
/* Add device info below */
extern const struct amdxdna_dev_info dev_npu1_info;
extern const struct amdxdna_dev_info dev_npu3_classic_info;
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH V4 19/19] accel/amdxdna: Implement runtime suspend and resume support
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
` (17 preceding siblings ...)
2026-10-09 22:53 ` [PATCH V4 18/19] accel/amdxdna: Implement AIE4 suspend and resume David Zhang
@ 2026-10-09 22:53 ` David Zhang
2026-10-09 23:17 ` sashiko-bot
18 siblings, 1 reply; 39+ messages in thread
From: David Zhang @ 2026-10-09 22:53 UTC (permalink / raw)
To: quic_jhugo, karol.wachowski, max.zhen, lizhi.hou, ogabbay,
dri-devel, linux-kernel
Cc: David Zhang, sonal.santan, mario.limonciello
Add runtime suspend/resume for the AIE4 classic device by using its
system suspend/resume handlers.
Runtime suspend returns -EBUSY for a device without runtime_suspend,
so the PM core keeps it active instead of entering an error state.
A context suspended by runtime PM makes the command wait return
-EAGAIN. Resume the device in the wait ioctl and wait again, so a
command wait does not fail because of power management.
Wrap .driver.pm and the AIE4 PM callbacks with pm_ptr(), so they are
discarded when CONFIG_PM is disabled.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie2_pci.c | 2 ++
drivers/accel/amdxdna/aie4_ctx.c | 10 +++++-
drivers/accel/amdxdna/aie4_pci.c | 4 +++
drivers/accel/amdxdna/amdxdna_ctx.c | 47 ++++++++++++++++++-------
drivers/accel/amdxdna/amdxdna_pci_drv.c | 4 +--
drivers/accel/amdxdna/amdxdna_pci_drv.h | 2 ++
drivers/accel/amdxdna/amdxdna_pm.c | 34 ++++++++++++++++++
drivers/accel/amdxdna/amdxdna_pm.h | 2 ++
8 files changed, 90 insertions(+), 15 deletions(-)
diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c
index 690ad035463c..a3866e8933e6 100644
--- a/drivers/accel/amdxdna/aie2_pci.c
+++ b/drivers/accel/amdxdna/aie2_pci.c
@@ -1221,6 +1221,8 @@ const struct amdxdna_dev_ops aie2_ops = {
.fini = aie2_fini,
.resume = aie2_hw_resume,
.suspend = aie2_hw_suspend,
+ .runtime_resume = aie2_hw_resume,
+ .runtime_suspend = aie2_hw_suspend,
.get_aie_info = aie2_get_info,
.set_aie_state = aie2_set_state,
.hwctx_init = aie2_hwctx_init,
diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
index a2b6b0fa2934..a3f0a69b93b7 100644
--- a/drivers/accel/amdxdna/aie4_ctx.c
+++ b/drivers/accel/amdxdna/aie4_ctx.c
@@ -22,6 +22,7 @@
#include "amdxdna_mailbox.h"
#include "amdxdna_mailbox_helper.h"
#include "amdxdna_pci_drv.h"
+#include "amdxdna_pm.h"
#define CTX_INVALID_ID (~0U)
#define CTX_INVALID_DOORBELL AMDXDNA_INVALID_DOORBELL_OFFSET
@@ -377,10 +378,14 @@ int aie4_hwctx_init(struct amdxdna_hwctx *hwctx)
if (ret)
goto destroy_lock;
- ret = aie4_hwctx_create(hwctx);
+ ret = amdxdna_pm_resume_get_locked(xdna);
if (ret)
goto umq_fini;
+ ret = aie4_hwctx_create(hwctx);
+ if (ret)
+ goto suspend_put;
+
priv->job_work_q = alloc_ordered_workqueue("aie4_job_%d_%d", 0,
client->pid, hwctx->fw_ctx_id);
if (!priv->job_work_q) {
@@ -388,12 +393,15 @@ int aie4_hwctx_init(struct amdxdna_hwctx *hwctx)
ret = -ENOMEM;
goto destroy_ctx;
}
+ amdxdna_pm_suspend_put(xdna);
XDNA_DBG(xdna, "hwctx %d.%d init completed", client->pid, hwctx->fw_ctx_id);
return 0;
destroy_ctx:
aie4_hwctx_destroy(hwctx, AIE4_HWCTX_NORMAL);
+suspend_put:
+ amdxdna_pm_suspend_put(xdna);
umq_fini:
aie4_hwctx_umq_fini(hwctx);
destroy_lock:
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index 70a052ab5f77..60140c3927a2 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -1041,6 +1041,7 @@ static int aie4_classic_init(struct amdxdna_dev *xdna)
if (ret)
goto free_work_buf;
+ amdxdna_pm_init(xdna);
return 0;
free_work_buf:
@@ -1064,6 +1065,7 @@ static void aie4_vf_fini(struct amdxdna_dev *xdna)
static void aie4_classic_fini(struct amdxdna_dev *xdna)
{
+ amdxdna_pm_fini(xdna);
aie4_classic_hw_stop(xdna->dev_handle);
aie4_free_fw_log_buffer(xdna->dev_handle);
aie4_free_work_buffer(xdna->dev_handle);
@@ -1408,4 +1410,6 @@ const struct amdxdna_dev_ops aie4_classic_ops = {
.set_aie_state = aie4_set_state,
.resume = pm_ptr(aie4_classic_resume),
.suspend = pm_ptr(aie4_classic_suspend),
+ .runtime_resume = pm_ptr(aie4_classic_resume),
+ .runtime_suspend = pm_ptr(aie4_classic_suspend),
};
diff --git a/drivers/accel/amdxdna/amdxdna_ctx.c b/drivers/accel/amdxdna/amdxdna_ctx.c
index 608b86fe8f6b..f4004630dc1b 100644
--- a/drivers/accel/amdxdna/amdxdna_ctx.c
+++ b/drivers/accel/amdxdna/amdxdna_ctx.c
@@ -761,13 +761,32 @@ int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_
return -EINVAL;
}
+static int amdxdna_hwctx_wait_cmd(struct amdxdna_client *client,
+ struct amdxdna_drm_wait_cmd *args)
+{
+ struct amdxdna_dev *xdna = client->xdna;
+ struct amdxdna_hwctx *hwctx;
+ int ret, idx;
+
+ idx = srcu_read_lock(&client->hwctx_srcu);
+ hwctx = xa_load(&client->hwctx_xa, args->hwctx);
+ if (!hwctx) {
+ XDNA_DBG(xdna, "PID %d failed to get ctx %d", client->pid, args->hwctx);
+ ret = -EINVAL;
+ } else {
+ ret = xdna->dev_info->ops->cmd_wait(hwctx, args->seq, args->timeout);
+ }
+ srcu_read_unlock(&client->hwctx_srcu, idx);
+
+ return ret;
+}
+
int amdxdna_drm_wait_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
struct amdxdna_client *client = filp->driver_priv;
struct amdxdna_dev *xdna = to_xdna_dev(dev);
struct amdxdna_drm_wait_cmd *args = data;
- struct amdxdna_hwctx *hwctx;
- int ret, idx;
+ int ret;
XDNA_DBG(xdna, "PID %d ctx %d timeout set %d ms for cmd %llu",
client->pid, args->hwctx, args->timeout, args->seq);
@@ -775,22 +794,26 @@ int amdxdna_drm_wait_cmd_ioctl(struct drm_device *dev, void *data, struct drm_fi
if (!xdna->dev_info->ops->cmd_wait)
return -EOPNOTSUPP;
- idx = srcu_read_lock(&client->hwctx_srcu);
- hwctx = xa_load(&client->hwctx_xa, args->hwctx);
- if (!hwctx) {
- XDNA_DBG(xdna, "PID %d failed to get ctx %d", client->pid, args->hwctx);
- ret = -EINVAL;
- goto unlock_ctx_srcu;
+ ret = amdxdna_hwctx_wait_cmd(client, args);
+ if (ret == -EAGAIN) {
+ /*
+ * Suspended by power management before the command completed.
+ * Resume the device, which reconnects the context, and wait
+ * again. Take the PM reference outside hwctx_srcu: runtime
+ * resume takes dev_lock, which hwctx destroy holds across
+ * synchronize_srcu().
+ */
+ ret = amdxdna_pm_resume_get(xdna);
+ if (ret)
+ return ret;
+ ret = amdxdna_hwctx_wait_cmd(client, args);
+ amdxdna_pm_suspend_put(xdna);
}
- ret = xdna->dev_info->ops->cmd_wait(hwctx, args->seq, args->timeout);
-
XDNA_DBG(xdna, "PID %d ctx %d cmd %lld wait finished, ret %d",
client->pid, args->hwctx, args->seq, ret);
trace_amdxdna_debug_point(current->comm, args->seq, "job returned to user");
-unlock_ctx_srcu:
- srcu_read_unlock(&client->hwctx_srcu, idx);
return ret;
}
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c
index f5f7831c4e80..cb78f145ffa1 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.c
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c
@@ -465,7 +465,7 @@ static void amdxdna_remove(struct pci_dev *pdev)
static const struct dev_pm_ops amdxdna_pm_ops = {
SYSTEM_SLEEP_PM_OPS(amdxdna_pm_suspend, amdxdna_pm_resume)
- RUNTIME_PM_OPS(amdxdna_pm_suspend, amdxdna_pm_resume, NULL)
+ RUNTIME_PM_OPS(amdxdna_pm_runtime_suspend, amdxdna_pm_runtime_resume, NULL)
};
static int amdxdna_sriov_configure(struct pci_dev *pdev, int num_vfs)
@@ -484,7 +484,7 @@ static struct pci_driver amdxdna_pci_driver = {
.id_table = pci_ids,
.probe = amdxdna_probe,
.remove = amdxdna_remove,
- .driver.pm = &amdxdna_pm_ops,
+ .driver.pm = pm_ptr(&amdxdna_pm_ops),
.sriov_configure = amdxdna_sriov_configure,
};
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
index 505477b4a292..4d047cf3d981 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -57,6 +57,8 @@ struct amdxdna_dev_ops {
void (*debugfs_init)(struct amdxdna_dev *xdna);
int (*resume)(struct amdxdna_dev *xdna);
int (*suspend)(struct amdxdna_dev *xdna);
+ int (*runtime_resume)(struct amdxdna_dev *xdna);
+ int (*runtime_suspend)(struct amdxdna_dev *xdna);
int (*sriov_configure)(struct amdxdna_dev *xdna, int num_vfs);
int (*hwctx_init)(struct amdxdna_hwctx *hwctx);
void (*hwctx_stop)(struct amdxdna_hwctx *hwctx);
diff --git a/drivers/accel/amdxdna/amdxdna_pm.c b/drivers/accel/amdxdna/amdxdna_pm.c
index b1fafddd7ad5..7d7bc965342d 100644
--- a/drivers/accel/amdxdna/amdxdna_pm.c
+++ b/drivers/accel/amdxdna/amdxdna_pm.c
@@ -37,11 +37,40 @@ int amdxdna_pm_resume(struct device *dev)
return ret;
}
+int amdxdna_pm_runtime_suspend(struct device *dev)
+{
+ struct amdxdna_dev *xdna = to_xdna_dev(dev_get_drvdata(dev));
+ int ret = -EBUSY;
+
+ guard(mutex)(&xdna->dev_lock);
+ if (xdna->dev_info->ops->runtime_suspend)
+ ret = xdna->dev_info->ops->runtime_suspend(xdna);
+
+ XDNA_DBG(xdna, "Runtime suspend done ret %d", ret);
+ return ret;
+}
+
+int amdxdna_pm_runtime_resume(struct device *dev)
+{
+ struct amdxdna_dev *xdna = to_xdna_dev(dev_get_drvdata(dev));
+ int ret = -EOPNOTSUPP;
+
+ guard(mutex)(&xdna->dev_lock);
+ if (xdna->dev_info->ops->runtime_resume)
+ ret = xdna->dev_info->ops->runtime_resume(xdna);
+
+ XDNA_DBG(xdna, "Runtime resume done ret %d", ret);
+ return ret;
+}
+
int amdxdna_pm_resume_get(struct amdxdna_dev *xdna)
{
struct device *dev = xdna->ddev.dev;
int ret;
+ if (!pm_runtime_enabled(dev))
+ return 0;
+
ret = pm_runtime_resume_and_get(dev);
if (ret) {
XDNA_ERR(xdna, "Resume failed: %d", ret);
@@ -55,6 +84,10 @@ void amdxdna_pm_suspend_put(struct amdxdna_dev *xdna)
{
struct device *dev = xdna->ddev.dev;
+ if (!pm_runtime_enabled(dev))
+ return;
+
+ pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
}
@@ -66,6 +99,7 @@ void amdxdna_pm_init(struct amdxdna_dev *xdna)
pm_runtime_set_autosuspend_delay(dev, AMDXDNA_AUTOSUSPEND_DELAY);
pm_runtime_use_autosuspend(dev);
pm_runtime_allow(dev);
+ pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
}
diff --git a/drivers/accel/amdxdna/amdxdna_pm.h b/drivers/accel/amdxdna/amdxdna_pm.h
index 3d26b973e0e3..02beef6448f1 100644
--- a/drivers/accel/amdxdna/amdxdna_pm.h
+++ b/drivers/accel/amdxdna/amdxdna_pm.h
@@ -10,6 +10,8 @@
int amdxdna_pm_suspend(struct device *dev);
int amdxdna_pm_resume(struct device *dev);
+int amdxdna_pm_runtime_suspend(struct device *dev);
+int amdxdna_pm_runtime_resume(struct device *dev);
int amdxdna_pm_resume_get(struct amdxdna_dev *xdna);
void amdxdna_pm_suspend_put(struct amdxdna_dev *xdna);
void amdxdna_pm_init(struct amdxdna_dev *xdna);
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4 19/19] accel/amdxdna: Implement runtime suspend and resume support
2026-10-09 22:53 ` [PATCH V4 19/19] accel/amdxdna: Implement runtime suspend and resume support David Zhang
@ 2026-10-09 23:17 ` sashiko-bot
0 siblings, 0 replies; 39+ messages in thread
From: sashiko-bot @ 2026-10-09 23:17 UTC (permalink / raw)
To: David Zhang; +Cc: dri-devel
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] amdxdna: Missing runtime PM reference during hardware context destruction
- [Low] amdxdna: Dead code due to unconditional assignment of PM callbacks in aie2_ops
--
commit e84dc9f8e09a4669bbdb0e93c4368ea773cd8d73
Author: David Zhang <yidong.zhang@amd.com>
accel/amdxdna: Implement runtime suspend and resume support
Add runtime suspend/resume for the AIE4 classic device by using its
system suspend/resume handlers.
> diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c
> index 690ad035463c5..a3866e8933e61 100644
> --- a/drivers/accel/amdxdna/aie2_pci.c
> +++ b/drivers/accel/amdxdna/aie2_pci.c
> @@ -1221,6 +1221,8 @@ const struct amdxdna_dev_ops aie2_ops = {
> .fini = aie2_fini,
> .resume = aie2_hw_resume,
> .suspend = aie2_hw_suspend,
> + .runtime_resume = aie2_hw_resume,
> + .runtime_suspend = aie2_hw_suspend,
[Severity: Low]
Are pm_ptr() wrappers missing here?
Unlike aie4_classic_ops, which correctly wraps these assignments in
pm_ptr(), aie2_ops omits the wrappers. When the power management
configuration is disabled, the compiler cannot automatically discard
these functions, resulting in dead code being linked into the kernel.
> .get_aie_info = aie2_get_info,
> .set_aie_state = aie2_set_state,
> .hwctx_init = aie2_hwctx_init,
[ ... ]
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index 70a052ab5f775..60140c3927a2e 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -1041,6 +1041,7 @@ static int aie4_classic_init(struct amdxdna_dev *xdna)
> if (ret)
> goto free_work_buf;
>
> + amdxdna_pm_init(xdna);
[Severity: High]
Could this introduce a bug when destroying hardware contexts while the device
is suspended?
The driver enables runtime autosuspend here, allowing the device to enter
a suspended state when idle. When a user destroys a hardware context,
the destruction path runs without ensuring the device is active:
amdxdna_drm_destroy_hwctx_ioctl()
amdxdna_hwctx_destroy_rcu()
aie4_hwctx_stop()
aie4_hwctx_destroy()
aie4_msg_destroy_context()
None of these destruction paths call amdxdna_pm_resume_get() to wake up the
device.
If the device has autosuspended, the firmware is stopped and the mailbox
is finalized (via aie4_mailbox_fini()). Accessing the mailbox registers
in this state will cause a bus error, system hang, or kernel crash.
> return 0;
>
> free_work_buf:
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009225343.3079074-1-yidong.zhang@amd.com?part=19
^ permalink raw reply [flat|nested] 39+ messages in thread