[PATCH i-g-t 00/11] Prepare lib/intel_compute for SVM/system allocator, part 2

[PATCH i-g-t 00/11] Prepare lib/intel_compute for SVM/system allocator, part 2

[Francois Dugast]

This series contains more preparation work to test SVM/system allocator,
which has now been merge into XeKMD. It is a follow-up of [1].

The first 6 patches should not introduce functional changes. Some small
changes are intentionally not squashed in order to make review easier.

[1] https://patchwork.freedesktop.org/series/144360/

*** BLURB HERE ***

Francois Dugast (11):
  lib/intel_compute: Use common constant for surface state size
  lib/intel_compute: Use common constant for dynamic state size
  lib/intel_compute: Use common constant for indirect object size
  lib/intel_compute: Use common constant for binding table size
  lib/intel_compute: Use common constant for general state size
  lib/intel_compute: Use constant for binding table address
  lib/intel_compute: Compact memory map
  lib/intel_compute: Relocate input and output objects
  lib/intel_compute: Fix enqueued local size in xehp
  lib/intel_compute: Use constants for thread groups and local work size
  lib/intel_compute: Make array size a dynamic parameter

 lib/intel_compute.c | 261 +++++++++++++++++++++++++++-----------------
 lib/intel_compute.h |   2 +
 2 files changed, 160 insertions(+), 103 deletions(-)

-- 
2.43.0

[PATCH i-g-t 01/11] lib/intel_compute: Use common constant for surface state size

[Francois Dugast]

Reduce magic values in the code, homogenize the size which has no
reason to be different among pipelines, define this value close to
the addresses to make it easier to spot potential overlaps in the
future.

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index dd9c83c9c..7d3380186 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -23,10 +23,13 @@
 #define PIPE_CONTROL			0x7a000004
 #define MEDIA_STATE_FLUSH		0x0
 #define MAX(X, Y)			(((X) > (Y)) ? (X) : (Y))
+
 #define SIZE_DATA			64
 #define SIZE_BATCH			0x10000
 #define SIZE_BUFFER_INPUT		MAX(sizeof(float) * SIZE_DATA, 0x10000)
 #define SIZE_BUFFER_OUTPUT		MAX(sizeof(float) * SIZE_DATA, 0x10000)
+#define SIZE_SURFACE_STATE		0x10000
+
 #define ADDR_SYNC			0x010000ULL
 #define ADDR_SYNC2			0x020000ULL
 #define ADDR_BATCH			0x100000ULL
@@ -691,7 +694,7 @@ static void compute_exec(int fd, const unsigned char *kernel,
 		  .size =  0x1000,
 		  .name = "dynamic state base" },
 		{ .addr = ADDR_SURFACE_STATE_BASE,
-		  .size =  0x1000,
+		  .size = SIZE_SURFACE_STATE,
 		  .name = "surface state base" },
 		{ .addr = ADDR_INDIRECT_OBJECT_BASE + OFFSET_INDIRECT_DATA_START,
 		  .size =  0x10000,
@@ -976,7 +979,7 @@ static void xehp_compute_exec(int fd, const unsigned char *kernel,
 		  .size = 0x100000,
 		  .name = "dynamic state base"},
 		{ .addr = ADDR_SURFACE_STATE_BASE,
-		  .size = 0x10000,
+		  .size = SIZE_SURFACE_STATE,
 		  .name = "surface state base"},
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
 		  .size =  0x10000,
@@ -1551,7 +1554,7 @@ static void xelpg_compute_exec(int fd, const unsigned char *kernel,
 		  .size = 0x100000,
 		  .name = "dynamic state base"},
 		{ .addr = ADDR_SURFACE_STATE_BASE,
-		  .size = 0x1000,
+		  .size = SIZE_SURFACE_STATE,
 		  .name = "surface state base"},
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
 		  .size =  0x1000,
@@ -1641,7 +1644,7 @@ static void xe2lpg_compute_exec(int fd, const unsigned char *kernel,
 		  .size = 0x100000,
 		  .name = "dynamic state base"},
 		{ .addr = ADDR_SURFACE_STATE_BASE,
-		  .size = 0x1000,
+		  .size = SIZE_SURFACE_STATE,
 		  .name = "surface state base"},
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
 		  .size =  0x1000,
@@ -1892,7 +1895,7 @@ static void xe2lpg_compute_preempt_exec(int fd, const unsigned char *long_kernel
 		  .size = 0x100000,
 		  .name = "dynamic state base"},
 		{ .addr = ADDR_SURFACE_STATE_BASE,
-		  .size = 0x1000,
+		  .size = SIZE_SURFACE_STATE,
 		  .name = "surface state base"},
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
 		  .size =  0x1000,
-- 
2.43.0

Re: [PATCH i-g-t 01/11] lib/intel_compute: Use common constant for surface state size

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> Reduce magic values in the code, homogenize the size which has no
> reason to be different among pipelines, define this value close to
> the addresses to make it easier to spot potential overlaps in the
> future.
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  lib/intel_compute.c | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index dd9c83c9c..7d3380186 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -23,10 +23,13 @@
>  #define PIPE_CONTROL			0x7a000004
>  #define MEDIA_STATE_FLUSH		0x0
>  #define MAX(X, Y)			(((X) > (Y)) ? (X) : (Y))
> +
>  #define SIZE_DATA			64
>  #define SIZE_BATCH			0x10000
>  #define SIZE_BUFFER_INPUT		MAX(sizeof(float) *
> SIZE_DATA, 0x10000)
>  #define SIZE_BUFFER_OUTPUT		MAX(sizeof(float) *
> SIZE_DATA, 0x10000)
> +#define SIZE_SURFACE_STATE		0x10000
> +
>  #define ADDR_SYNC			0x010000ULL
>  #define ADDR_SYNC2			0x020000ULL
>  #define ADDR_BATCH			0x100000ULL
> @@ -691,7 +694,7 @@ static void compute_exec(int fd, const unsigned
> char *kernel,
>  		  .size =  0x1000,
>  		  .name = "dynamic state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE,
> -		  .size =  0x1000,
> +		  .size = SIZE_SURFACE_STATE,
>  		  .name = "surface state base" },
>  		{ .addr = ADDR_INDIRECT_OBJECT_BASE +
> OFFSET_INDIRECT_DATA_START,
>  		  .size =  0x10000,
> @@ -976,7 +979,7 @@ static void xehp_compute_exec(int fd, const
> unsigned char *kernel,
>  		  .size = 0x100000,
>  		  .name = "dynamic state base"},
>  		{ .addr = ADDR_SURFACE_STATE_BASE,
> -		  .size = 0x10000,
> +		  .size = SIZE_SURFACE_STATE,
>  		  .name = "surface state base"},
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
>  		  .size =  0x10000,
> @@ -1551,7 +1554,7 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		  .size = 0x100000,
>  		  .name = "dynamic state base"},
>  		{ .addr = ADDR_SURFACE_STATE_BASE,
> -		  .size = 0x1000,
> +		  .size = SIZE_SURFACE_STATE,
>  		  .name = "surface state base"},
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
>  		  .size =  0x1000,
> @@ -1641,7 +1644,7 @@ static void xe2lpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		  .size = 0x100000,
>  		  .name = "dynamic state base"},
>  		{ .addr = ADDR_SURFACE_STATE_BASE,
> -		  .size = 0x1000,
> +		  .size = SIZE_SURFACE_STATE,
>  		  .name = "surface state base"},
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
>  		  .size =  0x1000,
> @@ -1892,7 +1895,7 @@ static void xe2lpg_compute_preempt_exec(int fd,
> const unsigned char *long_kernel
>  		  .size = 0x100000,
>  		  .name = "dynamic state base"},
>  		{ .addr = ADDR_SURFACE_STATE_BASE,
> -		  .size = 0x1000,
> +		  .size = SIZE_SURFACE_STATE,
>  		  .name = "surface state base"},
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
>  		  .size =  0x1000,

[PATCH i-g-t 02/11] lib/intel_compute: Use common constant for dynamic state size

[Francois Dugast]

Reduce magic values in the code, homogenize the size which has no
reason to be different among pipelines, define this value close to
the addresses to make it easier to spot potential overlaps in the
future.

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index 7d3380186..b4b022ae7 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -29,6 +29,7 @@
 #define SIZE_BUFFER_INPUT		MAX(sizeof(float) * SIZE_DATA, 0x10000)
 #define SIZE_BUFFER_OUTPUT		MAX(sizeof(float) * SIZE_DATA, 0x10000)
 #define SIZE_SURFACE_STATE		0x10000
+#define SIZE_DYNAMIC_STATE		0x100000
 
 #define ADDR_SYNC			0x010000ULL
 #define ADDR_SYNC2			0x020000ULL
@@ -691,7 +692,7 @@ static void compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_INDIRECT_OBJECT_BASE + OFFSET_KERNEL,
 		  .name = "kernel" },
 		{ .addr = ADDR_DYNAMIC_STATE_BASE,
-		  .size =  0x1000,
+		  .size = SIZE_DYNAMIC_STATE,
 		  .name = "dynamic state base" },
 		{ .addr = ADDR_SURFACE_STATE_BASE,
 		  .size = SIZE_SURFACE_STATE,
@@ -976,7 +977,7 @@ static void xehp_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_INSTRUCTION_STATE_BASE + OFFSET_KERNEL,
 		  .name = "instr state base"},
 		{ .addr = ADDR_DYNAMIC_STATE_BASE,
-		  .size = 0x100000,
+		  .size = SIZE_DYNAMIC_STATE,
 		  .name = "dynamic state base"},
 		{ .addr = ADDR_SURFACE_STATE_BASE,
 		  .size = SIZE_SURFACE_STATE,
@@ -1551,7 +1552,7 @@ static void xelpg_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_INSTRUCTION_STATE_BASE + OFFSET_KERNEL,
 		  .name = "instr state base"},
 		{ .addr = ADDR_DYNAMIC_STATE_BASE,
-		  .size = 0x100000,
+		  .size = SIZE_DYNAMIC_STATE,
 		  .name = "dynamic state base"},
 		{ .addr = ADDR_SURFACE_STATE_BASE,
 		  .size = SIZE_SURFACE_STATE,
@@ -1641,7 +1642,7 @@ static void xe2lpg_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_INSTRUCTION_STATE_BASE + OFFSET_KERNEL,
 		  .name = "instr state base"},
 		{ .addr = ADDR_DYNAMIC_STATE_BASE,
-		  .size = 0x100000,
+		  .size = SIZE_DYNAMIC_STATE,
 		  .name = "dynamic state base"},
 		{ .addr = ADDR_SURFACE_STATE_BASE,
 		  .size = SIZE_SURFACE_STATE,
@@ -1892,7 +1893,7 @@ static void xe2lpg_compute_preempt_exec(int fd, const unsigned char *long_kernel
 		{ .addr = ADDR_INSTRUCTION_STATE_BASE + OFFSET_KERNEL,
 		  .name = "instr state base"},
 		{ .addr = ADDR_DYNAMIC_STATE_BASE,
-		  .size = 0x100000,
+		  .size = SIZE_DYNAMIC_STATE,
 		  .name = "dynamic state base"},
 		{ .addr = ADDR_SURFACE_STATE_BASE,
 		  .size = SIZE_SURFACE_STATE,
-- 
2.43.0

Re: [PATCH i-g-t 02/11] lib/intel_compute: Use common constant for dynamic state size

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> Reduce magic values in the code, homogenize the size which has no
> reason to be different among pipelines, define this value close to
> the addresses to make it easier to spot potential overlaps in the
> future.
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  lib/intel_compute.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index 7d3380186..b4b022ae7 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -29,6 +29,7 @@
>  #define SIZE_BUFFER_INPUT		MAX(sizeof(float) *
> SIZE_DATA, 0x10000)
>  #define SIZE_BUFFER_OUTPUT		MAX(sizeof(float) *
> SIZE_DATA, 0x10000)
>  #define SIZE_SURFACE_STATE		0x10000
> +#define SIZE_DYNAMIC_STATE		0x100000
>  
>  #define ADDR_SYNC			0x010000ULL
>  #define ADDR_SYNC2			0x020000ULL
> @@ -691,7 +692,7 @@ static void compute_exec(int fd, const unsigned
> char *kernel,
>  		{ .addr = ADDR_INDIRECT_OBJECT_BASE + OFFSET_KERNEL,
>  		  .name = "kernel" },
>  		{ .addr = ADDR_DYNAMIC_STATE_BASE,
> -		  .size =  0x1000,
> +		  .size = SIZE_DYNAMIC_STATE,
>  		  .name = "dynamic state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE,
>  		  .size = SIZE_SURFACE_STATE,
> @@ -976,7 +977,7 @@ static void xehp_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_INSTRUCTION_STATE_BASE +
> OFFSET_KERNEL,
>  		  .name = "instr state base"},
>  		{ .addr = ADDR_DYNAMIC_STATE_BASE,
> -		  .size = 0x100000,
> +		  .size = SIZE_DYNAMIC_STATE,
>  		  .name = "dynamic state base"},
>  		{ .addr = ADDR_SURFACE_STATE_BASE,
>  		  .size = SIZE_SURFACE_STATE,
> @@ -1551,7 +1552,7 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_INSTRUCTION_STATE_BASE +
> OFFSET_KERNEL,
>  		  .name = "instr state base"},
>  		{ .addr = ADDR_DYNAMIC_STATE_BASE,
> -		  .size = 0x100000,
> +		  .size = SIZE_DYNAMIC_STATE,
>  		  .name = "dynamic state base"},
>  		{ .addr = ADDR_SURFACE_STATE_BASE,
>  		  .size = SIZE_SURFACE_STATE,
> @@ -1641,7 +1642,7 @@ static void xe2lpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_INSTRUCTION_STATE_BASE +
> OFFSET_KERNEL,
>  		  .name = "instr state base"},
>  		{ .addr = ADDR_DYNAMIC_STATE_BASE,
> -		  .size = 0x100000,
> +		  .size = SIZE_DYNAMIC_STATE,
>  		  .name = "dynamic state base"},
>  		{ .addr = ADDR_SURFACE_STATE_BASE,
>  		  .size = SIZE_SURFACE_STATE,
> @@ -1892,7 +1893,7 @@ static void xe2lpg_compute_preempt_exec(int fd,
> const unsigned char *long_kernel
>  		{ .addr = ADDR_INSTRUCTION_STATE_BASE +
> OFFSET_KERNEL,
>  		  .name = "instr state base"},
>  		{ .addr = ADDR_DYNAMIC_STATE_BASE,
> -		  .size = 0x100000,
> +		  .size = SIZE_DYNAMIC_STATE,
>  		  .name = "dynamic state base"},
>  		{ .addr = ADDR_SURFACE_STATE_BASE,
>  		  .size = SIZE_SURFACE_STATE,

[PATCH i-g-t 03/11] lib/intel_compute: Use common constant for indirect object size

[Francois Dugast]

Reduce magic values in the code, homogenize the size which has no
reason to be different among pipelines, define this value close to
the addresses to make it easier to spot potential overlaps in the
future.

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index b4b022ae7..e3c8cf244 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -30,6 +30,7 @@
 #define SIZE_BUFFER_OUTPUT		MAX(sizeof(float) * SIZE_DATA, 0x10000)
 #define SIZE_SURFACE_STATE		0x10000
 #define SIZE_DYNAMIC_STATE		0x100000
+#define SIZE_INDIRECT_OBJECT		0x10000
 
 #define ADDR_SYNC			0x010000ULL
 #define ADDR_SYNC2			0x020000ULL
@@ -698,7 +699,7 @@ static void compute_exec(int fd, const unsigned char *kernel,
 		  .size = SIZE_SURFACE_STATE,
 		  .name = "surface state base" },
 		{ .addr = ADDR_INDIRECT_OBJECT_BASE + OFFSET_INDIRECT_DATA_START,
-		  .size =  0x10000,
+		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect data start" },
 		{ .addr = ADDR_INPUT,
 		  .size = SIZE_BUFFER_INPUT,
@@ -983,7 +984,7 @@ static void xehp_compute_exec(int fd, const unsigned char *kernel,
 		  .size = SIZE_SURFACE_STATE,
 		  .name = "surface state base"},
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
-		  .size =  0x10000,
+		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect object base"},
 		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
 		  .name = "addr input"},
@@ -1200,7 +1201,7 @@ static void xehpc_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_INSTRUCTION_STATE_BASE + OFFSET_KERNEL,
 		  .name = "instr state base"},
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
-		  .size =  0x10000,
+		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect object base"},
 		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
 		  .name = "addr input"},
@@ -1558,7 +1559,7 @@ static void xelpg_compute_exec(int fd, const unsigned char *kernel,
 		  .size = SIZE_SURFACE_STATE,
 		  .name = "surface state base"},
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
-		  .size =  0x1000,
+		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect object base"},
 		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
 		  .name = "addr input"},
@@ -1648,7 +1649,7 @@ static void xe2lpg_compute_exec(int fd, const unsigned char *kernel,
 		  .size = SIZE_SURFACE_STATE,
 		  .name = "surface state base"},
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
-		  .size =  0x1000,
+		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect object base"},
 		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
 		  .name = "addr input"},
@@ -1899,7 +1900,7 @@ static void xe2lpg_compute_preempt_exec(int fd, const unsigned char *long_kernel
 		  .size = SIZE_SURFACE_STATE,
 		  .name = "surface state base"},
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
-		  .size =  0x1000,
+		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect object base"},
 		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
 		  .name = "addr input"},
-- 
2.43.0

Re: [PATCH i-g-t 03/11] lib/intel_compute: Use common constant for indirect object size

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> Reduce magic values in the code, homogenize the size which has no
> reason to be different among pipelines, define this value close to
> the addresses to make it easier to spot potential overlaps in the
> future.
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  lib/intel_compute.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index b4b022ae7..e3c8cf244 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -30,6 +30,7 @@
>  #define SIZE_BUFFER_OUTPUT		MAX(sizeof(float) *
> SIZE_DATA, 0x10000)
>  #define SIZE_SURFACE_STATE		0x10000
>  #define SIZE_DYNAMIC_STATE		0x100000
> +#define SIZE_INDIRECT_OBJECT		0x10000
>  
>  #define ADDR_SYNC			0x010000ULL
>  #define ADDR_SYNC2			0x020000ULL
> @@ -698,7 +699,7 @@ static void compute_exec(int fd, const unsigned
> char *kernel,
>  		  .size = SIZE_SURFACE_STATE,
>  		  .name = "surface state base" },
>  		{ .addr = ADDR_INDIRECT_OBJECT_BASE +
> OFFSET_INDIRECT_DATA_START,
> -		  .size =  0x10000,
> +		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect data start" },
>  		{ .addr = ADDR_INPUT,
>  		  .size = SIZE_BUFFER_INPUT,
> @@ -983,7 +984,7 @@ static void xehp_compute_exec(int fd, const
> unsigned char *kernel,
>  		  .size = SIZE_SURFACE_STATE,
>  		  .name = "surface state base"},
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
> -		  .size =  0x10000,
> +		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect object base"},
>  		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
>  		  .name = "addr input"},
> @@ -1200,7 +1201,7 @@ static void xehpc_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_INSTRUCTION_STATE_BASE +
> OFFSET_KERNEL,
>  		  .name = "instr state base"},
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
> -		  .size =  0x10000,
> +		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect object base"},
>  		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
>  		  .name = "addr input"},
> @@ -1558,7 +1559,7 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		  .size = SIZE_SURFACE_STATE,
>  		  .name = "surface state base"},
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
> -		  .size =  0x1000,
> +		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect object base"},
>  		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
>  		  .name = "addr input"},
> @@ -1648,7 +1649,7 @@ static void xe2lpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		  .size = SIZE_SURFACE_STATE,
>  		  .name = "surface state base"},
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
> -		  .size =  0x1000,
> +		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect object base"},
>  		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
>  		  .name = "addr input"},
> @@ -1899,7 +1900,7 @@ static void xe2lpg_compute_preempt_exec(int fd,
> const unsigned char *long_kernel
>  		  .size = SIZE_SURFACE_STATE,
>  		  .name = "surface state base"},
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
> -		  .size =  0x1000,
> +		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect object base"},
>  		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
>  		  .name = "addr input"},

[PATCH i-g-t 04/11] lib/intel_compute: Use common constant for binding table size

[Francois Dugast]

Reduce magic values in the code, homogenize the size which has no
reason to be different among pipelines, define this value close to
the addresses to make it easier to spot potential overlaps in the
future.

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index e3c8cf244..a85fd8121 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -31,6 +31,7 @@
 #define SIZE_SURFACE_STATE		0x10000
 #define SIZE_DYNAMIC_STATE		0x100000
 #define SIZE_INDIRECT_OBJECT		0x10000
+#define SIZE_BINDING_TABLE		0x10000
 
 #define ADDR_SYNC			0x010000ULL
 #define ADDR_SYNC2			0x020000ULL
@@ -993,7 +994,7 @@ static void xehp_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
 		  .name = "general state base" },
 		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
-		  .size = 0x10000,
+		  .size = SIZE_BINDING_TABLE,
 		  .name = "binding table" },
 		{ .addr = ADDR_BATCH, .size = SIZE_BATCH,
 		  .name = "batch" },
@@ -1568,7 +1569,7 @@ static void xelpg_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
 		  .name = "general state base" },
 		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
-		  .size = 0x1000,
+		  .size = SIZE_BINDING_TABLE,
 		  .name = "binding table" },
 		{ .addr = ADDR_BATCH,
 		  .size = SIZE_BATCH,
@@ -1658,7 +1659,7 @@ static void xe2lpg_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
 		  .name = "general state base" },
 		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
-		  .size = 0x1000,
+		  .size = SIZE_BINDING_TABLE,
 		  .name = "binding table" },
 		{ .addr = ADDR_BATCH,
 		  .size = SIZE_BATCH,
@@ -1909,7 +1910,7 @@ static void xe2lpg_compute_preempt_exec(int fd, const unsigned char *long_kernel
 		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
 		  .name = "general state base" },
 		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
-		  .size = 0x1000,
+		  .size = SIZE_BINDING_TABLE,
 		  .name = "binding table" },
 		{ .addr = ADDR_BATCH,
 		  .size = SIZE_BATCH,
-- 
2.43.0

Re: [PATCH i-g-t 04/11] lib/intel_compute: Use common constant for binding table size

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> Reduce magic values in the code, homogenize the size which has no
> reason to be different among pipelines, define this value close to
> the addresses to make it easier to spot potential overlaps in the
> future.
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  lib/intel_compute.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index e3c8cf244..a85fd8121 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -31,6 +31,7 @@
>  #define SIZE_SURFACE_STATE		0x10000
>  #define SIZE_DYNAMIC_STATE		0x100000
>  #define SIZE_INDIRECT_OBJECT		0x10000
> +#define SIZE_BINDING_TABLE		0x10000
>  
>  #define ADDR_SYNC			0x010000ULL
>  #define ADDR_SYNC2			0x020000ULL
> @@ -993,7 +994,7 @@ static void xehp_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> -		  .size = 0x10000,
> +		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH, .size = SIZE_BATCH,
>  		  .name = "batch" },
> @@ -1568,7 +1569,7 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> -		  .size = 0x1000,
> +		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH,
>  		  .size = SIZE_BATCH,
> @@ -1658,7 +1659,7 @@ static void xe2lpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> -		  .size = 0x1000,
> +		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH,
>  		  .size = SIZE_BATCH,
> @@ -1909,7 +1910,7 @@ static void xe2lpg_compute_preempt_exec(int fd,
> const unsigned char *long_kernel
>  		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> -		  .size = 0x1000,
> +		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH,
>  		  .size = SIZE_BATCH,

Re: [PATCH i-g-t 04/11] lib/intel_compute: Use common constant for binding table size

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> Reduce magic values in the code, homogenize the size which has no
> reason to be different among pipelines, define this value close to
> the addresses to make it easier to spot potential overlaps in the
> future.
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  lib/intel_compute.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index e3c8cf244..a85fd8121 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -31,6 +31,7 @@
>  #define SIZE_SURFACE_STATE		0x10000
>  #define SIZE_DYNAMIC_STATE		0x100000
>  #define SIZE_INDIRECT_OBJECT		0x10000
> +#define SIZE_BINDING_TABLE		0x10000
>  
>  #define ADDR_SYNC			0x010000ULL
>  #define ADDR_SYNC2			0x020000ULL
> @@ -993,7 +994,7 @@ static void xehp_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> -		  .size = 0x10000,
> +		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH, .size = SIZE_BATCH,
>  		  .name = "batch" },
> @@ -1568,7 +1569,7 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> -		  .size = 0x1000,
> +		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH,
>  		  .size = SIZE_BATCH,
> @@ -1658,7 +1659,7 @@ static void xe2lpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> -		  .size = 0x1000,
> +		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH,
>  		  .size = SIZE_BATCH,
> @@ -1909,7 +1910,7 @@ static void xe2lpg_compute_preempt_exec(int fd,
> const unsigned char *long_kernel
>  		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> -		  .size = 0x1000,
> +		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH,
>  		  .size = SIZE_BATCH,

[PATCH i-g-t 05/11] lib/intel_compute: Use common constant for general state size

[Francois Dugast]

Reduce magic values in the code, homogenize the size which has no
reason to be different among pipelines, define this value close to
the addresses to make it easier to spot potential overlaps in the
future.

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index a85fd8121..302a1d35c 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -32,6 +32,7 @@
 #define SIZE_DYNAMIC_STATE		0x100000
 #define SIZE_INDIRECT_OBJECT		0x10000
 #define SIZE_BINDING_TABLE		0x10000
+#define SIZE_GENERAL_STATE		0x100000
 
 #define ADDR_SYNC			0x010000ULL
 #define ADDR_SYNC2			0x020000ULL
@@ -991,7 +992,8 @@ static void xehp_compute_exec(int fd, const unsigned char *kernel,
 		  .name = "addr input"},
 		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
 		  .name = "addr output" },
-		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
+		{ .addr = ADDR_GENERAL_STATE_BASE,
+		  .size = SIZE_GENERAL_STATE,
 		  .name = "general state base" },
 		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
 		  .size = SIZE_BINDING_TABLE,
@@ -1208,7 +1210,8 @@ static void xehpc_compute_exec(int fd, const unsigned char *kernel,
 		  .name = "addr input"},
 		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
 		  .name = "addr output" },
-		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x10000,
+		{ .addr = ADDR_GENERAL_STATE_BASE,
+		  .size = SIZE_GENERAL_STATE,
 		  .name = "general state base" },
 		{ .addr = ADDR_BATCH, .size = SIZE_BATCH,
 		  .name = "batch" },
@@ -1566,7 +1569,8 @@ static void xelpg_compute_exec(int fd, const unsigned char *kernel,
 		  .name = "addr input"},
 		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
 		  .name = "addr output" },
-		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
+		{ .addr = ADDR_GENERAL_STATE_BASE,
+		  .size = SIZE_GENERAL_STATE,
 		  .name = "general state base" },
 		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
 		  .size = SIZE_BINDING_TABLE,
@@ -1656,7 +1660,8 @@ static void xe2lpg_compute_exec(int fd, const unsigned char *kernel,
 		  .name = "addr input"},
 		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
 		  .name = "addr output" },
-		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
+		{ .addr = ADDR_GENERAL_STATE_BASE,
+		  .size = SIZE_GENERAL_STATE,
 		  .name = "general state base" },
 		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
 		  .size = SIZE_BINDING_TABLE,
@@ -1907,7 +1912,8 @@ static void xe2lpg_compute_preempt_exec(int fd, const unsigned char *long_kernel
 		  .name = "addr input"},
 		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
 		  .name = "addr output" },
-		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
+		{ .addr = ADDR_GENERAL_STATE_BASE,
+		  .size = SIZE_GENERAL_STATE,
 		  .name = "general state base" },
 		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
 		  .size = SIZE_BINDING_TABLE,
-- 
2.43.0

Re: [PATCH i-g-t 05/11] lib/intel_compute: Use common constant for general state size

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> Reduce magic values in the code, homogenize the size which has no
> reason to be different among pipelines, define this value close to
> the addresses to make it easier to spot potential overlaps in the
> future.
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  lib/intel_compute.c | 16 +++++++++++-----
>  1 file changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index a85fd8121..302a1d35c 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -32,6 +32,7 @@
>  #define SIZE_DYNAMIC_STATE		0x100000
>  #define SIZE_INDIRECT_OBJECT		0x10000
>  #define SIZE_BINDING_TABLE		0x10000
> +#define SIZE_GENERAL_STATE		0x100000
>  
>  #define ADDR_SYNC			0x010000ULL
>  #define ADDR_SYNC2			0x020000ULL
> @@ -991,7 +992,8 @@ static void xehp_compute_exec(int fd, const
> unsigned char *kernel,
>  		  .name = "addr input"},
>  		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
>  		  .name = "addr output" },
> -		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
> +		{ .addr = ADDR_GENERAL_STATE_BASE,
> +		  .size = SIZE_GENERAL_STATE,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
>  		  .size = SIZE_BINDING_TABLE,
> @@ -1208,7 +1210,8 @@ static void xehpc_compute_exec(int fd, const
> unsigned char *kernel,
>  		  .name = "addr input"},
>  		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
>  		  .name = "addr output" },
> -		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x10000,
> +		{ .addr = ADDR_GENERAL_STATE_BASE,
> +		  .size = SIZE_GENERAL_STATE,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_BATCH, .size = SIZE_BATCH,
>  		  .name = "batch" },
> @@ -1566,7 +1569,8 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		  .name = "addr input"},
>  		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
>  		  .name = "addr output" },
> -		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
> +		{ .addr = ADDR_GENERAL_STATE_BASE,
> +		  .size = SIZE_GENERAL_STATE,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
>  		  .size = SIZE_BINDING_TABLE,
> @@ -1656,7 +1660,8 @@ static void xe2lpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		  .name = "addr input"},
>  		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
>  		  .name = "addr output" },
> -		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
> +		{ .addr = ADDR_GENERAL_STATE_BASE,
> +		  .size = SIZE_GENERAL_STATE,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
>  		  .size = SIZE_BINDING_TABLE,
> @@ -1907,7 +1912,8 @@ static void xe2lpg_compute_preempt_exec(int fd,
> const unsigned char *long_kernel
>  		  .name = "addr input"},
>  		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
>  		  .name = "addr output" },
> -		{ .addr = ADDR_GENERAL_STATE_BASE, .size = 0x100000,
> +		{ .addr = ADDR_GENERAL_STATE_BASE,
> +		  .size = SIZE_GENERAL_STATE,
>  		  .name = "general state base" },
>  		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
>  		  .size = SIZE_BINDING_TABLE,

[PATCH i-g-t 06/11] lib/intel_compute: Use constant for binding table address

[Francois Dugast]

The binding address is the same, no need to duplicate its definition
for each pipeline.

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index 302a1d35c..79c0f0f00 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -42,6 +42,7 @@
 #define ADDR_SURFACE_STATE_BASE		0x400000ULL
 #define ADDR_DYNAMIC_STATE_BASE		0x500000ULL
 #define ADDR_INDIRECT_OBJECT_BASE	0x100000000
+#define ADDR_BINDING_TABLE		(ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE)
 #define OFFSET_INDIRECT_DATA_START	0xFFFD0000
 #define OFFSET_KERNEL			0xFFFE0000
 
@@ -995,7 +996,7 @@ static void xehp_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_GENERAL_STATE_BASE,
 		  .size = SIZE_GENERAL_STATE,
 		  .name = "general state base" },
-		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
+		{ .addr = ADDR_BINDING_TABLE,
 		  .size = SIZE_BINDING_TABLE,
 		  .name = "binding table" },
 		{ .addr = ADDR_BATCH, .size = SIZE_BATCH,
@@ -1572,7 +1573,7 @@ static void xelpg_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_GENERAL_STATE_BASE,
 		  .size = SIZE_GENERAL_STATE,
 		  .name = "general state base" },
-		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
+		{ .addr = ADDR_BINDING_TABLE,
 		  .size = SIZE_BINDING_TABLE,
 		  .name = "binding table" },
 		{ .addr = ADDR_BATCH,
@@ -1663,7 +1664,7 @@ static void xe2lpg_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_GENERAL_STATE_BASE,
 		  .size = SIZE_GENERAL_STATE,
 		  .name = "general state base" },
-		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
+		{ .addr = ADDR_BINDING_TABLE,
 		  .size = SIZE_BINDING_TABLE,
 		  .name = "binding table" },
 		{ .addr = ADDR_BATCH,
@@ -1915,7 +1916,7 @@ static void xe2lpg_compute_preempt_exec(int fd, const unsigned char *long_kernel
 		{ .addr = ADDR_GENERAL_STATE_BASE,
 		  .size = SIZE_GENERAL_STATE,
 		  .name = "general state base" },
-		{ .addr = ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE,
+		{ .addr = ADDR_BINDING_TABLE,
 		  .size = SIZE_BINDING_TABLE,
 		  .name = "binding table" },
 		{ .addr = ADDR_BATCH,
-- 
2.43.0

Re: [PATCH i-g-t 06/11] lib/intel_compute: Use constant for binding table address

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> The binding address is the same, no need to duplicate its definition
> for each pipeline.
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  lib/intel_compute.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index 302a1d35c..79c0f0f00 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -42,6 +42,7 @@
>  #define ADDR_SURFACE_STATE_BASE		0x400000ULL
>  #define ADDR_DYNAMIC_STATE_BASE		0x500000ULL
>  #define ADDR_INDIRECT_OBJECT_BASE	0x100000000
> +#define ADDR_BINDING_TABLE		(ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE)
>  #define OFFSET_INDIRECT_DATA_START	0xFFFD0000
>  #define OFFSET_KERNEL			0xFFFE0000
>  
> @@ -995,7 +996,7 @@ static void xehp_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE,
>  		  .size = SIZE_GENERAL_STATE,
>  		  .name = "general state base" },
> -		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> +		{ .addr = ADDR_BINDING_TABLE,
>  		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH, .size = SIZE_BATCH,
> @@ -1572,7 +1573,7 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE,
>  		  .size = SIZE_GENERAL_STATE,
>  		  .name = "general state base" },
> -		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> +		{ .addr = ADDR_BINDING_TABLE,
>  		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH,
> @@ -1663,7 +1664,7 @@ static void xe2lpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE,
>  		  .size = SIZE_GENERAL_STATE,
>  		  .name = "general state base" },
> -		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> +		{ .addr = ADDR_BINDING_TABLE,
>  		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH,
> @@ -1915,7 +1916,7 @@ static void xe2lpg_compute_preempt_exec(int fd,
> const unsigned char *long_kernel
>  		{ .addr = ADDR_GENERAL_STATE_BASE,
>  		  .size = SIZE_GENERAL_STATE,
>  		  .name = "general state base" },
> -		{ .addr = ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE,
> +		{ .addr = ADDR_BINDING_TABLE,
>  		  .size = SIZE_BINDING_TABLE,
>  		  .name = "binding table" },
>  		{ .addr = ADDR_BATCH,

[PATCH i-g-t 07/11] lib/intel_compute: Compact memory map

[Francois Dugast]

Bring the objects close to each other at the beginning of the memory
space to reduce distribution and make room for very large contiguous
memory ranges for user buffers.

For compute square, memory after ADDR_INSTRUCTION_STATE_BASE + kernel
size is now free.

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index 79c0f0f00..364388e20 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -41,16 +41,16 @@
 #define ADDR_OUTPUT			0x300000ULL
 #define ADDR_SURFACE_STATE_BASE		0x400000ULL
 #define ADDR_DYNAMIC_STATE_BASE		0x500000ULL
-#define ADDR_INDIRECT_OBJECT_BASE	0x100000000
+#define ADDR_INDIRECT_OBJECT_BASE	0x600000ULL
 #define ADDR_BINDING_TABLE		(ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE)
-#define OFFSET_INDIRECT_DATA_START	0xFFFD0000
-#define OFFSET_KERNEL			0xFFFE0000
+#define OFFSET_INDIRECT_DATA_START	0x5D0000ULL
+#define OFFSET_KERNEL			0x5E0000ULL
 
-#define ADDR_GENERAL_STATE_BASE		0x80000000ULL
-#define ADDR_INSTRUCTION_STATE_BASE	0x90000000ULL
+#define ADDR_GENERAL_STATE_BASE		0x8000000ULL
+#define ADDR_INSTRUCTION_STATE_BASE	0xa000000ULL
 #define OFFSET_BINDING_TABLE		0x10000
 
-#define XE2_ADDR_STATE_CONTEXT_DATA_BASE	0x900000ULL
+#define XE2_ADDR_STATE_CONTEXT_DATA_BASE	0xb000000ULL
 #define OFFSET_STATE_SIP			0xFFFF0000
 
 #define USER_FENCE_VALUE			0xdeadbeefdeadbeefull
-- 
2.43.0

Re: [PATCH i-g-t 07/11] lib/intel_compute: Compact memory map

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> Bring the objects close to each other at the beginning of the memory
> space to reduce distribution and make room for very large contiguous
> memory ranges for user buffers.
> 
> For compute square, memory after ADDR_INSTRUCTION_STATE_BASE + kernel
> size is now free.
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  lib/intel_compute.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index 79c0f0f00..364388e20 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -41,16 +41,16 @@
>  #define ADDR_OUTPUT			0x300000ULL
>  #define ADDR_SURFACE_STATE_BASE		0x400000ULL
>  #define ADDR_DYNAMIC_STATE_BASE		0x500000ULL
> -#define ADDR_INDIRECT_OBJECT_BASE	0x100000000
> +#define ADDR_INDIRECT_OBJECT_BASE	0x600000ULL
>  #define ADDR_BINDING_TABLE		(ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE)
> -#define OFFSET_INDIRECT_DATA_START	0xFFFD0000
> -#define OFFSET_KERNEL			0xFFFE0000
> +#define OFFSET_INDIRECT_DATA_START	0x5D0000ULL
> +#define OFFSET_KERNEL			0x5E0000ULL
>  
> -#define ADDR_GENERAL_STATE_BASE		0x80000000ULL
> -#define ADDR_INSTRUCTION_STATE_BASE	0x90000000ULL
> +#define ADDR_GENERAL_STATE_BASE		0x8000000ULL
> +#define ADDR_INSTRUCTION_STATE_BASE	0xa000000ULL
>  #define OFFSET_BINDING_TABLE		0x10000
>  
> -#define XE2_ADDR_STATE_CONTEXT_DATA_BASE	0x900000ULL
> +#define XE2_ADDR_STATE_CONTEXT_DATA_BASE	0xb000000ULL
>  #define OFFSET_STATE_SIP			0xFFFF0000
>  
>  #define
> USER_FENCE_VALUE			0xdeadbeefdeadbeefull

[PATCH i-g-t 08/11] lib/intel_compute: Relocate input and output objects

[Francois Dugast]

Move those objects after other objects and add space between them to
make it possible to increase their dimension without overlapping
between input and output.

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index 364388e20..7a2e04b10 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -37,20 +37,20 @@
 #define ADDR_SYNC			0x010000ULL
 #define ADDR_SYNC2			0x020000ULL
 #define ADDR_BATCH			0x100000ULL
-#define ADDR_INPUT			0x200000ULL
-#define ADDR_OUTPUT			0x300000ULL
-#define ADDR_SURFACE_STATE_BASE		0x400000ULL
-#define ADDR_DYNAMIC_STATE_BASE		0x500000ULL
-#define ADDR_INDIRECT_OBJECT_BASE	0x600000ULL
+#define ADDR_INPUT			0x40000000ULL
+#define ADDR_OUTPUT			0x80000000ULL
+#define ADDR_SURFACE_STATE_BASE		0x200000ULL
+#define ADDR_DYNAMIC_STATE_BASE		0x300000ULL
+#define ADDR_INDIRECT_OBJECT_BASE	0x400000ULL
 #define ADDR_BINDING_TABLE		(ADDR_SURFACE_STATE_BASE + OFFSET_BINDING_TABLE)
-#define OFFSET_INDIRECT_DATA_START	0x5D0000ULL
-#define OFFSET_KERNEL			0x5E0000ULL
+#define OFFSET_INDIRECT_DATA_START	0x3D0000ULL
+#define OFFSET_KERNEL			0x3E0000ULL
 
-#define ADDR_GENERAL_STATE_BASE		0x8000000ULL
-#define ADDR_INSTRUCTION_STATE_BASE	0xa000000ULL
+#define ADDR_GENERAL_STATE_BASE		0x6000000ULL
+#define ADDR_INSTRUCTION_STATE_BASE	0x8000000ULL
 #define OFFSET_BINDING_TABLE		0x10000
 
-#define XE2_ADDR_STATE_CONTEXT_DATA_BASE	0xb000000ULL
+#define XE2_ADDR_STATE_CONTEXT_DATA_BASE	0x9000000ULL
 #define OFFSET_STATE_SIP			0xFFFF0000
 
 #define USER_FENCE_VALUE			0xdeadbeefdeadbeefull
-- 
2.43.0

Re: [PATCH i-g-t 08/11] lib/intel_compute: Relocate input and output objects

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> Move those objects after other objects and add space between them to
> make it possible to increase their dimension without overlapping
> between input and output.
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  lib/intel_compute.c | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index 364388e20..7a2e04b10 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -37,20 +37,20 @@
>  #define ADDR_SYNC			0x010000ULL
>  #define ADDR_SYNC2			0x020000ULL
>  #define ADDR_BATCH			0x100000ULL
> -#define ADDR_INPUT			0x200000ULL
> -#define ADDR_OUTPUT			0x300000ULL
> -#define ADDR_SURFACE_STATE_BASE		0x400000ULL
> -#define ADDR_DYNAMIC_STATE_BASE		0x500000ULL
> -#define ADDR_INDIRECT_OBJECT_BASE	0x600000ULL
> +#define ADDR_INPUT			0x40000000ULL
> +#define ADDR_OUTPUT			0x80000000ULL
> +#define ADDR_SURFACE_STATE_BASE		0x200000ULL
> +#define ADDR_DYNAMIC_STATE_BASE		0x300000ULL
> +#define ADDR_INDIRECT_OBJECT_BASE	0x400000ULL
>  #define ADDR_BINDING_TABLE		(ADDR_SURFACE_STATE_BASE +
> OFFSET_BINDING_TABLE)
> -#define OFFSET_INDIRECT_DATA_START	0x5D0000ULL
> -#define OFFSET_KERNEL			0x5E0000ULL
> +#define OFFSET_INDIRECT_DATA_START	0x3D0000ULL
> +#define OFFSET_KERNEL			0x3E0000ULL
>  
> -#define ADDR_GENERAL_STATE_BASE		0x8000000ULL
> -#define ADDR_INSTRUCTION_STATE_BASE	0xa000000ULL
> +#define ADDR_GENERAL_STATE_BASE		0x6000000ULL
> +#define ADDR_INSTRUCTION_STATE_BASE	0x8000000ULL
>  #define OFFSET_BINDING_TABLE		0x10000
>  
> -#define XE2_ADDR_STATE_CONTEXT_DATA_BASE	0xb000000ULL
> +#define XE2_ADDR_STATE_CONTEXT_DATA_BASE	0x9000000ULL
>  #define OFFSET_STATE_SIP			0xFFFF0000
>  
>  #define
> USER_FENCE_VALUE			0xdeadbeefdeadbeefull

[PATCH i-g-t 09/11] lib/intel_compute: Fix enqueued local size in xehp

[Francois Dugast]

According to the metadata of the compute kernel used for this test, the
enqueued_local_size comes at offset 52, right after the value of the
"count" argument. Fix it and add comments for clarity.

Relevant part of the kernel metadata:

      - arg_type:        arg_bypointer
        offset:          32
        size:            8
        arg_index:       0
        addrmode:        stateless
        addrspace:       global
        access_type:     readwrite
      - arg_type:        arg_bypointer
        offset:          40
        size:            8
        arg_index:       1
        addrmode:        stateless
        addrspace:       global
        access_type:     readwrite
      - arg_type:        arg_byvalue
        offset:          48
        size:            4
        arg_index:       2
      - arg_type:        enqueued_local_size
        offset:          52
        size:            12

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index 7a2e04b10..f5b3a88f0 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -781,12 +781,12 @@ static void xehp_create_indirect_data(uint32_t *addr_bo_buffer_batch,
 	addr_bo_buffer_batch[b++] = addr_output & 0xffffffff;
 	addr_bo_buffer_batch[b++] = addr_output >> 32;
 	addr_bo_buffer_batch[b++] = loop_count;
+	addr_bo_buffer_batch[b++] = 0x00000400; // Enqueued local size X
+	addr_bo_buffer_batch[b++] = 0x00000001; // Enqueued local size Y
+	addr_bo_buffer_batch[b++] = 0x00000001; // Enqueued local size Z
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
-	addr_bo_buffer_batch[b++] = 0x00000400;
-	addr_bo_buffer_batch[b++] = 0x00000001;
-	addr_bo_buffer_batch[b++] = 0x00000001;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
-- 
2.43.0

Re: [PATCH i-g-t 09/11] lib/intel_compute: Fix enqueued local size in xehp

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> According to the metadata of the compute kernel used for this test,
> the
> enqueued_local_size comes at offset 52, right after the value of the
> "count" argument. Fix it and add comments for clarity.
> 
> Relevant part of the kernel metadata:
> 
>       - arg_type:        arg_bypointer
>         offset:          32
>         size:            8
>         arg_index:       0
>         addrmode:        stateless
>         addrspace:       global
>         access_type:     readwrite
>       - arg_type:        arg_bypointer
>         offset:          40
>         size:            8
>         arg_index:       1
>         addrmode:        stateless
>         addrspace:       global
>         access_type:     readwrite
>       - arg_type:        arg_byvalue
>         offset:          48
>         size:            4
>         arg_index:       2
>       - arg_type:        enqueued_local_size
>         offset:          52
>         size:            12
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  lib/intel_compute.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index 7a2e04b10..f5b3a88f0 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -781,12 +781,12 @@ static void xehp_create_indirect_data(uint32_t
> *addr_bo_buffer_batch,
>  	addr_bo_buffer_batch[b++] = addr_output & 0xffffffff;
>  	addr_bo_buffer_batch[b++] = addr_output >> 32;
>  	addr_bo_buffer_batch[b++] = loop_count;
> +	addr_bo_buffer_batch[b++] = 0x00000400; // Enqueued local
> size X
> +	addr_bo_buffer_batch[b++] = 0x00000001; // Enqueued local
> size Y
> +	addr_bo_buffer_batch[b++] = 0x00000001; // Enqueued local
> size Z
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
> -	addr_bo_buffer_batch[b++] = 0x00000400;
> -	addr_bo_buffer_batch[b++] = 0x00000001;
> -	addr_bo_buffer_batch[b++] = 0x00000001;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;

[PATCH i-g-t 10/11] lib/intel_compute: Use constants for thread groups and local work size

[Francois Dugast]

Define new constants and use them to build the pipeline instead of
magic values. This also helps homogenize the code to enforce a
similar execution across GPUs. Having them grouped together in the
file makes it easier to experiment with different values, as they
depend on each other but where previously distributed.

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 34 ++++++++++++++++++++++------------
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index f5b3a88f0..068d64b24 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -55,6 +55,16 @@
 
 #define USER_FENCE_VALUE			0xdeadbeefdeadbeefull
 
+#define THREADS_PER_GROUP		32
+#define THREAD_GROUP_X			MAX(1, SIZE_DATA / (ENQUEUED_LOCAL_SIZE_X * \
+							    ENQUEUED_LOCAL_SIZE_Y * \
+							    ENQUEUED_LOCAL_SIZE_Z))
+#define THREAD_GROUP_Y			1
+#define THREAD_GROUP_Z			1
+#define ENQUEUED_LOCAL_SIZE_X		1024
+#define ENQUEUED_LOCAL_SIZE_Y		1
+#define ENQUEUED_LOCAL_SIZE_Z		1
+
 /*
  * TGP  - ThreadGroup Preemption
  * WMTP - Walker Mid Thread Preemption
@@ -781,9 +791,9 @@ static void xehp_create_indirect_data(uint32_t *addr_bo_buffer_batch,
 	addr_bo_buffer_batch[b++] = addr_output & 0xffffffff;
 	addr_bo_buffer_batch[b++] = addr_output >> 32;
 	addr_bo_buffer_batch[b++] = loop_count;
-	addr_bo_buffer_batch[b++] = 0x00000400; // Enqueued local size X
-	addr_bo_buffer_batch[b++] = 0x00000001; // Enqueued local size Y
-	addr_bo_buffer_batch[b++] = 0x00000001; // Enqueued local size Z
+	addr_bo_buffer_batch[b++] = ENQUEUED_LOCAL_SIZE_X;
+	addr_bo_buffer_batch[b++] = ENQUEUED_LOCAL_SIZE_Y;
+	addr_bo_buffer_batch[b++] = ENQUEUED_LOCAL_SIZE_Z;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
@@ -1164,7 +1174,7 @@ static void xehpc_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
 	addr_bo_buffer_batch[b++] = 0x00180000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
-	addr_bo_buffer_batch[b++] = 0x0c000020;
+	addr_bo_buffer_batch[b++] = 0x0c000000 | THREADS_PER_GROUP;
 
 	addr_bo_buffer_batch[b++] = 0x00000008;
 	addr_bo_buffer_batch[b++] = 0x00000000;
@@ -1332,10 +1342,10 @@ static void xelpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
 	addr_bo_buffer_batch[b++] = 0xbe040000;
 	addr_bo_buffer_batch[b++] = 0xffffffff;
 	addr_bo_buffer_batch[b++] = 0x000003ff;
-	addr_bo_buffer_batch[b++] = 0x00000001;
+	addr_bo_buffer_batch[b++] = THREAD_GROUP_X;
 
-	addr_bo_buffer_batch[b++] = 0x00000001;
-	addr_bo_buffer_batch[b++] = 0x00000001;
+	addr_bo_buffer_batch[b++] = THREAD_GROUP_Y;
+	addr_bo_buffer_batch[b++] = THREAD_GROUP_Z;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
@@ -1350,7 +1360,7 @@ static void xelpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00001080;
-	addr_bo_buffer_batch[b++] = 0x0c000020;
+	addr_bo_buffer_batch[b++] = 0x0c000000 | THREADS_PER_GROUP;
 
 	addr_bo_buffer_batch[b++] = 0x00000008;
 	addr_bo_buffer_batch[b++] = 0x00000000;
@@ -1470,10 +1480,10 @@ static void xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
 		 */
 		addr_bo_buffer_batch[b++] = 0x00200000; // Thread Group ID X Dimension
 	else
-		addr_bo_buffer_batch[b++] = 0x00000002;
+		addr_bo_buffer_batch[b++] = THREAD_GROUP_X;
 
-	addr_bo_buffer_batch[b++] = 0x00000001; // Thread Group ID Y Dimension
-	addr_bo_buffer_batch[b++] = 0x00000001; // Thread Group ID Z Dimension
+	addr_bo_buffer_batch[b++] = THREAD_GROUP_Y;
+	addr_bo_buffer_batch[b++] = THREAD_GROUP_Z;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
@@ -1494,7 +1504,7 @@ static void xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
 
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
-	addr_bo_buffer_batch[b++] = 0x0c000020;
+	addr_bo_buffer_batch[b++] = 0x0c000000 | THREADS_PER_GROUP;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00000000;
 	addr_bo_buffer_batch[b++] = 0x00001047;
-- 
2.43.0

Re: [PATCH i-g-t 10/11] lib/intel_compute: Use constants for thread groups and local work size

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> Define new constants and use them to build the pipeline instead of
> magic values. This also helps homogenize the code to enforce a
> similar execution across GPUs. Having them grouped together in the
> file makes it easier to experiment with different values, as they
> depend on each other but where previously distributed.
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
> ---
>  lib/intel_compute.c | 34 ++++++++++++++++++++++------------
>  1 file changed, 22 insertions(+), 12 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index f5b3a88f0..068d64b24 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -55,6 +55,16 @@
>  
>  #define
> USER_FENCE_VALUE			0xdeadbeefdeadbeefull
>  
> +#define THREADS_PER_GROUP		32
> +#define THREAD_GROUP_X			MAX(1, SIZE_DATA /
> (ENQUEUED_LOCAL_SIZE_X * \
> +							   
> ENQUEUED_LOCAL_SIZE_Y * \
> +							   
> ENQUEUED_LOCAL_SIZE_Z))
> +#define THREAD_GROUP_Y			1
> +#define THREAD_GROUP_Z			1
> +#define ENQUEUED_LOCAL_SIZE_X		1024
> +#define ENQUEUED_LOCAL_SIZE_Y		1
> +#define ENQUEUED_LOCAL_SIZE_Z		1

Nit: Perhaps define these before THREAD_GROUP macros to make it
clearer.
Anyway, 
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> +
>  /*
>   * TGP  - ThreadGroup Preemption
>   * WMTP - Walker Mid Thread Preemption
> @@ -781,9 +791,9 @@ static void xehp_create_indirect_data(uint32_t
> *addr_bo_buffer_batch,
>  	addr_bo_buffer_batch[b++] = addr_output & 0xffffffff;
>  	addr_bo_buffer_batch[b++] = addr_output >> 32;
>  	addr_bo_buffer_batch[b++] = loop_count;
> -	addr_bo_buffer_batch[b++] = 0x00000400; // Enqueued local
> size X
> -	addr_bo_buffer_batch[b++] = 0x00000001; // Enqueued local
> size Y
> -	addr_bo_buffer_batch[b++] = 0x00000001; // Enqueued local
> size Z
> +	addr_bo_buffer_batch[b++] = ENQUEUED_LOCAL_SIZE_X;
> +	addr_bo_buffer_batch[b++] = ENQUEUED_LOCAL_SIZE_Y;
> +	addr_bo_buffer_batch[b++] = ENQUEUED_LOCAL_SIZE_Z;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
> @@ -1164,7 +1174,7 @@ static void xehpc_compute_exec_compute(uint32_t
> *addr_bo_buffer_batch,
>  	addr_bo_buffer_batch[b++] = 0x00180000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
> -	addr_bo_buffer_batch[b++] = 0x0c000020;
> +	addr_bo_buffer_batch[b++] = 0x0c000000 | THREADS_PER_GROUP;
>  
>  	addr_bo_buffer_batch[b++] = 0x00000008;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
> @@ -1332,10 +1342,10 @@ static void
> xelpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
>  	addr_bo_buffer_batch[b++] = 0xbe040000;
>  	addr_bo_buffer_batch[b++] = 0xffffffff;
>  	addr_bo_buffer_batch[b++] = 0x000003ff;
> -	addr_bo_buffer_batch[b++] = 0x00000001;
> +	addr_bo_buffer_batch[b++] = THREAD_GROUP_X;
>  
> -	addr_bo_buffer_batch[b++] = 0x00000001;
> -	addr_bo_buffer_batch[b++] = 0x00000001;
> +	addr_bo_buffer_batch[b++] = THREAD_GROUP_Y;
> +	addr_bo_buffer_batch[b++] = THREAD_GROUP_Z;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
> @@ -1350,7 +1360,7 @@ static void xelpg_compute_exec_compute(uint32_t
> *addr_bo_buffer_batch,
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00001080;
> -	addr_bo_buffer_batch[b++] = 0x0c000020;
> +	addr_bo_buffer_batch[b++] = 0x0c000000 | THREADS_PER_GROUP;
>  
>  	addr_bo_buffer_batch[b++] = 0x00000008;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
> @@ -1470,10 +1480,10 @@ static void
> xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
>  		 */
>  		addr_bo_buffer_batch[b++] = 0x00200000; // Thread
> Group ID X Dimension
>  	else
> -		addr_bo_buffer_batch[b++] = 0x00000002;
> +		addr_bo_buffer_batch[b++] = THREAD_GROUP_X;
>  
> -	addr_bo_buffer_batch[b++] = 0x00000001; // Thread Group ID Y
> Dimension
> -	addr_bo_buffer_batch[b++] = 0x00000001; // Thread Group ID Z
> Dimension
> +	addr_bo_buffer_batch[b++] = THREAD_GROUP_Y;
> +	addr_bo_buffer_batch[b++] = THREAD_GROUP_Z;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
> @@ -1494,7 +1504,7 @@ static void
> xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
>  
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
> -	addr_bo_buffer_batch[b++] = 0x0c000020;
> +	addr_bo_buffer_batch[b++] = 0x0c000000 | THREADS_PER_GROUP;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00000000;
>  	addr_bo_buffer_batch[b++] = 0x00001047;

[PATCH i-g-t 11/11] lib/intel_compute: Make array size a dynamic parameter

[Francois Dugast]

Give the users of run_intel_compute_kernel() the possibility to change
the default size of the input and output arrays by adding a custom
size in struct user_execenv::array_size.

If no value is provided, the existing default value of SIZE_DATA will
be used.

Example:

    struct user_execenv env = {};
    env.array_size = 1024 * 1024;
    run_intel_compute_kernel(fd, &env);

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
 lib/intel_compute.c | 144 +++++++++++++++++++++++++++-----------------
 lib/intel_compute.h |   2 +
 2 files changed, 90 insertions(+), 56 deletions(-)

diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index 068d64b24..b2cba0fe0 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -26,8 +26,6 @@
 
 #define SIZE_DATA			64
 #define SIZE_BATCH			0x10000
-#define SIZE_BUFFER_INPUT		MAX(sizeof(float) * SIZE_DATA, 0x10000)
-#define SIZE_BUFFER_OUTPUT		MAX(sizeof(float) * SIZE_DATA, 0x10000)
 #define SIZE_SURFACE_STATE		0x10000
 #define SIZE_DYNAMIC_STATE		0x100000
 #define SIZE_INDIRECT_OBJECT		0x10000
@@ -56,9 +54,6 @@
 #define USER_FENCE_VALUE			0xdeadbeefdeadbeefull
 
 #define THREADS_PER_GROUP		32
-#define THREAD_GROUP_X			MAX(1, SIZE_DATA / (ENQUEUED_LOCAL_SIZE_X * \
-							    ENQUEUED_LOCAL_SIZE_Y * \
-							    ENQUEUED_LOCAL_SIZE_Z))
 #define THREAD_GROUP_Y			1
 #define THREAD_GROUP_Z			1
 #define ENQUEUED_LOCAL_SIZE_X		1024
@@ -91,6 +86,7 @@ struct bo_execenv {
 	/* Xe part */
 	uint32_t vm;
 	uint32_t exec_queue;
+	uint32_t array_size;
 
 	/* i915 part */
 	struct drm_i915_gem_execbuffer2 execbuf;
@@ -118,6 +114,11 @@ static void bo_execenv_create(int fd, struct bo_execenv *execenv,
 		else
 			execenv->vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
 
+		if (user && user->array_size)
+			execenv->array_size = user->array_size;
+		else
+			execenv->array_size = SIZE_DATA;
+
 		if (eci) {
 			execenv->exec_queue = xe_exec_queue_create(fd, execenv->vm,
 								   eci, 0);
@@ -306,6 +307,23 @@ static void bo_execenv_exec(struct bo_execenv *execenv, uint64_t start_addr)
 	}
 }
 
+static uint32_t size_thread_group_x(uint32_t work_size)
+{
+	return MAX(1, work_size / (ENQUEUED_LOCAL_SIZE_X *
+				   ENQUEUED_LOCAL_SIZE_Y *
+				   ENQUEUED_LOCAL_SIZE_Z));
+}
+
+static size_t size_input(uint32_t work_size)
+{
+	return MAX(sizeof(float) * work_size, 0x10000);
+}
+
+static size_t size_output(uint32_t work_size)
+{
+	return MAX(sizeof(float) * work_size, 0x10000);
+}
+
 /*
  * TGL compatible batch
  */
@@ -715,10 +733,8 @@ static void compute_exec(int fd, const unsigned char *kernel,
 		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect data start" },
 		{ .addr = ADDR_INPUT,
-		  .size = SIZE_BUFFER_INPUT,
 		  .name = "input" },
 		{ .addr = ADDR_OUTPUT,
-		  .size = SIZE_BUFFER_OUTPUT,
 		  .name = "output" },
 		{ .addr = ADDR_BATCH,
 		  .size = SIZE_BATCH,
@@ -730,8 +746,10 @@ static void compute_exec(int fd, const unsigned char *kernel,
 
 	bo_execenv_create(fd, &execenv, eci, user);
 
-	/* Sets Kernel size */
+	/* Set dynamic sizes */
 	bo_dict[0].size = ALIGN(size, 0x1000);
+	bo_dict[4].size = size_input(execenv.array_size);
+	bo_dict[5].size = size_output(execenv.array_size);
 
 	bo_execenv_bind(&execenv, bo_dict, BO_DICT_ENTRIES);
 
@@ -739,13 +757,13 @@ static void compute_exec(int fd, const unsigned char *kernel,
 	create_dynamic_state(bo_dict[1].data, OFFSET_KERNEL);
 	create_surface_state(bo_dict[2].data, ADDR_INPUT, ADDR_OUTPUT);
 	create_indirect_data(bo_dict[3].data, ADDR_INPUT, ADDR_OUTPUT,
-			     IS_DG1(devid) ? 0x200 : 0x40, SIZE_DATA);
+			     IS_DG1(devid) ? 0x200 : 0x40, execenv.array_size);
 
 	input_data = (float *) bo_dict[4].data;
 	output_data = (float *) bo_dict[5].data;
 	srand(time(NULL));
 
-	for (int i = 0; i < SIZE_DATA; i++)
+	for (int i = 0; i < execenv.array_size; i++)
 		input_data[i] = rand() / (float)RAND_MAX;
 
 	if (IS_DG1(devid))
@@ -763,7 +781,7 @@ static void compute_exec(int fd, const unsigned char *kernel,
 
 	bo_execenv_exec(&execenv, ADDR_BATCH);
 
-	for (int i = 0; i < SIZE_DATA; i++) {
+	for (int i = 0; i < execenv.array_size; i++) {
 		float input = input_data[i];
 		float output = output_data[i];
 		float expected_output = input * input;
@@ -999,9 +1017,9 @@ static void xehp_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
 		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect object base"},
-		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
+		{ .addr = ADDR_INPUT,
 		  .name = "addr input"},
-		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
+		{ .addr = ADDR_OUTPUT,
 		  .name = "addr output" },
 		{ .addr = ADDR_GENERAL_STATE_BASE,
 		  .size = SIZE_GENERAL_STATE,
@@ -1017,22 +1035,24 @@ static void xehp_compute_exec(int fd, const unsigned char *kernel,
 
 	bo_execenv_create(fd, &execenv, eci, user);
 
-	/* Sets Kernel size */
+	/* Set dynamic sizes */
 	bo_dict[0].size = ALIGN(size, xe_get_default_alignment(fd));
+	bo_dict[4].size = size_input(execenv.array_size);
+	bo_dict[5].size = size_output(execenv.array_size);
 
 	bo_execenv_bind(&execenv, bo_dict, XEHP_BO_DICT_ENTRIES);
 
 	memcpy(bo_dict[0].data, kernel, size);
 	create_dynamic_state(bo_dict[1].data, OFFSET_KERNEL);
 	xehp_create_surface_state(bo_dict[2].data, ADDR_INPUT, ADDR_OUTPUT);
-	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT, ADDR_OUTPUT, SIZE_DATA);
+	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT, ADDR_OUTPUT, execenv.array_size);
 	xehp_create_surface_state(bo_dict[7].data, ADDR_INPUT, ADDR_OUTPUT);
 
 	input_data = (float *) bo_dict[4].data;
 	output_data = (float *) bo_dict[5].data;
 	srand(time(NULL));
 
-	for (int i = 0; i < SIZE_DATA; i++)
+	for (int i = 0; i < execenv.array_size; i++)
 		input_data[i] = rand() / (float)RAND_MAX;
 
 	xehp_compute_exec_compute(bo_dict[8].data,
@@ -1045,7 +1065,7 @@ static void xehp_compute_exec(int fd, const unsigned char *kernel,
 
 	bo_execenv_exec(&execenv, ADDR_BATCH);
 
-	for (int i = 0; i < SIZE_DATA; i++) {
+	for (int i = 0; i < execenv.array_size; i++) {
 		float input = input_data[i];
 		float output = output_data[i];
 		float expected_output = input * input;
@@ -1217,9 +1237,9 @@ static void xehpc_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
 		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect object base"},
-		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
+		{ .addr = ADDR_INPUT,
 		  .name = "addr input"},
-		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
+		{ .addr = ADDR_OUTPUT,
 		  .name = "addr output" },
 		{ .addr = ADDR_GENERAL_STATE_BASE,
 		  .size = SIZE_GENERAL_STATE,
@@ -1232,19 +1252,21 @@ static void xehpc_compute_exec(int fd, const unsigned char *kernel,
 
 	bo_execenv_create(fd, &execenv, eci, user);
 
-	/* Sets Kernel size */
+	/* Set dynamic sizes */
 	bo_dict[0].size = ALIGN(size, xe_get_default_alignment(fd));
+	bo_dict[2].size = size_input(execenv.array_size);
+	bo_dict[3].size = size_output(execenv.array_size);
 
 	bo_execenv_bind(&execenv, bo_dict, XEHPC_BO_DICT_ENTRIES);
 
 	memcpy(bo_dict[0].data, kernel, size);
-	xehpc_create_indirect_data(bo_dict[1].data, ADDR_INPUT, ADDR_OUTPUT, SIZE_DATA);
+	xehpc_create_indirect_data(bo_dict[1].data, ADDR_INPUT, ADDR_OUTPUT, execenv.array_size);
 
 	input_data = (float *) bo_dict[2].data;
 	output_data = (float *) bo_dict[3].data;
 	srand(time(NULL));
 
-	for (int i = 0; i < SIZE_DATA; i++)
+	for (int i = 0; i < execenv.array_size; i++)
 		input_data[i] = rand() / (float)RAND_MAX;
 
 	xehpc_compute_exec_compute(bo_dict[5].data,
@@ -1257,7 +1279,7 @@ static void xehpc_compute_exec(int fd, const unsigned char *kernel,
 
 	bo_execenv_exec(&execenv, ADDR_BATCH);
 
-	for (int i = 0; i < SIZE_DATA; i++) {
+	for (int i = 0; i < execenv.array_size; i++) {
 		float input = input_data[i];
 		float output = output_data[i];
 		float expected_output = input * input;
@@ -1274,12 +1296,13 @@ static void xehpc_compute_exec(int fd, const unsigned char *kernel,
 }
 
 static void xelpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
-					uint64_t addr_general_state_base,
-					uint64_t addr_surface_state_base,
-					uint64_t addr_dynamic_state_base,
-					uint64_t addr_instruction_state_base,
-					uint64_t offset_indirect_data_start,
-					uint64_t kernel_start_pointer)
+				       uint64_t addr_general_state_base,
+				       uint64_t addr_surface_state_base,
+				       uint64_t addr_dynamic_state_base,
+				       uint64_t addr_instruction_state_base,
+				       uint64_t offset_indirect_data_start,
+				       uint64_t kernel_start_pointer,
+				       uint32_t work_size)
 {
 	int b = 0;
 
@@ -1342,7 +1365,7 @@ static void xelpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
 	addr_bo_buffer_batch[b++] = 0xbe040000;
 	addr_bo_buffer_batch[b++] = 0xffffffff;
 	addr_bo_buffer_batch[b++] = 0x000003ff;
-	addr_bo_buffer_batch[b++] = THREAD_GROUP_X;
+	addr_bo_buffer_batch[b++] = size_thread_group_x(work_size);
 
 	addr_bo_buffer_batch[b++] = THREAD_GROUP_Y;
 	addr_bo_buffer_batch[b++] = THREAD_GROUP_Z;
@@ -1398,7 +1421,8 @@ static void xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
 					uint64_t offset_indirect_data_start,
 					uint64_t kernel_start_pointer,
 					uint64_t sip_start_pointer,
-					bool	 threadgroup_preemption)
+					bool	 threadgroup_preemption,
+					uint32_t work_size)
 {
 	int b = 0;
 
@@ -1480,7 +1504,7 @@ static void xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
 		 */
 		addr_bo_buffer_batch[b++] = 0x00200000; // Thread Group ID X Dimension
 	else
-		addr_bo_buffer_batch[b++] = THREAD_GROUP_X;
+		addr_bo_buffer_batch[b++] = size_thread_group_x(work_size);
 
 	addr_bo_buffer_batch[b++] = THREAD_GROUP_Y;
 	addr_bo_buffer_batch[b++] = THREAD_GROUP_Z;
@@ -1576,9 +1600,9 @@ static void xelpg_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
 		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect object base"},
-		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
+		{ .addr = ADDR_INPUT,
 		  .name = "addr input"},
-		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
+		{ .addr = ADDR_OUTPUT,
 		  .name = "addr output" },
 		{ .addr = ADDR_GENERAL_STATE_BASE,
 		  .size = SIZE_GENERAL_STATE,
@@ -1596,8 +1620,10 @@ static void xelpg_compute_exec(int fd, const unsigned char *kernel,
 
 	bo_execenv_create(fd, &execenv, eci, user);
 
-	/* Sets Kernel size */
+	/* Set dynamic sizes */
 	bo_dict[0].size = ALIGN(size, 0x1000);
+	bo_dict[4].size = size_input(execenv.array_size);
+	bo_dict[5].size = size_output(execenv.array_size);
 
 	bo_execenv_bind(&execenv, bo_dict, XELPG_BO_DICT_ENTRIES);
 
@@ -1605,14 +1631,14 @@ static void xelpg_compute_exec(int fd, const unsigned char *kernel,
 
 	create_dynamic_state(bo_dict[1].data, OFFSET_KERNEL);
 	xehp_create_surface_state(bo_dict[2].data, ADDR_INPUT, ADDR_OUTPUT);
-	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT, ADDR_OUTPUT, SIZE_DATA);
+	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT, ADDR_OUTPUT, execenv.array_size);
 	xehp_create_surface_state(bo_dict[7].data, ADDR_INPUT, ADDR_OUTPUT);
 
 	input_data = (float *) bo_dict[4].data;
 	output_data = (float *) bo_dict[5].data;
 	srand(time(NULL));
 
-	for (int i = 0; i < SIZE_DATA; i++)
+	for (int i = 0; i < execenv.array_size; i++)
 		input_data[i] = rand() / (float)RAND_MAX;
 
 	xelpg_compute_exec_compute(bo_dict[8].data,
@@ -1621,11 +1647,12 @@ static void xelpg_compute_exec(int fd, const unsigned char *kernel,
 				   ADDR_DYNAMIC_STATE_BASE,
 				   ADDR_INSTRUCTION_STATE_BASE,
 				   OFFSET_INDIRECT_DATA_START,
-				   OFFSET_KERNEL);
+				   OFFSET_KERNEL,
+				   execenv.array_size);
 
 	bo_execenv_exec(&execenv, ADDR_BATCH);
 
-	for (int i = 0; i < SIZE_DATA; i++) {
+	for (int i = 0; i < execenv.array_size; i++) {
 		float input = input_data[i];
 		float output = output_data[i];
 		float expected_output = input * input;
@@ -1667,9 +1694,9 @@ static void xe2lpg_compute_exec(int fd, const unsigned char *kernel,
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
 		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect object base"},
-		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
+		{ .addr = ADDR_INPUT,
 		  .name = "addr input"},
-		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
+		{ .addr = ADDR_OUTPUT,
 		  .name = "addr output" },
 		{ .addr = ADDR_GENERAL_STATE_BASE,
 		  .size = SIZE_GENERAL_STATE,
@@ -1690,36 +1717,39 @@ static void xe2lpg_compute_exec(int fd, const unsigned char *kernel,
 
 	bo_execenv_create(fd, &execenv, eci, user);
 
-	/* Sets Kernel size */
+	/* Set dynamic sizes */
 	bo_dict[0].size = ALIGN(size, 0x1000);
+	bo_dict[4].size = size_input(execenv.array_size);
+	bo_dict[5].size = size_output(execenv.array_size);
 
 	bo_execenv_bind(&execenv, bo_dict, XE2_BO_DICT_ENTRIES);
 
 	memcpy(bo_dict[0].data, kernel, size);
 	create_dynamic_state(bo_dict[1].data, OFFSET_KERNEL);
 	xehp_create_surface_state(bo_dict[2].data, ADDR_INPUT, ADDR_OUTPUT);
-	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT, ADDR_OUTPUT, SIZE_DATA);
+	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT, ADDR_OUTPUT, execenv.array_size);
 	xehp_create_surface_state(bo_dict[7].data, ADDR_INPUT, ADDR_OUTPUT);
 
 	input_data = (float *) bo_dict[4].data;
 	output_data = (float *) bo_dict[5].data;
 	srand(time(NULL));
 
-	for (int i = 0; i < SIZE_DATA; i++)
+	for (int i = 0; i < execenv.array_size; i++)
 		input_data[i] = rand() / (float)RAND_MAX;
 
 	xe2lpg_compute_exec_compute(bo_dict[8].data,
-				  ADDR_GENERAL_STATE_BASE,
-				  ADDR_SURFACE_STATE_BASE,
-				  ADDR_DYNAMIC_STATE_BASE,
-				  ADDR_INSTRUCTION_STATE_BASE,
-				  XE2_ADDR_STATE_CONTEXT_DATA_BASE,
-				  OFFSET_INDIRECT_DATA_START,
-				  OFFSET_KERNEL, 0, false);
+				    ADDR_GENERAL_STATE_BASE,
+				    ADDR_SURFACE_STATE_BASE,
+				    ADDR_DYNAMIC_STATE_BASE,
+				    ADDR_INSTRUCTION_STATE_BASE,
+				    XE2_ADDR_STATE_CONTEXT_DATA_BASE,
+				    OFFSET_INDIRECT_DATA_START,
+				    OFFSET_KERNEL, 0, false,
+				    execenv.array_size);
 
 	bo_execenv_exec(&execenv, ADDR_BATCH);
 
-	for (int i = 0; i < SIZE_DATA; i++) {
+	for (int i = 0; i < execenv.array_size; i++) {
 		float input = input_data[i];
 		float output = output_data[i];
 		float expected_output = input * input;
@@ -1919,9 +1949,9 @@ static void xe2lpg_compute_preempt_exec(int fd, const unsigned char *long_kernel
 		{ .addr = ADDR_GENERAL_STATE_BASE + OFFSET_INDIRECT_DATA_START,
 		  .size = SIZE_INDIRECT_OBJECT,
 		  .name = "indirect object base"},
-		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
+		{ .addr = ADDR_INPUT, .size = MAX(sizeof(float) * SIZE_DATA, 0x10000),
 		  .name = "addr input"},
-		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
+		{ .addr = ADDR_OUTPUT, .size = MAX(sizeof(float) * SIZE_DATA, 0x10000),
 		  .name = "addr output" },
 		{ .addr = ADDR_GENERAL_STATE_BASE,
 		  .size = SIZE_GENERAL_STATE,
@@ -2039,12 +2069,14 @@ static void xe2lpg_compute_preempt_exec(int fd, const unsigned char *long_kernel
 	xe2lpg_compute_exec_compute(bo_dict_long[8].data, ADDR_GENERAL_STATE_BASE,
 				    ADDR_SURFACE_STATE_BASE, ADDR_DYNAMIC_STATE_BASE,
 				    ADDR_INSTRUCTION_STATE_BASE, XE2_ADDR_STATE_CONTEXT_DATA_BASE,
-				    OFFSET_INDIRECT_DATA_START, OFFSET_KERNEL, OFFSET_STATE_SIP, threadgroup_preemption);
+				    OFFSET_INDIRECT_DATA_START, OFFSET_KERNEL, OFFSET_STATE_SIP,
+				    threadgroup_preemption, SIZE_DATA);
 
 	xe2lpg_compute_exec_compute(bo_dict_short[8].data, ADDR_GENERAL_STATE_BASE,
 				    ADDR_SURFACE_STATE_BASE, ADDR_DYNAMIC_STATE_BASE,
 				    ADDR_INSTRUCTION_STATE_BASE, XE2_ADDR_STATE_CONTEXT_DATA_BASE,
-				    OFFSET_INDIRECT_DATA_START, OFFSET_KERNEL, OFFSET_STATE_SIP, false);
+				    OFFSET_INDIRECT_DATA_START, OFFSET_KERNEL, OFFSET_STATE_SIP,
+				    false, SIZE_DATA);
 
 	xe_exec_sync(fd, execenv_long.exec_queue, ADDR_BATCH, &sync_long, 1);
 	xe_exec_sync(fd, execenv_short.exec_queue, ADDR_BATCH, &sync_short, 1);
diff --git a/lib/intel_compute.h b/lib/intel_compute.h
index dc0fe2ec2..9fdb7fc73 100644
--- a/lib/intel_compute.h
+++ b/lib/intel_compute.h
@@ -55,6 +55,8 @@ struct user_execenv {
 	unsigned int kernel_size;
 	/** @skip_results_check: do not verify correctness of the results if true */
 	bool skip_results_check;
+	/** @array_size: size of input and output arrays */
+	uint32_t array_size;
 };
 
 extern const struct intel_compute_kernels intel_compute_square_kernels[];
-- 
2.43.0

Re: [PATCH i-g-t 11/11] lib/intel_compute: Make array size a dynamic parameter

[Thomas Hellström]

On Tue, 2025-03-11 at 16:21 +0100, Francois Dugast wrote:
> Give the users of run_intel_compute_kernel() the possibility to
> change
> the default size of the input and output arrays by adding a custom
> size in struct user_execenv::array_size.
> 
> If no value is provided, the existing default value of SIZE_DATA will
> be used.
> 
> Example:
> 
>     struct user_execenv env = {};
>     env.array_size = 1024 * 1024;
>     run_intel_compute_kernel(fd, &env);
> 
> Signed-off-by: Francois Dugast <francois.dugast@intel.com>
> ---
>  lib/intel_compute.c | 144 +++++++++++++++++++++++++++---------------
> --
>  lib/intel_compute.h |   2 +
>  2 files changed, 90 insertions(+), 56 deletions(-)
> 
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index 068d64b24..b2cba0fe0 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -26,8 +26,6 @@
>  
>  #define SIZE_DATA			64
>  #define SIZE_BATCH			0x10000
> -#define SIZE_BUFFER_INPUT		MAX(sizeof(float) *
> SIZE_DATA, 0x10000)
> -#define SIZE_BUFFER_OUTPUT		MAX(sizeof(float) *
> SIZE_DATA, 0x10000)
>  #define SIZE_SURFACE_STATE		0x10000
>  #define SIZE_DYNAMIC_STATE		0x100000
>  #define SIZE_INDIRECT_OBJECT		0x10000
> @@ -56,9 +54,6 @@
>  #define
> USER_FENCE_VALUE			0xdeadbeefdeadbeefull
>  
>  #define THREADS_PER_GROUP		32
> -#define THREAD_GROUP_X			MAX(1, SIZE_DATA /
> (ENQUEUED_LOCAL_SIZE_X * \
> -							   
> ENQUEUED_LOCAL_SIZE_Y * \
> -							   
> ENQUEUED_LOCAL_SIZE_Z))
>  #define THREAD_GROUP_Y			1
>  #define THREAD_GROUP_Z			1
>  #define ENQUEUED_LOCAL_SIZE_X		1024
> @@ -91,6 +86,7 @@ struct bo_execenv {
>  	/* Xe part */
>  	uint32_t vm;
>  	uint32_t exec_queue;
> +	uint32_t array_size;
>  
>  	/* i915 part */
>  	struct drm_i915_gem_execbuffer2 execbuf;
> @@ -118,6 +114,11 @@ static void bo_execenv_create(int fd, struct
> bo_execenv *execenv,
>  		else
>  			execenv->vm = xe_vm_create(fd,
> DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
>  
> +		if (user && user->array_size)
> +			execenv->array_size = user->array_size;
> +		else
> +			execenv->array_size = SIZE_DATA;
> +
>  		if (eci) {
>  			execenv->exec_queue =
> xe_exec_queue_create(fd, execenv->vm,
>  								  
> eci, 0);
> @@ -306,6 +307,23 @@ static void bo_execenv_exec(struct bo_execenv
> *execenv, uint64_t start_addr)
>  	}
>  }
>  
> +static uint32_t size_thread_group_x(uint32_t work_size)
> +{
> +	return MAX(1, work_size / (ENQUEUED_LOCAL_SIZE_X *
> +				   ENQUEUED_LOCAL_SIZE_Y *
> +				   ENQUEUED_LOCAL_SIZE_Z));
> +}
> +
> +static size_t size_input(uint32_t work_size)
> +{
> +	return MAX(sizeof(float) * work_size, 0x10000);
> +}
> +
> +static size_t size_output(uint32_t work_size)
> +{
> +	return MAX(sizeof(float) * work_size, 0x10000);
> +}
> +
>  /*
>   * TGL compatible batch
>   */
> @@ -715,10 +733,8 @@ static void compute_exec(int fd, const unsigned
> char *kernel,
>  		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect data start" },
>  		{ .addr = ADDR_INPUT,
> -		  .size = SIZE_BUFFER_INPUT,
>  		  .name = "input" },
>  		{ .addr = ADDR_OUTPUT,
> -		  .size = SIZE_BUFFER_OUTPUT,
>  		  .name = "output" },
>  		{ .addr = ADDR_BATCH,
>  		  .size = SIZE_BATCH,
> @@ -730,8 +746,10 @@ static void compute_exec(int fd, const unsigned
> char *kernel,
>  
>  	bo_execenv_create(fd, &execenv, eci, user);
>  
> -	/* Sets Kernel size */
> +	/* Set dynamic sizes */
>  	bo_dict[0].size = ALIGN(size, 0x1000);
> +	bo_dict[4].size = size_input(execenv.array_size);
> +	bo_dict[5].size = size_output(execenv.array_size);
>  
>  	bo_execenv_bind(&execenv, bo_dict, BO_DICT_ENTRIES);
>  
> @@ -739,13 +757,13 @@ static void compute_exec(int fd, const unsigned
> char *kernel,
>  	create_dynamic_state(bo_dict[1].data, OFFSET_KERNEL);
>  	create_surface_state(bo_dict[2].data, ADDR_INPUT,
> ADDR_OUTPUT);
>  	create_indirect_data(bo_dict[3].data, ADDR_INPUT,
> ADDR_OUTPUT,
> -			     IS_DG1(devid) ? 0x200 : 0x40,
> SIZE_DATA);
> +			     IS_DG1(devid) ? 0x200 : 0x40,
> execenv.array_size);
>  
>  	input_data = (float *) bo_dict[4].data;
>  	output_data = (float *) bo_dict[5].data;
>  	srand(time(NULL));
>  
> -	for (int i = 0; i < SIZE_DATA; i++)
> +	for (int i = 0; i < execenv.array_size; i++)
>  		input_data[i] = rand() / (float)RAND_MAX;
>  
>  	if (IS_DG1(devid))
> @@ -763,7 +781,7 @@ static void compute_exec(int fd, const unsigned
> char *kernel,
>  
>  	bo_execenv_exec(&execenv, ADDR_BATCH);
>  
> -	for (int i = 0; i < SIZE_DATA; i++) {
> +	for (int i = 0; i < execenv.array_size; i++) {
>  		float input = input_data[i];
>  		float output = output_data[i];
>  		float expected_output = input * input;
> @@ -999,9 +1017,9 @@ static void xehp_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
>  		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect object base"},
> -		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
> +		{ .addr = ADDR_INPUT,
>  		  .name = "addr input"},
> -		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
> +		{ .addr = ADDR_OUTPUT,
>  		  .name = "addr output" },
>  		{ .addr = ADDR_GENERAL_STATE_BASE,
>  		  .size = SIZE_GENERAL_STATE,
> @@ -1017,22 +1035,24 @@ static void xehp_compute_exec(int fd, const
> unsigned char *kernel,
>  
>  	bo_execenv_create(fd, &execenv, eci, user);
>  
> -	/* Sets Kernel size */
> +	/* Set dynamic sizes */
>  	bo_dict[0].size = ALIGN(size, xe_get_default_alignment(fd));
> +	bo_dict[4].size = size_input(execenv.array_size);
> +	bo_dict[5].size = size_output(execenv.array_size);
>  
>  	bo_execenv_bind(&execenv, bo_dict, XEHP_BO_DICT_ENTRIES);
>  
>  	memcpy(bo_dict[0].data, kernel, size);
>  	create_dynamic_state(bo_dict[1].data, OFFSET_KERNEL);
>  	xehp_create_surface_state(bo_dict[2].data, ADDR_INPUT,
> ADDR_OUTPUT);
> -	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT,
> ADDR_OUTPUT, SIZE_DATA);
> +	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT,
> ADDR_OUTPUT, execenv.array_size);
>  	xehp_create_surface_state(bo_dict[7].data, ADDR_INPUT,
> ADDR_OUTPUT);
>  
>  	input_data = (float *) bo_dict[4].data;
>  	output_data = (float *) bo_dict[5].data;
>  	srand(time(NULL));
>  
> -	for (int i = 0; i < SIZE_DATA; i++)
> +	for (int i = 0; i < execenv.array_size; i++)
>  		input_data[i] = rand() / (float)RAND_MAX;
>  
>  	xehp_compute_exec_compute(bo_dict[8].data,
> @@ -1045,7 +1065,7 @@ static void xehp_compute_exec(int fd, const
> unsigned char *kernel,
>  
>  	bo_execenv_exec(&execenv, ADDR_BATCH);
>  
> -	for (int i = 0; i < SIZE_DATA; i++) {
> +	for (int i = 0; i < execenv.array_size; i++) {
>  		float input = input_data[i];
>  		float output = output_data[i];
>  		float expected_output = input * input;
> @@ -1217,9 +1237,9 @@ static void xehpc_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
>  		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect object base"},
> -		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
> +		{ .addr = ADDR_INPUT,
>  		  .name = "addr input"},
> -		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
> +		{ .addr = ADDR_OUTPUT,
>  		  .name = "addr output" },
>  		{ .addr = ADDR_GENERAL_STATE_BASE,
>  		  .size = SIZE_GENERAL_STATE,
> @@ -1232,19 +1252,21 @@ static void xehpc_compute_exec(int fd, const
> unsigned char *kernel,
>  
>  	bo_execenv_create(fd, &execenv, eci, user);
>  
> -	/* Sets Kernel size */
> +	/* Set dynamic sizes */
>  	bo_dict[0].size = ALIGN(size, xe_get_default_alignment(fd));
> +	bo_dict[2].size = size_input(execenv.array_size);
> +	bo_dict[3].size = size_output(execenv.array_size);
>  
>  	bo_execenv_bind(&execenv, bo_dict, XEHPC_BO_DICT_ENTRIES);
>  
>  	memcpy(bo_dict[0].data, kernel, size);
> -	xehpc_create_indirect_data(bo_dict[1].data, ADDR_INPUT,
> ADDR_OUTPUT, SIZE_DATA);
> +	xehpc_create_indirect_data(bo_dict[1].data, ADDR_INPUT,
> ADDR_OUTPUT, execenv.array_size);
>  
>  	input_data = (float *) bo_dict[2].data;
>  	output_data = (float *) bo_dict[3].data;
>  	srand(time(NULL));
>  
> -	for (int i = 0; i < SIZE_DATA; i++)
> +	for (int i = 0; i < execenv.array_size; i++)
>  		input_data[i] = rand() / (float)RAND_MAX;
>  
>  	xehpc_compute_exec_compute(bo_dict[5].data,
> @@ -1257,7 +1279,7 @@ static void xehpc_compute_exec(int fd, const
> unsigned char *kernel,
>  
>  	bo_execenv_exec(&execenv, ADDR_BATCH);
>  
> -	for (int i = 0; i < SIZE_DATA; i++) {
> +	for (int i = 0; i < execenv.array_size; i++) {
>  		float input = input_data[i];
>  		float output = output_data[i];
>  		float expected_output = input * input;
> @@ -1274,12 +1296,13 @@ static void xehpc_compute_exec(int fd, const
> unsigned char *kernel,
>  }
>  
>  static void xelpg_compute_exec_compute(uint32_t
> *addr_bo_buffer_batch,
> -					uint64_t
> addr_general_state_base,
> -					uint64_t
> addr_surface_state_base,
> -					uint64_t
> addr_dynamic_state_base,
> -					uint64_t
> addr_instruction_state_base,
> -					uint64_t
> offset_indirect_data_start,
> -					uint64_t
> kernel_start_pointer)
> +				       uint64_t
> addr_general_state_base,
> +				       uint64_t
> addr_surface_state_base,
> +				       uint64_t
> addr_dynamic_state_base,
> +				       uint64_t
> addr_instruction_state_base,
> +				       uint64_t
> offset_indirect_data_start,
> +				       uint64_t
> kernel_start_pointer,
> +				       uint32_t work_size)

Pls double-check indentation / tab usage here. 


>  {
>  	int b = 0;
>  
> @@ -1342,7 +1365,7 @@ static void xelpg_compute_exec_compute(uint32_t
> *addr_bo_buffer_batch,
>  	addr_bo_buffer_batch[b++] = 0xbe040000;
>  	addr_bo_buffer_batch[b++] = 0xffffffff;
>  	addr_bo_buffer_batch[b++] = 0x000003ff;
> -	addr_bo_buffer_batch[b++] = THREAD_GROUP_X;
> +	addr_bo_buffer_batch[b++] = size_thread_group_x(work_size);
>  
>  	addr_bo_buffer_batch[b++] = THREAD_GROUP_Y;
>  	addr_bo_buffer_batch[b++] = THREAD_GROUP_Z;
> @@ -1398,7 +1421,8 @@ static void
> xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
>  					uint64_t
> offset_indirect_data_start,
>  					uint64_t
> kernel_start_pointer,
>  					uint64_t sip_start_pointer,
> -					bool	
> threadgroup_preemption)
> +					bool	
> threadgroup_preemption,
> +					uint32_t work_size)
>  {
>  	int b = 0;
>  
> @@ -1480,7 +1504,7 @@ static void
> xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
>  		 */
>  		addr_bo_buffer_batch[b++] = 0x00200000; // Thread
> Group ID X Dimension
>  	else
> -		addr_bo_buffer_batch[b++] = THREAD_GROUP_X;
> +		addr_bo_buffer_batch[b++] =
> size_thread_group_x(work_size);
>  
>  	addr_bo_buffer_batch[b++] = THREAD_GROUP_Y;
>  	addr_bo_buffer_batch[b++] = THREAD_GROUP_Z;
> @@ -1576,9 +1600,9 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
>  		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect object base"},
> -		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
> +		{ .addr = ADDR_INPUT,
>  		  .name = "addr input"},
> -		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
> +		{ .addr = ADDR_OUTPUT,
>  		  .name = "addr output" },
>  		{ .addr = ADDR_GENERAL_STATE_BASE,
>  		  .size = SIZE_GENERAL_STATE,
> @@ -1596,8 +1620,10 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  
>  	bo_execenv_create(fd, &execenv, eci, user);
>  
> -	/* Sets Kernel size */
> +	/* Set dynamic sizes */
>  	bo_dict[0].size = ALIGN(size, 0x1000);
> +	bo_dict[4].size = size_input(execenv.array_size);
> +	bo_dict[5].size = size_output(execenv.array_size);
>  
>  	bo_execenv_bind(&execenv, bo_dict, XELPG_BO_DICT_ENTRIES);
>  
> @@ -1605,14 +1631,14 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  
>  	create_dynamic_state(bo_dict[1].data, OFFSET_KERNEL);
>  	xehp_create_surface_state(bo_dict[2].data, ADDR_INPUT,
> ADDR_OUTPUT);
> -	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT,
> ADDR_OUTPUT, SIZE_DATA);
> +	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT,
> ADDR_OUTPUT, execenv.array_size);
>  	xehp_create_surface_state(bo_dict[7].data, ADDR_INPUT,
> ADDR_OUTPUT);
>  
>  	input_data = (float *) bo_dict[4].data;
>  	output_data = (float *) bo_dict[5].data;
>  	srand(time(NULL));
>  
> -	for (int i = 0; i < SIZE_DATA; i++)
> +	for (int i = 0; i < execenv.array_size; i++)
>  		input_data[i] = rand() / (float)RAND_MAX;
>  
>  	xelpg_compute_exec_compute(bo_dict[8].data,
> @@ -1621,11 +1647,12 @@ static void xelpg_compute_exec(int fd, const
> unsigned char *kernel,
>  				   ADDR_DYNAMIC_STATE_BASE,
>  				   ADDR_INSTRUCTION_STATE_BASE,
>  				   OFFSET_INDIRECT_DATA_START,
> -				   OFFSET_KERNEL);
> +				   OFFSET_KERNEL,
> +				   execenv.array_size);
>  
>  	bo_execenv_exec(&execenv, ADDR_BATCH);
>  
> -	for (int i = 0; i < SIZE_DATA; i++) {
> +	for (int i = 0; i < execenv.array_size; i++) {
>  		float input = input_data[i];
>  		float output = output_data[i];
>  		float expected_output = input * input;
> @@ -1667,9 +1694,9 @@ static void xe2lpg_compute_exec(int fd, const
> unsigned char *kernel,
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
>  		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect object base"},
> -		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
> +		{ .addr = ADDR_INPUT,
>  		  .name = "addr input"},
> -		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
> +		{ .addr = ADDR_OUTPUT,
>  		  .name = "addr output" },
>  		{ .addr = ADDR_GENERAL_STATE_BASE,
>  		  .size = SIZE_GENERAL_STATE,
> @@ -1690,36 +1717,39 @@ static void xe2lpg_compute_exec(int fd, const
> unsigned char *kernel,
>  
>  	bo_execenv_create(fd, &execenv, eci, user);
>  
> -	/* Sets Kernel size */
> +	/* Set dynamic sizes */
>  	bo_dict[0].size = ALIGN(size, 0x1000);
> +	bo_dict[4].size = size_input(execenv.array_size);
> +	bo_dict[5].size = size_output(execenv.array_size);
>  
>  	bo_execenv_bind(&execenv, bo_dict, XE2_BO_DICT_ENTRIES);
>  
>  	memcpy(bo_dict[0].data, kernel, size);
>  	create_dynamic_state(bo_dict[1].data, OFFSET_KERNEL);
>  	xehp_create_surface_state(bo_dict[2].data, ADDR_INPUT,
> ADDR_OUTPUT);
> -	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT,
> ADDR_OUTPUT, SIZE_DATA);
> +	xehp_create_indirect_data(bo_dict[3].data, ADDR_INPUT,
> ADDR_OUTPUT, execenv.array_size);
>  	xehp_create_surface_state(bo_dict[7].data, ADDR_INPUT,
> ADDR_OUTPUT);
>  
>  	input_data = (float *) bo_dict[4].data;
>  	output_data = (float *) bo_dict[5].data;
>  	srand(time(NULL));
>  
> -	for (int i = 0; i < SIZE_DATA; i++)
> +	for (int i = 0; i < execenv.array_size; i++)
>  		input_data[i] = rand() / (float)RAND_MAX;
>  
>  	xe2lpg_compute_exec_compute(bo_dict[8].data,
> -				  ADDR_GENERAL_STATE_BASE,
> -				  ADDR_SURFACE_STATE_BASE,
> -				  ADDR_DYNAMIC_STATE_BASE,
> -				  ADDR_INSTRUCTION_STATE_BASE,
> -				  XE2_ADDR_STATE_CONTEXT_DATA_BASE,
> -				  OFFSET_INDIRECT_DATA_START,
> -				  OFFSET_KERNEL, 0, false);
> +				    ADDR_GENERAL_STATE_BASE,
> +				    ADDR_SURFACE_STATE_BASE,
> +				    ADDR_DYNAMIC_STATE_BASE,
> +				    ADDR_INSTRUCTION_STATE_BASE,
> +				   
> XE2_ADDR_STATE_CONTEXT_DATA_BASE,
> +				    OFFSET_INDIRECT_DATA_START,
> +				    OFFSET_KERNEL, 0, false,
> +				    execenv.array_size);
>  

And here..



>  	bo_execenv_exec(&execenv, ADDR_BATCH);
>  
> -	for (int i = 0; i < SIZE_DATA; i++) {
> +	for (int i = 0; i < execenv.array_size; i++) {
>  		float input = input_data[i];
>  		float output = output_data[i];
>  		float expected_output = input * input;
> @@ -1919,9 +1949,9 @@ static void xe2lpg_compute_preempt_exec(int fd,
> const unsigned char *long_kernel
>  		{ .addr = ADDR_GENERAL_STATE_BASE +
> OFFSET_INDIRECT_DATA_START,
>  		  .size = SIZE_INDIRECT_OBJECT,
>  		  .name = "indirect object base"},
> -		{ .addr = ADDR_INPUT, .size = SIZE_BUFFER_INPUT,
> +		{ .addr = ADDR_INPUT, .size = MAX(sizeof(float) *
> SIZE_DATA, 0x10000),
>  		  .name = "addr input"},
> -		{ .addr = ADDR_OUTPUT, .size = SIZE_BUFFER_OUTPUT,
> +		{ .addr = ADDR_OUTPUT, .size = MAX(sizeof(float) *
> SIZE_DATA, 0x10000),
>  		  .name = "addr output" },
>  		{ .addr = ADDR_GENERAL_STATE_BASE,
>  		  .size = SIZE_GENERAL_STATE,
> @@ -2039,12 +2069,14 @@ static void xe2lpg_compute_preempt_exec(int
> fd, const unsigned char *long_kernel
>  	xe2lpg_compute_exec_compute(bo_dict_long[8].data,
> ADDR_GENERAL_STATE_BASE,
>  				    ADDR_SURFACE_STATE_BASE,
> ADDR_DYNAMIC_STATE_BASE,
>  				    ADDR_INSTRUCTION_STATE_BASE,
> XE2_ADDR_STATE_CONTEXT_DATA_BASE,
> -				    OFFSET_INDIRECT_DATA_START,
> OFFSET_KERNEL, OFFSET_STATE_SIP, threadgroup_preemption);
> +				    OFFSET_INDIRECT_DATA_START,
> OFFSET_KERNEL, OFFSET_STATE_SIP,
> +				    threadgroup_preemption,
> SIZE_DATA);
>  
>  	xe2lpg_compute_exec_compute(bo_dict_short[8].data,
> ADDR_GENERAL_STATE_BASE,
>  				    ADDR_SURFACE_STATE_BASE,
> ADDR_DYNAMIC_STATE_BASE,
>  				    ADDR_INSTRUCTION_STATE_BASE,
> XE2_ADDR_STATE_CONTEXT_DATA_BASE,
> -				    OFFSET_INDIRECT_DATA_START,
> OFFSET_KERNEL, OFFSET_STATE_SIP, false);
> +				    OFFSET_INDIRECT_DATA_START,
> OFFSET_KERNEL, OFFSET_STATE_SIP,
> +				    false, SIZE_DATA);
>  
>  	xe_exec_sync(fd, execenv_long.exec_queue, ADDR_BATCH,
> &sync_long, 1);
>  	xe_exec_sync(fd, execenv_short.exec_queue, ADDR_BATCH,
> &sync_short, 1);
> diff --git a/lib/intel_compute.h b/lib/intel_compute.h
> index dc0fe2ec2..9fdb7fc73 100644
> --- a/lib/intel_compute.h
> +++ b/lib/intel_compute.h
> @@ -55,6 +55,8 @@ struct user_execenv {
>  	unsigned int kernel_size;
>  	/** @skip_results_check: do not verify correctness of the
> results if true */
>  	bool skip_results_check;
> +	/** @array_size: size of input and output arrays */
> +	uint32_t array_size;
>  };
>  
>  extern const struct intel_compute_kernels
> intel_compute_square_kernels[];

With that,
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

It looks like this series is failing CI on DG2 / ATSM but it also looks
like you caught that? (64-bit alignment?)

/Thomas

✗ Xe.CI.BAT: failure for Prepare lib/intel_compute for SVM/system allocator, part 2

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1837 bytes --]

== Series Details ==

Series: Prepare lib/intel_compute for SVM/system allocator, part 2
URL   : https://patchwork.freedesktop.org/series/146146/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8271_BAT -> XEIGTPW_12748_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_12748_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_12748_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_12748_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_compute@compute-square:
    - bat-dg2-oem2:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/bat-dg2-oem2/igt@xe_compute@compute-square.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/bat-dg2-oem2/igt@xe_compute@compute-square.html
    - bat-atsm-2:         [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/bat-atsm-2/igt@xe_compute@compute-square.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/bat-atsm-2/igt@xe_compute@compute-square.html

  


Build changes
-------------

  * IGT: IGT_8271 -> IGTPW_12748

  IGTPW_12748: 12748
  IGT_8271: 8271
  xe-2797-eb17816e52395a403aa0b447aa0befa9d2f86dd5: eb17816e52395a403aa0b447aa0befa9d2f86dd5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/index.html

[-- Attachment #2: Type: text/html, Size: 2427 bytes --]

✓ i915.CI.BAT: success for Prepare lib/intel_compute for SVM/system allocator, part 2

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4319 bytes --]

== Series Details ==

Series: Prepare lib/intel_compute for SVM/system allocator, part 2
URL   : https://patchwork.freedesktop.org/series/146146/
State : success

== Summary ==

CI Bug Log - changes from IGT_8271 -> IGTPW_12748
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/index.html

Participating hosts (44 -> 43)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in IGTPW_12748 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests@dma_fence_chain:
    - fi-bsw-nick:        [PASS][1] -> [INCOMPLETE][2] ([i915#12904]) +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8271/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8271/bat-mtlp-8/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-2:         [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8271/bat-arlh-2/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/bat-arlh-2/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@core_auth@basic-auth:
    - fi-bsw-nick:        [DMESG-WARN][7] ([i915#13736]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8271/fi-bsw-nick/igt@core_auth@basic-auth.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/fi-bsw-nick/igt@core_auth@basic-auth.html

  * igt@i915_selftest@live:
    - bat-jsl-3:          [INCOMPLETE][9] ([i915#12445] / [i915#13241]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8271/bat-jsl-3/igt@i915_selftest@live.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/bat-jsl-3/igt@i915_selftest@live.html

  * igt@i915_selftest@live@hugepages:
    - bat-jsl-3:          [INCOMPLETE][11] ([i915#12445]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8271/bat-jsl-3/igt@i915_selftest@live@hugepages.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/bat-jsl-3/igt@i915_selftest@live@hugepages.html

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-6:         [DMESG-FAIL][13] ([i915#12061]) -> [PASS][14] +1 other test pass
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8271/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/bat-mtlp-6/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [ABORT][15] ([i915#13679]) -> [ABORT][16] ([i915#13465] / [i915#13679]) +1 other test abort
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8271/bat-atsm-1/igt@i915_selftest@live@mman.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12445]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12445
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#13241]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13241
  [i915#13465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13465
  [i915#13679]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13679
  [i915#13736]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13736


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8271 -> IGTPW_12748

  CI-20190529: 20190529
  CI_DRM_16265: eb17816e52395a403aa0b447aa0befa9d2f86dd5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_12748: 12748
  IGT_8271: 8271

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/index.html

[-- Attachment #2: Type: text/html, Size: 5399 bytes --]

✓ i915.CI.Full: success for Prepare lib/intel_compute for SVM/system allocator, part 2

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 871 bytes --]

== Series Details ==

Series: Prepare lib/intel_compute for SVM/system allocator, part 2
URL   : https://patchwork.freedesktop.org/series/146146/
State : success

== Summary ==

CI Bug Log - changes from IGT_8271_full -> IGTPW_12748_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/index.html

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8271 -> IGTPW_12748

  CI_DRM_16265: eb17816e52395a403aa0b447aa0befa9d2f86dd5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_12748: 12748
  IGT_8271: 8271

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12748/index.html

[-- Attachment #2: Type: text/html, Size: 1423 bytes --]

✗ Xe.CI.Full: failure for Prepare lib/intel_compute for SVM/system allocator, part 2

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 80595 bytes --]

== Series Details ==

Series: Prepare lib/intel_compute for SVM/system allocator, part 2
URL   : https://patchwork.freedesktop.org/series/146146/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8271_full -> XEIGTPW_12748_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_12748_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_12748_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_12748_full:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_compute@compute-square:
    - shard-dg2-set2:     [PASS][1] -> [FAIL][2] +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-466/igt@xe_compute@compute-square.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@xe_compute@compute-square.html

  * igt@xe_pat@pat-index-xe2:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][3] +1 other test incomplete
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@xe_pat@pat-index-xe2.html

  
New tests
---------

  New tests have been introduced between XEIGT_8271_full and XEIGTPW_12748_full:

### New IGT tests (1) ###

  * igt@kms_cursor_edge_walk@64x64-right-edge@pipe-c-edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [4.35] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_12748_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotunplug-rescan:
    - shard-lnl:          NOTRUN -> [ABORT][4] ([Intel XE#3914]) +1 other test abort
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-8/igt@core_hotunplug@hotunplug-rescan.html

  * igt@kms_3d:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#1465])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-3/igt@kms_3d.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#873])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@kms_async_flips@invalid-async-flip.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#873])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#3279])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-4/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2385])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2327]) +5 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#316]) +7 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-432/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#1407]) +7 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-7/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#1124]) +14 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#610])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#1428])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-3/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#1124]) +19 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#1124]) +14 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-dg2-set2:     [PASS][18] -> [SKIP][19] ([Intel XE#2191])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-466/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#2191])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-7/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#2191])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#367]) +6 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#367]) +5 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#367]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-7/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#787]) +212 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-434/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#2907])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#2887]) +15 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-8/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2887]) +17 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#3432]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#3432]) +2 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#3442])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][33] ([Intel XE#455] / [Intel XE#787]) +57 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][34] ([Intel XE#2705])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#4418])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-5/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-a-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#4417]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-432/igt@kms_cdclk@mode-transition@pipe-a-dp-2.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2724])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_cdclk@plane-scaling.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][39] ([Intel XE#4416]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#306])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_chamelium_color@ctm-negative.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][41] ([Intel XE#306])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2252]) +15 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#373]) +20 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#373]) +14 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          NOTRUN -> [FAIL][45] ([Intel XE#1178]) +1 other test fail
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@content-type-change:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#2341])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-7/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2390]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-7/igt@kms_content_protection@dp-mst-type-1.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#307]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-433/igt@kms_content_protection@dp-mst-type-1.html
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#307]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-4/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#3278]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_content_protection@lic-type-1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#308]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2320]) +2 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-rapid-movement-64x21:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#1424]) +3 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-5/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#2321]) +2 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-8/igt@kms_cursor_crc@cursor-sliding-512x170.html
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#2321]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][56] -> [SKIP][57] ([Intel XE#2291]) +3 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-8/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2286])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#323])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#323]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
    - shard-dg2-set2:     NOTRUN -> [SKIP][61] ([Intel XE#309]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#309]) +3 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#2291]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
    - shard-dg2-set2:     [PASS][64] -> [SKIP][65] ([Intel XE#309]) +4 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-463/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#4210])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#4354])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_dp_link_training@uhbr-sst.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][68] ([Intel XE#4356])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@kms_dp_link_training@uhbr-sst.html
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#4354])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#4294])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-7/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#2244])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-5/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#4422]) +2 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-435/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#4422]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-7/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#4422]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-4/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_feature_discovery@display-2x:
    - shard-dg2-set2:     [PASS][75] -> [SKIP][76] ([Intel XE#702])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-436/igt@kms_feature_discovery@display-2x.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@psr2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#1135])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@cd-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][78] -> [FAIL][79] ([Intel XE#301]) +2 other tests fail
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-434/igt@kms_flip@2x-flip-vs-expired-vblank@cd-hdmi-a6-dp4.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_flip@2x-flip-vs-expired-vblank@cd-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-panning:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#2316]) +3 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@kms_flip@2x-flip-vs-panning.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#1421]) +9 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-2/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][82] ([Intel XE#310]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-nonexisting-fb-interruptible:
    - shard-dg2-set2:     [PASS][83] -> [SKIP][84] ([Intel XE#310])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-435/igt@kms_flip@2x-nonexisting-fb-interruptible.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_flip@2x-nonexisting-fb-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [PASS][85] -> [SKIP][86] ([Intel XE#2316]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@blocking-wf_vblank@a-dp2:
    - shard-bmg:          NOTRUN -> [FAIL][87] ([Intel XE#2882]) +5 other tests fail
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-7/igt@kms_flip@blocking-wf_vblank@a-dp2.html

  * igt@kms_flip@bo-too-big-interruptible@a-edp1:
    - shard-lnl:          NOTRUN -> [TIMEOUT][88] ([Intel XE#1504]) +1 other test timeout
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-4/igt@kms_flip@bo-too-big-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@b-dp2:
    - shard-bmg:          NOTRUN -> [FAIL][89] ([Intel XE#3321])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank@b-dp2.html

  * igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a6:
    - shard-dg2-set2:     NOTRUN -> [FAIL][90] ([Intel XE#301]) +1 other test fail
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a6.html

  * igt@kms_flip@flip-vs-panning-interruptible@d-hdmi-a3:
    - shard-bmg:          [PASS][91] -> [INCOMPLETE][92] ([Intel XE#2049]) +1 other test incomplete
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-8/igt@kms_flip@flip-vs-panning-interruptible@d-hdmi-a3.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-7/igt@kms_flip@flip-vs-panning-interruptible@d-hdmi-a3.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-lnl:          [PASS][93] -> [FAIL][94] ([Intel XE#886]) +3 other tests fail
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-lnl-5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#2293]) +4 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#1397] / [Intel XE#1745])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#1397])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#2293] / [Intel XE#2380]) +4 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#1401] / [Intel XE#1745]) +5 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#1401]) +5 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#352])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-2/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#2312]) +19 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary:
    - shard-dg2-set2:     NOTRUN -> [SKIP][103] ([Intel XE#651]) +45 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2-set2:     [PASS][104] -> [SKIP][105] ([Intel XE#656]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][106] ([Intel XE#4141]) +13 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2-set2:     NOTRUN -> [SKIP][107] ([Intel XE#658])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#2352])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#2311]) +37 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][110] ([Intel XE#651]) +19 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][111] ([Intel XE#656]) +39 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][112] ([Intel XE#653]) +49 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][113] ([Intel XE#2313]) +31 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][114] ([Intel XE#656]) +8 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          NOTRUN -> [SKIP][115] ([Intel XE#1503])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][116] ([Intel XE#4298])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][117] ([Intel XE#346])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_joiner@invalid-modeset-big-joiner.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][118] ([Intel XE#346])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@kms_joiner@invalid-modeset-big-joiner.html
    - shard-lnl:          NOTRUN -> [SKIP][119] ([Intel XE#346])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-7/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][120] ([Intel XE#2934])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-7/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][121] ([Intel XE#2925])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
    - shard-lnl:          NOTRUN -> [SKIP][122] ([Intel XE#2934])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-5/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2-set2:     NOTRUN -> [SKIP][123] ([Intel XE#4359])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane@plane-position-hole:
    - shard-lnl:          NOTRUN -> [DMESG-FAIL][124] ([Intel XE#324]) +2 other tests dmesg-fail
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-1/igt@kms_plane@plane-position-hole.html

  * igt@kms_plane@plane-position-hole@pipe-b-plane-1:
    - shard-lnl:          NOTRUN -> [DMESG-WARN][125] ([Intel XE#324]) +3 other tests dmesg-warn
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-1/igt@kms_plane@plane-position-hole@pipe-b-plane-1.html

  * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
    - shard-dg2-set2:     NOTRUN -> [FAIL][126] ([Intel XE#616]) +3 other tests fail
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-433/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html

  * igt@kms_plane_lowres@tiling-x@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][127] ([Intel XE#599]) +3 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_plane_lowres@tiling-x@pipe-b-edp-1.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][128] ([Intel XE#2493])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-bmg:          NOTRUN -> [SKIP][129] ([Intel XE#2571])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][130] ([Intel XE#4212])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-434/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [ABORT][131] ([Intel XE#4540]) +1 other test abort
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-434/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d:
    - shard-bmg:          NOTRUN -> [SKIP][132] ([Intel XE#2763]) +29 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d:
    - shard-dg2-set2:     NOTRUN -> [SKIP][133] ([Intel XE#2763] / [Intel XE#455]) +7 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25:
    - shard-lnl:          NOTRUN -> [SKIP][134] ([Intel XE#2763]) +19 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-5/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b:
    - shard-dg2-set2:     NOTRUN -> [SKIP][135] ([Intel XE#2763]) +11 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-435/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b.html

  * igt@kms_pm_backlight@fade:
    - shard-dg2-set2:     NOTRUN -> [SKIP][136] ([Intel XE#870]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-bmg:          NOTRUN -> [SKIP][137] ([Intel XE#2391])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][138] ([Intel XE#908]) +1 other test skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][139] ([Intel XE#1439] / [Intel XE#836])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-8/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][140] ([Intel XE#1439] / [Intel XE#3141])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-1/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][141] ([Intel XE#2893]) +4 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-8/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][142] ([Intel XE#1489]) +9 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][143] ([Intel XE#1489]) +13 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][144] ([Intel XE#2387]) +1 other test skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-dg2-set2:     NOTRUN -> [SKIP][145] ([Intel XE#1122]) +1 other test skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@kms_psr2_su@page_flip-nv12.html
    - shard-lnl:          NOTRUN -> [SKIP][146] ([Intel XE#1128])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-2/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-pr-sprite-render:
    - shard-lnl:          NOTRUN -> [SKIP][147] ([Intel XE#1406]) +4 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_psr@fbc-pr-sprite-render.html

  * igt@kms_psr@psr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][148] ([Intel XE#2850] / [Intel XE#929]) +24 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_psr@psr-dpms.html

  * igt@kms_psr@psr-primary-page-flip:
    - shard-bmg:          NOTRUN -> [SKIP][149] ([Intel XE#2234] / [Intel XE#2850]) +16 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-7/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][150] ([Intel XE#2234])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_psr@psr2-primary-render.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-bmg:          NOTRUN -> [SKIP][151] ([Intel XE#3414] / [Intel XE#3904]) +3 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-lnl:          NOTRUN -> [SKIP][152] ([Intel XE#3414] / [Intel XE#3904]) +3 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-5/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2-set2:     NOTRUN -> [SKIP][153] ([Intel XE#1127])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
    - shard-lnl:          NOTRUN -> [SKIP][154] ([Intel XE#1127])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][155] ([Intel XE#3414]) +5 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-bmg:          NOTRUN -> [SKIP][156] ([Intel XE#2413])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_setmode@basic:
    - shard-lnl:          [PASS][157] -> [FAIL][158] ([Intel XE#2883]) +1 other test fail
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-lnl-7/igt@kms_setmode@basic.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_setmode@basic.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][159] ([Intel XE#1435])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_setmode@basic-clone-single-crtc.html
    - shard-lnl:          NOTRUN -> [SKIP][160] ([Intel XE#1435]) +1 other test skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_setmode@basic@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][161] -> [FAIL][162] ([Intel XE#2883]) +5 other tests fail
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-433/igt@kms_setmode@basic@pipe-a-hdmi-a-6.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@kms_setmode@basic@pipe-a-hdmi-a-6.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-dg2-set2:     NOTRUN -> [FAIL][163] ([Intel XE#771] / [Intel XE#899])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
    - shard-lnl:          [PASS][164] -> [FAIL][165] ([Intel XE#899])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-lnl-2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [FAIL][166] ([Intel XE#899])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [FAIL][167] ([Intel XE#4459]) +1 other test fail
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@kms_vrr@flipline:
    - shard-dg2-set2:     NOTRUN -> [SKIP][168] ([Intel XE#455]) +32 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@kms_vrr@flipline.html

  * igt@kms_vrr@lobf:
    - shard-bmg:          NOTRUN -> [SKIP][169] ([Intel XE#2168]) +1 other test skip
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_vrr@lobf.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][170] ([Intel XE#2168])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_vrr@lobf.html

  * igt@kms_vrr@max-min:
    - shard-bmg:          NOTRUN -> [SKIP][171] ([Intel XE#1499])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-7/igt@kms_vrr@max-min.html

  * igt@kms_vrr@negative-basic:
    - shard-lnl:          NOTRUN -> [SKIP][172] ([Intel XE#1499]) +1 other test skip
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@kms_vrr@negative-basic.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-bmg:          NOTRUN -> [SKIP][173] ([Intel XE#756]) +1 other test skip
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][174] ([Intel XE#756]) +1 other test skip
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
    - shard-lnl:          NOTRUN -> [SKIP][175] ([Intel XE#756])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-2/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute:
    - shard-dg2-set2:     NOTRUN -> [SKIP][176] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html

  * igt@xe_copy_basic@mem-copy-linear-0x3fff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][177] ([Intel XE#1123])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@xe_copy_basic@mem-copy-linear-0x3fff.html

  * igt@xe_eu_stall@unprivileged-access:
    - shard-dg2-set2:     NOTRUN -> [SKIP][178] ([Intel XE#4497])
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@xe_eu_stall@unprivileged-access.html

  * igt@xe_eudebug@basic-vm-bind-ufence-delay-ack:
    - shard-dg2-set2:     NOTRUN -> [SKIP][179] ([Intel XE#2905] / [Intel XE#3889])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-432/igt@xe_eudebug@basic-vm-bind-ufence-delay-ack.html
    - shard-lnl:          NOTRUN -> [SKIP][180] ([Intel XE#2905] / [Intel XE#3889])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-7/igt@xe_eudebug@basic-vm-bind-ufence-delay-ack.html
    - shard-bmg:          NOTRUN -> [SKIP][181] ([Intel XE#2905] / [Intel XE#3889])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@xe_eudebug@basic-vm-bind-ufence-delay-ack.html

  * igt@xe_eudebug@multiple-sessions:
    - shard-dg2-set2:     NOTRUN -> [SKIP][182] ([Intel XE#2905]) +16 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@xe_eudebug@multiple-sessions.html
    - shard-lnl:          NOTRUN -> [SKIP][183] ([Intel XE#2905]) +10 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-3/igt@xe_eudebug@multiple-sessions.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          NOTRUN -> [SKIP][184] ([Intel XE#2905]) +13 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@xe_eudebug_online@single-step.html

  * igt@xe_evict@evict-large-external-cm:
    - shard-lnl:          NOTRUN -> [SKIP][185] ([Intel XE#688]) +4 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-5/igt@xe_evict@evict-large-external-cm.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap:
    - shard-dg2-set2:     NOTRUN -> [SKIP][186] ([Intel XE#1392])
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race:
    - shard-dg2-set2:     [PASS][187] -> [SKIP][188] ([Intel XE#1392]) +1 other test skip
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-436/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][189] ([Intel XE#2322]) +12 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
    - shard-lnl:          NOTRUN -> [SKIP][190] ([Intel XE#1392]) +9 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-7/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html

  * igt@xe_exec_fault_mode@once-rebind-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][191] ([Intel XE#288]) +44 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@xe_exec_fault_mode@once-rebind-prefetch.html

  * igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
    - shard-lnl:          NOTRUN -> [SKIP][192] ([Intel XE#2229])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-1/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-bmg:          NOTRUN -> [SKIP][193] ([Intel XE#2229])
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_mmap@pci-membarrier-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][194] ([Intel XE#4045])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-8/igt@xe_mmap@pci-membarrier-parallel.html

  * igt@xe_noexec_ping_pong:
    - shard-lnl:          NOTRUN -> [SKIP][195] ([Intel XE#379])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-3/igt@xe_noexec_ping_pong.html

  * igt@xe_oa@buffer-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][196] ([Intel XE#4501])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-435/igt@xe_oa@buffer-size.html
    - shard-lnl:          NOTRUN -> [FAIL][197] ([Intel XE#4541])
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-1/igt@xe_oa@buffer-size.html

  * igt@xe_oa@polling-small-buf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][198] ([Intel XE#2541] / [Intel XE#3573]) +4 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@xe_oa@polling-small-buf.html

  * igt@xe_oa@syncs-ufence-wait-cfg:
    - shard-dg2-set2:     NOTRUN -> [SKIP][199] ([Intel XE#2541] / [Intel XE#3573] / [Intel XE#4501]) +1 other test skip
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-434/igt@xe_oa@syncs-ufence-wait-cfg.html

  * igt@xe_pat@pat-index-xe2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][200] ([Intel XE#977])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@xe_pat@pat-index-xe2.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-bmg:          NOTRUN -> [SKIP][201] ([Intel XE#1420])
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@xe_pat@pat-index-xehpc.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][202] ([Intel XE#2838] / [Intel XE#979])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-433/igt@xe_pat@pat-index-xehpc.html
    - shard-lnl:          NOTRUN -> [SKIP][203] ([Intel XE#1420] / [Intel XE#2838])
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-8/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-dg2-set2:     NOTRUN -> [SKIP][204] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-434/igt@xe_pm@d3cold-mmap-vram.html
    - shard-lnl:          NOTRUN -> [SKIP][205] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-8/igt@xe_pm@d3cold-mmap-vram.html
    - shard-bmg:          NOTRUN -> [SKIP][206] ([Intel XE#2284])
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@s3-multiple-execs:
    - shard-lnl:          NOTRUN -> [SKIP][207] ([Intel XE#584]) +1 other test skip
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@xe_pm@s3-multiple-execs.html

  * igt@xe_pm@s4-d3hot-basic-exec:
    - shard-dg2-set2:     NOTRUN -> [ABORT][208] ([Intel XE#4268]) +1 other test abort
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-432/igt@xe_pm@s4-d3hot-basic-exec.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-bmg:          NOTRUN -> [ABORT][209] ([Intel XE#4268]) +1 other test abort
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_query@multigpu-query-engines:
    - shard-dg2-set2:     NOTRUN -> [SKIP][210] ([Intel XE#944]) +4 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@xe_query@multigpu-query-engines.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-lnl:          NOTRUN -> [SKIP][211] ([Intel XE#944]) +2 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-6/igt@xe_query@multigpu-query-invalid-size.html

  * igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
    - shard-bmg:          NOTRUN -> [SKIP][212] ([Intel XE#944]) +2 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html

  * igt@xe_sriov_auto_provisioning@selfconfig-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][213] ([Intel XE#4130])
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-433/igt@xe_sriov_auto_provisioning@selfconfig-basic.html

  * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs:
    - shard-bmg:          NOTRUN -> [SKIP][214] ([Intel XE#4130]) +1 other test skip
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html

  * igt@xe_sriov_scheduling@nonpreempt-engine-resets:
    - shard-dg2-set2:     NOTRUN -> [SKIP][215] ([Intel XE#4351]) +1 other test skip
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html
    - shard-lnl:          NOTRUN -> [SKIP][216] ([Intel XE#4351])
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-2/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html
    - shard-bmg:          NOTRUN -> [SKIP][217] ([Intel XE#4351])
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html

  
#### Possible fixes ####

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][218] ([Intel XE#2191]) -> [PASS][219]
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-464/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][220] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4502] / [Intel XE#4522]) -> [PASS][221]
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][222] ([Intel XE#2291]) -> [PASS][223] +5 other tests pass
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-dg2-set2:     [INCOMPLETE][224] ([Intel XE#3226]) -> [PASS][225]
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-433/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-dg2-set2:     [SKIP][226] ([Intel XE#4354]) -> [PASS][227]
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-464/igt@kms_dp_link_training@non-uhbr-sst.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-dg2-set2:     [SKIP][228] ([Intel XE#310]) -> [PASS][229] +3 other tests pass
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-464/igt@kms_flip@2x-nonexisting-fb.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-bmg:          [SKIP][230] ([Intel XE#2316]) -> [PASS][231] +2 other tests pass
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-4/igt@kms_flip@2x-wf_vblank-ts-check.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_flip@2x-wf_vblank-ts-check.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-dg2-set2:     [FAIL][232] ([Intel XE#301]) -> [PASS][233]
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-432/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a3:
    - shard-bmg:          [FAIL][234] ([Intel XE#3321]) -> [PASS][235] +2 other tests pass
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-6/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a3.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a3.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][236] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][237]
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][238] ([Intel XE#656]) -> [PASS][239] +2 other tests pass
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-435/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
    - shard-dg2-set2:     [FAIL][240] ([Intel XE#616]) -> [PASS][241] +3 other tests pass
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-436/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-435/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [FAIL][242] ([Intel XE#718]) -> [PASS][243]
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-lnl-5/igt@kms_pm_dc@dc5-psr.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-8/igt@kms_pm_dc@dc5-psr.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue:
    - shard-dg2-set2:     [SKIP][244] ([Intel XE#1392]) -> [PASS][245] +1 other test pass
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-435/igt@xe_exec_basic@multigpu-once-bindexecqueue.html

  
#### Warnings ####

  * igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][246] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][247] ([Intel XE#787]) +5 other tests skip
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-464/igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-d-hdmi-a-6.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-463/igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][248] ([Intel XE#787]) -> [SKIP][249] ([Intel XE#455] / [Intel XE#787]) +5 other tests skip
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-463/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][250] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4522]) -> [INCOMPLETE][251] ([Intel XE#2705])
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-set2:     [FAIL][252] ([Intel XE#1178]) -> [SKIP][253] ([Intel XE#455])
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-432/igt@kms_content_protection@atomic-dpms.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_content_protection@atomic-dpms.html
    - shard-bmg:          [FAIL][254] ([Intel XE#1178]) -> [SKIP][255] ([Intel XE#2341])
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-8/igt@kms_content_protection@atomic-dpms.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-bmg:          [DMESG-WARN][256] ([Intel XE#877]) -> [SKIP][257] ([Intel XE#2291])
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-bmg:          [FAIL][258] ([Intel XE#3321]) -> [SKIP][259] ([Intel XE#2316])
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-6/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][260] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][261] ([Intel XE#301])
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt:
    - shard-dg2-set2:     [SKIP][262] ([Intel XE#656]) -> [SKIP][263] ([Intel XE#651]) +9 other tests skip
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][264] ([Intel XE#2312]) -> [SKIP][265] ([Intel XE#2311]) +12 other tests skip
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][266] ([Intel XE#2311]) -> [SKIP][267] ([Intel XE#2312]) +7 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][268] ([Intel XE#2312]) -> [SKIP][269] ([Intel XE#4141]) +6 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][270] ([Intel XE#4141]) -> [SKIP][271] ([Intel XE#2312]) +6 other tests skip
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     [SKIP][272] ([Intel XE#651]) -> [SKIP][273] ([Intel XE#656]) +5 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][274] ([Intel XE#2313]) -> [SKIP][275] ([Intel XE#2312]) +4 other tests skip
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [SKIP][276] ([Intel XE#656]) -> [SKIP][277] ([Intel XE#653]) +6 other tests skip
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][278] ([Intel XE#2312]) -> [SKIP][279] ([Intel XE#2313]) +14 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     [SKIP][280] ([Intel XE#653]) -> [SKIP][281] ([Intel XE#656]) +3 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][282] ([Intel XE#3544]) -> [SKIP][283] ([Intel XE#3374] / [Intel XE#3544])
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-bmg-4/igt@kms_hdr@brightness-with-hdr.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-bmg-8/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][284] ([Intel XE#362]) -> [SKIP][285] ([Intel XE#1500])
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-434/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@testdisplay:
    - shard-dg2-set2:     [ABORT][286] ([Intel XE#2705] / [Intel XE#4540]) -> [ABORT][287] ([Intel XE#4540])
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-432/igt@testdisplay.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-432/igt@testdisplay.html

  * igt@xe_pm@s4-basic:
    - shard-dg2-set2:     [ABORT][288] -> [ABORT][289] ([Intel XE#4268])
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8271/shard-dg2-434/igt@xe_pm@s4-basic.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/shard-dg2-435/igt@xe_pm@s4-basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1465]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1465
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1504
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2385
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2493]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2493
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
  [Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
  [Intel XE#3279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3279
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#379]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/379
  [Intel XE#3889]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3889
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#3914]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3914
  [Intel XE#4045]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4045
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4210]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4210
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4268]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4268
  [Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4356
  [Intel XE#4359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4359
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
  [Intel XE#4418]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4418
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4497]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4497
  [Intel XE#4501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4501
  [Intel XE#4502]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4502
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4540
  [Intel XE#4541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4541
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/771
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * IGT: IGT_8271 -> IGTPW_12748

  IGTPW_12748: 12748
  IGT_8271: 8271
  xe-2797-eb17816e52395a403aa0b447aa0befa9d2f86dd5: eb17816e52395a403aa0b447aa0befa9d2f86dd5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12748/index.html

[-- Attachment #2: Type: text/html, Size: 95238 bytes --]