* [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay
@ 2025-07-17 20:41 IVAN.LIPSKI
2025-07-18 15:37 ` Kamil Konieczny
0 siblings, 1 reply; 7+ messages in thread
From: IVAN.LIPSKI @ 2025-07-17 20:41 UTC (permalink / raw)
To: igt-dev; +Cc: sunpeng.li, harry.wentland, amd-gfx, Ivan Lipski
From: Ivan Lipski <ivan.lipski@amd.com>
[Why & How]
The AMD display hardware does not use dedicated cursor planes.
Instead, the cursor is rendered either using the primary plane
or an available overlay plane. This test verifies that the
cursor correctly falls back from native to overlay mode
when the underneath primary plane is incompatible. It also tests
It has 4 subtests:
rgb-to-yuv
Switches the primary plane to a NV12 format FB and verifies that
the cursor falls back from native to overlay.
non-full
Switches the primary planeto a FB that does not fill the entire CRTC
(currently sized at a quarter of the CRTC).
scaling-[50,75,125,150,175,200]
Switches the primary plane to a FB with a chosen scaling (50%-200%), which
is then filled in the CRTC.
no-available-planes
Enables all available overlay planes, a primary plane and a cursor. Then
switches the primary plane to YUV to cause the cursor to fall back to
overlay. Verifies that the atomic commit fails due to no available overlay
planes.
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
---
tests/amdgpu/amd_cursor_overlay.c | 433 ++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 434 insertions(+)
create mode 100644 tests/amdgpu/amd_cursor_overlay.c
diff --git a/tests/amdgpu/amd_cursor_overlay.c b/tests/amdgpu/amd_cursor_overlay.c
new file mode 100644
index 000000000..52cae8454
--- /dev/null
+++ b/tests/amdgpu/amd_cursor_overlay.c
@@ -0,0 +1,433 @@
+/*
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+
+/**
+ * TEST: amd_cursor_overlay
+ * Category: Display
+ * Description: Tests cursor fall back from native to overlay
+ * Driver requirement: amdgpu
+ */
+
+/**
+ * SUBTEST: rgb-to-yuv
+ * Description: Tests native cursor fall back to overlay cursor when a top plane
+ * switches from RGB to YUV.
+ * SUBTEST: non-full
+ * Description: Tests native cursor fall back to overlay cursor when a top plane
+ * does not fill the crtc.
+ * SUBTEST: scaling-%d
+ * Description: Tests native cursor fall back to overlay cursor when a top plane
+ * is scaled.
+ *
+ * arg[1].values: 50, 75, 125, 150, 175, 200
+ *
+ * SUBTEST: no-available-planes
+ * Description: Tests native cursor attempt to fall back to overlay cursor required,
+ * but fails atomic commit due to no available overlay planes.
+ */
+
+enum {
+ TEST_YUV = 1,
+ TEST_QUARTER_FB = 1 << 1,
+ TEST_SCALING = 1 << 2,
+ TEST_NO_PLANES = 1 << 3,
+};
+
+typedef struct {
+ int x;
+ int y;
+} pos_t;
+
+typedef struct {
+ int x;
+ int y;
+ int w;
+ int h;
+} rect_t;
+
+/* Common test data. */
+typedef struct data {
+ igt_display_t display;
+ igt_plane_t *primary;
+ igt_plane_t *cursor;
+ igt_plane_t *overlay1;
+ igt_plane_t *overlay2;
+ igt_output_t *output;
+ igt_pipe_t *pipe;
+ igt_pipe_crc_t *pipe_crc;
+ drmModeModeInfo *mode;
+ igt_fb_t rgb_fb;
+ igt_fb_t yuv_fb;
+ igt_fb_t rgb_fb_o1;
+ igt_fb_t rgb_fb_o2;
+ igt_fb_t quarter_fb;
+ igt_fb_t scale_fb;
+ igt_fb_t cfb;
+ enum pipe pipe_id;
+ int drm_fd;
+ rect_t or;
+ uint64_t max_curw;
+ uint64_t max_curh;
+} data_t;
+
+/* Common test setup. */
+static void test_init(data_t *data, enum pipe pipe_id, igt_output_t *output,
+ unsigned int flags)
+{
+ data->pipe_id = pipe_id;
+ data->pipe = &data->display.pipes[data->pipe_id];
+ data->output = output;
+ data->mode = igt_output_get_mode(data->output);
+ data->primary = igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY);
+ data->cursor = igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_CURSOR);
+
+ if (flags & TEST_NO_PLANES) {
+ data->overlay1 = igt_pipe_get_plane_type_index(data->pipe, DRM_PLANE_TYPE_OVERLAY, 0);
+ data->overlay2 = igt_pipe_get_plane_type_index(data->pipe, DRM_PLANE_TYPE_OVERLAY, 1);
+ }
+
+ igt_info("Using (pipe %s + %s) to run the subtest.\n",
+ kmstest_pipe_name(data->pipe_id), igt_output_name(data->output));
+
+ igt_require_pipe_crc(data->drm_fd);
+ data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe_id,
+ IGT_PIPE_CRC_SOURCE_AUTO);
+}
+
+/* Common test finish. */
+static void test_fini(data_t *data)
+{
+ igt_pipe_crc_free(data->pipe_crc);
+ igt_display_reset(&data->display);
+ igt_plane_set_fb(data->primary, NULL);
+ igt_plane_set_fb(data->cursor, NULL);
+ if (data->overlay1)
+ igt_plane_set_fb(data->overlay1, NULL);
+ if (data->overlay2)
+ igt_plane_set_fb(data->overlay2, NULL);
+ igt_display_commit2(&data->display, COMMIT_ATOMIC);
+}
+
+/* Common test cleanup. */
+static void test_cleanup(data_t *data)
+{
+ igt_remove_fb(data->drm_fd, &data->cfb);
+ igt_remove_fb(data->drm_fd, &data->rgb_fb);
+ igt_remove_fb(data->drm_fd, &data->yuv_fb);
+ igt_remove_fb(data->drm_fd, &data->rgb_fb_o1);
+ igt_remove_fb(data->drm_fd, &data->rgb_fb_o2);
+ igt_remove_fb(data->drm_fd, &data->quarter_fb);
+ igt_remove_fb(data->drm_fd, &data->scale_fb);
+}
+
+
+static void test_cursor_pos(data_t *data, int x, int y, unsigned int flags, unsigned int scaling_factor)
+{
+ igt_crc_t ref_crc, test_crc;
+ cairo_t *cr;
+ igt_fb_t *rgb_fb = &data->rgb_fb;
+ igt_fb_t *yuv_fb = &data->yuv_fb;
+ igt_fb_t *quarter_fb = &data->quarter_fb;
+ igt_fb_t *rgb_fb_o1 = &data->rgb_fb_o1;
+ igt_fb_t *rgb_fb_o2 = &data->rgb_fb_o2;
+ igt_fb_t *cfb = &data->cfb;
+ int cw = cfb->width;
+ int ch = cfb->height;
+ int ret;
+
+
+ cr = igt_get_cairo_ctx(rgb_fb->fd, rgb_fb);
+
+ igt_plane_set_fb(data->primary, rgb_fb);
+ igt_display_commit2(&data->display, COMMIT_ATOMIC);
+
+ igt_paint_color(cr, 0, 0, rgb_fb->width, rgb_fb->height, 0.0, 0.0, 0.0);
+
+ /* Draw a magenta square where the cursor should be. */
+ igt_paint_color(cr, x, y, cw, ch, 1.0, 0.0, 1.0);
+ igt_put_cairo_ctx(cr);
+
+
+ if (flags & TEST_NO_PLANES) {
+
+ /* Display the overlay planes. */
+ igt_plane_set_fb(data->overlay1, rgb_fb_o1);
+ igt_plane_set_position(data->overlay1, 0, 0);
+ igt_plane_set_fb(data->overlay2, rgb_fb_o2);
+ igt_plane_set_position(data->overlay2, data->rgb_fb_o1.width, data->rgb_fb_o1.height);
+ igt_display_commit_atomic(&data->display, 0, NULL);
+
+ /* Display the cursor. */
+ igt_plane_set_fb(data->cursor, cfb);
+ igt_plane_set_position(data->cursor, x, y);
+ igt_display_commit_atomic(&data->display, 0, NULL);
+
+ /* Trigger cursor fall back due to a YUV plane;
+ * expect the atomic commit to fail due to no
+ * available overlay planes.
+ */
+ igt_plane_set_fb(data->primary, &data->yuv_fb);
+ ret = igt_display_try_commit_atomic(&data->display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+ /* Remove the overlay planes. */
+ igt_plane_set_fb(data->overlay1, NULL);
+ igt_plane_set_fb(data->overlay2, NULL);
+ igt_plane_set_fb(data->cursor, NULL);
+ igt_display_commit_atomic(&data->display, 0, NULL);
+
+ /* Expected atomic commit to fail due to no available overlay planes. */
+ igt_assert_f(ret != 0, "Expected atomic commit to fail due to no available overlay planes.\n");
+ return;
+ }
+
+ /* Display the cursor. */
+ igt_plane_set_fb(data->cursor, cfb);
+ igt_plane_set_position(data->cursor, x, y);
+ igt_display_commit_atomic(&data->display, 0, NULL);
+
+ /** Record a reference CRC */
+ igt_pipe_crc_start(data->pipe_crc);
+ igt_pipe_crc_get_current(data->drm_fd, data->pipe_crc, &ref_crc);
+
+ /* Switch primary plane to use YUV Fb. */
+ if (flags & TEST_YUV) {
+ igt_plane_set_fb(data->primary, yuv_fb);
+ igt_plane_set_position(data->primary, 0, 0);
+ igt_plane_set_size(data->primary, yuv_fb->width, yuv_fb->height);
+ igt_display_commit_atomic(&data->display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+ /* Switch primary plane to use a quarter-sized FB. */
+ } else if (flags & TEST_QUARTER_FB) {
+ igt_plane_set_fb(data->primary, quarter_fb);
+ igt_plane_set_position(data->primary, 0, 0);
+ igt_display_commit_atomic(&data->display, 0, NULL);
+
+ /* Switch primary plane to use a scaled FB. */
+ } else if (flags & TEST_SCALING) {
+ igt_create_fb(data->drm_fd,
+ data->rgb_fb.width * scaling_factor / 100,
+ data->rgb_fb.height * scaling_factor / 100,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_LINEAR, &data->scale_fb);
+
+ igt_plane_set_fb(data->primary, &data->scale_fb);
+ igt_plane_set_position(data->primary, 0, 0);
+ igt_plane_set_size(data->primary, data->mode->hdisplay, data->mode->vdisplay);
+
+ igt_display_commit_atomic(&data->display, 0, NULL);
+ }
+
+ /* Wait for one more vblank since cursor updates are not
+ * synchronized to the same frame on AMD hw.
+ */
+ if (is_amdgpu_device(data->drm_fd))
+ igt_wait_for_vblank_count(data->drm_fd, data->display.pipes[data->pipe_id].crtc_offset, 1);
+
+ /* Record the new CRC. */
+ igt_pipe_crc_get_current(data->drm_fd, data->pipe_crc, &test_crc);
+ igt_pipe_crc_stop(data->pipe_crc);
+
+ /** CRC Check is sufficient for this test */
+ igt_assert_crc_equal(&ref_crc, &test_crc);
+}
+
+/*
+ * Tests the cursor on a variety of positions on the screen.
+ * Specific edge cases that should be captured here are the negative edges
+ * of each plane and the centers.
+ */
+static void test_cursor_spots(data_t *data, int size, unsigned int flags, unsigned int scaling_factor)
+{
+ int sw = data->mode->hdisplay;
+ int sh = data->mode->vdisplay;
+ int i;
+ const pos_t pos[] = {
+ /* Test diagonally from top left to bottom right. */
+ { -size / 3, -size / 3 },
+ { 0, 0 },
+ { sw / 4 - size, sh / 4 - size },
+ { sw / 4 - size / 3, sh / 4 - size / 3 },
+ { sw / 4, sh / 4 },
+ { sw / 4 + size, sh / 4 + size },
+ { sw / 2, sh / 2 },
+ { sw / 4 + sw / 2 - size, sh / 4 + sh / 2 - size },
+ { sw / 4 + sw / 2 - size / 3, sh / 4 + sh / 2 - size / 3 },
+ { sw / 4 + sw / 2 + size, sh / 4 + sh / 2 + size },
+ { sw - size, sh - size },
+ { sw - size / 3, sh - size / 3 },
+ /* Test remaining corners. */
+ { sw - size, 0 },
+ { 0, sh - size },
+ { sw / 4 + sw / 2 - size, sh / 4 },
+ { sw / 4, sh / 4 + sh / 2 - size }
+ };
+
+ for (i = 0; i < ARRAY_SIZE(pos); ++i)
+ test_cursor_pos(data, pos[i].x, pos[i].y, flags, scaling_factor);
+}
+
+static void test_cursor(data_t *data, int size, unsigned int flags, unsigned int scaling_factor)
+{
+ int sw, sh;
+
+ igt_skip_on(size > data->max_curw || size > data->max_curh);
+
+ sw = data->mode->hdisplay;
+ sh = data->mode->vdisplay;
+
+ test_cleanup(data);
+
+ /* Create RGB FB for reference. */
+ igt_create_color_fb(data->drm_fd, sw, sh, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_LINEAR, 0.0, 0.0, 0.0, &data->rgb_fb);
+
+ /* Create YUV FB for RGB-to-YUV and NO_PLANES subtests */
+ if (flags & TEST_YUV || flags & TEST_NO_PLANES)
+ igt_create_fb(data->drm_fd, sw, sh, DRM_FORMAT_NV12,
+ DRM_FORMAT_MOD_NONE, &data->yuv_fb);
+
+ /* Create a quarter-sized empty FB. */
+ if (flags & TEST_QUARTER_FB)
+ igt_create_color_fb(data->drm_fd, sw / 2, sh / 2, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_LINEAR, 0.0, 0.0, 0.0, &data->quarter_fb);
+
+ /* Create two RGB FBs for the overlay planes. */
+ if (flags & flags & TEST_NO_PLANES) {
+ igt_create_color_fb(data->drm_fd, sw / 2, sh / 2, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_NONE, 0.5, 0.0, 0.0, &data->rgb_fb_o1);
+ igt_create_color_fb(data->drm_fd, sw / 2, sh / 2, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_NONE, 0.0, 0.0, 0.5, &data->rgb_fb_o2);
+ }
+
+ /* Create a FB for scaling. */
+ if (flags & TEST_SCALING)
+ igt_create_color_fb(data->drm_fd, sw, sh, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_LINEAR, 0.0, 0.0, 0.0, &data->scale_fb);
+
+ /* Create a cursor FB. */
+ igt_create_color_fb(data->drm_fd, size, size, DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_MOD_LINEAR, 1.0, 0.0, 1.0, &data->cfb);
+
+ igt_output_set_pipe(data->output, data->pipe_id);
+
+ /* Run the test for different cursor spots. */
+ test_cursor_spots(data, size, flags, scaling_factor);
+
+}
+
+igt_main
+{
+ static const int cursor_sizes[] = { 64, 128, 256 };
+ data_t data = { .max_curw = 64, .max_curh = 64 };
+ enum pipe pipe;
+ igt_output_t *output;
+ igt_display_t *display;
+ int i, j;
+ struct {
+ const char *name;
+ unsigned int flags;
+ unsigned int scale_factor;
+ const char *desc;
+ } tests[] = {
+ { "rgb-to-yuv", TEST_YUV, 100,
+ "Tests native cursor fall back to overlay cursor when a top plane switches from RGB to YUV" },
+ {"non-full", TEST_QUARTER_FB, 100,
+ "Tests native cursor fall back to overlay cursor when a top plane does not fill the crtc"},
+ {"no-available-planes", TEST_NO_PLANES, 100,
+ "Tests native cursor attempt to fall back to overlay cursor required, but fails atomic commit due to no available overlay planes."},
+ {"scaling-50", TEST_SCALING, 50,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ {"scaling-75", TEST_SCALING, 75,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ {"scaling-125", TEST_SCALING, 125,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ {"scaling-150", TEST_SCALING, 150,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ {"scaling-175", TEST_SCALING, 175,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ {"scaling-200", TEST_SCALING, 200,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ };
+
+ igt_fixture {
+ int ret;
+
+ data.drm_fd = drm_open_driver_master(DRIVER_AMDGPU);
+
+ igt_display_require(&data.display, data.drm_fd);
+ igt_require(data.display.is_atomic);
+ igt_display_require_output(&data.display);
+ display = &data.display;
+
+ ret = drmGetCap(data.drm_fd, DRM_CAP_CURSOR_WIDTH, &data.max_curw);
+ igt_assert(ret == 0 || errno == EINVAL);
+ ret = drmGetCap(data.drm_fd, DRM_CAP_CURSOR_HEIGHT, &data.max_curh);
+ igt_assert(ret == 0 || errno == EINVAL);
+
+ kmstest_set_vt_graphics_mode();
+ }
+
+
+ for (i = 0; i < ARRAY_SIZE(tests); i++) {
+ igt_describe_f("%s", tests[i].desc);
+ igt_subtest_with_dynamic_f("%s", tests[i].name) {
+
+ /* Skip YUV and NO_PLANES subtests if YUV is not supported*/
+ if (tests[i].flags & TEST_YUV || tests[i].flags & TEST_NO_PLANES)
+ igt_require(igt_display_has_format_mod(display,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_MOD_LINEAR));
+
+ for_each_pipe_with_single_output(&data.display, pipe, output) {
+
+ igt_display_reset(display);
+
+ igt_output_set_pipe(output, pipe);
+ if (!intel_pipe_output_combo_valid(display))
+ continue;
+
+ test_init(&data, pipe, output, tests[i].flags);
+
+ for (j = 0; j < ARRAY_SIZE(cursor_sizes); j++) {
+ int size = cursor_sizes[j];
+
+ igt_dynamic_f("pipe-%s-%s-size-%d",
+ kmstest_pipe_name(pipe),
+ igt_output_name(output),
+ size)
+ test_cursor(&data, size, tests[i].flags, tests[i].scale_factor);
+
+ test_cleanup(&data);
+ }
+
+ test_fini(&data);
+ }
+ }
+ }
+
+ igt_fixture {
+ igt_display_fini(&data.display);
+ drm_close_driver(data.drm_fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 421e686d3..b9f1842e2 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -10,6 +10,7 @@ if libdrm_amdgpu.found()
'amd_color',
'amd_cp_dma_misc',
'amd_cs_nop',
+ 'amd_cursor_overlay',
'amd_deadlock',
'amd_dp_dsc',
'amd_freesync_video_mode',
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay
2025-07-17 20:41 IVAN.LIPSKI
@ 2025-07-18 15:37 ` Kamil Konieczny
0 siblings, 0 replies; 7+ messages in thread
From: Kamil Konieczny @ 2025-07-18 15:37 UTC (permalink / raw)
To: IVAN.LIPSKI; +Cc: igt-dev, sunpeng.li, harry.wentland, amd-gfx, Vitaly Prosyak
Hi IVAN.LIPSKI,
On 2025-07-17 at 16:41:46 -0400, IVAN.LIPSKI@amd.com wrote:
> From: Ivan Lipski <ivan.lipski@amd.com>
>
> [Why & How]
> The AMD display hardware does not use dedicated cursor planes.
> Instead, the cursor is rendered either using the primary plane
> or an available overlay plane. This test verifies that the
> cursor correctly falls back from native to overlay mode
> when the underneath primary plane is incompatible. It also tests
>
> It has 4 subtests:
>
> rgb-to-yuv
> Switches the primary plane to a NV12 format FB and verifies that
> the cursor falls back from native to overlay.
>
> non-full
> Switches the primary planeto a FB that does not fill the entire CRTC
> (currently sized at a quarter of the CRTC).
>
> scaling-[50,75,125,150,175,200]
> Switches the primary plane to a FB with a chosen scaling (50%-200%), which
> is then filled in the CRTC.
>
> no-available-planes
> Enables all available overlay planes, a primary plane and a cursor. Then
> switches the primary plane to YUV to cause the cursor to fall back to
> overlay. Verifies that the atomic commit fails due to no available overlay
> planes.
>
> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
> ---
> tests/amdgpu/amd_cursor_overlay.c | 433 ++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 434 insertions(+)
> create mode 100644 tests/amdgpu/amd_cursor_overlay.c
>
> diff --git a/tests/amdgpu/amd_cursor_overlay.c b/tests/amdgpu/amd_cursor_overlay.c
> new file mode 100644
> index 000000000..52cae8454
> --- /dev/null
> +++ b/tests/amdgpu/amd_cursor_overlay.c
> @@ -0,0 +1,433 @@
> +/*
> + * Copyright 2025 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
Please remove it and use SPDX instead.
+cc Vitaly
Regards,
Kamil
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "igt.h"
> +
[cut]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay
@ 2026-01-08 3:07 IVAN.LIPSKI
2026-01-08 4:10 ` ✓ Xe.CI.BAT: success for tests/amdgpu: Add test for native cursor fallback to overlay (rev5) Patchwork
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: IVAN.LIPSKI @ 2026-01-08 3:07 UTC (permalink / raw)
To: igt-dev; +Cc: sunpeng.li, harry.wentland, amd-gfx, Ivan Lipski
From: Ivan Lipski <ivan.lipski@amd.com>
[Why & How]
The AMD display hardware does not use dedicated cursor planes.
Instead, the cursor is rendered either using the primary plane (native)
or an available overlay plane (overlay). This test verifies that the
cursor correctly falls back from native to overlay mode
when the underneath primary plane is incompatible.
It has 5 subtests:
rgb-to-yuv
Switches the primary plane to a YUV format FB and verifies that
the cursor falls back from primary to overlay plane. Uses CRC to verify
that the cursor fall back to overlay plane is successful.
non-full
Switches the primary plane to a FB that does not fill the entire CRTC, not
underneath the cursor to trigger the fall back from native to overlay
plane. Uses CRC to verify that the cursor fall back to overlay plane is
successful.
scaling-[50,75,125,150,175,200]
Switches the primary plane to a FB with a chosen scaling (50%-200%), which
is then filled in the CRTC. Uses CRC to verify that the cursor fall back
to overlay plane is successful.
max-planes
Enables all but one overlay planes, a primary plane and a cursor above
the primary plane. Then switches the primary plane to YUV to cause the
cursor to fall back to use an overlay plane. Uses CRC to verify that the
cursor fall back to overlay plane is successful.
no-available-planes
Enables all available overlay planes, a primary plane and a cursor above
the primary plane. Then switches the primary plane to YUV to cause the
cursor to fall back to overlay. Verifies that the atomic commit fails due
to no available overlay planes.
NOTE: This subtest is currently only available for DCN 2.1 & DCN 3.5 AMD
APU's.
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
---
tests/amdgpu/amd_cursor_overlay.c | 529 ++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 530 insertions(+)
create mode 100644 tests/amdgpu/amd_cursor_overlay.c
diff --git a/tests/amdgpu/amd_cursor_overlay.c b/tests/amdgpu/amd_cursor_overlay.c
new file mode 100644
index 000000000..481219f9f
--- /dev/null
+++ b/tests/amdgpu/amd_cursor_overlay.c
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: MIT
+// Copyright 2025 Advanced Micro Devices, Inc.
+
+#include "igt.h"
+#include "igt_kms.h"
+#include "amdgpu_drm.h"
+#include "amdgpu.h"
+
+/*
+ * Only two ASICs of FAMILY_RV are DCN 2.1.
+ * They can be determined by their external chip revision.
+ *
+ * This is necessary to determine if the NO_AVAILABLE_PLANES subtest is
+ * applicable to the ASIC under test.
+ *
+ * NOTE: Copied from dal_asic_id.h in AMD's display driver on Linux.
+ */
+#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= 0x91) && (eChipRev < 0xF0))
+#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= 0xA1) && (eChipRev < 0xFF))
+
+
+/**
+ * TEST: amd_cursor_overlay
+ * Category: Display
+ * Description: Tests cursor fall back from native to overlay
+ * Driver requirement: amdgpu
+ */
+
+/**
+ * SUBTEST: rgb-to-yuv
+ * Description: Tests native cursor fall back to overlay cursor when a top plane
+ * switches from RGB to YUV.
+ * SUBTEST: non-full
+ * Description: Tests native cursor fall back to overlay cursor when a top plane
+ * does not fill the crtc.
+ * SUBTEST: scaling-%d
+ * Description: Tests native cursor fall back to overlay cursor when a top plane
+ * is scaled.
+ *
+ * arg[1].values: 50, 75, 125, 150, 175, 200
+ *
+ * SUBTEST: max-planes
+ * Description: Tests native cursor fall back to overlay cursor when a top plane
+ * is YUV and there are all but one overlay planes are used.
+ *
+ * SUBTEST: no-available-planes
+ * Description: Tests native cursor attempt to fall back to overlay cursor,
+ * but fails atomic commit due to no available overlay planes.
+ */
+
+enum {
+ TEST_YUV = 1,
+ TEST_QUARTER_FB = 1 << 1,
+ TEST_SCALING = 1 << 2,
+ TEST_MAX_PLANES = 1 << 3,
+ TEST_NO_AVAILABLE_PLANES = 1 << 4,
+};
+
+typedef struct {
+ int x;
+ int y;
+} pos_t;
+
+/* Common test data. */
+typedef struct data {
+ igt_display_t display;
+ igt_plane_t *primary;
+ igt_plane_t *cursor;
+ igt_plane_t *overlays[6];
+ igt_output_t *output;
+ igt_crtc_t *pipe;
+ igt_pipe_crc_t *pipe_crc;
+ drmModeModeInfo *mode;
+ igt_fb_t rgb_fb;
+ igt_fb_t rgb_fb_o;
+ igt_fb_t yuv_fb;
+ igt_fb_t quarter_fb;
+ igt_fb_t scale_fb;
+ igt_fb_t cfb;
+ enum pipe pipe_id;
+ int drm_fd;
+ int available_overlay_planes;
+ uint64_t max_curw;
+ uint64_t max_curh;
+} data_t;
+
+/* Retuns the number of available overlay planes. */
+static int get_overlay_planes_count(igt_display_t *display, enum pipe pipe)
+{
+ int count = 0;
+ igt_plane_t *plane;
+
+ for_each_plane_on_pipe(display, pipe, plane)
+ if (plane->type == DRM_PLANE_TYPE_OVERLAY)
+ count++;
+
+ return count;
+}
+
+/* Sets all overlay planes to the given fb and position, then commits. */
+static void set_overlay_planes(data_t *data, int count, igt_fb_t *fb, int x, int y)
+{
+ for (int i = 0; i < count; i++) {
+ igt_plane_set_fb(data->overlays[i], fb);
+ igt_plane_set_position(data->overlays[i], x, y);
+ }
+ igt_display_commit_atomic(&data->display, 0, NULL);
+}
+
+/*
+ * Checks the ASIC has enough overlay planes and from a supported family.
+ *
+ * Currently TEST_NO_AVAILABLE_PLANES subtest is only
+ * applicable to DCN 2.1 & DCN 3.5+ APUs.
+ */
+static bool can_support_all_overlay_planes(int available_overlay_planes, int family_id, int chip_rev_id)
+{
+ /* For now we only support ASICs with 3 overlay planes. */
+ if (available_overlay_planes != 3)
+ return false;
+
+ switch (family_id) {
+ case AMDGPU_FAMILY_RV:
+ return (ASICREV_IS_RENOIR(chip_rev_id) ||
+ ASICREV_IS_GREEN_SARDINE(chip_rev_id));
+ case AMDGPU_FAMILY_GC_11_5_0:
+ return true;
+ default:
+ return false;
+ }
+}
+
+/* Common test setup. */
+static void test_init(data_t *data, enum pipe pipe_id, igt_output_t *output,
+ unsigned int flags, int available_overlay_planes)
+{
+ int i;
+
+ data->pipe_id = pipe_id;
+ data->available_overlay_planes = available_overlay_planes;
+ data->pipe = &data->display.pipes[data->pipe_id];
+ data->output = output;
+ data->mode = igt_output_get_mode(data->output);
+ data->primary = igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY);
+ data->cursor = igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_CURSOR);
+
+ if (flags & TEST_MAX_PLANES)
+ for (i = 0; i < available_overlay_planes - 1; i++)
+ data->overlays[i] = igt_pipe_get_plane_type_index(data->pipe,
+ DRM_PLANE_TYPE_OVERLAY, i);
+ if (flags & TEST_NO_AVAILABLE_PLANES)
+ for (i = 0; i < available_overlay_planes; i++)
+ data->overlays[i] = igt_pipe_get_plane_type_index(data->pipe,
+ DRM_PLANE_TYPE_OVERLAY, i);
+
+ igt_info("Using (pipe %s + %s) to run the subtest.\n",
+ kmstest_pipe_name(data->pipe_id), igt_output_name(data->output));
+
+ igt_require_pipe_crc(data->drm_fd);
+ data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe_id,
+ IGT_PIPE_CRC_SOURCE_AUTO);
+}
+
+/* Common test finish. */
+static void test_fini(data_t *data)
+{
+ /* Free CRC collector first */
+ igt_pipe_crc_free(data->pipe_crc);
+
+ /* Clear all planes */
+ igt_plane_set_fb(data->primary, NULL);
+ igt_plane_set_fb(data->cursor, NULL);
+
+ for (int i = 0; i < data->available_overlay_planes; i++)
+ if (data->overlays[i])
+ igt_plane_set_fb(data->overlays[i], NULL);
+
+ /* Commit the cleared plane state before resetting the graph */
+ igt_display_commit2(&data->display, COMMIT_ATOMIC);
+
+ /* Reset the display graph after committing the null state */
+ igt_display_reset(&data->display);
+}
+
+/* Common test cleanup. */
+static void test_cleanup(data_t *data)
+{
+ igt_remove_fb(data->drm_fd, &data->cfb);
+ igt_remove_fb(data->drm_fd, &data->rgb_fb);
+ igt_remove_fb(data->drm_fd, &data->rgb_fb_o);
+ igt_remove_fb(data->drm_fd, &data->yuv_fb);
+ igt_remove_fb(data->drm_fd, &data->quarter_fb);
+ igt_remove_fb(data->drm_fd, &data->scale_fb);
+}
+
+
+static void test_cursor_pos(data_t *data, int x, int y, unsigned int flags)
+{
+ igt_crc_t ref_crc, test_crc;
+ cairo_t *cr;
+ igt_fb_t *rgb_fb = &data->rgb_fb;
+ igt_fb_t *rgb_fb_o = &data->rgb_fb_o;
+ igt_fb_t *yuv_fb = &data->yuv_fb;
+ igt_fb_t *quarter_fb = &data->quarter_fb;
+ igt_fb_t *cfb = &data->cfb;
+ igt_fb_t *scale_fb = &data->scale_fb;
+ int cw = cfb->width;
+ int ch = cfb->height;
+ int available_overlay_planes = data->available_overlay_planes;
+ int opp_x, opp_y, ret;
+
+ cr = igt_get_cairo_ctx(rgb_fb->fd, rgb_fb);
+
+ igt_plane_set_fb(data->primary, rgb_fb);
+ igt_display_commit2(&data->display, COMMIT_ATOMIC);
+
+ igt_paint_color(cr, 0, 0, rgb_fb->width, rgb_fb->height, 0.0, 0.0, 0.0);
+
+ /* Draw a magenta square where the cursor should be. */
+ igt_paint_color(cr, x, y, cw, ch, 1.0, 0.0, 1.0);
+ igt_put_cairo_ctx(cr);
+
+ /* Display the cursor. */
+ igt_plane_set_fb(data->cursor, cfb);
+ igt_plane_set_position(data->cursor, x, y);
+ igt_display_commit_atomic(&data->display, 0, NULL);
+
+ /* Place the overlay plane on the opposite quarter of the screen from the cursor. */
+ if (flags & TEST_MAX_PLANES ||
+ flags & TEST_NO_AVAILABLE_PLANES ||
+ flags & TEST_QUARTER_FB) {
+ opp_x = x < (data->mode->hdisplay / 2) ? (data->mode->hdisplay / 2) : 0;
+ opp_y = y < (data->mode->vdisplay / 2) ? (data->mode->vdisplay / 2) : 0;
+ }
+
+ if (flags & TEST_NO_AVAILABLE_PLANES) {
+
+ /* Display the overlay planes. */
+ set_overlay_planes(data, available_overlay_planes, rgb_fb_o, opp_x, opp_y);
+
+ /*
+ * Trigger cursor fall back due to a YUV plane;
+ * expect the atomic commit to fail due to no
+ * available overlay planes.
+ */
+ igt_plane_set_fb(data->primary, &data->yuv_fb);
+ ret = igt_display_try_commit_atomic(&data->display,
+ DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+ /* Expected atomic commit to fail due to no available overlay planes. */
+ igt_assert_f(ret == -EINVAL,
+ "Expected commit fail due to no available overlay planes.\n");
+
+ /* Exit early. */
+ return;
+ }
+
+ /* Display the overlay planes as a reference for TEST_MAX_PLANES. */
+ if (flags & TEST_MAX_PLANES) {
+ /* Display the overlay planes. */
+ set_overlay_planes(data, available_overlay_planes - 1, rgb_fb_o, opp_x, opp_y);
+ }
+
+ /** Record a reference CRC. */
+ igt_pipe_crc_start(data->pipe_crc);
+ igt_pipe_crc_get_current(data->drm_fd, data->pipe_crc, &ref_crc);
+
+ /* Switch primary plane to YUV FB for TEST_YUV and TEST_MAX_PLANES. */
+ if (flags & TEST_YUV || flags & TEST_MAX_PLANES) {
+ igt_plane_set_fb(data->primary, yuv_fb);
+ igt_plane_set_position(data->primary, 0, 0);
+ igt_plane_set_size(data->primary, yuv_fb->width, yuv_fb->height);
+ igt_display_commit_atomic(&data->display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+ /* Switch primary plane to use a quarter-sized FB, opposite from cursor. */
+ } else if (flags & TEST_QUARTER_FB) {
+ igt_plane_set_fb(data->primary, quarter_fb);
+ igt_plane_set_position(data->primary, opp_x, opp_y);
+ igt_display_commit_atomic(&data->display, 0, NULL);
+
+ /* Switch primary plane to use a scaled FB. */
+ } else if (flags & TEST_SCALING) {
+ igt_plane_set_fb(data->primary, scale_fb);
+ igt_plane_set_position(data->primary, 0, 0);
+ igt_plane_set_size(data->primary, data->mode->hdisplay, data->mode->vdisplay);
+ igt_display_commit_atomic(&data->display, 0, NULL);
+ }
+
+ /*
+ * Wait for one more vblank since cursor updates are not
+ * synchronized to the same frame on AMD hw.
+ */
+ if(is_amdgpu_device(data->drm_fd))
+ igt_wait_for_vblank_count(igt_crtc_for_pipe(&data->display, data->pipe_id), 1);
+
+ /* Record the new CRC. */
+ igt_pipe_crc_get_current(data->drm_fd, data->pipe_crc, &test_crc);
+ igt_pipe_crc_stop(data->pipe_crc);
+
+ /* CRC Check is sufficient for this test */
+ igt_assert_crc_equal(&ref_crc, &test_crc);
+}
+
+/*
+ * Tests the cursor on a variety of positions on the screen.
+ * Specific edge cases that should be captured here are the negative edges
+ * of each plane and the centers.
+ */
+static void test_cursor_spots(data_t *data, int size, unsigned int flags)
+{
+ int sw = data->mode->hdisplay;
+ int sh = data->mode->vdisplay;
+ int i;
+ const pos_t pos[] = {
+ /* Test diagonally from top left to bottom right. */
+ { -size / 3, -size / 3 },
+ { 0, 0 },
+ { sw / 4 - size, sh / 4 - size },
+ { sw / 4 - size / 3, sh / 4 - size / 3 },
+ { sw / 4, sh / 4 },
+ { sw / 4 + size, sh / 4 + size },
+ { sw / 2, sh / 2 },
+ { sw / 4 + sw / 2 - size, sh / 4 + sh / 2 - size },
+ { sw / 4 + sw / 2 - size / 3, sh / 4 + sh / 2 - size / 3 },
+ { sw / 4 + sw / 2 + size, sh / 4 + sh / 2 + size },
+ { sw - size, sh - size },
+ { sw - size / 3, sh - size / 3 },
+ /* Test remaining corners. */
+ { sw - size, 0 },
+ { 0, sh - size },
+ { sw / 4 + sw / 2 - size, sh / 4 },
+ { sw / 4, sh / 4 + sh / 2 - size }
+ };
+
+ for (i = 0; i < ARRAY_SIZE(pos); ++i)
+ test_cursor_pos(data, pos[i].x, pos[i].y, flags);
+}
+
+static void test_cursor(data_t *data, int size, unsigned int flags, unsigned int scaling_factor)
+{
+ int sw, sh;
+
+ igt_skip_on(size > data->max_curw || size > data->max_curh);
+
+ sw = data->mode->hdisplay;
+ sh = data->mode->vdisplay;
+
+ test_cleanup(data);
+
+ /* Create primary FB. */
+ igt_create_color_fb(data->drm_fd, sw, sh, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_LINEAR, 0.0, 0.0, 0.0, &data->rgb_fb);
+
+ /* Create cursor FB. */
+ igt_create_color_fb(data->drm_fd, size, size, DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_MOD_LINEAR, 1.0, 0.0, 1.0, &data->cfb);
+
+ /* Create YUV FB for RGB-to-YUV, MAX_PLANES and NO_AVAILABLE_PLANES subtests */
+ if (flags & TEST_YUV ||
+ flags & TEST_MAX_PLANES ||
+ flags & TEST_NO_AVAILABLE_PLANES)
+ igt_create_fb(data->drm_fd, sw, sh, DRM_FORMAT_NV12,
+ DRM_FORMAT_MOD_NONE, &data->yuv_fb);
+
+ /* Create a quarter-sized FB. */
+ if (flags & TEST_QUARTER_FB)
+ igt_create_color_fb(data->drm_fd, sw / 2, sh / 2, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_LINEAR, 0.0, 0.0, 0.0, &data->quarter_fb);
+
+ /* Create a FB for scaling. */
+ if (flags & TEST_SCALING)
+ igt_create_color_fb(data->drm_fd, (sw * scaling_factor) / 100, (sh * scaling_factor) / 100, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_LINEAR, 0.0, 0.0, 0.0, &data->scale_fb);
+
+ /*
+ * Create RGB FB for overlay planes for MAX_PLANES and
+ * NO_AVAILABLE_PLANES subtests.
+ *
+ * The overlay FB size is quarter the screen size to ensure that
+ * the cursor can be placed on the primary plane to trigger fall back.
+ */
+ if (flags & TEST_MAX_PLANES || flags & TEST_NO_AVAILABLE_PLANES) {
+ /* Create RGB FB for overlay planes. */
+ igt_create_color_fb(data->drm_fd, sw / 2, sh / 2, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_LINEAR, 0.0, 1.0, 0.0, &data->rgb_fb_o);
+ }
+
+ igt_output_set_crtc(data->output,
+ igt_crtc_for_pipe(data->output->display, data->pipe_id));
+
+ /* Run the test for different cursor spots. */
+ test_cursor_spots(data, size, flags);
+}
+
+int igt_main()
+{
+ static const int cursor_sizes[] = { 64, 128, 256 };
+ data_t data = { .max_curw = 64, .max_curh = 64 };
+ enum pipe pipe;
+ igt_output_t *output;
+ igt_display_t *display;
+ int i, j, available_overlay_planes;
+ int ret, err, family_id, chip_rev_id;
+ uint32_t major, minor;
+ amdgpu_device_handle device;
+ struct amdgpu_gpu_info gpu_info = {0};
+ struct {
+ const char *name;
+ unsigned int flags;
+ unsigned int scale_factor;
+ const char *desc;
+ } tests[] = {
+ { "rgb-to-yuv", TEST_YUV, 100,
+ "Tests native cursor fall back to overlay cursor when a top plane switches from RGB to YUV" },
+ {"non-full", TEST_QUARTER_FB, 100,
+ "Tests native cursor fall back to overlay cursor when a top plane does not fill the crtc"},
+ {"max-planes", TEST_MAX_PLANES, 100,
+ "Tests native cursor fall back to overlay cursor when a top plane is YUV and there are all but one overlay planes used."},
+ {"no-available-planes", TEST_NO_AVAILABLE_PLANES, 100,
+ "Tests native cursor attempt to fall back to overlay cursor required, but fails atomic commit due to no available overlay planes."},
+ {"scaling-50", TEST_SCALING, 50,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ {"scaling-75", TEST_SCALING, 75,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ {"scaling-125", TEST_SCALING, 125,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ {"scaling-150", TEST_SCALING, 150,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ {"scaling-175", TEST_SCALING, 175,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ {"scaling-200", TEST_SCALING, 200,
+ "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
+ };
+
+ igt_fixture() {
+
+ /* Initialize the driver and retrieve GPU info. */
+ data.drm_fd = drm_open_driver_master(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(data.drm_fd, &major, &minor, &device);
+ igt_require(err == 0);
+
+ err = amdgpu_query_gpu_info(device, &gpu_info);
+ igt_require(err == 0);
+
+ family_id = gpu_info.family_id;
+ chip_rev_id = gpu_info.chip_external_rev;
+
+ igt_display_require(&data.display, data.drm_fd);
+ igt_require(data.display.is_atomic);
+ igt_display_require_output(&data.display);
+ display = &data.display;
+
+ ret = drmGetCap(data.drm_fd, DRM_CAP_CURSOR_WIDTH, &data.max_curw);
+ igt_assert(ret == 0 || errno == EINVAL);
+ ret = drmGetCap(data.drm_fd, DRM_CAP_CURSOR_HEIGHT, &data.max_curh);
+ igt_assert(ret == 0 || errno == EINVAL);
+
+ kmstest_set_vt_graphics_mode();
+ }
+
+
+ for (i = 0; i < ARRAY_SIZE(tests); i++) {
+ igt_describe_f("%s", tests[i].desc);
+ igt_subtest_with_dynamic_f("%s", tests[i].name) {
+
+ /*
+ * Skip YUV, MAX_PLANES and NO_AVAILABLE_PLANES subtests
+ * if YUV is not supported.
+ */
+ if (tests[i].flags & TEST_YUV ||
+ tests[i].flags & TEST_MAX_PLANES ||
+ tests[i].flags & TEST_NO_AVAILABLE_PLANES)
+ igt_require(igt_display_has_format_mod(display,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_MOD_LINEAR));
+
+ for_each_pipe_with_single_output(&data.display, pipe, output) {
+
+ igt_display_reset(display);
+ igt_output_set_crtc(output,
+ igt_crtc_for_pipe(output->display, pipe));
+
+ available_overlay_planes = get_overlay_planes_count(display, pipe);
+
+ /* Require at least one overlay plane. */
+ if (!available_overlay_planes)
+ igt_skip("%s subtest requires at least 1 overlay plane.\n",
+ tests[i].name);
+
+ /*
+ * For now, NO_AVAILABLE_PLANES substest is only appropriate for
+ * AMD ASICs with 3 overlay planes and with DCN 2.1 & 3.5+ APU's.
+ */
+ if (tests[i].flags & TEST_NO_AVAILABLE_PLANES &&
+ !can_support_all_overlay_planes(available_overlay_planes, family_id, chip_rev_id))
+ igt_skip("%s subtest requires 3 overlay planes with a supported DCN.\n",
+ tests[i].name);
+
+ test_init(&data, pipe, output, tests[i].flags, available_overlay_planes);
+
+ for (j = 0; j < ARRAY_SIZE(cursor_sizes); j++) {
+ int size = cursor_sizes[j];
+
+ igt_dynamic_f("pipe-%s-%s-size-%d",
+ kmstest_pipe_name(pipe),
+ igt_output_name(output),
+ size)
+ test_cursor(&data, size, tests[i].flags, tests[i].scale_factor);
+
+ test_cleanup(&data);
+ }
+
+ test_fini(&data);
+
+ /* Detach output and commit a clean state before moving to the next subtest */
+ igt_output_set_crtc(output, NULL);
+ igt_display_commit2(&data.display, COMMIT_ATOMIC);
+ }
+ }
+ }
+
+ igt_fixture() {
+
+ igt_display_reset(&data.display);
+ igt_display_commit2(&data.display, COMMIT_ATOMIC);
+ igt_display_fini(&data.display);
+ drm_close_driver(data.drm_fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index b718699f1..01c8b4fec 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -12,6 +12,7 @@ if libdrm_amdgpu.found()
'amd_color',
'amd_cp_dma_misc',
'amd_cs_nop',
+ 'amd_cursor_overlay',
'amd_deadlock',
'amd_dp_dsc',
'amd_freesync_video_mode',
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ Xe.CI.BAT: success for tests/amdgpu: Add test for native cursor fallback to overlay (rev5)
2026-01-08 3:07 [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay IVAN.LIPSKI
@ 2026-01-08 4:10 ` Patchwork
2026-01-08 4:30 ` ✗ i915.CI.BAT: failure " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-01-08 4:10 UTC (permalink / raw)
To: ivan.lipski; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 1503 bytes --]
== Series Details ==
Series: tests/amdgpu: Add test for native cursor fallback to overlay (rev5)
URL : https://patchwork.freedesktop.org/series/151797/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_8692_BAT -> XEIGTPW_14311_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in XEIGTPW_14311_BAT that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@xe_waitfence@reltime:
- bat-dg2-oem2: [FAIL][1] ([Intel XE#6520]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520
Build changes
-------------
* IGT: IGT_8692 -> IGTPW_14311
* Linux: xe-4339-77ca0c5f244b2796408d20cf3c0741094304e09f -> xe-4343-25815d6185d3efe226238025baddf01299c4b070
IGTPW_14311: 14311
IGT_8692: 8692
xe-4339-77ca0c5f244b2796408d20cf3c0741094304e09f: 77ca0c5f244b2796408d20cf3c0741094304e09f
xe-4343-25815d6185d3efe226238025baddf01299c4b070: 25815d6185d3efe226238025baddf01299c4b070
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/index.html
[-- Attachment #2: Type: text/html, Size: 2079 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ i915.CI.BAT: failure for tests/amdgpu: Add test for native cursor fallback to overlay (rev5)
2026-01-08 3:07 [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay IVAN.LIPSKI
2026-01-08 4:10 ` ✓ Xe.CI.BAT: success for tests/amdgpu: Add test for native cursor fallback to overlay (rev5) Patchwork
@ 2026-01-08 4:30 ` Patchwork
2026-01-08 5:27 ` ✓ Xe.CI.Full: success " Patchwork
2026-01-12 14:35 ` [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay Leo Li
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-01-08 4:30 UTC (permalink / raw)
To: ivan.lipski; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 4080 bytes --]
== Series Details ==
Series: tests/amdgpu: Add test for native cursor fallback to overlay (rev5)
URL : https://patchwork.freedesktop.org/series/151797/
State : failure
== Summary ==
CI Bug Log - changes from IGT_8692 -> IGTPW_14311
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_14311 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_14311, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14311/index.html
Participating hosts (42 -> 41)
------------------------------
Additional (1): fi-glk-j4005
Missing (2): bat-dg2-13 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_14311:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@perf:
- bat-arlh-3: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8692/bat-arlh-3/igt@i915_selftest@live@perf.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14311/bat-arlh-3/igt@i915_selftest@live@perf.html
Known issues
------------
Here are the changes found in IGTPW_14311 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-glk-j4005: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14311/fi-glk-j4005/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-glk-j4005: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14311/fi-glk-j4005/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live:
- bat-arlh-3: [PASS][5] -> [INCOMPLETE][6] ([i915#14837])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8692/bat-arlh-3/igt@i915_selftest@live.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14311/bat-arlh-3/igt@i915_selftest@live.html
* igt@i915_selftest@live@guc:
- bat-adlp-11: [PASS][7] -> [ABORT][8] ([i915#14365]) +1 other test abort
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8692/bat-adlp-11/igt@i915_selftest@live@guc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14311/bat-adlp-11/igt@i915_selftest@live@guc.html
* igt@kms_psr@psr-primary-page-flip:
- fi-glk-j4005: NOTRUN -> [SKIP][9] +12 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14311/fi-glk-j4005/igt@kms_psr@psr-primary-page-flip.html
#### Possible fixes ####
* igt@i915_selftest@live@workarounds:
- bat-dg2-14: [DMESG-FAIL][10] ([i915#12061]) -> [PASS][11] +1 other test pass
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8692/bat-dg2-14/igt@i915_selftest@live@workarounds.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14311/bat-dg2-14/igt@i915_selftest@live@workarounds.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#14365]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14365
[i915#14837]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14837
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_8692 -> IGTPW_14311
* Linux: CI_DRM_17776 -> CI_DRM_17780
CI-20190529: 20190529
CI_DRM_17776: 77ca0c5f244b2796408d20cf3c0741094304e09f @ git://anongit.freedesktop.org/gfx-ci/linux
CI_DRM_17780: 25815d6185d3efe226238025baddf01299c4b070 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_14311: 14311
IGT_8692: 8692
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14311/index.html
[-- Attachment #2: Type: text/html, Size: 4872 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Xe.CI.Full: success for tests/amdgpu: Add test for native cursor fallback to overlay (rev5)
2026-01-08 3:07 [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay IVAN.LIPSKI
2026-01-08 4:10 ` ✓ Xe.CI.BAT: success for tests/amdgpu: Add test for native cursor fallback to overlay (rev5) Patchwork
2026-01-08 4:30 ` ✗ i915.CI.BAT: failure " Patchwork
@ 2026-01-08 5:27 ` Patchwork
2026-01-12 14:35 ` [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay Leo Li
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-01-08 5:27 UTC (permalink / raw)
To: ivan.lipski; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 45781 bytes --]
== Series Details ==
Series: tests/amdgpu: Add test for native cursor fallback to overlay (rev5)
URL : https://patchwork.freedesktop.org/series/151797/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_8692_FULL -> XEIGTPW_14311_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in XEIGTPW_14311_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@async-flip-with-page-flip-events-linear:
- shard-lnl: [PASS][1] -> [FAIL][2] ([Intel XE#5993]) +3 other tests fail
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][3] ([Intel XE#2327]) +4 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#610]) +1 other test skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-lnl: NOTRUN -> [SKIP][5] ([Intel XE#1124]) +2 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#1124]) +11 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p:
- shard-lnl: [PASS][7] -> [ABORT][8] ([Intel XE#4760])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-2/igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-8/igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p.html
* igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-1-displays-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#367]) +2 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html
* igt@kms_ccs@bad-aux-stride-yf-tiled-ccs:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#2887]) +24 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][12] ([Intel XE#2887]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2652] / [Intel XE#787]) +26 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#3432]) +2 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_cdclk@mode-transition:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2724])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#2325]) +3 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_color@gamma:
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#306])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-5/igt@kms_chamelium_color@gamma.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2252]) +11 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_hpd@dp-hpd-after-hibernate:
- shard-lnl: NOTRUN -> [SKIP][19] ([Intel XE#373]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@kms_chamelium_hpd@dp-hpd-after-hibernate.html
* igt@kms_content_protection@atomic:
- shard-bmg: NOTRUN -> [FAIL][20] ([Intel XE#1178] / [Intel XE#3304]) +5 other tests fail
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][21] ([Intel XE#3304]) +1 other test fail
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2390])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2341])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@uevent-hdcp14:
- shard-bmg: NOTRUN -> [FAIL][24] ([Intel XE#6707]) +1 other test fail
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@kms_content_protection@uevent-hdcp14.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#2320]) +7 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#2321]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-bmg: [PASS][27] -> [DMESG-WARN][28] ([Intel XE#5354])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-10/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-lnl: NOTRUN -> [SKIP][29] ([Intel XE#309])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#1508])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_dp_link_training@uhbr-sst:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#4354])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@kms_dp_link_training@uhbr-sst.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#2244]) +3 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#4422])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#776])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@chamelium:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2372])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@dp-mst:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#2375])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr2:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#2374])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-lnl: NOTRUN -> [SKIP][38] ([Intel XE#1421]) +1 other test skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#1401] / [Intel XE#1745])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][40] ([Intel XE#1401])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#2293] / [Intel XE#2380]) +10 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#2293]) +10 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#4141]) +19 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][44] ([Intel XE#651]) +2 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#2311]) +55 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2313]) +42 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#2350])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][48] ([Intel XE#656]) +6 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#3544])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3:
- shard-bmg: NOTRUN -> [ABORT][50] ([Intel XE#6740])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3.html
* igt@kms_hdr@static-toggle-suspend:
- shard-lnl: NOTRUN -> [SKIP][51] ([Intel XE#1503])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-7/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@basic-big-joiner:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#6901])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-lnl: NOTRUN -> [SKIP][53] ([Intel XE#6900])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#6911])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_pipe_stress@stress-xrgb8888-ytiled:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#4329] / [Intel XE#6912])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
* igt@kms_plane_lowres@tiling-none@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [SKIP][56] ([Intel XE#599]) +4 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-1/igt@kms_plane_lowres@tiling-none@pipe-b-edp-1.html
* igt@kms_plane_multiple@tiling-y:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#5020])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_plane_multiple@tiling-y.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#2938])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_backlight@fade:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#870])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@kms_pm_backlight@fade.html
* igt@kms_pm_dc@dc6-psr:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#2392]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#2499])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#1406] / [Intel XE#1489]) +13 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
- shard-lnl: NOTRUN -> [SKIP][64] ([Intel XE#1406] / [Intel XE#2893])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-bmg: NOTRUN -> [SKIP][65] ([Intel XE#1406] / [Intel XE#2387])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-psr2-cursor-plane-move:
- shard-bmg: NOTRUN -> [SKIP][66] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +21 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@kms_psr@fbc-psr2-cursor-plane-move.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-lnl: [PASS][67] -> [SKIP][68] ([Intel XE#1406] / [Intel XE#4692])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-8/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-bmg: NOTRUN -> [SKIP][69] ([Intel XE#1406] / [Intel XE#2414])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-bmg: NOTRUN -> [SKIP][70] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#2413])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_sharpness_filter@invalid-filter-with-scaling-mode:
- shard-bmg: NOTRUN -> [SKIP][72] ([Intel XE#6503]) +4 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@kms_sharpness_filter@invalid-filter-with-scaling-mode.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#1499])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
- shard-lnl: [PASS][74] -> [FAIL][75] ([Intel XE#2142]) +1 other test fail
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-7/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-lnl: NOTRUN -> [SKIP][76] ([Intel XE#1499])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-7/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@xe_compute@eu-busy-10s:
- shard-bmg: NOTRUN -> [SKIP][77] ([Intel XE#6599]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@xe_compute@eu-busy-10s.html
* igt@xe_eudebug@basic-vm-access-faultable:
- shard-lnl: NOTRUN -> [SKIP][78] ([Intel XE#4837]) +2 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-7/igt@xe_eudebug@basic-vm-access-faultable.html
* igt@xe_eudebug@basic-vm-bind-metadata-discovery:
- shard-bmg: NOTRUN -> [SKIP][79] ([Intel XE#4837]) +17 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
* igt@xe_eudebug_online@pagefault-one-of-many:
- shard-lnl: NOTRUN -> [SKIP][80] ([Intel XE#6665])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-4/igt@xe_eudebug_online@pagefault-one-of-many.html
* igt@xe_eudebug_online@pagefault-read-stress:
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#6665] / [Intel XE#6681])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@xe_eudebug_online@pagefault-read-stress.html
* igt@xe_eudebug_online@resume-dss:
- shard-lnl: NOTRUN -> [SKIP][82] ([Intel XE#4837] / [Intel XE#6665])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-5/igt@xe_eudebug_online@resume-dss.html
* igt@xe_eudebug_online@single-step:
- shard-bmg: NOTRUN -> [SKIP][83] ([Intel XE#4837] / [Intel XE#6665]) +8 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@xe_eudebug_online@single-step.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-bmg: NOTRUN -> [INCOMPLETE][84] ([Intel XE#6321])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_evict@evict-small-cm:
- shard-lnl: NOTRUN -> [SKIP][85] ([Intel XE#688]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-8/igt@xe_evict@evict-small-cm.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
- shard-bmg: NOTRUN -> [SKIP][86] ([Intel XE#2322]) +13 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
* igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap:
- shard-lnl: NOTRUN -> [SKIP][87] ([Intel XE#1392]) +2 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html
* igt@xe_exec_multi_queue@many-execs-priority:
- shard-lnl: NOTRUN -> [SKIP][88] ([Intel XE#6874]) +4 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@xe_exec_multi_queue@many-execs-priority.html
* igt@xe_exec_multi_queue@two-queues-priority:
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#6874]) +45 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@xe_exec_multi_queue@two-queues-priority.html
* igt@xe_exec_system_allocator@many-64k-mmap-new-huge:
- shard-bmg: NOTRUN -> [SKIP][90] ([Intel XE#5007]) +3 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge:
- shard-bmg: NOTRUN -> [SKIP][91] ([Intel XE#4943]) +37 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-new-huge:
- shard-lnl: NOTRUN -> [SKIP][92] ([Intel XE#4943]) +3 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-5/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-new-huge.html
* igt@xe_media_fill@media-fill:
- shard-bmg: NOTRUN -> [SKIP][93] ([Intel XE#2459] / [Intel XE#2596])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@xe_media_fill@media-fill.html
* igt@xe_multigpu_svm@mgpu-coherency-fail-prefetch:
- shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#6964]) +4 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@xe_multigpu_svm@mgpu-coherency-fail-prefetch.html
* igt@xe_multigpu_svm@mgpu-migration-prefetch:
- shard-lnl: NOTRUN -> [SKIP][95] ([Intel XE#6964]) +1 other test skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-2/igt@xe_multigpu_svm@mgpu-migration-prefetch.html
* igt@xe_pat@pat-index-xelpg:
- shard-bmg: NOTRUN -> [SKIP][96] ([Intel XE#2236])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@xe_pat@pat-index-xelpg.html
* igt@xe_peer2peer@read:
- shard-bmg: NOTRUN -> [SKIP][97] ([Intel XE#2427] / [Intel XE#6953])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@xe_peer2peer@read.html
* igt@xe_pm@d3hot-i2c:
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#5742])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@xe_pm@d3hot-i2c.html
* igt@xe_pm@s3-d3cold-basic-exec:
- shard-bmg: NOTRUN -> [SKIP][99] ([Intel XE#2284]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@xe_pm@s3-d3cold-basic-exec.html
* igt@xe_pxp@pxp-stale-bo-exec-post-suspend:
- shard-bmg: NOTRUN -> [SKIP][100] ([Intel XE#4733])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html
* igt@xe_query@multigpu-query-invalid-size:
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#944]) +3 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@xe_query@multigpu-query-invalid-size.html
* igt@xe_query@multigpu-query-topology:
- shard-lnl: NOTRUN -> [SKIP][102] ([Intel XE#944])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-8/igt@xe_query@multigpu-query-topology.html
#### Possible fixes ####
* igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
- shard-lnl: [FAIL][103] ([Intel XE#6054]) -> [PASS][104] +3 other tests pass
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-2/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [FAIL][105] ([Intel XE#301]) -> [PASS][106] +1 other test pass
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_pm_dc@dc6-dpms:
- shard-lnl: [FAIL][107] ([Intel XE#718]) -> [PASS][108] +1 other test pass
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-5/igt@kms_pm_dc@dc6-dpms.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-4/igt@kms_pm_dc@dc6-dpms.html
* igt@xe_module_load@load:
- shard-lnl: ([SKIP][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134]) ([Intel XE#378]) -> ([PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159])
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-7/igt@xe_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-5/igt@xe_module_load@load.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-4/igt@xe_module_load@load.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-5/igt@xe_module_load@load.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-7/igt@xe_module_load@load.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-8/igt@xe_module_load@load.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-8/igt@xe_module_load@load.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-1/igt@xe_module_load@load.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-4/igt@xe_module_load@load.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-2/igt@xe_module_load@load.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-2/igt@xe_module_load@load.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-3/igt@xe_module_load@load.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-4/igt@xe_module_load@load.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-3/igt@xe_module_load@load.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-3/igt@xe_module_load@load.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-4/igt@xe_module_load@load.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-8/igt@xe_module_load@load.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-2/igt@xe_module_load@load.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-1/igt@xe_module_load@load.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-1/igt@xe_module_load@load.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-8/igt@xe_module_load@load.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-5/igt@xe_module_load@load.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-7/igt@xe_module_load@load.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-7/igt@xe_module_load@load.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-7/igt@xe_module_load@load.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-lnl-3/igt@xe_module_load@load.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-8/igt@xe_module_load@load.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-7/igt@xe_module_load@load.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@xe_module_load@load.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@xe_module_load@load.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@xe_module_load@load.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-7/igt@xe_module_load@load.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-2/igt@xe_module_load@load.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-2/igt@xe_module_load@load.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-8/igt@xe_module_load@load.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-8/igt@xe_module_load@load.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-8/igt@xe_module_load@load.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-8/igt@xe_module_load@load.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-4/igt@xe_module_load@load.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-5/igt@xe_module_load@load.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-3/igt@xe_module_load@load.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-5/igt@xe_module_load@load.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-1/igt@xe_module_load@load.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-1/igt@xe_module_load@load.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-5/igt@xe_module_load@load.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-2/igt@xe_module_load@load.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-4/igt@xe_module_load@load.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-4/igt@xe_module_load@load.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-1/igt@xe_module_load@load.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-7/igt@xe_module_load@load.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-lnl-7/igt@xe_module_load@load.html
- shard-bmg: ([PASS][160], [SKIP][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172], [PASS][173]) ([Intel XE#2457]) -> ([PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179], [PASS][180], [PASS][181], [PASS][182], [PASS][183], [PASS][184], [PASS][185], [PASS][186])
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-1/igt@xe_module_load@load.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-3/igt@xe_module_load@load.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-9/igt@xe_module_load@load.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-3/igt@xe_module_load@load.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-3/igt@xe_module_load@load.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-9/igt@xe_module_load@load.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-3/igt@xe_module_load@load.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-10/igt@xe_module_load@load.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-9/igt@xe_module_load@load.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-10/igt@xe_module_load@load.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-2/igt@xe_module_load@load.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-2/igt@xe_module_load@load.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-2/igt@xe_module_load@load.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-1/igt@xe_module_load@load.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@xe_module_load@load.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@xe_module_load@load.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@xe_module_load@load.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@xe_module_load@load.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-1/igt@xe_module_load@load.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@xe_module_load@load.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-9/igt@xe_module_load@load.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@xe_module_load@load.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@xe_module_load@load.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@xe_module_load@load.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-10/igt@xe_module_load@load.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@xe_module_load@load.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@xe_module_load@load.html
#### Warnings ####
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][187] ([Intel XE#1503]) -> [ABORT][188] ([Intel XE#6740])
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-9/igt@kms_hdr@invalid-hdr.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-3/igt@kms_hdr@invalid-hdr.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][189] ([Intel XE#2426]) -> [FAIL][190] ([Intel XE#1729])
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8692/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern.html
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2350
[Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
[Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
[Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
[Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
[Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4692]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4692
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4760
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
[Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
[Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
[Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
[Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
[Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
[Intel XE#6681]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6681
[Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
[Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
[Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
[Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
[Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
[Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_8692 -> IGTPW_14311
* Linux: xe-4339-77ca0c5f244b2796408d20cf3c0741094304e09f -> xe-4343-25815d6185d3efe226238025baddf01299c4b070
IGTPW_14311: 14311
IGT_8692: 8692
xe-4339-77ca0c5f244b2796408d20cf3c0741094304e09f: 77ca0c5f244b2796408d20cf3c0741094304e09f
xe-4343-25815d6185d3efe226238025baddf01299c4b070: 25815d6185d3efe226238025baddf01299c4b070
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14311/index.html
[-- Attachment #2: Type: text/html, Size: 50643 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay
2026-01-08 3:07 [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay IVAN.LIPSKI
` (2 preceding siblings ...)
2026-01-08 5:27 ` ✓ Xe.CI.Full: success " Patchwork
@ 2026-01-12 14:35 ` Leo Li
3 siblings, 0 replies; 7+ messages in thread
From: Leo Li @ 2026-01-12 14:35 UTC (permalink / raw)
To: IVAN.LIPSKI, igt-dev; +Cc: harry.wentland, amd-gfx
On 2026-01-07 22:07, IVAN.LIPSKI@amd.com wrote:
> From: Ivan Lipski <ivan.lipski@amd.com>
>
> [Why & How]
> The AMD display hardware does not use dedicated cursor planes.
> Instead, the cursor is rendered either using the primary plane (native)
> or an available overlay plane (overlay). This test verifies that the
> cursor correctly falls back from native to overlay mode
> when the underneath primary plane is incompatible.
> It has 5 subtests:
>
> rgb-to-yuv
> Switches the primary plane to a YUV format FB and verifies that
> the cursor falls back from primary to overlay plane. Uses CRC to verify
> that the cursor fall back to overlay plane is successful.
>
> non-full
> Switches the primary plane to a FB that does not fill the entire CRTC, not
> underneath the cursor to trigger the fall back from native to overlay
> plane. Uses CRC to verify that the cursor fall back to overlay plane is
> successful.
>
> scaling-[50,75,125,150,175,200]
> Switches the primary plane to a FB with a chosen scaling (50%-200%), which
> is then filled in the CRTC. Uses CRC to verify that the cursor fall back
> to overlay plane is successful.
>
> max-planes
> Enables all but one overlay planes, a primary plane and a cursor above
> the primary plane. Then switches the primary plane to YUV to cause the
> cursor to fall back to use an overlay plane. Uses CRC to verify that the
> cursor fall back to overlay plane is successful.
>
> no-available-planes
> Enables all available overlay planes, a primary plane and a cursor above
> the primary plane. Then switches the primary plane to YUV to cause the
> cursor to fall back to overlay. Verifies that the atomic commit fails due
> to no available overlay planes.
> NOTE: This subtest is currently only available for DCN 2.1 & DCN 3.5 AMD
> APU's.
>
> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Thanks for the test!
Reviewed-by: Leo Li <sunpeng.li@amd.com>
- Leo
> ---
> tests/amdgpu/amd_cursor_overlay.c | 529 ++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 530 insertions(+)
> create mode 100644 tests/amdgpu/amd_cursor_overlay.c
>
> diff --git a/tests/amdgpu/amd_cursor_overlay.c b/tests/amdgpu/amd_cursor_overlay.c
> new file mode 100644
> index 000000000..481219f9f
> --- /dev/null
> +++ b/tests/amdgpu/amd_cursor_overlay.c
> @@ -0,0 +1,529 @@
> +// SPDX-License-Identifier: MIT
> +// Copyright 2025 Advanced Micro Devices, Inc.
> +
> +#include "igt.h"
> +#include "igt_kms.h"
> +#include "amdgpu_drm.h"
> +#include "amdgpu.h"
> +
> +/*
> + * Only two ASICs of FAMILY_RV are DCN 2.1.
> + * They can be determined by their external chip revision.
> + *
> + * This is necessary to determine if the NO_AVAILABLE_PLANES subtest is
> + * applicable to the ASIC under test.
> + *
> + * NOTE: Copied from dal_asic_id.h in AMD's display driver on Linux.
> + */
> +#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= 0x91) && (eChipRev < 0xF0))
> +#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= 0xA1) && (eChipRev < 0xFF))
> +
> +
> +/**
> + * TEST: amd_cursor_overlay
> + * Category: Display
> + * Description: Tests cursor fall back from native to overlay
> + * Driver requirement: amdgpu
> + */
> +
> +/**
> + * SUBTEST: rgb-to-yuv
> + * Description: Tests native cursor fall back to overlay cursor when a top plane
> + * switches from RGB to YUV.
> + * SUBTEST: non-full
> + * Description: Tests native cursor fall back to overlay cursor when a top plane
> + * does not fill the crtc.
> + * SUBTEST: scaling-%d
> + * Description: Tests native cursor fall back to overlay cursor when a top plane
> + * is scaled.
> + *
> + * arg[1].values: 50, 75, 125, 150, 175, 200
> + *
> + * SUBTEST: max-planes
> + * Description: Tests native cursor fall back to overlay cursor when a top plane
> + * is YUV and there are all but one overlay planes are used.
> + *
> + * SUBTEST: no-available-planes
> + * Description: Tests native cursor attempt to fall back to overlay cursor,
> + * but fails atomic commit due to no available overlay planes.
> + */
> +
> +enum {
> + TEST_YUV = 1,
> + TEST_QUARTER_FB = 1 << 1,
> + TEST_SCALING = 1 << 2,
> + TEST_MAX_PLANES = 1 << 3,
> + TEST_NO_AVAILABLE_PLANES = 1 << 4,
> +};
> +
> +typedef struct {
> + int x;
> + int y;
> +} pos_t;
> +
> +/* Common test data. */
> +typedef struct data {
> + igt_display_t display;
> + igt_plane_t *primary;
> + igt_plane_t *cursor;
> + igt_plane_t *overlays[6];
> + igt_output_t *output;
> + igt_crtc_t *pipe;
> + igt_pipe_crc_t *pipe_crc;
> + drmModeModeInfo *mode;
> + igt_fb_t rgb_fb;
> + igt_fb_t rgb_fb_o;
> + igt_fb_t yuv_fb;
> + igt_fb_t quarter_fb;
> + igt_fb_t scale_fb;
> + igt_fb_t cfb;
> + enum pipe pipe_id;
> + int drm_fd;
> + int available_overlay_planes;
> + uint64_t max_curw;
> + uint64_t max_curh;
> +} data_t;
> +
> +/* Retuns the number of available overlay planes. */
> +static int get_overlay_planes_count(igt_display_t *display, enum pipe pipe)
> +{
> + int count = 0;
> + igt_plane_t *plane;
> +
> + for_each_plane_on_pipe(display, pipe, plane)
> + if (plane->type == DRM_PLANE_TYPE_OVERLAY)
> + count++;
> +
> + return count;
> +}
> +
> +/* Sets all overlay planes to the given fb and position, then commits. */
> +static void set_overlay_planes(data_t *data, int count, igt_fb_t *fb, int x, int y)
> +{
> + for (int i = 0; i < count; i++) {
> + igt_plane_set_fb(data->overlays[i], fb);
> + igt_plane_set_position(data->overlays[i], x, y);
> + }
> + igt_display_commit_atomic(&data->display, 0, NULL);
> +}
> +
> +/*
> + * Checks the ASIC has enough overlay planes and from a supported family.
> + *
> + * Currently TEST_NO_AVAILABLE_PLANES subtest is only
> + * applicable to DCN 2.1 & DCN 3.5+ APUs.
> + */
> +static bool can_support_all_overlay_planes(int available_overlay_planes, int family_id, int chip_rev_id)
> +{
> + /* For now we only support ASICs with 3 overlay planes. */
> + if (available_overlay_planes != 3)
> + return false;
> +
> + switch (family_id) {
> + case AMDGPU_FAMILY_RV:
> + return (ASICREV_IS_RENOIR(chip_rev_id) ||
> + ASICREV_IS_GREEN_SARDINE(chip_rev_id));
> + case AMDGPU_FAMILY_GC_11_5_0:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +/* Common test setup. */
> +static void test_init(data_t *data, enum pipe pipe_id, igt_output_t *output,
> + unsigned int flags, int available_overlay_planes)
> +{
> + int i;
> +
> + data->pipe_id = pipe_id;
> + data->available_overlay_planes = available_overlay_planes;
> + data->pipe = &data->display.pipes[data->pipe_id];
> + data->output = output;
> + data->mode = igt_output_get_mode(data->output);
> + data->primary = igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY);
> + data->cursor = igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_CURSOR);
> +
> + if (flags & TEST_MAX_PLANES)
> + for (i = 0; i < available_overlay_planes - 1; i++)
> + data->overlays[i] = igt_pipe_get_plane_type_index(data->pipe,
> + DRM_PLANE_TYPE_OVERLAY, i);
> + if (flags & TEST_NO_AVAILABLE_PLANES)
> + for (i = 0; i < available_overlay_planes; i++)
> + data->overlays[i] = igt_pipe_get_plane_type_index(data->pipe,
> + DRM_PLANE_TYPE_OVERLAY, i);
> +
> + igt_info("Using (pipe %s + %s) to run the subtest.\n",
> + kmstest_pipe_name(data->pipe_id), igt_output_name(data->output));
> +
> + igt_require_pipe_crc(data->drm_fd);
> + data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe_id,
> + IGT_PIPE_CRC_SOURCE_AUTO);
> +}
> +
> +/* Common test finish. */
> +static void test_fini(data_t *data)
> +{
> + /* Free CRC collector first */
> + igt_pipe_crc_free(data->pipe_crc);
> +
> + /* Clear all planes */
> + igt_plane_set_fb(data->primary, NULL);
> + igt_plane_set_fb(data->cursor, NULL);
> +
> + for (int i = 0; i < data->available_overlay_planes; i++)
> + if (data->overlays[i])
> + igt_plane_set_fb(data->overlays[i], NULL);
> +
> + /* Commit the cleared plane state before resetting the graph */
> + igt_display_commit2(&data->display, COMMIT_ATOMIC);
> +
> + /* Reset the display graph after committing the null state */
> + igt_display_reset(&data->display);
> +}
> +
> +/* Common test cleanup. */
> +static void test_cleanup(data_t *data)
> +{
> + igt_remove_fb(data->drm_fd, &data->cfb);
> + igt_remove_fb(data->drm_fd, &data->rgb_fb);
> + igt_remove_fb(data->drm_fd, &data->rgb_fb_o);
> + igt_remove_fb(data->drm_fd, &data->yuv_fb);
> + igt_remove_fb(data->drm_fd, &data->quarter_fb);
> + igt_remove_fb(data->drm_fd, &data->scale_fb);
> +}
> +
> +
> +static void test_cursor_pos(data_t *data, int x, int y, unsigned int flags)
> +{
> + igt_crc_t ref_crc, test_crc;
> + cairo_t *cr;
> + igt_fb_t *rgb_fb = &data->rgb_fb;
> + igt_fb_t *rgb_fb_o = &data->rgb_fb_o;
> + igt_fb_t *yuv_fb = &data->yuv_fb;
> + igt_fb_t *quarter_fb = &data->quarter_fb;
> + igt_fb_t *cfb = &data->cfb;
> + igt_fb_t *scale_fb = &data->scale_fb;
> + int cw = cfb->width;
> + int ch = cfb->height;
> + int available_overlay_planes = data->available_overlay_planes;
> + int opp_x, opp_y, ret;
> +
> + cr = igt_get_cairo_ctx(rgb_fb->fd, rgb_fb);
> +
> + igt_plane_set_fb(data->primary, rgb_fb);
> + igt_display_commit2(&data->display, COMMIT_ATOMIC);
> +
> + igt_paint_color(cr, 0, 0, rgb_fb->width, rgb_fb->height, 0.0, 0.0, 0.0);
> +
> + /* Draw a magenta square where the cursor should be. */
> + igt_paint_color(cr, x, y, cw, ch, 1.0, 0.0, 1.0);
> + igt_put_cairo_ctx(cr);
> +
> + /* Display the cursor. */
> + igt_plane_set_fb(data->cursor, cfb);
> + igt_plane_set_position(data->cursor, x, y);
> + igt_display_commit_atomic(&data->display, 0, NULL);
> +
> + /* Place the overlay plane on the opposite quarter of the screen from the cursor. */
> + if (flags & TEST_MAX_PLANES ||
> + flags & TEST_NO_AVAILABLE_PLANES ||
> + flags & TEST_QUARTER_FB) {
> + opp_x = x < (data->mode->hdisplay / 2) ? (data->mode->hdisplay / 2) : 0;
> + opp_y = y < (data->mode->vdisplay / 2) ? (data->mode->vdisplay / 2) : 0;
> + }
> +
> + if (flags & TEST_NO_AVAILABLE_PLANES) {
> +
> + /* Display the overlay planes. */
> + set_overlay_planes(data, available_overlay_planes, rgb_fb_o, opp_x, opp_y);
> +
> + /*
> + * Trigger cursor fall back due to a YUV plane;
> + * expect the atomic commit to fail due to no
> + * available overlay planes.
> + */
> + igt_plane_set_fb(data->primary, &data->yuv_fb);
> + ret = igt_display_try_commit_atomic(&data->display,
> + DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
> +
> + /* Expected atomic commit to fail due to no available overlay planes. */
> + igt_assert_f(ret == -EINVAL,
> + "Expected commit fail due to no available overlay planes.\n");
> +
> + /* Exit early. */
> + return;
> + }
> +
> + /* Display the overlay planes as a reference for TEST_MAX_PLANES. */
> + if (flags & TEST_MAX_PLANES) {
> + /* Display the overlay planes. */
> + set_overlay_planes(data, available_overlay_planes - 1, rgb_fb_o, opp_x, opp_y);
> + }
> +
> + /** Record a reference CRC. */
> + igt_pipe_crc_start(data->pipe_crc);
> + igt_pipe_crc_get_current(data->drm_fd, data->pipe_crc, &ref_crc);
> +
> + /* Switch primary plane to YUV FB for TEST_YUV and TEST_MAX_PLANES. */
> + if (flags & TEST_YUV || flags & TEST_MAX_PLANES) {
> + igt_plane_set_fb(data->primary, yuv_fb);
> + igt_plane_set_position(data->primary, 0, 0);
> + igt_plane_set_size(data->primary, yuv_fb->width, yuv_fb->height);
> + igt_display_commit_atomic(&data->display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
> +
> + /* Switch primary plane to use a quarter-sized FB, opposite from cursor. */
> + } else if (flags & TEST_QUARTER_FB) {
> + igt_plane_set_fb(data->primary, quarter_fb);
> + igt_plane_set_position(data->primary, opp_x, opp_y);
> + igt_display_commit_atomic(&data->display, 0, NULL);
> +
> + /* Switch primary plane to use a scaled FB. */
> + } else if (flags & TEST_SCALING) {
> + igt_plane_set_fb(data->primary, scale_fb);
> + igt_plane_set_position(data->primary, 0, 0);
> + igt_plane_set_size(data->primary, data->mode->hdisplay, data->mode->vdisplay);
> + igt_display_commit_atomic(&data->display, 0, NULL);
> + }
> +
> + /*
> + * Wait for one more vblank since cursor updates are not
> + * synchronized to the same frame on AMD hw.
> + */
> + if(is_amdgpu_device(data->drm_fd))
> + igt_wait_for_vblank_count(igt_crtc_for_pipe(&data->display, data->pipe_id), 1);
> +
> + /* Record the new CRC. */
> + igt_pipe_crc_get_current(data->drm_fd, data->pipe_crc, &test_crc);
> + igt_pipe_crc_stop(data->pipe_crc);
> +
> + /* CRC Check is sufficient for this test */
> + igt_assert_crc_equal(&ref_crc, &test_crc);
> +}
> +
> +/*
> + * Tests the cursor on a variety of positions on the screen.
> + * Specific edge cases that should be captured here are the negative edges
> + * of each plane and the centers.
> + */
> +static void test_cursor_spots(data_t *data, int size, unsigned int flags)
> +{
> + int sw = data->mode->hdisplay;
> + int sh = data->mode->vdisplay;
> + int i;
> + const pos_t pos[] = {
> + /* Test diagonally from top left to bottom right. */
> + { -size / 3, -size / 3 },
> + { 0, 0 },
> + { sw / 4 - size, sh / 4 - size },
> + { sw / 4 - size / 3, sh / 4 - size / 3 },
> + { sw / 4, sh / 4 },
> + { sw / 4 + size, sh / 4 + size },
> + { sw / 2, sh / 2 },
> + { sw / 4 + sw / 2 - size, sh / 4 + sh / 2 - size },
> + { sw / 4 + sw / 2 - size / 3, sh / 4 + sh / 2 - size / 3 },
> + { sw / 4 + sw / 2 + size, sh / 4 + sh / 2 + size },
> + { sw - size, sh - size },
> + { sw - size / 3, sh - size / 3 },
> + /* Test remaining corners. */
> + { sw - size, 0 },
> + { 0, sh - size },
> + { sw / 4 + sw / 2 - size, sh / 4 },
> + { sw / 4, sh / 4 + sh / 2 - size }
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(pos); ++i)
> + test_cursor_pos(data, pos[i].x, pos[i].y, flags);
> +}
> +
> +static void test_cursor(data_t *data, int size, unsigned int flags, unsigned int scaling_factor)
> +{
> + int sw, sh;
> +
> + igt_skip_on(size > data->max_curw || size > data->max_curh);
> +
> + sw = data->mode->hdisplay;
> + sh = data->mode->vdisplay;
> +
> + test_cleanup(data);
> +
> + /* Create primary FB. */
> + igt_create_color_fb(data->drm_fd, sw, sh, DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_MOD_LINEAR, 0.0, 0.0, 0.0, &data->rgb_fb);
> +
> + /* Create cursor FB. */
> + igt_create_color_fb(data->drm_fd, size, size, DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_MOD_LINEAR, 1.0, 0.0, 1.0, &data->cfb);
> +
> + /* Create YUV FB for RGB-to-YUV, MAX_PLANES and NO_AVAILABLE_PLANES subtests */
> + if (flags & TEST_YUV ||
> + flags & TEST_MAX_PLANES ||
> + flags & TEST_NO_AVAILABLE_PLANES)
> + igt_create_fb(data->drm_fd, sw, sh, DRM_FORMAT_NV12,
> + DRM_FORMAT_MOD_NONE, &data->yuv_fb);
> +
> + /* Create a quarter-sized FB. */
> + if (flags & TEST_QUARTER_FB)
> + igt_create_color_fb(data->drm_fd, sw / 2, sh / 2, DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_MOD_LINEAR, 0.0, 0.0, 0.0, &data->quarter_fb);
> +
> + /* Create a FB for scaling. */
> + if (flags & TEST_SCALING)
> + igt_create_color_fb(data->drm_fd, (sw * scaling_factor) / 100, (sh * scaling_factor) / 100, DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_MOD_LINEAR, 0.0, 0.0, 0.0, &data->scale_fb);
> +
> + /*
> + * Create RGB FB for overlay planes for MAX_PLANES and
> + * NO_AVAILABLE_PLANES subtests.
> + *
> + * The overlay FB size is quarter the screen size to ensure that
> + * the cursor can be placed on the primary plane to trigger fall back.
> + */
> + if (flags & TEST_MAX_PLANES || flags & TEST_NO_AVAILABLE_PLANES) {
> + /* Create RGB FB for overlay planes. */
> + igt_create_color_fb(data->drm_fd, sw / 2, sh / 2, DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_MOD_LINEAR, 0.0, 1.0, 0.0, &data->rgb_fb_o);
> + }
> +
> + igt_output_set_crtc(data->output,
> + igt_crtc_for_pipe(data->output->display, data->pipe_id));
> +
> + /* Run the test for different cursor spots. */
> + test_cursor_spots(data, size, flags);
> +}
> +
> +int igt_main()
> +{
> + static const int cursor_sizes[] = { 64, 128, 256 };
> + data_t data = { .max_curw = 64, .max_curh = 64 };
> + enum pipe pipe;
> + igt_output_t *output;
> + igt_display_t *display;
> + int i, j, available_overlay_planes;
> + int ret, err, family_id, chip_rev_id;
> + uint32_t major, minor;
> + amdgpu_device_handle device;
> + struct amdgpu_gpu_info gpu_info = {0};
> + struct {
> + const char *name;
> + unsigned int flags;
> + unsigned int scale_factor;
> + const char *desc;
> + } tests[] = {
> + { "rgb-to-yuv", TEST_YUV, 100,
> + "Tests native cursor fall back to overlay cursor when a top plane switches from RGB to YUV" },
> + {"non-full", TEST_QUARTER_FB, 100,
> + "Tests native cursor fall back to overlay cursor when a top plane does not fill the crtc"},
> + {"max-planes", TEST_MAX_PLANES, 100,
> + "Tests native cursor fall back to overlay cursor when a top plane is YUV and there are all but one overlay planes used."},
> + {"no-available-planes", TEST_NO_AVAILABLE_PLANES, 100,
> + "Tests native cursor attempt to fall back to overlay cursor required, but fails atomic commit due to no available overlay planes."},
> + {"scaling-50", TEST_SCALING, 50,
> + "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
> + {"scaling-75", TEST_SCALING, 75,
> + "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
> + {"scaling-125", TEST_SCALING, 125,
> + "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
> + {"scaling-150", TEST_SCALING, 150,
> + "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
> + {"scaling-175", TEST_SCALING, 175,
> + "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
> + {"scaling-200", TEST_SCALING, 200,
> + "Tests native cursor fall back to overlay cursor when a top plane is scaled"},
> + };
> +
> + igt_fixture() {
> +
> + /* Initialize the driver and retrieve GPU info. */
> + data.drm_fd = drm_open_driver_master(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(data.drm_fd, &major, &minor, &device);
> + igt_require(err == 0);
> +
> + err = amdgpu_query_gpu_info(device, &gpu_info);
> + igt_require(err == 0);
> +
> + family_id = gpu_info.family_id;
> + chip_rev_id = gpu_info.chip_external_rev;
> +
> + igt_display_require(&data.display, data.drm_fd);
> + igt_require(data.display.is_atomic);
> + igt_display_require_output(&data.display);
> + display = &data.display;
> +
> + ret = drmGetCap(data.drm_fd, DRM_CAP_CURSOR_WIDTH, &data.max_curw);
> + igt_assert(ret == 0 || errno == EINVAL);
> + ret = drmGetCap(data.drm_fd, DRM_CAP_CURSOR_HEIGHT, &data.max_curh);
> + igt_assert(ret == 0 || errno == EINVAL);
> +
> + kmstest_set_vt_graphics_mode();
> + }
> +
> +
> + for (i = 0; i < ARRAY_SIZE(tests); i++) {
> + igt_describe_f("%s", tests[i].desc);
> + igt_subtest_with_dynamic_f("%s", tests[i].name) {
> +
> + /*
> + * Skip YUV, MAX_PLANES and NO_AVAILABLE_PLANES subtests
> + * if YUV is not supported.
> + */
> + if (tests[i].flags & TEST_YUV ||
> + tests[i].flags & TEST_MAX_PLANES ||
> + tests[i].flags & TEST_NO_AVAILABLE_PLANES)
> + igt_require(igt_display_has_format_mod(display,
> + DRM_FORMAT_NV12,
> + DRM_FORMAT_MOD_LINEAR));
> +
> + for_each_pipe_with_single_output(&data.display, pipe, output) {
> +
> + igt_display_reset(display);
> + igt_output_set_crtc(output,
> + igt_crtc_for_pipe(output->display, pipe));
> +
> + available_overlay_planes = get_overlay_planes_count(display, pipe);
> +
> + /* Require at least one overlay plane. */
> + if (!available_overlay_planes)
> + igt_skip("%s subtest requires at least 1 overlay plane.\n",
> + tests[i].name);
> +
> + /*
> + * For now, NO_AVAILABLE_PLANES substest is only appropriate for
> + * AMD ASICs with 3 overlay planes and with DCN 2.1 & 3.5+ APU's.
> + */
> + if (tests[i].flags & TEST_NO_AVAILABLE_PLANES &&
> + !can_support_all_overlay_planes(available_overlay_planes, family_id, chip_rev_id))
> + igt_skip("%s subtest requires 3 overlay planes with a supported DCN.\n",
> + tests[i].name);
> +
> + test_init(&data, pipe, output, tests[i].flags, available_overlay_planes);
> +
> + for (j = 0; j < ARRAY_SIZE(cursor_sizes); j++) {
> + int size = cursor_sizes[j];
> +
> + igt_dynamic_f("pipe-%s-%s-size-%d",
> + kmstest_pipe_name(pipe),
> + igt_output_name(output),
> + size)
> + test_cursor(&data, size, tests[i].flags, tests[i].scale_factor);
> +
> + test_cleanup(&data);
> + }
> +
> + test_fini(&data);
> +
> + /* Detach output and commit a clean state before moving to the next subtest */
> + igt_output_set_crtc(output, NULL);
> + igt_display_commit2(&data.display, COMMIT_ATOMIC);
> + }
> + }
> + }
> +
> + igt_fixture() {
> +
> + igt_display_reset(&data.display);
> + igt_display_commit2(&data.display, COMMIT_ATOMIC);
> + igt_display_fini(&data.display);
> + drm_close_driver(data.drm_fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index b718699f1..01c8b4fec 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -12,6 +12,7 @@ if libdrm_amdgpu.found()
> 'amd_color',
> 'amd_cp_dma_misc',
> 'amd_cs_nop',
> + 'amd_cursor_overlay',
> 'amd_deadlock',
> 'amd_dp_dsc',
> 'amd_freesync_video_mode',
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-01-12 14:35 UTC | newest]
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2026-01-08 3:07 [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay IVAN.LIPSKI
2026-01-08 4:10 ` ✓ Xe.CI.BAT: success for tests/amdgpu: Add test for native cursor fallback to overlay (rev5) Patchwork
2026-01-08 4:30 ` ✗ i915.CI.BAT: failure " Patchwork
2026-01-08 5:27 ` ✓ Xe.CI.Full: success " Patchwork
2026-01-12 14:35 ` [PATCH i-g-t] tests/amdgpu: Add test for native cursor fallback to overlay Leo Li
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2025-07-17 20:41 IVAN.LIPSKI
2025-07-18 15:37 ` Kamil Konieczny
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