* [igt-dev] [PATCH i-g-t 0/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin
@ 2023-08-04 10:24 Marcin Bernatowicz
2023-08-04 10:24 ` [igt-dev] [PATCH i-g-t 1/2] " Marcin Bernatowicz
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Marcin Bernatowicz @ 2023-08-04 10:24 UTC (permalink / raw)
To: igt-dev; +Cc: mauro.chehab
Introduced struct xe_spin_opts for xe_spin initialization,
adjusted tests to new xe_spin_init signature.
Extended spinner with fixed duration capability. It allows
to prepare fixed duration (ex. 10ms) workloads and take workloads/second
measurements, a handy utility for scheduling tests.
Basic test for xe_spin with fixed duration.
Marcin Bernatowicz (2):
lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin
tests/xe_spin_batch: spin-fixed-duration
lib/xe/xe_spin.c | 121 ++++++++++++++++++++++++++++++------
lib/xe/xe_spin.h | 23 ++++++-
tests/xe/xe_dma_buf_sync.c | 6 +-
tests/xe/xe_exec_balancer.c | 9 ++-
tests/xe/xe_exec_reset.c | 24 ++++---
tests/xe/xe_exec_threads.c | 7 ++-
tests/xe/xe_spin_batch.c | 59 ++++++++++++++++++
tests/xe/xe_vm.c | 9 +--
8 files changed, 213 insertions(+), 45 deletions(-)
--
2.30.2
^ permalink raw reply [flat|nested] 12+ messages in thread* [igt-dev] [PATCH i-g-t 1/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin 2023-08-04 10:24 [igt-dev] [PATCH i-g-t 0/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin Marcin Bernatowicz @ 2023-08-04 10:24 ` Marcin Bernatowicz 2023-08-07 6:54 ` Zbigniew Kempczyński 2023-08-07 14:10 ` Kamil Konieczny 2023-08-04 10:24 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe_spin_batch: spin-fixed-duration Marcin Bernatowicz ` (3 subsequent siblings) 4 siblings, 2 replies; 12+ messages in thread From: Marcin Bernatowicz @ 2023-08-04 10:24 UTC (permalink / raw) To: igt-dev; +Cc: mauro.chehab Introduced struct xe_spin_opts for xe_spin initialization, adjusted tests to new xe_spin_init signature. Extended spinner with fixed duration capability. It allows to prepare fixed duration (ex. 10ms) workloads and take workloads/second measurements, a handy utility for scheduling tests. Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> --- lib/xe/xe_spin.c | 121 ++++++++++++++++++++++++++++++------ lib/xe/xe_spin.h | 23 ++++++- tests/xe/xe_dma_buf_sync.c | 6 +- tests/xe/xe_exec_balancer.c | 9 ++- tests/xe/xe_exec_reset.c | 24 ++++--- tests/xe/xe_exec_threads.c | 7 ++- tests/xe/xe_vm.c | 9 +-- 7 files changed, 154 insertions(+), 45 deletions(-) diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c index cd9c1a7d3..44fca2258 100644 --- a/lib/xe/xe_spin.c +++ b/lib/xe/xe_spin.c @@ -16,41 +16,126 @@ #include "xe_ioctl.h" #include "xe_spin.h" +static int read_timestamp_frequency(int fd, int gt_id) +{ + struct xe_device *dev = xe_device_get(fd); + + igt_assert(dev && dev->gts && dev->gts->num_gt); + igt_assert(gt_id >= 0 && gt_id <= dev->gts->num_gt); + + return dev->gts->gts[gt_id].clock_freq; +} + +static uint64_t div64_u64_round_up(const uint64_t x, const uint64_t y) +{ + return (x + y - 1) / y; +} + +/** + * duration_to_ctx_ticks: + * @fd: opened device + * @gt_id: tile id + * @duration_ns: duration in nanoseconds to be converted to context timestamp ticks + * @return: duration converted to context timestamp ticks, 0 on failure. + */ +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t duration_ns) +{ + int f = read_timestamp_frequency(fd, gt_id); + uint64_t ctx_ticks = div64_u64_round_up(duration_ns * f, NSEC_PER_SEC); + + return ctx_ticks > XE_SPIN_MAX_CTX_TICKS ? 0 : ctx_ticks; +} + +#define MI_SRM_CS_MMIO (1 << 19) +#define MI_LRI_CS_MMIO (1 << 19) +#define MI_LRR_DST_CS_MMIO (1 << 19) +#define MI_LRR_SRC_CS_MMIO (1 << 18) +#define CTX_TIMESTAMP 0x3a8; +#define CS_GPR(x) (0x600 + 8 * (x)) +enum { START_TS, NOW_TS }; + /** * xe_spin_init: * @spin: pointer to mapped bo in which spinner code will be written - * @addr: offset of spinner within vm - * @preempt: allow spinner to be preempted or not + * @opts: pointer to spinner initialization options */ -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt) +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts) { - uint64_t batch_offset = (char *)&spin->batch - (char *)spin; - uint64_t batch_addr = addr + batch_offset; - uint64_t start_offset = (char *)&spin->start - (char *)spin; - uint64_t start_addr = addr + start_offset; - uint64_t end_offset = (char *)&spin->end - (char *)spin; - uint64_t end_addr = addr + end_offset; + uint64_t loop_addr; + uint64_t start_addr = opts->addr + offsetof(struct xe_spin, start); + uint64_t end_addr = opts->addr + offsetof(struct xe_spin, end); + uint64_t ticks_delta_addr = opts->addr + offsetof(struct xe_spin, ticks_delta); + uint64_t pad_addr = opts->addr + offsetof(struct xe_spin, pad); int b = 0; spin->start = 0; spin->end = 0xffffffff; + spin->ticks_delta = 0; + + if (opts->ctx_ticks) { + /* store start timestamp */ + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; + spin->batch[b++] = CS_GPR(START_TS) + 4; + spin->batch[b++] = 0; + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; + spin->batch[b++] = CTX_TIMESTAMP; + spin->batch[b++] = CS_GPR(START_TS); + } + + loop_addr = opts->addr + (char *)&spin->batch[b] - (char *)spin; spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; spin->batch[b++] = start_addr; spin->batch[b++] = start_addr >> 32; spin->batch[b++] = 0xc0ffee; - if (preempt) + if (opts->preempt) spin->batch[b++] = (0x5 << 23); + if (opts->ctx_ticks) { + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; + spin->batch[b++] = CS_GPR(NOW_TS) + 4; + spin->batch[b++] = 0; + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; + spin->batch[b++] = CTX_TIMESTAMP; + spin->batch[b++] = CS_GPR(NOW_TS); + + /* delta = now - start; inverted to match COND_BBE */ + spin->batch[b++] = MI_MATH(4); + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + spin->batch[b++] = MI_MATH_SUB; + spin->batch[b++] = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + /* Save delta for reading by COND_BBE */ + spin->batch[b++] = MI_STORE_REGISTER_MEM | MI_SRM_CS_MMIO | 2; + spin->batch[b++] = CS_GPR(NOW_TS); + spin->batch[b++] = ticks_delta_addr; + spin->batch[b++] = ticks_delta_addr >> 32; + + /* Delay between SRM and COND_BBE to post the writes */ + for (int n = 0; n < 8; n++) { + spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; + spin->batch[b++] = pad_addr; + spin->batch[b++] = pad_addr >> 32; + spin->batch[b++] = 0xc0ffee; + } + + /* Break if delta [time elapsed] > ns */ + spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; + spin->batch[b++] = ~(opts->ctx_ticks); + spin->batch[b++] = ticks_delta_addr; + spin->batch[b++] = ticks_delta_addr >> 32; + } + spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; spin->batch[b++] = 0; spin->batch[b++] = end_addr; spin->batch[b++] = end_addr >> 32; spin->batch[b++] = MI_BATCH_BUFFER_START | 1 << 8 | 1; - spin->batch[b++] = batch_addr; - spin->batch[b++] = batch_addr >> 32; + spin->batch[b++] = loop_addr; + spin->batch[b++] = loop_addr >> 32; igt_assert(b <= ARRAY_SIZE(spin->batch)); } @@ -106,6 +191,7 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt) .num_syncs = 1, .syncs = to_user_pointer(&sync), }; + struct xe_spin_opts spin_opts = {}; igt_assert(ahnd); spin = calloc(1, sizeof(struct igt_spin)); @@ -132,11 +218,9 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt) addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size); - if (!(opt->flags & IGT_SPIN_NO_PREEMPTION)) - xe_spin_init(xe_spin, addr, true); - else - xe_spin_init(xe_spin, addr, false); - + spin_opts.addr = addr; + spin_opts.preempt = !(opt->flags & IGT_SPIN_NO_PREEMPTION); + xe_spin_init(xe_spin, &spin_opts); exec.exec_queue_id = spin->engine; exec.address = addr; sync.handle = spin->syncobj; @@ -191,6 +275,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe, size_t bo_size = xe_get_default_alignment(fd); uint32_t vm, bo, exec_queue, syncobj; struct xe_spin *spin; + struct xe_spin_opts spin_opts = { .addr = addr, .preempt = true }; struct drm_xe_sync sync = { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }; @@ -211,7 +296,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe, exec_queue = xe_exec_queue_create(fd, vm, hwe, 0); syncobj = syncobj_create(fd, 0); - xe_spin_init(spin, addr, true); + xe_spin_init(spin, &spin_opts); exec.exec_queue_id = exec_queue; exec.address = addr; sync.handle = syncobj; diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h index c84db175d..14053a07e 100644 --- a/lib/xe/xe_spin.h +++ b/lib/xe/xe_spin.h @@ -15,15 +15,34 @@ #include "xe_query.h" #include "lib/igt_dummyload.h" +#define XE_SPIN_MAX_CTX_TICKS UINT32_MAX - 1000 + +/** struct xe_spin_opts + * + * @addr: offset of spinner within vm + * @preempt: allow spinner to be preempted or not + * @ctx_ticks: number of ticks after which spinner is stopped, applied if > 0 + * + * Used to initialize struct xe_spin spinner behavior. + */ +struct xe_spin_opts { + uint64_t addr; + bool preempt; + uint32_t ctx_ticks; +}; + /* Mapped GPU object */ struct xe_spin { - uint32_t batch[16]; + uint32_t batch[128]; uint64_t pad; uint32_t start; uint32_t end; + uint32_t ticks_delta; }; + igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt); -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt); +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns); +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts); bool xe_spin_started(struct xe_spin *spin); void xe_spin_sync_wait(int fd, struct igt_spin *spin); void xe_spin_wait_started(struct xe_spin *spin); diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c index 29d675154..627f4c1e5 100644 --- a/tests/xe/xe_dma_buf_sync.c +++ b/tests/xe/xe_dma_buf_sync.c @@ -144,7 +144,6 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, uint64_t sdi_offset = (char *)&data[i]->data - (char *)data[i]; uint64_t sdi_addr = addr + sdi_offset; uint64_t spin_offset = (char *)&data[i]->spin - (char *)data[i]; - uint64_t spin_addr = addr + spin_offset; struct drm_xe_sync sync[2] = { { .flags = DRM_XE_SYNC_SYNCOBJ, }, { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }, @@ -153,14 +152,15 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, .num_batch_buffer = 1, .syncs = to_user_pointer(sync), }; + struct xe_spin_opts spin_opts = { .addr = addr + spin_offset, .preempt = true }; uint32_t syncobj; int b = 0; int sync_fd; /* Write spinner on FD[0] */ - xe_spin_init(&data[i]->spin, spin_addr, true); + xe_spin_init(&data[i]->spin, &spin_opts); exec.exec_queue_id = exec_queue[0]; - exec.address = spin_addr; + exec.address = spin_opts.addr; xe_exec(fd[0], &exec); /* Export prime BO as sync file and veify business */ diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c index f364a4b7a..d7d8dd8fb 100644 --- a/tests/xe/xe_exec_balancer.c +++ b/tests/xe/xe_exec_balancer.c @@ -52,6 +52,7 @@ static void test_all_active(int fd, int gt, int class) struct { struct xe_spin spin; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; struct drm_xe_engine_class_instance *hwe; struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; int i, num_placements = 0; @@ -90,16 +91,14 @@ static void test_all_active(int fd, int gt, int class) xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); for (i = 0; i < num_placements; i++) { - uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = addr + spin_offset; - - xe_spin_init(&data[i].spin, spin_addr, false); + spin_opts.addr = addr + (char *)&data[i].spin - (char *)data; + xe_spin_init(&data[i].spin, &spin_opts); sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; sync[1].flags |= DRM_XE_SYNC_SIGNAL; sync[1].handle = syncobjs[i]; exec.exec_queue_id = exec_queues[i]; - exec.address = spin_addr; + exec.address = spin_opts.addr; xe_exec(fd, &exec); xe_spin_wait_started(&data[i].spin); } diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c index a2d33baf1..be6bbada6 100644 --- a/tests/xe/xe_exec_reset.c +++ b/tests/xe/xe_exec_reset.c @@ -44,6 +44,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) size_t bo_size; uint32_t bo = 0; struct xe_spin *spin; + struct xe_spin_opts spin_opts = { .addr = addr, .preempt = false }; vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); bo_size = sizeof(*spin); @@ -60,7 +61,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) sync[0].handle = syncobj_create(fd, 0); xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); - xe_spin_init(spin, addr, false); + xe_spin_init(spin, &spin_opts); sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; sync[1].flags |= DRM_XE_SYNC_SIGNAL; @@ -165,6 +166,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; struct drm_xe_engine_class_instance *hwe; struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; int i, j, b, num_placements = 0, bad_batches = 1; @@ -236,7 +238,6 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = base_addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = base_addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = base_addr + sdi_offset; uint64_t exec_addr; @@ -247,8 +248,9 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, batches[j] = batch_addr; if (i < bad_batches) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = base_addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; @@ -368,6 +370,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; int i, b; igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); @@ -417,15 +420,15 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = base_addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = base_addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = base_addr + sdi_offset; uint64_t exec_addr; int e = i % n_exec_queues; if (!i) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = base_addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; @@ -539,6 +542,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t exec_sync; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; int i, b; igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); @@ -593,15 +597,15 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = base_addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = base_addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = base_addr + sdi_offset; uint64_t exec_addr; int e = i % n_exec_queues; if (!i) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = base_addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c index e64c1639a..ff4ebc280 100644 --- a/tests/xe/xe_exec_threads.c +++ b/tests/xe/xe_exec_threads.c @@ -486,6 +486,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = false }; int i, j, b, hang_exec_queue = n_exec_queues / 2; bool owns_vm = false, owns_fd = false; @@ -562,15 +563,15 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, uint64_t batch_offset = (char *)&data[i].batch - (char *)data; uint64_t batch_addr = addr + batch_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = addr + spin_offset; uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = addr + sdi_offset; uint64_t exec_addr; int e = i % n_exec_queues; if (flags & HANG && e == hang_exec_queue && i == e) { - xe_spin_init(&data[i].spin, spin_addr, false); - exec_addr = spin_addr; + spin_opts.addr = addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); + exec_addr = spin_opts.addr; } else { b = 0; data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c index e42c04e33..87604a407 100644 --- a/tests/xe/xe_vm.c +++ b/tests/xe/xe_vm.c @@ -727,6 +727,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec uint64_t pad; uint32_t data; } *data; + struct xe_spin_opts spin_opts = { .preempt = true }; int i, b; vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); @@ -755,14 +756,14 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec uint64_t sdi_offset = (char *)&data[i].data - (char *)data; uint64_t sdi_addr = addr + sdi_offset; uint64_t spin_offset = (char *)&data[i].spin - (char *)data; - uint64_t spin_addr = addr + spin_offset; int e = i; if (i == 0) { - /* Cork 1st exec_queue with a spinner */ - xe_spin_init(&data[i].spin, spin_addr, true); + /* Cork 1st engine with a spinner */ + spin_opts.addr = addr + spin_offset; + xe_spin_init(&data[i].spin, &spin_opts); exec.exec_queue_id = exec_queues[e]; - exec.address = spin_addr; + exec.address = spin_opts.addr; sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; sync[1].flags |= DRM_XE_SYNC_SIGNAL; sync[1].handle = syncobjs[e]; -- 2.30.2 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin 2023-08-04 10:24 ` [igt-dev] [PATCH i-g-t 1/2] " Marcin Bernatowicz @ 2023-08-07 6:54 ` Zbigniew Kempczyński 2023-08-07 13:38 ` Bernatowicz, Marcin 2023-08-07 14:10 ` Kamil Konieczny 1 sibling, 1 reply; 12+ messages in thread From: Zbigniew Kempczyński @ 2023-08-07 6:54 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev, mauro.chehab On Fri, Aug 04, 2023 at 10:24:53AM +0000, Marcin Bernatowicz wrote: > Introduced struct xe_spin_opts for xe_spin initialization, > adjusted tests to new xe_spin_init signature. > > Extended spinner with fixed duration capability. It allows > to prepare fixed duration (ex. 10ms) workloads and take workloads/second > measurements, a handy utility for scheduling tests. > > Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> > --- > lib/xe/xe_spin.c | 121 ++++++++++++++++++++++++++++++------ > lib/xe/xe_spin.h | 23 ++++++- > tests/xe/xe_dma_buf_sync.c | 6 +- > tests/xe/xe_exec_balancer.c | 9 ++- > tests/xe/xe_exec_reset.c | 24 ++++--- > tests/xe/xe_exec_threads.c | 7 ++- > tests/xe/xe_vm.c | 9 +-- > 7 files changed, 154 insertions(+), 45 deletions(-) > > diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c > index cd9c1a7d3..44fca2258 100644 > --- a/lib/xe/xe_spin.c > +++ b/lib/xe/xe_spin.c > @@ -16,41 +16,126 @@ > #include "xe_ioctl.h" > #include "xe_spin.h" > > +static int read_timestamp_frequency(int fd, int gt_id) I would use uint32_t as clock_freq is u32. > +{ > + struct xe_device *dev = xe_device_get(fd); > + > + igt_assert(dev && dev->gts && dev->gts->num_gt); > + igt_assert(gt_id >= 0 && gt_id <= dev->gts->num_gt); > + > + return dev->gts->gts[gt_id].clock_freq; > +} > + > +static uint64_t div64_u64_round_up(const uint64_t x, const uint64_t y) > +{ Assert on divisor == 0 to avoid sigfpe surprise? > + return (x + y - 1) / y; > +} > + > +/** > + * duration_to_ctx_ticks: > + * @fd: opened device > + * @gt_id: tile id > + * @duration_ns: duration in nanoseconds to be converted to context timestamp ticks > + * @return: duration converted to context timestamp ticks, 0 on failure. > + */ > +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t duration_ns) > +{ > + int f = read_timestamp_frequency(fd, gt_id); > + uint64_t ctx_ticks = div64_u64_round_up(duration_ns * f, NSEC_PER_SEC); > + Same as above, f as uint32_t. > + return ctx_ticks > XE_SPIN_MAX_CTX_TICKS ? 0 : ctx_ticks; > +} Hmm. For 19MHz clock spinner time must be less than 223 seconds. For IGT test it is huge value. I would just assert if ctx_ticks is >= XE_SPIN_MAX_CTX_TICKS. > + > +#define MI_SRM_CS_MMIO (1 << 19) > +#define MI_LRI_CS_MMIO (1 << 19) > +#define MI_LRR_DST_CS_MMIO (1 << 19) > +#define MI_LRR_SRC_CS_MMIO (1 << 18) > +#define CTX_TIMESTAMP 0x3a8; > +#define CS_GPR(x) (0x600 + 8 * (x)) > +enum { START_TS, NOW_TS }; > + > /** > * xe_spin_init: > * @spin: pointer to mapped bo in which spinner code will be written > - * @addr: offset of spinner within vm > - * @preempt: allow spinner to be preempted or not > + * @opts: pointer to spinner initialization options > */ > -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt) > +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts) > { > - uint64_t batch_offset = (char *)&spin->batch - (char *)spin; > - uint64_t batch_addr = addr + batch_offset; > - uint64_t start_offset = (char *)&spin->start - (char *)spin; > - uint64_t start_addr = addr + start_offset; > - uint64_t end_offset = (char *)&spin->end - (char *)spin; > - uint64_t end_addr = addr + end_offset; > + uint64_t loop_addr; > + uint64_t start_addr = opts->addr + offsetof(struct xe_spin, start); > + uint64_t end_addr = opts->addr + offsetof(struct xe_spin, end); > + uint64_t ticks_delta_addr = opts->addr + offsetof(struct xe_spin, ticks_delta); > + uint64_t pad_addr = opts->addr + offsetof(struct xe_spin, pad); Nice, offsetof() makes this code clearer. > int b = 0; > > spin->start = 0; > spin->end = 0xffffffff; > + spin->ticks_delta = 0; > + > + if (opts->ctx_ticks) { > + /* store start timestamp */ > + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; > + spin->batch[b++] = CS_GPR(START_TS) + 4; > + spin->batch[b++] = 0; > + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; > + spin->batch[b++] = CTX_TIMESTAMP; > + spin->batch[b++] = CS_GPR(START_TS); > + } > + > + loop_addr = opts->addr + (char *)&spin->batch[b] - (char *)spin; loop_addr = opts->addr + b * sizeof(uint32_t); looks more readable imo. > > spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; > spin->batch[b++] = start_addr; > spin->batch[b++] = start_addr >> 32; > spin->batch[b++] = 0xc0ffee; > > - if (preempt) > + if (opts->preempt) > spin->batch[b++] = (0x5 << 23); > > + if (opts->ctx_ticks) { > + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; > + spin->batch[b++] = CS_GPR(NOW_TS) + 4; > + spin->batch[b++] = 0; > + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; > + spin->batch[b++] = CTX_TIMESTAMP; > + spin->batch[b++] = CS_GPR(NOW_TS); > + > + /* delta = now - start; inverted to match COND_BBE */ > + spin->batch[b++] = MI_MATH(4); > + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); > + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); > + spin->batch[b++] = MI_MATH_SUB; > + spin->batch[b++] = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); > + > + /* Save delta for reading by COND_BBE */ > + spin->batch[b++] = MI_STORE_REGISTER_MEM | MI_SRM_CS_MMIO | 2; > + spin->batch[b++] = CS_GPR(NOW_TS); > + spin->batch[b++] = ticks_delta_addr; > + spin->batch[b++] = ticks_delta_addr >> 32; > + > + /* Delay between SRM and COND_BBE to post the writes */ > + for (int n = 0; n < 8; n++) { > + spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; > + spin->batch[b++] = pad_addr; > + spin->batch[b++] = pad_addr >> 32; > + spin->batch[b++] = 0xc0ffee; > + } > + > + /* Break if delta [time elapsed] > ns */ > + spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; > + spin->batch[b++] = ~(opts->ctx_ticks); > + spin->batch[b++] = ticks_delta_addr; > + spin->batch[b++] = ticks_delta_addr >> 32; > + } Ok, this part looks good for me. > + > spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; > spin->batch[b++] = 0; > spin->batch[b++] = end_addr; > spin->batch[b++] = end_addr >> 32; > > spin->batch[b++] = MI_BATCH_BUFFER_START | 1 << 8 | 1; > - spin->batch[b++] = batch_addr; > - spin->batch[b++] = batch_addr >> 32; > + spin->batch[b++] = loop_addr; > + spin->batch[b++] = loop_addr >> 32; > > igt_assert(b <= ARRAY_SIZE(spin->batch)); > } > @@ -106,6 +191,7 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt) > .num_syncs = 1, > .syncs = to_user_pointer(&sync), > }; > + struct xe_spin_opts spin_opts = {}; > > igt_assert(ahnd); > spin = calloc(1, sizeof(struct igt_spin)); > @@ -132,11 +218,9 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt) > addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); > xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size); > > - if (!(opt->flags & IGT_SPIN_NO_PREEMPTION)) > - xe_spin_init(xe_spin, addr, true); > - else > - xe_spin_init(xe_spin, addr, false); > - > + spin_opts.addr = addr; > + spin_opts.preempt = !(opt->flags & IGT_SPIN_NO_PREEMPTION); > + xe_spin_init(xe_spin, &spin_opts); Or just: xe_spin_init(xe_spin, .addr = addr, .preempt = !(opt->flags & IGT_SPIN_NO_PREEMPTION)); ? See comment below. > exec.exec_queue_id = spin->engine; > exec.address = addr; > sync.handle = spin->syncobj; > @@ -191,6 +275,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe, > size_t bo_size = xe_get_default_alignment(fd); > uint32_t vm, bo, exec_queue, syncobj; > struct xe_spin *spin; > + struct xe_spin_opts spin_opts = { .addr = addr, .preempt = true }; > struct drm_xe_sync sync = { > .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, > }; > @@ -211,7 +296,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe, > exec_queue = xe_exec_queue_create(fd, vm, hwe, 0); > syncobj = syncobj_create(fd, 0); > > - xe_spin_init(spin, addr, true); > + xe_spin_init(spin, &spin_opts); > exec.exec_queue_id = exec_queue; > exec.address = addr; > sync.handle = syncobj; > diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h > index c84db175d..14053a07e 100644 > --- a/lib/xe/xe_spin.h > +++ b/lib/xe/xe_spin.h > @@ -15,15 +15,34 @@ > #include "xe_query.h" > #include "lib/igt_dummyload.h" > > +#define XE_SPIN_MAX_CTX_TICKS UINT32_MAX - 1000 > + > +/** struct xe_spin_opts > + * > + * @addr: offset of spinner within vm > + * @preempt: allow spinner to be preempted or not > + * @ctx_ticks: number of ticks after which spinner is stopped, applied if > 0 > + * > + * Used to initialize struct xe_spin spinner behavior. > + */ > +struct xe_spin_opts { > + uint64_t addr; > + bool preempt; > + uint32_t ctx_ticks; > +}; > + > /* Mapped GPU object */ > struct xe_spin { > - uint32_t batch[16]; > + uint32_t batch[128]; > uint64_t pad; > uint32_t start; > uint32_t end; > + uint32_t ticks_delta; > }; > + > igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt); > -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt); > +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns); > +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts); I would add: #define xe_spin_init_opts(fd, ...) \ xe_spin_init(fd, &((xe_spin_opts){__VA_ARGS__})) to call xe_spin_init() indirectly with .k = v initialization. > bool xe_spin_started(struct xe_spin *spin); > void xe_spin_sync_wait(int fd, struct igt_spin *spin); > void xe_spin_wait_started(struct xe_spin *spin); > diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c > index 29d675154..627f4c1e5 100644 > --- a/tests/xe/xe_dma_buf_sync.c > +++ b/tests/xe/xe_dma_buf_sync.c > @@ -144,7 +144,6 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, > uint64_t sdi_offset = (char *)&data[i]->data - (char *)data[i]; > uint64_t sdi_addr = addr + sdi_offset; > uint64_t spin_offset = (char *)&data[i]->spin - (char *)data[i]; > - uint64_t spin_addr = addr + spin_offset; > struct drm_xe_sync sync[2] = { > { .flags = DRM_XE_SYNC_SYNCOBJ, }, > { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }, > @@ -153,14 +152,15 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, > .num_batch_buffer = 1, > .syncs = to_user_pointer(sync), > }; > + struct xe_spin_opts spin_opts = { .addr = addr + spin_offset, .preempt = true }; > uint32_t syncobj; > int b = 0; > int sync_fd; > > /* Write spinner on FD[0] */ > - xe_spin_init(&data[i]->spin, spin_addr, true); > + xe_spin_init(&data[i]->spin, &spin_opts); > exec.exec_queue_id = exec_queue[0]; > - exec.address = spin_addr; > + exec.address = spin_opts.addr; > xe_exec(fd[0], &exec); > > /* Export prime BO as sync file and veify business */ > diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c > index f364a4b7a..d7d8dd8fb 100644 > --- a/tests/xe/xe_exec_balancer.c > +++ b/tests/xe/xe_exec_balancer.c > @@ -52,6 +52,7 @@ static void test_all_active(int fd, int gt, int class) > struct { > struct xe_spin spin; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = false }; > struct drm_xe_engine_class_instance *hwe; > struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; > int i, num_placements = 0; > @@ -90,16 +91,14 @@ static void test_all_active(int fd, int gt, int class) > xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); > > for (i = 0; i < num_placements; i++) { > - uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = addr + spin_offset; > - > - xe_spin_init(&data[i].spin, spin_addr, false); > + spin_opts.addr = addr + (char *)&data[i].spin - (char *)data; > + xe_spin_init(&data[i].spin, &spin_opts); > sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; > sync[1].flags |= DRM_XE_SYNC_SIGNAL; > sync[1].handle = syncobjs[i]; > > exec.exec_queue_id = exec_queues[i]; > - exec.address = spin_addr; > + exec.address = spin_opts.addr; > xe_exec(fd, &exec); > xe_spin_wait_started(&data[i].spin); > } > diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c > index a2d33baf1..be6bbada6 100644 > --- a/tests/xe/xe_exec_reset.c > +++ b/tests/xe/xe_exec_reset.c > @@ -44,6 +44,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) > size_t bo_size; > uint32_t bo = 0; > struct xe_spin *spin; > + struct xe_spin_opts spin_opts = { .addr = addr, .preempt = false }; > > vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); > bo_size = sizeof(*spin); > @@ -60,7 +61,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) > sync[0].handle = syncobj_create(fd, 0); > xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); > > - xe_spin_init(spin, addr, false); > + xe_spin_init(spin, &spin_opts); > > sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; > sync[1].flags |= DRM_XE_SYNC_SIGNAL; > @@ -165,6 +166,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, > uint64_t pad; > uint32_t data; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = false }; > struct drm_xe_engine_class_instance *hwe; > struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; > int i, j, b, num_placements = 0, bad_batches = 1; > @@ -236,7 +238,6 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, > uint64_t batch_offset = (char *)&data[i].batch - (char *)data; > uint64_t batch_addr = base_addr + batch_offset; > uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = base_addr + spin_offset; > uint64_t sdi_offset = (char *)&data[i].data - (char *)data; > uint64_t sdi_addr = base_addr + sdi_offset; > uint64_t exec_addr; > @@ -247,8 +248,9 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, > batches[j] = batch_addr; > > if (i < bad_batches) { > - xe_spin_init(&data[i].spin, spin_addr, false); > - exec_addr = spin_addr; > + spin_opts.addr = base_addr + spin_offset; > + xe_spin_init(&data[i].spin, &spin_opts); > + exec_addr = spin_opts.addr; > } else { > b = 0; > data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; > @@ -368,6 +370,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, > uint64_t pad; > uint32_t data; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = false }; > int i, b; > > igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > @@ -417,15 +420,15 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, > uint64_t batch_offset = (char *)&data[i].batch - (char *)data; > uint64_t batch_addr = base_addr + batch_offset; > uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = base_addr + spin_offset; > uint64_t sdi_offset = (char *)&data[i].data - (char *)data; > uint64_t sdi_addr = base_addr + sdi_offset; > uint64_t exec_addr; > int e = i % n_exec_queues; > > if (!i) { > - xe_spin_init(&data[i].spin, spin_addr, false); > - exec_addr = spin_addr; > + spin_opts.addr = base_addr + spin_offset; > + xe_spin_init(&data[i].spin, &spin_opts); > + exec_addr = spin_opts.addr; > } else { > b = 0; > data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; > @@ -539,6 +542,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > uint64_t exec_sync; > uint32_t data; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = false }; > int i, b; > > igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > @@ -593,15 +597,15 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > uint64_t batch_offset = (char *)&data[i].batch - (char *)data; > uint64_t batch_addr = base_addr + batch_offset; > uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = base_addr + spin_offset; > uint64_t sdi_offset = (char *)&data[i].data - (char *)data; > uint64_t sdi_addr = base_addr + sdi_offset; > uint64_t exec_addr; > int e = i % n_exec_queues; > > if (!i) { > - xe_spin_init(&data[i].spin, spin_addr, false); > - exec_addr = spin_addr; > + spin_opts.addr = base_addr + spin_offset; > + xe_spin_init(&data[i].spin, &spin_opts); > + exec_addr = spin_opts.addr; > } else { > b = 0; > data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; > diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c > index e64c1639a..ff4ebc280 100644 > --- a/tests/xe/xe_exec_threads.c > +++ b/tests/xe/xe_exec_threads.c > @@ -486,6 +486,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > uint64_t pad; > uint32_t data; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = false }; > int i, j, b, hang_exec_queue = n_exec_queues / 2; > bool owns_vm = false, owns_fd = false; > > @@ -562,15 +563,15 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > uint64_t batch_offset = (char *)&data[i].batch - (char *)data; > uint64_t batch_addr = addr + batch_offset; > uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = addr + spin_offset; > uint64_t sdi_offset = (char *)&data[i].data - (char *)data; > uint64_t sdi_addr = addr + sdi_offset; > uint64_t exec_addr; > int e = i % n_exec_queues; > > if (flags & HANG && e == hang_exec_queue && i == e) { > - xe_spin_init(&data[i].spin, spin_addr, false); > - exec_addr = spin_addr; > + spin_opts.addr = addr + spin_offset; > + xe_spin_init(&data[i].spin, &spin_opts); > + exec_addr = spin_opts.addr; > } else { > b = 0; > data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; > diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c > index e42c04e33..87604a407 100644 > --- a/tests/xe/xe_vm.c > +++ b/tests/xe/xe_vm.c > @@ -727,6 +727,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec > uint64_t pad; > uint32_t data; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = true }; > int i, b; > > vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); > @@ -755,14 +756,14 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec > uint64_t sdi_offset = (char *)&data[i].data - (char *)data; > uint64_t sdi_addr = addr + sdi_offset; > uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = addr + spin_offset; > int e = i; > > if (i == 0) { > - /* Cork 1st exec_queue with a spinner */ > - xe_spin_init(&data[i].spin, spin_addr, true); > + /* Cork 1st engine with a spinner */ > + spin_opts.addr = addr + spin_offset; > + xe_spin_init(&data[i].spin, &spin_opts); > exec.exec_queue_id = exec_queues[e]; > - exec.address = spin_addr; > + exec.address = spin_opts.addr; > sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; > sync[1].flags |= DRM_XE_SYNC_SIGNAL; > sync[1].handle = syncobjs[e]; > -- > 2.30.2 > Generally looks good to me, address my nits and: Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> -- Zbigniew ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin 2023-08-07 6:54 ` Zbigniew Kempczyński @ 2023-08-07 13:38 ` Bernatowicz, Marcin 0 siblings, 0 replies; 12+ messages in thread From: Bernatowicz, Marcin @ 2023-08-07 13:38 UTC (permalink / raw) To: Zbigniew Kempczyński; +Cc: igt-dev, mauro.chehab On 8/7/2023 8:54 AM, Zbigniew Kempczyński wrote: > On Fri, Aug 04, 2023 at 10:24:53AM +0000, Marcin Bernatowicz wrote: >> Introduced struct xe_spin_opts for xe_spin initialization, >> adjusted tests to new xe_spin_init signature. >> >> Extended spinner with fixed duration capability. It allows >> to prepare fixed duration (ex. 10ms) workloads and take workloads/second >> measurements, a handy utility for scheduling tests. >> >> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> >> --- >> lib/xe/xe_spin.c | 121 ++++++++++++++++++++++++++++++------ >> lib/xe/xe_spin.h | 23 ++++++- >> tests/xe/xe_dma_buf_sync.c | 6 +- >> tests/xe/xe_exec_balancer.c | 9 ++- >> tests/xe/xe_exec_reset.c | 24 ++++--- >> tests/xe/xe_exec_threads.c | 7 ++- >> tests/xe/xe_vm.c | 9 +-- >> 7 files changed, 154 insertions(+), 45 deletions(-) >> >> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c >> index cd9c1a7d3..44fca2258 100644 >> --- a/lib/xe/xe_spin.c >> +++ b/lib/xe/xe_spin.c >> @@ -16,41 +16,126 @@ >> #include "xe_ioctl.h" >> #include "xe_spin.h" >> >> +static int read_timestamp_frequency(int fd, int gt_id) > > I would use uint32_t as clock_freq is u32. ok > >> +{ >> + struct xe_device *dev = xe_device_get(fd); >> + >> + igt_assert(dev && dev->gts && dev->gts->num_gt); >> + igt_assert(gt_id >= 0 && gt_id <= dev->gts->num_gt); >> + >> + return dev->gts->gts[gt_id].clock_freq; >> +} >> + >> +static uint64_t div64_u64_round_up(const uint64_t x, const uint64_t y) >> +{ > > Assert on divisor == 0 to avoid sigfpe surprise? ok > >> + return (x + y - 1) / y; >> +} >> + >> +/** >> + * duration_to_ctx_ticks: >> + * @fd: opened device >> + * @gt_id: tile id >> + * @duration_ns: duration in nanoseconds to be converted to context timestamp ticks >> + * @return: duration converted to context timestamp ticks, 0 on failure. >> + */ >> +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t duration_ns) >> +{ >> + int f = read_timestamp_frequency(fd, gt_id); >> + uint64_t ctx_ticks = div64_u64_round_up(duration_ns * f, NSEC_PER_SEC); >> + > > Same as above, f as uint32_t. > >> + return ctx_ticks > XE_SPIN_MAX_CTX_TICKS ? 0 : ctx_ticks; >> +} > > Hmm. For 19MHz clock spinner time must be less than 223 seconds. > For IGT test it is huge value. > I would just assert if ctx_ticks is >= XE_SPIN_MAX_CTX_TICKS. will add igt_assert_lt_u64(ctx_ticks, XE_SPIN_MAX_CTX_TICKS); > >> + >> +#define MI_SRM_CS_MMIO (1 << 19) >> +#define MI_LRI_CS_MMIO (1 << 19) >> +#define MI_LRR_DST_CS_MMIO (1 << 19) >> +#define MI_LRR_SRC_CS_MMIO (1 << 18) >> +#define CTX_TIMESTAMP 0x3a8; >> +#define CS_GPR(x) (0x600 + 8 * (x)) >> +enum { START_TS, NOW_TS }; >> + >> /** >> * xe_spin_init: >> * @spin: pointer to mapped bo in which spinner code will be written >> - * @addr: offset of spinner within vm >> - * @preempt: allow spinner to be preempted or not >> + * @opts: pointer to spinner initialization options >> */ >> -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt) >> +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts) >> { >> - uint64_t batch_offset = (char *)&spin->batch - (char *)spin; >> - uint64_t batch_addr = addr + batch_offset; >> - uint64_t start_offset = (char *)&spin->start - (char *)spin; >> - uint64_t start_addr = addr + start_offset; >> - uint64_t end_offset = (char *)&spin->end - (char *)spin; >> - uint64_t end_addr = addr + end_offset; >> + uint64_t loop_addr; >> + uint64_t start_addr = opts->addr + offsetof(struct xe_spin, start); >> + uint64_t end_addr = opts->addr + offsetof(struct xe_spin, end); >> + uint64_t ticks_delta_addr = opts->addr + offsetof(struct xe_spin, ticks_delta); >> + uint64_t pad_addr = opts->addr + offsetof(struct xe_spin, pad); > > Nice, offsetof() makes this code clearer. > >> int b = 0; >> >> spin->start = 0; >> spin->end = 0xffffffff; >> + spin->ticks_delta = 0; >> + >> + if (opts->ctx_ticks) { >> + /* store start timestamp */ >> + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; >> + spin->batch[b++] = CS_GPR(START_TS) + 4; >> + spin->batch[b++] = 0; >> + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; >> + spin->batch[b++] = CTX_TIMESTAMP; >> + spin->batch[b++] = CS_GPR(START_TS); >> + } >> + >> + loop_addr = opts->addr + (char *)&spin->batch[b] - (char *)spin; > > loop_addr = opts->addr + b * sizeof(uint32_t); > > looks more readable imo. ok > >> >> spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; >> spin->batch[b++] = start_addr; >> spin->batch[b++] = start_addr >> 32; >> spin->batch[b++] = 0xc0ffee; >> >> - if (preempt) >> + if (opts->preempt) >> spin->batch[b++] = (0x5 << 23); >> >> + if (opts->ctx_ticks) { >> + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; >> + spin->batch[b++] = CS_GPR(NOW_TS) + 4; >> + spin->batch[b++] = 0; >> + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; >> + spin->batch[b++] = CTX_TIMESTAMP; >> + spin->batch[b++] = CS_GPR(NOW_TS); >> + >> + /* delta = now - start; inverted to match COND_BBE */ >> + spin->batch[b++] = MI_MATH(4); >> + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); >> + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); >> + spin->batch[b++] = MI_MATH_SUB; >> + spin->batch[b++] = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); >> + >> + /* Save delta for reading by COND_BBE */ >> + spin->batch[b++] = MI_STORE_REGISTER_MEM | MI_SRM_CS_MMIO | 2; >> + spin->batch[b++] = CS_GPR(NOW_TS); >> + spin->batch[b++] = ticks_delta_addr; >> + spin->batch[b++] = ticks_delta_addr >> 32; >> + >> + /* Delay between SRM and COND_BBE to post the writes */ >> + for (int n = 0; n < 8; n++) { >> + spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; >> + spin->batch[b++] = pad_addr; >> + spin->batch[b++] = pad_addr >> 32; >> + spin->batch[b++] = 0xc0ffee; >> + } >> + >> + /* Break if delta [time elapsed] > ns */ >> + spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; >> + spin->batch[b++] = ~(opts->ctx_ticks); >> + spin->batch[b++] = ticks_delta_addr; >> + spin->batch[b++] = ticks_delta_addr >> 32; >> + } > > Ok, this part looks good for me. > >> + >> spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; >> spin->batch[b++] = 0; >> spin->batch[b++] = end_addr; >> spin->batch[b++] = end_addr >> 32; >> >> spin->batch[b++] = MI_BATCH_BUFFER_START | 1 << 8 | 1; >> - spin->batch[b++] = batch_addr; >> - spin->batch[b++] = batch_addr >> 32; >> + spin->batch[b++] = loop_addr; >> + spin->batch[b++] = loop_addr >> 32; >> >> igt_assert(b <= ARRAY_SIZE(spin->batch)); >> } >> @@ -106,6 +191,7 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt) >> .num_syncs = 1, >> .syncs = to_user_pointer(&sync), >> }; >> + struct xe_spin_opts spin_opts = {}; >> >> igt_assert(ahnd); >> spin = calloc(1, sizeof(struct igt_spin)); >> @@ -132,11 +218,9 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt) >> addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); >> xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size); >> >> - if (!(opt->flags & IGT_SPIN_NO_PREEMPTION)) >> - xe_spin_init(xe_spin, addr, true); >> - else >> - xe_spin_init(xe_spin, addr, false); >> - >> + spin_opts.addr = addr; >> + spin_opts.preempt = !(opt->flags & IGT_SPIN_NO_PREEMPTION); >> + xe_spin_init(xe_spin, &spin_opts); > > Or just: > xe_spin_init(xe_spin, .addr = addr, > .preempt = !(opt->flags & IGT_SPIN_NO_PREEMPTION)); > > ? > > See comment below. > >> exec.exec_queue_id = spin->engine; >> exec.address = addr; >> sync.handle = spin->syncobj; >> @@ -191,6 +275,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe, >> size_t bo_size = xe_get_default_alignment(fd); >> uint32_t vm, bo, exec_queue, syncobj; >> struct xe_spin *spin; >> + struct xe_spin_opts spin_opts = { .addr = addr, .preempt = true }; >> struct drm_xe_sync sync = { >> .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, >> }; >> @@ -211,7 +296,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe, >> exec_queue = xe_exec_queue_create(fd, vm, hwe, 0); >> syncobj = syncobj_create(fd, 0); >> >> - xe_spin_init(spin, addr, true); >> + xe_spin_init(spin, &spin_opts); >> exec.exec_queue_id = exec_queue; >> exec.address = addr; >> sync.handle = syncobj; >> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h >> index c84db175d..14053a07e 100644 >> --- a/lib/xe/xe_spin.h >> +++ b/lib/xe/xe_spin.h >> @@ -15,15 +15,34 @@ >> #include "xe_query.h" >> #include "lib/igt_dummyload.h" >> >> +#define XE_SPIN_MAX_CTX_TICKS UINT32_MAX - 1000 >> + >> +/** struct xe_spin_opts >> + * >> + * @addr: offset of spinner within vm >> + * @preempt: allow spinner to be preempted or not >> + * @ctx_ticks: number of ticks after which spinner is stopped, applied if > 0 >> + * >> + * Used to initialize struct xe_spin spinner behavior. >> + */ >> +struct xe_spin_opts { >> + uint64_t addr; >> + bool preempt; >> + uint32_t ctx_ticks; >> +}; >> + >> /* Mapped GPU object */ >> struct xe_spin { >> - uint32_t batch[16]; >> + uint32_t batch[128]; >> uint64_t pad; >> uint32_t start; >> uint32_t end; >> + uint32_t ticks_delta; >> }; >> + >> igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt); >> -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt); >> +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns); >> +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts); > > I would add: > > #define xe_spin_init_opts(fd, ...) \ > xe_spin_init(fd, &((xe_spin_opts){__VA_ARGS__})) > > to call xe_spin_init() indirectly with .k = v initialization. ok, sounds good > >> bool xe_spin_started(struct xe_spin *spin); >> void xe_spin_sync_wait(int fd, struct igt_spin *spin); >> void xe_spin_wait_started(struct xe_spin *spin); >> diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c >> index 29d675154..627f4c1e5 100644 >> --- a/tests/xe/xe_dma_buf_sync.c >> +++ b/tests/xe/xe_dma_buf_sync.c >> @@ -144,7 +144,6 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, >> uint64_t sdi_offset = (char *)&data[i]->data - (char *)data[i]; >> uint64_t sdi_addr = addr + sdi_offset; >> uint64_t spin_offset = (char *)&data[i]->spin - (char *)data[i]; >> - uint64_t spin_addr = addr + spin_offset; >> struct drm_xe_sync sync[2] = { >> { .flags = DRM_XE_SYNC_SYNCOBJ, }, >> { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }, >> @@ -153,14 +152,15 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, >> .num_batch_buffer = 1, >> .syncs = to_user_pointer(sync), >> }; >> + struct xe_spin_opts spin_opts = { .addr = addr + spin_offset, .preempt = true }; >> uint32_t syncobj; >> int b = 0; >> int sync_fd; >> >> /* Write spinner on FD[0] */ >> - xe_spin_init(&data[i]->spin, spin_addr, true); >> + xe_spin_init(&data[i]->spin, &spin_opts); >> exec.exec_queue_id = exec_queue[0]; >> - exec.address = spin_addr; >> + exec.address = spin_opts.addr; >> xe_exec(fd[0], &exec); >> >> /* Export prime BO as sync file and veify business */ >> diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c >> index f364a4b7a..d7d8dd8fb 100644 >> --- a/tests/xe/xe_exec_balancer.c >> +++ b/tests/xe/xe_exec_balancer.c >> @@ -52,6 +52,7 @@ static void test_all_active(int fd, int gt, int class) >> struct { >> struct xe_spin spin; >> } *data; >> + struct xe_spin_opts spin_opts = { .preempt = false }; >> struct drm_xe_engine_class_instance *hwe; >> struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; >> int i, num_placements = 0; >> @@ -90,16 +91,14 @@ static void test_all_active(int fd, int gt, int class) >> xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); >> >> for (i = 0; i < num_placements; i++) { >> - uint64_t spin_offset = (char *)&data[i].spin - (char *)data; >> - uint64_t spin_addr = addr + spin_offset; >> - >> - xe_spin_init(&data[i].spin, spin_addr, false); >> + spin_opts.addr = addr + (char *)&data[i].spin - (char *)data; >> + xe_spin_init(&data[i].spin, &spin_opts); >> sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; >> sync[1].flags |= DRM_XE_SYNC_SIGNAL; >> sync[1].handle = syncobjs[i]; >> >> exec.exec_queue_id = exec_queues[i]; >> - exec.address = spin_addr; >> + exec.address = spin_opts.addr; >> xe_exec(fd, &exec); >> xe_spin_wait_started(&data[i].spin); >> } >> diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c >> index a2d33baf1..be6bbada6 100644 >> --- a/tests/xe/xe_exec_reset.c >> +++ b/tests/xe/xe_exec_reset.c >> @@ -44,6 +44,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) >> size_t bo_size; >> uint32_t bo = 0; >> struct xe_spin *spin; >> + struct xe_spin_opts spin_opts = { .addr = addr, .preempt = false }; >> >> vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); >> bo_size = sizeof(*spin); >> @@ -60,7 +61,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) >> sync[0].handle = syncobj_create(fd, 0); >> xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); >> >> - xe_spin_init(spin, addr, false); >> + xe_spin_init(spin, &spin_opts); >> >> sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; >> sync[1].flags |= DRM_XE_SYNC_SIGNAL; >> @@ -165,6 +166,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, >> uint64_t pad; >> uint32_t data; >> } *data; >> + struct xe_spin_opts spin_opts = { .preempt = false }; >> struct drm_xe_engine_class_instance *hwe; >> struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; >> int i, j, b, num_placements = 0, bad_batches = 1; >> @@ -236,7 +238,6 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, >> uint64_t batch_offset = (char *)&data[i].batch - (char *)data; >> uint64_t batch_addr = base_addr + batch_offset; >> uint64_t spin_offset = (char *)&data[i].spin - (char *)data; >> - uint64_t spin_addr = base_addr + spin_offset; >> uint64_t sdi_offset = (char *)&data[i].data - (char *)data; >> uint64_t sdi_addr = base_addr + sdi_offset; >> uint64_t exec_addr; >> @@ -247,8 +248,9 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, >> batches[j] = batch_addr; >> >> if (i < bad_batches) { >> - xe_spin_init(&data[i].spin, spin_addr, false); >> - exec_addr = spin_addr; >> + spin_opts.addr = base_addr + spin_offset; >> + xe_spin_init(&data[i].spin, &spin_opts); >> + exec_addr = spin_opts.addr; >> } else { >> b = 0; >> data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; >> @@ -368,6 +370,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, >> uint64_t pad; >> uint32_t data; >> } *data; >> + struct xe_spin_opts spin_opts = { .preempt = false }; >> int i, b; >> >> igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); >> @@ -417,15 +420,15 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, >> uint64_t batch_offset = (char *)&data[i].batch - (char *)data; >> uint64_t batch_addr = base_addr + batch_offset; >> uint64_t spin_offset = (char *)&data[i].spin - (char *)data; >> - uint64_t spin_addr = base_addr + spin_offset; >> uint64_t sdi_offset = (char *)&data[i].data - (char *)data; >> uint64_t sdi_addr = base_addr + sdi_offset; >> uint64_t exec_addr; >> int e = i % n_exec_queues; >> >> if (!i) { >> - xe_spin_init(&data[i].spin, spin_addr, false); >> - exec_addr = spin_addr; >> + spin_opts.addr = base_addr + spin_offset; >> + xe_spin_init(&data[i].spin, &spin_opts); >> + exec_addr = spin_opts.addr; >> } else { >> b = 0; >> data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; >> @@ -539,6 +542,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, >> uint64_t exec_sync; >> uint32_t data; >> } *data; >> + struct xe_spin_opts spin_opts = { .preempt = false }; >> int i, b; >> >> igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); >> @@ -593,15 +597,15 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, >> uint64_t batch_offset = (char *)&data[i].batch - (char *)data; >> uint64_t batch_addr = base_addr + batch_offset; >> uint64_t spin_offset = (char *)&data[i].spin - (char *)data; >> - uint64_t spin_addr = base_addr + spin_offset; >> uint64_t sdi_offset = (char *)&data[i].data - (char *)data; >> uint64_t sdi_addr = base_addr + sdi_offset; >> uint64_t exec_addr; >> int e = i % n_exec_queues; >> >> if (!i) { >> - xe_spin_init(&data[i].spin, spin_addr, false); >> - exec_addr = spin_addr; >> + spin_opts.addr = base_addr + spin_offset; >> + xe_spin_init(&data[i].spin, &spin_opts); >> + exec_addr = spin_opts.addr; >> } else { >> b = 0; >> data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; >> diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c >> index e64c1639a..ff4ebc280 100644 >> --- a/tests/xe/xe_exec_threads.c >> +++ b/tests/xe/xe_exec_threads.c >> @@ -486,6 +486,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, >> uint64_t pad; >> uint32_t data; >> } *data; >> + struct xe_spin_opts spin_opts = { .preempt = false }; >> int i, j, b, hang_exec_queue = n_exec_queues / 2; >> bool owns_vm = false, owns_fd = false; >> >> @@ -562,15 +563,15 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, >> uint64_t batch_offset = (char *)&data[i].batch - (char *)data; >> uint64_t batch_addr = addr + batch_offset; >> uint64_t spin_offset = (char *)&data[i].spin - (char *)data; >> - uint64_t spin_addr = addr + spin_offset; >> uint64_t sdi_offset = (char *)&data[i].data - (char *)data; >> uint64_t sdi_addr = addr + sdi_offset; >> uint64_t exec_addr; >> int e = i % n_exec_queues; >> >> if (flags & HANG && e == hang_exec_queue && i == e) { >> - xe_spin_init(&data[i].spin, spin_addr, false); >> - exec_addr = spin_addr; >> + spin_opts.addr = addr + spin_offset; >> + xe_spin_init(&data[i].spin, &spin_opts); >> + exec_addr = spin_opts.addr; >> } else { >> b = 0; >> data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; >> diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c >> index e42c04e33..87604a407 100644 >> --- a/tests/xe/xe_vm.c >> +++ b/tests/xe/xe_vm.c >> @@ -727,6 +727,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec >> uint64_t pad; >> uint32_t data; >> } *data; >> + struct xe_spin_opts spin_opts = { .preempt = true }; >> int i, b; >> >> vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); >> @@ -755,14 +756,14 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec >> uint64_t sdi_offset = (char *)&data[i].data - (char *)data; >> uint64_t sdi_addr = addr + sdi_offset; >> uint64_t spin_offset = (char *)&data[i].spin - (char *)data; >> - uint64_t spin_addr = addr + spin_offset; >> int e = i; >> >> if (i == 0) { >> - /* Cork 1st exec_queue with a spinner */ >> - xe_spin_init(&data[i].spin, spin_addr, true); >> + /* Cork 1st engine with a spinner */ >> + spin_opts.addr = addr + spin_offset; >> + xe_spin_init(&data[i].spin, &spin_opts); >> exec.exec_queue_id = exec_queues[e]; >> - exec.address = spin_addr; >> + exec.address = spin_opts.addr; >> sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; >> sync[1].flags |= DRM_XE_SYNC_SIGNAL; >> sync[1].handle = syncobjs[e]; >> -- >> 2.30.2 >> > > Generally looks good to me, address my nits and: > > Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Thanks for review, Marcin > > -- > Zbigniew ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin 2023-08-04 10:24 ` [igt-dev] [PATCH i-g-t 1/2] " Marcin Bernatowicz 2023-08-07 6:54 ` Zbigniew Kempczyński @ 2023-08-07 14:10 ` Kamil Konieczny 1 sibling, 0 replies; 12+ messages in thread From: Kamil Konieczny @ 2023-08-07 14:10 UTC (permalink / raw) To: igt-dev; +Cc: mauro.chehab Hi Marcin, small nit: in subject do not write about introduced structures, imho better: lib/xe_spin: introduced fixed duration xe_spin Regards, Kamil On 2023-08-04 at 10:24:53 +0000, Marcin Bernatowicz wrote: > Introduced struct xe_spin_opts for xe_spin initialization, > adjusted tests to new xe_spin_init signature. > > Extended spinner with fixed duration capability. It allows > to prepare fixed duration (ex. 10ms) workloads and take workloads/second > measurements, a handy utility for scheduling tests. > > Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> > --- > lib/xe/xe_spin.c | 121 ++++++++++++++++++++++++++++++------ > lib/xe/xe_spin.h | 23 ++++++- > tests/xe/xe_dma_buf_sync.c | 6 +- > tests/xe/xe_exec_balancer.c | 9 ++- > tests/xe/xe_exec_reset.c | 24 ++++--- > tests/xe/xe_exec_threads.c | 7 ++- > tests/xe/xe_vm.c | 9 +-- > 7 files changed, 154 insertions(+), 45 deletions(-) > > diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c > index cd9c1a7d3..44fca2258 100644 > --- a/lib/xe/xe_spin.c > +++ b/lib/xe/xe_spin.c > @@ -16,41 +16,126 @@ > #include "xe_ioctl.h" > #include "xe_spin.h" > > +static int read_timestamp_frequency(int fd, int gt_id) > +{ > + struct xe_device *dev = xe_device_get(fd); > + > + igt_assert(dev && dev->gts && dev->gts->num_gt); > + igt_assert(gt_id >= 0 && gt_id <= dev->gts->num_gt); > + > + return dev->gts->gts[gt_id].clock_freq; > +} > + > +static uint64_t div64_u64_round_up(const uint64_t x, const uint64_t y) > +{ > + return (x + y - 1) / y; > +} > + > +/** > + * duration_to_ctx_ticks: > + * @fd: opened device > + * @gt_id: tile id > + * @duration_ns: duration in nanoseconds to be converted to context timestamp ticks > + * @return: duration converted to context timestamp ticks, 0 on failure. > + */ > +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t duration_ns) > +{ > + int f = read_timestamp_frequency(fd, gt_id); > + uint64_t ctx_ticks = div64_u64_round_up(duration_ns * f, NSEC_PER_SEC); > + > + return ctx_ticks > XE_SPIN_MAX_CTX_TICKS ? 0 : ctx_ticks; > +} > + > +#define MI_SRM_CS_MMIO (1 << 19) > +#define MI_LRI_CS_MMIO (1 << 19) > +#define MI_LRR_DST_CS_MMIO (1 << 19) > +#define MI_LRR_SRC_CS_MMIO (1 << 18) > +#define CTX_TIMESTAMP 0x3a8; > +#define CS_GPR(x) (0x600 + 8 * (x)) > +enum { START_TS, NOW_TS }; > + > /** > * xe_spin_init: > * @spin: pointer to mapped bo in which spinner code will be written > - * @addr: offset of spinner within vm > - * @preempt: allow spinner to be preempted or not > + * @opts: pointer to spinner initialization options > */ > -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt) > +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts) > { > - uint64_t batch_offset = (char *)&spin->batch - (char *)spin; > - uint64_t batch_addr = addr + batch_offset; > - uint64_t start_offset = (char *)&spin->start - (char *)spin; > - uint64_t start_addr = addr + start_offset; > - uint64_t end_offset = (char *)&spin->end - (char *)spin; > - uint64_t end_addr = addr + end_offset; > + uint64_t loop_addr; > + uint64_t start_addr = opts->addr + offsetof(struct xe_spin, start); > + uint64_t end_addr = opts->addr + offsetof(struct xe_spin, end); > + uint64_t ticks_delta_addr = opts->addr + offsetof(struct xe_spin, ticks_delta); > + uint64_t pad_addr = opts->addr + offsetof(struct xe_spin, pad); > int b = 0; > > spin->start = 0; > spin->end = 0xffffffff; > + spin->ticks_delta = 0; > + > + if (opts->ctx_ticks) { > + /* store start timestamp */ > + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; > + spin->batch[b++] = CS_GPR(START_TS) + 4; > + spin->batch[b++] = 0; > + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; > + spin->batch[b++] = CTX_TIMESTAMP; > + spin->batch[b++] = CS_GPR(START_TS); > + } > + > + loop_addr = opts->addr + (char *)&spin->batch[b] - (char *)spin; > > spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; > spin->batch[b++] = start_addr; > spin->batch[b++] = start_addr >> 32; > spin->batch[b++] = 0xc0ffee; > > - if (preempt) > + if (opts->preempt) > spin->batch[b++] = (0x5 << 23); > > + if (opts->ctx_ticks) { > + spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO; > + spin->batch[b++] = CS_GPR(NOW_TS) + 4; > + spin->batch[b++] = 0; > + spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO; > + spin->batch[b++] = CTX_TIMESTAMP; > + spin->batch[b++] = CS_GPR(NOW_TS); > + > + /* delta = now - start; inverted to match COND_BBE */ > + spin->batch[b++] = MI_MATH(4); > + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); > + spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); > + spin->batch[b++] = MI_MATH_SUB; > + spin->batch[b++] = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); > + > + /* Save delta for reading by COND_BBE */ > + spin->batch[b++] = MI_STORE_REGISTER_MEM | MI_SRM_CS_MMIO | 2; > + spin->batch[b++] = CS_GPR(NOW_TS); > + spin->batch[b++] = ticks_delta_addr; > + spin->batch[b++] = ticks_delta_addr >> 32; > + > + /* Delay between SRM and COND_BBE to post the writes */ > + for (int n = 0; n < 8; n++) { > + spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4; > + spin->batch[b++] = pad_addr; > + spin->batch[b++] = pad_addr >> 32; > + spin->batch[b++] = 0xc0ffee; > + } > + > + /* Break if delta [time elapsed] > ns */ > + spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; > + spin->batch[b++] = ~(opts->ctx_ticks); > + spin->batch[b++] = ticks_delta_addr; > + spin->batch[b++] = ticks_delta_addr >> 32; > + } > + > spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2; > spin->batch[b++] = 0; > spin->batch[b++] = end_addr; > spin->batch[b++] = end_addr >> 32; > > spin->batch[b++] = MI_BATCH_BUFFER_START | 1 << 8 | 1; > - spin->batch[b++] = batch_addr; > - spin->batch[b++] = batch_addr >> 32; > + spin->batch[b++] = loop_addr; > + spin->batch[b++] = loop_addr >> 32; > > igt_assert(b <= ARRAY_SIZE(spin->batch)); > } > @@ -106,6 +191,7 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt) > .num_syncs = 1, > .syncs = to_user_pointer(&sync), > }; > + struct xe_spin_opts spin_opts = {}; > > igt_assert(ahnd); > spin = calloc(1, sizeof(struct igt_spin)); > @@ -132,11 +218,9 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt) > addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); > xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size); > > - if (!(opt->flags & IGT_SPIN_NO_PREEMPTION)) > - xe_spin_init(xe_spin, addr, true); > - else > - xe_spin_init(xe_spin, addr, false); > - > + spin_opts.addr = addr; > + spin_opts.preempt = !(opt->flags & IGT_SPIN_NO_PREEMPTION); > + xe_spin_init(xe_spin, &spin_opts); > exec.exec_queue_id = spin->engine; > exec.address = addr; > sync.handle = spin->syncobj; > @@ -191,6 +275,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe, > size_t bo_size = xe_get_default_alignment(fd); > uint32_t vm, bo, exec_queue, syncobj; > struct xe_spin *spin; > + struct xe_spin_opts spin_opts = { .addr = addr, .preempt = true }; > struct drm_xe_sync sync = { > .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, > }; > @@ -211,7 +296,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe, > exec_queue = xe_exec_queue_create(fd, vm, hwe, 0); > syncobj = syncobj_create(fd, 0); > > - xe_spin_init(spin, addr, true); > + xe_spin_init(spin, &spin_opts); > exec.exec_queue_id = exec_queue; > exec.address = addr; > sync.handle = syncobj; > diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h > index c84db175d..14053a07e 100644 > --- a/lib/xe/xe_spin.h > +++ b/lib/xe/xe_spin.h > @@ -15,15 +15,34 @@ > #include "xe_query.h" > #include "lib/igt_dummyload.h" > > +#define XE_SPIN_MAX_CTX_TICKS UINT32_MAX - 1000 > + > +/** struct xe_spin_opts > + * > + * @addr: offset of spinner within vm > + * @preempt: allow spinner to be preempted or not > + * @ctx_ticks: number of ticks after which spinner is stopped, applied if > 0 > + * > + * Used to initialize struct xe_spin spinner behavior. > + */ > +struct xe_spin_opts { > + uint64_t addr; > + bool preempt; > + uint32_t ctx_ticks; > +}; > + > /* Mapped GPU object */ > struct xe_spin { > - uint32_t batch[16]; > + uint32_t batch[128]; > uint64_t pad; > uint32_t start; > uint32_t end; > + uint32_t ticks_delta; > }; > + > igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt); > -void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt); > +uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns); > +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts); > bool xe_spin_started(struct xe_spin *spin); > void xe_spin_sync_wait(int fd, struct igt_spin *spin); > void xe_spin_wait_started(struct xe_spin *spin); > diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c > index 29d675154..627f4c1e5 100644 > --- a/tests/xe/xe_dma_buf_sync.c > +++ b/tests/xe/xe_dma_buf_sync.c > @@ -144,7 +144,6 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, > uint64_t sdi_offset = (char *)&data[i]->data - (char *)data[i]; > uint64_t sdi_addr = addr + sdi_offset; > uint64_t spin_offset = (char *)&data[i]->spin - (char *)data[i]; > - uint64_t spin_addr = addr + spin_offset; > struct drm_xe_sync sync[2] = { > { .flags = DRM_XE_SYNC_SYNCOBJ, }, > { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }, > @@ -153,14 +152,15 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, > .num_batch_buffer = 1, > .syncs = to_user_pointer(sync), > }; > + struct xe_spin_opts spin_opts = { .addr = addr + spin_offset, .preempt = true }; > uint32_t syncobj; > int b = 0; > int sync_fd; > > /* Write spinner on FD[0] */ > - xe_spin_init(&data[i]->spin, spin_addr, true); > + xe_spin_init(&data[i]->spin, &spin_opts); > exec.exec_queue_id = exec_queue[0]; > - exec.address = spin_addr; > + exec.address = spin_opts.addr; > xe_exec(fd[0], &exec); > > /* Export prime BO as sync file and veify business */ > diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c > index f364a4b7a..d7d8dd8fb 100644 > --- a/tests/xe/xe_exec_balancer.c > +++ b/tests/xe/xe_exec_balancer.c > @@ -52,6 +52,7 @@ static void test_all_active(int fd, int gt, int class) > struct { > struct xe_spin spin; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = false }; > struct drm_xe_engine_class_instance *hwe; > struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; > int i, num_placements = 0; > @@ -90,16 +91,14 @@ static void test_all_active(int fd, int gt, int class) > xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); > > for (i = 0; i < num_placements; i++) { > - uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = addr + spin_offset; > - > - xe_spin_init(&data[i].spin, spin_addr, false); > + spin_opts.addr = addr + (char *)&data[i].spin - (char *)data; > + xe_spin_init(&data[i].spin, &spin_opts); > sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; > sync[1].flags |= DRM_XE_SYNC_SIGNAL; > sync[1].handle = syncobjs[i]; > > exec.exec_queue_id = exec_queues[i]; > - exec.address = spin_addr; > + exec.address = spin_opts.addr; > xe_exec(fd, &exec); > xe_spin_wait_started(&data[i].spin); > } > diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c > index a2d33baf1..be6bbada6 100644 > --- a/tests/xe/xe_exec_reset.c > +++ b/tests/xe/xe_exec_reset.c > @@ -44,6 +44,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) > size_t bo_size; > uint32_t bo = 0; > struct xe_spin *spin; > + struct xe_spin_opts spin_opts = { .addr = addr, .preempt = false }; > > vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); > bo_size = sizeof(*spin); > @@ -60,7 +61,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) > sync[0].handle = syncobj_create(fd, 0); > xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); > > - xe_spin_init(spin, addr, false); > + xe_spin_init(spin, &spin_opts); > > sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; > sync[1].flags |= DRM_XE_SYNC_SIGNAL; > @@ -165,6 +166,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, > uint64_t pad; > uint32_t data; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = false }; > struct drm_xe_engine_class_instance *hwe; > struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; > int i, j, b, num_placements = 0, bad_batches = 1; > @@ -236,7 +238,6 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, > uint64_t batch_offset = (char *)&data[i].batch - (char *)data; > uint64_t batch_addr = base_addr + batch_offset; > uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = base_addr + spin_offset; > uint64_t sdi_offset = (char *)&data[i].data - (char *)data; > uint64_t sdi_addr = base_addr + sdi_offset; > uint64_t exec_addr; > @@ -247,8 +248,9 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, > batches[j] = batch_addr; > > if (i < bad_batches) { > - xe_spin_init(&data[i].spin, spin_addr, false); > - exec_addr = spin_addr; > + spin_opts.addr = base_addr + spin_offset; > + xe_spin_init(&data[i].spin, &spin_opts); > + exec_addr = spin_opts.addr; > } else { > b = 0; > data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; > @@ -368,6 +370,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, > uint64_t pad; > uint32_t data; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = false }; > int i, b; > > igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > @@ -417,15 +420,15 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, > uint64_t batch_offset = (char *)&data[i].batch - (char *)data; > uint64_t batch_addr = base_addr + batch_offset; > uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = base_addr + spin_offset; > uint64_t sdi_offset = (char *)&data[i].data - (char *)data; > uint64_t sdi_addr = base_addr + sdi_offset; > uint64_t exec_addr; > int e = i % n_exec_queues; > > if (!i) { > - xe_spin_init(&data[i].spin, spin_addr, false); > - exec_addr = spin_addr; > + spin_opts.addr = base_addr + spin_offset; > + xe_spin_init(&data[i].spin, &spin_opts); > + exec_addr = spin_opts.addr; > } else { > b = 0; > data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; > @@ -539,6 +542,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > uint64_t exec_sync; > uint32_t data; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = false }; > int i, b; > > igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > @@ -593,15 +597,15 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > uint64_t batch_offset = (char *)&data[i].batch - (char *)data; > uint64_t batch_addr = base_addr + batch_offset; > uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = base_addr + spin_offset; > uint64_t sdi_offset = (char *)&data[i].data - (char *)data; > uint64_t sdi_addr = base_addr + sdi_offset; > uint64_t exec_addr; > int e = i % n_exec_queues; > > if (!i) { > - xe_spin_init(&data[i].spin, spin_addr, false); > - exec_addr = spin_addr; > + spin_opts.addr = base_addr + spin_offset; > + xe_spin_init(&data[i].spin, &spin_opts); > + exec_addr = spin_opts.addr; > } else { > b = 0; > data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; > diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c > index e64c1639a..ff4ebc280 100644 > --- a/tests/xe/xe_exec_threads.c > +++ b/tests/xe/xe_exec_threads.c > @@ -486,6 +486,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > uint64_t pad; > uint32_t data; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = false }; > int i, j, b, hang_exec_queue = n_exec_queues / 2; > bool owns_vm = false, owns_fd = false; > > @@ -562,15 +563,15 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > uint64_t batch_offset = (char *)&data[i].batch - (char *)data; > uint64_t batch_addr = addr + batch_offset; > uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = addr + spin_offset; > uint64_t sdi_offset = (char *)&data[i].data - (char *)data; > uint64_t sdi_addr = addr + sdi_offset; > uint64_t exec_addr; > int e = i % n_exec_queues; > > if (flags & HANG && e == hang_exec_queue && i == e) { > - xe_spin_init(&data[i].spin, spin_addr, false); > - exec_addr = spin_addr; > + spin_opts.addr = addr + spin_offset; > + xe_spin_init(&data[i].spin, &spin_opts); > + exec_addr = spin_opts.addr; > } else { > b = 0; > data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4; > diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c > index e42c04e33..87604a407 100644 > --- a/tests/xe/xe_vm.c > +++ b/tests/xe/xe_vm.c > @@ -727,6 +727,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec > uint64_t pad; > uint32_t data; > } *data; > + struct xe_spin_opts spin_opts = { .preempt = true }; > int i, b; > > vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); > @@ -755,14 +756,14 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec > uint64_t sdi_offset = (char *)&data[i].data - (char *)data; > uint64_t sdi_addr = addr + sdi_offset; > uint64_t spin_offset = (char *)&data[i].spin - (char *)data; > - uint64_t spin_addr = addr + spin_offset; > int e = i; > > if (i == 0) { > - /* Cork 1st exec_queue with a spinner */ > - xe_spin_init(&data[i].spin, spin_addr, true); > + /* Cork 1st engine with a spinner */ > + spin_opts.addr = addr + spin_offset; > + xe_spin_init(&data[i].spin, &spin_opts); > exec.exec_queue_id = exec_queues[e]; > - exec.address = spin_addr; > + exec.address = spin_opts.addr; > sync[0].flags &= ~DRM_XE_SYNC_SIGNAL; > sync[1].flags |= DRM_XE_SYNC_SIGNAL; > sync[1].handle = syncobjs[e]; > -- > 2.30.2 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe_spin_batch: spin-fixed-duration 2023-08-04 10:24 [igt-dev] [PATCH i-g-t 0/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin Marcin Bernatowicz 2023-08-04 10:24 ` [igt-dev] [PATCH i-g-t 1/2] " Marcin Bernatowicz @ 2023-08-04 10:24 ` Marcin Bernatowicz 2023-08-07 6:56 ` Zbigniew Kempczyński 2023-08-04 13:41 ` [igt-dev] ✓ Fi.CI.BAT: success for lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin Patchwork ` (2 subsequent siblings) 4 siblings, 1 reply; 12+ messages in thread From: Marcin Bernatowicz @ 2023-08-04 10:24 UTC (permalink / raw) To: igt-dev; +Cc: mauro.chehab Basic test for xe_spin with fixed duration. Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> --- tests/xe/xe_spin_batch.c | 59 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c index 26f9daf36..bdad3bab9 100644 --- a/tests/xe/xe_spin_batch.c +++ b/tests/xe/xe_spin_batch.c @@ -1,8 +1,10 @@ #include "igt.h" +#include "igt_syncobj.h" #include "lib/intel_reg.h" #include "xe_drm.h" #include "xe/xe_ioctl.h" #include "xe/xe_query.h" +#include "xe/xe_spin.h" /** * TEST: Tests for spin batch submissons. @@ -138,6 +140,60 @@ static void spin_all(int fd, int gt, int class) xe_vm_destroy(fd, vm); } +/** + * SUBTEST: spin-fixed-duration + * Description: Basic test which validates the functionality of xe_spin with fixed duration. + * Run type: FULL + */ +static void xe_spin_fixed_duration(int fd) +{ + uint64_t ahnd; + uint32_t vm; + unsigned int exec_queue; + uint32_t bo; + size_t bo_size; + struct xe_spin *spin; + struct xe_spin_opts spin_opts = {}; + struct drm_xe_sync sync = { + .handle = syncobj_create(fd, 0), + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, + }; + struct drm_xe_exec exec = { + .num_batch_buffer = 1, + .num_syncs = 1, + .syncs = to_user_pointer(&sync), + }; + struct timespec tv; + uint64_t duration_ns = NSEC_PER_SEC / 10; /* 100ms */ + + vm = xe_vm_create(fd, 0, 0); + exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC); + bo_size = ALIGN(sizeof(*spin) + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); + bo = xe_bo_create(fd, 0, vm, bo_size); + spin = xe_bo_map(fd, bo, bo_size); + spin_opts.addr = intel_allocator_alloc_with_strategy(ahnd, bo, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); + spin_opts.ctx_ticks = duration_to_ctx_ticks(fd, 0, duration_ns); + xe_vm_bind_sync(fd, vm, bo, 0, spin_opts.addr, bo_size); + xe_spin_init(spin, &spin_opts); + exec.exec_queue_id = exec_queue; + exec.address = spin_opts.addr; + + igt_gettime(&tv); + xe_exec(fd, &exec); + xe_spin_wait_started(spin); + igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL)); + igt_info("%.0fms spin took %.1fms\n", duration_ns * 1e-6, igt_nsec_elapsed(&tv) * 1e-6); + + xe_vm_unbind_sync(fd, vm, 0, spin_opts.addr, bo_size); + syncobj_destroy(fd, sync.handle); + gem_munmap(spin, bo_size); + gem_close(fd, bo); + xe_exec_queue_destroy(fd, exec_queue); + xe_vm_destroy(fd, vm); + put_ahnd(ahnd); +} + igt_main { struct drm_xe_engine_class_instance *hwe; @@ -163,6 +219,9 @@ igt_main spin_all(fd, gt, class); } + igt_subtest("spin-fixed-duration") + xe_spin_fixed_duration(fd); + igt_fixture drm_close_driver(fd); } -- 2.30.2 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe_spin_batch: spin-fixed-duration 2023-08-04 10:24 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe_spin_batch: spin-fixed-duration Marcin Bernatowicz @ 2023-08-07 6:56 ` Zbigniew Kempczyński 2023-08-07 14:13 ` Bernatowicz, Marcin 0 siblings, 1 reply; 12+ messages in thread From: Zbigniew Kempczyński @ 2023-08-07 6:56 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev, mauro.chehab On Fri, Aug 04, 2023 at 10:24:54AM +0000, Marcin Bernatowicz wrote: > Basic test for xe_spin with fixed duration. > > Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> > --- > tests/xe/xe_spin_batch.c | 59 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 59 insertions(+) > > diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c > index 26f9daf36..bdad3bab9 100644 > --- a/tests/xe/xe_spin_batch.c > +++ b/tests/xe/xe_spin_batch.c > @@ -1,8 +1,10 @@ > #include "igt.h" > +#include "igt_syncobj.h" > #include "lib/intel_reg.h" > #include "xe_drm.h" > #include "xe/xe_ioctl.h" > #include "xe/xe_query.h" > +#include "xe/xe_spin.h" > > /** > * TEST: Tests for spin batch submissons. > @@ -138,6 +140,60 @@ static void spin_all(int fd, int gt, int class) > xe_vm_destroy(fd, vm); > } > > +/** > + * SUBTEST: spin-fixed-duration > + * Description: Basic test which validates the functionality of xe_spin with fixed duration. > + * Run type: FULL > + */ > +static void xe_spin_fixed_duration(int fd) > +{ > + uint64_t ahnd; > + uint32_t vm; > + unsigned int exec_queue; > + uint32_t bo; > + size_t bo_size; > + struct xe_spin *spin; > + struct xe_spin_opts spin_opts = {}; > + struct drm_xe_sync sync = { > + .handle = syncobj_create(fd, 0), > + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, > + }; > + struct drm_xe_exec exec = { > + .num_batch_buffer = 1, > + .num_syncs = 1, > + .syncs = to_user_pointer(&sync), > + }; > + struct timespec tv; > + uint64_t duration_ns = NSEC_PER_SEC / 10; /* 100ms */ > + > + vm = xe_vm_create(fd, 0, 0); > + exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC); > + bo_size = ALIGN(sizeof(*spin) + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); > + bo = xe_bo_create(fd, 0, vm, bo_size); > + spin = xe_bo_map(fd, bo, bo_size); > + spin_opts.addr = intel_allocator_alloc_with_strategy(ahnd, bo, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); > + spin_opts.ctx_ticks = duration_to_ctx_ticks(fd, 0, duration_ns); > + xe_vm_bind_sync(fd, vm, bo, 0, spin_opts.addr, bo_size); > + xe_spin_init(spin, &spin_opts); > + exec.exec_queue_id = exec_queue; > + exec.address = spin_opts.addr; > + > + igt_gettime(&tv); > + xe_exec(fd, &exec); > + xe_spin_wait_started(spin); > + igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL)); > + igt_info("%.0fms spin took %.1fms\n", duration_ns * 1e-6, igt_nsec_elapsed(&tv) * 1e-6); I would assume some error margin (let's say 10% of duration_ns) and assert if spinner doesn't end in this time. igt_info() is not enough imo if we want to be sure spinner runs in fixed time. -- Zbigniew > + > + xe_vm_unbind_sync(fd, vm, 0, spin_opts.addr, bo_size); > + syncobj_destroy(fd, sync.handle); > + gem_munmap(spin, bo_size); > + gem_close(fd, bo); > + xe_exec_queue_destroy(fd, exec_queue); > + xe_vm_destroy(fd, vm); > + put_ahnd(ahnd); > +} > + > igt_main > { > struct drm_xe_engine_class_instance *hwe; > @@ -163,6 +219,9 @@ igt_main > spin_all(fd, gt, class); > } > > + igt_subtest("spin-fixed-duration") > + xe_spin_fixed_duration(fd); > + > igt_fixture > drm_close_driver(fd); > } > -- > 2.30.2 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe_spin_batch: spin-fixed-duration 2023-08-07 6:56 ` Zbigniew Kempczyński @ 2023-08-07 14:13 ` Bernatowicz, Marcin 2023-08-09 11:23 ` Zbigniew Kempczyński 0 siblings, 1 reply; 12+ messages in thread From: Bernatowicz, Marcin @ 2023-08-07 14:13 UTC (permalink / raw) To: Zbigniew Kempczyński; +Cc: igt-dev, mauro.chehab On 8/7/2023 8:56 AM, Zbigniew Kempczyński wrote: > On Fri, Aug 04, 2023 at 10:24:54AM +0000, Marcin Bernatowicz wrote: >> Basic test for xe_spin with fixed duration. >> >> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> >> --- >> tests/xe/xe_spin_batch.c | 59 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 59 insertions(+) >> >> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c >> index 26f9daf36..bdad3bab9 100644 >> --- a/tests/xe/xe_spin_batch.c >> +++ b/tests/xe/xe_spin_batch.c >> @@ -1,8 +1,10 @@ >> #include "igt.h" >> +#include "igt_syncobj.h" >> #include "lib/intel_reg.h" >> #include "xe_drm.h" >> #include "xe/xe_ioctl.h" >> #include "xe/xe_query.h" >> +#include "xe/xe_spin.h" >> >> /** >> * TEST: Tests for spin batch submissons. >> @@ -138,6 +140,60 @@ static void spin_all(int fd, int gt, int class) >> xe_vm_destroy(fd, vm); >> } >> >> +/** >> + * SUBTEST: spin-fixed-duration >> + * Description: Basic test which validates the functionality of xe_spin with fixed duration. >> + * Run type: FULL >> + */ >> +static void xe_spin_fixed_duration(int fd) >> +{ >> + uint64_t ahnd; >> + uint32_t vm; >> + unsigned int exec_queue; >> + uint32_t bo; >> + size_t bo_size; >> + struct xe_spin *spin; >> + struct xe_spin_opts spin_opts = {}; >> + struct drm_xe_sync sync = { >> + .handle = syncobj_create(fd, 0), >> + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, >> + }; >> + struct drm_xe_exec exec = { >> + .num_batch_buffer = 1, >> + .num_syncs = 1, >> + .syncs = to_user_pointer(&sync), >> + }; >> + struct timespec tv; >> + uint64_t duration_ns = NSEC_PER_SEC / 10; /* 100ms */ >> + >> + vm = xe_vm_create(fd, 0, 0); >> + exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); >> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC); >> + bo_size = ALIGN(sizeof(*spin) + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); >> + bo = xe_bo_create(fd, 0, vm, bo_size); >> + spin = xe_bo_map(fd, bo, bo_size); >> + spin_opts.addr = intel_allocator_alloc_with_strategy(ahnd, bo, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); >> + spin_opts.ctx_ticks = duration_to_ctx_ticks(fd, 0, duration_ns); >> + xe_vm_bind_sync(fd, vm, bo, 0, spin_opts.addr, bo_size); >> + xe_spin_init(spin, &spin_opts); >> + exec.exec_queue_id = exec_queue; >> + exec.address = spin_opts.addr; >> + >> + igt_gettime(&tv); >> + xe_exec(fd, &exec); >> + xe_spin_wait_started(spin); >> + igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL)); >> + igt_info("%.0fms spin took %.1fms\n", duration_ns * 1e-6, igt_nsec_elapsed(&tv) * 1e-6); > > I would assume some error margin (let's say 10% of duration_ns) and assert > if spinner doesn't end in this time. igt_info() is not enough imo if > we want to be sure spinner runs in fixed time. > This may be a bit tricky, single run may actually exceed 10%, and it also depends on the drm debug level parameter used. We can complicate the sample a bit and take median of few execs: igt_stats_init_with_size(&stats, 5); for (i = 0; i < 5; ++i) { igt_gettime(&tv); xe_exec(fd, &exec); xe_spin_wait_started(spin); igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL)); igt_stats_push_float(&stats, igt_nsec_elapsed(&tv) * 1e-6); syncobj_reset(fd, &sync.handle, 1); igt_debug("i=%d %.2fms\n", i, stats.values_f[i]); } elapsed_ms = igt_stats_get_median(&stats); igt_info("%.0fms spin took %.2fms (median)\n", duration_ns * 1e-6, elapsed_ms); igt_assert(elapsed_ms < duration_ns * 1.5e-6 && elapsed_ms > duration_ns * 0.5e-6); -- marcin -- > Zbigniew > >> + >> + xe_vm_unbind_sync(fd, vm, 0, spin_opts.addr, bo_size); >> + syncobj_destroy(fd, sync.handle); >> + gem_munmap(spin, bo_size); >> + gem_close(fd, bo); >> + xe_exec_queue_destroy(fd, exec_queue); >> + xe_vm_destroy(fd, vm); >> + put_ahnd(ahnd); >> +} >> + >> igt_main >> { >> struct drm_xe_engine_class_instance *hwe; >> @@ -163,6 +219,9 @@ igt_main >> spin_all(fd, gt, class); >> } >> >> + igt_subtest("spin-fixed-duration") >> + xe_spin_fixed_duration(fd); >> + >> igt_fixture >> drm_close_driver(fd); >> } >> -- >> 2.30.2 >> ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe_spin_batch: spin-fixed-duration 2023-08-07 14:13 ` Bernatowicz, Marcin @ 2023-08-09 11:23 ` Zbigniew Kempczyński 0 siblings, 0 replies; 12+ messages in thread From: Zbigniew Kempczyński @ 2023-08-09 11:23 UTC (permalink / raw) To: Bernatowicz, Marcin; +Cc: igt-dev, mauro.chehab On Mon, Aug 07, 2023 at 04:13:37PM +0200, Bernatowicz, Marcin wrote: > > > On 8/7/2023 8:56 AM, Zbigniew Kempczyński wrote: > > On Fri, Aug 04, 2023 at 10:24:54AM +0000, Marcin Bernatowicz wrote: > > > Basic test for xe_spin with fixed duration. > > > > > > Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> > > > --- > > > tests/xe/xe_spin_batch.c | 59 ++++++++++++++++++++++++++++++++++++++++ > > > 1 file changed, 59 insertions(+) > > > > > > diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c > > > index 26f9daf36..bdad3bab9 100644 > > > --- a/tests/xe/xe_spin_batch.c > > > +++ b/tests/xe/xe_spin_batch.c > > > @@ -1,8 +1,10 @@ > > > #include "igt.h" > > > +#include "igt_syncobj.h" > > > #include "lib/intel_reg.h" > > > #include "xe_drm.h" > > > #include "xe/xe_ioctl.h" > > > #include "xe/xe_query.h" > > > +#include "xe/xe_spin.h" > > > /** > > > * TEST: Tests for spin batch submissons. > > > @@ -138,6 +140,60 @@ static void spin_all(int fd, int gt, int class) > > > xe_vm_destroy(fd, vm); > > > } > > > +/** > > > + * SUBTEST: spin-fixed-duration > > > + * Description: Basic test which validates the functionality of xe_spin with fixed duration. > > > + * Run type: FULL > > > + */ > > > +static void xe_spin_fixed_duration(int fd) > > > +{ > > > + uint64_t ahnd; > > > + uint32_t vm; > > > + unsigned int exec_queue; > > > + uint32_t bo; > > > + size_t bo_size; > > > + struct xe_spin *spin; > > > + struct xe_spin_opts spin_opts = {}; > > > + struct drm_xe_sync sync = { > > > + .handle = syncobj_create(fd, 0), > > > + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, > > > + }; > > > + struct drm_xe_exec exec = { > > > + .num_batch_buffer = 1, > > > + .num_syncs = 1, > > > + .syncs = to_user_pointer(&sync), > > > + }; > > > + struct timespec tv; > > > + uint64_t duration_ns = NSEC_PER_SEC / 10; /* 100ms */ > > > + > > > + vm = xe_vm_create(fd, 0, 0); > > > + exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); > > > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC); > > > + bo_size = ALIGN(sizeof(*spin) + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); > > > + bo = xe_bo_create(fd, 0, vm, bo_size); > > > + spin = xe_bo_map(fd, bo, bo_size); > > > + spin_opts.addr = intel_allocator_alloc_with_strategy(ahnd, bo, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); > > > + spin_opts.ctx_ticks = duration_to_ctx_ticks(fd, 0, duration_ns); > > > + xe_vm_bind_sync(fd, vm, bo, 0, spin_opts.addr, bo_size); > > > + xe_spin_init(spin, &spin_opts); > > > + exec.exec_queue_id = exec_queue; > > > + exec.address = spin_opts.addr; > > > + > > > + igt_gettime(&tv); > > > + xe_exec(fd, &exec); > > > + xe_spin_wait_started(spin); > > > + igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL)); > > > + igt_info("%.0fms spin took %.1fms\n", duration_ns * 1e-6, igt_nsec_elapsed(&tv) * 1e-6); > > > > I would assume some error margin (let's say 10% of duration_ns) and assert > > if spinner doesn't end in this time. igt_info() is not enough imo if > > we want to be sure spinner runs in fixed time. > > > This may be a bit tricky, single run may actually exceed 10%, and it also > depends on the drm debug level parameter used. > > We can complicate the sample a bit and take median of few execs: > > igt_stats_init_with_size(&stats, 5); > for (i = 0; i < 5; ++i) { > igt_gettime(&tv); > xe_exec(fd, &exec); > xe_spin_wait_started(spin); > igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL)); > igt_stats_push_float(&stats, igt_nsec_elapsed(&tv) * 1e-6); > syncobj_reset(fd, &sync.handle, 1); > igt_debug("i=%d %.2fms\n", i, stats.values_f[i]); > } > elapsed_ms = igt_stats_get_median(&stats); > igt_info("%.0fms spin took %.2fms (median)\n", duration_ns * 1e-6, > elapsed_ms); > igt_assert(elapsed_ms < duration_ns * 1.5e-6 && elapsed_ms > duration_ns * > 0.5e-6); > Ok, median is fine for me. With above: Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> -- Zbigniew > -- > marcin > -- > > Zbigniew > > > > > + > > > + xe_vm_unbind_sync(fd, vm, 0, spin_opts.addr, bo_size); > > > + syncobj_destroy(fd, sync.handle); > > > + gem_munmap(spin, bo_size); > > > + gem_close(fd, bo); > > > + xe_exec_queue_destroy(fd, exec_queue); > > > + xe_vm_destroy(fd, vm); > > > + put_ahnd(ahnd); > > > +} > > > + > > > igt_main > > > { > > > struct drm_xe_engine_class_instance *hwe; > > > @@ -163,6 +219,9 @@ igt_main > > > spin_all(fd, gt, class); > > > } > > > + igt_subtest("spin-fixed-duration") > > > + xe_spin_fixed_duration(fd); > > > + > > > igt_fixture > > > drm_close_driver(fd); > > > } > > > -- > > > 2.30.2 > > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin 2023-08-04 10:24 [igt-dev] [PATCH i-g-t 0/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin Marcin Bernatowicz 2023-08-04 10:24 ` [igt-dev] [PATCH i-g-t 1/2] " Marcin Bernatowicz 2023-08-04 10:24 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe_spin_batch: spin-fixed-duration Marcin Bernatowicz @ 2023-08-04 13:41 ` Patchwork 2023-08-04 14:13 ` [igt-dev] ○ CI.xeBAT: info " Patchwork 2023-08-04 20:13 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 4 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2023-08-04 13:41 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 9293 bytes --] == Series Details == Series: lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin URL : https://patchwork.freedesktop.org/series/122025/ State : success == Summary == CI Bug Log - changes from CI_DRM_13475 -> IGTPW_9518 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/index.html Participating hosts (42 -> 41) ------------------------------ Missing (1): fi-snb-2520m Known issues ------------ Here are the changes found in IGTPW_9518 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_lmem_swapping@parallel-random-engines: - bat-adlp-9: NOTRUN -> [SKIP][1] ([i915#4613]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-adlp-9/igt@gem_lmem_swapping@parallel-random-engines.html * igt@i915_pm_rpm@module-reload: - fi-rkl-11600: [PASS][2] -> [FAIL][3] ([i915#7940]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html - fi-skl-guc: [PASS][4] -> [FAIL][5] ([i915#7940]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/fi-skl-guc/igt@i915_pm_rpm@module-reload.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/fi-skl-guc/igt@i915_pm_rpm@module-reload.html * igt@i915_pm_rps@basic-api: - bat-adlp-9: NOTRUN -> [SKIP][6] ([i915#6621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-adlp-9/igt@i915_pm_rps@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - bat-jsl-1: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/bat-jsl-1/igt@i915_selftest@live@gt_heartbeat.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-jsl-1/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [PASS][9] -> [DMESG-FAIL][10] ([i915#7059]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@gt_pm: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][11] ([i915#4258] / [i915#7913]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-rpls-2/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [PASS][12] -> [DMESG-FAIL][13] ([i915#8497]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/bat-mtlp-8/igt@i915_selftest@live@requests.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-mtlp-8/igt@i915_selftest@live@requests.html * igt@i915_selftest@live@slpc: - bat-mtlp-8: [PASS][14] -> [DMESG-WARN][15] ([i915#6367]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/bat-mtlp-8/igt@i915_selftest@live@slpc.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-mtlp-8/igt@i915_selftest@live@slpc.html - bat-rpls-1: NOTRUN -> [DMESG-WARN][16] ([i915#6367]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-rpls-1/igt@i915_selftest@live@slpc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-adlp-9: NOTRUN -> [SKIP][17] ([i915#7828]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-adlp-9/igt@kms_chamelium_hpd@common-hpd-after-suspend.html - bat-rpls-2: NOTRUN -> [SKIP][18] ([i915#7828]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#1845] / [i915#5354]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1: - bat-rplp-1: [PASS][20] -> [ABORT][21] ([i915#8442] / [i915#8668]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-rpls-2: NOTRUN -> [SKIP][22] ([i915#1845]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html * igt@prime_vgem@basic-fence-read: - bat-adlp-9: NOTRUN -> [SKIP][23] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-adlp-9/igt@prime_vgem@basic-fence-read.html #### Possible fixes #### * igt@i915_pm_rpm@basic-rte: - bat-adlp-9: [ABORT][24] ([i915#7977] / [i915#8668]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/bat-adlp-9/igt@i915_pm_rpm@basic-rte.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-adlp-9/igt@i915_pm_rpm@basic-rte.html * igt@i915_selftest@live@gt_lrc: - bat-rpls-2: [INCOMPLETE][26] ([i915#4983] / [i915#7913]) -> [PASS][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/bat-rpls-2/igt@i915_selftest@live@gt_lrc.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-rpls-2/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@mman: - bat-rpls-1: [TIMEOUT][28] ([i915#6794] / [i915#7392]) -> [PASS][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/bat-rpls-1/igt@i915_selftest@live@mman.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-rpls-1/igt@i915_selftest@live@mman.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-rpls-1: [WARN][30] ([i915#8747]) -> [PASS][31] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html #### Warnings #### * igt@i915_module_load@load: - bat-adlp-11: [DMESG-WARN][32] ([i915#4423]) -> [ABORT][33] ([i915#4423]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/bat-adlp-11/igt@i915_module_load@load.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/bat-adlp-11/igt@i915_module_load@load.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-cfl-8700k: [FAIL][34] ([i915#7940]) -> [FAIL][35] ([i915#7691]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258 [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794 [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059 [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392 [i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940 [i915#7977]: https://gitlab.freedesktop.org/drm/intel/issues/7977 [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442 [i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#8747]: https://gitlab.freedesktop.org/drm/intel/issues/8747 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7414 -> IGTPW_9518 CI-20190529: 20190529 CI_DRM_13475: ae4f66974d076e3729337ffd1caf1316969916ef @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_9518: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/index.html IGT_7414: 056c9d7f2a63dd6d0b9b6462b4ab1b096178dcc6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Testlist changes ---------------- +igt@xe_spin_batch@spin-fixed-duration == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/index.html [-- Attachment #2: Type: text/html, Size: 10939 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] ○ CI.xeBAT: info for lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin 2023-08-04 10:24 [igt-dev] [PATCH i-g-t 0/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin Marcin Bernatowicz ` (2 preceding siblings ...) 2023-08-04 13:41 ` [igt-dev] ✓ Fi.CI.BAT: success for lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin Patchwork @ 2023-08-04 14:13 ` Patchwork 2023-08-04 20:13 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 4 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2023-08-04 14:13 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 358 bytes --] == Series Details == Series: lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin URL : https://patchwork.freedesktop.org/series/122025/ State : info == Summary == Participating hosts: bat-pvc-2 bat-atsm-2 bat-dg2-oem2 bat-adlp-7 Missing hosts results[0]: Results: [IGTPW_9518](https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9518/index.html) [-- Attachment #2: Type: text/html, Size: 874 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin 2023-08-04 10:24 [igt-dev] [PATCH i-g-t 0/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin Marcin Bernatowicz ` (3 preceding siblings ...) 2023-08-04 14:13 ` [igt-dev] ○ CI.xeBAT: info " Patchwork @ 2023-08-04 20:13 ` Patchwork 4 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2023-08-04 20:13 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 71616 bytes --] == Series Details == Series: lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin URL : https://patchwork.freedesktop.org/series/122025/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13475_full -> IGTPW_9518_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_9518_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_9518_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/index.html Participating hosts (10 -> 9) ------------------------------ Missing (1): pig-kbl-iris Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_9518_full: ### IGT changes ### #### Possible regressions #### * igt@fbdev@read: - shard-dg2: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-6/igt@fbdev@read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-5/igt@fbdev@read.html - shard-dg1: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-19/igt@fbdev@read.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-13/igt@fbdev@read.html * igt@gem_exec_schedule@wide@rcs0: - shard-rkl: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-rkl-7/igt@gem_exec_schedule@wide@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-4/igt@gem_exec_schedule@wide@rcs0.html Known issues ------------ Here are the changes found in IGTPW_9518_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@device_reset@unbind-cold-reset-rebind: - shard-mtlp: NOTRUN -> [SKIP][7] ([i915#7701]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-4/igt@device_reset@unbind-cold-reset-rebind.html * igt@drm_fdinfo@isolation@bcs0: - shard-dg2: NOTRUN -> [SKIP][8] ([i915#8414]) +10 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@drm_fdinfo@isolation@bcs0.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-mtlp: [PASS][9] -> [FAIL][10] ([i915#6121]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-2/igt@gem_ctx_exec@basic-nohangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-2/igt@gem_ctx_exec@basic-nohangcheck.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-tglu: [PASS][11] -> [DMESG-WARN][12] ([i915#5122] / [i915#5251]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-tglu-4/igt@gem_ctx_isolation@preservation-s3@bcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-2/igt@gem_ctx_isolation@preservation-s3@bcs0.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-tglu: [PASS][13] -> [ABORT][14] ([i915#5122] / [i915#5251]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-tglu-4/igt@gem_ctx_isolation@preservation-s3@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-2/igt@gem_ctx_isolation@preservation-s3@rcs0.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-tglu: [PASS][15] -> [DMESG-WARN][16] ([i915#5251]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-tglu-4/igt@gem_ctx_isolation@preservation-s3@vcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-2/igt@gem_ctx_isolation@preservation-s3@vcs0.html * igt@gem_ctx_persistence@engines-hang@vcs0: - shard-mtlp: [PASS][17] -> [FAIL][18] ([i915#2410]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-4/igt@gem_ctx_persistence@engines-hang@vcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-5/igt@gem_ctx_persistence@engines-hang@vcs0.html * igt@gem_ctx_persistence@heartbeat-hang: - shard-mtlp: NOTRUN -> [SKIP][19] ([i915#8555]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-1/igt@gem_ctx_persistence@heartbeat-hang.html * igt@gem_ctx_persistence@processes: - shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#1099]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-snb4/igt@gem_ctx_persistence@processes.html * igt@gem_ctx_sseu@invalid-sseu: - shard-dg2: NOTRUN -> [SKIP][21] ([i915#280]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-6/igt@gem_ctx_sseu@invalid-sseu.html * igt@gem_eio@unwedge-stress: - shard-dg1: [PASS][22] -> [FAIL][23] ([i915#5784]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-18/igt@gem_eio@unwedge-stress.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-14/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@noheartbeat: - shard-dg1: NOTRUN -> [SKIP][24] ([i915#8555]) +1 similar issue [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-13/igt@gem_exec_balancer@noheartbeat.html * igt@gem_exec_fair@basic-deadline: - shard-rkl: [PASS][25] -> [FAIL][26] ([i915#2846]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none: - shard-dg1: NOTRUN -> [SKIP][27] ([i915#3539] / [i915#4852]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-19/igt@gem_exec_fair@basic-none.html - shard-mtlp: NOTRUN -> [SKIP][28] ([i915#4473] / [i915#4771]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-7/igt@gem_exec_fair@basic-none.html * igt@gem_exec_fair@basic-none@bcs0: - shard-rkl: [PASS][29] -> [FAIL][30] ([i915#2842]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-rkl-6/igt@gem_exec_fair@basic-none@bcs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-2/igt@gem_exec_fair@basic-none@bcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-glk: [PASS][31] -> [FAIL][32] ([i915#2842]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-glk2/igt@gem_exec_fair@basic-pace@rcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-glk6/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fence@concurrent: - shard-mtlp: NOTRUN -> [SKIP][33] ([i915#4812]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-6/igt@gem_exec_fence@concurrent.html * igt@gem_exec_flush@basic-wb-prw-default: - shard-dg2: NOTRUN -> [SKIP][34] ([i915#3539] / [i915#4852]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-3/igt@gem_exec_flush@basic-wb-prw-default.html * igt@gem_exec_reloc@basic-concurrent0: - shard-dg2: NOTRUN -> [SKIP][35] ([i915#3281]) +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-8/igt@gem_exec_reloc@basic-concurrent0.html - shard-rkl: NOTRUN -> [SKIP][36] ([i915#3281]) +2 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-4/igt@gem_exec_reloc@basic-concurrent0.html * igt@gem_exec_reloc@basic-gtt-cpu-active: - shard-dg1: NOTRUN -> [SKIP][37] ([i915#3281]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-16/igt@gem_exec_reloc@basic-gtt-cpu-active.html * igt@gem_exec_reloc@basic-wc: - shard-mtlp: NOTRUN -> [SKIP][38] ([i915#3281]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-5/igt@gem_exec_reloc@basic-wc.html * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-mtlp: [PASS][39] -> [TIMEOUT][40] ([i915#7392] / [i915#8628]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-5/igt@gem_exec_whisper@basic-contexts-forked-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-8/igt@gem_exec_whisper@basic-contexts-forked-all.html * igt@gem_fence_thrash@bo-write-verify-y: - shard-mtlp: NOTRUN -> [SKIP][41] ([i915#4860]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-7/igt@gem_fence_thrash@bo-write-verify-y.html * igt@gem_lmem_swapping@heavy-random: - shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4613]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-8/igt@gem_lmem_swapping@heavy-random.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-rkl: NOTRUN -> [SKIP][43] ([i915#4613]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-2/igt@gem_lmem_swapping@heavy-verify-random.html * igt@gem_lmem_swapping@smem-oom@lmem0: - shard-dg1: [PASS][44] -> [DMESG-WARN][45] ([i915#4936] / [i915#5493]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html * igt@gem_media_fill@media-fill: - shard-mtlp: NOTRUN -> [SKIP][46] ([i915#8289]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-2/igt@gem_media_fill@media-fill.html * igt@gem_mmap_gtt@close-race: - shard-dg1: NOTRUN -> [SKIP][47] ([i915#4077]) +2 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-19/igt@gem_mmap_gtt@close-race.html * igt@gem_mmap_gtt@hang-busy: - shard-mtlp: NOTRUN -> [SKIP][48] ([i915#4077]) +5 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-4/igt@gem_mmap_gtt@hang-busy.html * igt@gem_mmap_gtt@zero-extend: - shard-dg2: NOTRUN -> [SKIP][49] ([i915#4077]) +4 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-2/igt@gem_mmap_gtt@zero-extend.html * igt@gem_mmap_wc@coherency: - shard-dg2: NOTRUN -> [SKIP][50] ([i915#4083]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-3/igt@gem_mmap_wc@coherency.html * igt@gem_mmap_wc@read-write: - shard-mtlp: NOTRUN -> [SKIP][51] ([i915#4083]) +3 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-8/igt@gem_mmap_wc@read-write.html * igt@gem_pread@display: - shard-dg2: NOTRUN -> [SKIP][52] ([i915#3282]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-5/igt@gem_pread@display.html - shard-rkl: NOTRUN -> [SKIP][53] ([i915#3282]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@gem_pread@display.html * igt@gem_pxp@verify-pxp-stale-buf-execution: - shard-dg1: NOTRUN -> [SKIP][54] ([i915#4270]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-14/igt@gem_pxp@verify-pxp-stale-buf-execution.html * igt@gem_readwrite@read-write: - shard-dg1: NOTRUN -> [SKIP][55] ([i915#3282]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-18/igt@gem_readwrite@read-write.html - shard-mtlp: NOTRUN -> [SKIP][56] ([i915#3282]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-2/igt@gem_readwrite@read-write.html * igt@gem_render_copy@y-tiled-to-vebox-x-tiled: - shard-mtlp: NOTRUN -> [SKIP][57] ([i915#8428]) +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-5/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled: - shard-dg2: NOTRUN -> [SKIP][58] ([i915#5190]) +7 similar issues [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-2/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html * igt@gem_render_tiled_blits@basic: - shard-mtlp: NOTRUN -> [SKIP][59] ([i915#4079]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-1/igt@gem_render_tiled_blits@basic.html * igt@gem_set_tiling_vs_blt@tiled-to-tiled: - shard-dg2: NOTRUN -> [SKIP][60] ([i915#4079]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-8/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html - shard-rkl: NOTRUN -> [SKIP][61] ([i915#8411]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-4/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html * igt@gem_userptr_blits@set-cache-level: - shard-mtlp: NOTRUN -> [SKIP][62] ([i915#3297]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-2/igt@gem_userptr_blits@set-cache-level.html * igt@gen7_exec_parse@basic-offset: - shard-dg1: NOTRUN -> [SKIP][63] ([fdo#109289]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-12/igt@gen7_exec_parse@basic-offset.html * igt@gen9_exec_parse@bb-secure: - shard-mtlp: NOTRUN -> [SKIP][64] ([i915#2856]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-1/igt@gen9_exec_parse@bb-secure.html * igt@gen9_exec_parse@unaligned-jump: - shard-dg2: NOTRUN -> [SKIP][65] ([i915#2856]) +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-8/igt@gen9_exec_parse@unaligned-jump.html - shard-rkl: NOTRUN -> [SKIP][66] ([i915#2527]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-4/igt@gen9_exec_parse@unaligned-jump.html * igt@i915_pm_dc@dc9-dpms: - shard-tglu: [PASS][67] -> [SKIP][68] ([i915#4281]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-tglu-9/igt@i915_pm_dc@dc9-dpms.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-3/igt@i915_pm_dc@dc9-dpms.html * igt@i915_pm_freq_mult@media-freq@gt0: - shard-dg1: NOTRUN -> [SKIP][69] ([i915#6590]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-14/igt@i915_pm_freq_mult@media-freq@gt0.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a: - shard-rkl: [PASS][70] -> [SKIP][71] ([i915#1937]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html * igt@i915_pm_lpsp@screens-disabled: - shard-dg2: NOTRUN -> [SKIP][72] ([i915#1902]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-6/igt@i915_pm_lpsp@screens-disabled.html * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-dg2: [PASS][73] -> [SKIP][74] ([i915#1397]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-5/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-10/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html * igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-lmem0: - shard-dg1: [PASS][75] -> [FAIL][76] ([i915#7940]) +1 similar issue [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-16/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-lmem0.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-17/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-lmem0.html * igt@i915_pm_rpm@modeset-lpsp-stress: - shard-dg1: [PASS][77] -> [SKIP][78] ([i915#1397]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-19/igt@i915_pm_rpm@modeset-lpsp-stress.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-16/igt@i915_pm_rpm@modeset-lpsp-stress.html * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait: - shard-rkl: [PASS][79] -> [SKIP][80] ([i915#1397]) +1 similar issue [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-mtlp: NOTRUN -> [SKIP][81] ([i915#1397]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-4/igt@i915_pm_rpm@modeset-non-lpsp-stress.html * igt@i915_pm_rps@thresholds-idle-park@gt0: - shard-dg2: NOTRUN -> [SKIP][82] ([i915#8925]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-10/igt@i915_pm_rps@thresholds-idle-park@gt0.html * igt@i915_selftest@live@gt_heartbeat: - shard-apl: [PASS][83] -> [DMESG-FAIL][84] ([i915#5334]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-apl1/igt@i915_selftest@live@gt_heartbeat.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_addfb_basic@invalid-smem-bo-on-discrete: - shard-rkl: NOTRUN -> [SKIP][85] ([i915#3826]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1: - shard-mtlp: [PASS][86] -> [FAIL][87] ([i915#2521]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-8/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-2-y-rc_ccs: - shard-rkl: NOTRUN -> [SKIP][88] ([i915#8502]) +3 similar issues [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-2-y-rc_ccs.html * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y-rc_ccs: - shard-dg1: NOTRUN -> [SKIP][89] ([i915#8502]) +7 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-19/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y-rc_ccs.html * igt@kms_async_flips@crc@pipe-a-hdmi-a-3: - shard-dg2: NOTRUN -> [FAIL][90] ([i915#8247]) +3 similar issues [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-1/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html * igt@kms_big_fb@4-tiled-64bpp-rotate-180: - shard-mtlp: [PASS][91] -> [FAIL][92] ([i915#5138]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-2/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-6/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-rkl: NOTRUN -> [SKIP][93] ([i915#5286]) +1 similar issue [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@x-tiled-8bpp-rotate-270: - shard-mtlp: NOTRUN -> [SKIP][94] ([fdo#111614]) +1 similar issue [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-4/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: - shard-mtlp: [PASS][95] -> [FAIL][96] ([i915#3743]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html * igt@kms_big_fb@yf-tiled-16bpp-rotate-270: - shard-mtlp: NOTRUN -> [SKIP][97] ([fdo#111615]) +2 similar issues [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-1/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-0: - shard-dg2: NOTRUN -> [SKIP][98] ([i915#4538] / [i915#5190]) +1 similar issue [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-5/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html - shard-rkl: NOTRUN -> [SKIP][99] ([fdo#110723]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html - shard-tglu: NOTRUN -> [SKIP][100] ([fdo#111615]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-8/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html * igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_mc_ccs: - shard-tglu: NOTRUN -> [SKIP][101] ([i915#5354] / [i915#6095]) +4 similar issues [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-4/igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_mc_ccs.html * igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_rc_ccs_cc: - shard-snb: NOTRUN -> [SKIP][102] ([fdo#109271]) +94 similar issues [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-snb2/igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_rc_ccs_cc.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs: - shard-dg2: NOTRUN -> [SKIP][103] ([i915#3689] / [i915#5354]) +7 similar issues [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs.html - shard-rkl: NOTRUN -> [SKIP][104] ([i915#3734] / [i915#5354] / [i915#6095]) +1 similar issue [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-4/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs.html - shard-tglu: NOTRUN -> [SKIP][105] ([i915#3689] / [i915#5354] / [i915#6095]) +1 similar issue [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-3/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs.html * igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs_cc: - shard-rkl: NOTRUN -> [SKIP][106] ([i915#5354] / [i915#6095]) +2 similar issues [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs_cc.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: - shard-mtlp: NOTRUN -> [SKIP][107] ([i915#3886] / [i915#6095]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: - shard-mtlp: NOTRUN -> [SKIP][108] ([i915#3886] / [i915#5354] / [i915#6095]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-6/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs: - shard-dg1: NOTRUN -> [SKIP][109] ([i915#3689] / [i915#5354] / [i915#6095]) +1 similar issue [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-15/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-4_tiled_mtl_rc_ccs: - shard-dg1: NOTRUN -> [SKIP][110] ([i915#5354] / [i915#6095]) +1 similar issue [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-14/igt@kms_ccs@pipe-b-ccs-on-another-bo-4_tiled_mtl_rc_ccs.html * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs: - shard-mtlp: NOTRUN -> [SKIP][111] ([i915#6095]) +9 similar issues [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-4/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs.html * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs: - shard-dg1: NOTRUN -> [SKIP][112] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-15/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-dg2: NOTRUN -> [SKIP][113] ([i915#3689] / [i915#3886] / [i915#5354]) +1 similar issue [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-10/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs: - shard-rkl: NOTRUN -> [SKIP][114] ([i915#5354]) +8 similar issues [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs: - shard-tglu: NOTRUN -> [SKIP][115] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-4/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs.html * igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][116] ([i915#4087]) +3 similar issues [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-5/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html * igt@kms_chamelium_color@degamma: - shard-mtlp: NOTRUN -> [SKIP][117] ([fdo#111827]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-4/igt@kms_chamelium_color@degamma.html * igt@kms_chamelium_edid@dp-edid-resolution-list: - shard-dg2: NOTRUN -> [SKIP][118] ([i915#7828]) +1 similar issue [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@kms_chamelium_edid@dp-edid-resolution-list.html * igt@kms_chamelium_edid@dp-mode-timings: - shard-dg1: NOTRUN -> [SKIP][119] ([i915#7828]) [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-19/igt@kms_chamelium_edid@dp-mode-timings.html * igt@kms_chamelium_edid@vga-edid-read: - shard-mtlp: NOTRUN -> [SKIP][120] ([i915#7828]) +1 similar issue [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-4/igt@kms_chamelium_edid@vga-edid-read.html * igt@kms_chamelium_hpd@vga-hpd-fast: - shard-rkl: NOTRUN -> [SKIP][121] ([i915#7828]) +2 similar issues [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-6/igt@kms_chamelium_hpd@vga-hpd-fast.html - shard-tglu: NOTRUN -> [SKIP][122] ([i915#7828]) +1 similar issue [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-9/igt@kms_chamelium_hpd@vga-hpd-fast.html * igt@kms_content_protection@atomic-dpms: - shard-mtlp: NOTRUN -> [SKIP][123] ([i915#6944]) [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-3/igt@kms_content_protection@atomic-dpms.html * igt@kms_cursor_crc@cursor-onscreen-32x10: - shard-dg2: NOTRUN -> [SKIP][124] ([i915#3555]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-8/igt@kms_cursor_crc@cursor-onscreen-32x10.html - shard-rkl: NOTRUN -> [SKIP][125] ([i915#3555]) [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-1/igt@kms_cursor_crc@cursor-onscreen-32x10.html * igt@kms_cursor_crc@cursor-onscreen-512x512: - shard-dg1: NOTRUN -> [SKIP][126] ([i915#3359]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-18/igt@kms_cursor_crc@cursor-onscreen-512x512.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-mtlp: [PASS][127] -> [FAIL][128] ([i915#8248]) [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-5/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-dg2: NOTRUN -> [SKIP][129] ([fdo#109274] / [i915#5354]) [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [PASS][130] -> [FAIL][131] ([i915#2346]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html - shard-apl: [PASS][132] -> [FAIL][133] ([i915#2346]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@2x-flip-vs-suspend: - shard-mtlp: NOTRUN -> [SKIP][134] ([i915#3637]) +2 similar issues [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-4/igt@kms_flip@2x-flip-vs-suspend.html * igt@kms_flip@2x-plain-flip-ts-check: - shard-dg2: NOTRUN -> [SKIP][135] ([fdo#109274]) +1 similar issue [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-6/igt@kms_flip@2x-plain-flip-ts-check.html - shard-rkl: NOTRUN -> [SKIP][136] ([fdo#111825]) +2 similar issues [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@kms_flip@2x-plain-flip-ts-check.html - shard-tglu: NOTRUN -> [SKIP][137] ([fdo#109274] / [i915#3637]) [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-9/igt@kms_flip@2x-plain-flip-ts-check.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-apl: [PASS][138] -> [ABORT][139] ([i915#180]) [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_flip@flip-vs-suspend@b-hdmi-a1: - shard-snb: NOTRUN -> [DMESG-WARN][140] ([i915#8841]) +6 similar issues [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-snb1/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode: - shard-dg2: NOTRUN -> [SKIP][141] ([i915#2672]) [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html - shard-rkl: NOTRUN -> [SKIP][142] ([i915#2672]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][143] ([i915#2672]) +2 similar issues [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-mtlp: NOTRUN -> [SKIP][144] ([i915#8708]) +3 similar issues [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw: - shard-dg1: NOTRUN -> [SKIP][145] ([fdo#111825]) +5 similar issues [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-dg2: NOTRUN -> [SKIP][146] ([i915#8708]) +5 similar issues [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html - shard-rkl: NOTRUN -> [SKIP][147] ([fdo#111825] / [i915#1825]) +10 similar issues [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html - shard-tglu: NOTRUN -> [SKIP][148] ([fdo#109280]) +4 similar issues [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render: - shard-mtlp: NOTRUN -> [SKIP][149] ([i915#1825]) +6 similar issues [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary: - shard-dg2: [PASS][150] -> [FAIL][151] ([i915#6880]) +1 similar issue [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu: - shard-dg1: NOTRUN -> [SKIP][152] ([i915#3458]) [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4: - shard-dg1: NOTRUN -> [SKIP][153] ([i915#5439]) [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc: - shard-dg1: NOTRUN -> [SKIP][154] ([i915#8708]) [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite: - shard-dg2: NOTRUN -> [SKIP][155] ([i915#3458]) +5 similar issues [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-pwrite: - shard-dg2: NOTRUN -> [SKIP][156] ([i915#5354]) +18 similar issues [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt: - shard-rkl: NOTRUN -> [SKIP][157] ([i915#3023]) +4 similar issues [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html - shard-tglu: NOTRUN -> [SKIP][158] ([fdo#110189]) +1 similar issue [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html * igt@kms_hdr@bpc-switch: - shard-dg2: NOTRUN -> [SKIP][159] ([i915#3555] / [i915#8228]) [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-10/igt@kms_hdr@bpc-switch.html * igt@kms_hdr@bpc-switch-dpms: - shard-rkl: NOTRUN -> [SKIP][160] ([i915#3555] / [i915#8228]) +1 similar issue [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_multipipe_modeset@basic-max-pipe-crc-check: - shard-dg1: NOTRUN -> [SKIP][161] ([i915#1839]) [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-18/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes: - shard-mtlp: NOTRUN -> [SKIP][162] ([fdo#109289]) +2 similar issues [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-7/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: - shard-dg2: [PASS][163] -> [FAIL][164] ([fdo#103375]) +1 similar issue [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-11/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html * igt@kms_plane_lowres@tiling-x@pipe-c-edp-1: - shard-mtlp: NOTRUN -> [SKIP][165] ([i915#3582]) +3 similar issues [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-6/igt@kms_plane_lowres@tiling-x@pipe-c-edp-1.html * igt@kms_plane_multiple@tiling-y: - shard-dg2: NOTRUN -> [SKIP][166] ([i915#8806]) [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-2/igt@kms_plane_multiple@tiling-y.html * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][167] ([i915#5176]) +7 similar issues [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1.html * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][168] ([i915#5176]) +3 similar issues [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-6/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-3.html * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-3: - shard-dg1: NOTRUN -> [SKIP][169] ([i915#5176]) +11 similar issues [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-13/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-3.html * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-d-hdmi-a-1: - shard-tglu: NOTRUN -> [SKIP][170] ([i915#5176]) +3 similar issues [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-4/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-d-hdmi-a-1.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a-hdmi-a-2: - shard-dg2: NOTRUN -> [SKIP][171] ([i915#5235]) +7 similar issues [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a-hdmi-a-2.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2: - shard-rkl: NOTRUN -> [SKIP][172] ([i915#5235]) +5 similar issues [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1: - shard-dg1: NOTRUN -> [SKIP][173] ([i915#5235]) +19 similar issues [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-19/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1: - shard-mtlp: NOTRUN -> [SKIP][174] ([i915#5235]) +3 similar issues [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-5/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1.html * igt@kms_prime@basic-crc-hybrid: - shard-dg2: NOTRUN -> [SKIP][175] ([i915#6524] / [i915#6805]) [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-5/igt@kms_prime@basic-crc-hybrid.html - shard-rkl: NOTRUN -> [SKIP][176] ([i915#6524]) [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-6/igt@kms_prime@basic-crc-hybrid.html - shard-tglu: NOTRUN -> [SKIP][177] ([i915#6524]) [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-4/igt@kms_prime@basic-crc-hybrid.html * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf: - shard-dg2: NOTRUN -> [SKIP][178] ([i915#658]) [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-8/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html - shard-rkl: NOTRUN -> [SKIP][179] ([i915#658]) [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-1/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html * igt@kms_psr@cursor_mmap_gtt: - shard-rkl: NOTRUN -> [SKIP][180] ([i915#1072]) +1 similar issue [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-6/igt@kms_psr@cursor_mmap_gtt.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-dg2: NOTRUN -> [SKIP][181] ([i915#1072]) +2 similar issues [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_psr@sprite_mmap_gtt: - shard-dg1: NOTRUN -> [SKIP][182] ([i915#1072]) [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-18/igt@kms_psr@sprite_mmap_gtt.html * igt@kms_selftest@drm_dp_mst: - shard-dg1: NOTRUN -> [SKIP][183] ([i915#8661]) [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-17/igt@kms_selftest@drm_dp_mst.html * igt@kms_setmode@basic@pipe-a-vga-1: - shard-snb: NOTRUN -> [FAIL][184] ([i915#5465]) +1 similar issue [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-snb6/igt@kms_setmode@basic@pipe-a-vga-1.html * igt@kms_tiled_display@basic-test-pattern: - shard-dg2: NOTRUN -> [SKIP][185] ([i915#8623]) +1 similar issue [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-5/igt@kms_tiled_display@basic-test-pattern.html * igt@kms_tiled_display@basic-test-pattern-with-chamelium: - shard-rkl: NOTRUN -> [SKIP][186] ([i915#8623]) +1 similar issue [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html - shard-tglu: NOTRUN -> [SKIP][187] ([i915#8623]) [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html * igt@kms_writeback@writeback-pixel-formats: - shard-dg2: NOTRUN -> [SKIP][188] ([i915#2437]) [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@kms_writeback@writeback-pixel-formats.html * igt@perf@unprivileged-single-ctx-counters: - shard-dg1: NOTRUN -> [SKIP][189] ([fdo#109289] / [i915#2433]) [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-15/igt@perf@unprivileged-single-ctx-counters.html * igt@perf_pmu@event-wait@rcs0: - shard-dg2: NOTRUN -> [SKIP][190] ([fdo#112283]) [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@perf_pmu@event-wait@rcs0.html - shard-rkl: NOTRUN -> [SKIP][191] ([fdo#112283]) [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-4/igt@perf_pmu@event-wait@rcs0.html - shard-tglu: NOTRUN -> [SKIP][192] ([fdo#112283]) [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-3/igt@perf_pmu@event-wait@rcs0.html * igt@perf_pmu@faulting-read@gtt: - shard-mtlp: NOTRUN -> [SKIP][193] ([i915#8440]) [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-1/igt@perf_pmu@faulting-read@gtt.html * igt@sysfs_heartbeat_interval@mixed@ccs0: - shard-mtlp: [PASS][194] -> [ABORT][195] ([i915#8552]) [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-6/igt@sysfs_heartbeat_interval@mixed@ccs0.html [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-3/igt@sysfs_heartbeat_interval@mixed@ccs0.html * igt@sysfs_heartbeat_interval@mixed@vecs0: - shard-mtlp: [PASS][196] -> [FAIL][197] ([i915#1731]) [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-6/igt@sysfs_heartbeat_interval@mixed@vecs0.html [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-3/igt@sysfs_heartbeat_interval@mixed@vecs0.html * igt@sysfs_preempt_timeout@timeout@vecs0: - shard-mtlp: [PASS][198] -> [ABORT][199] ([i915#8521]) [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-2/igt@sysfs_preempt_timeout@timeout@vecs0.html [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-7/igt@sysfs_preempt_timeout@timeout@vecs0.html * igt@v3d/v3d_submit_cl@bad-bo: - shard-mtlp: NOTRUN -> [SKIP][200] ([i915#2575]) +3 similar issues [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-8/igt@v3d/v3d_submit_cl@bad-bo.html * igt@v3d/v3d_submit_cl@bad-extension: - shard-tglu: NOTRUN -> [SKIP][201] ([fdo#109315] / [i915#2575]) [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-5/igt@v3d/v3d_submit_cl@bad-extension.html * igt@v3d/v3d_submit_csd@bad-flag: - shard-dg1: NOTRUN -> [SKIP][202] ([i915#2575]) +1 similar issue [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-14/igt@v3d/v3d_submit_csd@bad-flag.html * igt@v3d/v3d_submit_csd@multiple-job-submission: - shard-dg2: NOTRUN -> [SKIP][203] ([i915#2575]) +2 similar issues [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@v3d/v3d_submit_csd@multiple-job-submission.html - shard-rkl: NOTRUN -> [SKIP][204] ([fdo#109315]) +1 similar issue [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-1/igt@v3d/v3d_submit_csd@multiple-job-submission.html * igt@vc4/vc4_perfmon@create-perfmon-exceed: - shard-dg1: NOTRUN -> [SKIP][205] ([i915#7711]) [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-15/igt@vc4/vc4_perfmon@create-perfmon-exceed.html * igt@vc4/vc4_tiling@set-bad-modifier: - shard-dg2: NOTRUN -> [SKIP][206] ([i915#7711]) +1 similar issue [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@vc4/vc4_tiling@set-bad-modifier.html - shard-rkl: NOTRUN -> [SKIP][207] ([i915#7711]) +1 similar issue [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-1/igt@vc4/vc4_tiling@set-bad-modifier.html * igt@vc4/vc4_wait_seqno@bad-seqno-1ns: - shard-mtlp: NOTRUN -> [SKIP][208] ([i915#7711]) [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-8/igt@vc4/vc4_wait_seqno@bad-seqno-1ns.html #### Possible fixes #### * igt@drm_fdinfo@most-busy-idle-check-all@rcs0: - shard-rkl: [FAIL][209] ([i915#7742]) -> [PASS][210] [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html * igt@gem_create@create-ext-cpu-access-big: - shard-dg2: [ABORT][211] ([i915#7461]) -> [PASS][212] [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-11/igt@gem_create@create-ext-cpu-access-big.html [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-1/igt@gem_create@create-ext-cpu-access-big.html * igt@gem_ctx_persistence@engines-hostile@vcs0: - shard-mtlp: [FAIL][213] ([i915#2410]) -> [PASS][214] +2 similar issues [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-6/igt@gem_ctx_persistence@engines-hostile@vcs0.html [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-4/igt@gem_ctx_persistence@engines-hostile@vcs0.html * igt@gem_eio@hibernate: - shard-tglu: [ABORT][215] ([i915#7975] / [i915#8213] / [i915#8398]) -> [PASS][216] [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-tglu-10/igt@gem_eio@hibernate.html [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-5/igt@gem_eio@hibernate.html * igt@gem_eio@kms: - shard-dg1: [FAIL][217] ([i915#5784]) -> [PASS][218] [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-15/igt@gem_eio@kms.html [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-14/igt@gem_eio@kms.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [FAIL][219] ([i915#2842]) -> [PASS][220] [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-glk7/igt@gem_exec_fair@basic-none-share@rcs0.html [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [FAIL][221] ([i915#2842]) -> [PASS][222] [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglu: [FAIL][223] ([i915#2842]) -> [PASS][224] [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-rkl: [FAIL][225] ([i915#2842]) -> [PASS][226] [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-rkl-7/igt@gem_exec_fair@basic-pace-solo@rcs0.html [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_lmem_swapping@smem-oom@lmem0: - shard-dg2: [TIMEOUT][227] ([i915#5493]) -> [PASS][228] [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-8/igt@gem_lmem_swapping@smem-oom@lmem0.html [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-5/igt@gem_lmem_swapping@smem-oom@lmem0.html * igt@gem_userptr_blits@nohangcheck: - shard-mtlp: [FAIL][229] -> [PASS][230] [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-4/igt@gem_userptr_blits@nohangcheck.html [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-3/igt@gem_userptr_blits@nohangcheck.html * igt@i915_hangman@engine-engine-error@vcs0: - shard-mtlp: [FAIL][231] ([i915#7069]) -> [PASS][232] +1 similar issue [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-4/igt@i915_hangman@engine-engine-error@vcs0.html [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-2/igt@i915_hangman@engine-engine-error@vcs0.html * igt@i915_module_load@reload-with-fault-injection: - shard-mtlp: [ABORT][233] ([i915#8489] / [i915#8668]) -> [PASS][234] [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-4/igt@i915_module_load@reload-with-fault-injection.html [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-2/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_pm_dc@dc9-dpms: - shard-apl: [SKIP][235] ([fdo#109271]) -> [PASS][236] [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-apl4/igt@i915_pm_dc@dc9-dpms.html [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-apl7/igt@i915_pm_dc@dc9-dpms.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-dg1: [FAIL][237] ([i915#3591]) -> [PASS][238] +1 similar issue [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@i915_pm_rpm@cursor-dpms: - shard-tglu: [FAIL][239] ([i915#7940]) -> [PASS][240] +2 similar issues [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-tglu-3/igt@i915_pm_rpm@cursor-dpms.html [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-2/igt@i915_pm_rpm@cursor-dpms.html * igt@i915_pm_rpm@dpms-lpsp: - shard-rkl: [SKIP][241] ([i915#1397]) -> [PASS][242] +1 similar issue [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-rkl-4/igt@i915_pm_rpm@dpms-lpsp.html [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@i915_pm_rpm@dpms-lpsp.html * igt@i915_pm_rpm@gem-execbuf-stress@smem0: - shard-dg1: [FAIL][243] ([i915#7940]) -> [PASS][244] [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-16/igt@i915_pm_rpm@gem-execbuf-stress@smem0.html [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-17/igt@i915_pm_rpm@gem-execbuf-stress@smem0.html * igt@i915_selftest@live@requests: - shard-mtlp: [DMESG-FAIL][245] ([i915#8497]) -> [PASS][246] [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-4/igt@i915_selftest@live@requests.html [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-6/igt@i915_selftest@live@requests.html * igt@i915_selftest@live@slpc: - shard-mtlp: [DMESG-WARN][247] ([i915#6367]) -> [PASS][248] [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-4/igt@i915_selftest@live@slpc.html [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-6/igt@i915_selftest@live@slpc.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-mtlp: [FAIL][249] ([i915#3743]) -> [PASS][250] [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html * igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][251] ([i915#79]) -> [PASS][252] [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-suspend@a-hdmi-a3: - shard-dg2: [FAIL][253] ([fdo#103375]) -> [PASS][254] +4 similar issues [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-5/igt@kms_flip@flip-vs-suspend@a-hdmi-a3.html [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-8/igt@kms_flip@flip-vs-suspend@a-hdmi-a3.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: - shard-dg2: [FAIL][255] ([i915#6880]) -> [PASS][256] [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html * igt@kms_plane@pixel-format-source-clamping@pipe-b-planes: - shard-mtlp: [FAIL][257] ([i915#1623]) -> [PASS][258] [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-7/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-4/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1: - shard-tglu: [FAIL][259] ([i915#8292]) -> [PASS][260] [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-tglu-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-3/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html * igt@kms_sysfs_edid_timing: - shard-dg2: [FAIL][261] ([IGT#2]) -> [PASS][262] [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-1/igt@kms_sysfs_edid_timing.html [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@kms_sysfs_edid_timing.html * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend: - shard-mtlp: [ABORT][263] -> [PASS][264] [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-6/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html * igt@perf@non-zero-reason@0-rcs0: - shard-dg2: [FAIL][265] ([i915#7484]) -> [PASS][266] [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-8/igt@perf@non-zero-reason@0-rcs0.html [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-3/igt@perf@non-zero-reason@0-rcs0.html * igt@perf_pmu@most-busy-idle-check-all@rcs0: - shard-dg2: [FAIL][267] ([i915#5234]) -> [PASS][268] [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-5/igt@perf_pmu@most-busy-idle-check-all@rcs0.html [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-2/igt@perf_pmu@most-busy-idle-check-all@rcs0.html #### Warnings #### * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-tglu: [WARN][269] ([i915#2681]) -> [FAIL][270] ([i915#2681] / [i915#3591]) [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-tglu-9/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-tglu-2/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@i915_pm_rpm@i2c: - shard-dg1: [DMESG-WARN][271] ([i915#4391]) -> [DMESG-WARN][272] ([i915#4391] / [i915#4423]) [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-19/igt@i915_pm_rpm@i2c.html [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-16/igt@i915_pm_rpm@i2c.html * igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_dg2_mc_ccs: - shard-snb: [ABORT][273] -> [SKIP][274] ([fdo#109271]) [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-snb7/igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_dg2_mc_ccs.html [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-snb2/igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_dg2_mc_ccs.html * igt@kms_content_protection@content_type_change: - shard-dg2: [SKIP][275] ([i915#7118] / [i915#7162]) -> [SKIP][276] ([i915#7118]) [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-11/igt@kms_content_protection@content_type_change.html [276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-2/igt@kms_content_protection@content_type_change.html * igt@kms_content_protection@mei_interface: - shard-dg1: [SKIP][277] ([fdo#109300]) -> [SKIP][278] ([i915#7116]) [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-13/igt@kms_content_protection@mei_interface.html [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-19/igt@kms_content_protection@mei_interface.html * igt@kms_content_protection@type1: - shard-dg2: [SKIP][279] ([i915#7118]) -> [SKIP][280] ([i915#7118] / [i915#7162]) [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg2-3/igt@kms_content_protection@type1.html [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg2-11/igt@kms_content_protection@type1.html * igt@kms_fbcon_fbt@psr: - shard-rkl: [SKIP][281] ([fdo#110189] / [i915#3955]) -> [SKIP][282] ([i915#3955]) [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-rkl-1/igt@kms_fbcon_fbt@psr.html [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-rkl-7/igt@kms_fbcon_fbt@psr.html * igt@kms_psr@cursor_plane_move: - shard-dg1: [SKIP][283] ([i915#1072] / [i915#4078]) -> [SKIP][284] ([i915#1072]) +1 similar issue [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-12/igt@kms_psr@cursor_plane_move.html [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-15/igt@kms_psr@cursor_plane_move.html * igt@kms_psr@primary_mmap_gtt: - shard-dg1: [SKIP][285] ([i915#1072]) -> [SKIP][286] ([i915#1072] / [i915#4078]) [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-dg1-14/igt@kms_psr@primary_mmap_gtt.html [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-dg1-18/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@coherency-blt: - shard-mtlp: [DMESG-FAIL][287] ([i915#1982]) -> [FAIL][288] ([i915#8445]) [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13475/shard-mtlp-4/igt@prime_vgem@coherency-blt.html [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/shard-mtlp-3/igt@prime_vgem@coherency-blt.html [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1623]: https://gitlab.freedesktop.org/drm/intel/issues/1623 [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902 [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410 [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423 [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936 [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122 [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5251]: https://gitlab.freedesktop.org/drm/intel/issues/5251 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465 [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590 [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805 [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880 [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944 [i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 [i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162 [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392 [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461 [i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484 [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940 [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975 [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213 [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228 [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247 [i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248 [i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289 [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292 [i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398 [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411 [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414 [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428 [i915#8440]: https://gitlab.freedesktop.org/drm/intel/issues/8440 [i915#8445]: https://gitlab.freedesktop.org/drm/intel/issues/8445 [i915#8489]: https://gitlab.freedesktop.org/drm/intel/issues/8489 [i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497 [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502 [i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521 [i915#8552]: https://gitlab.freedesktop.org/drm/intel/issues/8552 [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555 [i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623 [i915#8628]: https://gitlab.freedesktop.org/drm/intel/issues/8628 [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708 [i915#8806]: https://gitlab.freedesktop.org/drm/intel/issues/8806 [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841 [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7414 -> IGTPW_9518 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_13475: ae4f66974d076e3729337ffd1caf1316969916ef @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_9518: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/index.html IGT_7414: 056c9d7f2a63dd6d0b9b6462b4ab1b096178dcc6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9518/index.html [-- Attachment #2: Type: text/html, Size: 85891 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-08-09 11:23 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-08-04 10:24 [igt-dev] [PATCH i-g-t 0/2] lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin Marcin Bernatowicz 2023-08-04 10:24 ` [igt-dev] [PATCH i-g-t 1/2] " Marcin Bernatowicz 2023-08-07 6:54 ` Zbigniew Kempczyński 2023-08-07 13:38 ` Bernatowicz, Marcin 2023-08-07 14:10 ` Kamil Konieczny 2023-08-04 10:24 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe_spin_batch: spin-fixed-duration Marcin Bernatowicz 2023-08-07 6:56 ` Zbigniew Kempczyński 2023-08-07 14:13 ` Bernatowicz, Marcin 2023-08-09 11:23 ` Zbigniew Kempczyński 2023-08-04 13:41 ` [igt-dev] ✓ Fi.CI.BAT: success for lib/xe_spin: introduced xe_spin_opts; fixed duration xe_spin Patchwork 2023-08-04 14:13 ` [igt-dev] ○ CI.xeBAT: info " Patchwork 2023-08-04 20:13 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
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