[igt-dev] [PATCH i-g-t 0/8] Add a new IGT test to validate DC3CO state.

[igt-dev] [PATCH i-g-t 0/8] Add a new IGT test to validate DC3CO state.

[Jeevan B]

This test is creating a vpb scenario for
selective frame update and validating 
that DC state stays in DC3CO during execution.
Sending this patch on top of /series/56713
as IGT for existing DC states (DC5/DC6) is still not merged.   
Patches:
igt/i915/i915_pm_dc: DC3CO PSR2 helpers
igt/i915/i915_pm_dc: DC3CO Video Playback Case IGT test
Only above two patches require review. 

Anshuman Gupta (2):
  tests/i915/i915_pm_dc:Skip the DC6 test if BIOS has disabled PC8+
  igt/i915/i915_pm_dc: DC3CO PSR2 helpers

Jeevan B (1):
  igt/i915/i915_pm_dc: DC3CO Video Playback Case IGT test

Jyoti Yadav (5):
  lib/igt_pm: igt lib helper routines to support DC5/6 tests
  tests/i915/i915_pm_dc: Added new test to verify Display C States
  tests/i915/i915_pm_dc: Added test for DC6 during PSR
  tests/i915/i915_pm_dc: Added test for DC5 during DPMS
  tests/i915/i915_pm_dc: Added test for DC6 during DPMS

 lib/igt_pm.c                   | 215 ++++++++++++++----
 lib/igt_pm.h                   |   7 +-
 tests/Makefile.sources         |   3 +
 tests/i915/i915_pm_backlight.c |   6 +-
 tests/i915/i915_pm_dc.c        | 489 +++++++++++++++++++++++++++++++++++++++++
 tests/i915/i915_pm_rpm.c       |  39 +---
 tests/meson.build              |   1 +
 7 files changed, 672 insertions(+), 88 deletions(-)
 create mode 100644 tests/i915/i915_pm_dc.c

-- 
2.7.4

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[igt-dev] [PATCH i-g-t 1/8] lib/igt_pm: igt lib helper routines to support DC5/6 tests

[Jeevan B]

From: Jyoti Yadav <jyoti.r.yadav@intel.com>

This patch does the following changes to lib/igt_pm.c

-dmc_loaded() will be used by new test i915_pm_dc.c which will validate
 Display C States. So moving the same to igt_pm library.

-Introduced igt_disable_runtime_pm() in order to disable runtime suspend
 for the function which support dc9.

-Changed the igt_pm_enable_sata_link_power_management() and
 igt_pm_restore_sata_link_power_management() in order to save
 and restore the sata link power policy by an exit handler.

v2: Simplify the comment section.
v3: Remove . from the subject line.
v4: Rebased, resolve conflicts in pm_rpm.c
    Included patch set version change log.
v5: Listing actual change in patch set changelog to make review easier.
v6: igt's lib added support for disabling runtime suspend,
    change in commit log. rebased due to test name pm_rpm changed
    to i915_pm_rpm.
v7: Addressed review comment by saving POWER_DIR values in
    igt_disable_runtime_pm(). [Imre]
v8: Addressed the review comment, igt_pm_enable_sata_link_power_management
    function to restore the original SATA link power policy if things fail
    by using an exit handler. [Imre]
v9: IGT failure fixture in i915_pm_backlight and i915_pm_rpm.
v10:Review comment fixup in sata_link_power_management
    lib functions. [Imre]
v11:Add igt_assert_fd(pm_status_fd) in igt_disable_runtime_pm().
    [Imre & Petri]
v12: Refactor is_bios_limits_pc8_plus_residencies() from
     supports_pc8_plus_residencies().
     Changed igt_disable_runtime_pm()return type. [Imre]

Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 lib/igt_pm.c                   | 215 ++++++++++++++++++++++++++++++++---------
 lib/igt_pm.h                   |   7 +-
 tests/i915/i915_pm_backlight.c |   6 +-
 tests/i915/i915_pm_rpm.c       |  39 +-------
 4 files changed, 179 insertions(+), 88 deletions(-)

diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index fd22273..540a9f9 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -38,6 +38,7 @@
 #include "drmtest.h"
 #include "igt_pm.h"
 #include "igt_aux.h"
+#include "igt_sysfs.h"
 
 /**
  * SECTION:igt_pm
@@ -58,16 +59,30 @@ enum {
 	POLICY_MIN_POWER = 2
 };
 
+#define MSR_PKG_CST_CONFIG_CONTROL	0xE2
+/*
+ * Below PKG CST limit mask and PC8 bits are meant for
+ * HSW,BDW SKL,ICL and Goldmont Microarch and future platforms.
+ * Refer IA S/W developers manual vol3c part3 chapter:35
+ */
+#define  PKG_CST_LIMIT_MASK		0xF
+#define  PKG_CST_LIMIT_C8		0x6
+
 #define MAX_PERFORMANCE_STR	"max_performance\n"
 #define MEDIUM_POWER_STR	"medium_power\n"
 #define MIN_POWER_STR		"min_power\n"
 /* Remember to fix this if adding longer strings */
 #define MAX_POLICY_STRLEN	strlen(MAX_PERFORMANCE_STR)
+int8_t *__sata_pm_policies;
+int __scsi_host_cnt;
 
 static char __igt_pm_audio_runtime_power_save[64];
 static char * __igt_pm_audio_runtime_control_path;
 static char __igt_pm_audio_runtime_control[64];
 
+static void __igt_pm_sata_link_pm_exit_handler(int sig);
+static void __igt_pm_restore_sata_link_power_management(void);
+
 static int __igt_pm_audio_restore_runtime_pm(void)
 {
 	int fd;
@@ -280,39 +295,26 @@ void igt_pm_enable_audio_runtime_pm(void)
 		igt_debug("Failed to enable audio runtime PM! (%d)\n", -err);
 }
 
-/**
- * igt_pm_enable_sata_link_power_management:
- *
- * Enable the min_power policy for SATA link power management.
- * Without this we cannot reach deep runtime power states.
- *
- * We don't have any assertions on open since the system might not have
- * a SATA host.
- *
- * Returns:
- * An opaque pointer to the data needed to restore the default values
- * after the test has terminated, or NULL if SATA link power management
- * is not supported. This pointer should be freed when no longer used
- * (typically after having called restore_sata_link_power_management()).
- */
-int8_t *igt_pm_enable_sata_link_power_management(void)
+static void __igt_pm_enable_sata_link_power_management(void)
 {
 	int fd, i;
 	ssize_t len;
 	char *buf;
 	char *file_name;
-	int8_t *link_pm_policies = NULL;
+	int8_t policy;
 
 	file_name = malloc(PATH_MAX);
 	buf = malloc(MAX_POLICY_STRLEN + 1);
 
-	for (i = 0; ; i++) {
-		int8_t policy;
-
+	for (__scsi_host_cnt = 0; ; __scsi_host_cnt++) {
 		snprintf(file_name, PATH_MAX,
 			 "/sys/class/scsi_host/host%d/link_power_management_policy",
-			 i);
+			 __scsi_host_cnt);
 
+		/*
+		 * We don't have any assertions on open since the system
+		 * might not have a SATA host.
+		 */
 		fd = open(file_name, O_RDWR);
 		if (fd < 0)
 			break;
@@ -332,12 +334,26 @@ int8_t *igt_pm_enable_sata_link_power_management(void)
 		else
 			policy = POLICY_UNKNOWN;
 
-		if (!(i % 256))
-			link_pm_policies = realloc(link_pm_policies,
-						   (i / 256 + 1) * 256 + 1);
+		if (!(__scsi_host_cnt % 256))
+			__sata_pm_policies = realloc(__sata_pm_policies,
+						     (__scsi_host_cnt / 256 + 1)
+						     * 256 + 1);
+
+		__sata_pm_policies[__scsi_host_cnt] = policy;
+		close(fd);
+	}
+
+	igt_install_exit_handler(__igt_pm_sata_link_pm_exit_handler);
+
+	for (i = 0; i < __scsi_host_cnt; i++) {
+		snprintf(file_name, PATH_MAX,
+			 "/sys/class/scsi_host/host%d/link_power_management_policy",
+			 i);
+		fd = open(file_name, O_RDWR);
+		if (fd < 0)
+			break;
 
-		link_pm_policies[i] = policy;
-		link_pm_policies[i + 1] = 0;
+		policy = __sata_pm_policies[i];
 
 		/* If the policy is something we don't know about,
 		 * don't touch it, since we might potentially break things.
@@ -355,39 +371,25 @@ int8_t *igt_pm_enable_sata_link_power_management(void)
 	}
 	free(buf);
 	free(file_name);
-
-	return link_pm_policies;
 }
 
-/**
- * igt_pm_restore_sata_link_power_management:
- * @pm_data: An opaque pointer with saved link PM policies;
- *           If NULL is passed we force enable the "max_performance" policy.
- *
- * Restore the link power management policies to the values
- * prior to enabling min_power.
- *
- * Caveat: If the system supports hotplugging and hotplugging takes
- *         place during our testing so that the hosts change numbers
- *         we might restore the settings to the wrong hosts.
- */
-void igt_pm_restore_sata_link_power_management(int8_t *pm_data)
-
+static void __igt_pm_restore_sata_link_power_management(void)
 {
 	int fd, i;
 	char *file_name;
 
+	if (!__sata_pm_policies)
+		return;
+
 	/* Disk runtime PM policies. */
 	file_name = malloc(PATH_MAX);
-	for (i = 0; ; i++) {
+	for (i = 0; i < __scsi_host_cnt; i++) {
 		int8_t policy;
 
-		if (!pm_data)
-			policy = POLICY_MAX_PERFORMANCE;
-		else if (pm_data[i] == POLICY_UNKNOWN)
+		if (__sata_pm_policies[i] == POLICY_UNKNOWN)
 			continue;
 		else
-			policy = pm_data[i];
+			policy = __sata_pm_policies[i];
 
 		snprintf(file_name, PATH_MAX,
 			 "/sys/class/scsi_host/host%d/link_power_management_policy",
@@ -421,7 +423,48 @@ void igt_pm_restore_sata_link_power_management(int8_t *pm_data)
 		close(fd);
 	}
 	free(file_name);
+	free(__sata_pm_policies);
+	__sata_pm_policies = NULL;
 }
+
+/**
+ * igt_pm_enable_sata_link_power_management:
+ *
+ * Enable the min_power policy for SATA link power management.
+ * Without this we cannot reach deep runtime power states.
+ */
+void igt_pm_enable_sata_link_power_management(void)
+{
+	/* Check if has been already saved. */
+	if (__sata_pm_policies)
+		return;
+
+	 __igt_pm_enable_sata_link_power_management();
+}
+
+/**
+ * igt_pm_restore_sata_link_power_management:
+ *
+ * Restore the link power management policies to the values
+ * prior to enabling min_power.
+ *
+ * Caveat: If the system supports hotplugging and hotplugging takes
+ *         place during our testing so that the hosts change numbers
+ *         we might restore the settings to the wrong hosts.
+ */
+void igt_pm_restore_sata_link_power_management(void)
+{
+	if (!__sata_pm_policies)
+		return;
+
+	 __igt_pm_restore_sata_link_power_management();
+}
+
+static void __igt_pm_sata_link_pm_exit_handler(int sig)
+{
+	__igt_pm_restore_sata_link_power_management();
+}
+
 #define POWER_DIR "/sys/devices/pci0000:00/0000:00:02.0/power"
 /* We just leak this on exit ... */
 int pm_status_fd = -1;
@@ -586,6 +629,34 @@ bool igt_setup_runtime_pm(void)
 }
 
 /**
+ * igt_disable_runtime_pm:
+ *
+ * Disable the runtime pm for i915 device.
+ * igt_disable_runtime_pm assumes that igt_setup_runtime_pm has already
+ * called to save runtime autosuspend and control attributes.
+ */
+void igt_disable_runtime_pm(void)
+{
+	int fd;
+	ssize_t size;
+	char buf[6];
+
+	igt_assert_fd(pm_status_fd);
+
+	/* We know we support runtime PM, let's try to disable it now. */
+	fd = open(POWER_DIR "/control", O_RDWR);
+	igt_assert_f(fd >= 0, "Can't open " POWER_DIR "/control\n");
+
+	size = write(fd, "on\n", 3);
+	igt_assert(size == 3);
+	lseek(fd, 0, SEEK_SET);
+	size = read(fd, buf, ARRAY_SIZE(buf));
+	igt_assert(size == 3);
+	igt_assert(strncmp(buf, "on\n", 3) == 0);
+	close(fd);
+}
+
+/**
  * igt_get_runtime_pm_status:
  *
  * Returns: The current runtime PM status.
@@ -628,3 +699,53 @@ bool igt_wait_for_pm_status(enum igt_runtime_pm_status status)
 {
 	return igt_wait(igt_get_runtime_pm_status() == status, 10000, 100);
 }
+
+/**
+ * dmc_loaded:
+ * @debugfs: fd to the debugfs dir.
+
+ * Check whether DMC FW is loaded or not. DMC FW is require for few Display C
+ * states like DC5 and DC6. FW does the Context Save and Restore during Display
+ * C States entry and exit.
+ *
+ * Returns:
+ * True if DMC FW is loaded otherwise false.
+ */
+bool igt_pm_dmc_loaded(int debugfs)
+{
+	char buf[15];
+	int len;
+
+	len = igt_sysfs_read(debugfs, "i915_dmc_info", buf, sizeof(buf) - 1);
+	if (len < 0)
+		return true; /* no CSR support, no DMC requirement */
+
+	buf[len] = '\0';
+
+	igt_info("DMC: %s\n", buf);
+	return strstr(buf, "fw loaded: yes");
+}
+
+/**
+ * is_bios_limits_pc8_plus_residencies:
+
+ * Check whether BIOS has disabled the PC8 package deeper state.
+ *
+ * Returns:
+ * True if PC8+ package deeper state enabled on machine otherwise false.
+ */
+bool is_bios_limits_pc8_plus_residencies(int msr_fd)
+{
+	int rc;
+	uint64_t val;
+
+	rc = pread(msr_fd, &val, sizeof(uint64_t), MSR_PKG_CST_CONFIG_CONTROL);
+	if (rc != sizeof(val))
+		return false;
+	if ((val & PKG_CST_LIMIT_MASK) < PKG_CST_LIMIT_C8) {
+		igt_info("PKG C-states limited below PC8 by the BIOS\n");
+		return false;
+	}
+
+	return true;
+}
diff --git a/lib/igt_pm.h b/lib/igt_pm.h
index 10cc679..f4d6c49 100644
--- a/lib/igt_pm.h
+++ b/lib/igt_pm.h
@@ -25,8 +25,8 @@
 #define IGT_PM_H
 
 void igt_pm_enable_audio_runtime_pm(void);
-int8_t *igt_pm_enable_sata_link_power_management(void);
-void igt_pm_restore_sata_link_power_management(int8_t *pm_data);
+void igt_pm_enable_sata_link_power_management(void);
+void igt_pm_restore_sata_link_power_management(void);
 
 /**
  * igt_runtime_pm_status:
@@ -47,8 +47,11 @@ enum igt_runtime_pm_status {
 };
 
 bool igt_setup_runtime_pm(void);
+void igt_disable_runtime_pm(void);
 void igt_restore_runtime_pm(void);
 enum igt_runtime_pm_status igt_get_runtime_pm_status(void);
 bool igt_wait_for_pm_status(enum igt_runtime_pm_status status);
+bool igt_pm_dmc_loaded(int debugfs);
+bool is_bios_limits_pc8_plus_residencies(int msr_fd);
 
 #endif /* IGT_PM_H */
diff --git a/tests/i915/i915_pm_backlight.c b/tests/i915/i915_pm_backlight.c
index 7662366..03af3e4 100644
--- a/tests/i915/i915_pm_backlight.c
+++ b/tests/i915/i915_pm_backlight.c
@@ -48,7 +48,6 @@ struct context {
 #define FADESPEED 100 /* milliseconds between steps */
 
 IGT_TEST_DESCRIPTION("Basic backlight sysfs test");
-static int8_t *pm_data = NULL;
 
 static int backlight_read(int *result, const char *fname)
 {
@@ -238,7 +237,7 @@ igt_main
 		igt_plane_set_fb(primary, &fb);
 
 		igt_display_commit2(&display, display.is_atomic ? COMMIT_ATOMIC : COMMIT_LEGACY);
-		pm_data = igt_pm_enable_sata_link_power_management();
+		igt_pm_enable_sata_link_power_management();
 	}
 
 	igt_subtest("basic-brightness")
@@ -258,8 +257,7 @@ igt_main
 
 		igt_display_fini(&display);
 		igt_remove_fb(display.drm_fd, &fb);
-		igt_pm_restore_sata_link_power_management(pm_data);
-		free(pm_data);
+		igt_pm_restore_sata_link_power_management();
 		close(display.drm_fd);
 	}
 }
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 31ce2a1..ec0faa8 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -52,11 +52,6 @@
 #include "igt_device.h"
 #include "igt_edid.h"
 
-#define MSR_PKG_CST_CONFIG_CONTROL	0xE2
-/* HSW/BDW: */
-#define  PKG_CST_LIMIT_MASK		0xF
-#define  PKG_CST_LIMIT_C8		0x6
-
 #define MSR_PC8_RES	0x630
 #define MSR_PC9_RES	0x631
 #define MSR_PC10_RES	0x632
@@ -123,8 +118,6 @@ struct modeset_params lpsp_mode_params;
 struct modeset_params non_lpsp_mode_params;
 struct modeset_params *default_mode_params;
 
-static int8_t *pm_data = NULL;
-
 static int modprobe(const char *driver)
 {
 	return igt_kmod_load(driver, NULL);
@@ -146,15 +139,7 @@ static bool supports_pc8_plus_residencies(void)
 	if (rc != sizeof(val))
 		return false;
 
-	rc = pread(msr_fd, &val, sizeof(uint64_t), MSR_PKG_CST_CONFIG_CONTROL);
-	if (rc != sizeof(val))
-		return false;
-	if ((val & PKG_CST_LIMIT_MASK) < PKG_CST_LIMIT_C8) {
-		igt_info("PKG C-states limited below PC8 by the BIOS\n");
-		return false;
-	}
-
-	return true;
+	return is_bios_limits_pc8_plus_residencies(msr_fd);
 }
 
 static uint64_t get_residency(uint32_t type)
@@ -755,21 +740,6 @@ static void setup_pc8(void)
 	has_pc8 = true;
 }
 
-static bool dmc_loaded(void)
-{
-	char buf[15];
-	int len;
-
-	len = igt_sysfs_read(debugfs, "i915_dmc_info", buf, sizeof(buf) - 1);
-	if (len < 0)
-	    return true; /* no CSR support, no DMC requirement */
-
-	buf[len] = '\0';
-
-	igt_info("DMC: %s\n", buf);
-	return strstr(buf, "fw loaded: yes");
-}
-
 static void dump_file(int dir, const char *filename)
 {
 	char *contents;
@@ -796,7 +766,7 @@ static bool setup_environment(void)
 
 	init_mode_set_data(&ms_data);
 
-	pm_data = igt_pm_enable_sata_link_power_management();
+	igt_pm_enable_sata_link_power_management();
 
 	has_runtime_pm = igt_setup_runtime_pm();
 	setup_pc8();
@@ -804,7 +774,7 @@ static bool setup_environment(void)
 	igt_info("Runtime PM support: %d\n", has_runtime_pm);
 	igt_info("PC8 residency support: %d\n", has_pc8);
 	igt_require(has_runtime_pm);
-	igt_require(dmc_loaded());
+	igt_require(igt_pm_dmc_loaded(debugfs));
 
 out:
 	disable_all_screens(&ms_data);
@@ -821,8 +791,7 @@ static void teardown_environment(void)
 
 	igt_restore_runtime_pm();
 
-	igt_pm_restore_sata_link_power_management(pm_data);
-	free(pm_data);
+	igt_pm_restore_sata_link_power_management();
 
 	fini_mode_set_data(&ms_data);
 
-- 
2.7.4

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[igt-dev] [PATCH i-g-t 2/8] tests/i915/i915_pm_dc: Added new test to verify Display C States

[Jeevan B]

From: Jyoti Yadav <jyoti.r.yadav@intel.com>

Currently this test validates DC5 upon PSR entry for supported platforms.
Added new file for compilation inside Makefile and Meson.

v2: Used the debugfs entry for DC counters instead of Registers.
    Used shorter names for variables.
    Introduced timeout to read DC counters.
v3: one second timeout is introduced to read DC counters.
    Skip the subtest if counters are not available for that platform.
v4: Rebased, to fix compilation error in psr_enable(), psr_wait_entry()
    and replaced igt_display_init() by igt_display_require() in pm_rpm.c.
    Addressed the review comment by removing unused function display_init,
    removing redundant igt commit suggested by Imre.
    Fixed typo in read_dc_counter().
v5: Addressed the review comment by removing redundant read_dc_counter(),
    clubbed cleanup() function in test_dc_state_psr() suggested by Imre.
    Rearranged  preprocessor directives at one place.
    Fixed compilation warning by adding function prototype for
    dc_state_wait_entry() and check_dc_counter().
    Listing actual change in patch set changelog to make review easier.
v6: Fixed "i915_edp_psr_status" string to "Sink support: yes".
v7: Rebased since test name changed from "pm_dc" to "i915_pm_dc",
    this will align with other PM tests.
    also changed the DC5/6 counter check timeout to 3 second.
v8: On few platform SATA i/p is blocking deeper package C states.
    used igt_pm_enable_sata_link_power_management() function in order
    to use min_power policy.
v9: Removed redundant igt_pm_remove_sata_link_power_management()
    as sata link policy values will be restored by exit handler.
v10: changed cleanup() to cleanup_dc_psr() symmetric to cleanup_dc_dpms().
v11: Removed unwanted headers. [Imre]

Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/Makefile.sources  |   3 +
 tests/i915/i915_pm_dc.c | 211 ++++++++++++++++++++++++++++++++++++++++++++++++
 tests/meson.build       |   1 +
 3 files changed, 215 insertions(+)
 create mode 100644 tests/i915/i915_pm_dc.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 549a350..06a0a48 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -520,6 +520,9 @@ i915_pm_rc6_residency_SOURCES = i915/i915_pm_rc6_residency.c
 TESTS_progs += i915_pm_rpm
 i915_pm_rpm_SOURCES = i915/i915_pm_rpm.c
 
+TESTS_progs += i915_pm_dc
+i915_pm_dc_SOURCES = i915/i915_pm_dc.c
+
 TESTS_progs += i915_pm_rps
 i915_pm_rps_SOURCES = i915/i915_pm_rps.c
 
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
new file mode 100644
index 0000000..c0e41c3
--- /dev/null
+++ b/tests/i915/i915_pm_dc.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+#include "igt.h"
+#include "igt_psr.h"
+#include "igt_sysfs.h"
+#include "limits.h"
+
+/* DC State Flags */
+#define CHECK_DC5	1
+#define CHECK_DC6	2
+
+typedef struct {
+	int drm_fd;
+	int debugfs_fd;
+	uint32_t devid;
+	igt_display_t display;
+	struct igt_fb fb_white;
+	enum psr_mode op_psr_mode;
+	drmModeModeInfo *mode;
+	igt_output_t *output;
+} data_t;
+
+static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count);
+static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count);
+
+static void setup_output(data_t *data)
+{
+	igt_display_t *display = &data->display;
+	igt_output_t *output;
+	enum pipe pipe;
+
+	for_each_pipe_with_valid_output(display, pipe, output) {
+		drmModeConnectorPtr c = output->config.connector;
+
+		if (c->connector_type != DRM_MODE_CONNECTOR_eDP)
+			continue;
+
+		igt_output_set_pipe(output, pipe);
+		data->output = output;
+		data->mode = igt_output_get_mode(output);
+
+		return;
+	}
+}
+
+static void display_fini(data_t *data)
+{
+	igt_display_fini(&data->display);
+}
+
+static bool edp_psr_sink_support(data_t *data)
+{
+	char buf[512];
+
+	igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
+				buf, sizeof(buf));
+
+	return strstr(buf, "Sink support: yes");
+}
+
+static void cleanup_dc_psr(data_t *data)
+{
+	igt_plane_t *primary;
+
+	primary = igt_output_get_plane_type(data->output,
+					    DRM_PLANE_TYPE_PRIMARY);
+	igt_plane_set_fb(primary, NULL);
+	igt_display_commit(&data->display);
+	igt_remove_fb(data->drm_fd, &data->fb_white);
+}
+
+static void setup_primary(data_t *data)
+{
+	igt_plane_t *primary;
+
+	primary = igt_output_get_plane_type(data->output,
+					    DRM_PLANE_TYPE_PRIMARY);
+	igt_plane_set_fb(primary, NULL);
+	igt_create_color_fb(data->drm_fd,
+			    data->mode->hdisplay, data->mode->vdisplay,
+			    DRM_FORMAT_XRGB8888,
+			    LOCAL_I915_FORMAT_MOD_X_TILED,
+			    1.0, 1.0, 1.0,
+			    &data->fb_white);
+	igt_plane_set_fb(primary, &data->fb_white);
+	igt_display_commit(&data->display);
+}
+
+static uint32_t get_dc_counter(char *dc_data)
+{
+	char *e;
+	long ret;
+	char *s = strchr(dc_data, ':');
+
+	assert(s);
+	s++;
+	ret = strtol(s, &e, 10);
+	assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) &&
+	       e > s && *e == '\n' && ret >= 0);
+	return ret;
+}
+
+static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
+{
+	char buf[4096];
+	char *str;
+
+	igt_debugfs_read(drm_fd, "i915_dmc_info", buf);
+
+	if (dc_flag & CHECK_DC5)
+		str = strstr(buf, "DC3 -> DC5 count");
+	else if (dc_flag & CHECK_DC6)
+		str = strstr(buf, "DC5 -> DC6 count");
+
+	/* Check DC5/DC6 counter is available for the platform.
+	 * Skip the test if counter is not available.
+	 */
+	igt_skip_on_f(!str, "DC%d counter is not available\n",
+		      dc_flag & CHECK_DC5 ? 5 : 6);
+	return get_dc_counter(str);
+}
+
+static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
+{
+	return igt_wait(read_dc_counter(drm_fd, dc_flag) >
+			prev_dc_count, 3000, 100);
+}
+
+static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
+{
+	igt_assert_f(dc_state_wait_entry(drm_fd, dc_flag, prev_dc_count),
+		     "DC%d state is not achieved\n",
+		     dc_flag & CHECK_DC5 ? 5 : 6);
+}
+
+static void test_dc_state_psr(data_t *data, int dc_flag)
+{
+	uint32_t dc_counter_before_psr;
+
+	dc_counter_before_psr = read_dc_counter(data->drm_fd, dc_flag);
+	setup_output(data);
+	setup_primary(data);
+	igt_assert(psr_wait_entry(data->debugfs_fd, data->op_psr_mode));
+	check_dc_counter(data->drm_fd, dc_flag, dc_counter_before_psr);
+	cleanup_dc_psr(data);
+}
+
+IGT_TEST_DESCRIPTION("Display Power DC states IGT Test");
+int main(int argc, char *argv[])
+{
+	bool has_runtime_pm;
+	data_t data = {};
+
+	igt_skip_on_simulation();
+	igt_subtest_init(argc, argv);
+	igt_fixture {
+		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
+		data.debugfs_fd = igt_debugfs_dir(data.drm_fd);
+		igt_require(data.debugfs_fd != -1);
+		kmstest_set_vt_graphics_mode();
+		data.devid = intel_get_drm_devid(data.drm_fd);
+		igt_pm_enable_sata_link_power_management();
+		has_runtime_pm = igt_setup_runtime_pm();
+		igt_info("Runtime PM support: %d\n", has_runtime_pm);
+		igt_require(has_runtime_pm);
+		igt_require(igt_pm_dmc_loaded(data.debugfs_fd));
+		igt_display_require(&data.display, data.drm_fd);
+	}
+
+	igt_describe("DC5 igt test with PSR Sleep state");
+	igt_subtest("dc5-psr") {
+		data.op_psr_mode = PSR_MODE_1;
+		psr_enable(data.debugfs_fd, data.op_psr_mode);
+		igt_require_f(edp_psr_sink_support(&data),
+			      "Sink does not support PSR\n");
+		test_dc_state_psr(&data, CHECK_DC5);
+	}
+
+	igt_fixture {
+		close(data.debugfs_fd);
+		display_fini(&data);
+	}
+
+	igt_exit();
+}
diff --git a/tests/meson.build b/tests/meson.build
index e14c827..acb2cce 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -235,6 +235,7 @@ i915_progs = [
 	'i915_pm_lpsp',
 	'i915_pm_rc6_residency',
 	'i915_pm_rpm',
+	'i915_pm_dc',
 	'i915_pm_rps',
 	'i915_pm_sseu',
 	'i915_query',
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 2/8] tests/i915/i915_pm_dc: Added new test to verify Display C States

[Petri Latvala]

On Thu, Sep 12, 2019 at 01:46:32PM +0530, Jeevan B wrote:
> From: Jyoti Yadav <jyoti.r.yadav@intel.com>
> 
> Currently this test validates DC5 upon PSR entry for supported platforms.
> Added new file for compilation inside Makefile and Meson.
> 
> v2: Used the debugfs entry for DC counters instead of Registers.
>     Used shorter names for variables.
>     Introduced timeout to read DC counters.
> v3: one second timeout is introduced to read DC counters.
>     Skip the subtest if counters are not available for that platform.
> v4: Rebased, to fix compilation error in psr_enable(), psr_wait_entry()
>     and replaced igt_display_init() by igt_display_require() in pm_rpm.c.
>     Addressed the review comment by removing unused function display_init,
>     removing redundant igt commit suggested by Imre.
>     Fixed typo in read_dc_counter().
> v5: Addressed the review comment by removing redundant read_dc_counter(),
>     clubbed cleanup() function in test_dc_state_psr() suggested by Imre.
>     Rearranged  preprocessor directives at one place.
>     Fixed compilation warning by adding function prototype for
>     dc_state_wait_entry() and check_dc_counter().
>     Listing actual change in patch set changelog to make review easier.
> v6: Fixed "i915_edp_psr_status" string to "Sink support: yes".
> v7: Rebased since test name changed from "pm_dc" to "i915_pm_dc",
>     this will align with other PM tests.
>     also changed the DC5/6 counter check timeout to 3 second.
> v8: On few platform SATA i/p is blocking deeper package C states.
>     used igt_pm_enable_sata_link_power_management() function in order
>     to use min_power policy.
> v9: Removed redundant igt_pm_remove_sata_link_power_management()
>     as sata link policy values will be restored by exit handler.
> v10: changed cleanup() to cleanup_dc_psr() symmetric to cleanup_dc_dpms().
> v11: Removed unwanted headers. [Imre]
> 
> Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  tests/Makefile.sources  |   3 +
>  tests/i915/i915_pm_dc.c | 211 ++++++++++++++++++++++++++++++++++++++++++++++++
>  tests/meson.build       |   1 +
>  3 files changed, 215 insertions(+)
>  create mode 100644 tests/i915/i915_pm_dc.c
> 
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index 549a350..06a0a48 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -520,6 +520,9 @@ i915_pm_rc6_residency_SOURCES = i915/i915_pm_rc6_residency.c
>  TESTS_progs += i915_pm_rpm
>  i915_pm_rpm_SOURCES = i915/i915_pm_rpm.c
>  
> +TESTS_progs += i915_pm_dc
> +i915_pm_dc_SOURCES = i915/i915_pm_dc.c
> +
>  TESTS_progs += i915_pm_rps
>  i915_pm_rps_SOURCES = i915/i915_pm_rps.c
>  
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> new file mode 100644
> index 0000000..c0e41c3
> --- /dev/null
> +++ b/tests/i915/i915_pm_dc.c
> @@ -0,0 +1,211 @@
> +/*
> + * Copyright © 2018 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include <errno.h>
> +#include <stdbool.h>
> +#include <stdio.h>
> +#include <string.h>
> +#include "igt.h"
> +#include "igt_psr.h"
> +#include "igt_sysfs.h"
> +#include "limits.h"
> +
> +/* DC State Flags */
> +#define CHECK_DC5	1
> +#define CHECK_DC6	2
> +
> +typedef struct {
> +	int drm_fd;
> +	int debugfs_fd;
> +	uint32_t devid;
> +	igt_display_t display;
> +	struct igt_fb fb_white;
> +	enum psr_mode op_psr_mode;
> +	drmModeModeInfo *mode;
> +	igt_output_t *output;
> +} data_t;
> +
> +static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count);
> +static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count);
> +
> +static void setup_output(data_t *data)
> +{
> +	igt_display_t *display = &data->display;
> +	igt_output_t *output;
> +	enum pipe pipe;
> +
> +	for_each_pipe_with_valid_output(display, pipe, output) {
> +		drmModeConnectorPtr c = output->config.connector;
> +
> +		if (c->connector_type != DRM_MODE_CONNECTOR_eDP)
> +			continue;
> +
> +		igt_output_set_pipe(output, pipe);
> +		data->output = output;
> +		data->mode = igt_output_get_mode(output);
> +
> +		return;
> +	}
> +}
> +
> +static void display_fini(data_t *data)
> +{
> +	igt_display_fini(&data->display);
> +}
> +
> +static bool edp_psr_sink_support(data_t *data)
> +{
> +	char buf[512];
> +
> +	igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
> +				buf, sizeof(buf));
> +
> +	return strstr(buf, "Sink support: yes");
> +}
> +
> +static void cleanup_dc_psr(data_t *data)
> +{
> +	igt_plane_t *primary;
> +
> +	primary = igt_output_get_plane_type(data->output,
> +					    DRM_PLANE_TYPE_PRIMARY);
> +	igt_plane_set_fb(primary, NULL);
> +	igt_display_commit(&data->display);
> +	igt_remove_fb(data->drm_fd, &data->fb_white);
> +}
> +
> +static void setup_primary(data_t *data)
> +{
> +	igt_plane_t *primary;
> +
> +	primary = igt_output_get_plane_type(data->output,
> +					    DRM_PLANE_TYPE_PRIMARY);
> +	igt_plane_set_fb(primary, NULL);
> +	igt_create_color_fb(data->drm_fd,
> +			    data->mode->hdisplay, data->mode->vdisplay,
> +			    DRM_FORMAT_XRGB8888,
> +			    LOCAL_I915_FORMAT_MOD_X_TILED,
> +			    1.0, 1.0, 1.0,
> +			    &data->fb_white);
> +	igt_plane_set_fb(primary, &data->fb_white);
> +	igt_display_commit(&data->display);
> +}
> +
> +static uint32_t get_dc_counter(char *dc_data)
> +{
> +	char *e;
> +	long ret;
> +	char *s = strchr(dc_data, ':');
> +
> +	assert(s);
> +	s++;
> +	ret = strtol(s, &e, 10);
> +	assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) &&
> +	       e > s && *e == '\n' && ret >= 0);
> +	return ret;
> +}
> +
> +static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
> +{
> +	char buf[4096];
> +	char *str;
> +
> +	igt_debugfs_read(drm_fd, "i915_dmc_info", buf);
> +
> +	if (dc_flag & CHECK_DC5)
> +		str = strstr(buf, "DC3 -> DC5 count");
> +	else if (dc_flag & CHECK_DC6)
> +		str = strstr(buf, "DC5 -> DC6 count");
> +
> +	/* Check DC5/DC6 counter is available for the platform.
> +	 * Skip the test if counter is not available.
> +	 */
> +	igt_skip_on_f(!str, "DC%d counter is not available\n",
> +		      dc_flag & CHECK_DC5 ? 5 : 6);
> +	return get_dc_counter(str);
> +}
> +
> +static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
> +{
> +	return igt_wait(read_dc_counter(drm_fd, dc_flag) >
> +			prev_dc_count, 3000, 100);
> +}
> +
> +static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
> +{
> +	igt_assert_f(dc_state_wait_entry(drm_fd, dc_flag, prev_dc_count),
> +		     "DC%d state is not achieved\n",
> +		     dc_flag & CHECK_DC5 ? 5 : 6);
> +}
> +
> +static void test_dc_state_psr(data_t *data, int dc_flag)
> +{
> +	uint32_t dc_counter_before_psr;
> +
> +	dc_counter_before_psr = read_dc_counter(data->drm_fd, dc_flag);
> +	setup_output(data);
> +	setup_primary(data);
> +	igt_assert(psr_wait_entry(data->debugfs_fd, data->op_psr_mode));
> +	check_dc_counter(data->drm_fd, dc_flag, dc_counter_before_psr);
> +	cleanup_dc_psr(data);
> +}
> +
> +IGT_TEST_DESCRIPTION("Display Power DC states IGT Test");
> +int main(int argc, char *argv[])
> +{
> +	bool has_runtime_pm;
> +	data_t data = {};
> +
> +	igt_skip_on_simulation();
> +	igt_subtest_init(argc, argv);
> +	igt_fixture {
> +		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
> +		data.debugfs_fd = igt_debugfs_dir(data.drm_fd);
> +		igt_require(data.debugfs_fd != -1);
> +		kmstest_set_vt_graphics_mode();
> +		data.devid = intel_get_drm_devid(data.drm_fd);
> +		igt_pm_enable_sata_link_power_management();
> +		has_runtime_pm = igt_setup_runtime_pm();
> +		igt_info("Runtime PM support: %d\n", has_runtime_pm);
> +		igt_require(has_runtime_pm);
> +		igt_require(igt_pm_dmc_loaded(data.debugfs_fd));
> +		igt_display_require(&data.display, data.drm_fd);
> +	}
> +
> +	igt_describe("DC5 igt test with PSR Sleep state");
> +	igt_subtest("dc5-psr") {


Can the documentation be fleshed out a bit more? For one, it's
redundant for an IGT test to state that it's an IGT test (applies to
both the igt_describe calls and the IGT_TEST_DESCRIPTION string).

"DC5 test with PSR Sleep state" is not clear what the test is
testing. Something like "Test that DC5 state is reached in PSR sleep
state"?


-- 
Petri Latvala
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Re: [igt-dev] [PATCH i-g-t 2/8] tests/i915/i915_pm_dc: Added new test to verify Display C States

[Gupta, Anshuman]

On 9/17/2019 5:10 PM, Petri Latvala wrote:
> On Thu, Sep 12, 2019 at 01:46:32PM +0530, Jeevan B wrote:
>> From: Jyoti Yadav <jyoti.r.yadav@intel.com>
>>
>> Currently this test validates DC5 upon PSR entry for supported platforms.
>> Added new file for compilation inside Makefile and Meson.
>>
>> v2: Used the debugfs entry for DC counters instead of Registers.
>>      Used shorter names for variables.
>>      Introduced timeout to read DC counters.
>> v3: one second timeout is introduced to read DC counters.
>>      Skip the subtest if counters are not available for that platform.
>> v4: Rebased, to fix compilation error in psr_enable(), psr_wait_entry()
>>      and replaced igt_display_init() by igt_display_require() in pm_rpm.c.
>>      Addressed the review comment by removing unused function display_init,
>>      removing redundant igt commit suggested by Imre.
>>      Fixed typo in read_dc_counter().
>> v5: Addressed the review comment by removing redundant read_dc_counter(),
>>      clubbed cleanup() function in test_dc_state_psr() suggested by Imre.
>>      Rearranged  preprocessor directives at one place.
>>      Fixed compilation warning by adding function prototype for
>>      dc_state_wait_entry() and check_dc_counter().
>>      Listing actual change in patch set changelog to make review easier.
>> v6: Fixed "i915_edp_psr_status" string to "Sink support: yes".
>> v7: Rebased since test name changed from "pm_dc" to "i915_pm_dc",
>>      this will align with other PM tests.
>>      also changed the DC5/6 counter check timeout to 3 second.
>> v8: On few platform SATA i/p is blocking deeper package C states.
>>      used igt_pm_enable_sata_link_power_management() function in order
>>      to use min_power policy.
>> v9: Removed redundant igt_pm_remove_sata_link_power_management()
>>      as sata link policy values will be restored by exit handler.
>> v10: changed cleanup() to cleanup_dc_psr() symmetric to cleanup_dc_dpms().
>> v11: Removed unwanted headers. [Imre]
>>
>> Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> ---
>>   tests/Makefile.sources  |   3 +
>>   tests/i915/i915_pm_dc.c | 211 ++++++++++++++++++++++++++++++++++++++++++++++++
>>   tests/meson.build       |   1 +
>>   3 files changed, 215 insertions(+)
>>   create mode 100644 tests/i915/i915_pm_dc.c
>>
>> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
>> index 549a350..06a0a48 100644
>> --- a/tests/Makefile.sources
>> +++ b/tests/Makefile.sources
>> @@ -520,6 +520,9 @@ i915_pm_rc6_residency_SOURCES = i915/i915_pm_rc6_residency.c
>>   TESTS_progs += i915_pm_rpm
>>   i915_pm_rpm_SOURCES = i915/i915_pm_rpm.c
>>   
>> +TESTS_progs += i915_pm_dc
>> +i915_pm_dc_SOURCES = i915/i915_pm_dc.c
>> +
>>   TESTS_progs += i915_pm_rps
>>   i915_pm_rps_SOURCES = i915/i915_pm_rps.c
>>   
>> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
>> new file mode 100644
>> index 0000000..c0e41c3
>> --- /dev/null
>> +++ b/tests/i915/i915_pm_dc.c
>> @@ -0,0 +1,211 @@
>> +/*
>> + * Copyright © 2018 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
>> +
>> +#include <errno.h>
>> +#include <stdbool.h>
>> +#include <stdio.h>
>> +#include <string.h>
>> +#include "igt.h"
>> +#include "igt_psr.h"
>> +#include "igt_sysfs.h"
>> +#include "limits.h"
>> +
>> +/* DC State Flags */
>> +#define CHECK_DC5	1
>> +#define CHECK_DC6	2
>> +
>> +typedef struct {
>> +	int drm_fd;
>> +	int debugfs_fd;
>> +	uint32_t devid;
>> +	igt_display_t display;
>> +	struct igt_fb fb_white;
>> +	enum psr_mode op_psr_mode;
>> +	drmModeModeInfo *mode;
>> +	igt_output_t *output;
>> +} data_t;
>> +
>> +static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count);
>> +static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count);
>> +
>> +static void setup_output(data_t *data)
>> +{
>> +	igt_display_t *display = &data->display;
>> +	igt_output_t *output;
>> +	enum pipe pipe;
>> +
>> +	for_each_pipe_with_valid_output(display, pipe, output) {
>> +		drmModeConnectorPtr c = output->config.connector;
>> +
>> +		if (c->connector_type != DRM_MODE_CONNECTOR_eDP)
>> +			continue;
>> +
>> +		igt_output_set_pipe(output, pipe);
>> +		data->output = output;
>> +		data->mode = igt_output_get_mode(output);
>> +
>> +		return;
>> +	}
>> +}
>> +
>> +static void display_fini(data_t *data)
>> +{
>> +	igt_display_fini(&data->display);
>> +}
>> +
>> +static bool edp_psr_sink_support(data_t *data)
>> +{
>> +	char buf[512];
>> +
>> +	igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
>> +				buf, sizeof(buf));
>> +
>> +	return strstr(buf, "Sink support: yes");
>> +}
>> +
>> +static void cleanup_dc_psr(data_t *data)
>> +{
>> +	igt_plane_t *primary;
>> +
>> +	primary = igt_output_get_plane_type(data->output,
>> +					    DRM_PLANE_TYPE_PRIMARY);
>> +	igt_plane_set_fb(primary, NULL);
>> +	igt_display_commit(&data->display);
>> +	igt_remove_fb(data->drm_fd, &data->fb_white);
>> +}
>> +
>> +static void setup_primary(data_t *data)
>> +{
>> +	igt_plane_t *primary;
>> +
>> +	primary = igt_output_get_plane_type(data->output,
>> +					    DRM_PLANE_TYPE_PRIMARY);
>> +	igt_plane_set_fb(primary, NULL);
>> +	igt_create_color_fb(data->drm_fd,
>> +			    data->mode->hdisplay, data->mode->vdisplay,
>> +			    DRM_FORMAT_XRGB8888,
>> +			    LOCAL_I915_FORMAT_MOD_X_TILED,
>> +			    1.0, 1.0, 1.0,
>> +			    &data->fb_white);
>> +	igt_plane_set_fb(primary, &data->fb_white);
>> +	igt_display_commit(&data->display);
>> +}
>> +
>> +static uint32_t get_dc_counter(char *dc_data)
>> +{
>> +	char *e;
>> +	long ret;
>> +	char *s = strchr(dc_data, ':');
>> +
>> +	assert(s);
>> +	s++;
>> +	ret = strtol(s, &e, 10);
>> +	assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) &&
>> +	       e > s && *e == '\n' && ret >= 0);
>> +	return ret;
>> +}
>> +
>> +static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
>> +{
>> +	char buf[4096];
>> +	char *str;
>> +
>> +	igt_debugfs_read(drm_fd, "i915_dmc_info", buf);
>> +
>> +	if (dc_flag & CHECK_DC5)
>> +		str = strstr(buf, "DC3 -> DC5 count");
>> +	else if (dc_flag & CHECK_DC6)
>> +		str = strstr(buf, "DC5 -> DC6 count");
>> +
>> +	/* Check DC5/DC6 counter is available for the platform.
>> +	 * Skip the test if counter is not available.
>> +	 */
>> +	igt_skip_on_f(!str, "DC%d counter is not available\n",
>> +		      dc_flag & CHECK_DC5 ? 5 : 6);
>> +	return get_dc_counter(str);
>> +}
>> +
>> +static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
>> +{
>> +	return igt_wait(read_dc_counter(drm_fd, dc_flag) >
>> +			prev_dc_count, 3000, 100);
>> +}
>> +
>> +static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
>> +{
>> +	igt_assert_f(dc_state_wait_entry(drm_fd, dc_flag, prev_dc_count),
>> +		     "DC%d state is not achieved\n",
>> +		     dc_flag & CHECK_DC5 ? 5 : 6);
>> +}
>> +
>> +static void test_dc_state_psr(data_t *data, int dc_flag)
>> +{
>> +	uint32_t dc_counter_before_psr;
>> +
>> +	dc_counter_before_psr = read_dc_counter(data->drm_fd, dc_flag);
>> +	setup_output(data);
>> +	setup_primary(data);
>> +	igt_assert(psr_wait_entry(data->debugfs_fd, data->op_psr_mode));
>> +	check_dc_counter(data->drm_fd, dc_flag, dc_counter_before_psr);
>> +	cleanup_dc_psr(data);
>> +}
>> +
>> +IGT_TEST_DESCRIPTION("Display Power DC states IGT Test");
>> +int main(int argc, char *argv[])
>> +{
>> +	bool has_runtime_pm;
>> +	data_t data = {};
>> +
>> +	igt_skip_on_simulation();
>> +	igt_subtest_init(argc, argv);
>> +	igt_fixture {
>> +		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
>> +		data.debugfs_fd = igt_debugfs_dir(data.drm_fd);
>> +		igt_require(data.debugfs_fd != -1);
>> +		kmstest_set_vt_graphics_mode();
>> +		data.devid = intel_get_drm_devid(data.drm_fd);
>> +		igt_pm_enable_sata_link_power_management();
>> +		has_runtime_pm = igt_setup_runtime_pm();
>> +		igt_info("Runtime PM support: %d\n", has_runtime_pm);
>> +		igt_require(has_runtime_pm);
>> +		igt_require(igt_pm_dmc_loaded(data.debugfs_fd));
>> +		igt_display_require(&data.display, data.drm_fd);
>> +	}
>> +
>> +	igt_describe("DC5 igt test with PSR Sleep state");
>> +	igt_subtest("dc5-psr") {
> 
> 
> Can the documentation be fleshed out a bit more? For one, it's
> redundant for an IGT test to state that it's an IGT test (applies to
> both the igt_describe calls and the IGT_TEST_DESCRIPTION string).
> 
> "DC5 test with PSR Sleep state" is not clear what the test is
> testing. Something like "Test that DC5 state is reached in PSR sleep
> state"?
Hi Petri ,

Thanks for your review comment, this series actually intended for DC3CO
IGT test as existing DC state patches are not merged yet, Jeevan has
sent DC3CO igt patches with existing dc state IGT patch series.
I have addressed your comment in below series, it has already having 
Imre's RB.
https://patchwork.freedesktop.org/series/56713/
Could you please help to merge this patch series.

Thanks ,
Anshuman Gupta.
> 
> 
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[igt-dev] [PATCH i-g-t 3/8] tests/i915/i915_pm_dc: Added test for DC6 during PSR

[Jeevan B]

From: Jyoti Yadav <jyoti.r.yadav@intel.com>

This patch add subtest to check DC6 entry on PSR for the supported
platforms.

v2: Rename the subtest with more meaningful name.
v3: Rebased.
v4: Rebased, to fix compilation error in psr_enable().
    Addressed review comment by fixing typo in comment description
    of DC6 PSR subtest.
v5: Addressed the review comment by removing redundant read_dc_counter(),
    clubbed cleanup() function in test_dc_state_psr() suggested by Imre.
    Listing actual change in patch set changelog to make review easier.
v6: Rebased due to test name pm_dc changed to i915_pm_dc, aligning to
    other PM tests.

Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/i915/i915_pm_dc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index c0e41c3..5a2c798 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -202,6 +202,15 @@ int main(int argc, char *argv[])
 		test_dc_state_psr(&data, CHECK_DC5);
 	}
 
+	igt_describe("DC6 igt test with PSR Sleep state");
+	igt_subtest("dc6-psr") {
+		data.op_psr_mode = PSR_MODE_1;
+		psr_enable(data.debugfs_fd, data.op_psr_mode);
+		igt_require_f(edp_psr_sink_support(&data),
+			      "Sink does not support PSR\n");
+		test_dc_state_psr(&data, CHECK_DC6);
+	}
+
 	igt_fixture {
 		close(data.debugfs_fd);
 		display_fini(&data);
-- 
2.7.4

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[igt-dev] [PATCH i-g-t 4/8] tests/i915/i915_pm_dc: Added test for DC5 during DPMS

[Jeevan B]

From: Jyoti Yadav <jyoti.r.yadav@intel.com>

Added new subtest for DC5 entry during DPMS on/off cycle.
During DPMS on/off cycle DC5 counter is incremented.

v2: Rename the subtest with meaningful name.
v3: Rebased.
v4: Addressed review comments by removing leftover code
    cleanup().
v5: Addressed the review comment by removing redundant
    read_dc_counter() suggested by Imre.
    Listing actual change in patch set changelog to make review easier.
v6: Three way patch applied, no functional change.
v7: Disabling runtime suspend for the platform which support, DC9.
    rebased due to test name pm_dc changed to i915_pm_dc, aligning to
    other PM tests.
v8: Introduced setup_dc_dpms() in order to disable runtime pm, restoring
    POWER_DIR values to its original and enabling runtime pm  for other
    followed sub-tests.
v9: Check DC5 counter value after DPMS off, broke the dpms_on_off
    function to dpms_on and dpms_off. [Imre]
v10:Added AT_LEAST_Gen11 condition instead of IS_ICELAKE in order to
    disable runtime suspend. [Imre]
v11:Added a cleanup_dc_dpms() function. [Imre]

Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 tests/i915/i915_pm_dc.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 5a2c798..cd9768c 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -44,6 +44,7 @@ typedef struct {
 	enum psr_mode op_psr_mode;
 	drmModeModeInfo *mode;
 	igt_output_t *output;
+	bool runtime_suspend_disabled;
 } data_t;
 
 static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count);
@@ -171,6 +172,67 @@ static void test_dc_state_psr(data_t *data, int dc_flag)
 	cleanup_dc_psr(data);
 }
 
+static void cleanup_dc_dpms(data_t *data)
+{
+	/*
+	 * if runtime PM is disabled for i915 restore it,
+	 * so any other sub-test can use runtime-PM.
+	 */
+	if (data->runtime_suspend_disabled) {
+		igt_restore_runtime_pm();
+		igt_setup_runtime_pm();
+	}
+}
+
+static void setup_dc_dpms(data_t *data)
+{
+	if (IS_BROXTON(data->devid) || IS_GEMINILAKE(data->devid) ||
+	    AT_LEAST_GEN(data->devid, 11)) {
+		igt_disable_runtime_pm();
+		data->runtime_suspend_disabled = true;
+	} else {
+		data->runtime_suspend_disabled = false;
+	}
+}
+
+static void dpms_off(data_t *data)
+{
+	for (int i = 0; i < data->display.n_outputs; i++) {
+		kmstest_set_connector_dpms(data->drm_fd,
+					   data->display.outputs[i].config.connector,
+					   DRM_MODE_DPMS_OFF);
+	}
+
+	if (!data->runtime_suspend_disabled)
+		igt_assert(igt_wait_for_pm_status
+			   (IGT_RUNTIME_PM_STATUS_SUSPENDED));
+}
+
+static void dpms_on(data_t *data)
+{
+	for (int i = 0; i < data->display.n_outputs; i++) {
+		kmstest_set_connector_dpms(data->drm_fd,
+					   data->display.outputs[i].config.connector,
+					   DRM_MODE_DPMS_ON);
+	}
+
+	if (!data->runtime_suspend_disabled)
+		igt_assert(igt_wait_for_pm_status
+			   (IGT_RUNTIME_PM_STATUS_ACTIVE));
+}
+
+static void test_dc_state_dpms(data_t *data, int dc_flag)
+{
+	uint32_t dc_counter;
+
+	setup_dc_dpms(data);
+	dc_counter = read_dc_counter(data->drm_fd, dc_flag);
+	dpms_off(data);
+	check_dc_counter(data->drm_fd, dc_flag, dc_counter);
+	dpms_on(data);
+	cleanup_dc_dpms(data);
+}
+
 IGT_TEST_DESCRIPTION("Display Power DC states IGT Test");
 int main(int argc, char *argv[])
 {
@@ -211,6 +273,11 @@ int main(int argc, char *argv[])
 		test_dc_state_psr(&data, CHECK_DC6);
 	}
 
+	igt_describe("DC5 igt test with all connectors DPMS OFF/ON");
+	igt_subtest("dc5-dpms") {
+		test_dc_state_dpms(&data, CHECK_DC5);
+	}
+
 	igt_fixture {
 		close(data.debugfs_fd);
 		display_fini(&data);
-- 
2.7.4

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[igt-dev] [PATCH i-g-t 5/8] tests/i915/i915_pm_dc: Added test for DC6 during DPMS

[Jeevan B]

From: Jyoti Yadav <jyoti.r.yadav@intel.com>

Added new subtest for DC6 entry during DPMS on/off cycle.
During DPMS on/off cycle DC6 counter is incremented.

v2: Renamed the subtest name.
v3: Rebased.
v4: Addressed review comment by replacing igt_display_init() to
    igt_display_require(), changes got done in patch set 2.
v5: Addressed the review comment by removing redundant read_dc_counter()
    suggested by Imre.
    Listing actual change in patch set changelog to make review easier.
v6: Rebased due to test name pm_dc changed to i915_pm_dc, aligning to
    other PM tests.
v7: Introduced setup_dc_dpms() inorder to disable i915 runtime PM for
    the platform supports DC9.

Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/i915/i915_pm_dc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index cd9768c..b93466a 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -278,6 +278,11 @@ int main(int argc, char *argv[])
 		test_dc_state_dpms(&data, CHECK_DC5);
 	}
 
+	igt_describe("DC6 igt test with all connectors DPMS OFF/ON");
+	igt_subtest("dc6-dpms") {
+		test_dc_state_dpms(&data, CHECK_DC6);
+	}
+
 	igt_fixture {
 		close(data.debugfs_fd);
 		display_fini(&data);
-- 
2.7.4

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[igt-dev] [PATCH i-g-t 6/8] tests/i915/i915_pm_dc:Skip the DC6 test if BIOS has disabled PC8+

[Jeevan B]

From: Anshuman Gupta <anshuman.gupta@intel.com>

As DC6 requires platform to enter PC8 package C state.
It make sense to skip the DC6 igt-test, if BIOS configuration
has disabled PC8+ package C states.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/i915/i915_pm_dc.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index b93466a..86c12ad 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -23,10 +23,12 @@
  */
 
 #include <errno.h>
+#include <fcntl.h>
 #include <stdbool.h>
 #include <stdio.h>
 #include <string.h>
 #include "igt.h"
+#include "igt_kmod.h"
 #include "igt_psr.h"
 #include "igt_sysfs.h"
 #include "limits.h"
@@ -37,6 +39,7 @@
 
 typedef struct {
 	int drm_fd;
+	int msr_fd;
 	int debugfs_fd;
 	uint32_t devid;
 	igt_display_t display;
@@ -253,6 +256,12 @@ int main(int argc, char *argv[])
 		igt_require(has_runtime_pm);
 		igt_require(igt_pm_dmc_loaded(data.debugfs_fd));
 		igt_display_require(&data.display, data.drm_fd);
+		/* Make sure our Kernel supports MSR and the module is loaded */
+		igt_require(igt_kmod_load("msr", NULL) == 0);
+
+		data.msr_fd = open("/dev/cpu/0/msr", O_RDONLY);
+		igt_assert_f(data.msr_fd >= 0,
+			     "Can't open /dev/cpu/0/msr.\n");
 	}
 
 	igt_describe("DC5 igt test with PSR Sleep state");
@@ -270,6 +279,8 @@ int main(int argc, char *argv[])
 		psr_enable(data.debugfs_fd, data.op_psr_mode);
 		igt_require_f(edp_psr_sink_support(&data),
 			      "Sink does not support PSR\n");
+		igt_require_f(is_bios_limits_pc8_plus_residencies(data.msr_fd),
+			      "PC8+ residencies not supported\n");
 		test_dc_state_psr(&data, CHECK_DC6);
 	}
 
@@ -280,11 +291,14 @@ int main(int argc, char *argv[])
 
 	igt_describe("DC6 igt test with all connectors DPMS OFF/ON");
 	igt_subtest("dc6-dpms") {
+		igt_require_f(is_bios_limits_pc8_plus_residencies(data.msr_fd),
+			      "PC8+ residencies not supported\n");
 		test_dc_state_dpms(&data, CHECK_DC6);
 	}
 
 	igt_fixture {
 		close(data.debugfs_fd);
+		close(data.msr_fd);
 		display_fini(&data);
 	}
 
-- 
2.7.4

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[igt-dev] [PATCH i-g-t 7/8] igt/i915/i915_pm_dc: DC3CO PSR2 helpers

[Jeevan B]

From: Anshuman Gupta <anshuman.gupta@intel.com>

Add DC3CO IGT validation prerequisites stuff
so a we can enable DC3CO IGT tests.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/i915/i915_pm_dc.c | 63 +++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 58 insertions(+), 5 deletions(-)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 86c12ad..c1b03a9 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -36,6 +36,10 @@
 /* DC State Flags */
 #define CHECK_DC5	1
 #define CHECK_DC6	2
+#define CHECK_DC3CO     4
+
+/* PSR2 status 9th bit is the PSR2 idle frame indication */
+#define PSR2_IDLE_FRMAE_STS_MASK (1 << 9)
 
 typedef struct {
 	int drm_fd;
@@ -88,6 +92,46 @@ static bool edp_psr_sink_support(data_t *data)
 	return strstr(buf, "Sink support: yes");
 }
 
+static bool edp_psr2_enabled(data_t *data)
+
+{
+	char buf[512];
+
+	igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
+				buf, sizeof(buf));
+
+	if (data->op_psr_mode == PSR_MODE_2)
+		return strstr(buf, "PSR mode: PSR2 enabled");
+
+	return false;
+}
+
+static uint32_t get_psr2_status(int debugfs_fd)
+{
+	char buf[512];
+	char *str;
+	uint32_t psr2_sts;
+	int ret;
+
+	igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status",
+				buf, sizeof(buf));
+
+	if (strstr(buf, "PSR mode: PSR2 enabled"))
+		str = strstr(buf, "SLEEP");
+	if (!str)
+		return 0;
+
+	ret = sscanf(str + 6, "%*c%*c%*c%x%*c", &psr2_sts);
+	igt_debug("psr2 status 0x%x\n", psr2_sts);
+	igt_assert_eq(ret, 1);
+}
+
+static bool psr2_idle_wait_entry(int debugfs_fd)
+{
+	return igt_wait((get_psr2_status(debugfs_fd) &
+			PSR2_IDLE_FRMAE_STS_MASK), 500, 20);
+}
+
 static void cleanup_dc_psr(data_t *data)
 {
 	igt_plane_t *primary;
@@ -141,12 +185,18 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
 		str = strstr(buf, "DC3 -> DC5 count");
 	else if (dc_flag & CHECK_DC6)
 		str = strstr(buf, "DC5 -> DC6 count");
+	else if (dc_flag & CHECK_DC3CO)
+		str = strstr(buf, "DC3CO count");
 
-	/* Check DC5/DC6 counter is available for the platform.
+	/* Check DC counter is available for the platform.
 	 * Skip the test if counter is not available.
 	 */
-	igt_skip_on_f(!str, "DC%d counter is not available\n",
-		      dc_flag & CHECK_DC5 ? 5 : 6);
+	if (dc_flag & CHECK_DC3CO)
+		igt_skip_on_f(!str, "DC3CO counter is not available\n");
+	else
+		igt_skip_on_f(!str, "DC%d counter is not available\n",
+			      dc_flag & CHECK_DC5 ? 5 : 6);
+
 	return get_dc_counter(str);
 }
 
@@ -158,9 +208,12 @@ static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
 
 static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
 {
+	char tmp[64];
+
+	snprintf(tmp, sizeof(tmp), "%s", dc_flag & CHECK_DC3CO ? "DC3CO" :
+		 (dc_flag & CHECK_DC5 ? "DC5" : "DC6"));
 	igt_assert_f(dc_state_wait_entry(drm_fd, dc_flag, prev_dc_count),
-		     "DC%d state is not achieved\n",
-		     dc_flag & CHECK_DC5 ? 5 : 6);
+		     "%s state is not achieved\n", tmp);
 }
 
 static void test_dc_state_psr(data_t *data, int dc_flag)
-- 
2.7.4

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[igt-dev] [PATCH i-g-t 8/8] igt/i915/i915_pm_dc: DC3CO Video Playback Case IGT test

[Jeevan B]

Add a subtest for DC3CO video playback case
to generate selective frame update and validate
that system stays in DC3CO state during execution.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/i915_pm_dc.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 134 insertions(+), 4 deletions(-)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index c1b03a9..4fab152 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -38,9 +38,20 @@
 #define CHECK_DC6	2
 #define CHECK_DC3CO     4
 
+/*Number of Frames Video Playback*/
+#define VIDEO_FRAMES 30
+
 /* PSR2 status 9th bit is the PSR2 idle frame indication */
 #define PSR2_IDLE_FRMAE_STS_MASK (1 << 9)
 
+/*Internal */
+typedef struct {
+	double r, g, b;
+} color_t;
+
+igt_fb_t fb1, fb2;
+igt_plane_t *primary;
+
 typedef struct {
 	int drm_fd;
 	int msr_fd;
@@ -124,6 +135,7 @@ static uint32_t get_psr2_status(int debugfs_fd)
 	ret = sscanf(str + 6, "%*c%*c%*c%x%*c", &psr2_sts);
 	igt_debug("psr2 status 0x%x\n", psr2_sts);
 	igt_assert_eq(ret, 1);
+	return psr2_sts;
 }
 
 static bool psr2_idle_wait_entry(int debugfs_fd)
@@ -134,8 +146,6 @@ static bool psr2_idle_wait_entry(int debugfs_fd)
 
 static void cleanup_dc_psr(data_t *data)
 {
-	igt_plane_t *primary;
-
 	primary = igt_output_get_plane_type(data->output,
 					    DRM_PLANE_TYPE_PRIMARY);
 	igt_plane_set_fb(primary, NULL);
@@ -143,10 +153,30 @@ static void cleanup_dc_psr(data_t *data)
 	igt_remove_fb(data->drm_fd, &data->fb_white);
 }
 
-static void setup_primary(data_t *data)
+static void paint_rectangles(data_t *data,
+				drmModeModeInfo *mode,
+				color_t *colors,
+				igt_fb_t *fb)
 {
-	igt_plane_t *primary;
+	cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
+	int i, l = mode->hdisplay / 3;
+	int rows_remaining = mode->hdisplay % 3;
+
+	/* Paint 3 solid rectangles. */
+	for (i = 0 ; i < 3; i++) {
+		igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
+				colors[i].r, colors[i].g, colors[i].b);
+	}
+
+	if (rows_remaining > 0)
+		igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
 
+	colors[i-1].r, colors[i-1].g, colors[i-1].b);
+	igt_put_cairo_ctx(data->drm_fd, fb, cr);
+}
+
+static void setup_primary(data_t *data)
+{
 	primary = igt_output_get_plane_type(data->output,
 					    DRM_PLANE_TYPE_PRIMARY);
 	igt_plane_set_fb(primary, NULL);
@@ -160,6 +190,53 @@ static void setup_primary(data_t *data)
 	igt_display_commit(&data->display);
 }
 
+static void create_rgb_fb(data_t *data)
+{
+	int fb_id1;
+	color_t red_green_blue[] = {
+		{ 1.0, 0.0, 0.0 },
+		{ 0.0, 1.0, 0.0 },
+		{ 0.0, 0.0, 1.0 },
+	};
+
+	primary = igt_output_get_plane_type(data->output,
+					DRM_PLANE_TYPE_PRIMARY);
+
+	igt_plane_set_fb(primary, NULL);
+	fb_id1 = igt_create_fb(data->drm_fd,
+				data->mode->hdisplay,
+				data->mode->vdisplay,
+				DRM_FORMAT_XRGB8888,
+				LOCAL_DRM_FORMAT_MOD_NONE,
+				&fb1);
+	igt_assert(fb_id1);
+	paint_rectangles(data, data->mode, red_green_blue, &fb1);
+}
+
+static void create_rgr_fb(data_t *data)
+{
+	int fb_id2;
+	color_t red_green_red[] = {
+		{ 1.0, 0.0, 0.0 },
+		{ 0.0, 1.0, 0.0 },
+		{ 1.0, 0.0, 0.0 },
+	};
+
+	primary = igt_output_get_plane_type(data->output,
+	DRM_PLANE_TYPE_PRIMARY);
+
+	igt_plane_set_fb(primary, NULL);
+	fb_id2 = igt_create_fb(data->drm_fd,
+				data->mode->hdisplay,
+				data->mode->vdisplay,
+				DRM_FORMAT_XRGB8888,
+				LOCAL_DRM_FORMAT_MOD_NONE,
+				&fb2);
+
+	igt_assert(fb_id2);
+	paint_rectangles(data, data->mode, red_green_red, &fb2);
+}
+
 static uint32_t get_dc_counter(char *dc_data)
 {
 	char *e;
@@ -216,6 +293,49 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
 		     "%s state is not achieved\n", tmp);
 }
 
+static void test_dc3co_vpb_simulation(data_t *data, int dc_flag)
+{
+	uint32_t dc3co_ctr_before_psr, dc3co_ctr_after_psr;
+	uint32_t dc5_ctr_before, dc5_ctr_after;
+	int i, delay;
+
+	setup_output(data);
+
+	create_rgb_fb(data);
+	create_rgr_fb(data);
+
+	igt_plane_set_fb(primary, NULL);
+
+	dc3co_ctr_before_psr = read_dc_counter(data->drm_fd, dc_flag);
+	dc5_ctr_before = read_dc_counter(data->drm_fd, CHECK_DC5);
+	/*Calculate delay to generate idle frame*/
+	delay = ((1000*1000*2)/data->mode->vrefresh);
+
+	for (i = 0; i < VIDEO_FRAMES; i++) {
+		if (i % 2 == 0) {
+			igt_plane_set_fb(primary, &fb1);
+			igt_display_commit(&data->display);
+		} else {
+			igt_plane_set_fb(primary, &fb2);
+			igt_display_commit(&data->display);
+		}
+
+	if (i == 0)
+		igt_assert(psr2_idle_wait_entry(data->debugfs_fd));
+
+	usleep(delay);
+	dc3co_ctr_after_psr = read_dc_counter(data->drm_fd, dc_flag);
+	igt_assert_f(dc3co_ctr_before_psr <= dc3co_ctr_after_psr,
+			"DC3CO counter got reset\n");
+	dc3co_ctr_before_psr = dc3co_ctr_after_psr;
+	}
+
+	dc5_ctr_after = read_dc_counter(data->drm_fd, CHECK_DC5);
+	igt_assert_f(dc5_ctr_after == dc5_ctr_before,
+			"System moved to DC5 state\n");
+	cleanup_dc_psr(data);
+}
+
 static void test_dc_state_psr(data_t *data, int dc_flag)
 {
 	uint32_t dc_counter_before_psr;
@@ -317,6 +437,16 @@ int main(int argc, char *argv[])
 			     "Can't open /dev/cpu/0/msr.\n");
 	}
 
+	igt_describe("DC3CO igt test for Video Playback Scenario");
+	igt_subtest("dc3co-vpb-simulation") {
+		igt_require(IS_TIGERLAKE(data.devid));
+		data.op_psr_mode = PSR_MODE_2;
+		psr_enable(data.debugfs_fd, data.op_psr_mode);
+		igt_require_f(edp_psr2_enabled(&data),
+				"PSR2 is not enabled\n");
+		test_dc3co_vpb_simulation(&data, CHECK_DC3CO);
+	}
+
 	igt_describe("DC5 igt test with PSR Sleep state");
 	igt_subtest("dc5-psr") {
 		data.op_psr_mode = PSR_MODE_1;
-- 
2.7.4

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Re: [igt-dev] [PATCH i-g-t 8/8] igt/i915/i915_pm_dc: DC3CO Video Playback Case IGT test

[Anshuman Gupta]

On 2019-09-12 at 13:46:38 +0530, Jeevan B wrote:
> Add a subtest for DC3CO video playback case
> to generate selective frame update and validate
> that system stays in DC3CO state during execution.
> 
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
>  tests/i915/i915_pm_dc.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 134 insertions(+), 4 deletions(-)
> 
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> index c1b03a9..4fab152 100644
> --- a/tests/i915/i915_pm_dc.c
> +++ b/tests/i915/i915_pm_dc.c
> @@ -38,9 +38,20 @@
>  #define CHECK_DC6	2
>  #define CHECK_DC3CO     4
>  
> +/*Number of Frames Video Playback*/
> +#define VIDEO_FRAMES 30
> +
>  /* PSR2 status 9th bit is the PSR2 idle frame indication */
>  #define PSR2_IDLE_FRMAE_STS_MASK (1 << 9)
>  
> +/*Internal */
> +typedef struct {
> +	double r, g, b;
> +} color_t;
> +
> +igt_fb_t fb1, fb2;
> +igt_plane_t *primary;
> +
>  typedef struct {
>  	int drm_fd;
>  	int msr_fd;
> @@ -124,6 +135,7 @@ static uint32_t get_psr2_status(int debugfs_fd)
>  	ret = sscanf(str + 6, "%*c%*c%*c%x%*c", &psr2_sts);
>  	igt_debug("psr2 status 0x%x\n", psr2_sts);
>  	igt_assert_eq(ret, 1);
> +	return psr2_sts;
could you please make return statement part of previous patch.
>  }
>  
>  static bool psr2_idle_wait_entry(int debugfs_fd)
> @@ -134,8 +146,6 @@ static bool psr2_idle_wait_entry(int debugfs_fd)
>  
>  static void cleanup_dc_psr(data_t *data)
>  {
> -	igt_plane_t *primary;
> -
>  	primary = igt_output_get_plane_type(data->output,
>  					    DRM_PLANE_TYPE_PRIMARY);
>  	igt_plane_set_fb(primary, NULL);
> @@ -143,10 +153,30 @@ static void cleanup_dc_psr(data_t *data)
>  	igt_remove_fb(data->drm_fd, &data->fb_white);
>  }
>  
> -static void setup_primary(data_t *data)
> +static void paint_rectangles(data_t *data,
> +				drmModeModeInfo *mode,
> +				color_t *colors,
> +				igt_fb_t *fb)
>  {
> -	igt_plane_t *primary;
> +	cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
> +	int i, l = mode->hdisplay / 3;
> +	int rows_remaining = mode->hdisplay % 3;
> +
> +	/* Paint 3 solid rectangles. */
> +	for (i = 0 ; i < 3; i++) {
> +		igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
> +				colors[i].r, colors[i].g, colors[i].b);
> +	}
> +
> +	if (rows_remaining > 0)
> +		igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
>  
> +	colors[i-1].r, colors[i-1].g, colors[i-1].b);
> +	igt_put_cairo_ctx(data->drm_fd, fb, cr);
> +}
> +
> +static void setup_primary(data_t *data)
> +{
>  	primary = igt_output_get_plane_type(data->output,
>  					    DRM_PLANE_TYPE_PRIMARY);
>  	igt_plane_set_fb(primary, NULL);
> @@ -160,6 +190,53 @@ static void setup_primary(data_t *data)
>  	igt_display_commit(&data->display);
>  }
>  
> +static void create_rgb_fb(data_t *data)
> +{
> +	int fb_id1;
> +	color_t red_green_blue[] = {
> +		{ 1.0, 0.0, 0.0 },
> +		{ 0.0, 1.0, 0.0 },
> +		{ 0.0, 0.0, 1.0 },
> +	};
> +
> +	primary = igt_output_get_plane_type(data->output,
> +					DRM_PLANE_TYPE_PRIMARY);
> +
> +	igt_plane_set_fb(primary, NULL);
> +	fb_id1 = igt_create_fb(data->drm_fd,
> +				data->mode->hdisplay,
> +				data->mode->vdisplay,
> +				DRM_FORMAT_XRGB8888,
> +				LOCAL_DRM_FORMAT_MOD_NONE,
> +				&fb1);
> +	igt_assert(fb_id1);
> +	paint_rectangles(data, data->mode, red_green_blue, &fb1);
> +}
> +
> +static void create_rgr_fb(data_t *data)
> +{
> +	int fb_id2;
> +	color_t red_green_red[] = {
> +		{ 1.0, 0.0, 0.0 },
> +		{ 0.0, 1.0, 0.0 },
> +		{ 1.0, 0.0, 0.0 },
> +	};
> +
> +	primary = igt_output_get_plane_type(data->output,
> +	DRM_PLANE_TYPE_PRIMARY);
> +
> +	igt_plane_set_fb(primary, NULL);
> +	fb_id2 = igt_create_fb(data->drm_fd,
> +				data->mode->hdisplay,
> +				data->mode->vdisplay,
> +				DRM_FORMAT_XRGB8888,
> +				LOCAL_DRM_FORMAT_MOD_NONE,
> +				&fb2);
> +
> +	igt_assert(fb_id2);
> +	paint_rectangles(data, data->mode, red_green_red, &fb2);
> +}
> +
create_rgr_fb and create_rgb_fb shares most part of code,
could you please create a single function like create_fb
and pass color and other different data to that function.
>  static uint32_t get_dc_counter(char *dc_data)
>  {
>  	char *e;
> @@ -216,6 +293,49 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
>  		     "%s state is not achieved\n", tmp);
>  }
>  
> +static void test_dc3co_vpb_simulation(data_t *data, int dc_flag)
> +{
> +	uint32_t dc3co_ctr_before_psr, dc3co_ctr_after_psr;
> +	uint32_t dc5_ctr_before, dc5_ctr_after;
> +	int i, delay;
> +
> +	setup_output(data);
> +
> +	create_rgb_fb(data);
> +	create_rgr_fb(data);
> +
> +	igt_plane_set_fb(primary, NULL);
> +
> +	dc3co_ctr_before_psr = read_dc_counter(data->drm_fd, dc_flag);
> +	dc5_ctr_before = read_dc_counter(data->drm_fd, CHECK_DC5);
> +	/*Calculate delay to generate idle frame*/
> +	delay = ((1000*1000*2)/data->mode->vrefresh);
> +
> +	for (i = 0; i < VIDEO_FRAMES; i++) {
> +		if (i % 2 == 0) {
> +			igt_plane_set_fb(primary, &fb1);
you can give a meaningfull name to fb1 like fb_rgr
> +			igt_display_commit(&data->display);
> +		} else {
> +			igt_plane_set_fb(primary, &fb2);
> +			igt_display_commit(&data->display);
> +		}
> +
> +	if (i == 0)
> +		igt_assert(psr2_idle_wait_entry(data->debugfs_fd));
> +
> +	usleep(delay);
> +	dc3co_ctr_after_psr = read_dc_counter(data->drm_fd, dc_flag);
> +	igt_assert_f(dc3co_ctr_before_psr <= dc3co_ctr_after_psr,
> +			"DC3CO counter got reset\n");
if both counters are equal then test will pass which is wrong, 
and message should be something like "DC3CO state is not achieved".
better to use check_dc_counter function, after loop ends
and pass the initial counter.
> +	dc3co_ctr_before_psr = dc3co_ctr_after_psr;
> +	}
> +
> +	dc5_ctr_after = read_dc_counter(data->drm_fd, CHECK_DC5);
> +	igt_assert_f(dc5_ctr_after == dc5_ctr_before,
> +			"System moved to DC5 state\n");
> +	cleanup_dc_psr(data);
> +}
> +
>  static void test_dc_state_psr(data_t *data, int dc_flag)
>  {
>  	uint32_t dc_counter_before_psr;
> @@ -317,6 +437,16 @@ int main(int argc, char *argv[])
>  			     "Can't open /dev/cpu/0/msr.\n");
>  	}
>  
> +	igt_describe("DC3CO igt test for Video Playback Scenario");
> +	igt_subtest("dc3co-vpb-simulation") {
> +		igt_require(IS_TIGERLAKE(data.devid));
> +		data.op_psr_mode = PSR_MODE_2;
> +		psr_enable(data.debugfs_fd, data.op_psr_mode);
> +		igt_require_f(edp_psr2_enabled(&data),
> +				"PSR2 is not enabled\n");
> +		test_dc3co_vpb_simulation(&data, CHECK_DC3CO);
> +	}
> +
>  	igt_describe("DC5 igt test with PSR Sleep state");
>  	igt_subtest("dc5-psr") {
>  		data.op_psr_mode = PSR_MODE_1;
> -- 
> 2.7.4
> 
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[igt-dev] ✓ Fi.CI.BAT: success for Add a new IGT test to validate DC3CO state.

[Patchwork]

== Series Details ==

Series: Add a new IGT test to validate DC3CO state.
URL   : https://patchwork.freedesktop.org/series/66648/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6888 -> IGTPW_3454
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/66648/revisions/1/mbox/

Known issues
------------

  Here are the changes found in IGTPW_3454 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_create@basic-files:
    - fi-icl-u3:          [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@gem_ctx_create@basic-files.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/fi-icl-u3/igt@gem_ctx_create@basic-files.html

  
#### Possible fixes ####

  * igt@gem_basic@bad-close:
    - fi-icl-u3:          [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@gem_basic@bad-close.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/fi-icl-u3/igt@gem_basic@bad-close.html

  * igt@gem_ctx_create@basic-files:
    - {fi-tgl-u2}:        [INCOMPLETE][5] -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-tgl-u2/igt@gem_ctx_create@basic-files.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/fi-tgl-u2/igt@gem_ctx_create@basic-files.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [DMESG-WARN][7] ([fdo#102614]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][9] ([fdo#111096]) -> [FAIL][10] ([fdo#111407])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (54 -> 43)
------------------------------

  Missing    (11): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-skl-6770hq fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-skl-lmem fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5179 -> IGTPW_3454

  CI-20190529: 20190529
  CI_DRM_6888: 52e9cd0877ee673ba1bb80c7c7be2e53c0821084 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3454: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/
  IGT_5179: 3374cd0b048f9c277b2815bf80502f9f89680176 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@i915_pm_dc@dc3co-vpb-simulation
+igt@i915_pm_dc@dc5-dpms
+igt@i915_pm_dc@dc5-psr
+igt@i915_pm_dc@dc6-dpms
+igt@i915_pm_dc@dc6-psr

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/
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[igt-dev] ✓ Fi.CI.IGT: success for Add a new IGT test to validate DC3CO state.

[Patchwork]

== Series Details ==

Series: Add a new IGT test to validate DC3CO state.
URL   : https://patchwork.freedesktop.org/series/66648/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6888_full -> IGTPW_3454_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/66648/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3454_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@i915_pm_dc@dc3co-vpb-simulation} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * {igt@i915_pm_dc@dc6-dpms} (NEW):
    - shard-iclb:         NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb1/igt@i915_pm_dc@dc6-dpms.html
    - shard-kbl:          NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-kbl1/igt@i915_pm_dc@dc6-dpms.html

  
New tests
---------

  New tests have been introduced between CI_DRM_6888_full and IGTPW_3454_full:

### New IGT tests (5) ###

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@i915_pm_dc@dc5-dpms:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 2.23] s

  * igt@i915_pm_dc@dc5-psr:
    - Statuses : 1 pass(s) 5 skip(s)
    - Exec time: [0.0, 3.39] s

  * igt@i915_pm_dc@dc6-dpms:
    - Statuses : 2 fail(s) 3 skip(s)
    - Exec time: [0.0, 3.52] s

  * igt@i915_pm_dc@dc6-psr:
    - Statuses : 1 pass(s) 5 skip(s)
    - Exec time: [0.0, 3.50] s

  

Known issues
------------

  Here are the changes found in IGTPW_3454_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_switch@legacy-bsd2-heavy:
    - shard-iclb:         [PASS][4] -> [SKIP][5] ([fdo#109276]) +15 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb4/igt@gem_ctx_switch@legacy-bsd2-heavy.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb8/igt@gem_ctx_switch@legacy-bsd2-heavy.html

  * igt@gem_exec_schedule@wide-bsd:
    - shard-iclb:         [PASS][6] -> [SKIP][7] ([fdo#111325]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb5/igt@gem_exec_schedule@wide-bsd.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-iclb:         [PASS][8] -> [FAIL][9] ([fdo#103167]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-apl:          [PASS][10] -> [DMESG-WARN][11] ([fdo#108566]) +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][12] -> [SKIP][13] ([fdo#109642] / [fdo#111068])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb6/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][14] -> [FAIL][15] ([fdo#108341])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb3/igt@kms_psr@no_drrs.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][16] -> [FAIL][17] ([fdo#99912])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-apl1/igt@kms_setmode@basic.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-apl3/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [DMESG-WARN][18] ([fdo#108566]) -> [PASS][19] +3 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_eio@reset-stress:
    - shard-iclb:         [FAIL][20] ([fdo#109661]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb8/igt@gem_eio@reset-stress.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb7/igt@gem_eio@reset-stress.html

  * igt@gem_exec_schedule@preempt-other-bsd1:
    - shard-iclb:         [SKIP][22] ([fdo#109276]) -> [PASS][23] +21 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb5/igt@gem_exec_schedule@preempt-other-bsd1.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb2/igt@gem_exec_schedule@preempt-other-bsd1.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][24] ([fdo#111325]) -> [PASS][25] +8 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_softpin@softpin:
    - shard-apl:          [INCOMPLETE][26] ([fdo#103927]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-apl5/igt@gem_softpin@softpin.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-apl5/igt@gem_softpin@softpin.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-kbl:          [DMESG-WARN][28] ([fdo#108686]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-kbl2/igt@gem_tiled_swapping@non-threaded.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-kbl2/igt@gem_tiled_swapping@non-threaded.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
    - shard-apl:          [FAIL][30] ([fdo#103232]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
    - shard-kbl:          [FAIL][32] ([fdo#103232]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - shard-hsw:          [FAIL][34] ([fdo#103355]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-hsw:          [INCOMPLETE][36] ([fdo#103540]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-hsw4/igt@kms_flip@2x-flip-vs-fences-interruptible.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-hsw6/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-iclb:         [FAIL][38] ([fdo#103167]) -> [PASS][39] +7 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][40] ([fdo#109441]) -> [PASS][41] +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_vblank@pipe-b-query-forked-hang:
    - shard-iclb:         [INCOMPLETE][42] ([fdo#107713]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb7/igt@kms_vblank@pipe-b-query-forked-hang.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb2/igt@kms_vblank@pipe-b-query-forked-hang.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [FAIL][44] ([fdo#111330]) -> [SKIP][45] ([fdo#109276]) +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/shard-iclb5/igt@gem_mocs_settings@mocs-reset-bsd2.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 6)
------------------------------

  Missing    (4): pig-skl-6260u shard-skl pig-hsw-4770r pig-glk-j5005 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5179 -> IGTPW_3454
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_6888: 52e9cd0877ee673ba1bb80c7c7be2e53c0821084 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3454: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/
  IGT_5179: 3374cd0b048f9c277b2815bf80502f9f89680176 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3454/
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