[igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state.

[igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state.

[Jeevan B]

This test is creating a vpb scenario for
selective frame update and validating
that DC state stays in DC3CO during execution.

Anshuman Gupta (1):
  igt/i915/i915_pm_dc: DC3CO PSR2 helpers

Jeevan B (1):
  Add a new IGT test to validate DC3CO state

 lib/igt_psr.c           |  11 +++
 lib/igt_psr.h           |   1 +
 tests/i915/i915_pm_dc.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++--
 3 files changed, 186 insertions(+), 6 deletions(-)

-- 
2.7.4

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[igt-dev] [PATCH i-g-t 1/2] igt/i915/i915_pm_dc: DC3CO PSR2 helpers

[Jeevan B]

From: Anshuman Gupta <anshuman.gupta@intel.com>

Add DC3CO IGT validation prerequisites stuff
so we can enable DC3CO IGT test.

v2: Removed psr2_idle_wait_entry and get_psr2_status function.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/i915_pm_dc.c | 34 +++++++++++++++++++++++++++++-----
 1 file changed, 29 insertions(+), 5 deletions(-)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index ce3319b..19d8a78 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -36,6 +36,7 @@
 /* DC State Flags */
 #define CHECK_DC5	1
 #define CHECK_DC6	2
+#define CHECK_DC3CO     4
 
 typedef struct {
 	int drm_fd;
@@ -88,6 +89,20 @@ static bool edp_psr_sink_support(data_t *data)
 	return strstr(buf, "Sink support: yes");
 }
 
+static bool edp_psr2_enabled(data_t *data)
+
+{
+	char buf[512];
+
+	igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
+				buf, sizeof(buf));
+
+	if (data->op_psr_mode == PSR_MODE_2)
+		return strstr(buf, "PSR mode: PSR2 enabled");
+
+	return false;
+}
+
 static void cleanup_dc_psr(data_t *data)
 {
 	igt_plane_t *primary;
@@ -141,12 +156,18 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
 		str = strstr(buf, "DC3 -> DC5 count");
 	else if (dc_flag & CHECK_DC6)
 		str = strstr(buf, "DC5 -> DC6 count");
+	else if (dc_flag & CHECK_DC3CO)
+		str = strstr(buf, "DC3CO count");
 
-	/* Check DC5/DC6 counter is available for the platform.
+	/* Check DC counter is available for the platform.
 	 * Skip the test if counter is not available.
 	 */
-	igt_skip_on_f(!str, "DC%d counter is not available\n",
-		      dc_flag & CHECK_DC5 ? 5 : 6);
+	if (dc_flag & CHECK_DC3CO)
+		igt_skip_on_f(!str, "DC3CO counter is not available\n");
+	else
+		igt_skip_on_f(!str, "DC%d counter is not available\n",
+			      dc_flag & CHECK_DC5 ? 5 : 6);
+
 	return get_dc_counter(str);
 }
 
@@ -158,9 +179,12 @@ static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
 
 static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
 {
+	char tmp[64];
+
+	snprintf(tmp, sizeof(tmp), "%s", dc_flag & CHECK_DC3CO ? "DC3CO" :
+		 (dc_flag & CHECK_DC5 ? "DC5" : "DC6"));
 	igt_assert_f(dc_state_wait_entry(drm_fd, dc_flag, prev_dc_count),
-		     "DC%d state is not achieved\n",
-		     dc_flag & CHECK_DC5 ? 5 : 6);
+		     "%s state is not achieved\n", tmp);
 }
 
 static void test_dc_state_psr(data_t *data, int dc_flag)
-- 
2.7.4

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[igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state

[Jeevan B]

Add a subtest for DC3CO video playback case
to generate selective frame update and validate
that system stays in DC3CO state during execution.

v2: Changed PSR2 idle check to sleep check and addressed
cosmetic changes.

v3: Renamed a function and restructured code according
to Anshuman’s comments.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 lib/igt_psr.c           |  11 ++++
 lib/igt_psr.h           |   1 +
 tests/i915/i915_pm_dc.c | 146 +++++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 157 insertions(+), 1 deletion(-)

diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index b92ea73..7806ce9 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -36,6 +36,17 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
 	return strstr(buf, state);
 }
 
+bool psr2_active_sleep_check(int debugfs_fd)
+{
+	char buf[PSR_STATUS_MAX_LEN];
+	const char *state = "SLEEP";
+
+	igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
+				sizeof(buf));
+
+	return strstr(buf, state);
+}
+
 static inline const char *psr_active_state_get(enum psr_mode mode)
 {
 	return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index ca38573..a0627dc 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -35,6 +35,7 @@ enum psr_mode {
 	PSR_MODE_2
 };
 
+bool psr2_active_sleep_check(int debugfs_fd);
 bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
 bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
 bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 19d8a78..dc0a215 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -38,13 +38,20 @@
 #define CHECK_DC6	2
 #define CHECK_DC3CO     4
 
+/*Number of Frames Video Playback*/
+#define VIDEO_FRAMES 100
+
+typedef struct {
+	double r, g, b;
+} color_t;
+
 typedef struct {
 	int drm_fd;
 	int msr_fd;
 	int debugfs_fd;
 	uint32_t devid;
 	igt_display_t display;
-	struct igt_fb fb_white;
+	struct igt_fb fb_white, fb_rgb, fb_rgr;
 	enum psr_mode op_psr_mode;
 	drmModeModeInfo *mode;
 	igt_output_t *output;
@@ -114,6 +121,41 @@ static void cleanup_dc_psr(data_t *data)
 	igt_remove_fb(data->drm_fd, &data->fb_white);
 }
 
+static void cleanup_dc3co(data_t *data)
+{
+	igt_plane_t *primary;
+
+	primary = igt_output_get_plane_type(data->output,
+						DRM_PLANE_TYPE_PRIMARY);
+	igt_plane_set_fb(primary, NULL);
+	/*Clear Frame Buffers*/
+	igt_display_commit(&data->display);
+	igt_remove_fb(data->drm_fd, &data->fb_rgb);
+	igt_remove_fb(data->drm_fd, &data->fb_rgr);
+}
+
+static void paint_rectangles(data_t *data,
+				drmModeModeInfo *mode,
+				color_t *colors,
+				igt_fb_t *fb)
+{
+	cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
+	int i, l = mode->hdisplay / 3;
+	int rows_remaining = mode->hdisplay % 3;
+
+	/* Paint 3 solid rectangles. */
+	for (i = 0 ; i < 3; i++) {
+		igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
+				colors[i].r, colors[i].g, colors[i].b);
+	}
+
+	if (rows_remaining > 0)
+		igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
+				colors[i-1].r, colors[i-1].g, colors[i-1].b);
+
+	igt_put_cairo_ctx(data->drm_fd, fb, cr);
+}
+
 static void setup_primary(data_t *data)
 {
 	igt_plane_t *primary;
@@ -131,6 +173,25 @@ static void setup_primary(data_t *data)
 	igt_display_commit(&data->display);
 }
 
+static void create_clr_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
+{
+	igt_plane_t *primary;
+	int fb_id;
+
+	primary = igt_output_get_plane_type(data->output,
+						DRM_PLANE_TYPE_PRIMARY);
+
+	igt_plane_set_fb(primary, NULL);
+	fb_id = igt_create_fb(data->drm_fd,
+				data->mode->hdisplay,
+				data->mode->vdisplay,
+				DRM_FORMAT_XRGB8888,
+				LOCAL_DRM_FORMAT_MOD_NONE,
+				fb);
+	igt_assert(fb_id);
+	paint_rectangles(data, data->mode, fb_color, fb);
+}
+
 static uint32_t get_dc_counter(char *dc_data)
 {
 	char *e;
@@ -171,6 +232,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
 	return get_dc_counter(str);
 }
 
+static bool psr2_wait_sleep_entry(int debugfs_fd)
+{
+	return igt_wait(psr2_active_sleep_check(debugfs_fd), 50, 10);
+}
+
 static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
 {
 	return igt_wait(read_dc_counter(drm_fd, dc_flag) >
@@ -187,6 +253,77 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
 		     "%s state is not achieved\n", tmp);
 }
 
+static void setup_vpb(data_t *data)
+{
+	color_t red_green_blue[] = {
+		{ 1.0, 0.0, 0.0 },
+		{ 0.0, 1.0, 0.0 },
+		{ 0.0, 0.0, 1.0 },
+	};
+	color_t red_green_red[] = {
+		{ 1.0, 0.0, 0.0 },
+		{ 0.0, 1.0, 0.0 },
+		{ 1.0, 0.0, 0.0 },
+	};
+
+	setup_output(data);
+
+	create_clr_fb(data, &data->fb_rgb, red_green_blue);
+	create_clr_fb(data, &data->fb_rgr, red_green_red);
+}
+
+static void run_videoplayback(data_t *data, int dc_flag)
+{
+	igt_plane_t *primary;
+	uint32_t dc3co_cnt_before_psr;
+	int i, delay;
+
+	primary = igt_output_get_plane_type(data->output,
+						DRM_PLANE_TYPE_PRIMARY);
+
+	igt_plane_set_fb(primary, NULL);
+
+	dc3co_cnt_before_psr = read_dc_counter(data->drm_fd, dc_flag);
+	/*Calculate delay to generate idle frame*/
+	delay = ((1000*1000)/data->mode->vrefresh);
+
+	for (i = 0; i < VIDEO_FRAMES; i++) {
+		if (i % 2 == 0) {
+			igt_plane_set_fb(primary, &data->fb_rgb);
+			igt_display_commit(&data->display);
+		} else {
+			igt_plane_set_fb(primary, &data->fb_rgr);
+			igt_display_commit(&data->display);
+		}
+		usleep(delay);
+		igt_assert(psr2_wait_sleep_entry(data->debugfs_fd));
+	}
+	check_dc_counter(data->drm_fd, dc_flag, dc3co_cnt_before_psr);
+}
+
+static void setup_dc3co(data_t *data)
+{
+	igt_require(IS_TIGERLAKE(data->devid));
+	data->op_psr_mode = PSR_MODE_2;
+	psr_enable(data->debugfs_fd, data->op_psr_mode);
+	igt_require_f(edp_psr2_enabled(data),
+			"PSR2 is not enabled\n");
+}
+
+static void test_dc3co_vpb_simulation(data_t *data, int dc_flag)
+{
+	uint32_t dc5_cnt_before, dc5_cnt_after;
+
+	setup_dc3co(data);
+	setup_vpb(data);
+	dc5_cnt_before = read_dc_counter(data->drm_fd, CHECK_DC5);
+	run_videoplayback(data, dc_flag);
+	dc5_cnt_after = read_dc_counter(data->drm_fd, CHECK_DC5);
+	igt_assert_f(dc5_cnt_after == dc5_cnt_before,
+			"DC State moved to DC5\n");
+	cleanup_dc3co(data);
+}
+
 static void test_dc_state_psr(data_t *data, int dc_flag)
 {
 	uint32_t dc_counter_before_psr;
@@ -288,6 +425,13 @@ int main(int argc, char *argv[])
 			     "Can't open /dev/cpu/0/msr.\n");
 	}
 
+	igt_describe("This test simulate videoplay back "
+		     "in order to validate DC3CO state "
+		     "while PSR2 is active and in SLEEP state");
+	igt_subtest("dc3co-vpb-simulation") {
+		test_dc3co_vpb_simulation(&data, CHECK_DC3CO);
+	}
+
 	igt_describe("This test validates display engine entry to DC5 state "
 		     "while PSR is active");
 	igt_subtest("dc5-psr") {
-- 
2.7.4

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Re: [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO statey

[Anshuman Gupta]

On 2019-10-01 at 17:02:57 +0530, Jeevan B wrote:
> Add a subtest for DC3CO video playback case
> to generate selective frame update and validate
> that system stays in DC3CO state during execution.
> 
> v2: Changed PSR2 idle check to sleep check and addressed
> cosmetic changes.
> 
> v3: Renamed a function and restructured code according
> to Anshuman’s comments.
> 
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
>  lib/igt_psr.c           |  11 ++++
>  lib/igt_psr.h           |   1 +
>  tests/i915/i915_pm_dc.c | 146 +++++++++++++++++++++++++++++++++++++++++++++++-
>  3 files changed, 157 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/igt_psr.c b/lib/igt_psr.c
> index b92ea73..7806ce9 100644
> --- a/lib/igt_psr.c
> +++ b/lib/igt_psr.c
> @@ -36,6 +36,17 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
>  	return strstr(buf, state);
>  }
>  
> +bool psr2_active_sleep_check(int debugfs_fd)
> +{
> +	char buf[PSR_STATUS_MAX_LEN];
> +	const char *state = "SLEEP";
> +
> +	igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
> +				sizeof(buf));
> +
> +	return strstr(buf, state);
> +}
> +
>  static inline const char *psr_active_state_get(enum psr_mode mode)
>  {
>  	return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";
> diff --git a/lib/igt_psr.h b/lib/igt_psr.h
> index ca38573..a0627dc 100644
> --- a/lib/igt_psr.h
> +++ b/lib/igt_psr.h
> @@ -35,6 +35,7 @@ enum psr_mode {
>  	PSR_MODE_2
>  };
>  
> +bool psr2_active_sleep_check(int debugfs_fd);
>  bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
>  bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
>  bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> index 19d8a78..dc0a215 100644
> --- a/tests/i915/i915_pm_dc.c
> +++ b/tests/i915/i915_pm_dc.c
> @@ -38,13 +38,20 @@
>  #define CHECK_DC6	2
>  #define CHECK_DC3CO     4
>  
> +/*Number of Frames Video Playback*/
> +#define VIDEO_FRAMES 100
> +
> +typedef struct {
> +	double r, g, b;
> +} color_t;
> +
>  typedef struct {
>  	int drm_fd;
>  	int msr_fd;
>  	int debugfs_fd;
>  	uint32_t devid;
>  	igt_display_t display;
> -	struct igt_fb fb_white;
> +	struct igt_fb fb_white, fb_rgb, fb_rgr;
>  	enum psr_mode op_psr_mode;
>  	drmModeModeInfo *mode;
>  	igt_output_t *output;
> @@ -114,6 +121,41 @@ static void cleanup_dc_psr(data_t *data)
>  	igt_remove_fb(data->drm_fd, &data->fb_white);
>  }
>  
> +static void cleanup_dc3co(data_t *data)
> +{
> +	igt_plane_t *primary;
> +
> +	primary = igt_output_get_plane_type(data->output,
> +						DRM_PLANE_TYPE_PRIMARY);
	Alignment should should match open parenthesis.
> +	igt_plane_set_fb(primary, NULL);
> +	/*Clear Frame Buffers*/
> +	igt_display_commit(&data->display);
> +	igt_remove_fb(data->drm_fd, &data->fb_rgb);
> +	igt_remove_fb(data->drm_fd, &data->fb_rgr);
> +}
> +
> +static void paint_rectangles(data_t *data,
> +				drmModeModeInfo *mode,
> +				color_t *colors,
> +				igt_fb_t *fb)
> +{
> +	cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
> +	int i, l = mode->hdisplay / 3;
> +	int rows_remaining = mode->hdisplay % 3;
> +
> +	/* Paint 3 solid rectangles. */
> +	for (i = 0 ; i < 3; i++) {
> +		igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
> +				colors[i].r, colors[i].g, colors[i].b);
> +	}
> +
> +	if (rows_remaining > 0)
> +		igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
> +				colors[i-1].r, colors[i-1].g, colors[i-1].b);
Space required before - and after - operator.
> +
> +	igt_put_cairo_ctx(data->drm_fd, fb, cr);
> +}
> +
>  static void setup_primary(data_t *data)
>  {
>  	igt_plane_t *primary;
> @@ -131,6 +173,25 @@ static void setup_primary(data_t *data)
>  	igt_display_commit(&data->display);
>  }
>  
> +static void create_clr_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
How about name create_color_fb ?
> +{
> +	igt_plane_t *primary;
> +	int fb_id;
> +
> +	primary = igt_output_get_plane_type(data->output,
> +						DRM_PLANE_TYPE_PRIMARY);
Alignment should should match open parenthesis.
> +
> +	igt_plane_set_fb(primary, NULL);
> +	fb_id = igt_create_fb(data->drm_fd,
Alignment should should match open parenthesis.
> +				data->mode->hdisplay,
> +				data->mode->vdisplay,
> +				DRM_FORMAT_XRGB8888,
> +				LOCAL_DRM_FORMAT_MOD_NONE,
> +				fb);
> +	igt_assert(fb_id);
> +	paint_rectangles(data, data->mode, fb_color, fb);
> +}
> +
>  static uint32_t get_dc_counter(char *dc_data)
>  {
>  	char *e;
> @@ -171,6 +232,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
>  	return get_dc_counter(str);
>  }
>  
> +static bool psr2_wait_sleep_entry(int debugfs_fd)
> +{
> +	return igt_wait(psr2_active_sleep_check(debugfs_fd), 50, 10);
> +}
> +
>  static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
>  {
>  	return igt_wait(read_dc_counter(drm_fd, dc_flag) >
> @@ -187,6 +253,77 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
>  		     "%s state is not achieved\n", tmp);
>  }
>  
> +static void setup_vpb(data_t *data)
> +{
> +	color_t red_green_blue[] = {
> +		{ 1.0, 0.0, 0.0 },
> +		{ 0.0, 1.0, 0.0 },
> +		{ 0.0, 0.0, 1.0 },
> +	};
> +	color_t red_green_red[] = {
> +		{ 1.0, 0.0, 0.0 },
> +		{ 0.0, 1.0, 0.0 },
> +		{ 1.0, 0.0, 0.0 },
> +	};
> +
> +	setup_output(data);
> +
> +	create_clr_fb(data, &data->fb_rgb, red_green_blue);
> +	create_clr_fb(data, &data->fb_rgr, red_green_red);
> +}
> +
> +static void run_videoplayback(data_t *data, int dc_flag)
> +{
> +	igt_plane_t *primary;
> +	uint32_t dc3co_cnt_before_psr;
I think dc3co_prev_cnt is better name.
> +	int i, delay;
> +
> +	primary = igt_output_get_plane_type(data->output,
> +						DRM_PLANE_TYPE_PRIMARY);
Alignment should should match open parenthesis.
> +
> +	igt_plane_set_fb(primary, NULL);
> +
> +	dc3co_cnt_before_psr = read_dc_counter(data->drm_fd, dc_flag);
> +	/*Calculate delay to generate idle frame*/
Better to use space like  /* Comment */ 
> +	delay = ((1000*1000)/data->mode->vrefresh);
Space require befor and after * and / operator.
> +
> +	for (i = 0; i < VIDEO_FRAMES; i++) {
> +		if (i % 2 == 0) {
> +			igt_plane_set_fb(primary, &data->fb_rgb);
> +			igt_display_commit(&data->display);
> +		} else {
> +			igt_plane_set_fb(primary, &data->fb_rgr);
> +			igt_display_commit(&data->display);
> +		}
> +		usleep(delay);
> +		igt_assert(psr2_wait_sleep_entry(data->debugfs_fd));
> +	}
> +	check_dc_counter(data->drm_fd, dc_flag, dc3co_cnt_before_psr);
> +}
> +
> +static void setup_dc3co(data_t *data)
> +{
> +	igt_require(IS_TIGERLAKE(data->devid));
> +	data->op_psr_mode = PSR_MODE_2;
> +	psr_enable(data->debugfs_fd, data->op_psr_mode);
> +	igt_require_f(edp_psr2_enabled(data),
> +			"PSR2 is not enabled\n");
Alignment should should match open parenthesis.
> +}
> +
> +static void test_dc3co_vpb_simulation(data_t *data, int dc_flag)
> +{
> +	uint32_t dc5_cnt_before, dc5_cnt_after;
> +
> +	setup_dc3co(data);
> +	setup_vpb(data);
> +	dc5_cnt_before = read_dc_counter(data->drm_fd, CHECK_DC5);
> +	run_videoplayback(data, dc_flag);
> +	dc5_cnt_after = read_dc_counter(data->drm_fd, CHECK_DC5);
> +	igt_assert_f(dc5_cnt_after == dc5_cnt_before,
> +			"DC State moved to DC5\n");
Alignment should should match open parenthesis.
you can run below command to check the coding guideline warnings.
git show --format=email HEAD | ~/$DRM_TIP_PATH/scripts/checkpatch.pl --strict
> +	cleanup_dc3co(data);
> +}
> +
>  static void test_dc_state_psr(data_t *data, int dc_flag)
>  {
>  	uint32_t dc_counter_before_psr;
> @@ -288,6 +425,13 @@ int main(int argc, char *argv[])
>  			     "Can't open /dev/cpu/0/msr.\n");
>  	}
>  
> +	igt_describe("This test simulate videoplay back "
					it shouls be video playback
Functionality wise the patch looks good to me, i will provide my
RB after fixing the coding guideline error.
Thanks,
Anshuman Gupta. 						
> +		     "in order to validate DC3CO state "
> +		     "while PSR2 is active and in SLEEP state");
> +	igt_subtest("dc3co-vpb-simulation") {
> +		test_dc3co_vpb_simulation(&data, CHECK_DC3CO);
> +	}
> +
>  	igt_describe("This test validates display engine entry to DC5 state "
>  		     "while PSR is active");
>  	igt_subtest("dc5-psr") {
> -- 
> 2.7.4
> 
_______________________________________________
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[igt-dev] ✓ Fi.CI.BAT: success for Add a new IGT test to validate DC3CO state. (rev3)

[Patchwork]

== Series Details ==

Series: Add a new IGT test to validate DC3CO state. (rev3)
URL   : https://patchwork.freedesktop.org/series/66648/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6982 -> IGTPW_3518
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/66648/revisions/3/mbox/

Known issues
------------

  Here are the changes found in IGTPW_3518 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-guc:         [PASS][1] -> [INCOMPLETE][2] ([fdo#106070] / [fdo#111700])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html

  * igt@i915_selftest@live_sanitycheck:
    - fi-icl-u3:          [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-read:
    - fi-icl-u3:          [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/fi-icl-u3/igt@gem_mmap_gtt@basic-read.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/fi-icl-u3/igt@gem_mmap_gtt@basic-read.html

  * igt@i915_module_load@reload-with-fault-injection:
    - {fi-icl-guc}:       [DMESG-WARN][7] ([fdo#106107]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/fi-icl-guc/igt@i915_module_load@reload-with-fault-injection.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/fi-icl-guc/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-skl-iommu:       [INCOMPLETE][9] ([fdo#111700]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/fi-skl-iommu/igt@i915_selftest@live_gem_contexts.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/fi-skl-iommu/igt@i915_selftest@live_gem_contexts.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][11] ([fdo#111407]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
  [fdo#111700]: https://bugs.freedesktop.org/show_bug.cgi?id=111700
  [fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831


Participating hosts (51 -> 47)
------------------------------

  Additional (1): fi-bsw-n3050 
  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5208 -> IGTPW_3518

  CI-20190529: 20190529
  CI_DRM_6982: 328a82d454d71506a156d389da4cba24f9ae3a34 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3518: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/index.html
  IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@i915_pm_dc@dc3co-vpb-simulation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✗ Fi.CI.IGT: failure for Add a new IGT test to validate DC3CO state. (rev3)

[Patchwork]

== Series Details ==

Series: Add a new IGT test to validate DC3CO state. (rev3)
URL   : https://patchwork.freedesktop.org/series/66648/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6982_full -> IGTPW_3518_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3518_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3518_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3518_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@i915_pm_dc@dc3co-vpb-simulation} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html

  
New tests
---------

  New tests have been introduced between CI_DRM_6982_full and IGTPW_3518_full:

### New IGT tests (1) ###

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_3518_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [PASS][2] -> [DMESG-WARN][3] ([fdo#108566]) +3 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-apl1/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [PASS][4] -> [SKIP][5] ([fdo#109276]) +10 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb2/igt@gem_exec_schedule@out-order-bsd2.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [PASS][6] -> [SKIP][7] ([fdo#111325]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb1/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-snb:          [PASS][8] -> [DMESG-WARN][9] ([fdo#111870]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-snb5/igt@gem_userptr_blits@coherency-sync.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-snb5/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-kbl:          [PASS][10] -> [DMESG-WARN][11] ([fdo#111870]) +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-kbl1/igt@gem_userptr_blits@dmabuf-sync.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-kbl2/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
    - shard-iclb:         [PASS][12] -> [DMESG-WARN][13] ([fdo#111870]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb3/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
    - shard-hsw:          [PASS][14] -> [DMESG-WARN][15] ([fdo#111870])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-iclb:         [PASS][16] -> [FAIL][17] ([fdo#103167]) +2 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_plane_cursor@pipe-a-primary-size-128:
    - shard-hsw:          [PASS][18] -> [INCOMPLETE][19] ([fdo#103540]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-hsw7/igt@kms_plane_cursor@pipe-a-primary-size-128.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-hsw8/igt@kms_plane_cursor@pipe-a-primary-size-128.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][20] -> [FAIL][21] ([fdo#103166])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][22] -> [SKIP][23] ([fdo#109441]) +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][24] ([fdo#111325]) -> [PASS][25] +8 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-kbl:          [DMESG-WARN][26] ([fdo#108686]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-kbl6/igt@gem_tiled_swapping@non-threaded.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-kbl3/igt@gem_tiled_swapping@non-threaded.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-hsw:          [DMESG-WARN][28] ([fdo#111870]) -> [PASS][29] +3 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-hsw7/igt@gem_userptr_blits@coherency-sync.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-hsw1/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-snb:          [DMESG-WARN][30] ([fdo#111870]) -> [PASS][31] +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
    - shard-kbl:          [DMESG-WARN][32] ([fdo#111870]) -> [PASS][33] +2 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-kbl1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-kbl7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-apl:          [DMESG-WARN][34] ([fdo#109385] / [fdo#111870]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-apl7/igt@gem_userptr_blits@sync-unmap-after-close.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-apl4/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-glk:          [DMESG-WARN][36] ([fdo#111870]) -> [PASS][37] +2 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-glk2/igt@gem_userptr_blits@sync-unmap-cycles.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-glk7/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [DMESG-WARN][38] ([fdo#108566]) -> [PASS][39] +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-apl7/igt@i915_suspend@sysfs-reader.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-apl6/igt@i915_suspend@sysfs-reader.html
    - shard-kbl:          [INCOMPLETE][40] ([fdo#103665] / [fdo#108767]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-kbl3/igt@i915_suspend@sysfs-reader.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-kbl1/igt@i915_suspend@sysfs-reader.html

  * igt@kms_flip@dpms-vs-vblank-race-interruptible:
    - shard-iclb:         [INCOMPLETE][42] ([fdo#107713]) -> [PASS][43] +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb7/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb6/igt@kms_flip@dpms-vs-vblank-race-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [FAIL][44] ([fdo#103167]) -> [PASS][45] +8 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][46] ([fdo#109441]) -> [PASS][47] +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-kbl:          [INCOMPLETE][48] ([fdo#103665]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-kbl3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-kbl6/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][50] ([fdo#109276]) -> [PASS][51] +13 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb5/igt@prime_busy@hang-bsd2.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb2/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-isolation-bsd2:
    - shard-iclb:         [SKIP][52] ([fdo#109276]) -> [FAIL][53] ([fdo#111330])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb7/igt@gem_mocs_settings@mocs-isolation-bsd2.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [FAIL][54] ([fdo#111330]) -> [SKIP][55] ([fdo#109276])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb8/igt@gem_mocs_settings@mocs-settings-bsd2.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870


Participating hosts (16 -> 6)
------------------------------

  ERROR: It appears as if the changes made in IGTPW_3518_full prevented too many machines from booting.

  Missing    (10): shard-skl pig-hsw-4770r shard-tglb1 shard-tglb2 shard-tglb3 shard-tglb4 shard-tglb5 shard-tglb6 pig-glk-j5005 pig-skl-6260u 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5208 -> IGTPW_3518
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_6982: 328a82d454d71506a156d389da4cba24f9ae3a34 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3518: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/index.html
  IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] ✗ Fi.CI.IGT: failure for Add a new IGT test to validate DC3CO state. (rev3)

[Anshuman Gupta]

On 2019-10-01 at 17:58:57 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: Add a new IGT test to validate DC3CO state. (rev3)
> URL   : https://patchwork.freedesktop.org/series/66648/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_6982_full -> IGTPW_3518_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with IGTPW_3518_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in IGTPW_3518_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/index.html
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in IGTPW_3518_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * {igt@i915_pm_dc@dc3co-vpb-simulation} (NEW):
>     - shard-iclb:         NOTRUN -> [SKIP][1]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
> 
>   
> New tests
> ---------
> 
>   New tests have been introduced between CI_DRM_6982_full and IGTPW_3518_full:
> 
> ### New IGT tests (1) ###
> 
>   * igt@i915_pm_dc@dc3co-vpb-simulation:
>     - Statuses : 6 skip(s)
>     - Exec time: [0.0] s
Hi Jeevan,

There is no single run on TGL for DC3CO igt test.
Could you please add this test to tests/intel-ci/fast-feedback.testlist list, then it will cover TGL platforms in CI.
You can add simply a line igt@i915_pm_dc@dc3co-vpb-simulation in tests/intel-ci/fast-feedback.testlist and create a patch with DO_NOT_MERGE tag, and send along with this series.

Thanks,
Anshuman Gupta.
> 
>   
> 
> Known issues
> ------------
> 
>   Here are the changes found in IGTPW_3518_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_ctx_isolation@rcs0-s3:
>     - shard-apl:          [PASS][2] -> [DMESG-WARN][3] ([fdo#108566]) +3 similar issues
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-apl1/igt@gem_ctx_isolation@rcs0-s3.html
> 
>   * igt@gem_exec_schedule@out-order-bsd2:
>     - shard-iclb:         [PASS][4] -> [SKIP][5] ([fdo#109276]) +10 similar issues
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb2/igt@gem_exec_schedule@out-order-bsd2.html
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html
> 
>   * igt@gem_exec_schedule@reorder-wide-bsd:
>     - shard-iclb:         [PASS][6] -> [SKIP][7] ([fdo#111325]) +2 similar issues
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb1/igt@gem_exec_schedule@reorder-wide-bsd.html
> 
>   * igt@gem_userptr_blits@coherency-sync:
>     - shard-snb:          [PASS][8] -> [DMESG-WARN][9] ([fdo#111870]) +2 similar issues
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-snb5/igt@gem_userptr_blits@coherency-sync.html
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-snb5/igt@gem_userptr_blits@coherency-sync.html
> 
>   * igt@gem_userptr_blits@dmabuf-sync:
>     - shard-kbl:          [PASS][10] -> [DMESG-WARN][11] ([fdo#111870]) +2 similar issues
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-kbl1/igt@gem_userptr_blits@dmabuf-sync.html
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-kbl2/igt@gem_userptr_blits@dmabuf-sync.html
> 
>   * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
>     - shard-iclb:         [PASS][12] -> [DMESG-WARN][13] ([fdo#111870]) +1 similar issue
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb3/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
>     - shard-hsw:          [PASS][14] -> [DMESG-WARN][15] ([fdo#111870])
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
>     - shard-iclb:         [PASS][16] -> [FAIL][17] ([fdo#103167]) +2 similar issues
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
> 
>   * igt@kms_plane_cursor@pipe-a-primary-size-128:
>     - shard-hsw:          [PASS][18] -> [INCOMPLETE][19] ([fdo#103540]) +1 similar issue
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-hsw7/igt@kms_plane_cursor@pipe-a-primary-size-128.html
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-hsw8/igt@kms_plane_cursor@pipe-a-primary-size-128.html
> 
>   * igt@kms_plane_lowres@pipe-a-tiling-x:
>     - shard-iclb:         [PASS][20] -> [FAIL][21] ([fdo#103166])
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-x.html
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
> 
>   * igt@kms_psr@psr2_primary_mmap_gtt:
>     - shard-iclb:         [PASS][22] -> [SKIP][23] ([fdo#109441]) +1 similar issue
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_exec_schedule@preemptive-hang-bsd:
>     - shard-iclb:         [SKIP][24] ([fdo#111325]) -> [PASS][25] +8 similar issues
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
> 
>   * igt@gem_tiled_swapping@non-threaded:
>     - shard-kbl:          [DMESG-WARN][26] ([fdo#108686]) -> [PASS][27]
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-kbl6/igt@gem_tiled_swapping@non-threaded.html
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-kbl3/igt@gem_tiled_swapping@non-threaded.html
> 
>   * igt@gem_userptr_blits@coherency-sync:
>     - shard-hsw:          [DMESG-WARN][28] ([fdo#111870]) -> [PASS][29] +3 similar issues
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-hsw7/igt@gem_userptr_blits@coherency-sync.html
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-hsw1/igt@gem_userptr_blits@coherency-sync.html
> 
>   * igt@gem_userptr_blits@map-fixed-invalidate-busy:
>     - shard-snb:          [DMESG-WARN][30] ([fdo#111870]) -> [PASS][31] +2 similar issues
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
>     - shard-kbl:          [DMESG-WARN][32] ([fdo#111870]) -> [PASS][33] +2 similar issues
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-kbl1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-kbl7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
> 
>   * igt@gem_userptr_blits@sync-unmap-after-close:
>     - shard-apl:          [DMESG-WARN][34] ([fdo#109385] / [fdo#111870]) -> [PASS][35]
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-apl7/igt@gem_userptr_blits@sync-unmap-after-close.html
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-apl4/igt@gem_userptr_blits@sync-unmap-after-close.html
> 
>   * igt@gem_userptr_blits@sync-unmap-cycles:
>     - shard-glk:          [DMESG-WARN][36] ([fdo#111870]) -> [PASS][37] +2 similar issues
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-glk2/igt@gem_userptr_blits@sync-unmap-cycles.html
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-glk7/igt@gem_userptr_blits@sync-unmap-cycles.html
> 
>   * igt@i915_suspend@sysfs-reader:
>     - shard-apl:          [DMESG-WARN][38] ([fdo#108566]) -> [PASS][39] +2 similar issues
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-apl7/igt@i915_suspend@sysfs-reader.html
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-apl6/igt@i915_suspend@sysfs-reader.html
>     - shard-kbl:          [INCOMPLETE][40] ([fdo#103665] / [fdo#108767]) -> [PASS][41]
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-kbl3/igt@i915_suspend@sysfs-reader.html
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-kbl1/igt@i915_suspend@sysfs-reader.html
> 
>   * igt@kms_flip@dpms-vs-vblank-race-interruptible:
>     - shard-iclb:         [INCOMPLETE][42] ([fdo#107713]) -> [PASS][43] +1 similar issue
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb7/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb6/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
>     - shard-iclb:         [FAIL][44] ([fdo#103167]) -> [PASS][45] +8 similar issues
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
> 
>   * igt@kms_psr@psr2_cursor_mmap_cpu:
>     - shard-iclb:         [SKIP][46] ([fdo#109441]) -> [PASS][47] +1 similar issue
>    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
> 
>   * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
>     - shard-kbl:          [INCOMPLETE][48] ([fdo#103665]) -> [PASS][49]
>    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-kbl3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-kbl6/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
> 
>   * igt@prime_busy@hang-bsd2:
>     - shard-iclb:         [SKIP][50] ([fdo#109276]) -> [PASS][51] +13 similar issues
>    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb5/igt@prime_busy@hang-bsd2.html
>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb2/igt@prime_busy@hang-bsd2.html
> 
>   
> #### Warnings ####
> 
>   * igt@gem_mocs_settings@mocs-isolation-bsd2:
>     - shard-iclb:         [SKIP][52] ([fdo#109276]) -> [FAIL][53] ([fdo#111330])
>    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb7/igt@gem_mocs_settings@mocs-isolation-bsd2.html
>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
> 
>   * igt@gem_mocs_settings@mocs-settings-bsd2:
>     - shard-iclb:         [FAIL][54] ([fdo#111330]) -> [SKIP][55] ([fdo#109276])
>    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/shard-iclb8/igt@gem_mocs_settings@mocs-settings-bsd2.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
>   [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>   [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
>   [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
>   [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
>   [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
>   [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
>   [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
>   [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
>   [fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
>   [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
>   [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
>   [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
>   [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
> 
> 
> Participating hosts (16 -> 6)
> ------------------------------
> 
>   ERROR: It appears as if the changes made in IGTPW_3518_full prevented too many machines from booting.
> 
>   Missing    (10): shard-skl pig-hsw-4770r shard-tglb1 shard-tglb2 shard-tglb3 shard-tglb4 shard-tglb5 shard-tglb6 pig-glk-j5005 pig-skl-6260u 
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * IGT: IGT_5208 -> IGTPW_3518
>   * Piglit: piglit_4509 -> None
> 
>   CI-20190529: 20190529
>   CI_DRM_6982: 328a82d454d71506a156d389da4cba24f9ae3a34 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGTPW_3518: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/index.html
>   IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3518/index.html
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state.

[Jeevan B]

This test is creating a vpb scenario for
selective frame update and validating
that DC state stays in DC3CO during execution.

Anshuman Gupta (1):
  igt/i915/i915_pm_dc: DC3CO PSR2 helpers

Jeevan B (1):
  Add a new IGT test to validate DC3CO state

 lib/igt_psr.c           |  10 +++
 lib/igt_psr.h           |   1 +
 tests/i915/i915_pm_dc.c | 172 +++++++++++++++++++++++++++++++++++++++++++++---
 3 files changed, 175 insertions(+), 8 deletions(-)

-- 
2.7.4

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[igt-dev] [PATCH i-g-t 1/2] igt/i915/i915_pm_dc: DC3CO PSR2 helpers

[Jeevan B]

From: Anshuman Gupta <anshuman.gupta@intel.com>

Add DC3CO IGT validation prerequisites stuff
so we can enable DC3CO IGT test.

v2: Removed psr2_idle_wait_entry and get_psr2_status function.

v3: Changed macro definition and removed extra line.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/i915_pm_dc.c | 37 ++++++++++++++++++++++++++++++-------
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index ce3319b..0ddd6b3 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -34,8 +34,9 @@
 #include "limits.h"
 
 /* DC State Flags */
-#define CHECK_DC5	1
-#define CHECK_DC6	2
+#define CHECK_DC5	(1 << 0)
+#define CHECK_DC6	(1 << 1)
+#define CHECK_DC3CO	(1 << 2)
 
 typedef struct {
 	int drm_fd;
@@ -88,6 +89,19 @@ static bool edp_psr_sink_support(data_t *data)
 	return strstr(buf, "Sink support: yes");
 }
 
+static bool edp_psr2_enabled(data_t *data)
+{
+	char buf[512];
+
+	igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
+				buf, sizeof(buf));
+
+	if (data->op_psr_mode == PSR_MODE_2)
+		return strstr(buf, "PSR mode: PSR2 enabled");
+
+	return false;
+}
+
 static void cleanup_dc_psr(data_t *data)
 {
 	igt_plane_t *primary;
@@ -141,12 +155,18 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
 		str = strstr(buf, "DC3 -> DC5 count");
 	else if (dc_flag & CHECK_DC6)
 		str = strstr(buf, "DC5 -> DC6 count");
+	else if (dc_flag & CHECK_DC3CO)
+		str = strstr(buf, "DC3CO count");
 
-	/* Check DC5/DC6 counter is available for the platform.
+	/* Check DC counter is available for the platform.
 	 * Skip the test if counter is not available.
 	 */
-	igt_skip_on_f(!str, "DC%d counter is not available\n",
-		      dc_flag & CHECK_DC5 ? 5 : 6);
+	if (dc_flag & CHECK_DC3CO)
+		igt_skip_on_f(!str, "DC3CO counter is not available\n");
+	else
+		igt_skip_on_f(!str, "DC%d counter is not available\n",
+			      dc_flag & CHECK_DC5 ? 5 : 6);
+
 	return get_dc_counter(str);
 }
 
@@ -158,9 +178,12 @@ static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
 
 static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
 {
+	char tmp[64];
+
+	snprintf(tmp, sizeof(tmp), "%s", dc_flag & CHECK_DC3CO ? "DC3CO" :
+		 (dc_flag & CHECK_DC5 ? "DC5" : "DC6"));
 	igt_assert_f(dc_state_wait_entry(drm_fd, dc_flag, prev_dc_count),
-		     "DC%d state is not achieved\n",
-		     dc_flag & CHECK_DC5 ? 5 : 6);
+		     "%s state is not achieved\n", tmp);
 }
 
 static void test_dc_state_psr(data_t *data, int dc_flag)
-- 
2.7.4

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Re: [igt-dev] [PATCH i-g-t 1/2] igt/i915/i915_pm_dc: DC3CO PSR2 helpers

[Arkadiusz Hiler]

On Thu, Oct 17, 2019 at 04:04:59PM +0530, Jeevan B wrote:
> ontent-Length: 2643
> 
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> 
> Add DC3CO IGT validation prerequisites stuff
> so we can enable DC3CO IGT test.
> 
> v2: Removed psr2_idle_wait_entry and get_psr2_status function.
> 
> v3: Changed macro definition and removed extra line.
> 
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
>  tests/i915/i915_pm_dc.c | 37 ++++++++++++++++++++++++++++++-------
>  1 file changed, 30 insertions(+), 7 deletions(-)
> 
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> index ce3319b..0ddd6b3 100644
> --- a/tests/i915/i915_pm_dc.c
> +++ b/tests/i915/i915_pm_dc.c
> @@ -34,8 +34,9 @@
>  #include "limits.h"
>  
>  /* DC State Flags */
> -#define CHECK_DC5	1
> -#define CHECK_DC6	2
> +#define CHECK_DC5	(1 << 0)
> +#define CHECK_DC6	(1 << 1)
> +#define CHECK_DC3CO	(1 << 2)
>  
>  typedef struct {
>  	int drm_fd;
> @@ -88,6 +89,19 @@ static bool edp_psr_sink_support(data_t *data)
>  	return strstr(buf, "Sink support: yes");
>  }
>  
> +static bool edp_psr2_enabled(data_t *data)
> +{
> +	char buf[512];
> +
> +	igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
> +				buf, sizeof(buf));
> +
> +	if (data->op_psr_mode == PSR_MODE_2)
> +		return strstr(buf, "PSR mode: PSR2 enabled");

This looks like a helper function to check whether we have PSR2 enabled,
so I don't quite get why we have this if here.

It's either enabled or not and some internal state of data struct should
not affect it.

> +
> +	return false;
> +}
> +
>  static void cleanup_dc_psr(data_t *data)
>  {
>  	igt_plane_t *primary;
> @@ -141,12 +155,18 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
>  		str = strstr(buf, "DC3 -> DC5 count");
>  	else if (dc_flag & CHECK_DC6)
>  		str = strstr(buf, "DC5 -> DC6 count");
> +	else if (dc_flag & CHECK_DC3CO)
> +		str = strstr(buf, "DC3CO count");
>  
> -	/* Check DC5/DC6 counter is available for the platform.
> +	/* Check DC counter is available for the platform.
>  	 * Skip the test if counter is not available.
>  	 */
> -	igt_skip_on_f(!str, "DC%d counter is not available\n",
> -		      dc_flag & CHECK_DC5 ? 5 : 6);
> +	if (dc_flag & CHECK_DC3CO)
> +		igt_skip_on_f(!str, "DC3CO counter is not available\n");
> +	else
> +		igt_skip_on_f(!str, "DC%d counter is not available\n",
> +			      dc_flag & CHECK_DC5 ? 5 : 6);
> +
>  	return get_dc_counter(str);
>  }
>  
> @@ -158,9 +178,12 @@ static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
>  
>  static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
>  {
> +	char tmp[64];
> +
> +	snprintf(tmp, sizeof(tmp), "%s", dc_flag & CHECK_DC3CO ? "DC3CO" :
> +		 (dc_flag & CHECK_DC5 ? "DC5" : "DC6"));
>  	igt_assert_f(dc_state_wait_entry(drm_fd, dc_flag, prev_dc_count),
> -		     "DC%d state is not achieved\n",
> -		     dc_flag & CHECK_DC5 ? 5 : 6);
> +		     "%s state is not achieved\n", tmp);
>  }
>  
>  static void test_dc_state_psr(data_t *data, int
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[igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state.

[Jeevan B]

This test is creating a vpb scenario for
selective frame update and validating 
that DC state stays in DC3CO during execution.

Anshuman Gupta (1):
  igt/i915/i915_pm_dc: DC3CO PSR2 helpers

Jeevan B (1):
  Add a new IGT test to validate DC3CO state

 lib/igt_psr.c           |  11 +++
 lib/igt_psr.h           |   1 +
 tests/i915/i915_pm_dc.c | 181 +++++++++++++++++++++++++++++++++++++++++++++---
 3 files changed, 183 insertions(+), 10 deletions(-)

-- 
2.7.4

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[igt-dev] [PATCH i-g-t 1/2] igt/i915/i915_pm_dc: DC3CO PSR2 helpers

[Jeevan B]

From: Anshuman Gupta <anshuman.gupta@intel.com>

Add DC3CO IGT validation prerequisites stuff
so we can enable DC3CO IGT test.

v2: Removed psr2_idle_wait_entry and get_psr2_status function.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/i915_pm_dc.c | 34 +++++++++++++++++++++++++++++-----
 1 file changed, 29 insertions(+), 5 deletions(-)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index ce3319b..19d8a78 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -36,6 +36,7 @@
 /* DC State Flags */
 #define CHECK_DC5	1
 #define CHECK_DC6	2
+#define CHECK_DC3CO     4
 
 typedef struct {
 	int drm_fd;
@@ -88,6 +89,20 @@ static bool edp_psr_sink_support(data_t *data)
 	return strstr(buf, "Sink support: yes");
 }
 
+static bool edp_psr2_enabled(data_t *data)
+
+{
+	char buf[512];
+
+	igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
+				buf, sizeof(buf));
+
+	if (data->op_psr_mode == PSR_MODE_2)
+		return strstr(buf, "PSR mode: PSR2 enabled");
+
+	return false;
+}
+
 static void cleanup_dc_psr(data_t *data)
 {
 	igt_plane_t *primary;
@@ -141,12 +156,18 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
 		str = strstr(buf, "DC3 -> DC5 count");
 	else if (dc_flag & CHECK_DC6)
 		str = strstr(buf, "DC5 -> DC6 count");
+	else if (dc_flag & CHECK_DC3CO)
+		str = strstr(buf, "DC3CO count");
 
-	/* Check DC5/DC6 counter is available for the platform.
+	/* Check DC counter is available for the platform.
 	 * Skip the test if counter is not available.
 	 */
-	igt_skip_on_f(!str, "DC%d counter is not available\n",
-		      dc_flag & CHECK_DC5 ? 5 : 6);
+	if (dc_flag & CHECK_DC3CO)
+		igt_skip_on_f(!str, "DC3CO counter is not available\n");
+	else
+		igt_skip_on_f(!str, "DC%d counter is not available\n",
+			      dc_flag & CHECK_DC5 ? 5 : 6);
+
 	return get_dc_counter(str);
 }
 
@@ -158,9 +179,12 @@ static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
 
 static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
 {
+	char tmp[64];
+
+	snprintf(tmp, sizeof(tmp), "%s", dc_flag & CHECK_DC3CO ? "DC3CO" :
+		 (dc_flag & CHECK_DC5 ? "DC5" : "DC6"));
 	igt_assert_f(dc_state_wait_entry(drm_fd, dc_flag, prev_dc_count),
-		     "DC%d state is not achieved\n",
-		     dc_flag & CHECK_DC5 ? 5 : 6);
+		     "%s state is not achieved\n", tmp);
 }
 
 static void test_dc_state_psr(data_t *data, int dc_flag)
-- 
2.7.4

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