* [igt-dev] [PATCH i-g-t] Add TigerLake Registers file
@ 2020-01-16 23:57 John Machado
2020-01-17 7:49 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: John Machado @ 2020-01-16 23:57 UTC (permalink / raw)
To: igt-dev; +Cc: John Machado, petri.latvala
Added the TigerLake register spec file and a register delta file
that contain additional registers corresponding to TigerLake.
The spec file uses the icelake file along with the newly added
register file for TGL register definations.
Suggested-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: John Machado <john.machado@intel.com>
---
tools/registers/tigerlake | 2 +
tools/registers/tigerlake_delta.txt | 319 ++++++++++++++++++++++++++++++++++++
2 files changed, 321 insertions(+)
create mode 100644 tools/registers/tigerlake
create mode 100644 tools/registers/tigerlake_delta.txt
diff --git a/tools/registers/tigerlake b/tools/registers/tigerlake
new file mode 100644
index 0000000..0cad0ab
--- /dev/null
+++ b/tools/registers/tigerlake
@@ -0,0 +1,2 @@
+icelake
+tigerlake_delta.txt
diff --git a/tools/registers/tigerlake_delta.txt b/tools/registers/tigerlake_delta.txt
new file mode 100644
index 0000000..e82049b
--- /dev/null
+++ b/tools/registers/tigerlake_delta.txt
@@ -0,0 +1,319 @@
+#CLOCKS
+('DPLL4_ENABLE', '0x46018', '')
+('DPLL4_CFGCR0', '0x164294', '')
+('DPLL4_CFGCR1', '0x164298', '')
+('DPLL0_SSC', '0x164b10', '')
+('DPLL1_SSC', '0x164c10', '')
+('DPLL4_SSC', '0x164e10', '')
+('TRANS_CLK_SEL_D', '0x4614c', '')
+#PIPE_A_PLANE
+('PLANE_OFFSET_4_A', '0x704a4', '')
+('PLANE_OFFSET_5_A', '0x705a4', '')
+('PLANE_OFFSET_6_A', '0x706a4', '')
+('PLANE_OFFSET_7_A', '0x707a4', '')
+('PLANE_KEYMSK_4_A', '0x70498', '')
+('PLANE_KEYMSK_5_A', '0x70598', '')
+('PLANE_KEYMSK_6_A', '0x70698', '')
+('PLANE_KEYMSK_7_A', '0x70798', '')
+('PLANE_KEYVAL_4_A', '0x70494', '')
+('PLANE_KEYVAL_5_A', '0x70594', '')
+('PLANE_KEYVAL_6_A', '0x70694', '')
+('PLANE_KEYVAL_7_A', '0x70794', '')
+('PLANE_STRIDE_4_A', '0x70488', '')
+('PLANE_STRIDE_5_A', '0x70588', '')
+('PLANE_STRIDE_6_A', '0x70688', '')
+('PLANE_STRIDE_7_A', '0x70788', '')
+('PLANE_SURF_4_A', '0x7049c', '')
+('PLANE_SURF_5_A', '0x7059c', '')
+('PLANE_SURF_6_A', '0x7069c', '')
+('PLANE_SURF_7_A', '0x7079c', '')
+('PLANE_SURFLIVE_4_A', '0x704ac', '')
+('PLANE_SURFLIVE_5_A', '0x705ac', '')
+('PLANE_SURFLIVE_6_A', '0x706ac', '')
+('PLANE_SURFLIVE_7_A', '0x707ac', '')
+#PIPE_B_PLANE
+('PLANE_OFFSET_4_B', '0x714a4', '')
+('PLANE_OFFSET_5_B', '0x715a4', '')
+('PLANE_OFFSET_6_B', '0x716a4', '')
+('PLANE_OFFSET_7_B', '0x717a4', '')
+('PLANE_KEYMSK_4_B', '0x71498', '')
+('PLANE_KEYMSK_5_B', '0x71598', '')
+('PLANE_KEYMSK_6_B', '0x71698', '')
+('PLANE_KEYMSK_7_B', '0x71798', '')
+('PLANE_KEYVAL_4_B', '0x71494', '')
+('PLANE_KEYVAL_5_B', '0x71594', '')
+('PLANE_KEYVAL_6_B', '0x71694', '')
+('PLANE_KEYVAL_7_B', '0x71794', '')
+('PLANE_STRIDE_4_B', '0x71488', '')
+('PLANE_STRIDE_5_B', '0x71588', '')
+('PLANE_STRIDE_6_B', '0x71688', '')
+('PLANE_STRIDE_7_B', '0x71788', '')
+('PLANE_SURF_4_B', '0x7149c', '')
+('PLANE_SURF_5_B', '0x7159c', '')
+('PLANE_SURF_6_B', '0x7169c', '')
+('PLANE_SURF_7_B', '0x7179c', '')
+('PLANE_SURFLIVE_4_B', '0x714ac', '')
+('PLANE_SURFLIVE_5_B', '0x715ac', '')
+('PLANE_SURFLIVE_6_B', '0x716ac', '')
+('PLANE_SURFLIVE_7_B', '0x717ac', '')
+#PIPE_C_PLANE
+('PLANE_OFFSET_4_C', '0x724a4', '')
+('PLANE_OFFSET_5_C', '0x725a4', '')
+('PLANE_OFFSET_6_C', '0x726a4', '')
+('PLANE_OFFSET_7_C', '0x727a4', '')
+('PLANE_KEYMSK_4_C', '0x72498', '')
+('PLANE_KEYMSK_5_C', '0x72598', '')
+('PLANE_KEYMSK_6_C', '0x72698', '')
+('PLANE_KEYMSK_7_C', '0x72798', '')
+('PLANE_KEYVAL_4_C', '0x72494', '')
+('PLANE_KEYVAL_5_C', '0x72594', '')
+('PLANE_KEYVAL_6_C', '0x72694', '')
+('PLANE_KEYVAL_7_C', '0x72794', '')
+('PLANE_STRIDE_4_C', '0x72488', '')
+('PLANE_STRIDE_5_C', '0x72588', '')
+('PLANE_STRIDE_6_C', '0x72688', '')
+('PLANE_STRIDE_7_C', '0x72788', '')
+('PLANE_SURF_4_C', '0x7249c', '')
+('PLANE_SURF_5_C', '0x7259c', '')
+('PLANE_SURF_6_C', '0x7269c', '')
+('PLANE_SURF_7_C', '0x7279c', '')
+('PLANE_SURFLIVE_4_C', '0x724ac', '')
+('PLANE_SURFLIVE_5_C', '0x725ac', '')
+('PLANE_SURFLIVE_6_C', '0x726ac', '')
+('PLANE_SURFLIVE_7_C', '0x727ac', '')
+#PIPE_D_PLANE
+('PLANE_AUX_DIST_1_D', '0x731c0', '')
+('PLANE_AUX_DIST_2_D', '0x732c0', '')
+('PLANE_AUX_DIST_3_D', '0x733c0', '')
+('PLANE_AUX_DIST_4_D', '0x734c0', '')
+('PLANE_AUX_DIST_5_D', '0x735c0', '')
+('PLANE_AUX_DIST_6_D', '0x736c0', '')
+('PLANE_AUX_DIST_7_D', '0x737c0', '')
+('PLANE_CTL_1_D', '0x73180', '')
+('PLANE_CTL_2_D', '0x73280', '')
+('PLANE_CTL_3_D', '0x73380', '')
+('PLANE_CTL_4_D', '0x73480', '')
+('PLANE_CTL_5_D', '0x73580', '')
+('PLANE_CTL_6_D', '0x73680', '')
+('PLANE_CTL_7_D', '0x73780', '')
+('PLANE_BUF_CFG_1_D', '0x7327c', '')
+('PLANE_BUF_CFG_2_D', '0x7337c', '')
+('PLANE_BUF_CFG_3_D', '0x7347c', '')
+('PLANE_BUF_CFG_4_D', '0x7357c', '')
+('PLANE_BUF_CFG_5_D', '0x7367c', '')
+('PLANE_BUF_CFG_6_D', '0x7377c', '')
+('PLANE_BUF_CFG_7_D', '0x7387c', '')
+('PLANE_COLOR_CTL_1_D', '0x731cc', '')
+('PLANE_COLOR_CTL_2_D', '0x732cc', '')
+('PLANE_COLOR_CTL_3_D', '0x733cc', '')
+('PLANE_COLOR_CTL_4_D', '0x734cc', '')
+('PLANE_COLOR_CTL_5_D', '0x735cc', '')
+('PLANE_COLOR_CTL_6_D', '0x736cc', '')
+('PLANE_COLOR_CTL_7_D', '0x737cc', '')
+('PLANE_OFFSET_1_D', '0x731a4', ''
+('PLANE_OFFSET_2_D', '0x732a4', '')
+('PLANE_OFFSET_3_D', '0x733a4', '')
+('PLANE_OFFSET_4_D', '0x734a4', '')
+('PLANE_OFFSET_5_D', '0x735a4', '')
+('PLANE_OFFSET_6_D', '0x736a4', '')
+('PLANE_OFFSET_7_D', '0x737a4', '')
+('PLANE_KEYMAX_1_D', '0x731a0', '')
+('PLANE_KEYMAX_2_D', '0x732a0', '')
+('PLANE_KEYMAX_3_D', '0x733a0', '')
+('PLANE_KEYMAX_4_D', '0x734a0', '')
+('PLANE_KEYMAX_5_D', '0x735a0', '')
+('PLANE_KEYMAX_6_D', '0x736a0', '')
+('PLANE_KEYMAX_7_D', '0x737a0', '')
+('PLANE_KEYMSK_1_D', '0x73198', '')
+('PLANE_KEYMSK_2_D', '0x73298', '')
+('PLANE_KEYMSK_3_D', '0x73398', '')
+('PLANE_KEYMSK_4_D', '0x73498', '')
+('PLANE_KEYMSK_5_D', '0x73598', '')
+('PLANE_KEYMSK_6_D', '0x73698', '')
+('PLANE_KEYMSK_7_D', '0x73798', '')
+('PLANE_KEYVAL_1_D', '0x73194', '')
+('PLANE_KEYVAL_2_D', '0x73294', '')
+('PLANE_KEYVAL_3_D', '0x73394', '')
+('PLANE_KEYVAL_4_D', '0x73494', '')
+('PLANE_KEYVAL_5_D', '0x73594', '')
+('PLANE_KEYVAL_6_D', '0x73694', '')
+('PLANE_KEYVAL_7_D', '0x73794', '')
+('PLANE_STRIDE_1_D', '0x73188', '')
+('PLANE_STRIDE_2_D', '0x73288', '')
+('PLANE_STRIDE_3_D', '0x73388', '')
+('PLANE_STRIDE_4_D', '0x73488', '')
+('PLANE_STRIDE_5_D', '0x73588', '')
+('PLANE_STRIDE_6_D', '0x73688', '')
+('PLANE_STRIDE_7_D', '0x73788', '')
+('PLANE_SURF_1_D', '0x7319c', '')
+('PLANE_SURF_2_D', '0x7329c', '')
+('PLANE_SURF_3_D', '0x7339c', '')
+('PLANE_SURF_4_D', '0x7349c', '')
+('PLANE_SURF_5_D', '0x7359c', '')
+('PLANE_SURF_6_D', '0x7369c', '')
+('PLANE_SURF_7_D', '0x7379c', '')
+('PLANE_SURFLIVE_1_D', '0x731ac', '')
+('PLANE_SURFLIVE_2_D', '0x732ac', '')
+('PLANE_SURFLIVE_3_D', '0x733ac', '')
+('PLANE_SURFLIVE_4_D', '0x734ac', '')
+('PLANE_SURFLIVE_5_D', '0x735ac', '')
+('PLANE_SURFLIVE_6_D', '0x736ac', '')
+('PLANE_SURFLIVE_7_D', '0x737ac', '')
+('PLANE_POS_1_D', '0x7318c', '')
+('PLANE_POS_2_D', '0x7328c', '')
+('PLANE_POS_3_D', '0x7338c', '')
+('PLANE_POS_4_D', '0x7348c', '')
+('PLANE_POS_5_D', '0x7358c', '')
+('PLANE_POS_6_D', '0x7368c', '')
+('PLANE_POS_7_D', '0x7378c', '')
+('PLANE_SIZE_1_D', '0x73190', '')
+('PLANE_SIZE_2_D', '0x73290', '')
+('PLANE_SIZE_3_D', '0x73390', '')
+('PLANE_SIZE_4_D', '0x73490', '')
+('PLANE_SIZE_5_D', '0x73590', '')
+('PLANE_SIZE_6_D', '0x73690', '')
+('PLANE_SIZE_7_D', '0x73790', '')
+('PLANE_WM_1_D_0', '0x73240', '')
+('PLANE_WM_1_D_1', '0x73244', '')
+('PLANE_WM_1_D_2', '0x73248', '')
+('PLANE_WM_1_D_3', '0x7324c', '')
+('PLANE_WM_1_D_4', '0x73250', '')
+('PLANE_WM_1_D_5', '0x73254', '')
+('PLANE_WM_1_D_6', '0x73258', '')
+('PLANE_WM_1_D_7', '0x7325c', '')
+('PLANE_WM_2_D_0', '0x73340', '')
+('PLANE_WM_2_D_1', '0x73344', '')
+('PLANE_WM_2_D_2', '0x73348', '')
+('PLANE_WM_2_D_3', '0x7334c', '')
+('PLANE_WM_2_D_4', '0x73350', '')
+('PLANE_WM_2_D_5', '0x73354', '')
+('PLANE_WM_2_D_6', '0x73358', '')
+('PLANE_WM_2_D_7', '0x7335c', '')
+('PLANE_WM_3_D_0', '0x73440', '')
+('PLANE_WM_3_D_1', '0x73444', '')
+('PLANE_WM_3_D_2', '0x73448', '')
+('PLANE_WM_3_D_3', '0x7344c', '')
+('PLANE_WM_3_D_4', '0x73450', '')
+('PLANE_WM_3_D_5', '0x73454', '')
+('PLANE_WM_3_D_6', '0x73458', '')
+('PLANE_WM_3_D_7', '0x7345c', '')
+('PLANE_WM_4_D_0', '0x73540', '')
+('PLANE_WM_4_D_1', '0x73544', '')
+('PLANE_WM_4_D_2', '0x73548', '')
+('PLANE_WM_4_D_3', '0x7354c', '')
+('PLANE_WM_4_D_4', '0x73550', '')
+('PLANE_WM_4_D_5', '0x73554', '')
+('PLANE_WM_4_D_6', '0x73558', '')
+('PLANE_WM_4_D_7', '0x7355c', '')
+('PLANE_WM_5_D_0', '0x73640', '')
+('PLANE_WM_5_D_1', '0x73644', '')
+('PLANE_WM_5_D_2', '0x73648', '')
+('PLANE_WM_5_D_3', '0x7364c', '')
+('PLANE_WM_5_D_4', '0x73650', '')
+('PLANE_WM_5_D_5', '0x73654', '')
+('PLANE_WM_5_D_6', '0x73658', '')
+('PLANE_WM_5_D_7', '0x7365c', '')
+('PLANE_WM_6_D_0', '0x73740', '')
+('PLANE_WM_6_D_1', '0x73744', '')
+('PLANE_WM_6_D_2', '0x73748', '')
+('PLANE_WM_6_D_3', '0x7374c', '')
+('PLANE_WM_6_D_4', '0x73750', '')
+('PLANE_WM_6_D_5', '0x73754', '')
+('PLANE_WM_6_D_6', '0x73758', '')
+('PLANE_WM_6_D_7', '0x7375c', '')
+('PLANE_WM_7_D_0', '0x73840', '')
+('PLANE_WM_7_D_1', '0x73844', '')
+('PLANE_WM_7_D_2', '0x73848', '')
+('PLANE_WM_7_D_3', '0x7384c', '')
+('PLANE_WM_7_D_4', '0x73850', '')
+('PLANE_WM_7_D_5', '0x73854', '')
+('PLANE_WM_7_D_6', '0x73858', '')
+('PLANE_WM_7_D_7', '0x7385c', '')
+('PLANE_WM_TRANS_1_D', '0x73268', '')
+('PLANE_WM_TRANS_2_D', '0x73368', '')
+('PLANE_WM_TRANS_3_D', '0x73468', '')
+('PLANE_WM_TRANS_4_D', '0x73568', '')
+('PLANE_WM_TRANS_5_D', '0x73668', '')
+('PLANE_WM_TRANS_6_D', '0x73768', '')
+('PLANE_WM_TRANS_7_D', '0x73868', '')
+# PIPE_D_CURSOR_PLANE
+('CUR_BUF_CFG_D', '0x7317c', '')
+('CUR_BASE_D', '0x73084', '')
+('CUR_CTL_D', '0x73080', '')
+('CUR_FBC_CTL_D', '0x730a0', '')
+('CUR_POS_D', '0x73088', '')
+('CUR_SURFLIVE_D', '0x730ac', '')
+('CUR_WM_0_D', '0x73140', '')
+('CUR_WM_1_D', '0x73144', '')
+('CUR_WM_2_D', '0x73148', '')
+('CUR_WM_3_D', '0x7314c', '')
+('CUR_WM_4_D', '0x73150', '')
+('CUR_WM_5_D', '0x73154', '')
+('CUR_WM_6_D', '0x73158', '')
+('CUR_WM_7_D', '0x7315c', '')
+('CUR_WM_TRANS_D', '0x73168', '')
+#PIPE_SCALER_D
+('PS_CTRL_1_D', '0x69980', '')
+('PS_CTRL_2_D', '0x69a80', '')
+('PS_ECC_STAT_1_D', '0x699d0', '')
+('PS_ECC_STAT_2_D', '0x69ad0', '')
+('PS_HPHASE_1_D', '0x69994', '')
+('PS_HPHASE_2_D', '0x69a94', '')
+('PS_HSCALE_1_D', '0x69990', '')
+('PS_HSCALE_2_D', '0x69a90', '')
+('PS_PWR_GATE_1_D', '0x69960', '')
+('PS_PWR_GATE_2_D', '0x69a60', '')
+('PS_VPHASE_1_D', '0x69988', '')
+('PS_VPHASE_2_D', '0x69a88', '')
+('PS_VSCALE_1_D', '0x69984', '')
+('PS_VSCALE_2_D', '0x69a84', '')
+('PS_WIN_POS_1_D', '0x69970', '')
+('PS_WIN_POS_2_D', '0x69a70', '')
+('PS_WIN_SZ_1_D', '0x69974', '')
+('PS_WIN_SZ_2_D', '0x69a74', '')
+#TRANSCODER_D_CONTROL
+('TRANS_CONF_D', '0x73008', '')
+#TRANSCODER_DSI_CONTROL
+('TRANS_CONF_DSI0', '0x7b008', '')
+('TRANS_CONF_DSI1', '0x7b808', '')
+# TRANSCODER_D_TIMING
+('TRANS_HBLANK_D', '0x63004', '')
+('TRANS_HSYNC_D', '0x63008', '')
+('TRANS_HTOTAL_D', '0x63000', '')
+('TRANS_MULT_D', '0x6302c', '')
+('TRANS_SPACE_D', '0x63024', '')
+('TRANS_VBLANK_D', '0x63010', '')
+('TRANS_VSYNC_D', '0x63014', '')
+('TRANS_VSYNCSHIFT_D', '0x63028', '')
+('TRANS_VTOTAL_D', '0x6300c', '')
+# TRANSCODER_DSI_TIMING
+('TRANS_HSYNC_DSI0', '0x6b008', '')
+('TRANS_HSYNC_DSI1', '0x6b808', '')
+('TRANS_HTOTAL_DSI0', '0x6b000', '')
+('TRANS_HTOTAL_DSI1', '0x6b800', '')
+('TRANS_SPACE_DSI0', '0x6b024', '')
+('TRANS_SPACE_DSI1', '0x6b824', '')
+('TRANS_VBLANK_DSI0', '0x6b010', '')
+('TRANS_VBLANK_DSI1', '0x6b810', '')
+('TRANS_VSYNC_DSI0', '0x6b014', '')
+('TRANS_VSYNC_DSI1', '0x6b814', '')
+('TRANS_VSYNCSHIFT_DSI0', '0x6b028', '')
+('TRANS_VSYNCSHIFT_DSI1', '0x6b828', '')
+('TRANS_VTOTAL_DSI0', '0x6b00c', '')
+('TRANS_VTOTAL_DSI1', '0x6b80c', '')
+# TRANSCODER_D_M_N
+('TRANS_DATAM1_D', '0x63030', '')
+('TRANS_DATAN1_D', '0x63034', '')
+('TRANS_LINKM1_D', '0x63040', '')
+('TRANS_LINKN1_D', '0x63044', '')
+# TRANSCODER_D_DDI_CONTROL
+('TRANS_DDI_FUNC_CTL_D', '0x63400', '')
+('TRANS_MSA_MISC_D', '0x63410', '')
+# TRANSCODER_DSI_DDI_CONTROL
+('TRANS_DDI_FUNC_CTL_DSI0', '0x6b400', '')
+('TRANS_DDI_FUNC_CTL_DSI1', '0x6bc00', '')
+# MBUS_CTL
+('MBUS_DBOX_CTL_D', '0x7303c', '')
+# WATERMARK
+('WM_LINETIME_D', '0x4527c', '')
+
--
2.7.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [igt-dev] ✓ Fi.CI.BAT: success for Add TigerLake Registers file 2020-01-16 23:57 [igt-dev] [PATCH i-g-t] Add TigerLake Registers file John Machado @ 2020-01-17 7:49 ` Patchwork 2020-01-21 4:24 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 2020-01-21 9:30 ` [igt-dev] [PATCH i-g-t] " Petri Latvala 2 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2020-01-17 7:49 UTC (permalink / raw) To: John Machado; +Cc: igt-dev == Series Details == Series: Add TigerLake Registers file URL : https://patchwork.freedesktop.org/series/72161/ State : success == Summary == CI Bug Log - changes from CI_DRM_7758 -> IGTPW_3930 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/index.html Known issues ------------ Here are the changes found in IGTPW_3930 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#889]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/fi-cfl-guc/igt@i915_module_load@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/fi-cfl-guc/igt@i915_module_load@reload-with-fault-injection.html - fi-skl-6700k2: [PASS][3] -> [INCOMPLETE][4] ([i915#671]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html - fi-kbl-x1275: [PASS][5] -> [INCOMPLETE][6] ([i915#879]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/fi-kbl-x1275/igt@i915_module_load@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/fi-kbl-x1275/igt@i915_module_load@reload-with-fault-injection.html #### Possible fixes #### * igt@gem_exec_create@basic: - fi-icl-dsi: [DMESG-WARN][7] ([i915#109]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/fi-icl-dsi/igt@gem_exec_create@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/fi-icl-dsi/igt@gem_exec_create@basic.html * igt@i915_selftest@live_blt: - fi-hsw-4770: [DMESG-FAIL][9] ([i915#553] / [i915#725]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/fi-hsw-4770/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][11] ([fdo#111096] / [i915#323]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#879]: https://gitlab.freedesktop.org/drm/intel/issues/879 [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889 Participating hosts (47 -> 46) ------------------------------ Additional (3): fi-kbl-soraka fi-byt-j1900 fi-byt-n2820 Missing (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5371 -> IGTPW_3930 CI-20190529: 20190529 CI_DRM_7758: d19270ce1f367fbfc1ff3b539bcb50e11ded181f @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3930: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/index.html IGT_5371: 1b2816124ec3dbd53b81725d39292f45d41d895b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 5+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Add TigerLake Registers file 2020-01-16 23:57 [igt-dev] [PATCH i-g-t] Add TigerLake Registers file John Machado 2020-01-17 7:49 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork @ 2020-01-21 4:24 ` Patchwork 2020-01-21 9:30 ` [igt-dev] [PATCH i-g-t] " Petri Latvala 2 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2020-01-21 4:24 UTC (permalink / raw) To: John Machado; +Cc: igt-dev == Series Details == Series: Add TigerLake Registers file URL : https://patchwork.freedesktop.org/series/72161/ State : success == Summary == CI Bug Log - changes from CI_DRM_7758_full -> IGTPW_3930_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/index.html Known issues ------------ Here are the changes found in IGTPW_3930_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +10 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb4/igt@gem_busy@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb5/igt@gem_busy@busy-vcs1.html * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-kbl7/igt@gem_ctx_isolation@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-kbl2/igt@gem_ctx_isolation@rcs0-s3.html * igt@gem_ctx_persistence@vcs1-mixed-process: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb2/igt@gem_ctx_persistence@vcs1-mixed-process.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb5/igt@gem_ctx_persistence@vcs1-mixed-process.html * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][7] -> [FAIL][8] ([i915#232]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-snb2/igt@gem_eio@unwedge-stress.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-snb2/igt@gem_eio@unwedge-stress.html * igt@gem_exec_parallel@fds: - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#470] / [i915#472]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb8/igt@gem_exec_parallel@fds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb7/igt@gem_exec_parallel@fds.html * igt@gem_exec_schedule@pi-ringfull-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb5/igt@gem_exec_schedule@pi-ringfull-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb4/igt@gem_exec_schedule@pi-ringfull-bsd.html * igt@gem_exec_suspend@basic-s3-devices: - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([i915#460] / [i915#472]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb1/igt@gem_exec_suspend@basic-s3-devices.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb6/igt@gem_exec_suspend@basic-s3-devices.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive: - shard-apl: [PASS][15] -> [TIMEOUT][16] ([fdo#112271] / [i915#530]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-apl2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-apl2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html * igt@gem_persistent_relocs@forked-thrash-inactive: - shard-kbl: [PASS][17] -> [TIMEOUT][18] ([fdo#112271] / [i915#530]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-kbl2/igt@gem_persistent_relocs@forked-thrash-inactive.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-kbl6/igt@gem_persistent_relocs@forked-thrash-inactive.html * igt@gem_persistent_relocs@forked-thrashing: - shard-hsw: [PASS][19] -> [INCOMPLETE][20] ([i915#530] / [i915#61]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-hsw5/igt@gem_persistent_relocs@forked-thrashing.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-hsw2/igt@gem_persistent_relocs@forked-thrashing.html * igt@gem_sync@basic-store-each: - shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#472]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb1/igt@gem_sync@basic-store-each.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb6/igt@gem_sync@basic-store-each.html * igt@kms_color@pipe-a-legacy-gamma: - shard-apl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#71]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-apl8/igt@kms_color@pipe-a-legacy-gamma.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-apl1/igt@kms_color@pipe-a-legacy-gamma.html - shard-kbl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#71]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-kbl4/igt@kms_color@pipe-a-legacy-gamma.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-kbl4/igt@kms_color@pipe-a-legacy-gamma.html * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen: - shard-glk: [PASS][27] -> [FAIL][28] ([i915#54]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html * igt@kms_cursor_crc@pipe-c-cursor-256x256-random: - shard-kbl: [PASS][29] -> [FAIL][30] ([i915#54]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-256x256-random.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-256x256-random.html - shard-apl: [PASS][31] -> [FAIL][32] ([i915#54]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-256x256-random.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-256x256-random.html * igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled: - shard-snb: [PASS][33] -> [DMESG-WARN][34] ([i915#478]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-snb5/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-snb4/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-tglb: [PASS][35] -> [FAIL][36] ([i915#49]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move: - shard-glk: [PASS][37] -> [FAIL][38] ([i915#49]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-glk1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-glk8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][39] -> [DMESG-WARN][40] ([i915#180]) +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - shard-tglb: [PASS][41] -> [SKIP][42] ([i915#668]) +5 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109642] / [fdo#111068]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb2/igt@kms_psr2_su@frontbuffer.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb8/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109441]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][47] -> [SKIP][48] ([fdo#109276]) +13 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html #### Possible fixes #### * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [SKIP][49] ([fdo#109276] / [fdo#112080]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html * igt@gem_ctx_persistence@processes: - shard-iclb: [FAIL][51] ([i915#570]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb4/igt@gem_ctx_persistence@processes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb6/igt@gem_ctx_persistence@processes.html * igt@gem_ctx_shared@q-smoketest-all: - shard-tglb: [INCOMPLETE][53] ([fdo#111735] / [i915#472]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb7/igt@gem_ctx_shared@q-smoketest-all.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb8/igt@gem_ctx_shared@q-smoketest-all.html * igt@gem_ctx_shared@q-smoketest-bsd2: - shard-tglb: [INCOMPLETE][55] ([i915#461] / [i915#472]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb3/igt@gem_ctx_shared@q-smoketest-bsd2.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb8/igt@gem_ctx_shared@q-smoketest-bsd2.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [SKIP][57] ([fdo#109276]) -> [PASS][58] +15 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb6/igt@gem_exec_schedule@independent-bsd2.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb1/igt@gem_exec_schedule@independent-bsd2.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [SKIP][59] ([fdo#112146]) -> [PASS][60] +5 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html * igt@gem_exec_schedule@smoketest-vebox: - shard-tglb: [INCOMPLETE][61] ([i915#472] / [i915#707]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb4/igt@gem_exec_schedule@smoketest-vebox.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb8/igt@gem_exec_schedule@smoketest-vebox.html * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive: - shard-tglb: [INCOMPLETE][63] ([i915#472]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb6/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb3/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing: - shard-apl: [TIMEOUT][65] ([fdo#112271] / [i915#530]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-apl6/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-apl1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive: - shard-kbl: [TIMEOUT][67] ([fdo#112271] / [i915#530]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-kbl4/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-kbl7/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html * igt@gem_pipe_control_store_loop@reused-buffer: - shard-tglb: [INCOMPLETE][69] ([i915#472] / [i915#707] / [i915#796]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb3/igt@gem_pipe_control_store_loop@reused-buffer.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb7/igt@gem_pipe_control_store_loop@reused-buffer.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-snb: [DMESG-WARN][71] ([fdo#111870] / [i915#478]) -> [PASS][72] +2 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html * {igt@i915_pm_rc6_residency@rc6-idle}: - shard-apl: [FAIL][73] ([i915#973]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-apl3/igt@i915_pm_rc6_residency@rc6-idle.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-apl4/igt@i915_pm_rc6_residency@rc6-idle.html * igt@i915_selftest@live_execlists: - shard-kbl: [INCOMPLETE][75] ([fdo#103665] / [fdo#112175] / [fdo#112259]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-kbl6/igt@i915_selftest@live_execlists.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-kbl7/igt@i915_selftest@live_execlists.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-apl: [DMESG-WARN][77] ([i915#180]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80] +3 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt: - shard-glk: [FAIL][81] ([i915#49]) -> [PASS][82] [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-glk8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt: - shard-tglb: [FAIL][83] ([i915#49]) -> [PASS][84] +2 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-iclb: [INCOMPLETE][85] ([i915#140] / [i915#250]) -> [PASS][86] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [SKIP][87] ([fdo#109441]) -> [PASS][88] +3 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@perf_pmu@busy-no-semaphores-vcs1: - shard-iclb: [SKIP][89] ([fdo#112080]) -> [PASS][90] +5 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-iclb6/igt@perf_pmu@busy-no-semaphores-vcs1.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html #### Warnings #### * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-snb: [DMESG-WARN][91] ([fdo#111870] / [i915#478]) -> [DMESG-WARN][92] ([fdo#110789] / [fdo#111870] / [i915#478]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html * igt@runner@aborted: - shard-glk: ([FAIL][93], [FAIL][94]) ([k.org#202321]) -> [FAIL][95] ([i915#997] / [k.org#202321]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-glk2/igt@runner@aborted.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7758/shard-glk9/igt@runner@aborted.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/shard-glk5/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735 [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [fdo#112175]: https://bugs.freedesktop.org/show_bug.cgi?id=112175 [fdo#112259]: https://bugs.freedesktop.org/show_bug.cgi?id=112259 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232 [i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250 [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460 [i915#461]: https://gitlab.freedesktop.org/drm/intel/issues/461 [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470 [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472 [i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#570]: https://gitlab.freedesktop.org/drm/intel/issues/570 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707 [i915#71]: https://gitlab.freedesktop.org/drm/intel/issues/71 [i915#796]: https://gitlab.freedesktop.org/drm/intel/issues/796 [i915#973]: https://gitlab.freedesktop.org/drm/intel/issues/973 [i915#997]: https://gitlab.freedesktop.org/drm/intel/issues/997 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (10 -> 8) ------------------------------ Missing (2): pig-skl-6260u pig-glk-j5005 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5371 -> IGTPW_3930 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_7758: d19270ce1f367fbfc1ff3b539bcb50e11ded181f @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3930: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/index.html IGT_5371: 1b2816124ec3dbd53b81725d39292f45d41d895b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3930/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] Add TigerLake Registers file 2020-01-16 23:57 [igt-dev] [PATCH i-g-t] Add TigerLake Registers file John Machado 2020-01-17 7:49 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork 2020-01-21 4:24 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork @ 2020-01-21 9:30 ` Petri Latvala 2020-01-21 9:31 ` Petri Latvala 2 siblings, 1 reply; 5+ messages in thread From: Petri Latvala @ 2020-01-21 9:30 UTC (permalink / raw) To: John Machado; +Cc: igt-dev On Fri, Jan 17, 2020 at 05:27:59AM +0530, John Machado wrote: > Added the TigerLake register spec file and a register delta file > that contain additional registers corresponding to TigerLake. > > The spec file uses the icelake file along with the newly added > register file for TGL register definations. > > Suggested-by: Swati Sharma <swati2.sharma@intel.com> > Signed-off-by: John Machado <john.machado@intel.com> igt@tools_test@tools_test doesn't explode. The values I'm not going to check, if they're incorrect we can fix them later, they're only used by the tools and won't affect CI. Acked-by: Petri Latvala <petri.latvala@intel.com> > --- > tools/registers/tigerlake | 2 + > tools/registers/tigerlake_delta.txt | 319 ++++++++++++++++++++++++++++++++++++ > 2 files changed, 321 insertions(+) > create mode 100644 tools/registers/tigerlake > create mode 100644 tools/registers/tigerlake_delta.txt > > diff --git a/tools/registers/tigerlake b/tools/registers/tigerlake > new file mode 100644 > index 0000000..0cad0ab > --- /dev/null > +++ b/tools/registers/tigerlake > @@ -0,0 +1,2 @@ > +icelake > +tigerlake_delta.txt > diff --git a/tools/registers/tigerlake_delta.txt b/tools/registers/tigerlake_delta.txt > new file mode 100644 > index 0000000..e82049b > --- /dev/null > +++ b/tools/registers/tigerlake_delta.txt > @@ -0,0 +1,319 @@ > +#CLOCKS > +('DPLL4_ENABLE', '0x46018', '') > +('DPLL4_CFGCR0', '0x164294', '') > +('DPLL4_CFGCR1', '0x164298', '') > +('DPLL0_SSC', '0x164b10', '') > +('DPLL1_SSC', '0x164c10', '') > +('DPLL4_SSC', '0x164e10', '') > +('TRANS_CLK_SEL_D', '0x4614c', '') > +#PIPE_A_PLANE > +('PLANE_OFFSET_4_A', '0x704a4', '') > +('PLANE_OFFSET_5_A', '0x705a4', '') > +('PLANE_OFFSET_6_A', '0x706a4', '') > +('PLANE_OFFSET_7_A', '0x707a4', '') > +('PLANE_KEYMSK_4_A', '0x70498', '') > +('PLANE_KEYMSK_5_A', '0x70598', '') > +('PLANE_KEYMSK_6_A', '0x70698', '') > +('PLANE_KEYMSK_7_A', '0x70798', '') > +('PLANE_KEYVAL_4_A', '0x70494', '') > +('PLANE_KEYVAL_5_A', '0x70594', '') > +('PLANE_KEYVAL_6_A', '0x70694', '') > +('PLANE_KEYVAL_7_A', '0x70794', '') > +('PLANE_STRIDE_4_A', '0x70488', '') > +('PLANE_STRIDE_5_A', '0x70588', '') > +('PLANE_STRIDE_6_A', '0x70688', '') > +('PLANE_STRIDE_7_A', '0x70788', '') > +('PLANE_SURF_4_A', '0x7049c', '') > +('PLANE_SURF_5_A', '0x7059c', '') > +('PLANE_SURF_6_A', '0x7069c', '') > +('PLANE_SURF_7_A', '0x7079c', '') > +('PLANE_SURFLIVE_4_A', '0x704ac', '') > +('PLANE_SURFLIVE_5_A', '0x705ac', '') > +('PLANE_SURFLIVE_6_A', '0x706ac', '') > +('PLANE_SURFLIVE_7_A', '0x707ac', '') > +#PIPE_B_PLANE > +('PLANE_OFFSET_4_B', '0x714a4', '') > +('PLANE_OFFSET_5_B', '0x715a4', '') > +('PLANE_OFFSET_6_B', '0x716a4', '') > +('PLANE_OFFSET_7_B', '0x717a4', '') > +('PLANE_KEYMSK_4_B', '0x71498', '') > +('PLANE_KEYMSK_5_B', '0x71598', '') > +('PLANE_KEYMSK_6_B', '0x71698', '') > +('PLANE_KEYMSK_7_B', '0x71798', '') > +('PLANE_KEYVAL_4_B', '0x71494', '') > +('PLANE_KEYVAL_5_B', '0x71594', '') > +('PLANE_KEYVAL_6_B', '0x71694', '') > +('PLANE_KEYVAL_7_B', '0x71794', '') > +('PLANE_STRIDE_4_B', '0x71488', '') > +('PLANE_STRIDE_5_B', '0x71588', '') > +('PLANE_STRIDE_6_B', '0x71688', '') > +('PLANE_STRIDE_7_B', '0x71788', '') > +('PLANE_SURF_4_B', '0x7149c', '') > +('PLANE_SURF_5_B', '0x7159c', '') > +('PLANE_SURF_6_B', '0x7169c', '') > +('PLANE_SURF_7_B', '0x7179c', '') > +('PLANE_SURFLIVE_4_B', '0x714ac', '') > +('PLANE_SURFLIVE_5_B', '0x715ac', '') > +('PLANE_SURFLIVE_6_B', '0x716ac', '') > +('PLANE_SURFLIVE_7_B', '0x717ac', '') > +#PIPE_C_PLANE > +('PLANE_OFFSET_4_C', '0x724a4', '') > +('PLANE_OFFSET_5_C', '0x725a4', '') > +('PLANE_OFFSET_6_C', '0x726a4', '') > +('PLANE_OFFSET_7_C', '0x727a4', '') > +('PLANE_KEYMSK_4_C', '0x72498', '') > +('PLANE_KEYMSK_5_C', '0x72598', '') > +('PLANE_KEYMSK_6_C', '0x72698', '') > +('PLANE_KEYMSK_7_C', '0x72798', '') > +('PLANE_KEYVAL_4_C', '0x72494', '') > +('PLANE_KEYVAL_5_C', '0x72594', '') > +('PLANE_KEYVAL_6_C', '0x72694', '') > +('PLANE_KEYVAL_7_C', '0x72794', '') > +('PLANE_STRIDE_4_C', '0x72488', '') > +('PLANE_STRIDE_5_C', '0x72588', '') > +('PLANE_STRIDE_6_C', '0x72688', '') > +('PLANE_STRIDE_7_C', '0x72788', '') > +('PLANE_SURF_4_C', '0x7249c', '') > +('PLANE_SURF_5_C', '0x7259c', '') > +('PLANE_SURF_6_C', '0x7269c', '') > +('PLANE_SURF_7_C', '0x7279c', '') > +('PLANE_SURFLIVE_4_C', '0x724ac', '') > +('PLANE_SURFLIVE_5_C', '0x725ac', '') > +('PLANE_SURFLIVE_6_C', '0x726ac', '') > +('PLANE_SURFLIVE_7_C', '0x727ac', '') > +#PIPE_D_PLANE > +('PLANE_AUX_DIST_1_D', '0x731c0', '') > +('PLANE_AUX_DIST_2_D', '0x732c0', '') > +('PLANE_AUX_DIST_3_D', '0x733c0', '') > +('PLANE_AUX_DIST_4_D', '0x734c0', '') > +('PLANE_AUX_DIST_5_D', '0x735c0', '') > +('PLANE_AUX_DIST_6_D', '0x736c0', '') > +('PLANE_AUX_DIST_7_D', '0x737c0', '') > +('PLANE_CTL_1_D', '0x73180', '') > +('PLANE_CTL_2_D', '0x73280', '') > +('PLANE_CTL_3_D', '0x73380', '') > +('PLANE_CTL_4_D', '0x73480', '') > +('PLANE_CTL_5_D', '0x73580', '') > +('PLANE_CTL_6_D', '0x73680', '') > +('PLANE_CTL_7_D', '0x73780', '') > +('PLANE_BUF_CFG_1_D', '0x7327c', '') > +('PLANE_BUF_CFG_2_D', '0x7337c', '') > +('PLANE_BUF_CFG_3_D', '0x7347c', '') > +('PLANE_BUF_CFG_4_D', '0x7357c', '') > +('PLANE_BUF_CFG_5_D', '0x7367c', '') > +('PLANE_BUF_CFG_6_D', '0x7377c', '') > +('PLANE_BUF_CFG_7_D', '0x7387c', '') > +('PLANE_COLOR_CTL_1_D', '0x731cc', '') > +('PLANE_COLOR_CTL_2_D', '0x732cc', '') > +('PLANE_COLOR_CTL_3_D', '0x733cc', '') > +('PLANE_COLOR_CTL_4_D', '0x734cc', '') > +('PLANE_COLOR_CTL_5_D', '0x735cc', '') > +('PLANE_COLOR_CTL_6_D', '0x736cc', '') > +('PLANE_COLOR_CTL_7_D', '0x737cc', '') > +('PLANE_OFFSET_1_D', '0x731a4', '' > +('PLANE_OFFSET_2_D', '0x732a4', '') > +('PLANE_OFFSET_3_D', '0x733a4', '') > +('PLANE_OFFSET_4_D', '0x734a4', '') > +('PLANE_OFFSET_5_D', '0x735a4', '') > +('PLANE_OFFSET_6_D', '0x736a4', '') > +('PLANE_OFFSET_7_D', '0x737a4', '') > +('PLANE_KEYMAX_1_D', '0x731a0', '') > +('PLANE_KEYMAX_2_D', '0x732a0', '') > +('PLANE_KEYMAX_3_D', '0x733a0', '') > +('PLANE_KEYMAX_4_D', '0x734a0', '') > +('PLANE_KEYMAX_5_D', '0x735a0', '') > +('PLANE_KEYMAX_6_D', '0x736a0', '') > +('PLANE_KEYMAX_7_D', '0x737a0', '') > +('PLANE_KEYMSK_1_D', '0x73198', '') > +('PLANE_KEYMSK_2_D', '0x73298', '') > +('PLANE_KEYMSK_3_D', '0x73398', '') > +('PLANE_KEYMSK_4_D', '0x73498', '') > +('PLANE_KEYMSK_5_D', '0x73598', '') > +('PLANE_KEYMSK_6_D', '0x73698', '') > +('PLANE_KEYMSK_7_D', '0x73798', '') > +('PLANE_KEYVAL_1_D', '0x73194', '') > +('PLANE_KEYVAL_2_D', '0x73294', '') > +('PLANE_KEYVAL_3_D', '0x73394', '') > +('PLANE_KEYVAL_4_D', '0x73494', '') > +('PLANE_KEYVAL_5_D', '0x73594', '') > +('PLANE_KEYVAL_6_D', '0x73694', '') > +('PLANE_KEYVAL_7_D', '0x73794', '') > +('PLANE_STRIDE_1_D', '0x73188', '') > +('PLANE_STRIDE_2_D', '0x73288', '') > +('PLANE_STRIDE_3_D', '0x73388', '') > +('PLANE_STRIDE_4_D', '0x73488', '') > +('PLANE_STRIDE_5_D', '0x73588', '') > +('PLANE_STRIDE_6_D', '0x73688', '') > +('PLANE_STRIDE_7_D', '0x73788', '') > +('PLANE_SURF_1_D', '0x7319c', '') > +('PLANE_SURF_2_D', '0x7329c', '') > +('PLANE_SURF_3_D', '0x7339c', '') > +('PLANE_SURF_4_D', '0x7349c', '') > +('PLANE_SURF_5_D', '0x7359c', '') > +('PLANE_SURF_6_D', '0x7369c', '') > +('PLANE_SURF_7_D', '0x7379c', '') > +('PLANE_SURFLIVE_1_D', '0x731ac', '') > +('PLANE_SURFLIVE_2_D', '0x732ac', '') > +('PLANE_SURFLIVE_3_D', '0x733ac', '') > +('PLANE_SURFLIVE_4_D', '0x734ac', '') > +('PLANE_SURFLIVE_5_D', '0x735ac', '') > +('PLANE_SURFLIVE_6_D', '0x736ac', '') > +('PLANE_SURFLIVE_7_D', '0x737ac', '') > +('PLANE_POS_1_D', '0x7318c', '') > +('PLANE_POS_2_D', '0x7328c', '') > +('PLANE_POS_3_D', '0x7338c', '') > +('PLANE_POS_4_D', '0x7348c', '') > +('PLANE_POS_5_D', '0x7358c', '') > +('PLANE_POS_6_D', '0x7368c', '') > +('PLANE_POS_7_D', '0x7378c', '') > +('PLANE_SIZE_1_D', '0x73190', '') > +('PLANE_SIZE_2_D', '0x73290', '') > +('PLANE_SIZE_3_D', '0x73390', '') > +('PLANE_SIZE_4_D', '0x73490', '') > +('PLANE_SIZE_5_D', '0x73590', '') > +('PLANE_SIZE_6_D', '0x73690', '') > +('PLANE_SIZE_7_D', '0x73790', '') > +('PLANE_WM_1_D_0', '0x73240', '') > +('PLANE_WM_1_D_1', '0x73244', '') > +('PLANE_WM_1_D_2', '0x73248', '') > +('PLANE_WM_1_D_3', '0x7324c', '') > +('PLANE_WM_1_D_4', '0x73250', '') > +('PLANE_WM_1_D_5', '0x73254', '') > +('PLANE_WM_1_D_6', '0x73258', '') > +('PLANE_WM_1_D_7', '0x7325c', '') > +('PLANE_WM_2_D_0', '0x73340', '') > +('PLANE_WM_2_D_1', '0x73344', '') > +('PLANE_WM_2_D_2', '0x73348', '') > +('PLANE_WM_2_D_3', '0x7334c', '') > +('PLANE_WM_2_D_4', '0x73350', '') > +('PLANE_WM_2_D_5', '0x73354', '') > +('PLANE_WM_2_D_6', '0x73358', '') > +('PLANE_WM_2_D_7', '0x7335c', '') > +('PLANE_WM_3_D_0', '0x73440', '') > +('PLANE_WM_3_D_1', '0x73444', '') > +('PLANE_WM_3_D_2', '0x73448', '') > +('PLANE_WM_3_D_3', '0x7344c', '') > +('PLANE_WM_3_D_4', '0x73450', '') > +('PLANE_WM_3_D_5', '0x73454', '') > +('PLANE_WM_3_D_6', '0x73458', '') > +('PLANE_WM_3_D_7', '0x7345c', '') > +('PLANE_WM_4_D_0', '0x73540', '') > +('PLANE_WM_4_D_1', '0x73544', '') > +('PLANE_WM_4_D_2', '0x73548', '') > +('PLANE_WM_4_D_3', '0x7354c', '') > +('PLANE_WM_4_D_4', '0x73550', '') > +('PLANE_WM_4_D_5', '0x73554', '') > +('PLANE_WM_4_D_6', '0x73558', '') > +('PLANE_WM_4_D_7', '0x7355c', '') > +('PLANE_WM_5_D_0', '0x73640', '') > +('PLANE_WM_5_D_1', '0x73644', '') > +('PLANE_WM_5_D_2', '0x73648', '') > +('PLANE_WM_5_D_3', '0x7364c', '') > +('PLANE_WM_5_D_4', '0x73650', '') > +('PLANE_WM_5_D_5', '0x73654', '') > +('PLANE_WM_5_D_6', '0x73658', '') > +('PLANE_WM_5_D_7', '0x7365c', '') > +('PLANE_WM_6_D_0', '0x73740', '') > +('PLANE_WM_6_D_1', '0x73744', '') > +('PLANE_WM_6_D_2', '0x73748', '') > +('PLANE_WM_6_D_3', '0x7374c', '') > +('PLANE_WM_6_D_4', '0x73750', '') > +('PLANE_WM_6_D_5', '0x73754', '') > +('PLANE_WM_6_D_6', '0x73758', '') > +('PLANE_WM_6_D_7', '0x7375c', '') > +('PLANE_WM_7_D_0', '0x73840', '') > +('PLANE_WM_7_D_1', '0x73844', '') > +('PLANE_WM_7_D_2', '0x73848', '') > +('PLANE_WM_7_D_3', '0x7384c', '') > +('PLANE_WM_7_D_4', '0x73850', '') > +('PLANE_WM_7_D_5', '0x73854', '') > +('PLANE_WM_7_D_6', '0x73858', '') > +('PLANE_WM_7_D_7', '0x7385c', '') > +('PLANE_WM_TRANS_1_D', '0x73268', '') > +('PLANE_WM_TRANS_2_D', '0x73368', '') > +('PLANE_WM_TRANS_3_D', '0x73468', '') > +('PLANE_WM_TRANS_4_D', '0x73568', '') > +('PLANE_WM_TRANS_5_D', '0x73668', '') > +('PLANE_WM_TRANS_6_D', '0x73768', '') > +('PLANE_WM_TRANS_7_D', '0x73868', '') > +# PIPE_D_CURSOR_PLANE > +('CUR_BUF_CFG_D', '0x7317c', '') > +('CUR_BASE_D', '0x73084', '') > +('CUR_CTL_D', '0x73080', '') > +('CUR_FBC_CTL_D', '0x730a0', '') > +('CUR_POS_D', '0x73088', '') > +('CUR_SURFLIVE_D', '0x730ac', '') > +('CUR_WM_0_D', '0x73140', '') > +('CUR_WM_1_D', '0x73144', '') > +('CUR_WM_2_D', '0x73148', '') > +('CUR_WM_3_D', '0x7314c', '') > +('CUR_WM_4_D', '0x73150', '') > +('CUR_WM_5_D', '0x73154', '') > +('CUR_WM_6_D', '0x73158', '') > +('CUR_WM_7_D', '0x7315c', '') > +('CUR_WM_TRANS_D', '0x73168', '') > +#PIPE_SCALER_D > +('PS_CTRL_1_D', '0x69980', '') > +('PS_CTRL_2_D', '0x69a80', '') > +('PS_ECC_STAT_1_D', '0x699d0', '') > +('PS_ECC_STAT_2_D', '0x69ad0', '') > +('PS_HPHASE_1_D', '0x69994', '') > +('PS_HPHASE_2_D', '0x69a94', '') > +('PS_HSCALE_1_D', '0x69990', '') > +('PS_HSCALE_2_D', '0x69a90', '') > +('PS_PWR_GATE_1_D', '0x69960', '') > +('PS_PWR_GATE_2_D', '0x69a60', '') > +('PS_VPHASE_1_D', '0x69988', '') > +('PS_VPHASE_2_D', '0x69a88', '') > +('PS_VSCALE_1_D', '0x69984', '') > +('PS_VSCALE_2_D', '0x69a84', '') > +('PS_WIN_POS_1_D', '0x69970', '') > +('PS_WIN_POS_2_D', '0x69a70', '') > +('PS_WIN_SZ_1_D', '0x69974', '') > +('PS_WIN_SZ_2_D', '0x69a74', '') > +#TRANSCODER_D_CONTROL > +('TRANS_CONF_D', '0x73008', '') > +#TRANSCODER_DSI_CONTROL > +('TRANS_CONF_DSI0', '0x7b008', '') > +('TRANS_CONF_DSI1', '0x7b808', '') > +# TRANSCODER_D_TIMING > +('TRANS_HBLANK_D', '0x63004', '') > +('TRANS_HSYNC_D', '0x63008', '') > +('TRANS_HTOTAL_D', '0x63000', '') > +('TRANS_MULT_D', '0x6302c', '') > +('TRANS_SPACE_D', '0x63024', '') > +('TRANS_VBLANK_D', '0x63010', '') > +('TRANS_VSYNC_D', '0x63014', '') > +('TRANS_VSYNCSHIFT_D', '0x63028', '') > +('TRANS_VTOTAL_D', '0x6300c', '') > +# TRANSCODER_DSI_TIMING > +('TRANS_HSYNC_DSI0', '0x6b008', '') > +('TRANS_HSYNC_DSI1', '0x6b808', '') > +('TRANS_HTOTAL_DSI0', '0x6b000', '') > +('TRANS_HTOTAL_DSI1', '0x6b800', '') > +('TRANS_SPACE_DSI0', '0x6b024', '') > +('TRANS_SPACE_DSI1', '0x6b824', '') > +('TRANS_VBLANK_DSI0', '0x6b010', '') > +('TRANS_VBLANK_DSI1', '0x6b810', '') > +('TRANS_VSYNC_DSI0', '0x6b014', '') > +('TRANS_VSYNC_DSI1', '0x6b814', '') > +('TRANS_VSYNCSHIFT_DSI0', '0x6b028', '') > +('TRANS_VSYNCSHIFT_DSI1', '0x6b828', '') > +('TRANS_VTOTAL_DSI0', '0x6b00c', '') > +('TRANS_VTOTAL_DSI1', '0x6b80c', '') > +# TRANSCODER_D_M_N > +('TRANS_DATAM1_D', '0x63030', '') > +('TRANS_DATAN1_D', '0x63034', '') > +('TRANS_LINKM1_D', '0x63040', '') > +('TRANS_LINKN1_D', '0x63044', '') > +# TRANSCODER_D_DDI_CONTROL > +('TRANS_DDI_FUNC_CTL_D', '0x63400', '') > +('TRANS_MSA_MISC_D', '0x63410', '') > +# TRANSCODER_DSI_DDI_CONTROL > +('TRANS_DDI_FUNC_CTL_DSI0', '0x6b400', '') > +('TRANS_DDI_FUNC_CTL_DSI1', '0x6bc00', '') > +# MBUS_CTL > +('MBUS_DBOX_CTL_D', '0x7303c', '') > +# WATERMARK > +('WM_LINETIME_D', '0x4527c', '') > + > -- > 2.7.4 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] Add TigerLake Registers file 2020-01-21 9:30 ` [igt-dev] [PATCH i-g-t] " Petri Latvala @ 2020-01-21 9:31 ` Petri Latvala 0 siblings, 0 replies; 5+ messages in thread From: Petri Latvala @ 2020-01-21 9:31 UTC (permalink / raw) To: John Machado; +Cc: igt-dev On Tue, Jan 21, 2020 at 11:30:14AM +0200, Petri Latvala wrote: > On Fri, Jan 17, 2020 at 05:27:59AM +0530, John Machado wrote: > > Added the TigerLake register spec file and a register delta file > > that contain additional registers corresponding to TigerLake. > > > > The spec file uses the icelake file along with the newly added > > register file for TGL register definations. > > > > Suggested-by: Swati Sharma <swati2.sharma@intel.com> > > Signed-off-by: John Machado <john.machado@intel.com> > > igt@tools_test@tools_test doesn't explode. The values I'm not going to > check, if they're incorrect we can fix them later, they're only used > by the tools and won't affect CI. > > Acked-by: Petri Latvala <petri.latvala@intel.com> And now merged, thanks. -- Petri Latvala _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-01-21 9:31 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-01-16 23:57 [igt-dev] [PATCH i-g-t] Add TigerLake Registers file John Machado 2020-01-17 7:49 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork 2020-01-21 4:24 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 2020-01-21 9:30 ` [igt-dev] [PATCH i-g-t] " Petri Latvala 2020-01-21 9:31 ` Petri Latvala
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