[Intel-gfx] [PATCH i-g-t] i915: Update i915_drm.h

[Intel-gfx] [PATCH i-g-t] i915: Update i915_drm.h

[Chris Wilson]

Copy uapi/i915_drm.h across from
kernel commit d1172ab3d443e84ade75285f8c107bfac7e386d8
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Fri Apr 12 08:14:16 2019 +0100

    drm/i915: Introduce struct class_instance for engines across the uAPI

and adapt gem_ctx_sseu to match the new struct.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 include/drm-uapi/i915_drm.h | 191 +++++++++++++++++++++++++-----------
 tests/i915/gem_ctx_sseu.c   |  26 ++---
 2 files changed, 147 insertions(+), 70 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 4ae1c6ff6..e01b3e1fd 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -62,6 +62,28 @@ extern "C" {
 #define I915_ERROR_UEVENT		"ERROR"
 #define I915_RESET_UEVENT		"RESET"
 
+/*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+	__u64 next_extension;
+	__u32 name;
+	__u32 flags; /* All undefined bits must be zero. */
+	__u32 rsvd[4]; /* Reserved for future use; must be zero. */
+};
+
 /*
  * MOCS indexes used for GPU surfaces, defining the cacheability of the
  * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
@@ -104,6 +126,18 @@ enum drm_i915_gem_engine_class {
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
+/*
+ * There may be more than one engine fulfilling any role within the system.
+ * Each engine of a class is given a unique instance number and therefore
+ * any engine can be specified by its class:instance tuplet. APIs that allow
+ * access to any engine in the system will use struct i915_engine_class_instance
+ * for this identification.
+ */
+struct i915_engine_class_instance {
+	__u16 engine_class; /* see enum drm_i915_gem_engine_class */
+	__u16 engine_instance;
+};
+
 /**
  * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
  *
@@ -370,6 +404,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
 #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -1421,65 +1456,17 @@ struct drm_i915_gem_wait {
 };
 
 struct drm_i915_gem_context_create {
-	/*  output: id of new context*/
-	__u32 ctx_id;
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 pad;
 };
 
-struct drm_i915_gem_context_destroy {
-	__u32 ctx_id;
-	__u32 pad;
-};
-
-struct drm_i915_reg_read {
-	/*
-	 * Register offset.
-	 * For 64bit wide registers where the upper 32bits don't immediately
-	 * follow the lower 32bits, the offset of the lower 32bits must
-	 * be specified
-	 */
-	__u64 offset;
-#define I915_REG_READ_8B_WA (1ul << 0)
-
-	__u64 val; /* Return value */
-};
-/* Known registers:
- *
- * Render engine timestamp - 0x2358 + 64bit - gen7+
- * - Note this register returns an invalid value if using the default
- *   single instruction 8byte read, in order to workaround that pass
- *   flag I915_REG_READ_8B_WA in offset field.
- *
- */
-
-struct drm_i915_reset_stats {
-	__u32 ctx_id;
-	__u32 flags;
-
-	/* All resets since boot/module reload, for all contexts */
-	__u32 reset_count;
-
-	/* Number of batches lost when active in GPU, for this context */
-	__u32 batch_active;
-
-	/* Number of batches lost pending for execution, for this context */
-	__u32 batch_pending;
-
-	__u32 pad;
-};
-
-struct drm_i915_gem_userptr {
-	__u64 user_ptr;
-	__u64 user_size;
+struct drm_i915_gem_context_create_ext {
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 flags;
-#define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
-	/**
-	 * Returned handle for the object.
-	 *
-	 * Object handles are nonzero.
-	 */
-	__u32 handle;
+#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS	(1u << 0)
+#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
+	(-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
+	__u64 extensions;
 };
 
 struct drm_i915_gem_context_param {
@@ -1521,6 +1508,7 @@ struct drm_i915_gem_context_param {
  */
 #define I915_CONTEXT_PARAM_RECOVERABLE	0x8
 /* Must be kept compact -- no holes and well documented */
+
 	__u64 value;
 };
 
@@ -1549,8 +1537,7 @@ struct drm_i915_gem_context_param_sseu {
 	/*
 	 * Engine class & instance to be configured or queried.
 	 */
-	__u16 engine_class;
-	__u16 engine_instance;
+	struct i915_engine_class_instance engine;
 
 	/*
 	 * Unused for now. Must be cleared to zero.
@@ -1583,6 +1570,96 @@ struct drm_i915_gem_context_param_sseu {
 	__u32 rsvd;
 };
 
+struct drm_i915_gem_context_create_ext_setparam {
+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
+	struct i915_user_extension base;
+	struct drm_i915_gem_context_param param;
+};
+
+struct drm_i915_gem_context_destroy {
+	__u32 ctx_id;
+	__u32 pad;
+};
+
+/*
+ * DRM_I915_GEM_VM_CREATE -
+ *
+ * Create a new virtual memory address space (ppGTT) for use within a context
+ * on the same file. Extensions can be provided to configure exactly how the
+ * address space is setup upon creation.
+ *
+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
+ * returned in the outparam @id.
+ *
+ * No flags are defined, with all bits reserved and must be zero.
+ *
+ * An extension chain maybe provided, starting with @extensions, and terminated
+ * by the @next_extension being 0. Currently, no extensions are defined.
+ *
+ * DRM_I915_GEM_VM_DESTROY -
+ *
+ * Destroys a previously created VM id, specified in @id.
+ *
+ * No extensions or flags are allowed currently, and so must be zero.
+ */
+struct drm_i915_gem_vm_control {
+	__u64 extensions;
+	__u32 flags;
+	__u32 vm_id;
+};
+
+struct drm_i915_reg_read {
+	/*
+	 * Register offset.
+	 * For 64bit wide registers where the upper 32bits don't immediately
+	 * follow the lower 32bits, the offset of the lower 32bits must
+	 * be specified
+	 */
+	__u64 offset;
+#define I915_REG_READ_8B_WA (1ul << 0)
+
+	__u64 val; /* Return value */
+};
+
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ *   single instruction 8byte read, in order to workaround that pass
+ *   flag I915_REG_READ_8B_WA in offset field.
+ *
+ */
+
+struct drm_i915_reset_stats {
+	__u32 ctx_id;
+	__u32 flags;
+
+	/* All resets since boot/module reload, for all contexts */
+	__u32 reset_count;
+
+	/* Number of batches lost when active in GPU, for this context */
+	__u32 batch_active;
+
+	/* Number of batches lost pending for execution, for this context */
+	__u32 batch_pending;
+
+	__u32 pad;
+};
+
+struct drm_i915_gem_userptr {
+	__u64 user_ptr;
+	__u64 user_size;
+	__u32 flags;
+#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	__u32 handle;
+};
+
 enum drm_i915_oa_format {
 	I915_OA_FORMAT_A13 = 1,	    /* HSW only */
 	I915_OA_FORMAT_A29,	    /* HSW only */
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index 3afa5c152..48e4411c8 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -144,23 +144,23 @@ static void test_engines(int fd)
 
 	/* get_param */
 
-	sseu.engine_instance = -1; /* Assumed invalid. */
+	sseu.engine.engine_instance = -1; /* Assumed invalid. */
 	igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
 
-	sseu.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
+	sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
 	igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
 
-	sseu.engine_instance = 0; /* Class invalid. */
+	sseu.engine.engine_instance = 0; /* Class invalid. */
 	igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
-	sseu.engine_class = I915_ENGINE_CLASS_RENDER;
+	sseu.engine.engine_class = I915_ENGINE_CLASS_RENDER;
 
 	last_with_engines = -1;
 	for (class = 0; class < ~0; class++) {
 		for (instance = 0; instance < ~0; instance++) {
 			int ret;
 
-			sseu.engine_class = class;
-			sseu.engine_instance = instance;
+			sseu.engine.engine_class = class;
+			sseu.engine.engine_instance = instance;
 
 			ret = __gem_context_get_param(fd, &arg);
 
@@ -182,19 +182,19 @@ static void test_engines(int fd)
 	 * Get some proper values before trying to reprogram them onto
 	 * an invalid engine.
 	 */
-	sseu.engine_class = 0;
-	sseu.engine_instance = 0;
+	sseu.engine.engine_class = 0;
+	sseu.engine.engine_instance = 0;
 	gem_context_get_param(fd, &arg);
 
 	/* set_param */
 
-	sseu.engine_instance = -1; /* Assumed invalid. */
+	sseu.engine.engine_instance = -1; /* Assumed invalid. */
 	igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
 
-	sseu.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
+	sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
 	igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
 
-	sseu.engine_instance = 0; /* Class invalid. */
+	sseu.engine.engine_instance = 0; /* Class invalid. */
 	igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
 
 	last_with_engines = -1;
@@ -202,8 +202,8 @@ static void test_engines(int fd)
 		for (instance = 0; instance < ~0; instance++) {
 			int ret;
 
-			sseu.engine_class = class;
-			sseu.engine_instance = instance;
+			sseu.engine.engine_class = class;
+			sseu.engine.engine_instance = instance;
 
 			ret = __gem_context_set_param(fd, &arg);
 
-- 
2.20.1

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Re: [igt-dev] [PATCH i-g-t] i915: Update i915_drm.h

[Tvrtko Ursulin]

On 17/04/2019 07:32, Chris Wilson wrote:
> Copy uapi/i915_drm.h across from
> kernel commit d1172ab3d443e84ade75285f8c107bfac7e386d8
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date:   Fri Apr 12 08:14:16 2019 +0100
> 
>      drm/i915: Introduce struct class_instance for engines across the uAPI
> 
> and adapt gem_ctx_sseu to match the new struct.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   include/drm-uapi/i915_drm.h | 191 +++++++++++++++++++++++++-----------
>   tests/i915/gem_ctx_sseu.c   |  26 ++---
>   2 files changed, 147 insertions(+), 70 deletions(-)
> 
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index 4ae1c6ff6..e01b3e1fd 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -62,6 +62,28 @@ extern "C" {
>   #define I915_ERROR_UEVENT		"ERROR"
>   #define I915_RESET_UEVENT		"RESET"
>   
> +/*
> + * i915_user_extension: Base class for defining a chain of extensions
> + *
> + * Many interfaces need to grow over time. In most cases we can simply
> + * extend the struct and have userspace pass in more data. Another option,
> + * as demonstrated by Vulkan's approach to providing extensions for forward
> + * and backward compatibility, is to use a list of optional structs to
> + * provide those extra details.
> + *
> + * The key advantage to using an extension chain is that it allows us to
> + * redefine the interface more easily than an ever growing struct of
> + * increasing complexity, and for large parts of that interface to be
> + * entirely optional. The downside is more pointer chasing; chasing across
> + * the boundary with pointers encapsulated inside u64.
> + */
> +struct i915_user_extension {
> +	__u64 next_extension;
> +	__u32 name;
> +	__u32 flags; /* All undefined bits must be zero. */
> +	__u32 rsvd[4]; /* Reserved for future use; must be zero. */
> +};
> +
>   /*
>    * MOCS indexes used for GPU surfaces, defining the cacheability of the
>    * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
> @@ -104,6 +126,18 @@ enum drm_i915_gem_engine_class {
>   	I915_ENGINE_CLASS_INVALID	= -1
>   };
>   
> +/*
> + * There may be more than one engine fulfilling any role within the system.
> + * Each engine of a class is given a unique instance number and therefore
> + * any engine can be specified by its class:instance tuplet. APIs that allow
> + * access to any engine in the system will use struct i915_engine_class_instance
> + * for this identification.
> + */
> +struct i915_engine_class_instance {
> +	__u16 engine_class; /* see enum drm_i915_gem_engine_class */
> +	__u16 engine_instance;
> +};
> +
>   /**
>    * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
>    *
> @@ -370,6 +404,7 @@ typedef struct _drm_i915_sarea {
>   #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
>   #define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
>   #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
> +#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
>   #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
>   #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
>   #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
> @@ -1421,65 +1456,17 @@ struct drm_i915_gem_wait {
>   };
>   
>   struct drm_i915_gem_context_create {
> -	/*  output: id of new context*/
> -	__u32 ctx_id;
> +	__u32 ctx_id; /* output: id of new context*/
>   	__u32 pad;
>   };
>   
> -struct drm_i915_gem_context_destroy {
> -	__u32 ctx_id;
> -	__u32 pad;
> -};
> -
> -struct drm_i915_reg_read {
> -	/*
> -	 * Register offset.
> -	 * For 64bit wide registers where the upper 32bits don't immediately
> -	 * follow the lower 32bits, the offset of the lower 32bits must
> -	 * be specified
> -	 */
> -	__u64 offset;
> -#define I915_REG_READ_8B_WA (1ul << 0)
> -
> -	__u64 val; /* Return value */
> -};
> -/* Known registers:
> - *
> - * Render engine timestamp - 0x2358 + 64bit - gen7+
> - * - Note this register returns an invalid value if using the default
> - *   single instruction 8byte read, in order to workaround that pass
> - *   flag I915_REG_READ_8B_WA in offset field.
> - *
> - */
> -
> -struct drm_i915_reset_stats {
> -	__u32 ctx_id;
> -	__u32 flags;
> -
> -	/* All resets since boot/module reload, for all contexts */
> -	__u32 reset_count;
> -
> -	/* Number of batches lost when active in GPU, for this context */
> -	__u32 batch_active;
> -
> -	/* Number of batches lost pending for execution, for this context */
> -	__u32 batch_pending;
> -
> -	__u32 pad;
> -};
> -
> -struct drm_i915_gem_userptr {
> -	__u64 user_ptr;
> -	__u64 user_size;
> +struct drm_i915_gem_context_create_ext {
> +	__u32 ctx_id; /* output: id of new context*/
>   	__u32 flags;
> -#define I915_USERPTR_READ_ONLY 0x1
> -#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
> -	/**
> -	 * Returned handle for the object.
> -	 *
> -	 * Object handles are nonzero.
> -	 */
> -	__u32 handle;
> +#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS	(1u << 0)
> +#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
> +	(-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
> +	__u64 extensions;
>   };
>   
>   struct drm_i915_gem_context_param {
> @@ -1521,6 +1508,7 @@ struct drm_i915_gem_context_param {
>    */
>   #define I915_CONTEXT_PARAM_RECOVERABLE	0x8
>   /* Must be kept compact -- no holes and well documented */
> +
>   	__u64 value;
>   };
>   
> @@ -1549,8 +1537,7 @@ struct drm_i915_gem_context_param_sseu {
>   	/*
>   	 * Engine class & instance to be configured or queried.
>   	 */
> -	__u16 engine_class;
> -	__u16 engine_instance;
> +	struct i915_engine_class_instance engine;
>   
>   	/*
>   	 * Unused for now. Must be cleared to zero.
> @@ -1583,6 +1570,96 @@ struct drm_i915_gem_context_param_sseu {
>   	__u32 rsvd;
>   };
>   
> +struct drm_i915_gem_context_create_ext_setparam {
> +#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
> +	struct i915_user_extension base;
> +	struct drm_i915_gem_context_param param;
> +};
> +
> +struct drm_i915_gem_context_destroy {
> +	__u32 ctx_id;
> +	__u32 pad;
> +};
> +
> +/*
> + * DRM_I915_GEM_VM_CREATE -
> + *
> + * Create a new virtual memory address space (ppGTT) for use within a context
> + * on the same file. Extensions can be provided to configure exactly how the
> + * address space is setup upon creation.
> + *
> + * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
> + * returned in the outparam @id.
> + *
> + * No flags are defined, with all bits reserved and must be zero.
> + *
> + * An extension chain maybe provided, starting with @extensions, and terminated
> + * by the @next_extension being 0. Currently, no extensions are defined.
> + *
> + * DRM_I915_GEM_VM_DESTROY -
> + *
> + * Destroys a previously created VM id, specified in @id.
> + *
> + * No extensions or flags are allowed currently, and so must be zero.
> + */
> +struct drm_i915_gem_vm_control {
> +	__u64 extensions;
> +	__u32 flags;
> +	__u32 vm_id;
> +};
> +
> +struct drm_i915_reg_read {
> +	/*
> +	 * Register offset.
> +	 * For 64bit wide registers where the upper 32bits don't immediately
> +	 * follow the lower 32bits, the offset of the lower 32bits must
> +	 * be specified
> +	 */
> +	__u64 offset;
> +#define I915_REG_READ_8B_WA (1ul << 0)
> +
> +	__u64 val; /* Return value */
> +};
> +
> +/* Known registers:
> + *
> + * Render engine timestamp - 0x2358 + 64bit - gen7+
> + * - Note this register returns an invalid value if using the default
> + *   single instruction 8byte read, in order to workaround that pass
> + *   flag I915_REG_READ_8B_WA in offset field.
> + *
> + */
> +
> +struct drm_i915_reset_stats {
> +	__u32 ctx_id;
> +	__u32 flags;
> +
> +	/* All resets since boot/module reload, for all contexts */
> +	__u32 reset_count;
> +
> +	/* Number of batches lost when active in GPU, for this context */
> +	__u32 batch_active;
> +
> +	/* Number of batches lost pending for execution, for this context */
> +	__u32 batch_pending;
> +
> +	__u32 pad;
> +};
> +
> +struct drm_i915_gem_userptr {
> +	__u64 user_ptr;
> +	__u64 user_size;
> +	__u32 flags;
> +#define I915_USERPTR_READ_ONLY 0x1
> +#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
> +	/**
> +	 * Returned handle for the object.
> +	 *
> +	 * Object handles are nonzero.
> +	 */
> +	__u32 handle;
> +};
> +
>   enum drm_i915_oa_format {
>   	I915_OA_FORMAT_A13 = 1,	    /* HSW only */
>   	I915_OA_FORMAT_A29,	    /* HSW only */
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index 3afa5c152..48e4411c8 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -144,23 +144,23 @@ static void test_engines(int fd)
>   
>   	/* get_param */
>   
> -	sseu.engine_instance = -1; /* Assumed invalid. */
> +	sseu.engine.engine_instance = -1; /* Assumed invalid. */
>   	igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
>   
> -	sseu.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
> +	sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
>   	igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
>   
> -	sseu.engine_instance = 0; /* Class invalid. */
> +	sseu.engine.engine_instance = 0; /* Class invalid. */
>   	igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
> -	sseu.engine_class = I915_ENGINE_CLASS_RENDER;
> +	sseu.engine.engine_class = I915_ENGINE_CLASS_RENDER;
>   
>   	last_with_engines = -1;
>   	for (class = 0; class < ~0; class++) {
>   		for (instance = 0; instance < ~0; instance++) {
>   			int ret;
>   
> -			sseu.engine_class = class;
> -			sseu.engine_instance = instance;
> +			sseu.engine.engine_class = class;
> +			sseu.engine.engine_instance = instance;
>   
>   			ret = __gem_context_get_param(fd, &arg);
>   
> @@ -182,19 +182,19 @@ static void test_engines(int fd)
>   	 * Get some proper values before trying to reprogram them onto
>   	 * an invalid engine.
>   	 */
> -	sseu.engine_class = 0;
> -	sseu.engine_instance = 0;
> +	sseu.engine.engine_class = 0;
> +	sseu.engine.engine_instance = 0;
>   	gem_context_get_param(fd, &arg);
>   
>   	/* set_param */
>   
> -	sseu.engine_instance = -1; /* Assumed invalid. */
> +	sseu.engine.engine_instance = -1; /* Assumed invalid. */
>   	igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
>   
> -	sseu.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
> +	sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
>   	igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
>   
> -	sseu.engine_instance = 0; /* Class invalid. */
> +	sseu.engine.engine_instance = 0; /* Class invalid. */
>   	igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
>   
>   	last_with_engines = -1;
> @@ -202,8 +202,8 @@ static void test_engines(int fd)
>   		for (instance = 0; instance < ~0; instance++) {
>   			int ret;
>   
> -			sseu.engine_class = class;
> -			sseu.engine_instance = instance;
> +			sseu.engine.engine_class = class;
> +			sseu.engine.engine_instance = instance;
>   
>   			ret = __gem_context_set_param(fd, &arg);
>   
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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[igt-dev] ✓ Fi.CI.BAT: success for i915: Update i915_drm.h

[Patchwork]

== Series Details ==

Series: i915: Update i915_drm.h
URL   : https://patchwork.freedesktop.org/series/59623/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5943 -> IGTPW_2881
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/59623/revisions/1/mbox/

Known issues
------------

  Here are the changes found in IGTPW_2881 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - fi-glk-dsi:         PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191]

  
#### Possible fixes ####

  * igt@i915_selftest@live_hangcheck:
    - fi-skl-iommu:       INCOMPLETE [fdo#108602] / [fdo#108744] -> PASS

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#103191] -> PASS

  
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (50 -> 44)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

    * IGT: IGT_4954 -> IGTPW_2881

  CI_DRM_5943: 739f9bd5ae97972c9eebf3fe3574a59f286719ff @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2881: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2881/
  IGT_4954: a2fd0489c87a4d647c339f98057e6a1550e0e2f5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2881/
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[igt-dev] ✓ Fi.CI.IGT: success for i915: Update i915_drm.h

[Patchwork]

== Series Details ==

Series: i915: Update i915_drm.h
URL   : https://patchwork.freedesktop.org/series/59623/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5943_full -> IGTPW_2881_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/59623/revisions/1/mbox/

Known issues
------------

  Here are the changes found in IGTPW_2881_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_tiled_swapping@non-threaded:
    - shard-hsw:          PASS -> FAIL [fdo#108686]

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          PASS -> DMESG-WARN [fdo#108566] +2

  * igt@kms_busy@extended-modeset-hang-oldfb-render-d:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1

  * igt@kms_busy@extended-pageflip-hang-oldfb-render-f:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1

  * igt@kms_content_protection@legacy:
    - shard-apl:          NOTRUN -> FAIL [fdo#110321] / [fdo#110336]

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-hsw:          PASS -> INCOMPLETE [fdo#103540]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-glk:          PASS -> FAIL [fdo#103167]
    - shard-kbl:          PASS -> FAIL [fdo#103167]
    - shard-apl:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] +123

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +4

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] +17

  * igt@kms_lease@cursor_implicit_plane:
    - shard-apl:          NOTRUN -> FAIL [fdo#110278]

  * igt@kms_panel_fitting@legacy:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] +21

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-f:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-glk:          PASS -> SKIP [fdo#109271]

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-apl:          NOTRUN -> FAIL [fdo#108145] +2

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         PASS -> SKIP [fdo#109642]

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         PASS -> SKIP [fdo#109441] +1

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-snb:          PASS -> SKIP [fdo#109271] +3

  
#### Possible fixes ####

  * igt@i915_selftest@live_workarounds:
    - shard-iclb:         DMESG-FAIL [fdo#108954] -> PASS

  * igt@i915_suspend@fence-restore-untiled:
    - shard-apl:          DMESG-WARN [fdo#108566] -> PASS +2

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         SKIP [fdo#109349] -> PASS

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-glk:          FAIL [fdo#105363] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
    - shard-apl:          INCOMPLETE [fdo#103927] -> PASS

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +5

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         SKIP [fdo#109441] -> PASS +2

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-apl:          DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +11

  * igt@kms_sysfs_edid_timing:
    - shard-iclb:         FAIL [fdo#100047] -> PASS

  
#### Warnings ####

  * igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing:
    - shard-apl:          INCOMPLETE [fdo#103927] -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-apl:          DMESG-FAIL [fdo#103232] / [fdo#103558] / [fdo#105602] -> DMESG-WARN [fdo#108566]

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-kbl:          FAIL [fdo#109016] -> INCOMPLETE [fdo#103665]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110278]: https://bugs.freedesktop.org/show_bug.cgi?id=110278
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336


Participating hosts (10 -> 6)
------------------------------

  Missing    (4): pig-skl-6260u shard-skl pig-hsw-4770r pig-glk-j5005 


Build changes
-------------

    * IGT: IGT_4954 -> IGTPW_2881
    * Piglit: piglit_4509 -> None

  CI_DRM_5943: 739f9bd5ae97972c9eebf3fe3574a59f286719ff @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2881: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2881/
  IGT_4954: a2fd0489c87a4d647c339f98057e6a1550e0e2f5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2881/
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