[igt-dev] [PATCH i-g-t v3 0/6] IGT bits for small-bar

[igt-dev] [PATCH i-g-t v3 0/6] IGT bits for small-bar

[Matthew Auld]

small-bar IGT changes for Xe.

v2: Rebase on latest IGT, plus various improvements
v3: Rebase + some small fixes

Kernel: https://patchwork.freedesktop.org/series/115515/

-- 
2.41.0

[igt-dev] [PATCH i-g-t v3 1/6] xe: sync small-bar uapi

[Matthew Auld]

We need a couple new fields for the region query and the new flag to
ensure the buffer is CPU accessible.

make headers_install at fcd32328261c ("drm/xe/uapi: add the userspace
bits for small-bar")

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 include/drm-uapi/xe_drm.h | 78 ++++++++++++++++++++++++++++++++++-----
 1 file changed, 69 insertions(+), 9 deletions(-)

diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 432bd87ca..02419c1d5 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -29,7 +29,7 @@ extern "C" {
  * redefine the interface more easily than an ever growing struct of
  * increasing complexity, and for large parts of that interface to be
  * entirely optional. The downside is more pointer chasing; chasing across
- * the __user boundary with pointers encapsulated inside u64.
+ * the boundary with pointers encapsulated inside u64.
  *
  * Example chaining:
  *
@@ -180,8 +180,37 @@ struct drm_xe_query_mem_region {
 	 * zero.
 	 */
 	__u64 used;
+	/*
+	 * @cpu_visible_size: How much of this region can be CPU
+	 * accessed, in bytes.
+	 *
+	 * This will always be <= @total_size, and the remainder (if
+	 * any) will not be CPU accessible. If the CPU accessible part
+	 * is smaller than @total_size then this is referred to as a
+	 * small BAR system.
+	 *
+	 * On systems without small BAR (full BAR), the probed_size will
+	 * always equal the @total_size, since all of it will be CPU
+	 * accessible.
+	 *
+	 * Note this is only tracked for XE_MEM_REGION_CLASS_VRAM
+	 * regions (for other types the value here will always equal
+	 * zero).
+	 */
+	__u64 cpu_visible_size;
+	/**
+	 * @cpu_visible_used: Estimate of CPU visible memory used, in
+	 * bytes.
+	 *
+	 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
+	 * accounting. Without this the value here will always equal
+	 * zero.  Note this is only currently tracked for
+	 * XE_MEM_REGION_CLASS_VRAM regions (for other types the value
+	 * here will always be zero).
+	 */
+	__u64 cpu_visible_used;
 	/** @reserved: MBZ */
-	__u64 reserved[8];
+	__u64 reserved[6];
 };
 
 /**
@@ -242,11 +271,13 @@ struct drm_xe_query_gts {
 	/** @pad: MBZ */
 	__u32 pad;
 
-	/*
+	/**
+	 * @gts: The GTs returned for this device
+	 *
+	 * TODO: convert drm_xe_query_gt to proper kernel-doc.
 	 * TODO: Perhaps info about every mem region relative to this GT? e.g.
 	 * bandwidth between this GT and remote region?
 	 */
-
 	struct drm_xe_query_gt {
 #define XE_QUERY_GT_TYPE_MAIN		0
 #define XE_QUERY_GT_TYPE_REMOTE		1
@@ -381,6 +412,22 @@ struct drm_xe_gem_create {
 
 #define XE_GEM_CREATE_FLAG_DEFER_BACKING	(0x1 << 24)
 #define XE_GEM_CREATE_FLAG_SCANOUT		(0x1 << 25)
+/*
+ * When using VRAM as a possible placement, ensure that the corresponding VRAM
+ * allocation will always use the CPU accessible part of VRAM. This is important
+ * for small-bar systems (on full-bar systems this gets turned into a noop).
+ *
+ * Note: System memory can be used as an extra placement if the kernel should
+ * spill the allocation to system memory, if space can't be made available in
+ * the CPU accessible part of VRAM (giving the same behaviour as the i915
+ * interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS).
+ *
+ * Note: For clear-color CCS surfaces the kernel needs to read the clear-color
+ * value stored in the buffer, and on discrete platforms we need to use VRAM for
+ * display surfaces, therefore the kernel requires setting this flag for such
+ * objects, otherwise an error is thrown on small-bar systems.
+ */
+#define XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(0x1 << 26)
 	/**
 	 * @flags: Flags, currently a mask of memory instances of where BO can
 	 * be placed
@@ -799,7 +846,7 @@ struct drm_xe_exec {
 	/** @extensions: Pointer to the first extension struct, if any */
 	__u64 extensions;
 
-	/** @vm_id: VM ID to run batch buffer in */
+	/** @engine_id: Engine ID for the batch buffer */
 	__u32 engine_id;
 
 	/** @num_syncs: Amount of struct drm_xe_sync in array. */
@@ -852,8 +899,9 @@ struct drm_xe_mmio {
  * struct drm_xe_wait_user_fence - wait user fence
  *
  * Wait on user fence, XE will wakeup on every HW engine interrupt in the
- * instances list and check if user fence is complete:
- * (*addr & MASK) OP (VALUE & MASK)
+ * instances list and check if user fence is complete::
+ *
+ *	(*addr & MASK) OP (VALUE & MASK)
  *
  * Returns to user on user fence completion or timeout.
  */
@@ -901,8 +949,20 @@ struct drm_xe_wait_user_fence {
 #define DRM_XE_UFENCE_WAIT_U64		0xffffffffffffffffu
 	/** @mask: comparison mask */
 	__u64 mask;
-
-	/** @timeout: how long to wait before bailing, value in jiffies */
+	/**
+	 * @timeout: how long to wait before bailing, value in nanoseconds.
+	 * Without DRM_XE_UFENCE_WAIT_ABSTIME flag set (relative timeout)
+	 * it contains timeout expressed in nanoseconds to wait (fence will
+	 * expire at now() + timeout).
+	 * When DRM_XE_UFENCE_WAIT_ABSTIME flat is set (absolute timeout) wait
+	 * will end at timeout (uses system MONOTONIC_CLOCK).
+	 * Passing negative timeout leads to neverending wait.
+	 *
+	 * On relative timeout this value is updated with timeout left
+	 * (for restarting the call in case of signal delivery).
+	 * On absolute timeout this value stays intact (restarted call still
+	 * expire at the same point of time).
+	 */
 	__s64 timeout;
 
 	/**
-- 
2.41.0

[igt-dev] [PATCH i-g-t v3 2/6] lib/xe: add visible vram helpers

[Matthew Auld]

Add helpers for object creation and querying the cpu_visible related bits.

v2: Make it backwards compat with older kernels

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 lib/xe/xe_query.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++-
 lib/xe/xe_query.h |  6 ++++
 2 files changed, 91 insertions(+), 1 deletion(-)

diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index f535ad853..5412fbeb5 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -140,6 +140,17 @@ static uint64_t gt_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
 	return 0;
 }
 
+static uint64_t gt_visible_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
+				     const struct drm_xe_query_gts *gts, int gt)
+{
+	int region_idx = ffs(native_region_for_gt(gts, gt)) - 1;
+
+	if (XE_IS_CLASS_VRAM(&mem_usage->regions[region_idx]))
+		return mem_usage->regions[region_idx].cpu_visible_size;
+
+	return 0;
+}
+
 static bool __mem_has_vram(struct drm_xe_query_mem_usage *mem_usage)
 {
 	for (int i = 0; i < mem_usage->num_regions; i++)
@@ -246,9 +257,14 @@ struct xe_device *xe_device_get(int fd)
 	xe_dev->hw_engines = xe_query_engines_new(fd, &xe_dev->number_hw_engines);
 	xe_dev->mem_usage = xe_query_mem_usage_new(fd);
 	xe_dev->vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->vram_size));
-	for (int gt = 0; gt < xe_dev->number_gt; gt++)
+	xe_dev->visible_vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->visible_vram_size));
+	for (int gt = 0; gt < xe_dev->number_gt; gt++) {
 		xe_dev->vram_size[gt] = gt_vram_size(xe_dev->mem_usage,
 						     xe_dev->gts, gt);
+		xe_dev->visible_vram_size[gt] =
+			gt_visible_vram_size(xe_dev->mem_usage,
+					     xe_dev->gts, gt);
+	}
 	xe_dev->default_alignment = __mem_default_alignment(xe_dev->mem_usage);
 	xe_dev->has_vram = __mem_has_vram(xe_dev->mem_usage);
 
@@ -383,6 +399,33 @@ uint64_t vram_memory(int fd, int gt)
 	return xe_has_vram(fd) ? native_region_for_gt(xe_dev->gts, gt) : 0;
 }
 
+static uint64_t __xe_visible_vram_size(int fd, int gt)
+{
+	struct xe_device *xe_dev;
+
+	xe_dev = find_in_cache(fd);
+	igt_assert(xe_dev);
+
+	return xe_dev->visible_vram_size[gt];
+}
+
+/**
+ * visible_vram_memory:
+ * @fd: xe device fd
+ * @gt: gt id
+ *
+ * Returns vram memory bitmask for xe device @fd and @gt id, with
+ * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
+ * possible.
+ */
+uint64_t visible_vram_memory(int fd, int gt)
+{
+	if (__xe_visible_vram_size(fd, gt))
+		return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
+	else
+		return vram_memory(fd, gt); /* older kernel */
+}
+
 /**
  * vram_if_possible:
  * @fd: xe device fd
@@ -396,6 +439,28 @@ uint64_t vram_if_possible(int fd, int gt)
 	return vram_memory(fd, gt) ?: system_memory(fd);
 }
 
+/**
+ * visible_vram_if_possible:
+ * @fd: xe device fd
+ * @gt: gt id
+ *
+ * Returns vram memory bitmask for xe device @fd and @gt id or system memory if
+ * there's no vram memory available for @gt. Also attaches the
+ * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
+ * when using vram.
+ */
+uint64_t visible_vram_if_possible(int fd, int gt)
+{
+	uint64_t regions = all_memory_regions(fd);
+	uint64_t system_memory = regions & 0x1;
+	uint64_t vram = regions & (0x2 << gt);
+
+	if (__xe_visible_vram_size(fd, gt))
+		return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
+	else
+		return vram ? vram : system_memory; /* older kernel */
+}
+
 /**
  * xe_hw_engines:
  * @fd: xe device fd
@@ -536,6 +601,24 @@ uint64_t xe_vram_size(int fd, int gt)
 	return xe_dev->vram_size[gt];
 }
 
+/**
+ * xe_visible_vram_size:
+ * @fd: xe device fd
+ * @gt: gt
+ *
+ * Returns size of visible vram of xe device @fd.
+ */
+uint64_t xe_visible_vram_size(int fd, int gt)
+{
+	uint64_t visible_size;
+
+	visible_size = __xe_visible_vram_size(fd, gt);
+	if (!visible_size) /* older kernel */
+		visible_size = xe_vram_size(fd, gt);
+
+	return visible_size;
+}
+
 /**
  * xe_get_default_alignment:
  * @fd: xe device fd
@@ -552,6 +635,7 @@ xe_dev_FN(xe_get_default_alignment, default_alignment, uint32_t);
  */
 xe_dev_FN(xe_va_bits, va_bits, uint32_t);
 
+
 /**
  * xe_dev_id:
  * @fd: xe device fd
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 68ca5a680..1b74c58ab 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -47,6 +47,9 @@ struct xe_device {
 	/** @vram_size: array of vram sizes for all gts */
 	uint64_t *vram_size;
 
+	/** @visible_vram_size: array of visible vram sizes for all gts */
+	uint64_t *visible_vram_size;
+
 	/** @default_alignment: safe alignment regardless region location */
 	uint32_t default_alignment;
 
@@ -80,7 +83,9 @@ unsigned int xe_number_gt(int fd);
 uint64_t all_memory_regions(int fd);
 uint64_t system_memory(int fd);
 uint64_t vram_memory(int fd, int gt);
+uint64_t visible_vram_memory(int fd, int gt);
 uint64_t vram_if_possible(int fd, int gt);
+uint64_t visible_vram_if_possible(int fd, int gt);
 struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
 struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
 struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);
@@ -91,6 +96,7 @@ struct drm_xe_query_config *xe_config(int fd);
 unsigned int xe_number_hw_engines(int fd);
 bool xe_has_vram(int fd);
 uint64_t xe_vram_size(int fd, int gt);
+uint64_t xe_visible_vram_size(int fd, int gt);
 uint32_t xe_get_default_alignment(int fd);
 uint32_t xe_va_bits(int fd);
 uint16_t xe_dev_id(int fd);
-- 
2.41.0

Re: [igt-dev] [PATCH i-g-t v3 2/6] lib/xe: add visible vram helpers

[Souza, Jose]

On Fri, 2023-07-14 at 15:42 +0100, Matthew Auld wrote:
> Add helpers for object creation and querying the cpu_visible related bits.
> 
> v2: Make it backwards compat with older kernels
> 
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  lib/xe/xe_query.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++-
>  lib/xe/xe_query.h |  6 ++++
>  2 files changed, 91 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index f535ad853..5412fbeb5 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -140,6 +140,17 @@ static uint64_t gt_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
>  	return 0;
>  }
>  
> +static uint64_t gt_visible_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
> +				     const struct drm_xe_query_gts *gts, int gt)
> +{
> +	int region_idx = ffs(native_region_for_gt(gts, gt)) - 1;
> +
> +	if (XE_IS_CLASS_VRAM(&mem_usage->regions[region_idx]))
> +		return mem_usage->regions[region_idx].cpu_visible_size;
> +
> +	return 0;
> +}
> +
>  static bool __mem_has_vram(struct drm_xe_query_mem_usage *mem_usage)
>  {
>  	for (int i = 0; i < mem_usage->num_regions; i++)
> @@ -246,9 +257,14 @@ struct xe_device *xe_device_get(int fd)
>  	xe_dev->hw_engines = xe_query_engines_new(fd, &xe_dev->number_hw_engines);
>  	xe_dev->mem_usage = xe_query_mem_usage_new(fd);
>  	xe_dev->vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->vram_size));
> -	for (int gt = 0; gt < xe_dev->number_gt; gt++)
> +	xe_dev->visible_vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->visible_vram_size));
> +	for (int gt = 0; gt < xe_dev->number_gt; gt++) {
>  		xe_dev->vram_size[gt] = gt_vram_size(xe_dev->mem_usage,
>  						     xe_dev->gts, gt);
> +		xe_dev->visible_vram_size[gt] =
> +			gt_visible_vram_size(xe_dev->mem_usage,
> +					     xe_dev->gts, gt);
> +	}
>  	xe_dev->default_alignment = __mem_default_alignment(xe_dev->mem_usage);
>  	xe_dev->has_vram = __mem_has_vram(xe_dev->mem_usage);
>  
> @@ -383,6 +399,33 @@ uint64_t vram_memory(int fd, int gt)
>  	return xe_has_vram(fd) ? native_region_for_gt(xe_dev->gts, gt) : 0;
>  }
>  
> +static uint64_t __xe_visible_vram_size(int fd, int gt)
> +{
> +	struct xe_device *xe_dev;
> +
> +	xe_dev = find_in_cache(fd);
> +	igt_assert(xe_dev);
> +
> +	return xe_dev->visible_vram_size[gt];
> +}
> +
> +/**
> + * visible_vram_memory:
> + * @fd: xe device fd
> + * @gt: gt id
> + *
> + * Returns vram memory bitmask for xe device @fd and @gt id, with
> + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
> + * possible.
> + */
> +uint64_t visible_vram_memory(int fd, int gt)
> +{
> +	if (__xe_visible_vram_size(fd, gt))
> +		return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
> +	else
> +		return vram_memory(fd, gt); /* older kernel */

We don't need to maintain any compability with older Xe kernels for now...

> +}
> +
>  /**
>   * vram_if_possible:
>   * @fd: xe device fd
> @@ -396,6 +439,28 @@ uint64_t vram_if_possible(int fd, int gt)
>  	return vram_memory(fd, gt) ?: system_memory(fd);
>  }
>  
> +/**
> + * visible_vram_if_possible:
> + * @fd: xe device fd
> + * @gt: gt id
> + *
> + * Returns vram memory bitmask for xe device @fd and @gt id or system memory if
> + * there's no vram memory available for @gt. Also attaches the
> + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
> + * when using vram.
> + */
> +uint64_t visible_vram_if_possible(int fd, int gt)
> +{
> +	uint64_t regions = all_memory_regions(fd);
> +	uint64_t system_memory = regions & 0x1;
> +	uint64_t vram = regions & (0x2 << gt);
> +
> +	if (__xe_visible_vram_size(fd, gt))
> +		return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
> +	else
> +		return vram ? vram : system_memory; /* older kernel */
> +}

so this can be dropped and current callers should use visible_vram_memory().

> +
>  /**
>   * xe_hw_engines:
>   * @fd: xe device fd
> @@ -536,6 +601,24 @@ uint64_t xe_vram_size(int fd, int gt)
>  	return xe_dev->vram_size[gt];
>  }
>  
> +/**
> + * xe_visible_vram_size:
> + * @fd: xe device fd
> + * @gt: gt
> + *
> + * Returns size of visible vram of xe device @fd.
> + */
> +uint64_t xe_visible_vram_size(int fd, int gt)
> +{
> +	uint64_t visible_size;
> +
> +	visible_size = __xe_visible_vram_size(fd, gt);
> +	if (!visible_size) /* older kernel */
> +		visible_size = xe_vram_size(fd, gt);
> +
> +	return visible_size;
> +}
> +
>  /**
>   * xe_get_default_alignment:
>   * @fd: xe device fd
> @@ -552,6 +635,7 @@ xe_dev_FN(xe_get_default_alignment, default_alignment, uint32_t);
>   */
>  xe_dev_FN(xe_va_bits, va_bits, uint32_t);
>  
> +
>  /**
>   * xe_dev_id:
>   * @fd: xe device fd
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index 68ca5a680..1b74c58ab 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -47,6 +47,9 @@ struct xe_device {
>  	/** @vram_size: array of vram sizes for all gts */
>  	uint64_t *vram_size;
>  
> +	/** @visible_vram_size: array of visible vram sizes for all gts */
> +	uint64_t *visible_vram_size;
> +
>  	/** @default_alignment: safe alignment regardless region location */
>  	uint32_t default_alignment;
>  
> @@ -80,7 +83,9 @@ unsigned int xe_number_gt(int fd);
>  uint64_t all_memory_regions(int fd);
>  uint64_t system_memory(int fd);
>  uint64_t vram_memory(int fd, int gt);
> +uint64_t visible_vram_memory(int fd, int gt);
>  uint64_t vram_if_possible(int fd, int gt);
> +uint64_t visible_vram_if_possible(int fd, int gt);
>  struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
>  struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
>  struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);
> @@ -91,6 +96,7 @@ struct drm_xe_query_config *xe_config(int fd);
>  unsigned int xe_number_hw_engines(int fd);
>  bool xe_has_vram(int fd);
>  uint64_t xe_vram_size(int fd, int gt);
> +uint64_t xe_visible_vram_size(int fd, int gt);
>  uint32_t xe_get_default_alignment(int fd);
>  uint32_t xe_va_bits(int fd);
>  uint16_t xe_dev_id(int fd);

Re: [igt-dev] [PATCH i-g-t v3 2/6] lib/xe: add visible vram helpers

[Souza, Jose]

On Fri, 2023-07-14 at 09:30 -0700, José Roberto de Souza wrote:
> On Fri, 2023-07-14 at 15:42 +0100, Matthew Auld wrote:
> > Add helpers for object creation and querying the cpu_visible related bits.
> > 
> > v2: Make it backwards compat with older kernels
> > 
> > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  lib/xe/xe_query.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++-
> >  lib/xe/xe_query.h |  6 ++++
> >  2 files changed, 91 insertions(+), 1 deletion(-)
> > 
> > diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> > index f535ad853..5412fbeb5 100644
> > --- a/lib/xe/xe_query.c
> > +++ b/lib/xe/xe_query.c
> > @@ -140,6 +140,17 @@ static uint64_t gt_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
> >  	return 0;
> >  }
> >  
> > +static uint64_t gt_visible_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
> > +				     const struct drm_xe_query_gts *gts, int gt)
> > +{
> > +	int region_idx = ffs(native_region_for_gt(gts, gt)) - 1;
> > +
> > +	if (XE_IS_CLASS_VRAM(&mem_usage->regions[region_idx]))
> > +		return mem_usage->regions[region_idx].cpu_visible_size;
> > +
> > +	return 0;
> > +}
> > +
> >  static bool __mem_has_vram(struct drm_xe_query_mem_usage *mem_usage)
> >  {
> >  	for (int i = 0; i < mem_usage->num_regions; i++)
> > @@ -246,9 +257,14 @@ struct xe_device *xe_device_get(int fd)
> >  	xe_dev->hw_engines = xe_query_engines_new(fd, &xe_dev->number_hw_engines);
> >  	xe_dev->mem_usage = xe_query_mem_usage_new(fd);
> >  	xe_dev->vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->vram_size));
> > -	for (int gt = 0; gt < xe_dev->number_gt; gt++)
> > +	xe_dev->visible_vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->visible_vram_size));
> > +	for (int gt = 0; gt < xe_dev->number_gt; gt++) {
> >  		xe_dev->vram_size[gt] = gt_vram_size(xe_dev->mem_usage,
> >  						     xe_dev->gts, gt);
> > +		xe_dev->visible_vram_size[gt] =
> > +			gt_visible_vram_size(xe_dev->mem_usage,
> > +					     xe_dev->gts, gt);
> > +	}
> >  	xe_dev->default_alignment = __mem_default_alignment(xe_dev->mem_usage);
> >  	xe_dev->has_vram = __mem_has_vram(xe_dev->mem_usage);
> >  
> > @@ -383,6 +399,33 @@ uint64_t vram_memory(int fd, int gt)
> >  	return xe_has_vram(fd) ? native_region_for_gt(xe_dev->gts, gt) : 0;
> >  }
> >  
> > +static uint64_t __xe_visible_vram_size(int fd, int gt)
> > +{
> > +	struct xe_device *xe_dev;
> > +
> > +	xe_dev = find_in_cache(fd);
> > +	igt_assert(xe_dev);
> > +
> > +	return xe_dev->visible_vram_size[gt];
> > +}
> > +
> > +/**
> > + * visible_vram_memory:
> > + * @fd: xe device fd
> > + * @gt: gt id
> > + *
> > + * Returns vram memory bitmask for xe device @fd and @gt id, with
> > + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
> > + * possible.
> > + */
> > +uint64_t visible_vram_memory(int fd, int gt)
> > +{
> > +	if (__xe_visible_vram_size(fd, gt))
> > +		return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
> > +	else
> > +		return vram_memory(fd, gt); /* older kernel */
> 
> We don't need to maintain any compability with older Xe kernels for now...
> 
> > +}
> > +
> >  /**
> >   * vram_if_possible:
> >   * @fd: xe device fd
> > @@ -396,6 +439,28 @@ uint64_t vram_if_possible(int fd, int gt)
> >  	return vram_memory(fd, gt) ?: system_memory(fd);
> >  }
> >  
> > +/**
> > + * visible_vram_if_possible:
> > + * @fd: xe device fd
> > + * @gt: gt id
> > + *
> > + * Returns vram memory bitmask for xe device @fd and @gt id or system memory if
> > + * there's no vram memory available for @gt. Also attaches the
> > + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
> > + * when using vram.
> > + */
> > +uint64_t visible_vram_if_possible(int fd, int gt)
> > +{
> > +	uint64_t regions = all_memory_regions(fd);
> > +	uint64_t system_memory = regions & 0x1;
> > +	uint64_t vram = regions & (0x2 << gt);
> > +
> > +	if (__xe_visible_vram_size(fd, gt))
> > +		return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
> > +	else
> > +		return vram ? vram : system_memory; /* older kernel */
> > +}
> 
> so this can be dropped and current callers should use visible_vram_memory().

Ignore the comment above...

But this function should be changed to ignore older Xe KMD behavior.

> 
> > +
> >  /**
> >   * xe_hw_engines:
> >   * @fd: xe device fd
> > @@ -536,6 +601,24 @@ uint64_t xe_vram_size(int fd, int gt)
> >  	return xe_dev->vram_size[gt];
> >  }
> >  
> > +/**
> > + * xe_visible_vram_size:
> > + * @fd: xe device fd
> > + * @gt: gt
> > + *
> > + * Returns size of visible vram of xe device @fd.
> > + */
> > +uint64_t xe_visible_vram_size(int fd, int gt)
> > +{
> > +	uint64_t visible_size;
> > +
> > +	visible_size = __xe_visible_vram_size(fd, gt);
> > +	if (!visible_size) /* older kernel */
> > +		visible_size = xe_vram_size(fd, gt);
> > +
> > +	return visible_size;
> > +}
> > +
> >  /**
> >   * xe_get_default_alignment:
> >   * @fd: xe device fd
> > @@ -552,6 +635,7 @@ xe_dev_FN(xe_get_default_alignment, default_alignment, uint32_t);
> >   */
> >  xe_dev_FN(xe_va_bits, va_bits, uint32_t);
> >  
> > +
> >  /**
> >   * xe_dev_id:
> >   * @fd: xe device fd
> > diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> > index 68ca5a680..1b74c58ab 100644
> > --- a/lib/xe/xe_query.h
> > +++ b/lib/xe/xe_query.h
> > @@ -47,6 +47,9 @@ struct xe_device {
> >  	/** @vram_size: array of vram sizes for all gts */
> >  	uint64_t *vram_size;
> >  
> > +	/** @visible_vram_size: array of visible vram sizes for all gts */
> > +	uint64_t *visible_vram_size;
> > +
> >  	/** @default_alignment: safe alignment regardless region location */
> >  	uint32_t default_alignment;
> >  
> > @@ -80,7 +83,9 @@ unsigned int xe_number_gt(int fd);
> >  uint64_t all_memory_regions(int fd);
> >  uint64_t system_memory(int fd);
> >  uint64_t vram_memory(int fd, int gt);
> > +uint64_t visible_vram_memory(int fd, int gt);
> >  uint64_t vram_if_possible(int fd, int gt);
> > +uint64_t visible_vram_if_possible(int fd, int gt);
> >  struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
> >  struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
> >  struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);
> > @@ -91,6 +96,7 @@ struct drm_xe_query_config *xe_config(int fd);
> >  unsigned int xe_number_hw_engines(int fd);
> >  bool xe_has_vram(int fd);
> >  uint64_t xe_vram_size(int fd, int gt);
> > +uint64_t xe_visible_vram_size(int fd, int gt);
> >  uint32_t xe_get_default_alignment(int fd);
> >  uint32_t xe_va_bits(int fd);
> >  uint16_t xe_dev_id(int fd);
> 

Re: [igt-dev] [PATCH i-g-t v3 2/6] lib/xe: add visible vram helpers

[Matthew Auld]

On 14/07/2023 17:30, Souza, Jose wrote:
> On Fri, 2023-07-14 at 15:42 +0100, Matthew Auld wrote:
>> Add helpers for object creation and querying the cpu_visible related bits.
>>
>> v2: Make it backwards compat with older kernels
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> ---
>>   lib/xe/xe_query.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++-
>>   lib/xe/xe_query.h |  6 ++++
>>   2 files changed, 91 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
>> index f535ad853..5412fbeb5 100644
>> --- a/lib/xe/xe_query.c
>> +++ b/lib/xe/xe_query.c
>> @@ -140,6 +140,17 @@ static uint64_t gt_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
>>   	return 0;
>>   }
>>   
>> +static uint64_t gt_visible_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
>> +				     const struct drm_xe_query_gts *gts, int gt)
>> +{
>> +	int region_idx = ffs(native_region_for_gt(gts, gt)) - 1;
>> +
>> +	if (XE_IS_CLASS_VRAM(&mem_usage->regions[region_idx]))
>> +		return mem_usage->regions[region_idx].cpu_visible_size;
>> +
>> +	return 0;
>> +}
>> +
>>   static bool __mem_has_vram(struct drm_xe_query_mem_usage *mem_usage)
>>   {
>>   	for (int i = 0; i < mem_usage->num_regions; i++)
>> @@ -246,9 +257,14 @@ struct xe_device *xe_device_get(int fd)
>>   	xe_dev->hw_engines = xe_query_engines_new(fd, &xe_dev->number_hw_engines);
>>   	xe_dev->mem_usage = xe_query_mem_usage_new(fd);
>>   	xe_dev->vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->vram_size));
>> -	for (int gt = 0; gt < xe_dev->number_gt; gt++)
>> +	xe_dev->visible_vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->visible_vram_size));
>> +	for (int gt = 0; gt < xe_dev->number_gt; gt++) {
>>   		xe_dev->vram_size[gt] = gt_vram_size(xe_dev->mem_usage,
>>   						     xe_dev->gts, gt);
>> +		xe_dev->visible_vram_size[gt] =
>> +			gt_visible_vram_size(xe_dev->mem_usage,
>> +					     xe_dev->gts, gt);
>> +	}
>>   	xe_dev->default_alignment = __mem_default_alignment(xe_dev->mem_usage);
>>   	xe_dev->has_vram = __mem_has_vram(xe_dev->mem_usage);
>>   
>> @@ -383,6 +399,33 @@ uint64_t vram_memory(int fd, int gt)
>>   	return xe_has_vram(fd) ? native_region_for_gt(xe_dev->gts, gt) : 0;
>>   }
>>   
>> +static uint64_t __xe_visible_vram_size(int fd, int gt)
>> +{
>> +	struct xe_device *xe_dev;
>> +
>> +	xe_dev = find_in_cache(fd);
>> +	igt_assert(xe_dev);
>> +
>> +	return xe_dev->visible_vram_size[gt];
>> +}
>> +
>> +/**
>> + * visible_vram_memory:
>> + * @fd: xe device fd
>> + * @gt: gt id
>> + *
>> + * Returns vram memory bitmask for xe device @fd and @gt id, with
>> + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
>> + * possible.
>> + */
>> +uint64_t visible_vram_memory(int fd, int gt)
>> +{
>> +	if (__xe_visible_vram_size(fd, gt))
>> +		return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
>> +	else
>> +		return vram_memory(fd, gt); /* older kernel */
> 
> We don't need to maintain any compability with older Xe kernels for now...
> 
>> +}
>> +
>>   /**
>>    * vram_if_possible:
>>    * @fd: xe device fd
>> @@ -396,6 +439,28 @@ uint64_t vram_if_possible(int fd, int gt)
>>   	return vram_memory(fd, gt) ?: system_memory(fd);
>>   }
>>   
>> +/**
>> + * visible_vram_if_possible:
>> + * @fd: xe device fd
>> + * @gt: gt id
>> + *
>> + * Returns vram memory bitmask for xe device @fd and @gt id or system memory if
>> + * there's no vram memory available for @gt. Also attaches the
>> + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
>> + * when using vram.
>> + */
>> +uint64_t visible_vram_if_possible(int fd, int gt)
>> +{
>> +	uint64_t regions = all_memory_regions(fd);
>> +	uint64_t system_memory = regions & 0x1;
>> +	uint64_t vram = regions & (0x2 << gt);
>> +
>> +	if (__xe_visible_vram_size(fd, gt))
>> +		return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
>> +	else
>> +		return vram ? vram : system_memory; /* older kernel */
>> +}
> 
> so this can be dropped and current callers should use visible_vram_memory().

Here I just wanted to keep it compatible so I could merge the IGT in any 
order. Ideally I want to merge the IGT first and let that soak for a 
couple of hours, and assuming there is no new breakage I can re-send the 
kernel patches with a hack patch to force small-bar on some CI machine 
to get pre-merge testing. Once that all passes I can merge the kernel 
side. The above compatibility stuff can then be removed after.

> 
>> +
>>   /**
>>    * xe_hw_engines:
>>    * @fd: xe device fd
>> @@ -536,6 +601,24 @@ uint64_t xe_vram_size(int fd, int gt)
>>   	return xe_dev->vram_size[gt];
>>   }
>>   
>> +/**
>> + * xe_visible_vram_size:
>> + * @fd: xe device fd
>> + * @gt: gt
>> + *
>> + * Returns size of visible vram of xe device @fd.
>> + */
>> +uint64_t xe_visible_vram_size(int fd, int gt)
>> +{
>> +	uint64_t visible_size;
>> +
>> +	visible_size = __xe_visible_vram_size(fd, gt);
>> +	if (!visible_size) /* older kernel */
>> +		visible_size = xe_vram_size(fd, gt);
>> +
>> +	return visible_size;
>> +}
>> +
>>   /**
>>    * xe_get_default_alignment:
>>    * @fd: xe device fd
>> @@ -552,6 +635,7 @@ xe_dev_FN(xe_get_default_alignment, default_alignment, uint32_t);
>>    */
>>   xe_dev_FN(xe_va_bits, va_bits, uint32_t);
>>   
>> +
>>   /**
>>    * xe_dev_id:
>>    * @fd: xe device fd
>> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
>> index 68ca5a680..1b74c58ab 100644
>> --- a/lib/xe/xe_query.h
>> +++ b/lib/xe/xe_query.h
>> @@ -47,6 +47,9 @@ struct xe_device {
>>   	/** @vram_size: array of vram sizes for all gts */
>>   	uint64_t *vram_size;
>>   
>> +	/** @visible_vram_size: array of visible vram sizes for all gts */
>> +	uint64_t *visible_vram_size;
>> +
>>   	/** @default_alignment: safe alignment regardless region location */
>>   	uint32_t default_alignment;
>>   
>> @@ -80,7 +83,9 @@ unsigned int xe_number_gt(int fd);
>>   uint64_t all_memory_regions(int fd);
>>   uint64_t system_memory(int fd);
>>   uint64_t vram_memory(int fd, int gt);
>> +uint64_t visible_vram_memory(int fd, int gt);
>>   uint64_t vram_if_possible(int fd, int gt);
>> +uint64_t visible_vram_if_possible(int fd, int gt);
>>   struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
>>   struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
>>   struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);
>> @@ -91,6 +96,7 @@ struct drm_xe_query_config *xe_config(int fd);
>>   unsigned int xe_number_hw_engines(int fd);
>>   bool xe_has_vram(int fd);
>>   uint64_t xe_vram_size(int fd, int gt);
>> +uint64_t xe_visible_vram_size(int fd, int gt);
>>   uint32_t xe_get_default_alignment(int fd);
>>   uint32_t xe_va_bits(int fd);
>>   uint16_t xe_dev_id(int fd);
> 

Re: [igt-dev] [PATCH i-g-t v3 2/6] lib/xe: add visible vram helpers

[Souza, Jose]

On Fri, 2023-07-14 at 17:55 +0100, Matthew Auld wrote:
> On 14/07/2023 17:30, Souza, Jose wrote:
> > On Fri, 2023-07-14 at 15:42 +0100, Matthew Auld wrote:
> > > Add helpers for object creation and querying the cpu_visible related bits.
> > > 
> > > v2: Make it backwards compat with older kernels
> > > 
> > > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > ---
> > >   lib/xe/xe_query.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++-
> > >   lib/xe/xe_query.h |  6 ++++
> > >   2 files changed, 91 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> > > index f535ad853..5412fbeb5 100644
> > > --- a/lib/xe/xe_query.c
> > > +++ b/lib/xe/xe_query.c
> > > @@ -140,6 +140,17 @@ static uint64_t gt_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
> > >   	return 0;
> > >   }
> > >   
> > > +static uint64_t gt_visible_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
> > > +				     const struct drm_xe_query_gts *gts, int gt)
> > > +{
> > > +	int region_idx = ffs(native_region_for_gt(gts, gt)) - 1;
> > > +
> > > +	if (XE_IS_CLASS_VRAM(&mem_usage->regions[region_idx]))
> > > +		return mem_usage->regions[region_idx].cpu_visible_size;
> > > +
> > > +	return 0;
> > > +}
> > > +
> > >   static bool __mem_has_vram(struct drm_xe_query_mem_usage *mem_usage)
> > >   {
> > >   	for (int i = 0; i < mem_usage->num_regions; i++)
> > > @@ -246,9 +257,14 @@ struct xe_device *xe_device_get(int fd)
> > >   	xe_dev->hw_engines = xe_query_engines_new(fd, &xe_dev->number_hw_engines);
> > >   	xe_dev->mem_usage = xe_query_mem_usage_new(fd);
> > >   	xe_dev->vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->vram_size));
> > > -	for (int gt = 0; gt < xe_dev->number_gt; gt++)
> > > +	xe_dev->visible_vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->visible_vram_size));
> > > +	for (int gt = 0; gt < xe_dev->number_gt; gt++) {
> > >   		xe_dev->vram_size[gt] = gt_vram_size(xe_dev->mem_usage,
> > >   						     xe_dev->gts, gt);
> > > +		xe_dev->visible_vram_size[gt] =
> > > +			gt_visible_vram_size(xe_dev->mem_usage,
> > > +					     xe_dev->gts, gt);
> > > +	}
> > >   	xe_dev->default_alignment = __mem_default_alignment(xe_dev->mem_usage);
> > >   	xe_dev->has_vram = __mem_has_vram(xe_dev->mem_usage);
> > >   
> > > @@ -383,6 +399,33 @@ uint64_t vram_memory(int fd, int gt)
> > >   	return xe_has_vram(fd) ? native_region_for_gt(xe_dev->gts, gt) : 0;
> > >   }
> > >   
> > > +static uint64_t __xe_visible_vram_size(int fd, int gt)
> > > +{
> > > +	struct xe_device *xe_dev;
> > > +
> > > +	xe_dev = find_in_cache(fd);
> > > +	igt_assert(xe_dev);
> > > +
> > > +	return xe_dev->visible_vram_size[gt];
> > > +}
> > > +
> > > +/**
> > > + * visible_vram_memory:
> > > + * @fd: xe device fd
> > > + * @gt: gt id
> > > + *
> > > + * Returns vram memory bitmask for xe device @fd and @gt id, with
> > > + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
> > > + * possible.
> > > + */
> > > +uint64_t visible_vram_memory(int fd, int gt)
> > > +{
> > > +	if (__xe_visible_vram_size(fd, gt))
> > > +		return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
> > > +	else
> > > +		return vram_memory(fd, gt); /* older kernel */
> > 
> > We don't need to maintain any compability with older Xe kernels for now...
> > 
> > > +}
> > > +
> > >   /**
> > >    * vram_if_possible:
> > >    * @fd: xe device fd
> > > @@ -396,6 +439,28 @@ uint64_t vram_if_possible(int fd, int gt)
> > >   	return vram_memory(fd, gt) ?: system_memory(fd);
> > >   }
> > >   
> > > +/**
> > > + * visible_vram_if_possible:
> > > + * @fd: xe device fd
> > > + * @gt: gt id
> > > + *
> > > + * Returns vram memory bitmask for xe device @fd and @gt id or system memory if
> > > + * there's no vram memory available for @gt. Also attaches the
> > > + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
> > > + * when using vram.
> > > + */
> > > +uint64_t visible_vram_if_possible(int fd, int gt)
> > > +{
> > > +	uint64_t regions = all_memory_regions(fd);
> > > +	uint64_t system_memory = regions & 0x1;
> > > +	uint64_t vram = regions & (0x2 << gt);
> > > +
> > > +	if (__xe_visible_vram_size(fd, gt))
> > > +		return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
> > > +	else
> > > +		return vram ? vram : system_memory; /* older kernel */
> > > +}
> > 
> > so this can be dropped and current callers should use visible_vram_memory().
> 
> Here I just wanted to keep it compatible so I could merge the IGT in any 
> order. Ideally I want to merge the IGT first and let that soak for a 
> couple of hours, and assuming there is no new breakage I can re-send the 
> kernel patches with a hack patch to force small-bar on some CI machine 
> to get pre-merge testing. Once that all passes I can merge the kernel 
> side. The above compatibility stuff can then be removed after.

Okay, so please add this plans to the commit description...maybe leave a TODO to remove it in code as well.

> 
> > 
> > > +
> > >   /**
> > >    * xe_hw_engines:
> > >    * @fd: xe device fd
> > > @@ -536,6 +601,24 @@ uint64_t xe_vram_size(int fd, int gt)
> > >   	return xe_dev->vram_size[gt];
> > >   }
> > >   
> > > +/**
> > > + * xe_visible_vram_size:
> > > + * @fd: xe device fd
> > > + * @gt: gt
> > > + *
> > > + * Returns size of visible vram of xe device @fd.
> > > + */
> > > +uint64_t xe_visible_vram_size(int fd, int gt)
> > > +{
> > > +	uint64_t visible_size;
> > > +
> > > +	visible_size = __xe_visible_vram_size(fd, gt);
> > > +	if (!visible_size) /* older kernel */
> > > +		visible_size = xe_vram_size(fd, gt);
> > > +
> > > +	return visible_size;
> > > +}
> > > +
> > >   /**
> > >    * xe_get_default_alignment:
> > >    * @fd: xe device fd
> > > @@ -552,6 +635,7 @@ xe_dev_FN(xe_get_default_alignment, default_alignment, uint32_t);
> > >    */
> > >   xe_dev_FN(xe_va_bits, va_bits, uint32_t);
> > >   
> > > +
> > >   /**
> > >    * xe_dev_id:
> > >    * @fd: xe device fd
> > > diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> > > index 68ca5a680..1b74c58ab 100644
> > > --- a/lib/xe/xe_query.h
> > > +++ b/lib/xe/xe_query.h
> > > @@ -47,6 +47,9 @@ struct xe_device {
> > >   	/** @vram_size: array of vram sizes for all gts */
> > >   	uint64_t *vram_size;
> > >   
> > > +	/** @visible_vram_size: array of visible vram sizes for all gts */
> > > +	uint64_t *visible_vram_size;
> > > +
> > >   	/** @default_alignment: safe alignment regardless region location */
> > >   	uint32_t default_alignment;
> > >   
> > > @@ -80,7 +83,9 @@ unsigned int xe_number_gt(int fd);
> > >   uint64_t all_memory_regions(int fd);
> > >   uint64_t system_memory(int fd);
> > >   uint64_t vram_memory(int fd, int gt);
> > > +uint64_t visible_vram_memory(int fd, int gt);
> > >   uint64_t vram_if_possible(int fd, int gt);
> > > +uint64_t visible_vram_if_possible(int fd, int gt);
> > >   struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
> > >   struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
> > >   struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);
> > > @@ -91,6 +96,7 @@ struct drm_xe_query_config *xe_config(int fd);
> > >   unsigned int xe_number_hw_engines(int fd);
> > >   bool xe_has_vram(int fd);
> > >   uint64_t xe_vram_size(int fd, int gt);
> > > +uint64_t xe_visible_vram_size(int fd, int gt);
> > >   uint32_t xe_get_default_alignment(int fd);
> > >   uint32_t xe_va_bits(int fd);
> > >   uint16_t xe_dev_id(int fd);
> > 

[igt-dev] [PATCH i-g-t v3 3/6] lib/xe: handle small-bar systems

[Matthew Auld]

The spinner stuff wants to use mmap. The fb related stuff might want to
CPU access the buffer, so just always ask for it. And the batch buffer
stuff is pretty much always going to need to CPU access the buffer.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
 lib/igt_draw.c          | 2 +-
 lib/igt_fb.c            | 2 +-
 lib/intel_batchbuffer.c | 4 ++--
 lib/xe/xe_spin.c        | 6 ++++--
 4 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 1f814bfc8..13b90702c 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -794,7 +794,7 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
 	else
 		tmp.handle = xe_bo_create_flags(fd, 0,
 						ALIGN(tmp.size, xe_get_default_alignment(fd)),
-						vram_if_possible(fd, 0));
+						visible_vram_if_possible(fd, 0));
 
 	tmp.stride = rect->w * pixel_size;
 	tmp.bpp = buf->bpp;
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 1814e8db1..17738d7f1 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -1194,7 +1194,7 @@ static int create_bo_for_fb(struct igt_fb *fb, bool prefer_sysmem)
 			igt_assert(err == 0 || err == -EOPNOTSUPP);
 		} else if (is_xe_device(fd)) {
 			fb->gem_handle = xe_bo_create_flags(fd, 0, fb->size,
-							vram_if_possible(fd, 0));
+							visible_vram_if_possible(fd, 0));
 		} else if (is_vc4_device(fd)) {
 			fb->gem_handle = igt_vc4_create_bo(fd, fb->size);
 
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 0408d62ba..163d39d6b 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -943,7 +943,7 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
 
 		ibb->alignment = xe_get_default_alignment(fd);
 		size = ALIGN(size, ibb->alignment);
-		ibb->handle = xe_bo_create_flags(fd, 0, size, vram_if_possible(fd, 0));
+		ibb->handle = xe_bo_create_flags(fd, 0, size, visible_vram_if_possible(fd, 0));
 
 		/* Limit to 48-bit due to MI_* address limitation */
 		ibb->gtt_size = 1ull << min_t(uint32_t, xe_va_bits(fd), 48);
@@ -1399,7 +1399,7 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
 		ibb->handle = gem_create(ibb->fd, ibb->size);
 	else
 		ibb->handle = xe_bo_create_flags(ibb->fd, 0, ibb->size,
-						 vram_if_possible(ibb->fd, 0));
+						 visible_vram_if_possible(ibb->fd, 0));
 
 	/* Reacquire offset for RELOC and SIMPLE */
 	if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE ||
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 529b76844..e799fcfc5 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -126,7 +126,8 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt)
 			spin->engine = xe_engine_create_class(fd, spin->vm, DRM_XE_ENGINE_CLASS_COPY);
 	}
 
-	spin->handle = xe_bo_create(fd, 0, spin->vm, bo_size);
+	spin->handle = xe_bo_create_flags(fd, spin->vm, bo_size,
+					  visible_vram_if_possible(fd, 0));
 	xe_spin = xe_bo_map(fd, spin->handle, bo_size);
 	addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
 	xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
@@ -201,7 +202,8 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
 
 	vm = xe_vm_create(fd, 0, 0);
 
-	bo = xe_bo_create(fd, hwe->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, hwe->gt_id));
 	spin = xe_bo_map(fd, bo, 0x1000);
 
 	xe_vm_bind_sync(fd, vm, bo, 0, addr, bo_size);
-- 
2.41.0

[igt-dev] [PATCH i-g-t v3 4/6] tests/xe: handle small-bar systems

[Matthew Auld]

Convert all the existing tests that require CPU access.

v2:
  - Split out the lib changes
  - Prefer SZ_256M and SZ_1G in xe_evict
  - Simplify and fix the bo_flags handling in test_exec
v3:
  - Small fix in xe_evict conversion (missing system_memory(fd))

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 tests/xe/xe_dma_buf_sync.c      |  3 ++-
 tests/xe/xe_evict.c             | 34 +++++++++++++++++++++------------
 tests/xe/xe_exec_balancer.c     |  6 +++---
 tests/xe/xe_exec_basic.c        | 17 ++++++++---------
 tests/xe/xe_exec_compute_mode.c |  4 ++--
 tests/xe/xe_exec_fault_mode.c   | 12 ++++++++----
 tests/xe/xe_exec_reset.c        | 13 ++++++++-----
 tests/xe/xe_exec_store.c        |  6 ++++--
 tests/xe/xe_exec_threads.c      |  9 ++++++---
 tests/xe/xe_guc_pc.c            |  3 ++-
 tests/xe/xe_mmap.c              |  4 ++--
 tests/xe/xe_pm.c                |  3 ++-
 tests/xe/xe_prime_self_import.c |  8 ++++----
 tests/xe/xe_vm.c                | 23 +++++++++++++++-------
 14 files changed, 89 insertions(+), 56 deletions(-)

diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c
index c08f8ac18..4e76d85ab 100644
--- a/tests/xe/xe_dma_buf_sync.c
+++ b/tests/xe/xe_dma_buf_sync.c
@@ -120,7 +120,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd[0]),
 			xe_get_default_alignment(fd[0]));
 	for (i = 0; i < n_bo; ++i) {
-		bo[i] = xe_bo_create(fd[0], hwe0->gt_id, 0, bo_size);
+		bo[i] = xe_bo_create_flags(fd[0], 0, bo_size,
+					   visible_vram_if_possible(fd[0], hwe0->gt_id));
 		dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
 		import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
 
diff --git a/tests/xe/xe_evict.c b/tests/xe/xe_evict.c
index 1a70f1b45..c44cb80dc 100644
--- a/tests/xe/xe_evict.c
+++ b/tests/xe/xe_evict.c
@@ -97,15 +97,17 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
                                 i < n_execs / 8 ? 0 : vm;
 
 			if (flags & MULTI_VM) {
-				__bo = bo[i] = xe_bo_create(fd, eci->gt_id, 0,
-							    bo_size);
+				__bo = bo[i] = xe_bo_create_flags(fd, 0,
+								  bo_size,
+								  visible_vram_memory(fd, eci->gt_id));
 			} else if (flags & THREADED) {
-				__bo = bo[i] = xe_bo_create(fd, eci->gt_id, vm,
-							    bo_size);
+				__bo = bo[i] = xe_bo_create_flags(fd, vm,
+								  bo_size,
+								  visible_vram_memory(fd, eci->gt_id));
 			} else {
 				__bo = bo[i] = xe_bo_create_flags(fd, _vm,
 								  bo_size,
-								  vram_memory(fd, eci->gt_id) |
+								  visible_vram_memory(fd, eci->gt_id) |
 								  system_memory(fd));
 			}
 		} else {
@@ -278,15 +280,17 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
                                 i < n_execs / 8 ? 0 : vm;
 
 			if (flags & MULTI_VM) {
-				__bo = bo[i] = xe_bo_create(fd, eci->gt_id,
-							    0, bo_size);
+				__bo = bo[i] = xe_bo_create_flags(fd, 0,
+								  bo_size,
+								  visible_vram_memory(fd, eci->gt_id));
 			} else if (flags & THREADED) {
-				__bo = bo[i] = xe_bo_create(fd, eci->gt_id,
-							    vm, bo_size);
+				__bo = bo[i] = xe_bo_create_flags(fd, vm,
+								  bo_size,
+								  visible_vram_memory(fd, eci->gt_id));
 			} else {
 				__bo = bo[i] = xe_bo_create_flags(fd, _vm,
 								  bo_size,
-								  vram_memory(fd, eci->gt_id) |
+								  visible_vram_memory(fd, eci->gt_id) |
 								  system_memory(fd));
 			}
 		} else {
@@ -449,9 +453,15 @@ threads(int fd, struct drm_xe_engine_class_instance *eci,
 		pthread_join(threads_data[i].thread, NULL);
 }
 
+#define SZ_256M 0x10000000
+#define SZ_1G   0x40000000
+
 static uint64_t calc_bo_size(uint64_t vram_size, int mul, int div)
 {
-	return (ALIGN(vram_size, 0x40000000)  * mul) / div;
+	if (vram_size >= SZ_1G)
+		return (ALIGN(vram_size, SZ_1G)  * mul) / div;
+	else
+		return (ALIGN(vram_size, SZ_256M)  * mul) / div; /* small-bar */
 }
 
 /**
@@ -664,7 +674,7 @@ igt_main
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_XE);
 		igt_require(xe_has_vram(fd));
-		vram_size = xe_vram_size(fd, 0);
+		vram_size = xe_visible_vram_size(fd, 0);
 		igt_assert(vram_size);
 
 		xe_for_each_hw_engine(fd, hwe)
diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c
index 8df6ceba8..0b00d93de 100644
--- a/tests/xe/xe_exec_balancer.c
+++ b/tests/xe/xe_exec_balancer.c
@@ -69,7 +69,7 @@ static void test_all_active(int fd, int gt, int class)
 	bo_size = sizeof(*data) * num_placements;
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, gt, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	for (i = 0; i < num_placements; i++) {
@@ -225,7 +225,7 @@ test_exec(int fd, int gt, int class, int n_engines, int n_execs,
 		}
 		memset(data, 0, bo_size);
 	} else {
-		bo = xe_bo_create(fd, gt, vm, bo_size);
+		bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 
@@ -447,7 +447,7 @@ test_cm(int fd, int gt, int class, int n_engines, int n_execs,
 			igt_assert(data);
 		}
 	} else {
-		bo = xe_bo_create(fd, gt, vm, bo_size);
+		bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);
diff --git a/tests/xe/xe_exec_basic.c b/tests/xe/xe_exec_basic.c
index af581c327..a4bae93f0 100644
--- a/tests/xe/xe_exec_basic.c
+++ b/tests/xe/xe_exec_basic.c
@@ -126,15 +126,14 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
 		}
 		memset(data, 0, bo_size);
 	} else {
-		if (flags & DEFER_ALLOC) {
-			bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
-						bo_size,
-						vram_if_possible(fd, eci->gt_id) |
-						XE_GEM_CREATE_FLAG_DEFER_BACKING);
-		} else {
-			bo = xe_bo_create(fd, eci->gt_id, n_vm == 1 ? vm[0] : 0,
-					  bo_size);
-		}
+		uint32_t bo_flags;
+
+		bo_flags = visible_vram_if_possible(fd, eci->gt_id);
+		if (flags & DEFER_ALLOC)
+			bo_flags |= XE_GEM_CREATE_FLAG_DEFER_BACKING;
+
+		bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
+					bo_size, bo_flags);
 		if (!(flags & DEFER_BIND))
 			data = xe_bo_map(fd, bo, bo_size);
 	}
diff --git a/tests/xe/xe_exec_compute_mode.c b/tests/xe/xe_exec_compute_mode.c
index 27b538414..ee9756c21 100644
--- a/tests/xe/xe_exec_compute_mode.c
+++ b/tests/xe/xe_exec_compute_mode.c
@@ -150,8 +150,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
 			igt_assert(data);
 		}
 	} else {
-		bo = xe_bo_create(fd, eci->gt_id, flags & VM_FOR_BO ? vm : 0,
-				  bo_size);
+		bo = xe_bo_create_flags(fd, flags & VM_FOR_BO ? vm : 0,
+					bo_size, visible_vram_if_possible(fd, eci->gt_id));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);
diff --git a/tests/xe/xe_exec_fault_mode.c b/tests/xe/xe_exec_fault_mode.c
index bf7230c5a..7dcbb3c45 100644
--- a/tests/xe/xe_exec_fault_mode.c
+++ b/tests/xe/xe_exec_fault_mode.c
@@ -153,9 +153,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
 	} else {
 		if (flags & PREFETCH)
 			bo = xe_bo_create_flags(fd, 0, bo_size,
-						all_memory_regions(fd));
+						all_memory_regions(fd) |
+						visible_vram_if_possible(fd, 0));
 		else
-			bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
+			bo = xe_bo_create_flags(fd, 0, bo_size,
+						visible_vram_if_possible(fd, eci->gt_id));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);
@@ -382,8 +384,10 @@ test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
 	addr_wait = addr + bo_size;
 
 	bo = xe_bo_create_flags(fd, vm, bo_size,
-				all_memory_regions(fd));
-	bo_wait = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+				all_memory_regions(fd) |
+				visible_vram_if_possible(fd, 0));
+	bo_wait = xe_bo_create_flags(fd, vm, bo_size,
+				     visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 	wait = xe_bo_map(fd, bo_wait, bo_size);
 	ptr = &data[0].data;
diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c
index 6ca1cd769..dfbaa6035 100644
--- a/tests/xe/xe_exec_reset.c
+++ b/tests/xe/xe_exec_reset.c
@@ -50,7 +50,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	spin = xe_bo_map(fd, bo, bo_size);
 
 	engine = xe_engine_create(fd, vm, eci, 0);
@@ -187,7 +188,7 @@ test_balancer(int fd, int gt, int class, int n_engines, int n_execs,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, gt, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	for (i = 0; i < n_engines; i++) {
@@ -379,7 +380,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	for (i = 0; i < n_engines; i++) {
@@ -550,7 +552,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 	memset(data, 0, bo_size);
 
@@ -682,7 +685,7 @@ static void submit_jobs(struct gt_thread_data *t)
 	uint32_t bo;
 	uint32_t *data;
 
-	bo = xe_bo_create(fd, 0, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
 	data = xe_bo_map(fd, bo, bo_size);
 	data[0] = MI_BATCH_BUFFER_END;
 
diff --git a/tests/xe/xe_exec_store.c b/tests/xe/xe_exec_store.c
index 9640b1567..ab1bde36e 100644
--- a/tests/xe/xe_exec_store.c
+++ b/tests/xe/xe_exec_store.c
@@ -82,7 +82,8 @@ static void store(int fd)
 			xe_get_default_alignment(fd));
 
 	hw_engine = xe_hw_engine(fd, 1);
-	bo = xe_bo_create(fd, hw_engine->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, hw_engine->gt_id));
 
 	xe_vm_bind_async(fd, vm, hw_engine->gt_id, bo, 0, addr, bo_size, &sync, 1);
 	data = xe_bo_map(fd, bo, bo_size);
@@ -138,7 +139,8 @@ static void store_all(int fd, int gt, int class)
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, 0, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, 0));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	xe_for_each_hw_engine(fd, hwe) {
diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c
index 414d8ee9a..396398984 100644
--- a/tests/xe/xe_exec_threads.c
+++ b/tests/xe/xe_exec_threads.c
@@ -106,7 +106,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
 			igt_assert(data);
 		}
 	} else {
-		bo = xe_bo_create(fd, gt, vm, bo_size);
+		bo = xe_bo_create_flags(fd, vm, bo_size,
+					visible_vram_if_possible(fd, gt));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);
@@ -306,7 +307,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
 			igt_assert(data);
 		}
 	} else {
-		bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
+		bo = xe_bo_create_flags(fd, 0, bo_size,
+					visible_vram_if_possible(fd, eci->gt_id));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);
@@ -516,7 +518,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
 			igt_assert(data);
 		}
 	} else {
-		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+		bo = xe_bo_create_flags(fd, vm, bo_size,
+					visible_vram_if_possible(fd, eci->gt_id));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);
diff --git a/tests/xe/xe_guc_pc.c b/tests/xe/xe_guc_pc.c
index c34df8d60..6339b3893 100644
--- a/tests/xe/xe_guc_pc.c
+++ b/tests/xe/xe_guc_pc.c
@@ -64,7 +64,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	for (i = 0; i < n_engines; i++) {
diff --git a/tests/xe/xe_mmap.c b/tests/xe/xe_mmap.c
index 798facca9..583f39d7a 100644
--- a/tests/xe/xe_mmap.c
+++ b/tests/xe/xe_mmap.c
@@ -118,10 +118,10 @@ igt_main
 		test_mmap(fd, system_memory(fd));
 
 	igt_subtest("vram")
-		test_mmap(fd, vram_memory(fd, 0));
+		test_mmap(fd, visible_vram_memory(fd, 0));
 
 	igt_subtest("vram-system")
-		test_mmap(fd, vram_memory(fd, 0) | system_memory(fd));
+		test_mmap(fd, visible_vram_memory(fd, 0) | system_memory(fd));
 
 	igt_subtest("bad-flags")
 		test_bad_flags(fd);
diff --git a/tests/xe/xe_pm.c b/tests/xe/xe_pm.c
index a7f73c4e6..559eccdeb 100644
--- a/tests/xe/xe_pm.c
+++ b/tests/xe/xe_pm.c
@@ -254,7 +254,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
 	if (check_rpm && runtime_usage_available(device.pci_xe))
 		rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
 
-	bo = xe_bo_create(device.fd_xe, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(device.fd_xe, vm, bo_size,
+				visible_vram_if_possible(device.fd_xe, eci->gt_id));
 	data = xe_bo_map(device.fd_xe, bo, bo_size);
 
 	for (i = 0; i < n_engines; i++) {
diff --git a/tests/xe/xe_prime_self_import.c b/tests/xe/xe_prime_self_import.c
index 0fd79f704..e712e2a9c 100644
--- a/tests/xe/xe_prime_self_import.c
+++ b/tests/xe/xe_prime_self_import.c
@@ -107,7 +107,7 @@ static void test_with_fd_dup(void)
 	fd1 = drm_open_driver(DRIVER_XE);
 	fd2 = drm_open_driver(DRIVER_XE);
 
-	handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
+	handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
 
 	dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
 	gem_close(fd1, handle);
@@ -141,8 +141,8 @@ static void test_with_two_bos(void)
 	fd1 = drm_open_driver(DRIVER_XE);
 	fd2 = drm_open_driver(DRIVER_XE);
 
-	handle1 = xe_bo_create(fd1, 0, 0, BO_SIZE);
-	handle2 = xe_bo_create(fd1, 0, 0, BO_SIZE);
+	handle1 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
+	handle2 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
 
 	dma_buf_fd = prime_handle_to_fd(fd1, handle1);
 	handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
@@ -211,7 +211,7 @@ static void test_with_one_bo(void)
 	fd1 = drm_open_driver(DRIVER_XE);
 	fd2 = drm_open_driver(DRIVER_XE);
 
-	handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
+	handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
 
 	dma_buf_fd = prime_handle_to_fd(fd1, handle);
 	handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
index 04d6c3956..982c50f6d 100644
--- a/tests/xe/xe_vm.c
+++ b/tests/xe/xe_vm.c
@@ -52,7 +52,8 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
 	batch_size = (n_dwords * 4 + 1) * sizeof(uint32_t);
 	batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
 			   xe_get_default_alignment(fd));
-	batch_bo = xe_bo_create(fd, 0, vm, batch_size);
+	batch_bo = xe_bo_create_flags(fd, vm, batch_size,
+				      visible_vram_if_possible(fd, 0));
 	batch_map = xe_bo_map(fd, batch_bo, batch_size);
 
 	for (i = 0; i < n_dwords; i++) {
@@ -116,7 +117,7 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
 		vms = malloc(sizeof(*vms) * n_addrs);
 		igt_assert(vms);
 	}
-	bo = xe_bo_create(fd, 0, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
 	map = xe_bo_map(fd, bo, bo_size);
 	memset(map, 0, bo_size);
 
@@ -554,7 +555,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
 			xe_get_default_alignment(fd));
 
 	for (i = 0; i < n_bo; ++i) {
-		bo[i] = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+		bo[i] = xe_bo_create_flags(fd, vm, bo_size,
+					   visible_vram_if_possible(fd, eci->gt_id));
 		data[i] = xe_bo_map(fd, bo[i], bo_size);
 	}
 
@@ -723,7 +725,8 @@ test_bind_engines_independent(int fd, struct drm_xe_engine_class_instance *eci)
 	bo_size = sizeof(*data) * N_ENGINES;
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	for (i = 0; i < N_ENGINES; i++) {
@@ -880,7 +883,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	if (flags & BIND_ARRAY_BIND_ENGINE_FLAG)
@@ -1072,7 +1076,11 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
 		map = aligned_alloc(xe_get_default_alignment(fd), bo_size);
 		igt_assert(map);
 	} else {
-		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+		igt_skip_on(xe_visible_vram_size(fd, 0) && bo_size >
+			    xe_visible_vram_size(fd, 0));
+
+		bo = xe_bo_create_flags(fd, vm, bo_size,
+					visible_vram_if_possible(fd, eci->gt_id));
 		map = xe_bo_map(fd, bo, bo_size);
 	}
 
@@ -1350,7 +1358,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
 			    MAP_ANONYMOUS, -1, 0);
 		igt_assert(map != MAP_FAILED);
 	} else {
-		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+		bo = xe_bo_create_flags(fd, vm, bo_size,
+					visible_vram_if_possible(fd, eci->gt_id));
 		map = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(map, 0, bo_size);
-- 
2.41.0

Re: [igt-dev] [PATCH i-g-t v3 4/6] tests/xe: handle small-bar systems

[Souza, Jose]

On Fri, 2023-07-14 at 15:42 +0100, Matthew Auld wrote:
> Convert all the existing tests that require CPU access.
> 

Missing conversion in test_bad_flags(), test_bad_extensions(), test_bad_object(), test_with_one_bo_two_files(), test_reimport_close_race(),
thread_fn_export_vs_close(), test_llseek_size(), test_llseek_bad().

The mmaps tests are expected to fail but not because region is not cpu mmaped.
For the prime_self_import test it is also good to require visible vram even if the test don't do any operation with CPU, in real world applications
you need to give applications the flexibility to access it in CPU as well. 


> v2:
>   - Split out the lib changes
>   - Prefer SZ_256M and SZ_1G in xe_evict
>   - Simplify and fix the bo_flags handling in test_exec
> v3:
>   - Small fix in xe_evict conversion (missing system_memory(fd))
> 
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  tests/xe/xe_dma_buf_sync.c      |  3 ++-
>  tests/xe/xe_evict.c             | 34 +++++++++++++++++++++------------
>  tests/xe/xe_exec_balancer.c     |  6 +++---
>  tests/xe/xe_exec_basic.c        | 17 ++++++++---------
>  tests/xe/xe_exec_compute_mode.c |  4 ++--
>  tests/xe/xe_exec_fault_mode.c   | 12 ++++++++----
>  tests/xe/xe_exec_reset.c        | 13 ++++++++-----
>  tests/xe/xe_exec_store.c        |  6 ++++--
>  tests/xe/xe_exec_threads.c      |  9 ++++++---
>  tests/xe/xe_guc_pc.c            |  3 ++-
>  tests/xe/xe_mmap.c              |  4 ++--
>  tests/xe/xe_pm.c                |  3 ++-
>  tests/xe/xe_prime_self_import.c |  8 ++++----
>  tests/xe/xe_vm.c                | 23 +++++++++++++++-------
>  14 files changed, 89 insertions(+), 56 deletions(-)
> 
> diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c
> index c08f8ac18..4e76d85ab 100644
> --- a/tests/xe/xe_dma_buf_sync.c
> +++ b/tests/xe/xe_dma_buf_sync.c
> @@ -120,7 +120,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
>  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd[0]),
>  			xe_get_default_alignment(fd[0]));
>  	for (i = 0; i < n_bo; ++i) {
> -		bo[i] = xe_bo_create(fd[0], hwe0->gt_id, 0, bo_size);
> +		bo[i] = xe_bo_create_flags(fd[0], 0, bo_size,
> +					   visible_vram_if_possible(fd[0], hwe0->gt_id));
>  		dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
>  		import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
>  
> diff --git a/tests/xe/xe_evict.c b/tests/xe/xe_evict.c
> index 1a70f1b45..c44cb80dc 100644
> --- a/tests/xe/xe_evict.c
> +++ b/tests/xe/xe_evict.c
> @@ -97,15 +97,17 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
>                                  i < n_execs / 8 ? 0 : vm;
>  
>  			if (flags & MULTI_VM) {
> -				__bo = bo[i] = xe_bo_create(fd, eci->gt_id, 0,
> -							    bo_size);
> +				__bo = bo[i] = xe_bo_create_flags(fd, 0,
> +								  bo_size,
> +								  visible_vram_memory(fd, eci->gt_id));
>  			} else if (flags & THREADED) {
> -				__bo = bo[i] = xe_bo_create(fd, eci->gt_id, vm,
> -							    bo_size);
> +				__bo = bo[i] = xe_bo_create_flags(fd, vm,
> +								  bo_size,
> +								  visible_vram_memory(fd, eci->gt_id));
>  			} else {
>  				__bo = bo[i] = xe_bo_create_flags(fd, _vm,
>  								  bo_size,
> -								  vram_memory(fd, eci->gt_id) |
> +								  visible_vram_memory(fd, eci->gt_id) |
>  								  system_memory(fd));
>  			}
>  		} else {
> @@ -278,15 +280,17 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
>                                  i < n_execs / 8 ? 0 : vm;
>  
>  			if (flags & MULTI_VM) {
> -				__bo = bo[i] = xe_bo_create(fd, eci->gt_id,
> -							    0, bo_size);
> +				__bo = bo[i] = xe_bo_create_flags(fd, 0,
> +								  bo_size,
> +								  visible_vram_memory(fd, eci->gt_id));
>  			} else if (flags & THREADED) {
> -				__bo = bo[i] = xe_bo_create(fd, eci->gt_id,
> -							    vm, bo_size);
> +				__bo = bo[i] = xe_bo_create_flags(fd, vm,
> +								  bo_size,
> +								  visible_vram_memory(fd, eci->gt_id));
>  			} else {
>  				__bo = bo[i] = xe_bo_create_flags(fd, _vm,
>  								  bo_size,
> -								  vram_memory(fd, eci->gt_id) |
> +								  visible_vram_memory(fd, eci->gt_id) |
>  								  system_memory(fd));
>  			}
>  		} else {
> @@ -449,9 +453,15 @@ threads(int fd, struct drm_xe_engine_class_instance *eci,
>  		pthread_join(threads_data[i].thread, NULL);
>  }
>  
> +#define SZ_256M 0x10000000
> +#define SZ_1G   0x40000000
> +
>  static uint64_t calc_bo_size(uint64_t vram_size, int mul, int div)
>  {
> -	return (ALIGN(vram_size, 0x40000000)  * mul) / div;
> +	if (vram_size >= SZ_1G)
> +		return (ALIGN(vram_size, SZ_1G)  * mul) / div;
> +	else
> +		return (ALIGN(vram_size, SZ_256M)  * mul) / div; /* small-bar */
>  }
>  
>  /**
> @@ -664,7 +674,7 @@ igt_main
>  	igt_fixture {
>  		fd = drm_open_driver(DRIVER_XE);
>  		igt_require(xe_has_vram(fd));
> -		vram_size = xe_vram_size(fd, 0);
> +		vram_size = xe_visible_vram_size(fd, 0);
>  		igt_assert(vram_size);
>  
>  		xe_for_each_hw_engine(fd, hwe)
> diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c
> index 8df6ceba8..0b00d93de 100644
> --- a/tests/xe/xe_exec_balancer.c
> +++ b/tests/xe/xe_exec_balancer.c
> @@ -69,7 +69,7 @@ static void test_all_active(int fd, int gt, int class)
>  	bo_size = sizeof(*data) * num_placements;
>  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
>  
> -	bo = xe_bo_create(fd, gt, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
>  	data = xe_bo_map(fd, bo, bo_size);
>  
>  	for (i = 0; i < num_placements; i++) {
> @@ -225,7 +225,7 @@ test_exec(int fd, int gt, int class, int n_engines, int n_execs,
>  		}
>  		memset(data, 0, bo_size);
>  	} else {
> -		bo = xe_bo_create(fd, gt, vm, bo_size);
> +		bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
>  		data = xe_bo_map(fd, bo, bo_size);
>  	}
>  
> @@ -447,7 +447,7 @@ test_cm(int fd, int gt, int class, int n_engines, int n_execs,
>  			igt_assert(data);
>  		}
>  	} else {
> -		bo = xe_bo_create(fd, gt, vm, bo_size);
> +		bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
>  		data = xe_bo_map(fd, bo, bo_size);
>  	}
>  	memset(data, 0, bo_size);
> diff --git a/tests/xe/xe_exec_basic.c b/tests/xe/xe_exec_basic.c
> index af581c327..a4bae93f0 100644
> --- a/tests/xe/xe_exec_basic.c
> +++ b/tests/xe/xe_exec_basic.c
> @@ -126,15 +126,14 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
>  		}
>  		memset(data, 0, bo_size);
>  	} else {
> -		if (flags & DEFER_ALLOC) {
> -			bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
> -						bo_size,
> -						vram_if_possible(fd, eci->gt_id) |
> -						XE_GEM_CREATE_FLAG_DEFER_BACKING);
> -		} else {
> -			bo = xe_bo_create(fd, eci->gt_id, n_vm == 1 ? vm[0] : 0,
> -					  bo_size);
> -		}
> +		uint32_t bo_flags;
> +
> +		bo_flags = visible_vram_if_possible(fd, eci->gt_id);
> +		if (flags & DEFER_ALLOC)
> +			bo_flags |= XE_GEM_CREATE_FLAG_DEFER_BACKING;
> +
> +		bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
> +					bo_size, bo_flags);
>  		if (!(flags & DEFER_BIND))
>  			data = xe_bo_map(fd, bo, bo_size);
>  	}
> diff --git a/tests/xe/xe_exec_compute_mode.c b/tests/xe/xe_exec_compute_mode.c
> index 27b538414..ee9756c21 100644
> --- a/tests/xe/xe_exec_compute_mode.c
> +++ b/tests/xe/xe_exec_compute_mode.c
> @@ -150,8 +150,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
>  			igt_assert(data);
>  		}
>  	} else {
> -		bo = xe_bo_create(fd, eci->gt_id, flags & VM_FOR_BO ? vm : 0,
> -				  bo_size);
> +		bo = xe_bo_create_flags(fd, flags & VM_FOR_BO ? vm : 0,
> +					bo_size, visible_vram_if_possible(fd, eci->gt_id));
>  		data = xe_bo_map(fd, bo, bo_size);
>  	}
>  	memset(data, 0, bo_size);
> diff --git a/tests/xe/xe_exec_fault_mode.c b/tests/xe/xe_exec_fault_mode.c
> index bf7230c5a..7dcbb3c45 100644
> --- a/tests/xe/xe_exec_fault_mode.c
> +++ b/tests/xe/xe_exec_fault_mode.c
> @@ -153,9 +153,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
>  	} else {
>  		if (flags & PREFETCH)
>  			bo = xe_bo_create_flags(fd, 0, bo_size,
> -						all_memory_regions(fd));
> +						all_memory_regions(fd) |
> +						visible_vram_if_possible(fd, 0));
>  		else
> -			bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
> +			bo = xe_bo_create_flags(fd, 0, bo_size,
> +						visible_vram_if_possible(fd, eci->gt_id));
>  		data = xe_bo_map(fd, bo, bo_size);
>  	}
>  	memset(data, 0, bo_size);
> @@ -382,8 +384,10 @@ test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
>  	addr_wait = addr + bo_size;
>  
>  	bo = xe_bo_create_flags(fd, vm, bo_size,
> -				all_memory_regions(fd));
> -	bo_wait = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +				all_memory_regions(fd) |
> +				visible_vram_if_possible(fd, 0));
> +	bo_wait = xe_bo_create_flags(fd, vm, bo_size,
> +				     visible_vram_if_possible(fd, eci->gt_id));
>  	data = xe_bo_map(fd, bo, bo_size);
>  	wait = xe_bo_map(fd, bo_wait, bo_size);
>  	ptr = &data[0].data;
> diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c
> index 6ca1cd769..dfbaa6035 100644
> --- a/tests/xe/xe_exec_reset.c
> +++ b/tests/xe/xe_exec_reset.c
> @@ -50,7 +50,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
>  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
>  			xe_get_default_alignment(fd));
>  
> -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				visible_vram_if_possible(fd, eci->gt_id));
>  	spin = xe_bo_map(fd, bo, bo_size);
>  
>  	engine = xe_engine_create(fd, vm, eci, 0);
> @@ -187,7 +188,7 @@ test_balancer(int fd, int gt, int class, int n_engines, int n_execs,
>  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
>  			xe_get_default_alignment(fd));
>  
> -	bo = xe_bo_create(fd, gt, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
>  	data = xe_bo_map(fd, bo, bo_size);
>  
>  	for (i = 0; i < n_engines; i++) {
> @@ -379,7 +380,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
>  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
>  			xe_get_default_alignment(fd));
>  
> -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				visible_vram_if_possible(fd, eci->gt_id));
>  	data = xe_bo_map(fd, bo, bo_size);
>  
>  	for (i = 0; i < n_engines; i++) {
> @@ -550,7 +552,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
>  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
>  			xe_get_default_alignment(fd));
>  
> -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				visible_vram_if_possible(fd, eci->gt_id));
>  	data = xe_bo_map(fd, bo, bo_size);
>  	memset(data, 0, bo_size);
>  
> @@ -682,7 +685,7 @@ static void submit_jobs(struct gt_thread_data *t)
>  	uint32_t bo;
>  	uint32_t *data;
>  
> -	bo = xe_bo_create(fd, 0, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
>  	data = xe_bo_map(fd, bo, bo_size);
>  	data[0] = MI_BATCH_BUFFER_END;
>  
> diff --git a/tests/xe/xe_exec_store.c b/tests/xe/xe_exec_store.c
> index 9640b1567..ab1bde36e 100644
> --- a/tests/xe/xe_exec_store.c
> +++ b/tests/xe/xe_exec_store.c
> @@ -82,7 +82,8 @@ static void store(int fd)
>  			xe_get_default_alignment(fd));
>  
>  	hw_engine = xe_hw_engine(fd, 1);
> -	bo = xe_bo_create(fd, hw_engine->gt_id, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				visible_vram_if_possible(fd, hw_engine->gt_id));
>  
>  	xe_vm_bind_async(fd, vm, hw_engine->gt_id, bo, 0, addr, bo_size, &sync, 1);
>  	data = xe_bo_map(fd, bo, bo_size);
> @@ -138,7 +139,8 @@ static void store_all(int fd, int gt, int class)
>  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
>  			xe_get_default_alignment(fd));
>  
> -	bo = xe_bo_create(fd, 0, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				visible_vram_if_possible(fd, 0));
>  	data = xe_bo_map(fd, bo, bo_size);
>  
>  	xe_for_each_hw_engine(fd, hwe) {
> diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c
> index 414d8ee9a..396398984 100644
> --- a/tests/xe/xe_exec_threads.c
> +++ b/tests/xe/xe_exec_threads.c
> @@ -106,7 +106,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
>  			igt_assert(data);
>  		}
>  	} else {
> -		bo = xe_bo_create(fd, gt, vm, bo_size);
> +		bo = xe_bo_create_flags(fd, vm, bo_size,
> +					visible_vram_if_possible(fd, gt));
>  		data = xe_bo_map(fd, bo, bo_size);
>  	}
>  	memset(data, 0, bo_size);
> @@ -306,7 +307,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
>  			igt_assert(data);
>  		}
>  	} else {
> -		bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
> +		bo = xe_bo_create_flags(fd, 0, bo_size,
> +					visible_vram_if_possible(fd, eci->gt_id));
>  		data = xe_bo_map(fd, bo, bo_size);
>  	}
>  	memset(data, 0, bo_size);
> @@ -516,7 +518,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
>  			igt_assert(data);
>  		}
>  	} else {
> -		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +		bo = xe_bo_create_flags(fd, vm, bo_size,
> +					visible_vram_if_possible(fd, eci->gt_id));
>  		data = xe_bo_map(fd, bo, bo_size);
>  	}
>  	memset(data, 0, bo_size);
> diff --git a/tests/xe/xe_guc_pc.c b/tests/xe/xe_guc_pc.c
> index c34df8d60..6339b3893 100644
> --- a/tests/xe/xe_guc_pc.c
> +++ b/tests/xe/xe_guc_pc.c
> @@ -64,7 +64,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
>  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
>  			xe_get_default_alignment(fd));
>  
> -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				visible_vram_if_possible(fd, eci->gt_id));
>  	data = xe_bo_map(fd, bo, bo_size);
>  
>  	for (i = 0; i < n_engines; i++) {
> diff --git a/tests/xe/xe_mmap.c b/tests/xe/xe_mmap.c
> index 798facca9..583f39d7a 100644
> --- a/tests/xe/xe_mmap.c
> +++ b/tests/xe/xe_mmap.c
> @@ -118,10 +118,10 @@ igt_main
>  		test_mmap(fd, system_memory(fd));
>  
>  	igt_subtest("vram")
> -		test_mmap(fd, vram_memory(fd, 0));
> +		test_mmap(fd, visible_vram_memory(fd, 0));
>  
>  	igt_subtest("vram-system")
> -		test_mmap(fd, vram_memory(fd, 0) | system_memory(fd));
> +		test_mmap(fd, visible_vram_memory(fd, 0) | system_memory(fd));
>  
>  	igt_subtest("bad-flags")
>  		test_bad_flags(fd);
> diff --git a/tests/xe/xe_pm.c b/tests/xe/xe_pm.c
> index a7f73c4e6..559eccdeb 100644
> --- a/tests/xe/xe_pm.c
> +++ b/tests/xe/xe_pm.c
> @@ -254,7 +254,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
>  	if (check_rpm && runtime_usage_available(device.pci_xe))
>  		rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
>  
> -	bo = xe_bo_create(device.fd_xe, eci->gt_id, vm, bo_size);
> +	bo = xe_bo_create_flags(device.fd_xe, vm, bo_size,
> +				visible_vram_if_possible(device.fd_xe, eci->gt_id));
>  	data = xe_bo_map(device.fd_xe, bo, bo_size);
>  
>  	for (i = 0; i < n_engines; i++) {
> diff --git a/tests/xe/xe_prime_self_import.c b/tests/xe/xe_prime_self_import.c
> index 0fd79f704..e712e2a9c 100644
> --- a/tests/xe/xe_prime_self_import.c
> +++ b/tests/xe/xe_prime_self_import.c
> @@ -107,7 +107,7 @@ static void test_with_fd_dup(void)
>  	fd1 = drm_open_driver(DRIVER_XE);
>  	fd2 = drm_open_driver(DRIVER_XE);
>  
> -	handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
> +	handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
>  
>  	dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
>  	gem_close(fd1, handle);
> @@ -141,8 +141,8 @@ static void test_with_two_bos(void)
>  	fd1 = drm_open_driver(DRIVER_XE);
>  	fd2 = drm_open_driver(DRIVER_XE);
>  
> -	handle1 = xe_bo_create(fd1, 0, 0, BO_SIZE);
> -	handle2 = xe_bo_create(fd1, 0, 0, BO_SIZE);
> +	handle1 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> +	handle2 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
>  
>  	dma_buf_fd = prime_handle_to_fd(fd1, handle1);
>  	handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
> @@ -211,7 +211,7 @@ static void test_with_one_bo(void)
>  	fd1 = drm_open_driver(DRIVER_XE);
>  	fd2 = drm_open_driver(DRIVER_XE);
>  
> -	handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
> +	handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
>  
>  	dma_buf_fd = prime_handle_to_fd(fd1, handle);
>  	handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
> diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
> index 04d6c3956..982c50f6d 100644
> --- a/tests/xe/xe_vm.c
> +++ b/tests/xe/xe_vm.c
> @@ -52,7 +52,8 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
>  	batch_size = (n_dwords * 4 + 1) * sizeof(uint32_t);
>  	batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
>  			   xe_get_default_alignment(fd));
> -	batch_bo = xe_bo_create(fd, 0, vm, batch_size);
> +	batch_bo = xe_bo_create_flags(fd, vm, batch_size,
> +				      visible_vram_if_possible(fd, 0));
>  	batch_map = xe_bo_map(fd, batch_bo, batch_size);
>  
>  	for (i = 0; i < n_dwords; i++) {
> @@ -116,7 +117,7 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
>  		vms = malloc(sizeof(*vms) * n_addrs);
>  		igt_assert(vms);
>  	}
> -	bo = xe_bo_create(fd, 0, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
>  	map = xe_bo_map(fd, bo, bo_size);
>  	memset(map, 0, bo_size);
>  
> @@ -554,7 +555,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
>  			xe_get_default_alignment(fd));
>  
>  	for (i = 0; i < n_bo; ++i) {
> -		bo[i] = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +		bo[i] = xe_bo_create_flags(fd, vm, bo_size,
> +					   visible_vram_if_possible(fd, eci->gt_id));
>  		data[i] = xe_bo_map(fd, bo[i], bo_size);
>  	}
>  
> @@ -723,7 +725,8 @@ test_bind_engines_independent(int fd, struct drm_xe_engine_class_instance *eci)
>  	bo_size = sizeof(*data) * N_ENGINES;
>  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
>  			xe_get_default_alignment(fd));
> -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				visible_vram_if_possible(fd, eci->gt_id));
>  	data = xe_bo_map(fd, bo, bo_size);
>  
>  	for (i = 0; i < N_ENGINES; i++) {
> @@ -880,7 +883,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
>  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
>  			xe_get_default_alignment(fd));
>  
> -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				visible_vram_if_possible(fd, eci->gt_id));
>  	data = xe_bo_map(fd, bo, bo_size);
>  
>  	if (flags & BIND_ARRAY_BIND_ENGINE_FLAG)
> @@ -1072,7 +1076,11 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
>  		map = aligned_alloc(xe_get_default_alignment(fd), bo_size);
>  		igt_assert(map);
>  	} else {
> -		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +		igt_skip_on(xe_visible_vram_size(fd, 0) && bo_size >
> +			    xe_visible_vram_size(fd, 0));


redundant 'xe_visible_vram_size(fd, 0)' if it is 0 it will be smaller than bo_size.

Other than this and the missing cases LGTM.

> +
> +		bo = xe_bo_create_flags(fd, vm, bo_size,
> +					visible_vram_if_possible(fd, eci->gt_id));
>  		map = xe_bo_map(fd, bo, bo_size);
>  	}
>  
> @@ -1350,7 +1358,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
>  			    MAP_ANONYMOUS, -1, 0);
>  		igt_assert(map != MAP_FAILED);
>  	} else {
> -		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> +		bo = xe_bo_create_flags(fd, vm, bo_size,
> +					visible_vram_if_possible(fd, eci->gt_id));
>  		map = xe_bo_map(fd, bo, bo_size);
>  	}
>  	memset(map, 0, bo_size);

Re: [igt-dev] [PATCH i-g-t v3 4/6] tests/xe: handle small-bar systems

[Souza, Jose]

On Fri, 2023-07-14 at 10:01 -0700, José Roberto de Souza wrote:
> On Fri, 2023-07-14 at 15:42 +0100, Matthew Auld wrote:
> > Convert all the existing tests that require CPU access.
> > 
> 
> Missing conversion in test_bad_flags(), test_bad_extensions(), test_bad_object(), test_with_one_bo_two_files(), test_reimport_close_race(),
> thread_fn_export_vs_close(), test_llseek_size(), test_llseek_bad().
> 
> The mmaps tests are expected to fail but not because region is not cpu mmaped.
> For the prime_self_import test it is also good to require visible vram even if the test don't do any operation with CPU, in real world applications
> you need to give applications the flexibility to access it in CPU as well. 
> 
> 
> > v2:
> >   - Split out the lib changes
> >   - Prefer SZ_256M and SZ_1G in xe_evict
> >   - Simplify and fix the bo_flags handling in test_exec
> > v3:
> >   - Small fix in xe_evict conversion (missing system_memory(fd))
> > 
> > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  tests/xe/xe_dma_buf_sync.c      |  3 ++-
> >  tests/xe/xe_evict.c             | 34 +++++++++++++++++++++------------
> >  tests/xe/xe_exec_balancer.c     |  6 +++---
> >  tests/xe/xe_exec_basic.c        | 17 ++++++++---------
> >  tests/xe/xe_exec_compute_mode.c |  4 ++--
> >  tests/xe/xe_exec_fault_mode.c   | 12 ++++++++----
> >  tests/xe/xe_exec_reset.c        | 13 ++++++++-----
> >  tests/xe/xe_exec_store.c        |  6 ++++--
> >  tests/xe/xe_exec_threads.c      |  9 ++++++---
> >  tests/xe/xe_guc_pc.c            |  3 ++-
> >  tests/xe/xe_mmap.c              |  4 ++--
> >  tests/xe/xe_pm.c                |  3 ++-
> >  tests/xe/xe_prime_self_import.c |  8 ++++----
> >  tests/xe/xe_vm.c                | 23 +++++++++++++++-------
> >  14 files changed, 89 insertions(+), 56 deletions(-)
> > 
> > diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c
> > index c08f8ac18..4e76d85ab 100644
> > --- a/tests/xe/xe_dma_buf_sync.c
> > +++ b/tests/xe/xe_dma_buf_sync.c
> > @@ -120,7 +120,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
> >  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd[0]),
> >  			xe_get_default_alignment(fd[0]));
> >  	for (i = 0; i < n_bo; ++i) {
> > -		bo[i] = xe_bo_create(fd[0], hwe0->gt_id, 0, bo_size);
> > +		bo[i] = xe_bo_create_flags(fd[0], 0, bo_size,
> > +					   visible_vram_if_possible(fd[0], hwe0->gt_id));
> >  		dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
> >  		import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
> >  
> > diff --git a/tests/xe/xe_evict.c b/tests/xe/xe_evict.c
> > index 1a70f1b45..c44cb80dc 100644
> > --- a/tests/xe/xe_evict.c
> > +++ b/tests/xe/xe_evict.c
> > @@ -97,15 +97,17 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
> >                                  i < n_execs / 8 ? 0 : vm;
> >  
> >  			if (flags & MULTI_VM) {
> > -				__bo = bo[i] = xe_bo_create(fd, eci->gt_id, 0,
> > -							    bo_size);
> > +				__bo = bo[i] = xe_bo_create_flags(fd, 0,
> > +								  bo_size,
> > +								  visible_vram_memory(fd, eci->gt_id));
> >  			} else if (flags & THREADED) {
> > -				__bo = bo[i] = xe_bo_create(fd, eci->gt_id, vm,
> > -							    bo_size);
> > +				__bo = bo[i] = xe_bo_create_flags(fd, vm,
> > +								  bo_size,
> > +								  visible_vram_memory(fd, eci->gt_id));
> >  			} else {
> >  				__bo = bo[i] = xe_bo_create_flags(fd, _vm,
> >  								  bo_size,
> > -								  vram_memory(fd, eci->gt_id) |
> > +								  visible_vram_memory(fd, eci->gt_id) |
> >  								  system_memory(fd));
> >  			}
> >  		} else {
> > @@ -278,15 +280,17 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
> >                                  i < n_execs / 8 ? 0 : vm;
> >  
> >  			if (flags & MULTI_VM) {
> > -				__bo = bo[i] = xe_bo_create(fd, eci->gt_id,
> > -							    0, bo_size);
> > +				__bo = bo[i] = xe_bo_create_flags(fd, 0,
> > +								  bo_size,
> > +								  visible_vram_memory(fd, eci->gt_id));
> >  			} else if (flags & THREADED) {
> > -				__bo = bo[i] = xe_bo_create(fd, eci->gt_id,
> > -							    vm, bo_size);
> > +				__bo = bo[i] = xe_bo_create_flags(fd, vm,
> > +								  bo_size,
> > +								  visible_vram_memory(fd, eci->gt_id));
> >  			} else {
> >  				__bo = bo[i] = xe_bo_create_flags(fd, _vm,
> >  								  bo_size,
> > -								  vram_memory(fd, eci->gt_id) |
> > +								  visible_vram_memory(fd, eci->gt_id) |
> >  								  system_memory(fd));
> >  			}
> >  		} else {
> > @@ -449,9 +453,15 @@ threads(int fd, struct drm_xe_engine_class_instance *eci,
> >  		pthread_join(threads_data[i].thread, NULL);
> >  }
> >  
> > +#define SZ_256M 0x10000000
> > +#define SZ_1G   0x40000000
> > +
> >  static uint64_t calc_bo_size(uint64_t vram_size, int mul, int div)
> >  {
> > -	return (ALIGN(vram_size, 0x40000000)  * mul) / div;
> > +	if (vram_size >= SZ_1G)
> > +		return (ALIGN(vram_size, SZ_1G)  * mul) / div;
> > +	else
> > +		return (ALIGN(vram_size, SZ_256M)  * mul) / div; /* small-bar */
> >  }
> >  
> >  /**
> > @@ -664,7 +674,7 @@ igt_main
> >  	igt_fixture {
> >  		fd = drm_open_driver(DRIVER_XE);
> >  		igt_require(xe_has_vram(fd));
> > -		vram_size = xe_vram_size(fd, 0);
> > +		vram_size = xe_visible_vram_size(fd, 0);
> >  		igt_assert(vram_size);
> >  
> >  		xe_for_each_hw_engine(fd, hwe)
> > diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c
> > index 8df6ceba8..0b00d93de 100644
> > --- a/tests/xe/xe_exec_balancer.c
> > +++ b/tests/xe/xe_exec_balancer.c
> > @@ -69,7 +69,7 @@ static void test_all_active(int fd, int gt, int class)
> >  	bo_size = sizeof(*data) * num_placements;
> >  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
> >  
> > -	bo = xe_bo_create(fd, gt, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> >  	data = xe_bo_map(fd, bo, bo_size);
> >  
> >  	for (i = 0; i < num_placements; i++) {
> > @@ -225,7 +225,7 @@ test_exec(int fd, int gt, int class, int n_engines, int n_execs,
> >  		}
> >  		memset(data, 0, bo_size);
> >  	} else {
> > -		bo = xe_bo_create(fd, gt, vm, bo_size);
> > +		bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> >  		data = xe_bo_map(fd, bo, bo_size);
> >  	}
> >  
> > @@ -447,7 +447,7 @@ test_cm(int fd, int gt, int class, int n_engines, int n_execs,
> >  			igt_assert(data);
> >  		}
> >  	} else {
> > -		bo = xe_bo_create(fd, gt, vm, bo_size);
> > +		bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> >  		data = xe_bo_map(fd, bo, bo_size);
> >  	}
> >  	memset(data, 0, bo_size);
> > diff --git a/tests/xe/xe_exec_basic.c b/tests/xe/xe_exec_basic.c
> > index af581c327..a4bae93f0 100644
> > --- a/tests/xe/xe_exec_basic.c
> > +++ b/tests/xe/xe_exec_basic.c
> > @@ -126,15 +126,14 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> >  		}
> >  		memset(data, 0, bo_size);
> >  	} else {
> > -		if (flags & DEFER_ALLOC) {
> > -			bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
> > -						bo_size,
> > -						vram_if_possible(fd, eci->gt_id) |
> > -						XE_GEM_CREATE_FLAG_DEFER_BACKING);
> > -		} else {
> > -			bo = xe_bo_create(fd, eci->gt_id, n_vm == 1 ? vm[0] : 0,
> > -					  bo_size);
> > -		}
> > +		uint32_t bo_flags;
> > +
> > +		bo_flags = visible_vram_if_possible(fd, eci->gt_id);
> > +		if (flags & DEFER_ALLOC)
> > +			bo_flags |= XE_GEM_CREATE_FLAG_DEFER_BACKING;
> > +
> > +		bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
> > +					bo_size, bo_flags);
> >  		if (!(flags & DEFER_BIND))
> >  			data = xe_bo_map(fd, bo, bo_size);
> >  	}
> > diff --git a/tests/xe/xe_exec_compute_mode.c b/tests/xe/xe_exec_compute_mode.c
> > index 27b538414..ee9756c21 100644
> > --- a/tests/xe/xe_exec_compute_mode.c
> > +++ b/tests/xe/xe_exec_compute_mode.c
> > @@ -150,8 +150,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> >  			igt_assert(data);
> >  		}
> >  	} else {
> > -		bo = xe_bo_create(fd, eci->gt_id, flags & VM_FOR_BO ? vm : 0,
> > -				  bo_size);
> > +		bo = xe_bo_create_flags(fd, flags & VM_FOR_BO ? vm : 0,
> > +					bo_size, visible_vram_if_possible(fd, eci->gt_id));
> >  		data = xe_bo_map(fd, bo, bo_size);
> >  	}
> >  	memset(data, 0, bo_size);
> > diff --git a/tests/xe/xe_exec_fault_mode.c b/tests/xe/xe_exec_fault_mode.c
> > index bf7230c5a..7dcbb3c45 100644
> > --- a/tests/xe/xe_exec_fault_mode.c
> > +++ b/tests/xe/xe_exec_fault_mode.c
> > @@ -153,9 +153,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> >  	} else {
> >  		if (flags & PREFETCH)
> >  			bo = xe_bo_create_flags(fd, 0, bo_size,
> > -						all_memory_regions(fd));
> > +						all_memory_regions(fd) |
> > +						visible_vram_if_possible(fd, 0));
> >  		else
> > -			bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
> > +			bo = xe_bo_create_flags(fd, 0, bo_size,
> > +						visible_vram_if_possible(fd, eci->gt_id));
> >  		data = xe_bo_map(fd, bo, bo_size);
> >  	}
> >  	memset(data, 0, bo_size);
> > @@ -382,8 +384,10 @@ test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
> >  	addr_wait = addr + bo_size;
> >  
> >  	bo = xe_bo_create_flags(fd, vm, bo_size,
> > -				all_memory_regions(fd));
> > -	bo_wait = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +				all_memory_regions(fd) |
> > +				visible_vram_if_possible(fd, 0));
> > +	bo_wait = xe_bo_create_flags(fd, vm, bo_size,
> > +				     visible_vram_if_possible(fd, eci->gt_id));
> >  	data = xe_bo_map(fd, bo, bo_size);
> >  	wait = xe_bo_map(fd, bo_wait, bo_size);
> >  	ptr = &data[0].data;
> > diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c
> > index 6ca1cd769..dfbaa6035 100644
> > --- a/tests/xe/xe_exec_reset.c
> > +++ b/tests/xe/xe_exec_reset.c
> > @@ -50,7 +50,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
> >  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> >  			xe_get_default_alignment(fd));
> >  
> > -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size,
> > +				visible_vram_if_possible(fd, eci->gt_id));
> >  	spin = xe_bo_map(fd, bo, bo_size);
> >  
> >  	engine = xe_engine_create(fd, vm, eci, 0);
> > @@ -187,7 +188,7 @@ test_balancer(int fd, int gt, int class, int n_engines, int n_execs,
> >  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> >  			xe_get_default_alignment(fd));
> >  
> > -	bo = xe_bo_create(fd, gt, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> >  	data = xe_bo_map(fd, bo, bo_size);
> >  
> >  	for (i = 0; i < n_engines; i++) {
> > @@ -379,7 +380,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
> >  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> >  			xe_get_default_alignment(fd));
> >  
> > -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size,
> > +				visible_vram_if_possible(fd, eci->gt_id));
> >  	data = xe_bo_map(fd, bo, bo_size);
> >  
> >  	for (i = 0; i < n_engines; i++) {
> > @@ -550,7 +552,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
> >  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> >  			xe_get_default_alignment(fd));
> >  
> > -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size,
> > +				visible_vram_if_possible(fd, eci->gt_id));
> >  	data = xe_bo_map(fd, bo, bo_size);
> >  	memset(data, 0, bo_size);
> >  
> > @@ -682,7 +685,7 @@ static void submit_jobs(struct gt_thread_data *t)
> >  	uint32_t bo;
> >  	uint32_t *data;
> >  
> > -	bo = xe_bo_create(fd, 0, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> >  	data = xe_bo_map(fd, bo, bo_size);
> >  	data[0] = MI_BATCH_BUFFER_END;
> >  
> > diff --git a/tests/xe/xe_exec_store.c b/tests/xe/xe_exec_store.c
> > index 9640b1567..ab1bde36e 100644
> > --- a/tests/xe/xe_exec_store.c
> > +++ b/tests/xe/xe_exec_store.c
> > @@ -82,7 +82,8 @@ static void store(int fd)
> >  			xe_get_default_alignment(fd));
> >  
> >  	hw_engine = xe_hw_engine(fd, 1);
> > -	bo = xe_bo_create(fd, hw_engine->gt_id, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size,
> > +				visible_vram_if_possible(fd, hw_engine->gt_id));
> >  
> >  	xe_vm_bind_async(fd, vm, hw_engine->gt_id, bo, 0, addr, bo_size, &sync, 1);
> >  	data = xe_bo_map(fd, bo, bo_size);
> > @@ -138,7 +139,8 @@ static void store_all(int fd, int gt, int class)
> >  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> >  			xe_get_default_alignment(fd));
> >  
> > -	bo = xe_bo_create(fd, 0, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size,
> > +				visible_vram_if_possible(fd, 0));
> >  	data = xe_bo_map(fd, bo, bo_size);
> >  
> >  	xe_for_each_hw_engine(fd, hwe) {
> > diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c
> > index 414d8ee9a..396398984 100644
> > --- a/tests/xe/xe_exec_threads.c
> > +++ b/tests/xe/xe_exec_threads.c
> > @@ -106,7 +106,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
> >  			igt_assert(data);
> >  		}
> >  	} else {
> > -		bo = xe_bo_create(fd, gt, vm, bo_size);
> > +		bo = xe_bo_create_flags(fd, vm, bo_size,
> > +					visible_vram_if_possible(fd, gt));
> >  		data = xe_bo_map(fd, bo, bo_size);
> >  	}
> >  	memset(data, 0, bo_size);
> > @@ -306,7 +307,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
> >  			igt_assert(data);
> >  		}
> >  	} else {
> > -		bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
> > +		bo = xe_bo_create_flags(fd, 0, bo_size,
> > +					visible_vram_if_possible(fd, eci->gt_id));
> >  		data = xe_bo_map(fd, bo, bo_size);
> >  	}
> >  	memset(data, 0, bo_size);
> > @@ -516,7 +518,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
> >  			igt_assert(data);
> >  		}
> >  	} else {
> > -		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +		bo = xe_bo_create_flags(fd, vm, bo_size,
> > +					visible_vram_if_possible(fd, eci->gt_id));
> >  		data = xe_bo_map(fd, bo, bo_size);
> >  	}
> >  	memset(data, 0, bo_size);
> > diff --git a/tests/xe/xe_guc_pc.c b/tests/xe/xe_guc_pc.c
> > index c34df8d60..6339b3893 100644
> > --- a/tests/xe/xe_guc_pc.c
> > +++ b/tests/xe/xe_guc_pc.c
> > @@ -64,7 +64,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
> >  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> >  			xe_get_default_alignment(fd));
> >  
> > -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size,
> > +				visible_vram_if_possible(fd, eci->gt_id));
> >  	data = xe_bo_map(fd, bo, bo_size);
> >  
> >  	for (i = 0; i < n_engines; i++) {
> > diff --git a/tests/xe/xe_mmap.c b/tests/xe/xe_mmap.c
> > index 798facca9..583f39d7a 100644
> > --- a/tests/xe/xe_mmap.c
> > +++ b/tests/xe/xe_mmap.c
> > @@ -118,10 +118,10 @@ igt_main
> >  		test_mmap(fd, system_memory(fd));
> >  
> >  	igt_subtest("vram")
> > -		test_mmap(fd, vram_memory(fd, 0));
> > +		test_mmap(fd, visible_vram_memory(fd, 0));
> >  
> >  	igt_subtest("vram-system")
> > -		test_mmap(fd, vram_memory(fd, 0) | system_memory(fd));
> > +		test_mmap(fd, visible_vram_memory(fd, 0) | system_memory(fd));
> >  
> >  	igt_subtest("bad-flags")
> >  		test_bad_flags(fd);
> > diff --git a/tests/xe/xe_pm.c b/tests/xe/xe_pm.c
> > index a7f73c4e6..559eccdeb 100644
> > --- a/tests/xe/xe_pm.c
> > +++ b/tests/xe/xe_pm.c
> > @@ -254,7 +254,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
> >  	if (check_rpm && runtime_usage_available(device.pci_xe))
> >  		rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
> >  
> > -	bo = xe_bo_create(device.fd_xe, eci->gt_id, vm, bo_size);
> > +	bo = xe_bo_create_flags(device.fd_xe, vm, bo_size,
> > +				visible_vram_if_possible(device.fd_xe, eci->gt_id));
> >  	data = xe_bo_map(device.fd_xe, bo, bo_size);
> >  
> >  	for (i = 0; i < n_engines; i++) {
> > diff --git a/tests/xe/xe_prime_self_import.c b/tests/xe/xe_prime_self_import.c
> > index 0fd79f704..e712e2a9c 100644
> > --- a/tests/xe/xe_prime_self_import.c
> > +++ b/tests/xe/xe_prime_self_import.c
> > @@ -107,7 +107,7 @@ static void test_with_fd_dup(void)
> >  	fd1 = drm_open_driver(DRIVER_XE);
> >  	fd2 = drm_open_driver(DRIVER_XE);
> >  
> > -	handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
> > +	handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> >  
> >  	dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
> >  	gem_close(fd1, handle);
> > @@ -141,8 +141,8 @@ static void test_with_two_bos(void)
> >  	fd1 = drm_open_driver(DRIVER_XE);
> >  	fd2 = drm_open_driver(DRIVER_XE);
> >  
> > -	handle1 = xe_bo_create(fd1, 0, 0, BO_SIZE);
> > -	handle2 = xe_bo_create(fd1, 0, 0, BO_SIZE);
> > +	handle1 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> > +	handle2 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> >  
> >  	dma_buf_fd = prime_handle_to_fd(fd1, handle1);
> >  	handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
> > @@ -211,7 +211,7 @@ static void test_with_one_bo(void)
> >  	fd1 = drm_open_driver(DRIVER_XE);
> >  	fd2 = drm_open_driver(DRIVER_XE);
> >  
> > -	handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
> > +	handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> >  
> >  	dma_buf_fd = prime_handle_to_fd(fd1, handle);
> >  	handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
> > diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
> > index 04d6c3956..982c50f6d 100644
> > --- a/tests/xe/xe_vm.c
> > +++ b/tests/xe/xe_vm.c
> > @@ -52,7 +52,8 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
> >  	batch_size = (n_dwords * 4 + 1) * sizeof(uint32_t);
> >  	batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
> >  			   xe_get_default_alignment(fd));
> > -	batch_bo = xe_bo_create(fd, 0, vm, batch_size);
> > +	batch_bo = xe_bo_create_flags(fd, vm, batch_size,
> > +				      visible_vram_if_possible(fd, 0));
> >  	batch_map = xe_bo_map(fd, batch_bo, batch_size);
> >  
> >  	for (i = 0; i < n_dwords; i++) {
> > @@ -116,7 +117,7 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
> >  		vms = malloc(sizeof(*vms) * n_addrs);
> >  		igt_assert(vms);
> >  	}
> > -	bo = xe_bo_create(fd, 0, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> >  	map = xe_bo_map(fd, bo, bo_size);
> >  	memset(map, 0, bo_size);
> >  
> > @@ -554,7 +555,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
> >  			xe_get_default_alignment(fd));
> >  
> >  	for (i = 0; i < n_bo; ++i) {
> > -		bo[i] = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +		bo[i] = xe_bo_create_flags(fd, vm, bo_size,
> > +					   visible_vram_if_possible(fd, eci->gt_id));
> >  		data[i] = xe_bo_map(fd, bo[i], bo_size);
> >  	}
> >  
> > @@ -723,7 +725,8 @@ test_bind_engines_independent(int fd, struct drm_xe_engine_class_instance *eci)
> >  	bo_size = sizeof(*data) * N_ENGINES;
> >  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> >  			xe_get_default_alignment(fd));
> > -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size,
> > +				visible_vram_if_possible(fd, eci->gt_id));
> >  	data = xe_bo_map(fd, bo, bo_size);
> >  
> >  	for (i = 0; i < N_ENGINES; i++) {
> > @@ -880,7 +883,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
> >  	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> >  			xe_get_default_alignment(fd));
> >  
> > -	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +	bo = xe_bo_create_flags(fd, vm, bo_size,
> > +				visible_vram_if_possible(fd, eci->gt_id));
> >  	data = xe_bo_map(fd, bo, bo_size);
> >  
> >  	if (flags & BIND_ARRAY_BIND_ENGINE_FLAG)
> > @@ -1072,7 +1076,11 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
> >  		map = aligned_alloc(xe_get_default_alignment(fd), bo_size);
> >  		igt_assert(map);
> >  	} else {
> > -		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +		igt_skip_on(xe_visible_vram_size(fd, 0) && bo_size >
> > +			    xe_visible_vram_size(fd, 0));
> 
> 
> redundant 'xe_visible_vram_size(fd, 0)' if it is 0 it will be smaller than bo_size.

miss read this, please ignore the comment above.

> 
> Other than this and the missing cases LGTM.
> 
> > +
> > +		bo = xe_bo_create_flags(fd, vm, bo_size,
> > +					visible_vram_if_possible(fd, eci->gt_id));
> >  		map = xe_bo_map(fd, bo, bo_size);
> >  	}
> >  
> > @@ -1350,7 +1358,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
> >  			    MAP_ANONYMOUS, -1, 0);
> >  		igt_assert(map != MAP_FAILED);
> >  	} else {
> > -		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> > +		bo = xe_bo_create_flags(fd, vm, bo_size,
> > +					visible_vram_if_possible(fd, eci->gt_id));
> >  		map = xe_bo_map(fd, bo, bo_size);
> >  	}
> >  	memset(map, 0, bo_size);
> 

[igt-dev] [PATCH i-g-t v3 5/6] tests/xe/query: extend for CPU visible accounting

[Matthew Auld]

Print the visible size and how much is used. Also sanity check the
values.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 tests/xe/xe_query.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/tests/xe/xe_query.c b/tests/xe/xe_query.c
index beee12ef9..47aa98a8f 100644
--- a/tests/xe/xe_query.c
+++ b/tests/xe/xe_query.c
@@ -230,6 +230,23 @@ test_query_mem_usage(int fd)
 		igt_info("min_page_size=0x%x, max_page_size=0x%x\n",
 		       mem_usage->regions[i].min_page_size,
 		       mem_usage->regions[i].max_page_size);
+
+		igt_info("visible size=%lluMiB\n",
+			 mem_usage->regions[i].cpu_visible_size >> 20);
+		igt_info("visible used=%lluMiB\n",
+			 mem_usage->regions[i].cpu_visible_used >> 20);
+
+		igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_size,
+				   mem_usage->regions[i].total_size);
+		igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_used,
+				   mem_usage->regions[i].cpu_visible_size);
+		igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_used,
+				   mem_usage->regions[i].used);
+		igt_assert_lte_u64(mem_usage->regions[i].used,
+				   mem_usage->regions[i].total_size);
+		igt_assert_lte_u64(mem_usage->regions[i].used -
+				   mem_usage->regions[i].cpu_visible_used,
+				   mem_usage->regions[i].total_size);
 	}
 	dump_hex_debug(mem_usage, query.size);
 	free(mem_usage);
-- 
2.41.0

[igt-dev] [PATCH i-g-t v3 6/6] tests/xe/mmap: sanity check small-bar

[Matthew Auld]

Some basic sanity checks.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
 lib/xe/xe_ioctl.c  | 28 ++++++++++----
 lib/xe/xe_ioctl.h  |  2 +
 tests/xe/xe_mmap.c | 92 +++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 114 insertions(+), 8 deletions(-)

diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 0b5c7a4fc..f9f722335 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -233,17 +233,31 @@ void xe_vm_destroy(int fd, uint32_t vm)
 	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_DESTROY, &destroy), 0);
 }
 
+uint32_t __xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags,
+			      uint32_t *handle)
+{
+	struct drm_xe_gem_create create = {
+		.vm_id = vm,
+		.size = size,
+		.flags = flags,
+	};
+	int err;
+
+	err = igt_ioctl(fd, DRM_IOCTL_XE_GEM_CREATE, &create);
+	if (err)
+		return err;
+
+	*handle = create.handle;
+	return 0;
+}
+
 uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags)
 {
-	struct drm_xe_gem_create create = {
-		.vm_id = vm,
-		.size = size,
-		.flags = flags,
-	};
+	uint32_t handle;
 
-	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_GEM_CREATE, &create), 0);
+	igt_assert_eq(__xe_bo_create_flags(fd, vm, size, flags, &handle), 0);
 
-	return create.handle;
+	return handle;
 }
 
 uint32_t xe_bo_create(int fd, int gt, uint32_t vm, uint64_t size)
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index 320e0f9f6..f9c3acb4a 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -64,6 +64,8 @@ void xe_vm_unbind_all_async(int fd, uint32_t vm, uint32_t engine,
 			    uint32_t bo, struct drm_xe_sync *sync,
 			    uint32_t num_syncs);
 void xe_vm_destroy(int fd, uint32_t vm);
+uint32_t __xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags,
+			      uint32_t *handle);
 uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags);
 uint32_t xe_bo_create(int fd, int gt, uint32_t vm, uint64_t size);
 uint32_t xe_engine_create(int fd, uint32_t vm,
diff --git a/tests/xe/xe_mmap.c b/tests/xe/xe_mmap.c
index 583f39d7a..cd2076336 100644
--- a/tests/xe/xe_mmap.c
+++ b/tests/xe/xe_mmap.c
@@ -18,14 +18,21 @@
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 
+#include <setjmp.h>
+#include <signal.h>
 #include <string.h>
 
-
 /**
  * SUBTEST: system
  * Description: Test mmap on system memory
  */
 
+/**
+ * SUBTEST: small-bar
+ * Description: Sanity check mmap behaviour on small-bar systems
+ * GPU requirements: GPU needs to have dedicated VRAM and using small-bar
+ */
+
 /**
  * SUBTEST: %s
  * Description: Test mmap on %arg[1] memory
@@ -107,6 +114,83 @@ static void test_bad_object(int fd)
 	do_ioctl_err(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo, ENOENT);
 }
 
+static jmp_buf jmp;
+
+__noreturn static void sigtrap(int sig)
+{
+	siglongjmp(jmp, sig);
+}
+
+static void trap_sigbus(uint32_t *ptr)
+{
+	sighandler_t old_sigbus;
+
+	old_sigbus = signal(SIGBUS, sigtrap);
+	switch (sigsetjmp(jmp, SIGBUS)) {
+	case SIGBUS:
+		break;
+	case 0:
+		*ptr = 0xdeadbeaf;
+	default:
+		igt_assert(!"reached");
+		break;
+	}
+	signal(SIGBUS, old_sigbus);
+}
+
+/**
+ * SUBTEST: small-bar
+ * Description: Test mmap behaviour on small-bar systems.
+ *
+ */
+static void test_small_bar(int fd)
+{
+	uint32_t visible_size = xe_visible_vram_size(fd, 0);
+	uint32_t bo;
+	uint64_t mmo;
+	uint32_t *map;
+
+	/* 2BIG invalid case */
+	igt_assert_neq(__xe_bo_create_flags(fd, 0, visible_size + 4096,
+					    visible_vram_memory(fd, 0), &bo),
+		       0);
+
+	/* Normal operation */
+	bo = xe_bo_create_flags(fd, 0, visible_size / 4,
+				visible_vram_memory(fd, 0));
+	mmo = xe_bo_mmap_offset(fd, bo);
+	map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
+	igt_assert(map != MAP_FAILED);
+
+	map[0] = 0xdeadbeaf;
+
+	munmap(map, 4096);
+	gem_close(fd, bo);
+
+	/* Normal operation with system memory spilling */
+	bo = xe_bo_create_flags(fd, 0, visible_size,
+				visible_vram_memory(fd, 0) |
+				system_memory(fd));
+	mmo = xe_bo_mmap_offset(fd, bo);
+	map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
+	igt_assert(map != MAP_FAILED);
+
+	map[0] = 0xdeadbeaf;
+
+	munmap(map, 4096);
+	gem_close(fd, bo);
+
+	/* Bogus operation with SIGBUS */
+	bo = xe_bo_create_flags(fd, 0, visible_size + 4096,
+				vram_memory(fd, 0));
+	mmo = xe_bo_mmap_offset(fd, bo);
+	map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
+	igt_assert(map != MAP_FAILED);
+
+	trap_sigbus(map);
+	gem_close(fd, bo);
+}
+
 igt_main
 {
 	int fd;
@@ -132,6 +216,12 @@ igt_main
 	igt_subtest("bad-object")
 		test_bad_object(fd);
 
+	igt_subtest("small-bar") {
+		igt_require(xe_visible_vram_size(fd, 0));
+		igt_require(xe_visible_vram_size(fd, 0) < xe_vram_size(fd, 0));
+		test_small_bar(fd);
+	}
+
 	igt_fixture
 		drm_close_driver(fd);
 }
-- 
2.41.0

[igt-dev] ✓ Fi.CI.BAT: success for IGT bits for small-bar (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7397 bytes --]

== Series Details ==

Series: IGT bits for small-bar (rev5)
URL   : https://patchwork.freedesktop.org/series/115786/
State : success

== Summary ==

CI Bug Log - changes from IGT_7388 -> IGTPW_9411
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/index.html

Participating hosts (44 -> 42)
------------------------------

  Missing    (2): fi-kbl-soraka fi-snb-2520m 

Known issues
------------

  Here are the changes found in IGTPW_9411 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_auth@basic-auth:
    - bat-adlp-11:        NOTRUN -> [ABORT][1] ([i915#8011])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/bat-adlp-11/igt@core_auth@basic-auth.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-cfl-8700k:       [PASS][2] -> [FAIL][3] ([i915#7940]) +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-skl-guc:         [PASS][4] -> [FAIL][5] ([i915#7940]) +1 similar issue
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/fi-skl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/fi-skl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-apl-guc:         [PASS][6] -> [DMESG-FAIL][7] ([i915#5334])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
    - fi-glk-j4005:       [PASS][8] -> [DMESG-FAIL][9] ([i915#5334])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-cfl-8109u:       [FAIL][10] ([i915#7940]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/fi-cfl-8109u/igt@i915_pm_rpm@basic-pci-d3-state.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/fi-cfl-8109u/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-cfl-guc:         [FAIL][12] ([i915#7940]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
    - fi-rkl-11600:       [FAIL][14] ([i915#7940]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@gt_mocs:
    - bat-mtlp-6:         [DMESG-FAIL][16] ([i915#7059]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@migrate:
    - bat-mtlp-8:         [DMESG-FAIL][18] ([i915#7699]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/bat-mtlp-8/igt@i915_selftest@live@migrate.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/bat-mtlp-8/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@slpc:
    - bat-mtlp-6:         [DMESG-WARN][20] ([i915#6367]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/bat-mtlp-6/igt@i915_selftest@live@slpc.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/bat-mtlp-6/igt@i915_selftest@live@slpc.html
    - bat-rpls-1:         [DMESG-WARN][22] ([i915#6367]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/bat-rpls-1/igt@i915_selftest@live@slpc.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/bat-rpls-1/igt@i915_selftest@live@slpc.html

  
#### Warnings ####

  * igt@i915_module_load@load:
    - bat-adlp-11:        [ABORT][24] ([i915#4423]) -> [DMESG-WARN][25] ([i915#4423])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/bat-adlp-11/igt@i915_module_load@load.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/bat-adlp-11/igt@i915_module_load@load.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-kbl-guc:         [SKIP][26] ([fdo#109271]) -> [FAIL][27] ([i915#7940])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-8809g:       [FAIL][28] ([i915#8843]) -> [FAIL][29] ([i915#7940])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/fi-kbl-8809g/igt@i915_pm_rpm@basic-rte.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/fi-kbl-8809g/igt@i915_pm_rpm@basic-rte.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-rplp-1:         [ABORT][30] ([i915#8442] / [i915#8668] / [i915#8712]) -> [ABORT][31] ([i915#8712])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
  [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
  [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8712]: https://gitlab.freedesktop.org/drm/intel/issues/8712
  [i915#8843]: https://gitlab.freedesktop.org/drm/intel/issues/8843


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7388 -> IGTPW_9411

  CI-20190529: 20190529
  CI_DRM_13385: f8be3c363790b79801f7be6bd40062219e3789bc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9411: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/index.html
  IGT_7388: 7388


Testlist changes
----------------

+igt@xe_mmap@small-bar
-igt@syncobj_eventfd@binary-wait
-igt@syncobj_eventfd@binary-wait-before-signal
-igt@syncobj_eventfd@binary-wait-signaled
-igt@syncobj_eventfd@invalid-bad-flags
-igt@syncobj_eventfd@invalid-bad-pad
-igt@syncobj_eventfd@invalid-illegal-eventfd
-igt@syncobj_eventfd@invalid-illegal-handle
-igt@syncobj_eventfd@timeline-wait
-igt@syncobj_eventfd@timeline-wait-before-signal
-igt@syncobj_eventfd@timeline-wait-signaled

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/index.html

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[igt-dev] ○ CI.xeBAT: info for IGT bits for small-bar (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 327 bytes --]

== Series Details ==

Series: IGT bits for small-bar (rev5)
URL   : https://patchwork.freedesktop.org/series/115786/
State : info

== Summary ==

Participating hosts:
bat-pvc-2
bat-atsm-2
bat-dg2-oem2
bat-adlp-7
Missing hosts results[0]:
Results: [IGTPW_9411](https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9411/index.html)



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[igt-dev] ✓ Fi.CI.IGT: success for IGT bits for small-bar (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 69055 bytes --]

== Series Details ==

Series: IGT bits for small-bar (rev5)
URL   : https://patchwork.freedesktop.org/series/115786/
State : success

== Summary ==

CI Bug Log - changes from IGT_7388_full -> IGTPW_9411_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/index.html

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in IGTPW_9411_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@device_reset@cold-reset-bound:
    - shard-tglu:         NOTRUN -> [SKIP][1] ([i915#7701])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-4/igt@device_reset@cold-reset-bound.html

  * igt@drm_fdinfo@busy-idle-check-all@vcs0:
    - shard-dg2:          NOTRUN -> [SKIP][2] ([i915#8414]) +9 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-11/igt@drm_fdinfo@busy-idle-check-all@vcs0.html

  * igt@drm_fdinfo@virtual-busy-hang:
    - shard-mtlp:         NOTRUN -> [SKIP][3] ([i915#8414])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-8/igt@drm_fdinfo@virtual-busy-hang.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-rkl:          NOTRUN -> [SKIP][4] ([i915#3555] / [i915#5325])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@gem_ccs@block-copy-compressed.html
    - shard-tglu:         NOTRUN -> [SKIP][5] ([i915#3555] / [i915#5325])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-2/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-mtlp:         NOTRUN -> [SKIP][6] ([i915#5325])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-rkl:          NOTRUN -> [SKIP][7] ([i915#6335])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-4/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-mtlp:         NOTRUN -> [SKIP][8] ([i915#6335])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_ctx_persistence@engines-hostile@vcs0:
    - shard-mtlp:         [PASS][9] -> [FAIL][10] ([i915#2410]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-2/igt@gem_ctx_persistence@engines-hostile@vcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-7/igt@gem_ctx_persistence@engines-hostile@vcs0.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-mtlp:         NOTRUN -> [SKIP][11] ([i915#280])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_eio@kms:
    - shard-dg2:          [PASS][12] -> [FAIL][13] ([i915#5784])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg2-3/igt@gem_eio@kms.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-11/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@full-pulse:
    - shard-dg2:          NOTRUN -> [FAIL][14] ([i915#6032])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-12/igt@gem_exec_balancer@full-pulse.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-mtlp:         NOTRUN -> [SKIP][15] ([i915#4036])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-7/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_balancer@noheartbeat:
    - shard-dg2:          NOTRUN -> [SKIP][16] ([i915#8555]) +2 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-11/igt@gem_exec_balancer@noheartbeat.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-tglu:         NOTRUN -> [SKIP][17] ([i915#6344])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-3/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_fair@basic-none:
    - shard-snb:          NOTRUN -> [SKIP][18] ([fdo#109271]) +83 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-snb2/igt@gem_exec_fair@basic-none.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-rkl:          [PASS][19] -> [FAIL][20] ([i915#2842]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-rkl-2/igt@gem_exec_fair@basic-pace@bcs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-7/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_fence@submit:
    - shard-dg2:          NOTRUN -> [SKIP][21] ([i915#4812])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-1/igt@gem_exec_fence@submit.html

  * igt@gem_exec_flush@basic-wb-ro-default:
    - shard-dg2:          NOTRUN -> [SKIP][22] ([i915#3539] / [i915#4852])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-12/igt@gem_exec_flush@basic-wb-ro-default.html

  * igt@gem_exec_reloc@basic-cpu-read-active:
    - shard-apl:          [PASS][23] -> [DMESG-WARN][24] ([i915#8585]) +35 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-apl4/igt@gem_exec_reloc@basic-cpu-read-active.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-apl1/igt@gem_exec_reloc@basic-cpu-read-active.html

  * igt@gem_exec_reloc@basic-wc-noreloc:
    - shard-dg2:          NOTRUN -> [SKIP][25] ([i915#3281])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-5/igt@gem_exec_reloc@basic-wc-noreloc.html
    - shard-rkl:          NOTRUN -> [SKIP][26] ([i915#3281])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@gem_exec_reloc@basic-wc-noreloc.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - shard-mtlp:         NOTRUN -> [SKIP][27] ([i915#3281])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-7/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_exec_schedule@preempt-queue:
    - shard-mtlp:         NOTRUN -> [SKIP][28] ([i915#4812]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@gem_exec_schedule@preempt-queue.html

  * igt@gem_exec_suspend@basic-s4-devices@lmem0:
    - shard-dg2:          NOTRUN -> [ABORT][29] ([i915#7975] / [i915#8213])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-2/igt@gem_exec_suspend@basic-s4-devices@lmem0.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#4860])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-10/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html

  * igt@gem_lmem_swapping@basic:
    - shard-mtlp:         NOTRUN -> [SKIP][31] ([i915#4613]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-6/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-tglu:         NOTRUN -> [SKIP][32] ([i915#4613]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-2/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-rkl:          NOTRUN -> [SKIP][33] ([i915#4613]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-6/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_mmap_gtt@coherency:
    - shard-tglu:         NOTRUN -> [SKIP][34] ([fdo#111656])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-5/igt@gem_mmap_gtt@coherency.html

  * igt@gem_mmap_gtt@hang-busy:
    - shard-mtlp:         NOTRUN -> [SKIP][35] ([i915#4077]) +6 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@gem_mmap_gtt@hang-busy.html

  * igt@gem_mmap_gtt@medium-copy-xy:
    - shard-dg2:          NOTRUN -> [SKIP][36] ([i915#4077]) +4 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-11/igt@gem_mmap_gtt@medium-copy-xy.html

  * igt@gem_mmap_wc@copy:
    - shard-mtlp:         NOTRUN -> [SKIP][37] ([i915#4083]) +3 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-8/igt@gem_mmap_wc@copy.html

  * igt@gem_mmap_wc@write-wc-read-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#4083]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-12/igt@gem_mmap_wc@write-wc-read-gtt.html

  * igt@gem_partial_pwrite_pread@write:
    - shard-mtlp:         NOTRUN -> [SKIP][39] ([i915#3282])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-2/igt@gem_partial_pwrite_pread@write.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-rkl:          NOTRUN -> [SKIP][40] ([i915#3282])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_pread@bench:
    - shard-dg2:          NOTRUN -> [SKIP][41] ([i915#3282]) +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-8/igt@gem_pread@bench.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-mtlp:         NOTRUN -> [SKIP][42] ([i915#4270]) +2 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-6/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#4270])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-11/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
    - shard-rkl:          NOTRUN -> [SKIP][44] ([i915#4270])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-7/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
    - shard-tglu:         NOTRUN -> [SKIP][45] ([i915#4270])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-8/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html

  * igt@gem_render_copy@linear-to-vebox-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][46] ([i915#8428]) +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-8/igt@gem_render_copy@linear-to-vebox-y-tiled.html

  * igt@gem_tiled_pread_basic:
    - shard-mtlp:         NOTRUN -> [SKIP][47] ([i915#4079])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-2/igt@gem_tiled_pread_basic.html

  * igt@gem_userptr_blits@access-control:
    - shard-mtlp:         NOTRUN -> [SKIP][48] ([i915#3297]) +3 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-7/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#3297]) +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-6/igt@gem_userptr_blits@create-destroy-unsync.html
    - shard-rkl:          NOTRUN -> [SKIP][50] ([i915#3297]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@nohangcheck:
    - shard-mtlp:         [PASS][51] -> [FAIL][52] ([i915#7916])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-5/igt@gem_userptr_blits@nohangcheck.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-7/igt@gem_userptr_blits@nohangcheck.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][53] ([i915#3297])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-5/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gen3_render_tiledx_blits:
    - shard-mtlp:         NOTRUN -> [SKIP][54] ([fdo#109289])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@gen3_render_tiledx_blits.html

  * igt@gen7_exec_parse@basic-allocation:
    - shard-rkl:          NOTRUN -> [SKIP][55] ([fdo#109289])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-4/igt@gen7_exec_parse@basic-allocation.html

  * igt@gen7_exec_parse@bitmasks:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([fdo#109289]) +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-10/igt@gen7_exec_parse@bitmasks.html

  * igt@gen9_exec_parse@batch-zero-length:
    - shard-mtlp:         NOTRUN -> [SKIP][57] ([i915#2856]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@gen9_exec_parse@batch-zero-length.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#2856]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-5/igt@gen9_exec_parse@shadow-peek.html
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#2527]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_hangman@engine-engine-error@vcs0:
    - shard-mtlp:         [PASS][60] -> [FAIL][61] ([i915#7069]) +2 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-7/igt@i915_hangman@engine-engine-error@vcs0.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@i915_hangman@engine-engine-error@vcs0.html

  * igt@i915_module_load@resize-bar:
    - shard-mtlp:         NOTRUN -> [SKIP][62] ([i915#6412])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-3/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_backlight@fade-with-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][63] ([i915#5354] / [i915#7561])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-7/igt@i915_pm_backlight@fade-with-dpms.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-mtlp:         NOTRUN -> [SKIP][64] ([i915#3361])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][65] ([i915#3361])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-4/igt@i915_pm_dc@dc9-dpms.html
    - shard-tglu:         NOTRUN -> [SKIP][66] ([i915#4281])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-3/igt@i915_pm_dc@dc9-dpms.html
    - shard-apl:          [PASS][67] -> [SKIP][68] ([fdo#109271])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-apl6/igt@i915_pm_dc@dc9-dpms.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-apl2/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_freq_api@freq-basic-api@gt0:
    - shard-mtlp:         NOTRUN -> [FAIL][69] ([i915#8670])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@i915_pm_freq_api@freq-basic-api@gt0.html

  * igt@i915_pm_lpsp@screens-disabled:
    - shard-tglu:         NOTRUN -> [SKIP][70] ([i915#1902])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-9/igt@i915_pm_lpsp@screens-disabled.html

  * igt@i915_pm_rpm@cursor-dpms:
    - shard-tglu:         [PASS][71] -> [FAIL][72] ([i915#7940]) +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-tglu-8/igt@i915_pm_rpm@cursor-dpms.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-6/igt@i915_pm_rpm@cursor-dpms.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-dg2:          [PASS][73] -> [SKIP][74] ([i915#1397])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg2-7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - shard-dg2:          [PASS][75] -> [FAIL][76] ([fdo#103375]) +3 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg2-3/igt@i915_pm_rpm@system-suspend-modeset.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-5/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@i915_pm_rps@basic-api:
    - shard-mtlp:         NOTRUN -> [SKIP][77] ([i915#6621])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-2/igt@i915_pm_rps@basic-api.html

  * igt@i915_query@query-topology-unsupported:
    - shard-mtlp:         NOTRUN -> [SKIP][78] ([fdo#109302])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-3/igt@i915_query@query-topology-unsupported.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-snb:          NOTRUN -> [DMESG-WARN][79] ([i915#8841]) +2 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-snb2/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][80] ([i915#4212]) +1 similar issue
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@kms_addfb_basic@basic-x-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - shard-dg2:          NOTRUN -> [SKIP][81] ([i915#4212])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-12/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
    - shard-mtlp:         [PASS][82] -> [FAIL][83] ([i915#2521])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html

  * igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [FAIL][84] ([i915#8247]) +3 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-1/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][85] ([i915#5286]) +2 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-mtlp:         NOTRUN -> [FAIL][86] ([i915#3743])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][87] -> [FAIL][88] ([i915#5138])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][89] ([fdo#111615] / [i915#5286])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([fdo#111614] / [i915#3638]) +1 similar issue
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@kms_big_fb@linear-64bpp-rotate-90.html
    - shard-tglu:         NOTRUN -> [SKIP][91] ([fdo#111614])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-2/igt@kms_big_fb@linear-64bpp-rotate-90.html
    - shard-dg2:          NOTRUN -> [SKIP][92] ([fdo#111614])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-5/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-mtlp:         NOTRUN -> [SKIP][93] ([fdo#111614]) +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][94] ([i915#5190]) +3 similar issues
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-12/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][95] ([fdo#111615]) +5 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
    - shard-rkl:          NOTRUN -> [SKIP][96] ([fdo#110723])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#4538] / [i915#5190])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-3/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-tglu:         NOTRUN -> [SKIP][98] ([fdo#111615])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-mtlp:         NOTRUN -> [SKIP][99] ([i915#3886] / [i915#6095]) +3 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][100] ([i915#3689] / [i915#3886] / [i915#5354]) +2 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-11/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
    - shard-rkl:          NOTRUN -> [SKIP][101] ([i915#3886] / [i915#5354] / [i915#6095])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
    - shard-tglu:         NOTRUN -> [SKIP][102] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_ccs:
    - shard-tglu:         NOTRUN -> [SKIP][103] ([i915#3689] / [i915#5354] / [i915#6095]) +1 similar issue
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-10/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs:
    - shard-tglu:         NOTRUN -> [SKIP][104] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-8/igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#5354] / [i915#6095]) +4 similar issues
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html
    - shard-tglu:         NOTRUN -> [SKIP][106] ([i915#5354] / [i915#6095]) +4 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-10/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#3886])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-apl4/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][108] ([i915#3689] / [i915#5354]) +8 similar issues
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-2/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs.html
    - shard-rkl:          NOTRUN -> [SKIP][109] ([i915#5354]) +8 similar issues
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-4/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][110] ([i915#6095]) +18 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][111] ([i915#4087] / [i915#7213]) +3 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-5/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-mtlp:         NOTRUN -> [SKIP][112] ([fdo#111827])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-2/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_edid@vga-edid-read:
    - shard-dg2:          NOTRUN -> [SKIP][113] ([i915#7828]) +4 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-6/igt@kms_chamelium_edid@vga-edid-read.html
    - shard-rkl:          NOTRUN -> [SKIP][114] ([i915#7828]) +4 similar issues
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@kms_chamelium_edid@vga-edid-read.html

  * igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
    - shard-tglu:         NOTRUN -> [SKIP][115] ([i915#7828]) +5 similar issues
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-5/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html

  * igt@kms_chamelium_hpd@vga-hpd-without-ddc:
    - shard-mtlp:         NOTRUN -> [SKIP][116] ([i915#7828]) +2 similar issues
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-2/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#3299]) +1 similar issue
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-6/igt@kms_content_protection@dp-mst-lic-type-1.html
    - shard-rkl:          NOTRUN -> [SKIP][118] ([i915#3116]) +1 similar issue
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][119] ([i915#3116] / [i915#3299])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-10/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-mtlp:         NOTRUN -> [SKIP][120] ([i915#3299])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@srm@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][121] ([i915#7173])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-11/igt@kms_content_protection@srm@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][122] ([i915#3359])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-10/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][123] ([fdo#111767] / [i915#3546])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][124] ([i915#3546]) +5 similar issues
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-tglu:         NOTRUN -> [SKIP][125] ([fdo#109274]) +1 similar issue
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-5/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
    - shard-dg2:          NOTRUN -> [SKIP][126] ([fdo#109274] / [i915#5354])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-5/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [PASS][127] -> [FAIL][128] ([i915#2346]) +1 similar issue
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-apl:          [PASS][129] -> [DMESG-WARN][130] ([i915#1982] / [i915#8585]) +2 similar issues
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-mtlp:         NOTRUN -> [SKIP][131] ([i915#4213])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          NOTRUN -> [SKIP][132] ([i915#3555]) +1 similar issue
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-8/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-mtlp:         NOTRUN -> [SKIP][133] ([i915#3840])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-6/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank:
    - shard-mtlp:         NOTRUN -> [SKIP][134] ([i915#3637]) +3 similar issues
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@kms_flip@2x-blocking-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-mtlp:         NOTRUN -> [SKIP][135] ([fdo#111767] / [i915#3637])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][136] -> [FAIL][137] ([i915#79])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-modeset:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([fdo#109274]) +1 similar issue
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-6/igt@kms_flip@2x-flip-vs-modeset.html
    - shard-rkl:          NOTRUN -> [SKIP][139] ([fdo#111825]) +3 similar issues
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-4/igt@kms_flip@2x-flip-vs-modeset.html
    - shard-tglu:         NOTRUN -> [SKIP][140] ([fdo#109274] / [i915#3637]) +1 similar issue
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-4/igt@kms_flip@2x-flip-vs-modeset.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-snb:          NOTRUN -> [SKIP][141] ([fdo#109271] / [fdo#111767])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-snb2/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-panning-vs-hang@a-dp1:
    - shard-apl:          [PASS][142] -> [DMESG-WARN][143] ([i915#180] / [i915#1982] / [i915#7634] / [i915#8585])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-apl3/igt@kms_flip@flip-vs-panning-vs-hang@a-dp1.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-apl1/igt@kms_flip@flip-vs-panning-vs-hang@a-dp1.html

  * igt@kms_flip@plain-flip-ts-check@c-hdmi-a1:
    - shard-glk:          [PASS][144] -> [FAIL][145] ([i915#2122])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-glk4/igt@kms_flip@plain-flip-ts-check@c-hdmi-a1.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-glk9/igt@kms_flip@plain-flip-ts-check@c-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][146] ([i915#2672]) +1 similar issue
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][147] ([i915#2587] / [i915#2672]) +1 similar issue
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][148] ([i915#2672])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][149] ([i915#8810]) +1 similar issue
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][150] ([i915#2672])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
    - shard-dg2:          [PASS][151] -> [FAIL][152] ([i915#6880])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][153] ([i915#8708]) +3 similar issues
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#8708]) +11 similar issues
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][155] ([i915#1825]) +15 similar issues
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][156] ([i915#3023]) +9 similar issues
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-pwrite:
    - shard-tglu:         NOTRUN -> [SKIP][157] ([fdo#109280]) +8 similar issues
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][158] ([i915#5354]) +12 similar issues
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([fdo#111825] / [i915#1825]) +7 similar issues
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#3458]) +4 similar issues
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][161] ([i915#3555] / [i915#8228])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-5/igt@kms_hdr@static-toggle.html
    - shard-rkl:          NOTRUN -> [SKIP][162] ([i915#3555] / [i915#8228])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@kms_hdr@static-toggle.html
    - shard-tglu:         NOTRUN -> [SKIP][163] ([i915#3555] / [i915#8228])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-2/igt@kms_hdr@static-toggle.html

  * igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][164] ([fdo#109289]) +1 similar issue
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-4/igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c.html

  * igt@kms_plane_cursor@viewport@pipe-d-edp-1-size-128:
    - shard-mtlp:         [PASS][165] -> [DMESG-WARN][166] ([i915#1982])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-6/igt@kms_plane_cursor@viewport@pipe-d-edp-1-size-128.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@kms_plane_cursor@viewport@pipe-d-edp-1-size-128.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#3555]) +1 similar issue
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-1/igt@kms_plane_multiple@tiling-yf.html
    - shard-tglu:         NOTRUN -> [SKIP][168] ([i915#3555])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-5/igt@kms_plane_multiple@tiling-yf.html
    - shard-dg2:          NOTRUN -> [SKIP][169] ([i915#3555] / [i915#8806])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-12/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][170] ([i915#5176]) +3 similar issues
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][171] ([i915#5176]) +3 similar issues
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-8/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][172] ([i915#5235]) +3 similar issues
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][173] ([i915#5235]) +7 similar issues
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][174] ([i915#5235]) +15 similar issues
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html

  * igt@kms_prime@basic-crc-vgem@second-to-first:
    - shard-apl:          [PASS][175] -> [DMESG-WARN][176] ([i915#7634] / [i915#8585]) +12 similar issues
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-apl1/igt@kms_prime@basic-crc-vgem@second-to-first.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-apl1/igt@kms_prime@basic-crc-vgem@second-to-first.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-mtlp:         NOTRUN -> [SKIP][177] ([i915#4348])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([i915#1072]) +2 similar issues
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-6/igt@kms_psr@psr2_cursor_mmap_gtt.html
    - shard-rkl:          NOTRUN -> [SKIP][179] ([i915#1072]) +1 similar issue
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@kms_psr@psr2_sprite_plane_onoff:
    - shard-tglu:         NOTRUN -> [SKIP][180] ([fdo#110189]) +5 similar issues
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-7/igt@kms_psr@psr2_sprite_plane_onoff.html

  * igt@kms_pwrite_crc:
    - shard-apl:          [PASS][181] -> [DMESG-WARN][182] ([i915#180] / [i915#7634] / [i915#8585]) +20 similar issues
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-apl7/igt@kms_pwrite_crc.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-apl1/igt@kms_pwrite_crc.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-mtlp:         NOTRUN -> [SKIP][183] ([i915#5289])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-dg2:          NOTRUN -> [SKIP][184] ([i915#4235] / [i915#5190])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-rkl:          [PASS][185] -> [ABORT][186] ([i915#7461])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-rkl-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-dg2:          NOTRUN -> [SKIP][187] ([fdo#109309])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-12/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm:
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#4070] / [i915#6768])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-6/igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm.html

  * igt@kms_vblank@pipe-d-query-forked-hang:
    - shard-rkl:          NOTRUN -> [SKIP][189] ([i915#4070] / [i915#533] / [i915#6768]) +1 similar issue
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-4/igt@kms_vblank@pipe-d-query-forked-hang.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-mtlp:         NOTRUN -> [SKIP][190] ([i915#2437])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-dg2:          NOTRUN -> [SKIP][191] ([i915#2436])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-7/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf_pmu@busy-idle-check-all@ccs0:
    - shard-mtlp:         NOTRUN -> [FAIL][192] ([i915#4521]) +3 similar issues
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@perf_pmu@busy-idle-check-all@ccs0.html

  * igt@perf_pmu@busy-idle-check-all@vcs0:
    - shard-dg2:          [PASS][193] -> [FAIL][194] ([i915#4521]) +7 similar issues
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg2-8/igt@perf_pmu@busy-idle-check-all@vcs0.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-6/igt@perf_pmu@busy-idle-check-all@vcs0.html

  * igt@prime_vgem@basic-fence-read:
    - shard-mtlp:         NOTRUN -> [SKIP][195] ([i915#3708])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@prime_vgem@basic-fence-read.html

  * igt@runner@aborted:
    - shard-snb:          NOTRUN -> ([FAIL][196], [FAIL][197], [FAIL][198]) ([i915#7812] / [i915#8848])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-snb7/igt@runner@aborted.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-snb4/igt@runner@aborted.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-snb5/igt@runner@aborted.html

  * igt@sysfs_heartbeat_interval@mixed@ccs0:
    - shard-mtlp:         NOTRUN -> [ABORT][199] ([i915#8552])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@sysfs_heartbeat_interval@mixed@ccs0.html

  * igt@sysfs_heartbeat_interval@mixed@vecs0:
    - shard-mtlp:         NOTRUN -> [FAIL][200] ([i915#1731])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-4/igt@sysfs_heartbeat_interval@mixed@vecs0.html

  * igt@v3d/v3d_submit_cl@bad-multisync-pad:
    - shard-tglu:         NOTRUN -> [SKIP][201] ([fdo#109315] / [i915#2575]) +4 similar issues
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-8/igt@v3d/v3d_submit_cl@bad-multisync-pad.html
    - shard-mtlp:         NOTRUN -> [SKIP][202] ([i915#2575]) +5 similar issues
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-6/igt@v3d/v3d_submit_cl@bad-multisync-pad.html

  * igt@v3d/v3d_wait_bo@used-bo-0ns:
    - shard-dg2:          NOTRUN -> [SKIP][203] ([i915#2575]) +5 similar issues
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-1/igt@v3d/v3d_wait_bo@used-bo-0ns.html
    - shard-rkl:          NOTRUN -> [SKIP][204] ([fdo#109315]) +4 similar issues
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-2/igt@v3d/v3d_wait_bo@used-bo-0ns.html

  * igt@vc4/vc4_perfmon@create-perfmon-exceed:
    - shard-mtlp:         NOTRUN -> [SKIP][205] ([i915#7711]) +3 similar issues
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@vc4/vc4_perfmon@create-perfmon-exceed.html

  * igt@vc4/vc4_perfmon@get-values-invalid-perfmon:
    - shard-dg2:          NOTRUN -> [SKIP][206] ([i915#7711])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-7/igt@vc4/vc4_perfmon@get-values-invalid-perfmon.html

  * igt@vc4/vc4_tiling@get-after-free:
    - shard-tglu:         NOTRUN -> [SKIP][207] ([i915#2575])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-10/igt@vc4/vc4_tiling@get-after-free.html

  
#### Possible fixes ####

  * igt@gem_create@hog-create@smem0:
    - shard-dg2:          [FAIL][208] ([i915#5892] / [i915#8758]) -> [PASS][209]
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg2-6/igt@gem_create@hog-create@smem0.html
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-5/igt@gem_create@hog-create@smem0.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-rkl:          [FAIL][210] ([i915#6268]) -> [PASS][211]
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-6/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_isolation@preservation-s3@ccs0:
    - shard-dg2:          [FAIL][212] ([fdo#103375]) -> [PASS][213] +3 similar issues
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg2-5/igt@gem_ctx_isolation@preservation-s3@ccs0.html
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-5/igt@gem_ctx_isolation@preservation-s3@ccs0.html

  * igt@gem_ctx_persistence@engines-hang@vcs0:
    - shard-mtlp:         [FAIL][214] ([i915#2410]) -> [PASS][215]
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-6/igt@gem_ctx_persistence@engines-hang@vcs0.html
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-3/igt@gem_ctx_persistence@engines-hang@vcs0.html

  * igt@gem_ctx_persistence@saturated-hostile@vecs0:
    - shard-mtlp:         [FAIL][216] ([i915#7816]) -> [PASS][217] +2 similar issues
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-5/igt@gem_ctx_persistence@saturated-hostile@vecs0.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@gem_ctx_persistence@saturated-hostile@vecs0.html

  * igt@gem_eio@in-flight-contexts-10ms:
    - shard-mtlp:         [ABORT][218] ([i915#7941]) -> [PASS][219]
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-8/igt@gem_eio@in-flight-contexts-10ms.html
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@gem_eio@in-flight-contexts-10ms.html

  * igt@gem_eio@in-flight-contexts-immediate:
    - shard-mtlp:         [ABORT][220] ([i915#8503]) -> [PASS][221]
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-6/igt@gem_eio@in-flight-contexts-immediate.html
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@gem_eio@in-flight-contexts-immediate.html

  * igt@gem_exec_capture@capture@vcs1-smem:
    - shard-mtlp:         [DMESG-WARN][222] ([i915#5591]) -> [PASS][223]
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-2/igt@gem_exec_capture@capture@vcs1-smem.html
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-2/igt@gem_exec_capture@capture@vcs1-smem.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglu:         [FAIL][224] ([i915#2842]) -> [PASS][225]
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-tglu-10/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-7/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-rkl:          [FAIL][226] ([i915#2842]) -> [PASS][227] +2 similar issues
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-rkl-6/igt@gem_exec_fair@basic-throttle@rcs0.html
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-4/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglu:         [FAIL][228] ([i915#3989] / [i915#454]) -> [PASS][229]
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-tglu-9/igt@i915_pm_dc@dc6-dpms.html
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-2/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg2:          [SKIP][230] ([i915#1397]) -> [PASS][231]
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg2-2/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-12/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [SKIP][232] ([i915#1397]) -> [PASS][233] +1 similar issue
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-4/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - {shard-dg1}:        [SKIP][234] ([i915#1397]) -> [PASS][235] +2 similar issues
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg1-19/igt@i915_pm_rpm@dpms-non-lpsp.html
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg1-18/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@gem-execbuf-stress@smem0:
    - {shard-dg1}:        [FAIL][236] ([i915#7940]) -> [PASS][237] +2 similar issues
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg1-18/igt@i915_pm_rpm@gem-execbuf-stress@smem0.html
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg1-19/igt@i915_pm_rpm@gem-execbuf-stress@smem0.html
    - shard-tglu:         [FAIL][238] ([i915#7940]) -> [PASS][239] +2 similar issues
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-tglu-9/igt@i915_pm_rpm@gem-execbuf-stress@smem0.html
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-10/igt@i915_pm_rpm@gem-execbuf-stress@smem0.html

  * igt@i915_selftest@live@gt_mocs:
    - shard-mtlp:         [DMESG-FAIL][240] ([i915#7059]) -> [PASS][241]
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-6/igt@i915_selftest@live@gt_mocs.html
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-6/igt@i915_selftest@live@gt_mocs.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-mtlp:         [FAIL][242] ([i915#5138]) -> [PASS][243]
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-mtlp:         [FAIL][244] ([i915#3743]) -> [PASS][245]
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
    - shard-mtlp:         [FAIL][246] ([i915#8248]) -> [PASS][247]
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
    - shard-tglu:         [ABORT][248] ([i915#5122] / [i915#5251]) -> [PASS][249] +1 similar issue
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-tglu-8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-tglu:         [INCOMPLETE][250] ([i915#1982]) -> [PASS][251]
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-tglu-8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-tglu-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@perf@non-zero-reason@0-rcs0:
    - shard-dg2:          [FAIL][252] ([i915#7484]) -> [PASS][253]
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg2-3/igt@perf@non-zero-reason@0-rcs0.html
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-6/igt@perf@non-zero-reason@0-rcs0.html

  * igt@sysfs_heartbeat_interval@nopreempt@vcs0:
    - shard-mtlp:         [FAIL][254] ([i915#6015]) -> [PASS][255] +1 similar issue
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-5/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-2/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html

  
#### Warnings ####

  * igt@gem_exec_whisper@basic-contexts-forked-all:
    - shard-mtlp:         [ABORT][256] ([i915#8131]) -> [TIMEOUT][257] ([i915#8628])
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-1/igt@gem_exec_whisper@basic-contexts-forked-all.html
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-5/igt@gem_exec_whisper@basic-contexts-forked-all.html

  * igt@gem_exec_whisper@basic-contexts-priority-all:
    - shard-mtlp:         [ABORT][258] ([i915#8131]) -> [TIMEOUT][259] ([i915#7392])
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-mtlp-5/igt@gem_exec_whisper@basic-contexts-priority-all.html
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-mtlp-8/igt@gem_exec_whisper@basic-contexts-priority-all.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          [TIMEOUT][260] ([i915#5493]) -> [DMESG-WARN][261] ([i915#4936] / [i915#5493])
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-dg2-3/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][262] ([i915#4816]) -> [SKIP][263] ([i915#4070] / [i915#4816])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7388/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#4521]: https://gitlab.freedesktop.org/drm/intel/issues/4521
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5251]: https://gitlab.freedesktop.org/drm/intel/issues/5251
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892
  [i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
  [i915#6032]: https://gitlab.freedesktop.org/drm/intel/issues/6032
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
  [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
  [i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
  [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7634]: https://gitlab.freedesktop.org/drm/intel/issues/7634
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7812]: https://gitlab.freedesktop.org/drm/intel/issues/7812
  [i915#7816]: https://gitlab.freedesktop.org/drm/intel/issues/7816
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7916]: https://gitlab.freedesktop.org/drm/intel/issues/7916
  [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
  [i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8131]: https://gitlab.freedesktop.org/drm/intel/issues/8131
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
  [i915#8503]: https://gitlab.freedesktop.org/drm/intel/issues/8503
  [i915#8552]: https://gitlab.freedesktop.org/drm/intel/issues/8552
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8585]: https://gitlab.freedesktop.org/drm/intel/issues/8585
  [i915#8628]: https://gitlab.freedesktop.org/drm/intel/issues/8628
  [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
  [i915#8670]: https://gitlab.freedesktop.org/drm/intel/issues/8670
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8758]: https://gitlab.freedesktop.org/drm/intel/issues/8758
  [i915#8806]: https://gitlab.freedesktop.org/drm/intel/issues/8806
  [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
  [i915#8848]: https://gitlab.freedesktop.org/drm/intel/issues/8848


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7388 -> IGTPW_9411

  CI-20190529: 20190529
  CI_DRM_13385: f8be3c363790b79801f7be6bd40062219e3789bc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9411: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/index.html
  IGT_7388: 7388

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9411/index.html

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