* [PATCH v1 0/3] Multi-tile support for xe_sriov_flr and other MMIO improvements
@ 2025-10-20 16:26 Piórkowski, Piotr
2025-10-20 16:26 ` [PATCH v1 1/3] lib/xe_mmio: Introduce tile-level XE MMIO access helpers Piórkowski, Piotr
` (7 more replies)
0 siblings, 8 replies; 14+ messages in thread
From: Piórkowski, Piotr @ 2025-10-20 16:26 UTC (permalink / raw)
To: igt-dev; +Cc: Piotr Piórkowski
From: Piotr Piórkowski <piotr.piorkowski@intel.com>
This series extends SR-IOV VF FLR tests to properly handle multi-tile Xe
devices and refactors related MMIO access layers for tile-level awareness
Piotr Piórkowski (3):
lib/xe_mmio: Introduce tile-level XE MMIO access helpers
lib/xe_mmio: Add init flag and helper to check initialization
tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices
lib/xe/xe_mmio.c | 108 +++++--
lib/xe/xe_mmio.h | 18 +-
lib/xe/xe_query.c | 45 +++
lib/xe/xe_query.h | 6 +
lib/xe/xe_sriov_provisioning.c | 6 +-
lib/xe/xe_sriov_provisioning.h | 2 +-
tests/intel/xe_sriov_flr.c | 513 ++++++++++++++++++---------------
7 files changed, 438 insertions(+), 260 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1 1/3] lib/xe_mmio: Introduce tile-level XE MMIO access helpers
2025-10-20 16:26 [PATCH v1 0/3] Multi-tile support for xe_sriov_flr and other MMIO improvements Piórkowski, Piotr
@ 2025-10-20 16:26 ` Piórkowski, Piotr
2025-10-22 11:54 ` Sokolowski, Jan
2025-10-20 16:26 ` [PATCH v1 2/3] lib/xe_mmio: Add init flag and helper to check initialization Piórkowski, Piotr
` (6 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Piórkowski, Piotr @ 2025-10-20 16:26 UTC (permalink / raw)
To: igt-dev; +Cc: Piotr Piórkowski, Lukasz Laguna, Marcin Bernatowicz
From: Piotr Piórkowski <piotr.piorkowski@intel.com>
Add new helpers for tile-based MMIO access:
- xe_mmio_tile_read32()
- xe_mmio_tile_read64()
- xe_mmio_tile_write32()
- xe_mmio_tile_write64()
These functions provide explicit MMIO read/write operations within
a given tile by applying TILE_MMIO_SIZE offsetting logic. Existing
GT-level MMIO helpers (xe_mmio_gt_*()) are refactored to use these
new tile-level accessors, simplifying code and improving consistency
across MMIO operations.
GGTT is also a per-tile resource, so let's adjust the GGTT access
helpers to use tile IDs instead of GT.
Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
---
lib/xe/xe_mmio.c | 94 ++++++++++++++++++++++++++--------
lib/xe/xe_mmio.h | 20 +++++---
lib/xe/xe_sriov_provisioning.c | 6 +--
lib/xe/xe_sriov_provisioning.h | 2 +-
tests/intel/xe_sriov_flr.c | 10 ++--
5 files changed, 95 insertions(+), 37 deletions(-)
diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
index 834816133..8bc446fb9 100644
--- a/lib/xe/xe_mmio.c
+++ b/lib/xe/xe_mmio.c
@@ -107,6 +107,62 @@ void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val)
return iowrite64(mmio->intel_mmio.igt_mmio, offset, val);
}
+/** xe_mmio_tile_read32:
+ * @mmio: xe mmio structure for IO operations
+ * @tile: tile id
+ * @offset: mmio register offset in the tile
+ *
+ * 32-bit read of the register at @offset in the specified @tile
+ *
+ * Returns: The value read from the register.
+ */
+uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
+{
+ return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * tile));
+}
+
+/** xe_mmio_tile_read64:
+ * @mmio: xe mmio structure for IO operations
+ * @tile: tile id
+ * @offset: mmio register offset in the @tile
+ *
+ * 64-bit read of the register at @offset in the specified @tile
+ *
+ * Returns: The value read from the register.
+ */
+uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
+{
+ return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * tile));
+}
+
+/**
+ * xe_mmio_tile_write32:
+ * @mmio: xe mmio structure for IO operations
+ * @tile: tile id
+ * @offset: mmio register offset in the @tile
+ * @val: value to write
+ *
+ * 32-bit write to the register at @offset in the specified @tile
+ */
+void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint32_t val)
+{
+ xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * tile), val);
+}
+
+/**
+ * xe_mmio_tile_write64:
+ * @mmio: xe mmio structure for IO operations
+ * @tile: tile id
+ * @offset: mmio register offset in the @tile
+ * @val: value to write
+ *
+ * 64-bit write to the register at @offset in the specified @tile
+ */
+void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint64_t val)
+{
+ xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * tile), val);
+}
+
/**
* xe_mmio_gt_read32:
* @mmio: xe mmio structure for IO operations
@@ -118,9 +174,9 @@ void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val)
* Returns:
* The value read from the register.
*/
-uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset)
+uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset)
{
- return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
+ return xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset);
}
/**
@@ -134,9 +190,9 @@ uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset)
* Returns:
* The value read from the register.
*/
-uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset)
+uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset)
{
- return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
+ return xe_mmio_tile_read64(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset);
}
/**
@@ -148,10 +204,9 @@ uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset)
*
* 32-bit write to the register at @offset in tile to which @gt belongs.
*/
-void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val)
+void xe_mmio_gt_write32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint32_t val)
{
- return xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
- val);
+ return xe_mmio_tile_write32(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset, val);
}
/**
@@ -163,38 +218,37 @@ void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t
*
* 64-bit write to the register at @offset in tile to which @gt belongs.
*/
-void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val)
+void xe_mmio_gt_write64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint64_t val)
{
- return xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
- val);
+ return xe_mmio_tile_write64(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset, val);
}
/**
* xe_mmio_ggtt_read:
* @mmio: xe mmio structure for IO operations
- * @gt: gt id
- * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
+ * @tile: tile id
+ * @offset: PTE offset from the beginning of GGTT in @tile
*
- * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
+ * Read of GGTT PTE at GGTT @offset in the @tile.
*
* Returns:
* The value read from the register.
*/
-xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t offset)
+xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
{
- return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
+ return xe_mmio_tile_read64(mmio, tile, offset + GGTT_OFFSET_IN_TILE);
}
/**
* xe_mmio_ggtt_write:
* @mmio: xe mmio structure for IO operations
- * @gt: gt id
- * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
+ * @tile: tile id
+ * @offset: PTE offset from the beginning of GGTT in @tile
* @pte: PTE value to write
*
- * Write PTE value at GGTT @offset in tile to which @gt belongs.
+ * Write PTE value at GGTT @offset in the @tile.
*/
-void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset, xe_ggtt_pte_t pte)
+void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, xe_ggtt_pte_t pte)
{
- return xe_mmio_gt_write64(mmio, gt, offset + GGTT_OFFSET_IN_TILE, pte);
+ return xe_mmio_tile_write64(mmio, tile, offset + GGTT_OFFSET_IN_TILE, pte);
}
diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
index f144d4b53..f15017c96 100644
--- a/lib/xe/xe_mmio.h
+++ b/lib/xe/xe_mmio.h
@@ -29,13 +29,17 @@ uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t offset);
void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, uint32_t val);
void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val);
-uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset);
-uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset);
-
-void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val);
-void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val);
-
-xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
-void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
+uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset);
+uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset);
+void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint32_t val);
+void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint64_t val);
+
+uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset);
+uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset);
+void xe_mmio_gt_write32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint32_t val);
+void xe_mmio_gt_write64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint64_t val);
+
+xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
+void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
#endif /* XE_MMIO_H */
diff --git a/lib/xe/xe_sriov_provisioning.c b/lib/xe/xe_sriov_provisioning.c
index ff9d1f7d2..2ca73d2ef 100644
--- a/lib/xe/xe_sriov_provisioning.c
+++ b/lib/xe/xe_sriov_provisioning.c
@@ -90,7 +90,7 @@ static int append_range(struct xe_sriov_provisioned_range **ranges,
/**
* xe_sriov_find_ggtt_provisioned_pte_offsets - Find GGTT provisioned PTE offsets
* @pf_fd: File descriptor for the Physical Function
- * @gt: GT identifier
+ * @tile: Tile id
* @mmio: Pointer to the MMIO structure
* @ranges: Pointer to the array of provisioned ranges
* @nr_ranges: Pointer to the number of provisioned ranges
@@ -106,7 +106,7 @@ static int append_range(struct xe_sriov_provisioned_range **ranges,
*
* Returns 0 on success, or a negative error code on failure.
*/
-int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio *mmio,
+int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile, struct xe_mmio *mmio,
struct xe_sriov_provisioned_range **ranges,
unsigned int *nr_ranges)
{
@@ -122,7 +122,7 @@ int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio
for (uint32_t offset = START_PTE_OFFSET; offset < MAX_PTE_OFFSET;
offset += sizeof(xe_ggtt_pte_t)) {
- pte = xe_mmio_ggtt_read(mmio, gt, offset);
+ pte = xe_mmio_ggtt_read(mmio, tile, offset);
vf_id = (pte & vfid_mask) >> GGTT_PTE_VFID_SHIFT;
if (vf_id != current_vf_id) {
diff --git a/lib/xe/xe_sriov_provisioning.h b/lib/xe/xe_sriov_provisioning.h
index e1a9d0a63..1e1dca866 100644
--- a/lib/xe/xe_sriov_provisioning.h
+++ b/lib/xe/xe_sriov_provisioning.h
@@ -92,7 +92,7 @@ struct xe_sriov_provisioned_range {
const char *xe_sriov_shared_res_to_string(enum xe_sriov_shared_res res);
bool xe_sriov_is_shared_res_provisionable(int pf, enum xe_sriov_shared_res res, unsigned int gt);
-int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio *mmio,
+int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile, struct xe_mmio *mmio,
struct xe_sriov_provisioned_range **ranges,
unsigned int *nr_ranges);
const char *xe_sriov_shared_res_attr_name(enum xe_sriov_shared_res res,
diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
index aabbd8c05..59e4d215c 100644
--- a/tests/intel/xe_sriov_flr.c
+++ b/tests/intel/xe_sriov_flr.c
@@ -493,20 +493,20 @@ struct ggtt_data {
static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
{
- return xe_mmio_ggtt_read(mmio, gt, pte_offset);
+ return xe_mmio_ggtt_read(mmio, 0, pte_offset);
}
static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
{
- xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
+ xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
}
static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
{
- xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
+ xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
/* force flush by read some MMIO register */
- xe_mmio_gt_read32(mmio, gt, GEN12_VF_CAP_REG);
+ xe_mmio_tile_read32(mmio, 0, GEN12_VF_CAP_REG);
}
static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
@@ -548,7 +548,7 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
igt_assert(gdata->pte_offsets);
- ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, gt, gdata->mmio,
+ ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, 0, gdata->mmio,
&ranges, &nr_ranges);
if (ret) {
set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 2/3] lib/xe_mmio: Add init flag and helper to check initialization
2025-10-20 16:26 [PATCH v1 0/3] Multi-tile support for xe_sriov_flr and other MMIO improvements Piórkowski, Piotr
2025-10-20 16:26 ` [PATCH v1 1/3] lib/xe_mmio: Introduce tile-level XE MMIO access helpers Piórkowski, Piotr
@ 2025-10-20 16:26 ` Piórkowski, Piotr
2025-10-22 11:55 ` Sokolowski, Jan
2025-10-20 16:26 ` [PATCH v1 3/3] tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices Piórkowski, Piotr
` (5 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Piórkowski, Piotr @ 2025-10-20 16:26 UTC (permalink / raw)
To: igt-dev; +Cc: Piotr Piórkowski, Lukasz Laguna, Marcin Bernatowicz
From: Piotr Piórkowski <piotr.piorkowski@intel.com>
Track MMIO initialization state via a new `init` flag and expose it
through xe_mmio_is_initialized().
Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
---
lib/xe/xe_mmio.c | 14 ++++++++++++++
lib/xe/xe_mmio.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
index 8bc446fb9..43aa354ff 100644
--- a/lib/xe/xe_mmio.c
+++ b/lib/xe/xe_mmio.c
@@ -25,6 +25,7 @@ void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio)
intel_register_access_init(&mmio->intel_mmio, pci_dev, false);
mmio->fd = pf_fd;
+ mmio->init = true;
}
/**
@@ -39,6 +40,18 @@ void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio)
xe_mmio_vf_access_init(pf_fd, 0, mmio);
}
+/**
+ * xe_mmio_is_initialized:
+ * @mmio: xe mmio structure for IO operations
+ *
+ * Returns:
+ * Non-zero if the xe mmio structure is initialized.
+ */
+bool xe_mmio_is_initialized(const struct xe_mmio *mmio)
+{
+ return mmio->init;
+}
+
/**
* xe_mmio_access_fini:
* @mmio: xe mmio structure for IO operations
@@ -49,6 +62,7 @@ void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio)
void xe_mmio_access_fini(struct xe_mmio *mmio)
{
intel_register_access_fini(&mmio->intel_mmio);
+ mmio->init = false;
}
/**
diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
index f15017c96..1710a384f 100644
--- a/lib/xe/xe_mmio.h
+++ b/lib/xe/xe_mmio.h
@@ -16,11 +16,13 @@ typedef uint64_t xe_ggtt_pte_t;
struct xe_mmio {
int fd;
+ bool init;
struct intel_mmio_data intel_mmio;
};
void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio);
void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio);
+bool xe_mmio_is_initialized(const struct xe_mmio *mmio);
void xe_mmio_access_fini(struct xe_mmio *mmio);
uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t offset);
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 3/3] tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices
2025-10-20 16:26 [PATCH v1 0/3] Multi-tile support for xe_sriov_flr and other MMIO improvements Piórkowski, Piotr
2025-10-20 16:26 ` [PATCH v1 1/3] lib/xe_mmio: Introduce tile-level XE MMIO access helpers Piórkowski, Piotr
2025-10-20 16:26 ` [PATCH v1 2/3] lib/xe_mmio: Add init flag and helper to check initialization Piórkowski, Piotr
@ 2025-10-20 16:26 ` Piórkowski, Piotr
2025-10-23 10:43 ` Bernatowicz, Marcin
` (2 more replies)
2025-10-21 2:23 ` ✓ i915.CI.BAT: success for Multi-tile support for xe_sriov_flr and other MMIO improvements Patchwork
` (4 subsequent siblings)
7 siblings, 3 replies; 14+ messages in thread
From: Piórkowski, Piotr @ 2025-10-20 16:26 UTC (permalink / raw)
To: igt-dev; +Cc: Piotr Piórkowski, Lukasz Laguna, Marcin Bernatowicz
From: Piotr Piórkowski <piotr.piorkowski@intel.com>
Let's introduce tile-level iteration and per-tile resource management
for GGTT, LMEM, and register subchecks.
Key updates:
- Add xe_number_tiles() and xe_tile_get_main_gt_id() helpers.
- Introduce xe_for_each_tile() macro for tile iteration.
- Refactor subcheck callbacks to include tile-aware arguments.
- Replace GT-based logic with per-tile handling for GGTT and LMEM.
Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
---
lib/xe/xe_query.c | 45 ++++
lib/xe/xe_query.h | 6 +
tests/intel/xe_sriov_flr.c | 513 ++++++++++++++++++++-----------------
3 files changed, 334 insertions(+), 230 deletions(-)
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index a89e0b980..14677e862 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -515,6 +515,22 @@ unsigned int xe_dev_max_gt(int fd)
return igt_fls(xe_dev->gt_mask) - 1;
}
+/**
+ * xe_number_tiles
+ * @fd: xe device fd
+ *
+ * Return number of tiles for xe device fd.
+ */
+uint8_t xe_number_tiles(int fd)
+{
+ struct xe_device *xe_dev;
+
+ xe_dev = find_in_cache(fd);
+ igt_assert(xe_dev);
+
+ return (uint8_t)__builtin_popcountll(xe_dev->tile_mask);
+}
+
/**
* all_memory_regions:
* @fd: xe device fd
@@ -995,6 +1011,35 @@ uint16_t xe_gt_get_tile_id(int fd, int gt)
return xe_dev->gt_list->gt_list[gt].tile_id;
}
+/**
+ * xe_tile_get_main_gt_id:
+ * @fd: xe device fd
+ * @tile: tile id
+ *
+ * Returns main GT ID for given @tile.
+ */
+uint16_t xe_tile_get_main_gt_id(int fd, uint8_t tile)
+{
+ struct xe_device *xe_dev;
+ int gt_id = -1;
+
+ xe_dev = find_in_cache(fd);
+ igt_assert(xe_dev);
+
+ for (int i = 0; i < xe_dev->gt_list->num_gt; i++) {
+ const struct drm_xe_gt *gt_data = &xe_dev->gt_list->gt_list[i];
+
+ if (gt_data->tile_id == tile && gt_data->type == DRM_XE_QUERY_GT_TYPE_MAIN) {
+ gt_id = gt_data->gt_id;
+ break;
+ }
+ }
+
+ igt_assert_f(gt_id >= 0, "No main GT found for tile %d\n", tile);
+
+ return gt_id;
+}
+
/**
* xe_hwconfig_lookup_value:
* @fd: xe device fd
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 715b64e2f..e1ed61675 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -86,6 +86,10 @@ struct xe_device {
for (uint64_t igt_unique(__mask) = xe_device_get(__fd)->gt_mask; \
__gt = ffsll(igt_unique(__mask)) - 1, igt_unique(__mask) != 0; \
igt_unique(__mask) &= ~(1ull << __gt))
+#define xe_for_each_tile(__fd, __tile) \
+ for (uint8_t igt_unique(__mask) = xe_device_get(__fd)->tile_mask; \
+ __tile = ffsll(igt_unique(__mask)) - 1, igt_unique(__mask) != 0; \
+ igt_unique(__mask) &= ~(1ull << __tile))
#define xe_for_each_mem_region(__fd, __memreg, __r) \
for (uint64_t igt_unique(__i) = 0; igt_unique(__i) < igt_fls(__memreg); igt_unique(__i)++) \
for_if(__r = (__memreg & (1ull << igt_unique(__i))))
@@ -101,6 +105,7 @@ struct xe_device {
unsigned int xe_number_gt(int fd);
unsigned int xe_dev_max_gt(int fd);
+uint8_t xe_number_tiles(int fd);
uint64_t all_memory_regions(int fd);
uint64_t system_memory(int fd);
const struct drm_xe_gt *drm_xe_get_gt(struct xe_device *xe_dev, int gt_id);
@@ -135,6 +140,7 @@ uint16_t xe_gt_type(int fd, int gt);
bool xe_is_media_gt(int fd, int gt);
bool xe_is_main_gt(int fd, int gt);
uint16_t xe_gt_get_tile_id(int fd, int gt);
+uint16_t xe_tile_get_main_gt_id(int fd, uint8_t tile);
uint32_t *xe_hwconfig_lookup_value(int fd, enum intel_hwconfig attribute, uint32_t *len);
int xe_query_pxp_status(int fd);
int xe_wait_for_pxp_init(int fd);
diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
index 59e4d215c..b58545384 100644
--- a/tests/intel/xe_sriov_flr.c
+++ b/tests/intel/xe_sriov_flr.c
@@ -53,7 +53,9 @@
IGT_TEST_DESCRIPTION("Xe tests for SR-IOV VF FLR (Functional Level Reset)");
-const char *SKIP_REASON = "SKIP";
+#define STOP_REASON_ABORT "ABORT"
+#define STOP_REASON_FAIL "FAIL"
+#define STOP_REASON_SKIP "SKIP"
/**
* struct subcheck_data - Base structure for subcheck data.
@@ -66,8 +68,6 @@ const char *SKIP_REASON = "SKIP";
* @pf_fd: File descriptor for the Physical Function.
* @num_vfs: Number of Virtual Functions (VFs) enabled and under test. This count is
* used to iterate over and manage the VFs during the testing process.
- * @gt: GT under test. This identifier is used to specify a particular GT
- * for operations when GT-specific testing is required.
* @stop_reason: Pointer to a string that indicates why a subcheck should skip or fail.
* This field is crucial for controlling the flow of subcheck execution.
* If set, it should prevent further execution of the current subcheck,
@@ -79,12 +79,11 @@ const char *SKIP_REASON = "SKIP";
* Example usage:
* A typical use of this structure involves initializing it with the necessary test setup
* parameters, checking the `stop_reason` field before proceeding with each subcheck operation,
- * and using `pf_fd`, `num_vfs`, and `gt` as needed based on the specific subcheck requirements.
+ * and using `pf_fd` and `num_vfs` as needed based on the specific subcheck requirements.
*/
struct subcheck_data {
int pf_fd;
- int num_vfs;
- int gt;
+ unsigned int num_vfs;
char *stop_reason;
};
@@ -100,37 +99,48 @@ struct subcheck_data {
*
* @name: Name of the subcheck operation, used for identification and reporting.
*
+ * @alloc: Allocate resources for the subcheck.
+ * @param data: Shared data needed for allocation.
+ * @param num_tiles: Number of tiles in the device (for multi-tile devices).
+ * @param num_vfs: Number of VFs enabled on the PF.
+ *
* @init: Initialize the subcheck environment.
* Sets up the initial state required for the subcheck, including preparing
* resources and ensuring the system is ready for testing.
* @param data: Shared data needed for initialization.
+ * @param tile: Tile index for multi-tile devices.
*
* @prepare_vf: Prepare subcheck data for a specific VF.
* Called for each VF before FLR is performed. It might involve marking
* specific memory regions or setting up PTE addresses.
- * @param vf_id: Identifier of the VF being prepared.
* @param data: Shared common data.
+ * @param tile: Tile index for multi-tile devices.
+ * @param vf_id: Identifier of the VF being prepared.
*
* @verify_vf: Verify the state of a VF after FLR.
* Checks the VF's state post FLR to ensure the expected results,
* such as verifying that only the FLRed VF has its state reset.
+ * @param data: Shared common data.
+ * @param flr_vf_id: Identifier of the VF that underwent FLR.
+ *
* @param vf_id: Identifier of the VF to verify.
* @param flr_vf_id: Identifier of the VF that underwent FLR.
- * @param data: Shared common data.
*
* @cleanup: Clean up the subcheck environment.
* Releases resources and restores the system to its original state
* after the subchecks, ensuring no resource leaks and preparing the system
* for subsequent tests.
* @param data: Shared common data.
+ * @param num_tiles: Number of tiles in the device (for multi-tile devices).
*/
struct subcheck {
struct subcheck_data *data;
const char *name;
- void (*init)(struct subcheck_data *data);
- void (*prepare_vf)(int vf_id, struct subcheck_data *data);
- void (*verify_vf)(int vf_id, int flr_vf_id, struct subcheck_data *data);
- void (*cleanup)(struct subcheck_data *data);
+ void (*alloc)(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs);
+ void (*init)(struct subcheck_data *data, uint8_t tile);
+ void (*prepare_vf)(struct subcheck_data *data, uint8_t tile, int vf_id);
+ void (*verify_vf)(struct subcheck_data *data, uint8_t tile, int vf_id, int flr_vf_id);
+ void (*cleanup)(struct subcheck_data *data, uint8_t num_tiles);
};
__attribute__((format(printf, 3, 0)))
@@ -154,12 +164,12 @@ static void set_stop_reason_v(struct subcheck_data *data, const char *prefix,
}
__attribute__((format(printf, 2, 3)))
-static void set_skip_reason(struct subcheck_data *data, const char *format, ...)
+static void set_abort_reason(struct subcheck_data *data, const char *format, ...)
{
va_list args;
va_start(args, format);
- set_stop_reason_v(data, SKIP_REASON, format, args);
+ set_stop_reason_v(data, STOP_REASON_ABORT, format, args);
va_end(args);
}
@@ -169,7 +179,17 @@ static void set_fail_reason(struct subcheck_data *data, const char *format, ...)
va_list args;
va_start(args, format);
- set_stop_reason_v(data, "FAIL", format, args);
+ set_stop_reason_v(data, STOP_REASON_FAIL, format, args);
+ va_end(args);
+}
+
+__attribute__((format(printf, 2, 3)))
+static void set_skip_reason(struct subcheck_data *data, const char *format, ...)
+{
+ va_list args;
+
+ va_start(args, format);
+ set_stop_reason_v(data, STOP_REASON_SKIP, format, args);
va_end(args);
}
@@ -197,7 +217,7 @@ static bool no_subchecks_can_proceed(struct subcheck *checks, int num_checks)
static bool is_subcheck_skipped(struct subcheck *subcheck)
{
return subcheck->data && subcheck->data->stop_reason &&
- !strncmp(SKIP_REASON, subcheck->data->stop_reason, strlen(SKIP_REASON));
+ !strncmp(STOP_REASON_SKIP, subcheck->data->stop_reason, strlen(STOP_REASON_SKIP));
}
static void subchecks_report_results(struct subcheck *checks, int num_checks)
@@ -269,10 +289,12 @@ typedef int (*flr_exec_strategy)(int pf_fd, int num_vfs,
* A timeout is used to wait for FLR operations to complete.
*/
static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
- int num_checks, flr_exec_strategy exec_strategy)
+ size_t num_checks, flr_exec_strategy exec_strategy)
{
const int wait_flr_ms = 200;
int i, vf_id, flr_vf_id = -1;
+ uint8_t num_tiles = xe_number_tiles(pf_fd);
+ uint8_t tile;
igt_sriov_disable_driver_autoprobe(pf_fd);
igt_sriov_enable_vfs(pf_fd, num_vfs);
@@ -284,12 +306,19 @@ static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
goto disable_vfs;
for (i = 0; i < num_checks; ++i)
- checks[i].init(checks[i].data);
+ if (checks[i].alloc)
+ checks[i].alloc(checks[i].data, num_tiles, num_vfs);
- for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
+ xe_for_each_tile(pf_fd, tile) {
for (i = 0; i < num_checks; ++i)
if (subcheck_can_proceed(&checks[i]))
- checks[i].prepare_vf(vf_id, checks[i].data);
+ checks[i].init(checks[i].data, tile);
+
+ for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
+ for (i = 0; i < num_checks; ++i)
+ if (subcheck_can_proceed(&checks[i]))
+ checks[i].prepare_vf(checks[i].data, tile, vf_id);
+ }
if (no_subchecks_can_proceed(checks, num_checks))
goto cleanup;
@@ -299,7 +328,7 @@ static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
cleanup:
for (i = 0; i < num_checks; ++i)
- checks[i].cleanup(checks[i].data);
+ checks[i].cleanup(checks[i].data, num_tiles);
disable_vfs:
igt_sriov_disable_vfs(pf_fd);
@@ -315,6 +344,7 @@ static int execute_sequential_flr(int pf_fd, int num_vfs,
const int wait_flr_ms)
{
int i, vf_id, flr_vf_id = 1;
+ uint8_t tile;
do {
if (igt_warn_on_f(!igt_sriov_device_reset(pf_fd, flr_vf_id),
@@ -324,16 +354,20 @@ static int execute_sequential_flr(int pf_fd, int num_vfs,
/* Assume FLR is finished after wait_flr_ms */
usleep(wait_flr_ms * 1000);
- for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
- for (i = 0; i < num_checks; ++i)
- if (subcheck_can_proceed(&checks[i]))
- checks[i].verify_vf(vf_id, flr_vf_id, checks[i].data);
-
- /* Reinitialize test data for the FLRed VF */
- if (flr_vf_id < num_vfs)
- for (i = 0; i < num_checks; ++i)
- if (subcheck_can_proceed(&checks[i]))
- checks[i].prepare_vf(flr_vf_id, checks[i].data);
+ xe_for_each_tile(pf_fd, tile) {
+ for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
+ for (i = 0; i < num_checks; ++i)
+ if (subcheck_can_proceed(&checks[i]))
+ checks[i].verify_vf(checks[i].data, tile, vf_id,
+ flr_vf_id);
+
+ /* Reinitialize test data for the FLRed VF */
+ if (flr_vf_id < num_vfs)
+ for (i = 0; i < num_checks; ++i)
+ if (subcheck_can_proceed(&checks[i]))
+ checks[i].prepare_vf(checks[i].data, tile,
+ flr_vf_id);
+ }
if (no_subchecks_can_proceed(checks, num_checks))
break;
@@ -431,15 +465,19 @@ cleanup_threads:
/* Verify results */
for (i = 0; i < created_threads; ++i) {
+ uint8_t tile;
+
vf_id = thread_data[i].vf_id;
/* Skip already checked VF or if the FLR initiation failed */
if (vf_id == last_vf_id || thread_data[i].result != 0)
continue;
- for (k = 0; k < num_checks; ++k)
- if (subcheck_can_proceed(&checks[k]))
- checks[k].verify_vf(vf_id, vf_id, checks[k].data);
+ xe_for_each_tile(pf_fd, tile) {
+ for (k = 0; k < num_checks; ++k)
+ if (subcheck_can_proceed(&checks[k]))
+ checks[k].verify_vf(checks[k].data, tile, vf_id, vf_id);
+ }
if (no_subchecks_can_proceed(checks, num_checks))
break;
@@ -470,8 +508,8 @@ static int execute_parallel_flr_twice(int pf_fd, int num_vfs,
#define GGTT_PTE_ADDR_SHIFT 12
struct ggtt_ops {
- void (*set_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
- xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
+ void (*set_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
+ xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
};
struct ggtt_provisioned_offset_range {
@@ -486,74 +524,89 @@ struct ggtt_provisioned_offset_range {
struct ggtt_data {
struct subcheck_data base;
- struct ggtt_provisioned_offset_range *pte_offsets;
+ struct ggtt_provisioned_offset_range **pte_offsets;
struct xe_mmio *mmio;
struct ggtt_ops ggtt;
};
-static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
+static void ggtt_subcheck_alloc(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs)
{
- return xe_mmio_ggtt_read(mmio, 0, pte_offset);
+ struct ggtt_data *gdata = (struct ggtt_data *)data;
+
+ gdata->pte_offsets = calloc(num_tiles, sizeof(*gdata->pte_offsets));
+ if (!gdata->pte_offsets) {
+ set_abort_reason(data, "Failed to allocate memory for pte_offsets array\n");
+ return;
+ }
+
+ for (uint8_t tile = 0; tile < num_tiles; tile++) {
+ gdata->pte_offsets[tile] = calloc(num_vfs + 1, sizeof(**gdata->pte_offsets));
+ if (!gdata->pte_offsets[tile]) {
+ set_abort_reason(data, "Failed to allocate memory for pte_offsets[%u]\n",
+ tile);
+ return;
+ }
+ }
}
-static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
+static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset)
{
- xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
+ return xe_mmio_ggtt_read(mmio, tile, pte_offset);
}
-static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
+static void intel_set_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset,
+ xe_ggtt_pte_t pte)
{
- xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
+ xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
+}
+
+static void intel_mtl_set_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset,
+ xe_ggtt_pte_t pte)
+{
+ xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
/* force flush by read some MMIO register */
- xe_mmio_tile_read32(mmio, 0, GEN12_VF_CAP_REG);
+ xe_mmio_tile_read32(mmio, tile, GEN12_VF_CAP_REG);
}
-static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
- uint8_t gpa, xe_ggtt_pte_t *out)
+static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
+ uint32_t pte_offset, uint8_t gpa, xe_ggtt_pte_t *out)
{
xe_ggtt_pte_t pte;
- pte = ggtt->get_pte(mmio, gt, pte_offset);
+ pte = ggtt->get_pte(mmio, tile, pte_offset);
pte &= ~GGTT_PTE_TEST_FIELD_MASK;
pte |= ((xe_ggtt_pte_t)gpa << GGTT_PTE_ADDR_SHIFT) & GGTT_PTE_TEST_FIELD_MASK;
- ggtt->set_pte(mmio, gt, pte_offset, pte);
- *out = ggtt->get_pte(mmio, gt, pte_offset);
+ ggtt->set_pte(mmio, tile, pte_offset, pte);
+ *out = ggtt->get_pte(mmio, tile, pte_offset);
return *out == pte;
}
-static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
- uint8_t expected_gpa, xe_ggtt_pte_t *out)
+static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
+ uint32_t pte_offset, uint8_t expected_gpa, xe_ggtt_pte_t *out)
{
uint8_t val;
- *out = ggtt->get_pte(mmio, gt, pte_offset);
+ *out = ggtt->get_pte(mmio, tile, pte_offset);
val = (uint8_t)((*out & GGTT_PTE_TEST_FIELD_MASK) >> GGTT_PTE_ADDR_SHIFT);
return val == expected_gpa;
}
-static bool is_intel_mmio_initialized(const struct intel_mmio_data *mmio)
-{
- return mmio->dev;
-}
-
-static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
+static void populate_ggtt_pte_offsets(struct ggtt_data *gdata, uint8_t tile)
{
int ret, pf_fd = gdata->base.pf_fd, num_vfs = gdata->base.num_vfs;
struct xe_sriov_provisioned_range *ranges;
- unsigned int nr_ranges, gt = gdata->base.gt;
+ unsigned int nr_ranges;
- gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
- igt_assert(gdata->pte_offsets);
-
- ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, 0, gdata->mmio,
+ ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, tile, gdata->mmio,
&ranges, &nr_ranges);
if (ret) {
- set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
- gt, ret);
- return -1;
+ set_abort_reason(&gdata->base,
+ "Tile%u: Failed to scan GGTT PTE offset ranges (%d)\n",
+ tile, ret);
+ return;
}
for (unsigned int i = 0; i < nr_ranges; ++i) {
@@ -563,46 +616,38 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
continue;
if (vf_id < 1 || vf_id > num_vfs) {
- set_skip_reason(&gdata->base, "Unexpected VF%u at range entry %u [%#" PRIx64 "-%#" PRIx64 "], num_vfs=%u\n",
- vf_id, i, ranges[i].start, ranges[i].end, num_vfs);
- free(ranges);
- return -1;
+ set_abort_reason(&gdata->base,
+ "Tile%u: Unexpected VF%u at range entry %u [%#" PRIx64 "-%#" PRIx64 "], num_vfs=%u\n",
+ tile, vf_id, i, ranges[i].start, ranges[i].end, num_vfs);
+ goto out;
}
- if (gdata->pte_offsets[vf_id].end) {
- set_skip_reason(&gdata->base, "Duplicate GGTT PTE offset range for VF%u\n",
- vf_id);
- free(ranges);
- return -1;
+ if (gdata->pte_offsets[tile][vf_id].end) {
+ set_abort_reason(&gdata->base,
+ "Tile%u: Duplicate GGTT PTE offset range for VF%u\n",
+ tile, vf_id);
+ goto out;
}
- gdata->pte_offsets[vf_id].start = ranges[i].start;
- gdata->pte_offsets[vf_id].end = ranges[i].end;
+ gdata->pte_offsets[tile][vf_id].start = ranges[i].start;
+ gdata->pte_offsets[tile][vf_id].end = ranges[i].end;
}
- free(ranges);
-
for (int vf_id = 1; vf_id <= num_vfs; ++vf_id)
- if (!gdata->pte_offsets[vf_id].end) {
- set_skip_reason(&gdata->base,
- "Failed to find VF%u provisioned GGTT PTE offset range\n",
- vf_id);
- return -1;
+ if (!gdata->pte_offsets[tile][vf_id].end) {
+ set_abort_reason(&gdata->base,
+ "Tile%u: Failed to find VF%u provisioned GGTT PTE offset range\n",
+ tile, vf_id);
+ goto out;
}
-
- return 0;
+out:
+ free(ranges);
}
-static void ggtt_subcheck_init(struct subcheck_data *data)
+static void ggtt_subcheck_init(struct subcheck_data *data, uint8_t tile)
{
struct ggtt_data *gdata = (struct ggtt_data *)data;
- if (!xe_is_main_gt(data->pf_fd, data->gt)) {
- set_skip_reason(data, "GGTT provisioning not exposed on GT%d (non-MAIN)\n",
- data->gt);
- return;
- }
-
gdata->ggtt.get_pte = intel_get_pte;
if (IS_METEORLAKE(intel_get_drm_devid(data->pf_fd)))
gdata->ggtt.set_pte = intel_mtl_set_pte;
@@ -610,16 +655,16 @@ static void ggtt_subcheck_init(struct subcheck_data *data)
gdata->ggtt.set_pte = intel_set_pte;
if (gdata->mmio) {
- if (!is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
- xe_mmio_vf_access_init(data->pf_fd, 0 /*PF*/, gdata->mmio);
+ if (!xe_mmio_is_initialized(gdata->mmio))
+ xe_mmio_access_init(data->pf_fd, gdata->mmio);
- populate_ggtt_pte_offsets(gdata);
+ populate_ggtt_pte_offsets(gdata, tile);
} else {
- set_skip_reason(data, "xe_mmio is NULL\n");
+ set_abort_reason(data, "xe_mmio is NULL\n");
}
}
-static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
+static void ggtt_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
{
struct ggtt_data *gdata = (struct ggtt_data *)data;
xe_ggtt_pte_t pte;
@@ -628,22 +673,23 @@ static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
if (data->stop_reason)
return;
- igt_debug("Prepare gpa on VF%u offset range [%#x-%#x]\n", vf_id,
- gdata->pte_offsets[vf_id].start,
- gdata->pte_offsets[vf_id].end);
+ igt_debug("Tile%u: Prepare gpa on VF%u offset range [%#x-%#x]\n", tile, vf_id,
+ gdata->pte_offsets[tile][vf_id].start,
+ gdata->pte_offsets[tile][vf_id].end);
- for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
- if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
+ for_each_pte_offset(pte_offset, &gdata->pte_offsets[tile][vf_id]) {
+ if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, tile, pte_offset,
(uint8_t)vf_id, &pte)) {
set_skip_reason(data,
- "Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x\n",
- vf_id, pte, pte_offset);
+ "Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x on tile%u\n",
+ vf_id, pte, pte_offset, tile);
return;
}
}
}
-static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
+static void ggtt_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
+ int flr_vf_id)
{
struct ggtt_data *gdata = (struct ggtt_data *)data;
uint8_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
@@ -653,33 +699,62 @@ static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
if (data->stop_reason)
return;
- for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
- if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
+ for_each_pte_offset(pte_offset, &gdata->pte_offsets[tile][vf_id]) {
+ if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, tile, pte_offset,
expected, &pte)) {
set_fail_reason(data,
- "GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
- flr_vf_id, vf_id, pte, pte_offset);
+ "Tile%u: GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
+ tile, flr_vf_id, vf_id, pte, pte_offset);
return;
}
}
}
-static void ggtt_subcheck_cleanup(struct subcheck_data *data)
+static void ggtt_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
{
struct ggtt_data *gdata = (struct ggtt_data *)data;
- free(gdata->pte_offsets);
- if (gdata->mmio && is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
+ if (gdata->pte_offsets) {
+ for (uint8_t tile = 0; tile < num_tiles; tile++)
+ free(gdata->pte_offsets[tile]);
+ free(gdata->pte_offsets);
+ }
+
+ if (gdata->mmio && xe_mmio_is_initialized(gdata->mmio))
xe_mmio_access_fini(gdata->mmio);
}
-
struct lmem_data {
struct subcheck_data base;
- size_t *vf_lmem_size;
+ size_t **vf_lmem_size;
};
const size_t STEP = SZ_1M;
+static void lmem_subcheck_alloc(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs)
+{
+ struct lmem_data *ldata = (struct lmem_data *)data;
+
+ if (!xe_has_vram(data->pf_fd)) {
+ set_skip_reason(data, "No LMEM\n");
+ return;
+ }
+
+ ldata->vf_lmem_size = calloc(num_vfs + 1, sizeof(size_t *));
+ if (!ldata->vf_lmem_size) {
+ set_abort_reason(data, "Failed to allocate memory for vf_lmem_size array\n");
+ return;
+ }
+
+ for (uint8_t tile = 0; tile < num_tiles; tile++) {
+ ldata->vf_lmem_size[tile] = calloc(num_vfs + 1, sizeof(**ldata->vf_lmem_size));
+ if (!ldata->vf_lmem_size[tile]) {
+ set_abort_reason(data, "Failed to allocate memory for vf_lmem_size[%u]\n",
+ tile);
+ return;
+ }
+ }
+}
+
static bool lmem_write_pattern(struct vram_mapping *m, uint8_t value, size_t start, size_t step)
{
uint8_t read;
@@ -735,66 +810,51 @@ static bool lmem_mmap_write_munmap(int pf_fd, int vf_num, size_t length, char va
return result;
}
-static int populate_vf_lmem_sizes(struct subcheck_data *data)
+static void populate_vf_lmem_sizes(struct subcheck_data *data, uint8_t tile)
{
struct lmem_data *ldata = (struct lmem_data *)data;
+ unsigned int main_gt = xe_tile_get_main_gt_id(data->pf_fd, tile);
struct xe_sriov_provisioned_range *ranges;
- unsigned int nr_ranges, gt;
+ unsigned int nr_ranges;
int ret;
- ldata->vf_lmem_size = calloc(data->num_vfs + 1, sizeof(size_t));
- igt_assert(ldata->vf_lmem_size);
-
- xe_for_each_gt(data->pf_fd, gt) {
- if (!xe_is_main_gt(data->pf_fd, gt))
- continue;
-
- ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd,
- XE_SRIOV_SHARED_RES_LMEM,
- gt, &ranges, &nr_ranges);
- if (ret) {
- set_skip_reason(data, "Failed read %s on gt%u (%d)\n",
- xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
- gt, ret);
- return -1;
- }
-
- for (unsigned int i = 0; i < nr_ranges; ++i) {
- const unsigned int vf_id = ranges[i].vf_id;
+ ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd, XE_SRIOV_SHARED_RES_LMEM,
+ main_gt, &ranges, &nr_ranges);
+ if (ret) {
+ set_abort_reason(data, "Tile%u: Failed read %s on main GT (%d)\n", tile,
+ xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
+ ret);
+ return;
+ }
- igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
- /* Sum the allocation for vf_id (inclusive range) */
- ldata->vf_lmem_size[vf_id] += ranges[i].end - ranges[i].start + 1;
- }
+ for (unsigned int i = 0; i < nr_ranges; ++i) {
+ const unsigned int vf_id = ranges[i].vf_id;
- free(ranges);
+ igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
+ /* Sum the allocation for vf_id (inclusive range) */
+ ldata->vf_lmem_size[tile][vf_id] += ranges[i].end - ranges[i].start + 1;
}
+ free(ranges);
+
for (int vf_id = 1; vf_id <= data->num_vfs; ++vf_id)
- if (!ldata->vf_lmem_size[vf_id]) {
- set_skip_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
- return -1;
+ if (!ldata->vf_lmem_size[tile][vf_id]) {
+ set_abort_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
+ return;
}
- return 0;
+ return;
}
-static void lmem_subcheck_init(struct subcheck_data *data)
+static void lmem_subcheck_init(struct subcheck_data *data, uint8_t tile)
{
igt_assert_fd(data->pf_fd);
igt_assert(data->num_vfs);
- if (!xe_has_vram(data->pf_fd)) {
- set_skip_reason(data, "No LMEM\n");
- return;
- }
-
- if (populate_vf_lmem_sizes(data))
- /* skip reason set in populate_vf_lmem_sizes */
- return;
+ populate_vf_lmem_sizes(data, tile);
}
-static void lmem_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
+static void lmem_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
{
struct lmem_data *ldata = (struct lmem_data *)data;
@@ -804,12 +864,13 @@ static void lmem_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
igt_assert(vf_id > 0 && vf_id <= data->num_vfs);
if (!lmem_mmap_write_munmap(data->pf_fd, vf_id,
- ldata->vf_lmem_size[vf_id], vf_id)) {
- set_skip_reason(data, "LMEM write failed on VF%u\n", vf_id);
+ ldata->vf_lmem_size[tile][vf_id], vf_id)) {
+ set_abort_reason(data, "LMEM write failed on VF%u\n", vf_id);
}
}
-static void lmem_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
+static void lmem_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
+ int flr_vf_id)
{
struct lmem_data *ldata = (struct lmem_data *)data;
char expected = (vf_id == flr_vf_id) ? 0 : vf_id;
@@ -818,14 +879,14 @@ static void lmem_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
return;
if (!lmem_contains_expected_values(data->pf_fd, vf_id,
- ldata->vf_lmem_size[vf_id], expected)) {
+ ldata->vf_lmem_size[tile][vf_id], expected)) {
set_fail_reason(data,
"LMEM check after VF%u FLR failed on VF%u\n",
flr_vf_id, vf_id);
}
}
-static void lmem_subcheck_cleanup(struct subcheck_data *data)
+static void lmem_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
{
struct lmem_data *ldata = (struct lmem_data *)data;
@@ -839,12 +900,12 @@ static void lmem_subcheck_cleanup(struct subcheck_data *data)
struct regs_data {
struct subcheck_data base;
- struct intel_mmio_data *mmio;
+ struct xe_mmio *mmio;
uint32_t reg_addr;
int reg_count;
};
-static void regs_subcheck_init(struct subcheck_data *data)
+static void regs_subcheck_init(struct subcheck_data *data, uint8_t tile)
{
struct regs_data *rdata = (struct regs_data *)data;
@@ -854,7 +915,7 @@ static void regs_subcheck_init(struct subcheck_data *data)
}
}
-static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
+static void regs_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
{
struct regs_data *rdata = (struct regs_data *)data;
uint32_t reg;
@@ -863,32 +924,22 @@ static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
if (data->stop_reason)
return;
- if (!is_intel_mmio_initialized(&rdata->mmio[vf_id])) {
- struct pci_device *pci_dev = __igt_device_get_pci_device(data->pf_fd, vf_id);
-
- if (!pci_dev) {
- set_skip_reason(data, "No PCI device found for VF%u\n", vf_id);
- return;
- }
-
- if (intel_register_access_init(&rdata->mmio[vf_id], pci_dev, false)) {
- set_skip_reason(data, "Failed to get access to VF%u MMIO\n", vf_id);
- return;
- }
- }
+ if (!xe_mmio_is_initialized(&rdata->mmio[vf_id]))
+ xe_mmio_vf_access_init(data->pf_fd, vf_id, &rdata->mmio[vf_id]);
for (i = 0; i < rdata->reg_count; i++) {
reg = rdata->reg_addr + i * 4;
- intel_register_write(&rdata->mmio[vf_id], reg, vf_id);
- if (intel_register_read(&rdata->mmio[vf_id], reg) != vf_id) {
+ xe_mmio_tile_write32(&rdata->mmio[vf_id], tile, reg, vf_id);
+ if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != vf_id) {
set_skip_reason(data, "Registers write/read check failed on VF%u\n", vf_id);
return;
}
}
}
-static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
+static void regs_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
+ int flr_vf_id)
{
struct regs_data *rdata = (struct regs_data *)data;
uint32_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
@@ -901,7 +952,7 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
for (i = 0; i < rdata->reg_count; i++) {
reg = rdata->reg_addr + i * 4;
- if (intel_register_read(&rdata->mmio[vf_id], reg) != expected) {
+ if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != expected) {
set_fail_reason(data,
"Registers check after VF%u FLR failed on VF%u\n",
flr_vf_id, vf_id);
@@ -910,84 +961,86 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
}
}
-static void regs_subcheck_cleanup(struct subcheck_data *data)
+static void regs_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
{
struct regs_data *rdata = (struct regs_data *)data;
int i;
if (rdata->mmio)
for (i = 1; i <= data->num_vfs; ++i)
- if (is_intel_mmio_initialized(&rdata->mmio[i]))
- intel_register_access_fini(&rdata->mmio[i]);
+ if (xe_mmio_is_initialized(&rdata->mmio[i]))
+ xe_mmio_access_fini(&rdata->mmio[i]);
}
-static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
+static void clear_tests(const int pf_fd, const unsigned int num_vfs,
+ const flr_exec_strategy exec_strategy)
{
- struct xe_mmio xemmio = { };
- const unsigned int num_gts = xe_number_gt(pf_fd);
- struct ggtt_data gdata[num_gts];
+ struct subcheck_data base = { .pf_fd = pf_fd, .num_vfs = num_vfs };
+ struct xe_mmio *mmio = calloc(1 + num_vfs, sizeof(*mmio));
+ struct ggtt_data gdata = {
+ .base = base,
+ .mmio = mmio,
+ };
struct lmem_data ldata = {
- .base = { .pf_fd = pf_fd, .num_vfs = num_vfs }
+ .base = base,
};
- struct intel_mmio_data mmio[num_vfs + 1];
struct regs_data scratch_data = {
- .base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
+ .base = base,
.mmio = mmio,
.reg_addr = SCRATCH_REG,
.reg_count = SCRATCH_REG_COUNT
};
struct regs_data media_scratch_data = {
- .base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
+ .base = base,
.mmio = mmio,
.reg_addr = MED_SCRATCH_REG,
.reg_count = MED_SCRATCH_REG_COUNT
};
- const unsigned int num_checks = num_gts + 3;
- struct subcheck checks[num_checks];
- int i = 0, gt_id;
-
- memset(mmio, 0, sizeof(mmio));
-
- xe_for_each_gt(pf_fd, gt_id) {
- gdata[i] = (struct ggtt_data){
- .base = { .pf_fd = pf_fd, .num_vfs = num_vfs, .gt = gt_id },
- .mmio = &xemmio
- };
- checks[i] = (struct subcheck){
- .data = (struct subcheck_data *)&gdata[i],
+ struct subcheck checks[] = {
+ {
+ .data = (struct subcheck_data *)&gdata,
.name = "clear-ggtt",
+ .alloc = ggtt_subcheck_alloc,
.init = ggtt_subcheck_init,
.prepare_vf = ggtt_subcheck_prepare_vf,
.verify_vf = ggtt_subcheck_verify_vf,
.cleanup = ggtt_subcheck_cleanup
- };
- i++;
- }
- checks[i++] = (struct subcheck) {
- .data = (struct subcheck_data *)&ldata,
- .name = "clear-lmem",
- .init = lmem_subcheck_init,
- .prepare_vf = lmem_subcheck_prepare_vf,
- .verify_vf = lmem_subcheck_verify_vf,
- .cleanup = lmem_subcheck_cleanup };
- checks[i++] = (struct subcheck) {
- .data = (struct subcheck_data *)&scratch_data,
- .name = "clear-scratch-regs",
- .init = regs_subcheck_init,
- .prepare_vf = regs_subcheck_prepare_vf,
- .verify_vf = regs_subcheck_verify_vf,
- .cleanup = regs_subcheck_cleanup };
- checks[i++] = (struct subcheck) {
- .data = (struct subcheck_data *)&media_scratch_data,
- .name = "clear-media-scratch-regs",
- .init = regs_subcheck_init,
- .prepare_vf = regs_subcheck_prepare_vf,
- .verify_vf = regs_subcheck_verify_vf,
- .cleanup = regs_subcheck_cleanup
+ },
+ {
+ .data = (struct subcheck_data *)&ldata,
+ .name = "clear-lmem",
+ .alloc = lmem_subcheck_alloc,
+ .init = lmem_subcheck_init,
+ .prepare_vf = lmem_subcheck_prepare_vf,
+ .verify_vf = lmem_subcheck_verify_vf,
+ .cleanup = lmem_subcheck_cleanup
+ },
+ {
+ .data = (struct subcheck_data *)&scratch_data,
+ .name = "clear-scratch-regs",
+ .alloc = NULL,
+ .init = regs_subcheck_init,
+ .prepare_vf = regs_subcheck_prepare_vf,
+ .verify_vf = regs_subcheck_verify_vf,
+ .cleanup = regs_subcheck_cleanup
+ },
+ {
+ .data = (struct subcheck_data *)&media_scratch_data,
+ .name = "clear-media-scratch-regs",
+ .alloc = NULL,
+ .init = regs_subcheck_init,
+ .prepare_vf = regs_subcheck_prepare_vf,
+ .verify_vf = regs_subcheck_verify_vf,
+ .cleanup = regs_subcheck_cleanup
+ }
+
};
- igt_assert_eq(i, num_checks);
- verify_flr(pf_fd, num_vfs, checks, num_checks, exec_strategy);
+ igt_abort_on_f(!mmio, "Failed to allocate memory for mmio array\n");
+
+ verify_flr(pf_fd, num_vfs, checks, ARRAY_SIZE(checks), exec_strategy);
+
+ free(mmio);
}
igt_main
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✓ i915.CI.BAT: success for Multi-tile support for xe_sriov_flr and other MMIO improvements
2025-10-20 16:26 [PATCH v1 0/3] Multi-tile support for xe_sriov_flr and other MMIO improvements Piórkowski, Piotr
` (2 preceding siblings ...)
2025-10-20 16:26 ` [PATCH v1 3/3] tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices Piórkowski, Piotr
@ 2025-10-21 2:23 ` Patchwork
2025-10-21 4:20 ` ✓ Xe.CI.BAT: " Patchwork
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-10-21 2:23 UTC (permalink / raw)
To: Piórkowski, Piotr; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 8623 bytes --]
== Series Details ==
Series: Multi-tile support for xe_sriov_flr and other MMIO improvements
URL : https://patchwork.freedesktop.org/series/156216/
State : success
== Summary ==
CI Bug Log - changes from IGT_8594 -> IGTPW_13923
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/index.html
Participating hosts (44 -> 44)
------------------------------
Additional (1): bat-twl-1
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_13923 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@dmabuf@all-tests:
- bat-apl-1: [PASS][1] -> [ABORT][2] ([i915#12904]) +1 other test abort
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/bat-apl-1/igt@dmabuf@all-tests.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-apl-1/igt@dmabuf@all-tests.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-twl-1: NOTRUN -> [SKIP][3] ([i915#10213] / [i915#11671]) +3 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_tiled_pread_basic:
- bat-twl-1: NOTRUN -> [SKIP][4] ([i915#11031])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-twl-1: NOTRUN -> [SKIP][5] ([i915#10209] / [i915#11681])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-9: [PASS][6] -> [DMESG-FAIL][7] ([i915#12061]) +1 other test dmesg-fail
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
* igt@intel_hwmon@hwmon-read:
- bat-twl-1: NOTRUN -> [SKIP][8] ([i915#7707]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@intel_hwmon@hwmon-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-twl-1: NOTRUN -> [SKIP][9] ([i915#11030] / [i915#11731]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-twl-1: NOTRUN -> [SKIP][10] ([i915#9886])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-twl-1: NOTRUN -> [SKIP][11] ([i915#11032])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@psr-primary-mmap-gtt:
- fi-bsw-n3050: NOTRUN -> [SKIP][12] +21 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/fi-bsw-n3050/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-twl-1: NOTRUN -> [SKIP][13] ([i915#8809])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-twl-1: NOTRUN -> [SKIP][14] ([i915#10212] / [i915#3708])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- bat-twl-1: NOTRUN -> [SKIP][15] ([i915#10214] / [i915#3708])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-twl-1: NOTRUN -> [SKIP][16] ([i915#10216] / [i915#3708])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-twl-1/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_module_load@load:
- bat-mtlp-9: [DMESG-WARN][17] ([i915#13494]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/bat-mtlp-9/igt@i915_module_load@load.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-mtlp-9/igt@i915_module_load@load.html
* igt@i915_selftest@live:
- bat-mtlp-8: [DMESG-FAIL][19] ([i915#12061]) -> [PASS][20] +1 other test pass
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/bat-mtlp-8/igt@i915_selftest@live.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-mtlp-8/igt@i915_selftest@live.html
- bat-arlh-3: [INCOMPLETE][21] ([i915#14764] / [i915#14818] / [i915#14837]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/bat-arlh-3/igt@i915_selftest@live.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-arlh-3/igt@i915_selftest@live.html
* igt@i915_selftest@live@active:
- bat-arlh-3: [INCOMPLETE][23] -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/bat-arlh-3/igt@i915_selftest@live@active.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-arlh-3/igt@i915_selftest@live@active.html
* igt@i915_selftest@live@workarounds:
- bat-arls-6: [DMESG-FAIL][25] ([i915#12061]) -> [PASS][26] +1 other test pass
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/bat-arls-6/igt@i915_selftest@live@workarounds.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-arls-6/igt@i915_selftest@live@workarounds.html
#### Warnings ####
* igt@i915_selftest@live:
- bat-atsm-1: [DMESG-FAIL][27] ([i915#12061] / [i915#14204]) -> [DMESG-FAIL][28] ([i915#12061] / [i915#13929])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/bat-atsm-1/igt@i915_selftest@live.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-atsm-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@mman:
- bat-atsm-1: [DMESG-FAIL][29] ([i915#14204]) -> [DMESG-FAIL][30] ([i915#13929])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/bat-atsm-1/igt@i915_selftest@live@mman.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/bat-atsm-1/igt@i915_selftest@live@mman.html
[i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
[i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
[i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
[i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
[i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
[i915#11030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11030
[i915#11031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11031
[i915#11032]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11032
[i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11731]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11731
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
[i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
[i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
[i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204
[i915#14764]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14764
[i915#14818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14818
[i915#14837]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14837
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_8594 -> IGTPW_13923
CI-20190529: 20190529
CI_DRM_17393: bee2d9e4308e4b888e2524014a246793233f75e8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_13923: 46d3e0a9b87bf7fdb50ff31d8394f9a401fac957 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8594: 8594
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/index.html
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^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Xe.CI.BAT: success for Multi-tile support for xe_sriov_flr and other MMIO improvements
2025-10-20 16:26 [PATCH v1 0/3] Multi-tile support for xe_sriov_flr and other MMIO improvements Piórkowski, Piotr
` (3 preceding siblings ...)
2025-10-21 2:23 ` ✓ i915.CI.BAT: success for Multi-tile support for xe_sriov_flr and other MMIO improvements Patchwork
@ 2025-10-21 4:20 ` Patchwork
2025-10-21 5:50 ` ✗ Xe.CI.Full: failure " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-10-21 4:20 UTC (permalink / raw)
To: Piórkowski, Piotr; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 1464 bytes --]
== Series Details ==
Series: Multi-tile support for xe_sriov_flr and other MMIO improvements
URL : https://patchwork.freedesktop.org/series/156216/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_8594_BAT -> XEIGTPW_13923_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in XEIGTPW_13923_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1:
- bat-adlp-7: [PASS][1] -> [DMESG-WARN][2] ([Intel XE#4543]) +1 other test dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
Build changes
-------------
* IGT: IGT_8594 -> IGTPW_13923
IGTPW_13923: 46d3e0a9b87bf7fdb50ff31d8394f9a401fac957 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8594: 8594
xe-3950-76e60b5ce41fc1bcabf7941a57303d541bffd6ad: 76e60b5ce41fc1bcabf7941a57303d541bffd6ad
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/index.html
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^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Xe.CI.Full: failure for Multi-tile support for xe_sriov_flr and other MMIO improvements
2025-10-20 16:26 [PATCH v1 0/3] Multi-tile support for xe_sriov_flr and other MMIO improvements Piórkowski, Piotr
` (4 preceding siblings ...)
2025-10-21 4:20 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-10-21 5:50 ` Patchwork
2025-10-21 12:15 ` Patchwork
2025-10-21 17:29 ` ✗ i915.CI.Full: " Patchwork
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-10-21 5:50 UTC (permalink / raw)
To: Piórkowski, Piotr; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 356 bytes --]
== Series Details ==
Series: Multi-tile support for xe_sriov_flr and other MMIO improvements
URL : https://patchwork.freedesktop.org/series/156216/
State : failure
== Summary ==
ERROR: The runconfig 'XEIGTPW_13923_FULL' does not exist in the database
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/index.html
[-- Attachment #2: Type: text/html, Size: 918 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Xe.CI.Full: failure for Multi-tile support for xe_sriov_flr and other MMIO improvements
2025-10-20 16:26 [PATCH v1 0/3] Multi-tile support for xe_sriov_flr and other MMIO improvements Piórkowski, Piotr
` (5 preceding siblings ...)
2025-10-21 5:50 ` ✗ Xe.CI.Full: failure " Patchwork
@ 2025-10-21 12:15 ` Patchwork
2025-10-21 17:29 ` ✗ i915.CI.Full: " Patchwork
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-10-21 12:15 UTC (permalink / raw)
To: Piórkowski, Piotr; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 57984 bytes --]
== Series Details ==
Series: Multi-tile support for xe_sriov_flr and other MMIO improvements
URL : https://patchwork.freedesktop.org/series/156216/
State : failure
== Summary ==
CI Bug Log - changes from XEIGT_8594_FULL -> XEIGTPW_13923_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with XEIGTPW_13923_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in XEIGTPW_13923_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 3)
------------------------------
Missing (1): shard-adlp
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in XEIGTPW_13923_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_sriov_flr@flr-each-isolation:
- shard-bmg: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-4/igt@xe_sriov_flr@flr-each-isolation.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@xe_sriov_flr@flr-each-isolation.html
Known issues
------------
Here are the changes found in XEIGTPW_13923_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- shard-dg2-set2: NOTRUN -> [SKIP][3] ([Intel XE#623])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-435/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
- shard-lnl: [PASS][4] -> [FAIL][5] ([Intel XE#6054]) +3 other tests fail
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-2/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
* igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1:
- shard-lnl: NOTRUN -> [FAIL][6] ([Intel XE#5993]) +3 other tests fail
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-4/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#2327]) +2 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-5/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#1124]) +6 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#607])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-8/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
- shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#607])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-436/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
- shard-lnl: NOTRUN -> [SKIP][11] ([Intel XE#1477])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-2/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-dg2-set2: NOTRUN -> [SKIP][12] ([Intel XE#1124]) +8 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-432/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2328])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-4/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-lnl: NOTRUN -> [SKIP][14] ([Intel XE#1124]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_bw@linear-tiling-2-displays-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#367])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-4/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-2-displays-3840x2160p:
- shard-dg2-set2: NOTRUN -> [SKIP][16] ([Intel XE#367])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-464/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][17] ([Intel XE#2887]) +9 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-8/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][18] ([Intel XE#2887]) +2 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#2652] / [Intel XE#787]) +17 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-1/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-c-dp-4:
- shard-dg2-set2: [PASS][20] -> [INCOMPLETE][21] ([Intel XE#3862])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-dg2-464/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-c-dp-4.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-463/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-c-dp-4.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#3432])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][23] ([Intel XE#455] / [Intel XE#787]) +9 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-435/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][24] ([Intel XE#787]) +34 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-435/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-b-dp-4.html
* igt@kms_cdclk@plane-scaling:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#2724])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-7/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_color@gamma:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#306]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-432/igt@kms_chamelium_color@gamma.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#2252]) +5 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-lnl: NOTRUN -> [SKIP][28] ([Intel XE#373])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-4/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm:
- shard-dg2-set2: NOTRUN -> [SKIP][29] ([Intel XE#373]) +3 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-463/igt@kms_chamelium_hpd@hdmi-hpd-storm.html
* igt@kms_content_protection@atomic:
- shard-bmg: NOTRUN -> [FAIL][30] ([Intel XE#1178]) +3 other tests fail
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@content-type-change:
- shard-lnl: NOTRUN -> [SKIP][31] ([Intel XE#3278]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-4/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@type1:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#2341]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-5/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2320]) +3 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-dg2-set2: NOTRUN -> [SKIP][34] ([Intel XE#308])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-432/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-128x42:
- shard-lnl: NOTRUN -> [SKIP][35] ([Intel XE#1424])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-bmg: [PASS][36] -> [SKIP][37] ([Intel XE#2291]) +3 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [PASS][38] -> [FAIL][39] ([Intel XE#4633]) +1 other test fail
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_display_modes@extended-mode-basic:
- shard-bmg: [PASS][40] -> [SKIP][41] ([Intel XE#4302])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-1/igt@kms_display_modes@extended-mode-basic.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#4354])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-8/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#2244])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-1/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-lnl: NOTRUN -> [SKIP][44] ([Intel XE#1421]) +2 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-4/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-bmg: [PASS][45] -> [SKIP][46] ([Intel XE#2316]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-4/igt@kms_flip@2x-plain-flip-fb-recreate.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-bmg: NOTRUN -> [FAIL][47] ([Intel XE#5408])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a3:
- shard-bmg: NOTRUN -> [FAIL][48] ([Intel XE#6266])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
- shard-lnl: NOTRUN -> [SKIP][49] ([Intel XE#1397] / [Intel XE#1745])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][50] ([Intel XE#1397])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#2293] / [Intel XE#2380])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#2293])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-lnl: NOTRUN -> [SKIP][53] ([Intel XE#1401] / [Intel XE#1745])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#1401])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][55] ([Intel XE#6312])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][56] ([Intel XE#6313])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#5390]) +8 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff:
- shard-dg2-set2: NOTRUN -> [SKIP][58] ([Intel XE#651]) +13 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff.html
- shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#651]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#2311]) +12 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render:
- shard-dg2-set2: NOTRUN -> [SKIP][61] ([Intel XE#6312]) +2 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#2313]) +18 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#2312]) +2 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][64] ([Intel XE#653]) +14 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
- shard-lnl: NOTRUN -> [SKIP][65] ([Intel XE#656]) +7 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@static-toggle-dpms:
- shard-bmg: [PASS][66] -> [SKIP][67] ([Intel XE#1503])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-8/igt@kms_hdr@static-toggle-dpms.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#2927])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-7/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_pipe_stress@stress-xrgb8888-yftiled:
- shard-dg2-set2: NOTRUN -> [SKIP][69] ([Intel XE#5624])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-432/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
* igt@kms_pm_backlight@basic-brightness:
- shard-dg2-set2: NOTRUN -> [SKIP][70] ([Intel XE#870])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-435/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_dc@dc6-psr:
- shard-lnl: [PASS][71] -> [FAIL][72] ([Intel XE#718])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-1/igt@kms_pm_dc@dc6-psr.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-5/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#2499])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-7/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][74] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][75] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-436/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
- shard-lnl: NOTRUN -> [SKIP][76] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [SKIP][77] ([Intel XE#1406] / [Intel XE#4608]) +2 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf:
- shard-lnl: NOTRUN -> [SKIP][78] ([Intel XE#1406] / [Intel XE#2893])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@fbc-pr-sprite-render:
- shard-lnl: NOTRUN -> [SKIP][79] ([Intel XE#1406])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@kms_psr@fbc-pr-sprite-render.html
* igt@kms_psr@fbc-psr2-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][80] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +3 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-434/igt@kms_psr@fbc-psr2-dpms.html
* igt@kms_psr@psr-basic:
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +8 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@kms_psr@psr-basic.html
* igt@kms_psr@psr2-primary-render:
- shard-bmg: NOTRUN -> [SKIP][82] ([Intel XE#1406] / [Intel XE#2234])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-1/igt@kms_psr@psr2-primary-render.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-bmg: NOTRUN -> [SKIP][83] ([Intel XE#2330])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-bmg: NOTRUN -> [SKIP][84] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
- shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#3414])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-463/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
- shard-lnl: NOTRUN -> [SKIP][86] ([Intel XE#3414] / [Intel XE#3904])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_tv_load_detect@load-detect:
- shard-bmg: NOTRUN -> [SKIP][87] ([Intel XE#2450])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-4/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vrr@flip-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][88] ([Intel XE#455]) +4 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-435/igt@kms_vrr@flip-dpms.html
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#1499])
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-5/igt@kms_vrr@flip-dpms.html
* igt@xe_compute_preempt@compute-preempt-many:
- shard-dg2-set2: NOTRUN -> [SKIP][90] ([Intel XE#6360]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-463/igt@xe_compute_preempt@compute-preempt-many.html
* igt@xe_copy_basic@mem-copy-linear-0x3fff:
- shard-dg2-set2: NOTRUN -> [SKIP][91] ([Intel XE#1123])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-466/igt@xe_copy_basic@mem-copy-linear-0x3fff.html
* igt@xe_copy_basic@mem-page-copy-17:
- shard-dg2-set2: NOTRUN -> [SKIP][92] ([Intel XE#5300])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-436/igt@xe_copy_basic@mem-page-copy-17.html
* igt@xe_eudebug@basic-vm-bind:
- shard-lnl: NOTRUN -> [SKIP][93] ([Intel XE#4837]) +1 other test skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-2/igt@xe_eudebug@basic-vm-bind.html
* igt@xe_eudebug@basic-vm-bind-metadata-discovery:
- shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#4837]) +9 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
* igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram:
- shard-dg2-set2: NOTRUN -> [SKIP][95] ([Intel XE#4837]) +3 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-432/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram.html
* igt@xe_evict@evict-threads-small-multi-vm:
- shard-lnl: NOTRUN -> [SKIP][96] ([Intel XE#688]) +2 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-5/igt@xe_evict@evict-threads-small-multi-vm.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
- shard-bmg: NOTRUN -> [SKIP][97] ([Intel XE#2322]) +6 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html
* igt@xe_exec_basic@multigpu-no-exec-userptr-rebind:
- shard-lnl: NOTRUN -> [SKIP][98] ([Intel XE#1392])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-3/igt@xe_exec_basic@multigpu-no-exec-userptr-rebind.html
* igt@xe_exec_fault_mode@many-userptr-invalidate-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#288]) +9 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-464/igt@xe_exec_fault_mode@many-userptr-invalidate-imm.html
* igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
- shard-dg2-set2: NOTRUN -> [SKIP][100] ([Intel XE#2360])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-466/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html
* igt@xe_exec_system_allocator@many-large-mmap-free-huge-nomemset:
- shard-lnl: NOTRUN -> [SKIP][101] ([Intel XE#4943])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-4/igt@xe_exec_system_allocator@many-large-mmap-free-huge-nomemset.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-single-vma:
- shard-lnl: NOTRUN -> [SKIP][102] ([Intel XE#6196])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-single-vma.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
- shard-bmg: NOTRUN -> [SKIP][103] ([Intel XE#4943]) +14 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-8/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html
* igt@xe_exec_system_allocator@twice-malloc-fork-read:
- shard-dg2-set2: NOTRUN -> [SKIP][104] ([Intel XE#4915]) +139 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-433/igt@xe_exec_system_allocator@twice-malloc-fork-read.html
* igt@xe_media_fill@media-fill:
- shard-bmg: NOTRUN -> [SKIP][105] ([Intel XE#2459] / [Intel XE#2596])
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@xe_media_fill@media-fill.html
* igt@xe_module_load@force-load:
- shard-bmg: NOTRUN -> [SKIP][106] ([Intel XE#2457])
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-1/igt@xe_module_load@force-load.html
* igt@xe_oa@privileged-forked-access-vaddr:
- shard-dg2-set2: NOTRUN -> [SKIP][107] ([Intel XE#3573]) +3 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-466/igt@xe_oa@privileged-forked-access-vaddr.html
* igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p:
- shard-dg2-set2: NOTRUN -> [FAIL][108] ([Intel XE#1173]) +1 other test fail
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-435/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html
* igt@xe_pm@s4-basic:
- shard-dg2-set2: [PASS][109] -> [FAIL][110] ([Intel XE#6406]) +1 other test fail
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-dg2-463/igt@xe_pm@s4-basic.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-432/igt@xe_pm@s4-basic.html
- shard-lnl: [PASS][111] -> [FAIL][112] ([Intel XE#6406]) +2 other tests fail
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-2/igt@xe_pm@s4-basic.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@xe_pm@s4-basic.html
* igt@xe_pm@s4-multiple-execs:
- shard-bmg: [PASS][113] -> [FAIL][114] ([Intel XE#6406]) +1 other test fail
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-6/igt@xe_pm@s4-multiple-execs.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-7/igt@xe_pm@s4-multiple-execs.html
* igt@xe_pxp@pxp-stale-queue-post-suspend:
- shard-bmg: NOTRUN -> [SKIP][115] ([Intel XE#4733])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-1/igt@xe_pxp@pxp-stale-queue-post-suspend.html
- shard-dg2-set2: NOTRUN -> [SKIP][116] ([Intel XE#4733])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-432/igt@xe_pxp@pxp-stale-queue-post-suspend.html
* igt@xe_query@multigpu-query-cs-cycles:
- shard-bmg: NOTRUN -> [SKIP][117] ([Intel XE#944])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@xe_query@multigpu-query-cs-cycles.html
* igt@xe_query@multigpu-query-invalid-cs-cycles:
- shard-dg2-set2: NOTRUN -> [SKIP][118] ([Intel XE#944]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-436/igt@xe_query@multigpu-query-invalid-cs-cycles.html
- shard-lnl: NOTRUN -> [SKIP][119] ([Intel XE#944])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@xe_query@multigpu-query-invalid-cs-cycles.html
#### Possible fixes ####
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [INCOMPLETE][120] ([Intel XE#3862]) -> [PASS][121] +1 other test pass
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-bmg: [SKIP][122] ([Intel XE#2291]) -> [PASS][123] +1 other test pass
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-7/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-bmg: [SKIP][124] ([Intel XE#4354]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-5/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-bmg: [SKIP][126] ([Intel XE#2316]) -> [PASS][127] +1 other test pass
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@absolute-wf_vblank-interruptible@b-hdmi-a6:
- shard-dg2-set2: [INCOMPLETE][128] ([Intel XE#2049]) -> [PASS][129] +1 other test pass
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-dg2-432/igt@kms_flip@absolute-wf_vblank-interruptible@b-hdmi-a6.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-436/igt@kms_flip@absolute-wf_vblank-interruptible@b-hdmi-a6.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][130] ([Intel XE#1503]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@kms_hdr@invalid-hdr.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-bmg: [SKIP][132] ([Intel XE#3012]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-bmg: [SKIP][134] ([Intel XE#2685] / [Intel XE#3307]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-2/igt@kms_plane_scaling@intel-max-src-size.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@kms_plane_scaling@intel-max-src-size.html
- shard-dg2-set2: [SKIP][136] ([Intel XE#455]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-dg2-432/igt@kms_plane_scaling@intel-max-src-size.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-433/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_pm_dc@dc5-psr:
- shard-lnl: [FAIL][138] ([Intel XE#718]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-7/igt@kms_pm_dc@dc5-psr.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@kms_pm_dc@dc5-psr.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [FAIL][140] ([Intel XE#4459]) -> [PASS][141] +1 other test pass
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@xe_exec_balancer@once-parallel-userptr-invalidate:
- shard-bmg: [DMESG-FAIL][142] ([Intel XE#3876]) -> [PASS][143] +2 other tests pass
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@xe_exec_balancer@once-parallel-userptr-invalidate.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-4/igt@xe_exec_balancer@once-parallel-userptr-invalidate.html
* igt@xe_exec_basic@many-null-defer-bind:
- shard-bmg: [DMESG-WARN][144] ([Intel XE#3876]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@xe_exec_basic@many-null-defer-bind.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-5/igt@xe_exec_basic@many-null-defer-bind.html
* igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm:
- shard-bmg: [FAIL][146] ([Intel XE#5625]) -> [PASS][147] +3 other tests pass
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-1/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm.html
* igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm:
- shard-bmg: [FAIL][148] ([Intel XE#6050]) -> [PASS][149] +1 other test pass
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html
* igt@xe_exec_reset@cm-gt-reset:
- shard-bmg: [FAIL][150] ([Intel XE#6325]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@xe_exec_reset@cm-gt-reset.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-7/igt@xe_exec_reset@cm-gt-reset.html
* igt@xe_exec_system_allocator@twice-mmap-new-race-nomemset:
- shard-bmg: [FAIL][152] ([Intel XE#4937] / [Intel XE#5625]) -> [PASS][153] +31 other tests pass
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@xe_exec_system_allocator@twice-mmap-new-race-nomemset.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@xe_exec_system_allocator@twice-mmap-new-race-nomemset.html
* igt@xe_module_load@load:
- shard-lnl: ([PASS][154], [SKIP][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172], [PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179]) ([Intel XE#378]) -> ([PASS][180], [PASS][181], [PASS][182], [PASS][183], [PASS][184], [PASS][185], [PASS][186], [PASS][187], [PASS][188], [PASS][189], [PASS][190], [PASS][191], [PASS][192], [PASS][193], [PASS][194], [PASS][195], [PASS][196], [PASS][197], [PASS][198], [PASS][199], [PASS][200], [PASS][201], [PASS][202], [PASS][203], [PASS][204])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-1/igt@xe_module_load@load.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-2/igt@xe_module_load@load.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-8/igt@xe_module_load@load.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-8/igt@xe_module_load@load.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-8/igt@xe_module_load@load.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-8/igt@xe_module_load@load.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-4/igt@xe_module_load@load.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-4/igt@xe_module_load@load.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-2/igt@xe_module_load@load.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-2/igt@xe_module_load@load.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-2/igt@xe_module_load@load.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-2/igt@xe_module_load@load.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-5/igt@xe_module_load@load.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-1/igt@xe_module_load@load.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-5/igt@xe_module_load@load.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-5/igt@xe_module_load@load.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-4/igt@xe_module_load@load.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-7/igt@xe_module_load@load.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-7/igt@xe_module_load@load.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-7/igt@xe_module_load@load.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-5/igt@xe_module_load@load.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-1/igt@xe_module_load@load.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-1/igt@xe_module_load@load.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-3/igt@xe_module_load@load.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-3/igt@xe_module_load@load.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-3/igt@xe_module_load@load.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@xe_module_load@load.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@xe_module_load@load.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@xe_module_load@load.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-8/igt@xe_module_load@load.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-1/igt@xe_module_load@load.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-5/igt@xe_module_load@load.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-5/igt@xe_module_load@load.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-5/igt@xe_module_load@load.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-7/igt@xe_module_load@load.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-7/igt@xe_module_load@load.html
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-2/igt@xe_module_load@load.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-5/igt@xe_module_load@load.html
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-1/igt@xe_module_load@load.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-3/igt@xe_module_load@load.html
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-3/igt@xe_module_load@load.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-3/igt@xe_module_load@load.html
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-4/igt@xe_module_load@load.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-7/igt@xe_module_load@load.html
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-7/igt@xe_module_load@load.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-2/igt@xe_module_load@load.html
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-1/igt@xe_module_load@load.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-1/igt@xe_module_load@load.html
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-4/igt@xe_module_load@load.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-4/igt@xe_module_load@load.html
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-2/igt@xe_module_load@load.html
* igt@xe_pm@s2idle-exec-after:
- shard-bmg: [TIMEOUT][205] ([Intel XE#3876] / [Intel XE#6162]) -> [PASS][206]
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@xe_pm@s2idle-exec-after.html
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-8/igt@xe_pm@s2idle-exec-after.html
* igt@xe_pm@s4-vm-bind-unbind-all:
- shard-bmg: [FAIL][207] ([Intel XE#6406]) -> [PASS][208]
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-1/igt@xe_pm@s4-vm-bind-unbind-all.html
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-4/igt@xe_pm@s4-vm-bind-unbind-all.html
- shard-dg2-set2: [FAIL][209] ([Intel XE#6406]) -> [PASS][210]
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-dg2-463/igt@xe_pm@s4-vm-bind-unbind-all.html
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-435/igt@xe_pm@s4-vm-bind-unbind-all.html
* igt@xe_pm@s4-vm-bind-userptr:
- shard-lnl: [FAIL][211] ([Intel XE#6406]) -> [PASS][212] +2 other tests pass
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-lnl-7/igt@xe_pm@s4-vm-bind-userptr.html
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-lnl-5/igt@xe_pm@s4-vm-bind-userptr.html
* igt@xe_pm_residency@gt-c6-freeze@gt0:
- shard-bmg: [DMESG-FAIL][213] ([Intel XE#5545]) -> [PASS][214] +1 other test pass
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@xe_pm_residency@gt-c6-freeze@gt0.html
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-2/igt@xe_pm_residency@gt-c6-freeze@gt0.html
* igt@xe_pm_residency@gt-c6-freeze@gt1:
- shard-bmg: [FAIL][215] ([Intel XE#5545]) -> [PASS][216]
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@xe_pm_residency@gt-c6-freeze@gt1.html
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-2/igt@xe_pm_residency@gt-c6-freeze@gt1.html
* igt@xe_pmu@gt-c6-idle:
- shard-dg2-set2: [FAIL][217] ([Intel XE#6366]) -> [PASS][218]
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-dg2-434/igt@xe_pmu@gt-c6-idle.html
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-433/igt@xe_pmu@gt-c6-idle.html
* igt@xe_vm@munmap-style-unbind-userptr-inval-front:
- shard-bmg: [INCOMPLETE][219] -> [PASS][220]
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@xe_vm@munmap-style-unbind-userptr-inval-front.html
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-3/igt@xe_vm@munmap-style-unbind-userptr-inval-front.html
#### Warnings ####
* igt@kms_content_protection@lic-type-0:
- shard-bmg: [FAIL][221] ([Intel XE#1178]) -> [SKIP][222] ([Intel XE#2341])
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-1/igt@kms_content_protection@lic-type-0.html
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_content_protection@lic-type-0.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt:
- shard-bmg: [SKIP][223] ([Intel XE#2311]) -> [SKIP][224] ([Intel XE#2312]) +7 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt.html
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][225] ([Intel XE#5390]) -> [SKIP][226] ([Intel XE#2312]) +6 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][227] ([Intel XE#2312]) -> [SKIP][228] ([Intel XE#5390]) +3 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff:
- shard-bmg: [SKIP][229] ([Intel XE#2312]) -> [SKIP][230] ([Intel XE#2311]) +5 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff.html
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
- shard-bmg: [SKIP][231] ([Intel XE#2312]) -> [SKIP][232] ([Intel XE#2313]) +4 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff:
- shard-bmg: [SKIP][233] ([Intel XE#2313]) -> [SKIP][234] ([Intel XE#2312]) +7 other tests skip
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][235] ([Intel XE#2426]) -> [SKIP][236] ([Intel XE#2509])
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-dg2-set2: [ABORT][237] ([Intel XE#4917] / [Intel XE#5466]) -> [ABORT][238] ([Intel XE#5466])
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-dg2-464/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-dg2-463/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
- shard-bmg: [ABORT][239] ([Intel XE#4917] / [Intel XE#5466] / [Intel XE#5530]) -> [ABORT][240] ([Intel XE#5466] / [Intel XE#5530])
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8594/shard-bmg-8/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/shard-bmg-5/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
[Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
[Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2685]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2685
[Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
[Intel XE#3307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3307
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#4937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4937
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
[Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
[Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
[Intel XE#6050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6050
[Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6162
[Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
[Intel XE#623]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/623
[Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6313
[Intel XE#6325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6325
[Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
[Intel XE#6366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6366
[Intel XE#6406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6406
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_8594 -> IGTPW_13923
IGTPW_13923: 46d3e0a9b87bf7fdb50ff31d8394f9a401fac957 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8594: 8594
xe-3950-76e60b5ce41fc1bcabf7941a57303d541bffd6ad: 76e60b5ce41fc1bcabf7941a57303d541bffd6ad
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13923/index.html
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^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ i915.CI.Full: failure for Multi-tile support for xe_sriov_flr and other MMIO improvements
2025-10-20 16:26 [PATCH v1 0/3] Multi-tile support for xe_sriov_flr and other MMIO improvements Piórkowski, Piotr
` (6 preceding siblings ...)
2025-10-21 12:15 ` Patchwork
@ 2025-10-21 17:29 ` Patchwork
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-10-21 17:29 UTC (permalink / raw)
To: Piórkowski, Piotr; +Cc: igt-dev
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== Series Details ==
Series: Multi-tile support for xe_sriov_flr and other MMIO improvements
URL : https://patchwork.freedesktop.org/series/156216/
State : failure
== Summary ==
CI Bug Log - changes from IGT_8594_full -> IGTPW_13923_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_13923_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_13923_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/index.html
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_13923_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-rkl: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@i915_suspend@fence-restore-tiled2untiled.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_plane_cursor@viewport@pipe-a-hdmi-a-2-size-64:
- shard-rkl: NOTRUN -> [FAIL][3] +2 other tests fail
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_plane_cursor@viewport@pipe-a-hdmi-a-2-size-64.html
* igt@kms_setmode@basic:
- shard-dg1: [PASS][4] -> [FAIL][5] +2 other tests fail
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg1-19/igt@kms_setmode@basic.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-16/igt@kms_setmode@basic.html
#### Warnings ####
* igt@kms_plane_cursor@viewport:
- shard-rkl: [SKIP][6] ([i915#14544]) -> [FAIL][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_plane_cursor@viewport.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_plane_cursor@viewport.html
Known issues
------------
Here are the changes found in IGTPW_13923_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg2-9: NOTRUN -> [SKIP][8] ([i915#8411])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#8411])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@device_reset@cold-reset-bound:
- shard-dg2-9: NOTRUN -> [SKIP][10] ([i915#11078])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@device_reset@cold-reset-bound.html
* igt@fbdev@eof:
- shard-rkl: NOTRUN -> [SKIP][11] ([i915#14544] / [i915#2582])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@fbdev@eof.html
* igt@fbdev@pan:
- shard-rkl: [PASS][12] -> [SKIP][13] ([i915#14544] / [i915#2582])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@fbdev@pan.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@fbdev@pan.html
* igt@gem_bad_reloc@negative-reloc-bltcopy:
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#3281]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-4/igt@gem_bad_reloc@negative-reloc-bltcopy.html
* igt@gem_busy@semaphore:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#3936])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@gem_busy@semaphore.html
* igt@gem_ccs@suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][16] ([i915#9323])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-18/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-dg2-9: NOTRUN -> [SKIP][17] ([i915#7697])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-rkl: NOTRUN -> [SKIP][18] ([i915#6335]) +1 other test skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@gem_create@create-ext-cpu-access-sanity-check.html
* igt@gem_ctx_persistence@hang:
- shard-dg2-9: NOTRUN -> [SKIP][19] ([i915#8555]) +2 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg2: NOTRUN -> [SKIP][20] ([i915#8555]) +2 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@gem_ctx_persistence@heartbeat-hang.html
- shard-mtlp: NOTRUN -> [SKIP][21] ([i915#8555]) +1 other test skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-3/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][22] ([i915#1099])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-snb7/igt@gem_ctx_persistence@idempotent.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg2: NOTRUN -> [SKIP][23] ([i915#280]) +1 other test skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@gem_ctx_sseu@invalid-sseu.html
- shard-tglu-1: NOTRUN -> [SKIP][24] ([i915#280]) +1 other test skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@gem_ctx_sseu@invalid-sseu.html
- shard-dg1: NOTRUN -> [SKIP][25] ([i915#280])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_ctx_sseu@mmap-args:
- shard-rkl: NOTRUN -> [SKIP][26] ([i915#14544] / [i915#280])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@in-flight-suspend:
- shard-glk10: NOTRUN -> [INCOMPLETE][27] ([i915#13390])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk10/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@reset-stress:
- shard-snb: NOTRUN -> [FAIL][28] ([i915#8898])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-snb5/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-dual:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#4771])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@bonded-sync:
- shard-dg2-9: NOTRUN -> [SKIP][30] ([i915#4771])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#4036])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-rkl: NOTRUN -> [SKIP][32] ([i915#4525])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglu-1: NOTRUN -> [SKIP][33] ([i915#4525])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_big@single:
- shard-tglu: [PASS][34] -> [ABORT][35] ([i915#11713])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-tglu-5/igt@gem_exec_big@single.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-7/igt@gem_exec_big@single.html
* igt@gem_exec_capture@capture-invisible:
- shard-glk10: NOTRUN -> [SKIP][36] ([i915#6334]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk10/igt@gem_exec_capture@capture-invisible.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-tglu-1: NOTRUN -> [SKIP][37] ([i915#6334]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_capture@capture@vecs0-lmem0:
- shard-dg1: NOTRUN -> [FAIL][38] ([i915#11965]) +2 other tests fail
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-18/igt@gem_exec_capture@capture@vecs0-lmem0.html
- shard-dg2-9: NOTRUN -> [FAIL][39] ([i915#11965]) +4 other tests fail
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_exec_capture@capture@vecs0-lmem0.html
* igt@gem_exec_fence@concurrent:
- shard-dg2-9: NOTRUN -> [SKIP][40] ([i915#4812]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_exec_fence@concurrent.html
* igt@gem_exec_fence@submit3:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#4812]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@gem_exec_fence@submit3.html
* igt@gem_exec_fence@syncobj-backward-timeline-chain-engines:
- shard-snb: NOTRUN -> [SKIP][42] +63 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-snb5/igt@gem_exec_fence@syncobj-backward-timeline-chain-engines.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg2-9: NOTRUN -> [SKIP][43] ([i915#3539] / [i915#4852])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#3539] / [i915#4852]) +3 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@gem_exec_flush@basic-uc-pro-default.html
- shard-dg1: NOTRUN -> [SKIP][45] ([i915#3539] / [i915#4852]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-15/igt@gem_exec_flush@basic-uc-pro-default.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-mtlp: NOTRUN -> [SKIP][46] ([i915#5107])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@gem_exec_params@rsvd2-dirt.html
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#5107])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_params@secure-non-master:
- shard-mtlp: NOTRUN -> [SKIP][48] +4 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@gem_exec_params@secure-non-master.html
* igt@gem_exec_reloc@basic-range:
- shard-dg2-9: NOTRUN -> [SKIP][49] ([i915#3281]) +8 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_exec_reloc@basic-range.html
* igt@gem_exec_reloc@basic-write-read-active:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#3281]) +10 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@gem_exec_reloc@basic-write-read-active.html
- shard-dg1: NOTRUN -> [SKIP][51] ([i915#3281]) +7 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@gem_exec_reloc@basic-write-read-active.html
* igt@gem_exec_reloc@basic-write-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][52] ([i915#3281]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@gem_exec_reloc@basic-write-read-noreloc.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-dg1: NOTRUN -> [SKIP][53] ([i915#4812]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-18/igt@gem_exec_schedule@preempt-queue-contexts.html
- shard-dg2-9: NOTRUN -> [SKIP][54] ([i915#4537] / [i915#4812])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#4537] / [i915#4812]) +2 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_exec_suspend@basic-s0:
- shard-dg2: [PASS][56] -> [INCOMPLETE][57] ([i915#13356]) +1 other test incomplete
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg2-7/igt@gem_exec_suspend@basic-s0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-3/igt@gem_exec_suspend@basic-s0.html
* igt@gem_fence_thrash@bo-copy:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#4860]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@gem_fence_thrash@bo-copy.html
* igt@gem_fenced_exec_thrash@no-spare-fences:
- shard-dg1: NOTRUN -> [SKIP][59] ([i915#4860])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-16/igt@gem_fenced_exec_thrash@no-spare-fences.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-dg2-9: NOTRUN -> [SKIP][60] ([i915#4860])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: NOTRUN -> [SKIP][61] ([i915#2190])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@gem_huc_copy@huc-copy.html
- shard-tglu: NOTRUN -> [SKIP][62] ([i915#2190])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-10/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-rkl: NOTRUN -> [SKIP][63] ([i915#4613] / [i915#7582])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@gem_lmem_evict@dontneed-evict-race.html
- shard-tglu: NOTRUN -> [SKIP][64] ([i915#4613] / [i915#7582])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-5/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#4613]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@random-engines:
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#14544] / [i915#4613])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_lmem_swapping@random-engines.html
- shard-tglu: NOTRUN -> [SKIP][67] ([i915#4613]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-7/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: NOTRUN -> [TIMEOUT][68] ([i915#5493]) +1 other test timeout
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify:
- shard-tglu-1: NOTRUN -> [SKIP][69] ([i915#4613])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@gem_lmem_swapping@verify.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-dg1: NOTRUN -> [SKIP][70] ([i915#12193])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-19/igt@gem_lmem_swapping@verify-ccs.html
- shard-mtlp: NOTRUN -> [SKIP][71] ([i915#4613]) +1 other test skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-7/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_lmem_swapping@verify-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#4565])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-19/igt@gem_lmem_swapping@verify-ccs@lmem0.html
* igt@gem_mmap@bad-object:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#4083])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-8/igt@gem_mmap@bad-object.html
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- shard-dg2-9: NOTRUN -> [SKIP][74] ([i915#4077]) +9 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
* igt@gem_mmap_gtt@hang-busy:
- shard-mtlp: NOTRUN -> [SKIP][75] ([i915#4077]) +5 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-4/igt@gem_mmap_gtt@hang-busy.html
* igt@gem_mmap_wc@bad-object:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#4083]) +5 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@gem_mmap_wc@bad-object.html
* igt@gem_mmap_wc@pf-nonblock:
- shard-dg2-9: NOTRUN -> [SKIP][77] ([i915#4083]) +8 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_mmap_wc@pf-nonblock.html
* igt@gem_partial_pwrite_pread@writes-after-reads-display:
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#3282]) +5 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#3282]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#3282]) +3 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
- shard-mtlp: NOTRUN -> [SKIP][81] ([i915#3282]) +1 other test skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-4/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
* igt@gem_pxp@create-valid-protected-context:
- shard-rkl: NOTRUN -> [TIMEOUT][82] ([i915#12964])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@hw-rejects-pxp-context:
- shard-tglu-1: NOTRUN -> [SKIP][83] ([i915#13398])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@gem_pxp@hw-rejects-pxp-context.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-rkl: [PASS][84] -> [TIMEOUT][85] ([i915#12917] / [i915#12964]) +1 other test timeout
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#4270]) +1 other test skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@gem_pxp@reject-modify-context-protection-off-3.html
- shard-dg1: NOTRUN -> [SKIP][87] ([i915#4270])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@gem_pxp@reject-modify-context-protection-off-3.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-dg2-9: NOTRUN -> [SKIP][88] ([i915#4270]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
- shard-rkl: NOTRUN -> [TIMEOUT][89] ([i915#12917] / [i915#12964])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_readwrite@new-obj:
- shard-dg2-9: NOTRUN -> [SKIP][90] ([i915#3282]) +2 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_readwrite@new-obj.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-dg2-9: NOTRUN -> [SKIP][91] ([i915#5190] / [i915#8428]) +4 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_render_copy@y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][92] ([i915#8428]) +2 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-5/igt@gem_render_copy@y-tiled.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
- shard-glk: NOTRUN -> [SKIP][93] +145 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk1/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
* igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#5190] / [i915#8428]) +4 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-rkl: NOTRUN -> [SKIP][95] ([i915#14544] / [i915#8411])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
- shard-dg2-9: NOTRUN -> [SKIP][96] ([i915#4079])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_softpin@evict-snoop:
- shard-dg2-9: NOTRUN -> [SKIP][97] ([i915#4885]) +1 other test skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_softpin@evict-snoop.html
* igt@gem_softpin@noreloc-s3:
- shard-rkl: [PASS][98] -> [ABORT][99] ([i915#15131])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@gem_softpin@noreloc-s3.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@gem_softpin@noreloc-s3.html
* igt@gem_tiled_pread_pwrite:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#14544] / [i915#3282])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_tiled_pread_pwrite.html
* igt@gem_userptr_blits@forbidden-operations:
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#3282] / [i915#3297])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@gem_userptr_blits@forbidden-operations.html
- shard-dg2-9: NOTRUN -> [SKIP][102] ([i915#3282] / [i915#3297])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gem_userptr_blits@forbidden-operations.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#3297] / [i915#4880]) +1 other test skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@relocations:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#3281] / [i915#3297])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@gem_userptr_blits@relocations.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-rkl: NOTRUN -> [SKIP][105] ([i915#3297])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@gem_userptr_blits@unsync-unmap.html
- shard-tglu: NOTRUN -> [SKIP][106] ([i915#3297])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-10/igt@gem_userptr_blits@unsync-unmap.html
- shard-mtlp: NOTRUN -> [SKIP][107] ([i915#3297])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-3/igt@gem_userptr_blits@unsync-unmap.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#3297]) +1 other test skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@gem_userptr_blits@unsync-unmap-cycles.html
- shard-dg1: NOTRUN -> [SKIP][109] ([i915#3297]) +1 other test skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-19/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_workarounds@suspend-resume:
- shard-glk: NOTRUN -> [INCOMPLETE][110] ([i915#13356] / [i915#14586])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk9/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@basic-rejected:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#2527]) +1 other test skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-tglu: NOTRUN -> [SKIP][112] ([i915#2527] / [i915#2856])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-5/igt@gen9_exec_parse@batch-zero-length.html
* igt@gen9_exec_parse@bb-large:
- shard-dg2-9: NOTRUN -> [SKIP][113] ([i915#2856]) +1 other test skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@gen9_exec_parse@bb-large.html
* igt@gen9_exec_parse@bb-secure:
- shard-dg1: NOTRUN -> [SKIP][114] ([i915#2527])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@bb-start-far:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#2856]) +4 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@gen9_exec_parse@bb-start-far.html
- shard-tglu-1: NOTRUN -> [SKIP][116] ([i915#2527] / [i915#2856]) +1 other test skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@gen9_exec_parse@bb-start-far.html
- shard-mtlp: NOTRUN -> [SKIP][117] ([i915#2856])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@gen9_exec_parse@bb-start-far.html
* igt@i915_drm_fdinfo@all-busy-check-all:
- shard-mtlp: NOTRUN -> [SKIP][118] ([i915#14123])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-2/igt@i915_drm_fdinfo@all-busy-check-all.html
* igt@i915_drm_fdinfo@all-busy-idle-check-all:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#14123]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@i915_drm_fdinfo@all-busy-idle-check-all.html
* igt@i915_drm_fdinfo@busy:
- shard-dg2-9: NOTRUN -> [SKIP][120] ([i915#14073]) +7 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@i915_drm_fdinfo@busy.html
* igt@i915_drm_fdinfo@busy-check-all:
- shard-dg1: NOTRUN -> [SKIP][121] ([i915#11527]) +11 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-17/igt@i915_drm_fdinfo@busy-check-all.html
* igt@i915_drm_fdinfo@busy-check-all@vecs0:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#11527]) +7 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@i915_drm_fdinfo@busy-check-all@vecs0.html
* igt@i915_drm_fdinfo@virtual-busy-hang:
- shard-dg2-9: NOTRUN -> [SKIP][123] ([i915#14118]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@i915_drm_fdinfo@virtual-busy-hang.html
* igt@i915_drm_fdinfo@virtual-busy-hang-all:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#14118])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@i915_drm_fdinfo@virtual-busy-hang-all.html
* igt@i915_module_load@reload-no-display:
- shard-snb: [PASS][125] -> [DMESG-WARN][126] ([i915#14545])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-snb1/igt@i915_module_load@reload-no-display.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-snb7/igt@i915_module_load@reload-no-display.html
* igt@i915_module_load@resize-bar:
- shard-dg2: NOTRUN -> [DMESG-WARN][127] ([i915#14545])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@i915_module_load@resize-bar.html
- shard-rkl: NOTRUN -> [SKIP][128] ([i915#6412])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@i915_module_load@resize-bar.html
- shard-dg1: NOTRUN -> [SKIP][129] ([i915#7178])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-16/igt@i915_module_load@resize-bar.html
- shard-tglu: NOTRUN -> [SKIP][130] ([i915#6412])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-7/igt@i915_module_load@resize-bar.html
- shard-mtlp: NOTRUN -> [SKIP][131] ([i915#6412])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-rkl: NOTRUN -> [SKIP][132] ([i915#6590]) +1 other test skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-dg2-9: NOTRUN -> [FAIL][133] ([i915#12964]) +1 other test fail
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-rkl: [PASS][134] -> [SKIP][135] ([i915#13328])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@i915_pm_rpm@debugfs-forcewake-user.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@i915_pm_rpm@debugfs-forcewake-user.html
* igt@i915_pm_rps@thresholds:
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#11681])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@i915_pm_rps@thresholds.html
- shard-dg1: NOTRUN -> [SKIP][137] ([i915#11681])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-19/igt@i915_pm_rps@thresholds.html
- shard-mtlp: NOTRUN -> [SKIP][138] ([i915#11681])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-7/igt@i915_pm_rps@thresholds.html
* igt@i915_power@sanity:
- shard-rkl: NOTRUN -> [SKIP][139] ([i915#7984])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@i915_power@sanity.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-glk: [PASS][140] -> [INCOMPLETE][141] ([i915#4817])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-glk1/igt@i915_suspend@fence-restore-tiled2untiled.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk5/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@i915_suspend@fence-restore-untiled:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#4077]) +13 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@i915_suspend@fence-restore-untiled.html
* igt@i915_suspend@forcewake:
- shard-rkl: [PASS][143] -> [INCOMPLETE][144] ([i915#4817]) +1 other test incomplete
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@i915_suspend@forcewake.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@i915_suspend@forcewake.html
- shard-glk10: NOTRUN -> [INCOMPLETE][145] ([i915#4817])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk10/igt@i915_suspend@forcewake.html
* igt@i915_suspend@sysfs-reader:
- shard-glk: NOTRUN -> [INCOMPLETE][146] ([i915#4817])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk6/igt@i915_suspend@sysfs-reader.html
* igt@intel_hwmon@hwmon-write:
- shard-tglu-1: NOTRUN -> [SKIP][147] ([i915#7707])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@intel_hwmon@hwmon-write.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#4212])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-3/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#4212]) +1 other test skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
- shard-dg1: NOTRUN -> [SKIP][150] ([i915#4212]) +1 other test skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-15/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-dg2: [PASS][151] -> [FAIL][152] ([i915#5956]) +1 other test fail
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg2-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
- shard-tglu: [PASS][153] -> [FAIL][154] ([i915#14857]) +1 other test fail
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-tglu-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-10/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1:
- shard-mtlp: [PASS][155] -> [FAIL][156] ([i915#5956]) +1 other test fail
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-mtlp-4/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-7/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][157] ([i915#4538] / [i915#5286]) +2 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-dg2-9: NOTRUN -> [SKIP][158] +10 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#5286]) +1 other test skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_big_fb@4-tiled-addfb.html
- shard-tglu: NOTRUN -> [SKIP][160] ([i915#5286]) +1 other test skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-10/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-tglu-1: NOTRUN -> [SKIP][161] ([i915#5286]) +1 other test skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: [PASS][162] -> [FAIL][163] ([i915#5138])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][164] +14 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][165] ([i915#3638]) +1 other test skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
- shard-dg1: NOTRUN -> [SKIP][166] ([i915#3638])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-19/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#4538] / [i915#5190]) +7 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-dg2: NOTRUN -> [SKIP][168] ([i915#5190])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- shard-dg2-9: NOTRUN -> [SKIP][169] ([i915#4538] / [i915#5190]) +7 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-dg1: NOTRUN -> [SKIP][170] ([i915#4538])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][171] ([i915#6095]) +19 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-10/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-1.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
- shard-rkl: NOTRUN -> [SKIP][172] ([i915#14544]) +6 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#12313]) +2 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#12313]) +2 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
- shard-dg1: NOTRUN -> [SKIP][175] ([i915#12313])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-13/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
- shard-tglu: NOTRUN -> [SKIP][176] ([i915#12313])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-10/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
- shard-mtlp: NOTRUN -> [SKIP][177] ([i915#12313])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-3/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][178] ([i915#6095]) +118 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-17/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#6095]) +44 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2:
- shard-dg2-9: NOTRUN -> [SKIP][180] ([i915#10307] / [i915#6095]) +48 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2.html
* igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][181] ([i915#12313])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][182] ([i915#6095]) +24 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][183] ([i915#14098] / [i915#6095]) +42 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][184] ([i915#6095]) +4 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-2/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-edp-1.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#10307] / [i915#6095]) +97 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][186] ([i915#10307] / [i915#10434] / [i915#6095])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#12805])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#12805])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
- shard-tglu: NOTRUN -> [SKIP][189] ([i915#12805])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-4/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#6095]) +18 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [INCOMPLETE][191] ([i915#12796]) +1 other test incomplete
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk9/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][192] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@plane-scaling:
- shard-tglu-1: NOTRUN -> [SKIP][193] ([i915#3742])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-dg1: NOTRUN -> [SKIP][194] ([i915#11151] / [i915#7828]) +2 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-16/igt@kms_chamelium_audio@hdmi-audio-edid.html
- shard-tglu: NOTRUN -> [SKIP][195] ([i915#11151] / [i915#7828]) +2 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-7/igt@kms_chamelium_audio@hdmi-audio-edid.html
- shard-mtlp: NOTRUN -> [SKIP][196] ([i915#11151] / [i915#7828]) +1 other test skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_edid@dp-edid-read:
- shard-dg2-9: NOTRUN -> [SKIP][197] ([i915#11151] / [i915#7828]) +4 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_chamelium_edid@dp-edid-read.html
* igt@kms_chamelium_edid@vga-edid-read:
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#11151] / [i915#7828]) +4 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_chamelium_edid@vga-edid-read.html
* igt@kms_chamelium_frames@dp-frame-dump:
- shard-dg2: NOTRUN -> [SKIP][199] ([i915#11151] / [i915#7828]) +5 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_chamelium_frames@dp-frame-dump.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-tglu-1: NOTRUN -> [SKIP][200] ([i915#11151] / [i915#7828]) +2 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_color@ctm-blue-to-red:
- shard-rkl: [PASS][201] -> [SKIP][202] ([i915#12655] / [i915#14544])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@kms_color@ctm-blue-to-red.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_color@ctm-blue-to-red.html
* igt@kms_content_protection@content-type-change:
- shard-tglu-1: NOTRUN -> [SKIP][203] ([i915#6944] / [i915#9424]) +1 other test skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#3299])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg1: NOTRUN -> [SKIP][205] ([i915#3299])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2-9: NOTRUN -> [SKIP][206] ([i915#3299])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#7118] / [i915#9424]) +1 other test skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@kms_content_protection@legacy.html
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#7118] / [i915#9424]) +1 other test skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_content_protection@legacy.html
- shard-dg1: NOTRUN -> [SKIP][209] ([i915#7116] / [i915#9424])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_content_protection@legacy.html
- shard-tglu: NOTRUN -> [SKIP][210] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424]) +1 other test skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-9/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-1:
- shard-rkl: NOTRUN -> [SKIP][211] ([i915#9424])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@srm:
- shard-dg1: NOTRUN -> [SKIP][212] ([i915#7116])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-mtlp: NOTRUN -> [SKIP][213] ([i915#6944] / [i915#9424]) +1 other test skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-4/igt@kms_content_protection@uevent.html
- shard-dg1: NOTRUN -> [SKIP][214] ([i915#4423] / [i915#7116] / [i915#9424])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-onscreen-128x42:
- shard-tglu: [PASS][215] -> [FAIL][216] ([i915#13566]) +5 other tests fail
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-tglu-2/igt@kms_cursor_crc@cursor-onscreen-128x42.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-7/igt@kms_cursor_crc@cursor-onscreen-128x42.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-dg2: NOTRUN -> [SKIP][217] ([i915#3555]) +5 other tests skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_cursor_crc@cursor-onscreen-max-size.html
- shard-mtlp: NOTRUN -> [SKIP][218] ([i915#3555] / [i915#8814])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-3/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-128x128@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [DMESG-WARN][219] ([i915#12964]) +13 other tests dmesg-warn
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_cursor_crc@cursor-random-128x128@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][220] ([i915#13566]) +1 other test fail
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-2.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-tglu: NOTRUN -> [SKIP][221] ([i915#3555])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-3/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#13049])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-128x128:
- shard-rkl: [PASS][223] -> [SKIP][224] ([i915#14544]) +33 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_cursor_crc@cursor-rapid-movement-128x128.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-128x128.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-rkl: NOTRUN -> [SKIP][225] ([i915#3555]) +3 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1:
- shard-rkl: [PASS][226] -> [FAIL][227] ([i915#13566]) +3 other tests fail
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-dg2-9: NOTRUN -> [SKIP][228] ([i915#13049]) +1 other test skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_cursor_crc@cursor-sliding-512x170.html
- shard-dg1: NOTRUN -> [SKIP][229] ([i915#13049])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-tglu-1: NOTRUN -> [SKIP][230] ([i915#3555]) +1 other test skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-rkl: NOTRUN -> [FAIL][231] ([i915#15077])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-mtlp: NOTRUN -> [SKIP][232] ([i915#9809]) +1 other test skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-dg2-9: NOTRUN -> [SKIP][233] ([i915#13046] / [i915#5354]) +1 other test skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-dg2: NOTRUN -> [SKIP][234] ([i915#13046] / [i915#5354]) +4 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-rkl: [PASS][235] -> [FAIL][236] ([i915#2346])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-dg1: NOTRUN -> [SKIP][237] ([i915#9067])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-19/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-tglu-1: NOTRUN -> [SKIP][238] ([i915#4103])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-rkl: NOTRUN -> [SKIP][239] ([i915#4103])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-dg2: NOTRUN -> [SKIP][240] ([i915#4103] / [i915#4213]) +1 other test skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-rkl: NOTRUN -> [SKIP][241] ([i915#9723])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
- shard-tglu: NOTRUN -> [SKIP][242] ([i915#9723])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-2/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-tglu-1: NOTRUN -> [SKIP][243] ([i915#9723])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_dp_aux_dev:
- shard-dg2-9: NOTRUN -> [SKIP][244] ([i915#1257])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_dp_aux_dev.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-dg2-9: NOTRUN -> [SKIP][245] ([i915#13749])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-dg2: NOTRUN -> [SKIP][246] ([i915#13707])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@kms_dp_linktrain_fallback@dp-fallback.html
- shard-mtlp: NOTRUN -> [SKIP][247] ([i915#13707])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_dsc@dsc-basic:
- shard-rkl: NOTRUN -> [SKIP][248] ([i915#3555] / [i915#3840]) +1 other test skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_dsc@dsc-basic.html
- shard-tglu: NOTRUN -> [SKIP][249] ([i915#3555] / [i915#3840])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-10/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg2: NOTRUN -> [SKIP][250] ([i915#3840] / [i915#9688])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-with-bpc:
- shard-mtlp: NOTRUN -> [SKIP][251] ([i915#3555] / [i915#3840])
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-4/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2: NOTRUN -> [SKIP][252] ([i915#3555] / [i915#3840]) +1 other test skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_fbcon_fbt@psr:
- shard-dg2-9: NOTRUN -> [SKIP][253] ([i915#3469])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@chamelium:
- shard-tglu: NOTRUN -> [SKIP][254] ([i915#2065] / [i915#4854])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-6/igt@kms_feature_discovery@chamelium.html
- shard-mtlp: NOTRUN -> [SKIP][255] ([i915#4854])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@kms_feature_discovery@chamelium.html
- shard-dg2-9: NOTRUN -> [SKIP][256] ([i915#4854])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_feature_discovery@chamelium.html
- shard-rkl: NOTRUN -> [SKIP][257] ([i915#4854])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_feature_discovery@chamelium.html
- shard-dg1: NOTRUN -> [SKIP][258] ([i915#4854])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-2x:
- shard-dg1: NOTRUN -> [SKIP][259] ([i915#1839])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-13/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2: NOTRUN -> [SKIP][260] ([i915#1839])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-3/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@display-4x:
- shard-dg2-9: NOTRUN -> [SKIP][261] ([i915#1839])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@dp-mst:
- shard-rkl: NOTRUN -> [SKIP][262] ([i915#14544] / [i915#9337])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_feature_discovery@dp-mst.html
* igt@kms_fence_pin_leak:
- shard-dg2-9: NOTRUN -> [SKIP][263] ([i915#4881])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglu-1: NOTRUN -> [SKIP][264] ([i915#3637] / [i915#9934]) +1 other test skip
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-dg1: NOTRUN -> [SKIP][265] ([i915#9934]) +1 other test skip
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-dg2-9: NOTRUN -> [SKIP][266] ([i915#9934]) +3 other tests skip
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-tglu: NOTRUN -> [SKIP][267] ([i915#9934]) +1 other test skip
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-10/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][268] ([i915#9934])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-3/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg2: NOTRUN -> [SKIP][269] ([i915#8381])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-dg2: NOTRUN -> [SKIP][270] ([i915#9934]) +9 other tests skip
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
- shard-mtlp: NOTRUN -> [SKIP][271] ([i915#3637] / [i915#9934]) +1 other test skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-7/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-tglu: NOTRUN -> [SKIP][272] ([i915#3637] / [i915#9934]) +1 other test skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-6/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-rkl: NOTRUN -> [SKIP][273] ([i915#9934]) +2 other tests skip
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-wf_vblank-ts-check:
- shard-rkl: NOTRUN -> [SKIP][274] ([i915#14544] / [i915#9934]) +1 other test skip
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_flip@2x-wf_vblank-ts-check.html
* igt@kms_flip@basic-flip-vs-dpms:
- shard-rkl: [PASS][275] -> [SKIP][276] ([i915#14544] / [i915#3637]) +1 other test skip
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_flip@basic-flip-vs-dpms.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_flip@basic-flip-vs-dpms.html
* igt@kms_flip@nonexisting-fb:
- shard-rkl: NOTRUN -> [SKIP][277] ([i915#14544] / [i915#3637])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_flip@nonexisting-fb.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][278] ([i915#2672] / [i915#3555])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][279] ([i915#2587] / [i915#2672])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][280] ([i915#2672]) +3 other tests skip
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
- shard-rkl: NOTRUN -> [SKIP][281] ([i915#2672] / [i915#3555])
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-rkl: [PASS][282] -> [SKIP][283] ([i915#14544] / [i915#3555]) +1 other test skip
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-dg2-9: NOTRUN -> [SKIP][284] ([i915#2672] / [i915#3555] / [i915#5190])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][285] ([i915#2672]) +4 other tests skip
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][286] ([i915#3555] / [i915#8810] / [i915#8813]) +1 other test skip
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
- shard-dg2-9: NOTRUN -> [SKIP][287] ([i915#2672] / [i915#3555]) +2 other tests skip
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-dg2-9: NOTRUN -> [SKIP][288] ([i915#2672]) +3 other tests skip
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-dg1: NOTRUN -> [SKIP][289] ([i915#2672] / [i915#3555])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-18/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][290] ([i915#2587] / [i915#2672])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-18/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-dg2: NOTRUN -> [SKIP][291] ([i915#2672] / [i915#3555] / [i915#5190]) +2 other tests skip
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-dg2: NOTRUN -> [SKIP][292] ([i915#2672] / [i915#3555]) +2 other tests skip
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][293] ([i915#8708]) +3 other tests skip
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-rkl: [PASS][294] -> [SKIP][295] ([i915#14544] / [i915#1849] / [i915#5354]) +4 other tests skip
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][296] ([i915#14544] / [i915#1849] / [i915#5354]) +2 other tests skip
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][297] ([i915#1825]) +4 other tests skip
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][298] ([i915#8708]) +14 other tests skip
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-tglu: NOTRUN -> [SKIP][299] +11 other tests skip
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-rkl: [PASS][300] -> [DMESG-WARN][301] ([i915#12917] / [i915#12964])
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][302] ([i915#15102]) +8 other tests skip
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc:
- shard-dg2-9: NOTRUN -> [SKIP][303] ([i915#15104]) +1 other test skip
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-rkl: NOTRUN -> [SKIP][304] ([i915#15102] / [i915#3023]) +6 other tests skip
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][305] ([i915#15102] / [i915#3458]) +12 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
- shard-tglu-1: NOTRUN -> [SKIP][306] +17 other tests skip
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-glk10: NOTRUN -> [SKIP][307] +139 other tests skip
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk10/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
- shard-dg2-9: NOTRUN -> [SKIP][308] ([i915#8708]) +14 other tests skip
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][309] +14 other tests skip
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
- shard-dg2: NOTRUN -> [SKIP][310] ([i915#5354]) +34 other tests skip
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-fullscreen:
- shard-dg2-9: NOTRUN -> [SKIP][311] ([i915#5354]) +21 other tests skip
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-dg1: NOTRUN -> [SKIP][312] ([i915#15102] / [i915#3458]) +6 other tests skip
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
- shard-dg2-9: NOTRUN -> [SKIP][313] ([i915#15102] / [i915#3458]) +13 other tests skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][314] ([i915#5439])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-tglu-1: NOTRUN -> [SKIP][315] ([i915#9766])
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-dg1: NOTRUN -> [SKIP][316] ([i915#9766])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt:
- shard-tglu-1: NOTRUN -> [SKIP][317] ([i915#15102]) +6 other tests skip
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][318] ([i915#15102])
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-render:
- shard-dg2: NOTRUN -> [SKIP][319] ([i915#15102])
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][320] ([i915#15104]) +1 other test skip
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-pwrite:
- shard-dg2-9: NOTRUN -> [SKIP][321] ([i915#15102]) +1 other test skip
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][322] ([i915#1825]) +11 other tests skip
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_hdr@static-toggle:
- shard-dg2: NOTRUN -> [SKIP][323] ([i915#3555] / [i915#8228])
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@kms_hdr@static-toggle.html
- shard-rkl: NOTRUN -> [SKIP][324] ([i915#3555] / [i915#8228])
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-3/igt@kms_hdr@static-toggle.html
* igt@kms_invalid_mode@zero-clock:
- shard-rkl: [PASS][325] -> [SKIP][326] ([i915#14544] / [i915#3555] / [i915#8826])
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_invalid_mode@zero-clock.html
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_invalid_mode@zero-clock.html
* igt@kms_invalid_mode@zero-hdisplay:
- shard-rkl: NOTRUN -> [SKIP][327] ([i915#14544] / [i915#3555] / [i915#8826])
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_invalid_mode@zero-hdisplay.html
* igt@kms_joiner@basic-big-joiner:
- shard-dg2: NOTRUN -> [SKIP][328] ([i915#10656])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-tglu: NOTRUN -> [SKIP][329] ([i915#12388])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-3/igt@kms_joiner@basic-force-big-joiner.html
- shard-dg2: NOTRUN -> [SKIP][330] ([i915#12388])
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@kms_joiner@basic-force-big-joiner.html
- shard-rkl: NOTRUN -> [SKIP][331] ([i915#12388])
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_joiner@basic-force-big-joiner.html
- shard-dg1: NOTRUN -> [SKIP][332] ([i915#12388])
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-19/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-dg2: NOTRUN -> [SKIP][333] ([i915#13688])
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-dg2: NOTRUN -> [SKIP][334] ([i915#12339])
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@kms_joiner@basic-ultra-joiner.html
- shard-tglu-1: NOTRUN -> [SKIP][335] ([i915#12339])
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-dg2-9: NOTRUN -> [SKIP][336] ([i915#10656])
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-tglu-1: NOTRUN -> [SKIP][337] ([i915#1839])
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-dg1: NOTRUN -> [SKIP][338] ([i915#6301])
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_pipe_stress@stress-xrgb8888-yftiled:
- shard-dg2: NOTRUN -> [SKIP][339] ([i915#14712])
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
* igt@kms_pipe_stress@stress-xrgb8888-ytiled:
- shard-dg2-9: NOTRUN -> [SKIP][340] ([i915#13705])
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
* igt@kms_plane@plane-panning-bottom-right-suspend:
- shard-glk: NOTRUN -> [INCOMPLETE][341] ([i915#13026]) +1 other test incomplete
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk5/igt@kms_plane@plane-panning-bottom-right-suspend.html
* igt@kms_plane@plane-panning-top-left:
- shard-rkl: [PASS][342] -> [SKIP][343] ([i915#14544] / [i915#8825]) +1 other test skip
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_plane@plane-panning-top-left.html
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane@plane-panning-top-left.html
* igt@kms_plane_alpha_blend@alpha-7efc:
- shard-rkl: [PASS][344] -> [SKIP][345] ([i915#14544] / [i915#7294]) +2 other tests skip
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-7/igt@kms_plane_alpha_blend@alpha-7efc.html
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_alpha_blend@alpha-7efc.html
* igt@kms_plane_alpha_blend@alpha-basic:
- shard-glk10: NOTRUN -> [FAIL][346] ([i915#12178])
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk10/igt@kms_plane_alpha_blend@alpha-basic.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
- shard-glk10: NOTRUN -> [FAIL][347] ([i915#7862]) +1 other test fail
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk10/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html
* igt@kms_plane_lowres@tiling-y:
- shard-dg2-9: NOTRUN -> [SKIP][348] ([i915#8821])
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-dg2-9: NOTRUN -> [SKIP][349] ([i915#13958])
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_plane_multiple@tiling-4:
- shard-rkl: NOTRUN -> [SKIP][350] ([i915#14259])
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_plane_multiple@tiling-4.html
- shard-dg1: NOTRUN -> [SKIP][351] ([i915#14259])
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-13/igt@kms_plane_multiple@tiling-4.html
- shard-tglu: NOTRUN -> [SKIP][352] ([i915#14259])
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-10/igt@kms_plane_multiple@tiling-4.html
* igt@kms_plane_multiple@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][353] ([i915#14259])
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-dg2-9: NOTRUN -> [SKIP][354] ([i915#13046] / [i915#5354] / [i915#9423])
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_plane_scaling@invalid-parameters:
- shard-rkl: [PASS][355] -> [SKIP][356] ([i915#14544] / [i915#8152])
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_plane_scaling@invalid-parameters.html
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_scaling@invalid-parameters.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-d:
- shard-tglu-1: NOTRUN -> [SKIP][357] ([i915#12247]) +4 other tests skip
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-d.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c:
- shard-rkl: NOTRUN -> [SKIP][358] ([i915#12247])
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
- shard-dg1: NOTRUN -> [SKIP][359] ([i915#3555])
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-13/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
- shard-dg1: NOTRUN -> [SKIP][360] ([i915#12247]) +8 other tests skip
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75:
- shard-rkl: NOTRUN -> [SKIP][361] ([i915#14544] / [i915#3555] / [i915#6953] / [i915#8152])
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][362] ([i915#12247] / [i915#14544])
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b:
- shard-rkl: NOTRUN -> [SKIP][363] ([i915#12247] / [i915#14544] / [i915#8152])
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75:
- shard-rkl: [PASS][364] -> [SKIP][365] ([i915#12247] / [i915#14544] / [i915#6953] / [i915#8152])
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a:
- shard-rkl: [PASS][366] -> [SKIP][367] ([i915#12247] / [i915#14544]) +1 other test skip
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a.html
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b:
- shard-rkl: [PASS][368] -> [SKIP][369] ([i915#12247] / [i915#14544] / [i915#8152]) +1 other test skip
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25:
- shard-rkl: [PASS][370] -> [SKIP][371] ([i915#14544] / [i915#3555] / [i915#6953] / [i915#8152])
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-7/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-dg2-9: NOTRUN -> [SKIP][372] ([i915#12343])
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_backlight@fade:
- shard-tglu: NOTRUN -> [SKIP][373] ([i915#9812]) +1 other test skip
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-5/igt@kms_pm_backlight@fade.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-rkl: NOTRUN -> [SKIP][374] ([i915#5354]) +1 other test skip
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_pm_backlight@fade-with-dpms.html
- shard-dg1: NOTRUN -> [SKIP][375] ([i915#5354])
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-19/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2-9: NOTRUN -> [SKIP][376] ([i915#9685]) +1 other test skip
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc5-dpms-negative:
- shard-rkl: [PASS][377] -> [DMESG-WARN][378] ([i915#12964]) +22 other tests dmesg-warn
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@kms_pm_dc@dc5-dpms-negative.html
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_pm_dc@dc5-dpms-negative.html
* igt@kms_pm_dc@dc5-psr:
- shard-dg2: NOTRUN -> [SKIP][379] ([i915#9685])
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@kms_pm_dc@dc5-psr.html
- shard-tglu-1: NOTRUN -> [SKIP][380] ([i915#9685])
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_pm_dc@dc5-psr.html
- shard-dg1: NOTRUN -> [SKIP][381] ([i915#9685])
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: [PASS][382] -> [SKIP][383] ([i915#15073]) +2 other tests skip
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg2-4/igt@kms_pm_rpm@dpms-lpsp.html
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@fences:
- shard-dg1: NOTRUN -> [SKIP][384] ([i915#4077]) +4 other tests skip
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_pm_rpm@fences.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2: NOTRUN -> [SKIP][385] ([i915#15073])
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-tglu: NOTRUN -> [SKIP][386] ([i915#15073])
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-7/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [PASS][387] -> [SKIP][388] ([i915#15073]) +1 other test skip
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@system-suspend-modeset:
- shard-glk: NOTRUN -> [INCOMPLETE][389] ([i915#10553])
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk6/igt@kms_pm_rpm@system-suspend-modeset.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][390] ([i915#6524] / [i915#6805])
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-3/igt@kms_prime@basic-crc-hybrid.html
- shard-dg1: NOTRUN -> [SKIP][391] ([i915#6524])
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
- shard-rkl: NOTRUN -> [SKIP][392] ([i915#11520]) +2 other tests skip
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
- shard-glk: NOTRUN -> [SKIP][393] ([i915#11520]) +4 other tests skip
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk1/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
- shard-tglu-1: NOTRUN -> [SKIP][394] ([i915#11520]) +3 other tests skip
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][395] ([i915#11520] / [i915#14544]) +2 other tests skip
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html
- shard-dg1: NOTRUN -> [SKIP][396] ([i915#11520]) +2 other tests skip
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-18/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html
- shard-snb: NOTRUN -> [SKIP][397] ([i915#11520]) +1 other test skip
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-snb1/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html
- shard-tglu: NOTRUN -> [SKIP][398] ([i915#11520]) +1 other test skip
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-9/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][399] ([i915#9808])
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-8/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][400] ([i915#12316]) +2 other tests skip
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-8/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][401] ([i915#11520]) +8 other tests skip
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area:
- shard-glk10: NOTRUN -> [SKIP][402] ([i915#11520]) +4 other tests skip
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk10/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
- shard-dg2-9: NOTRUN -> [SKIP][403] ([i915#11520]) +7 other tests skip
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-rkl: NOTRUN -> [SKIP][404] ([i915#9683])
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_psr2_su@page_flip-p010.html
- shard-tglu: NOTRUN -> [SKIP][405] ([i915#9683])
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-8/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-pr-sprite-plane-onoff:
- shard-mtlp: NOTRUN -> [SKIP][406] ([i915#9688]) +5 other tests skip
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
* igt@kms_psr@fbc-pr-suspend:
- shard-rkl: NOTRUN -> [SKIP][407] ([i915#1072] / [i915#14544] / [i915#9732]) +2 other tests skip
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_psr@fbc-pr-suspend.html
- shard-dg1: NOTRUN -> [SKIP][408] ([i915#1072] / [i915#4423] / [i915#9732])
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-15/igt@kms_psr@fbc-pr-suspend.html
* igt@kms_psr@fbc-psr-cursor-plane-move:
- shard-dg2: NOTRUN -> [SKIP][409] ([i915#1072] / [i915#9732]) +21 other tests skip
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@kms_psr@fbc-psr-cursor-plane-move.html
* igt@kms_psr@fbc-psr2-cursor-render:
- shard-dg2-9: NOTRUN -> [SKIP][410] ([i915#1072] / [i915#9732]) +16 other tests skip
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_psr@fbc-psr2-cursor-render.html
* igt@kms_psr@pr-primary-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][411] ([i915#1072] / [i915#9732]) +8 other tests skip
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-13/igt@kms_psr@pr-primary-mmap-gtt.html
* igt@kms_psr@psr-sprite-blt:
- shard-tglu: NOTRUN -> [SKIP][412] ([i915#9732]) +5 other tests skip
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-8/igt@kms_psr@psr-sprite-blt.html
* igt@kms_psr@psr2-cursor-blt:
- shard-tglu-1: NOTRUN -> [SKIP][413] ([i915#9732]) +7 other tests skip
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_psr@psr2-cursor-blt.html
* igt@kms_psr@psr2-cursor-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][414] ([i915#1072] / [i915#9732]) +9 other tests skip
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_psr@psr2-cursor-mmap-gtt.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-mtlp: NOTRUN -> [SKIP][415] ([i915#12755])
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-8/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-tglu-1: NOTRUN -> [SKIP][416] ([i915#5289])
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][417] ([i915#12755] / [i915#5190]) +1 other test skip
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-tglu: NOTRUN -> [SKIP][418] ([i915#5289])
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][419] ([i915#12755])
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-6/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-dg2-9: NOTRUN -> [SKIP][420] ([i915#12755])
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_selftest@drm_cmdline_parser:
- shard-tglu: NOTRUN -> [FAIL][421] ([i915#15119]) +2 other tests fail
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-7/igt@kms_selftest@drm_cmdline_parser.html
* igt@kms_selftest@drm_cmdline_parser@drm_test_cmdline_tv_options:
- shard-glk: NOTRUN -> [FAIL][422] ([i915#15119]) +2 other tests fail
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk1/igt@kms_selftest@drm_cmdline_parser@drm_test_cmdline_tv_options.html
- shard-rkl: NOTRUN -> [FAIL][423] ([i915#15119]) +2 other tests fail
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_selftest@drm_cmdline_parser@drm_test_cmdline_tv_options.html
* igt@kms_setmode@basic:
- shard-snb: [PASS][424] -> [FAIL][425] ([i915#15106]) +1 other test fail
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-snb5/igt@kms_setmode@basic.html
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-snb6/igt@kms_setmode@basic.html
- shard-tglu: [PASS][426] -> [FAIL][427] ([i915#15106]) +2 other tests fail
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-tglu-8/igt@kms_setmode@basic.html
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-4/igt@kms_setmode@basic.html
- shard-mtlp: [PASS][428] -> [FAIL][429] ([i915#15106]) +1 other test fail
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-mtlp-6/igt@kms_setmode@basic.html
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@kms_setmode@basic.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglu-1: NOTRUN -> [SKIP][430] ([i915#8623])
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@flipline:
- shard-dg2-9: NOTRUN -> [SKIP][431] ([i915#3555]) +8 other tests skip
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_vrr@flipline.html
* igt@kms_vrr@negative-basic:
- shard-dg2-9: NOTRUN -> [SKIP][432] ([i915#3555] / [i915#9906])
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-dg2-9: NOTRUN -> [SKIP][433] ([i915#9906])
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-rkl: NOTRUN -> [SKIP][434] ([i915#9906])
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_vrr@seamless-rr-switch-vrr.html
- shard-tglu: NOTRUN -> [SKIP][435] ([i915#9906])
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-8/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-fb-id:
- shard-glk: NOTRUN -> [SKIP][436] ([i915#2437])
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk1/igt@kms_writeback@writeback-fb-id.html
- shard-rkl: NOTRUN -> [SKIP][437] ([i915#2437])
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-tglu-1: NOTRUN -> [SKIP][438] ([i915#2437] / [i915#9412])
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-dg2: NOTRUN -> [SKIP][439] ([i915#2437] / [i915#9412]) +1 other test skip
[439]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@kms_writeback@writeback-pixel-formats.html
- shard-dg1: NOTRUN -> [SKIP][440] ([i915#2437] / [i915#9412]) +1 other test skip
[440]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-17/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2: NOTRUN -> [SKIP][441] ([i915#2436])
[441]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@mi-rpc:
- shard-dg2: NOTRUN -> [SKIP][442] ([i915#2434])
[442]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@perf@mi-rpc.html
* igt@perf_pmu@event-wait:
- shard-mtlp: NOTRUN -> [SKIP][443] ([i915#8807])
[443]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-3/igt@perf_pmu@event-wait.html
* igt@perf_pmu@event-wait@rcs0:
- shard-rkl: NOTRUN -> [SKIP][444] +7 other tests skip
[444]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@perf_pmu@event-wait@rcs0.html
- shard-mtlp: NOTRUN -> [SKIP][445] ([i915#3555] / [i915#8807])
[445]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-3/igt@perf_pmu@event-wait@rcs0.html
* igt@perf_pmu@frequency@gt0:
- shard-dg2-9: NOTRUN -> [FAIL][446] ([i915#12549] / [i915#6806]) +1 other test fail
[446]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@perf_pmu@frequency@gt0.html
* igt@perf_pmu@module-unload:
- shard-tglu-1: NOTRUN -> [FAIL][447] ([i915#14433])
[447]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-1/igt@perf_pmu@module-unload.html
- shard-glk10: NOTRUN -> [FAIL][448] ([i915#14433])
[448]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-glk10/igt@perf_pmu@module-unload.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg2: NOTRUN -> [SKIP][449] ([i915#8516]) +1 other test skip
[449]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@render-node-busy-idle:
- shard-mtlp: [PASS][450] -> [FAIL][451] ([i915#4349]) +2 other tests fail
[450]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-mtlp-7/igt@perf_pmu@render-node-busy-idle.html
[451]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-2/igt@perf_pmu@render-node-busy-idle.html
* igt@prime_mmap@test_aperture_limit:
- shard-dg2: NOTRUN -> [SKIP][452] ([i915#14121]) +1 other test skip
[452]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-7/igt@prime_mmap@test_aperture_limit.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg1: NOTRUN -> [SKIP][453] ([i915#14121]) +1 other test skip
[453]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-16/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
- shard-mtlp: NOTRUN -> [SKIP][454] ([i915#14121]) +1 other test skip
[454]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@prime_vgem@basic-fence-mmap:
- shard-dg2-9: NOTRUN -> [SKIP][455] ([i915#3708] / [i915#4077])
[455]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][456] ([i915#3291] / [i915#3708])
[456]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- shard-dg2-9: NOTRUN -> [SKIP][457] ([i915#3291] / [i915#3708])
[457]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@prime_vgem@basic-read.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> [SKIP][458] ([i915#3708] / [i915#4077])
[458]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-5/igt@prime_vgem@coherency-gtt.html
- shard-mtlp: NOTRUN -> [SKIP][459] ([i915#3708] / [i915#4077])
[459]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-6/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-flip-hang:
- shard-dg2: NOTRUN -> [SKIP][460] ([i915#3708])
[460]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-1/igt@prime_vgem@fence-flip-hang.html
* igt@prime_vgem@fence-read-hang:
- shard-dg2-9: NOTRUN -> [SKIP][461] ([i915#3708])
[461]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@prime_vgem@fence-read-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][462] ([i915#9917])
[462]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@bind-unbind-vf@vf-4:
- shard-tglu: NOTRUN -> [FAIL][463] ([i915#12910]) +9 other tests fail
[463]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-8/igt@sriov_basic@bind-unbind-vf@vf-4.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-dg2-9: NOTRUN -> [SKIP][464] ([i915#9917]) +1 other test skip
[464]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@sriov_basic@enable-vfs-autoprobe-on.html
- shard-dg1: NOTRUN -> [SKIP][465] ([i915#9917])
[465]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-18/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@tools_test@sysfs_l3_parity:
- shard-dg2-9: NOTRUN -> [SKIP][466] ([i915#4818])
[466]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-9/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@fbdev@nullptr:
- shard-rkl: [SKIP][467] ([i915#14544] / [i915#2582]) -> [PASS][468] +1 other test pass
[467]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@fbdev@nullptr.html
[468]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@fbdev@nullptr.html
* igt@gem_eio@hibernate:
- shard-tglu: [FAIL][469] ([i915#15136]) -> [PASS][470]
[469]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-tglu-6/igt@gem_eio@hibernate.html
[470]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-8/igt@gem_eio@hibernate.html
- shard-mtlp: [FAIL][471] ([Intel XE#6339] / [i915#15136]) -> [PASS][472]
[471]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-mtlp-6/igt@gem_eio@hibernate.html
[472]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-5/igt@gem_eio@hibernate.html
- shard-rkl: [FAIL][473] ([i915#15136]) -> [PASS][474]
[473]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-7/igt@gem_eio@hibernate.html
[474]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@gem_eio@hibernate.html
* igt@gem_mmap_offset@clear-via-pagefault:
- shard-mtlp: [ABORT][475] ([i915#13427]) -> [PASS][476] +1 other test pass
[475]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-mtlp-8/igt@gem_mmap_offset@clear-via-pagefault.html
[476]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-mtlp-2/igt@gem_mmap_offset@clear-via-pagefault.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-rkl: [TIMEOUT][477] ([i915#12917] / [i915#12964]) -> [PASS][478]
[477]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@gem_pxp@reject-modify-context-protection-off-1.html
[478]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_workarounds@suspend-resume:
- shard-rkl: [INCOMPLETE][479] ([i915#13356]) -> [PASS][480]
[479]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@gem_workarounds@suspend-resume.html
[480]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@gem_workarounds@suspend-resume.html
* igt@i915_module_load@reload-no-display:
- shard-dg1: [DMESG-WARN][481] ([i915#13029] / [i915#14545]) -> [PASS][482]
[481]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg1-15/igt@i915_module_load@reload-no-display.html
[482]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@i915_module_load@reload-no-display.html
* igt@kms_color@degamma:
- shard-rkl: [SKIP][483] ([i915#12655] / [i915#14544]) -> [PASS][484] +1 other test pass
[483]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_color@degamma.html
[484]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_color@degamma.html
* igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
- shard-rkl: [FAIL][485] ([i915#13566]) -> [PASS][486] +2 other tests pass
[485]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-7/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html
[486]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1:
- shard-tglu: [FAIL][487] ([i915#13566]) -> [PASS][488] +3 other tests pass
[487]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-tglu-4/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1.html
[488]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-tglu-6/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- shard-rkl: [SKIP][489] ([i915#11190] / [i915#14544]) -> [PASS][490] +4 other tests pass
[489]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
[490]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-rkl: [SKIP][491] ([i915#14544]) -> [PASS][492] +45 other tests pass
[491]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_draw_crc@draw-method-mmap-gtt.html
[492]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_flip@bo-too-big-interruptible:
- shard-rkl: [SKIP][493] ([i915#14544] / [i915#3637]) -> [PASS][494] +7 other tests pass
[493]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_flip@bo-too-big-interruptible.html
[494]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_flip@bo-too-big-interruptible.html
* igt@kms_flip@flip-vs-dpms-on-nop:
- shard-rkl: [SKIP][495] ([i915#14544] / [i915#14553]) -> [PASS][496]
[495]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_flip@flip-vs-dpms-on-nop.html
[496]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@kms_flip@flip-vs-dpms-on-nop.html
* igt@kms_flip_event_leak@basic:
- shard-dg1: [DMESG-WARN][497] ([i915#4423]) -> [PASS][498] +2 other tests pass
[497]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg1-16/igt@kms_flip_event_leak@basic.html
[498]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-18/igt@kms_flip_event_leak@basic.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- shard-rkl: [SKIP][499] ([i915#14544] / [i915#3555]) -> [PASS][500] +1 other test pass
[499]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
[500]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-blt:
- shard-rkl: [SKIP][501] ([i915#14544] / [i915#1849] / [i915#5354]) -> [PASS][502] +2 other tests pass
[501]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-blt.html
[502]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-blt.html
* igt@kms_hdmi_inject@inject-audio:
- shard-snb: [SKIP][503] -> [PASS][504]
[503]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-snb5/igt@kms_hdmi_inject@inject-audio.html
[504]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-snb1/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_invalid_mode@clock-too-high:
- shard-rkl: [SKIP][505] ([i915#14544] / [i915#3555] / [i915#8826]) -> [PASS][506]
[505]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_invalid_mode@clock-too-high.html
[506]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_invalid_mode@clock-too-high.html
* igt@kms_plane_alpha_blend@alpha-basic:
- shard-rkl: [SKIP][507] ([i915#14544] / [i915#7294]) -> [PASS][508]
[507]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_plane_alpha_blend@alpha-basic.html
[508]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_plane_alpha_blend@alpha-basic.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers:
- shard-rkl: [SKIP][509] ([i915#14544] / [i915#8152]) -> [PASS][510] +1 other test pass
[509]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html
[510]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20:
- shard-rkl: [SKIP][511] ([i915#12247] / [i915#14544] / [i915#8152]) -> [PASS][512] +5 other tests pass
[511]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20.html
[512]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5:
- shard-rkl: [SKIP][513] ([i915#12247] / [i915#14544] / [i915#3555] / [i915#6953] / [i915#8152]) -> [PASS][514] +1 other test pass
[513]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
[514]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a:
- shard-rkl: [SKIP][515] ([i915#12247] / [i915#14544]) -> [PASS][516] +4 other tests pass
[515]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a.html
[516]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a.html
* igt@kms_pm_rpm@basic-rte:
- shard-rkl: [DMESG-FAIL][517] ([i915#12964]) -> [PASS][518]
[517]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_pm_rpm@basic-rte.html
[518]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_pm_rpm@basic-rte.html
* igt@kms_pm_rpm@cursor-dpms:
- shard-rkl: [SKIP][519] ([i915#14544] / [i915#1849]) -> [PASS][520]
[519]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_pm_rpm@cursor-dpms.html
[520]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_pm_rpm@cursor-dpms.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-rkl: [SKIP][521] ([i915#15073]) -> [PASS][522]
[521]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_pm_rpm@dpms-non-lpsp.html
[522]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_prime@basic-crc-vgem:
- shard-rkl: [SKIP][523] ([i915#14544] / [i915#6524]) -> [PASS][524]
[523]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_prime@basic-crc-vgem.html
[524]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_prime@basic-crc-vgem.html
* igt@kms_vblank@wait-forked-busy-hang:
- shard-rkl: [DMESG-WARN][525] ([i915#12964]) -> [PASS][526] +23 other tests pass
[525]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_vblank@wait-forked-busy-hang.html
[526]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_vblank@wait-forked-busy-hang.html
#### Warnings ####
* igt@gem_ccs@large-ctrl-surf-copy:
- shard-rkl: [SKIP][527] ([i915#13008] / [i915#14544]) -> [SKIP][528] ([i915#13008])
[527]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@gem_ccs@large-ctrl-surf-copy.html
[528]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@gem_ccs@large-ctrl-surf-copy.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: [SKIP][529] ([i915#14544] / [i915#7697]) -> [SKIP][530] ([i915#7697])
[529]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@gem_close_race@multigpu-basic-process.html
[530]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-rkl: [SKIP][531] ([i915#7697]) -> [SKIP][532] ([i915#14544] / [i915#7697])
[531]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@gem_close_race@multigpu-basic-threads.html
[532]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-rkl: [SKIP][533] ([i915#14544] / [i915#4525]) -> [SKIP][534] ([i915#4525])
[533]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@gem_exec_balancer@parallel-contexts.html
[534]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-rkl: [SKIP][535] ([i915#6334]) -> [SKIP][536] ([i915#14544] / [i915#6334]) +1 other test skip
[535]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@gem_exec_capture@capture-invisible@smem0.html
[536]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_reloc@basic-cpu-noreloc:
- shard-rkl: [SKIP][537] ([i915#14544] / [i915#3281]) -> [SKIP][538] ([i915#3281]) +4 other tests skip
[537]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-noreloc.html
[538]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@gem_exec_reloc@basic-cpu-noreloc.html
* igt@gem_exec_reloc@basic-softpin:
- shard-rkl: [SKIP][539] ([i915#3281]) -> [SKIP][540] ([i915#14544] / [i915#3281]) +3 other tests skip
[539]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@gem_exec_reloc@basic-softpin.html
[540]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_exec_reloc@basic-softpin.html
* igt@gem_exec_suspend@basic-s3:
- shard-rkl: [ABORT][541] ([i915#15131]) -> [INCOMPLETE][542] ([i915#13356]) +1 other test incomplete
[541]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-4/igt@gem_exec_suspend@basic-s3.html
[542]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-3/igt@gem_exec_suspend@basic-s3.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-rkl: [SKIP][543] ([i915#14544] / [i915#4613]) -> [SKIP][544] ([i915#4613]) +3 other tests skip
[543]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
[544]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-3/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-rkl: [SKIP][545] ([i915#4613]) -> [SKIP][546] ([i915#14544] / [i915#4613]) +2 other tests skip
[545]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@gem_lmem_swapping@heavy-verify-random.html
[546]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_partial_pwrite_pread@reads:
- shard-rkl: [SKIP][547] ([i915#14544] / [i915#3282]) -> [SKIP][548] ([i915#3282]) +3 other tests skip
[547]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@gem_partial_pwrite_pread@reads.html
[548]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-rkl: [SKIP][549] ([i915#3282]) -> [SKIP][550] ([i915#14544] / [i915#3282]) +4 other tests skip
[549]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@gem_partial_pwrite_pread@reads-uncached.html
[550]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_pxp@create-regular-context-1:
- shard-rkl: [SKIP][551] ([i915#4270]) -> [TIMEOUT][552] ([i915#12917] / [i915#12964])
[551]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-7/igt@gem_pxp@create-regular-context-1.html
[552]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@hw-rejects-pxp-buffer:
- shard-rkl: [TIMEOUT][553] ([i915#12917] / [i915#12964]) -> [FAIL][554] ([i915#15138])
[553]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@gem_pxp@hw-rejects-pxp-buffer.html
[554]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@gem_pxp@hw-rejects-pxp-buffer.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-rkl: [TIMEOUT][555] ([i915#12964]) -> [SKIP][556] ([i915#14544] / [i915#4270])
[555]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@gem_pxp@regular-baseline-src-copy-readible.html
[556]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-rkl: [SKIP][557] ([i915#14544] / [i915#3297]) -> [SKIP][558] ([i915#3297])
[557]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@gem_userptr_blits@unsync-unmap-cycles.html
[558]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen9_exec_parse@allowed-all:
- shard-rkl: [SKIP][559] ([i915#2527]) -> [SKIP][560] ([i915#14544] / [i915#2527])
[559]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@gen9_exec_parse@allowed-all.html
[560]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-rkl: [SKIP][561] ([i915#14544] / [i915#2527]) -> [SKIP][562] ([i915#2527]) +1 other test skip
[561]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@gen9_exec_parse@allowed-single.html
[562]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-rkl: [SKIP][563] ([i915#14544] / [i915#8399]) -> [SKIP][564] ([i915#8399])
[563]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@i915_pm_freq_api@freq-basic-api.html
[564]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-rkl: [SKIP][565] -> [SKIP][566] ([i915#13328])
[565]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
[566]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@system-suspend:
- shard-rkl: [ABORT][567] -> [INCOMPLETE][568] ([i915#13356])
[567]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-4/igt@i915_pm_rpm@system-suspend.html
[568]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-3/igt@i915_pm_rpm@system-suspend.html
* igt@i915_pm_sseu@full-enable:
- shard-rkl: [SKIP][569] ([i915#14544] / [i915#4387]) -> [SKIP][570] ([i915#4387])
[569]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@i915_pm_sseu@full-enable.html
[570]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@hwconfig_table:
- shard-rkl: [SKIP][571] ([i915#6245]) -> [SKIP][572] ([i915#14544] / [i915#6245])
[571]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@i915_query@hwconfig_table.html
[572]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@i915_query@hwconfig_table.html
* igt@intel_hwmon@hwmon-read:
- shard-rkl: [SKIP][573] ([i915#14544] / [i915#7707]) -> [SKIP][574] ([i915#7707])
[573]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@intel_hwmon@hwmon-read.html
[574]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@intel_hwmon@hwmon-read.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-rkl: [SKIP][575] ([i915#14544]) -> [SKIP][576] ([i915#5286]) +5 other tests skip
[575]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
[576]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-rkl: [SKIP][577] ([i915#5286]) -> [SKIP][578] ([i915#14544]) +3 other tests skip
[577]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
[578]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-rkl: [SKIP][579] ([i915#3638]) -> [SKIP][580] ([i915#14544])
[579]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
[580]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-rkl: [SKIP][581] ([i915#14544]) -> [SKIP][582] ([i915#3638]) +3 other tests skip
[581]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
[582]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-rkl: [SKIP][583] -> [SKIP][584] ([i915#14544]) +8 other tests skip
[583]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[584]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
- shard-dg1: [SKIP][585] ([i915#4538]) -> [SKIP][586] ([i915#4423] / [i915#4538])
[585]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg1-15/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
[586]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-15/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
- shard-rkl: [SKIP][587] ([i915#14544]) -> [SKIP][588] ([i915#14098] / [i915#6095]) +11 other tests skip
[587]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
[588]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
- shard-rkl: [SKIP][589] ([i915#14544]) -> [SKIP][590] ([i915#12313])
[589]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
[590]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-b-hdmi-a-2:
- shard-rkl: [SKIP][591] ([i915#6095]) -> [SKIP][592] ([i915#14098] / [i915#6095]) +1 other test skip
[591]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-b-hdmi-a-2.html
[592]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: [SKIP][593] ([i915#14098] / [i915#6095]) -> [SKIP][594] ([i915#6095]) +1 other test skip
[593]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html
[594]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs:
- shard-rkl: [SKIP][595] ([i915#14098] / [i915#6095]) -> [SKIP][596] ([i915#14544]) +8 other tests skip
[595]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html
[596]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4:
- shard-dg1: [SKIP][597] ([i915#4423] / [i915#6095]) -> [SKIP][598] ([i915#6095]) +3 other tests skip
[597]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg1-17/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4.html
[598]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-14/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4.html
* igt@kms_cdclk@plane-scaling:
- shard-rkl: [SKIP][599] ([i915#3742]) -> [SKIP][600] ([i915#14544] / [i915#3742])
[599]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_cdclk@plane-scaling.html
[600]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-rkl: [SKIP][601] ([i915#11151] / [i915#7828]) -> [SKIP][602] ([i915#11151] / [i915#14544] / [i915#7828]) +2 other tests skip
[601]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
[602]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-rkl: [SKIP][603] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][604] ([i915#11151] / [i915#7828]) +5 other tests skip
[603]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_chamelium_hpd@vga-hpd-fast.html
[604]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_content_protection@content-type-change:
- shard-rkl: [SKIP][605] ([i915#9424]) -> [SKIP][606] ([i915#14544])
[605]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_content_protection@content-type-change.html
[606]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-rkl: [SKIP][607] ([i915#3116]) -> [SKIP][608] ([i915#14544])
[607]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_content_protection@dp-mst-type-1.html
[608]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: [SKIP][609] ([i915#9424]) -> [SKIP][610] ([i915#9433])
[609]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg1-14/igt@kms_content_protection@mei-interface.html
[610]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@kms_content_protection@mei-interface.html
* igt@kms_cursor_crc@cursor-random-256x85:
- shard-rkl: [DMESG-WARN][611] ([i915#12964]) -> [FAIL][612] ([i915#13566])
[611]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_cursor_crc@cursor-random-256x85.html
[612]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_cursor_crc@cursor-random-256x85.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-rkl: [SKIP][613] ([i915#13049]) -> [SKIP][614] ([i915#14544])
[613]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_cursor_crc@cursor-random-512x170.html
[614]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-sliding-256x85:
- shard-rkl: [SKIP][615] ([i915#14544]) -> [FAIL][616] ([i915#13566])
[615]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-256x85.html
[616]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-256x85.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-rkl: [SKIP][617] ([i915#14544]) -> [SKIP][618] ([i915#3555]) +6 other tests skip
[617]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-32x10.html
[618]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_edge_walk@128x128-top-edge:
- shard-rkl: [SKIP][619] ([i915#14544]) -> [DMESG-WARN][620] ([i915#12964])
[619]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_cursor_edge_walk@128x128-top-edge.html
[620]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@kms_cursor_edge_walk@128x128-top-edge.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-rkl: [SKIP][621] ([i915#11190] / [i915#14544]) -> [SKIP][622] ([i915#4103])
[621]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[622]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-rkl: [SKIP][623] ([i915#14544]) -> [SKIP][624] +21 other tests skip
[623]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
[624]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-rkl: [SKIP][625] ([i915#14544]) -> [FAIL][626] ([i915#2346])
[625]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[626]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-rkl: [FAIL][627] ([i915#2346]) -> [DMESG-WARN][628] ([i915#12964])
[627]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[628]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-rkl: [SKIP][629] ([i915#4103]) -> [SKIP][630] ([i915#14544])
[629]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
[630]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_display_modes@extended-mode-basic:
- shard-rkl: [SKIP][631] ([i915#14544]) -> [SKIP][632] ([i915#13691])
[631]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_display_modes@extended-mode-basic.html
[632]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-3/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-rkl: [SKIP][633] ([i915#14544]) -> [SKIP][634] ([i915#13707])
[633]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
[634]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-rkl: [SKIP][635] ([i915#14544]) -> [SKIP][636] ([i915#3840])
[635]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp.html
[636]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-rkl: [SKIP][637] ([i915#3840]) -> [SKIP][638] ([i915#14544])
[637]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
[638]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-rkl: [SKIP][639] ([i915#14544]) -> [SKIP][640] ([i915#3555] / [i915#3840]) +1 other test skip
[639]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_dsc@dsc-with-bpc-formats.html
[640]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][641] ([i915#14544] / [i915#3955]) -> [SKIP][642] ([i915#3955])
[641]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
[642]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@display-3x:
- shard-rkl: [SKIP][643] ([i915#14544] / [i915#1839]) -> [SKIP][644] ([i915#1839])
[643]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_feature_discovery@display-3x.html
[644]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_feature_discovery@display-3x.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-rkl: [SKIP][645] ([i915#9934]) -> [SKIP][646] ([i915#14544] / [i915#9934]) +3 other tests skip
[645]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_flip@2x-absolute-wf_vblank.html
[646]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-rkl: [SKIP][647] ([i915#14544] / [i915#9934]) -> [SKIP][648] ([i915#9934]) +7 other tests skip
[647]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
[648]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-rkl: [SKIP][649] ([i915#14544] / [i915#3555]) -> [SKIP][650] ([i915#2672] / [i915#3555]) +3 other tests skip
[649]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
[650]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-rkl: [SKIP][651] ([i915#2672] / [i915#3555]) -> [SKIP][652] ([i915#14544] / [i915#3555]) +3 other tests skip
[651]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
[652]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt:
- shard-rkl: [SKIP][653] ([i915#14544]) -> [SKIP][654] ([i915#15102]) +1 other test skip
[653]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
[654]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-dg2: [SKIP][655] ([i915#15102] / [i915#3458]) -> [SKIP][656] ([i915#10433] / [i915#15102] / [i915#3458])
[655]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
[656]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-rkl: [SKIP][657] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][658] ([i915#15102] / [i915#3023]) +15 other tests skip
[657]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
[658]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-rkl: [SKIP][659] ([i915#1825]) -> [SKIP][660] ([i915#14544] / [i915#1849] / [i915#5354]) +20 other tests skip
[659]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
[660]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite:
- shard-dg1: [SKIP][661] -> [SKIP][662] ([i915#4423])
[661]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite.html
[662]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-rkl: [SKIP][663] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][664] ([i915#1825]) +40 other tests skip
[663]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
[664]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu:
- shard-rkl: [SKIP][665] ([i915#15102] / [i915#3023]) -> [SKIP][666] ([i915#14544] / [i915#1849] / [i915#5354]) +12 other tests skip
[665]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html
[666]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt:
- shard-rkl: [SKIP][667] ([i915#15102]) -> [SKIP][668] ([i915#14544]) +2 other tests skip
[667]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html
[668]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
- shard-dg1: [SKIP][669] ([i915#15102] / [i915#3458]) -> [SKIP][670] ([i915#15102] / [i915#3458] / [i915#4423])
[669]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
[670]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
- shard-dg2: [SKIP][671] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][672] ([i915#15102] / [i915#3458]) +1 other test skip
[671]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html
[672]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-rkl: [SKIP][673] ([i915#3555] / [i915#8228]) -> [SKIP][674] ([i915#14544])
[673]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_hdr@bpc-switch-suspend.html
[674]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-rkl: [SKIP][675] ([i915#13688] / [i915#14544]) -> [SKIP][676] ([i915#13688])
[675]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_joiner@basic-max-non-joiner.html
[676]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-dg1: [SKIP][677] ([i915#12339]) -> [SKIP][678] ([i915#12339] / [i915#4423])
[677]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg1-15/igt@kms_joiner@invalid-modeset-ultra-joiner.html
[678]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-12/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_pipe_stress@stress-xrgb8888-yftiled:
- shard-rkl: [SKIP][679] ([i915#14544]) -> [SKIP][680] ([i915#14712])
[679]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
[680]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
* igt@kms_plane_lowres@tiling-yf:
- shard-rkl: [SKIP][681] ([i915#3555]) -> [SKIP][682] ([i915#14544]) +1 other test skip
[681]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_plane_lowres@tiling-yf.html
[682]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@2x-tiling-4:
- shard-rkl: [SKIP][683] ([i915#13958]) -> [SKIP][684] ([i915#14544])
[683]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_plane_multiple@2x-tiling-4.html
[684]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-4.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-rkl: [SKIP][685] ([i915#14544]) -> [SKIP][686] ([i915#13958])
[685]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-y.html
[686]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-4/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-b:
- shard-rkl: [SKIP][687] ([i915#12247] / [i915#14544] / [i915#8152]) -> [SKIP][688] ([i915#12247]) +5 other tests skip
[687]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-b.html
[688]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-b.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
- shard-rkl: [SKIP][689] ([i915#12247] / [i915#14544]) -> [SKIP][690] ([i915#12247]) +2 other tests skip
[689]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html
[690]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: [SKIP][691] ([i915#3361]) -> [FAIL][692] ([i915#9295])
[691]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html
[692]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][693] ([i915#4281]) -> [SKIP][694] ([i915#14544] / [i915#4281])
[693]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-4/igt@kms_pm_dc@dc9-dpms.html
[694]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [SKIP][695] ([i915#9340]) -> [SKIP][696] ([i915#14544] / [i915#9340])
[695]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_pm_lpsp@kms-lpsp.html
[696]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [SKIP][697] ([i915#14544] / [i915#15073]) -> [SKIP][698] ([i915#15073]) +1 other test skip
[697]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp-stress.html
[698]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: [SKIP][699] ([i915#15073]) -> [SKIP][700] ([i915#14544] / [i915#15073])
[699]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp.html
[700]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_prime@basic-crc-hybrid:
- shard-rkl: [SKIP][701] ([i915#14544] / [i915#6524]) -> [SKIP][702] ([i915#6524])
[701]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_prime@basic-crc-hybrid.html
[702]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
- shard-rkl: [SKIP][703] ([i915#11520]) -> [SKIP][704] ([i915#11520] / [i915#14544]) +1 other test skip
[703]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html
[704]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
- shard-rkl: [SKIP][705] ([i915#11520] / [i915#14544]) -> [SKIP][706] ([i915#11520]) +8 other tests skip
[705]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
[706]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr@fbc-psr2-sprite-render:
- shard-rkl: [SKIP][707] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][708] ([i915#1072] / [i915#9732]) +17 other tests skip
[707]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_psr@fbc-psr2-sprite-render.html
[708]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_psr@fbc-psr2-sprite-render.html
* igt@kms_psr@psr-sprite-blt:
- shard-dg1: [SKIP][709] ([i915#1072] / [i915#4423] / [i915#9732]) -> [SKIP][710] ([i915#1072] / [i915#9732])
[709]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-dg1-17/igt@kms_psr@psr-sprite-blt.html
[710]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-dg1-13/igt@kms_psr@psr-sprite-blt.html
* igt@kms_psr@psr2-cursor-blt:
- shard-rkl: [SKIP][711] ([i915#1072] / [i915#9732]) -> [SKIP][712] ([i915#1072] / [i915#14544] / [i915#9732]) +8 other tests skip
[711]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-8/igt@kms_psr@psr2-cursor-blt.html
[712]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_psr@psr2-cursor-blt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-rkl: [SKIP][713] ([i915#9685]) -> [SKIP][714] ([i915#14544] / [i915#9685])
[713]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[714]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-rkl: [SKIP][715] ([i915#5289]) -> [SKIP][716] ([i915#14544])
[715]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
[716]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-rkl: [SKIP][717] ([i915#14544]) -> [SKIP][718] ([i915#5289])
[717]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
[718]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-rkl: [SKIP][719] ([i915#14544] / [i915#3555]) -> [SKIP][720] ([i915#3555])
[719]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
[720]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_vrr@flip-basic-fastset:
- shard-rkl: [SKIP][721] ([i915#9906]) -> [SKIP][722] ([i915#14544])
[721]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-7/igt@kms_vrr@flip-basic-fastset.html
[722]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-rkl: [SKIP][723] ([i915#14544]) -> [SKIP][724] ([i915#9906])
[723]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_vrr@seamless-rr-switch-drrs.html
[724]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-7/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-rkl: [SKIP][725] ([i915#14544] / [i915#2437] / [i915#9412]) -> [SKIP][726] ([i915#2437] / [i915#9412])
[725]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@kms_writeback@writeback-check-output-xrgb2101010.html
[726]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-rkl: [SKIP][727] ([i915#14544] / [i915#2436]) -> [SKIP][728] ([i915#2436])
[727]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@perf@gen8-unprivileged-single-ctx-counters.html
[728]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@mi-rpc:
- shard-rkl: [SKIP][729] ([i915#14544] / [i915#2434]) -> [SKIP][730] ([i915#2434])
[729]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@perf@mi-rpc.html
[730]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@perf@mi-rpc.html
* igt@perf_pmu@rc6-all-gts:
- shard-rkl: [SKIP][731] ([i915#14544] / [i915#8516]) -> [SKIP][732] ([i915#8516])
[731]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@perf_pmu@rc6-all-gts.html
[732]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-5/igt@perf_pmu@rc6-all-gts.html
* igt@prime_vgem@basic-read:
- shard-rkl: [SKIP][733] ([i915#14544] / [i915#3291] / [i915#3708]) -> [SKIP][734] ([i915#3291] / [i915#3708])
[733]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@prime_vgem@basic-read.html
[734]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@prime_vgem@basic-read.html
* igt@prime_vgem@fence-flip-hang:
- shard-rkl: [SKIP][735] ([i915#14544] / [i915#3708]) -> [SKIP][736] ([i915#3708])
[735]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@prime_vgem@fence-flip-hang.html
[736]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-2/igt@prime_vgem@fence-flip-hang.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-rkl: [SKIP][737] ([i915#9917]) -> [SKIP][738] ([i915#14544] / [i915#9917])
[737]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-5/igt@sriov_basic@enable-vfs-autoprobe-on.html
[738]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-6/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-rkl: [SKIP][739] ([i915#14544] / [i915#9917]) -> [SKIP][740] ([i915#9917])
[739]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8594/shard-rkl-6/igt@sriov_basic@enable-vfs-bind-unbind-each.html
[740]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/shard-rkl-8/igt@sriov_basic@enable-vfs-bind-unbind-each.html
[Intel XE#6339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6339
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10553]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10553
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11190
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11527
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11713
[i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
[i915#12178]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12178
[i915#12193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12193
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
[i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
[i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
[i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
[i915#12549]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12549
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
[i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
[i915#12796]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12796
[i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
[i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
[i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
[i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
[i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
[i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
[i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
[i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13328]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13328
[i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
[i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
[i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
[i915#13427]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13427
[i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
[i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
[i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
[i915#13705]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13705
[i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
[i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
[i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
[i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
[i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
[i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
[i915#14121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14121
[i915#14123]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14123
[i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
[i915#14433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14433
[i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
[i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
[i915#14553]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14553
[i915#14586]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14586
[i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
[i915#14857]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14857
[i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
[i915#15077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15077
[i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
[i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
[i915#15106]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15106
[i915#15119]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15119
[i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
[i915#15136]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15136
[i915#15138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15138
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
[i915#2065]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2065
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
[i915#4036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4036
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4818
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#5107]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5107
[i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
[i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
[i915#6806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6806
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7178]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7178
[i915#7294]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7294
[i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7862]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7862
[i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
[i915#8152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8152
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8807]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8807
[i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
[i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
[i915#8825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8825
[i915#8826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8826
[i915#8898]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8898
[i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_8594 -> IGTPW_13923
CI-20190529: 20190529
CI_DRM_17393: bee2d9e4308e4b888e2524014a246793233f75e8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_13923: 46d3e0a9b87bf7fdb50ff31d8394f9a401fac957 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8594: 8594
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13923/index.html
[-- Attachment #2: Type: text/html, Size: 242869 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH v1 1/3] lib/xe_mmio: Introduce tile-level XE MMIO access helpers
2025-10-20 16:26 ` [PATCH v1 1/3] lib/xe_mmio: Introduce tile-level XE MMIO access helpers Piórkowski, Piotr
@ 2025-10-22 11:54 ` Sokolowski, Jan
0 siblings, 0 replies; 14+ messages in thread
From: Sokolowski, Jan @ 2025-10-22 11:54 UTC (permalink / raw)
To: Piorkowski, Piotr, igt-dev@lists.freedesktop.org
Cc: Piorkowski, Piotr, Laguna, Lukasz, Marcin Bernatowicz
> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of
> Piórkowski, Piotr
> Sent: Monday, October 20, 2025 6:27 PM
> To: igt-dev@lists.freedesktop.org
> Cc: Piorkowski, Piotr <piotr.piorkowski@intel.com>; Laguna, Lukasz
> <lukasz.laguna@intel.com>; Marcin Bernatowicz
> <marcin.bernatowicz@linux.intel.com>
> Subject: [PATCH v1 1/3] lib/xe_mmio: Introduce tile-level XE MMIO access
> helpers
>
> From: Piotr Piórkowski <piotr.piorkowski@intel.com>
>
> Add new helpers for tile-based MMIO access:
> - xe_mmio_tile_read32()
> - xe_mmio_tile_read64()
> - xe_mmio_tile_write32()
> - xe_mmio_tile_write64()
>
> These functions provide explicit MMIO read/write operations within
> a given tile by applying TILE_MMIO_SIZE offsetting logic. Existing
> GT-level MMIO helpers (xe_mmio_gt_*()) are refactored to use these
> new tile-level accessors, simplifying code and improving consistency
> across MMIO operations.
> GGTT is also a per-tile resource, so let's adjust the GGTT access
> helpers to use tile IDs instead of GT.
>
> Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
> Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> ---
> lib/xe/xe_mmio.c | 94 ++++++++++++++++++++++++++--------
> lib/xe/xe_mmio.h | 20 +++++---
> lib/xe/xe_sriov_provisioning.c | 6 +--
> lib/xe/xe_sriov_provisioning.h | 2 +-
> tests/intel/xe_sriov_flr.c | 10 ++--
> 5 files changed, 95 insertions(+), 37 deletions(-)
>
> diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
> index 834816133..8bc446fb9 100644
> --- a/lib/xe/xe_mmio.c
> +++ b/lib/xe/xe_mmio.c
> @@ -107,6 +107,62 @@ void xe_mmio_write64(struct xe_mmio *mmio,
> uint32_t offset, uint64_t val)
> return iowrite64(mmio->intel_mmio.igt_mmio, offset, val);
> }
>
> +/** xe_mmio_tile_read32:
> + * @mmio: xe mmio structure for IO operations
> + * @tile: tile id
> + * @offset: mmio register offset in the tile
> + *
> + * 32-bit read of the register at @offset in the specified @tile
> + *
> + * Returns: The value read from the register.
> + */
> +uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile,
> uint32_t offset)
> +{
> + return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * tile));
> +}
> +
> +/** xe_mmio_tile_read64:
> + * @mmio: xe mmio structure for IO operations
> + * @tile: tile id
> + * @offset: mmio register offset in the @tile
> + *
> + * 64-bit read of the register at @offset in the specified @tile
> + *
> + * Returns: The value read from the register.
> + */
> +uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile,
> uint32_t offset)
> +{
> + return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * tile));
> +}
> +
> +/**
> + * xe_mmio_tile_write32:
> + * @mmio: xe mmio structure for IO operations
> + * @tile: tile id
> + * @offset: mmio register offset in the @tile
> + * @val: value to write
> + *
> + * 32-bit write to the register at @offset in the specified @tile
> + */
> +void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t
> offset, uint32_t val)
> +{
> + xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * tile), val);
> +}
> +
> +/**
> + * xe_mmio_tile_write64:
> + * @mmio: xe mmio structure for IO operations
> + * @tile: tile id
> + * @offset: mmio register offset in the @tile
> + * @val: value to write
> + *
> + * 64-bit write to the register at @offset in the specified @tile
> + */
> +void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t
> offset, uint64_t val)
> +{
> + xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * tile), val);
> +}
> +
> /**
> * xe_mmio_gt_read32:
> * @mmio: xe mmio structure for IO operations
> @@ -118,9 +174,9 @@ void xe_mmio_write64(struct xe_mmio *mmio,
> uint32_t offset, uint64_t val)
> * Returns:
> * The value read from the register.
> */
> -uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t
> offset)
> +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, uint8_t gt, uint32_t
> offset)
> {
> - return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE *
> xe_gt_get_tile_id(mmio->fd, gt)));
> + return xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd,
> gt), offset);
> }
>
> /**
> @@ -134,9 +190,9 @@ uint32_t xe_mmio_gt_read32(struct xe_mmio
> *mmio, int gt, uint32_t offset)
> * Returns:
> * The value read from the register.
> */
> -uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t
> offset)
> +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, uint8_t gt, uint32_t
> offset)
> {
> - return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE *
> xe_gt_get_tile_id(mmio->fd, gt)));
> + return xe_mmio_tile_read64(mmio, xe_gt_get_tile_id(mmio->fd,
> gt), offset);
> }
>
> /**
> @@ -148,10 +204,9 @@ uint64_t xe_mmio_gt_read64(struct xe_mmio
> *mmio, int gt, uint32_t offset)
> *
> * 32-bit write to the register at @offset in tile to which @gt belongs.
> */
> -void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset,
> uint32_t val)
> +void xe_mmio_gt_write32(struct xe_mmio *mmio, uint8_t gt, uint32_t
> offset, uint32_t val)
> {
> - return xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE *
> xe_gt_get_tile_id(mmio->fd, gt)),
> - val);
> + return xe_mmio_tile_write32(mmio, xe_gt_get_tile_id(mmio->fd,
> gt), offset, val);
> }
>
> /**
> @@ -163,38 +218,37 @@ void xe_mmio_gt_write32(struct xe_mmio *mmio,
> int gt, uint32_t offset, uint32_t
> *
> * 64-bit write to the register at @offset in tile to which @gt belongs.
> */
> -void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset,
> uint64_t val)
> +void xe_mmio_gt_write64(struct xe_mmio *mmio, uint8_t gt, uint32_t
> offset, uint64_t val)
> {
> - return xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE *
> xe_gt_get_tile_id(mmio->fd, gt)),
> - val);
> + return xe_mmio_tile_write64(mmio, xe_gt_get_tile_id(mmio->fd,
> gt), offset, val);
> }
>
> /**
> * xe_mmio_ggtt_read:
> * @mmio: xe mmio structure for IO operations
> - * @gt: gt id
> - * @offset: PTE offset from the beginning of GGTT, in tile to which @gt
> belongs
> + * @tile: tile id
> + * @offset: PTE offset from the beginning of GGTT in @tile
> *
> - * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
> + * Read of GGTT PTE at GGTT @offset in the @tile.
> *
> * Returns:
> * The value read from the register.
> */
> -xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t
> offset)
> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile,
> uint32_t offset)
> {
> - return xe_mmio_gt_read64(mmio, gt, offset +
> GGTT_OFFSET_IN_TILE);
> + return xe_mmio_tile_read64(mmio, tile, offset +
> GGTT_OFFSET_IN_TILE);
> }
>
> /**
> * xe_mmio_ggtt_write:
> * @mmio: xe mmio structure for IO operations
> - * @gt: gt id
> - * @offset: PTE offset from the beginning of GGTT, in tile to which @gt
> belongs
> + * @tile: tile id
> + * @offset: PTE offset from the beginning of GGTT in @tile
> * @pte: PTE value to write
> *
> - * Write PTE value at GGTT @offset in tile to which @gt belongs.
> + * Write PTE value at GGTT @offset in the @tile.
> */
> -void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset,
> xe_ggtt_pte_t pte)
> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t
> offset, xe_ggtt_pte_t pte)
> {
> - return xe_mmio_gt_write64(mmio, gt, offset +
> GGTT_OFFSET_IN_TILE, pte);
> + return xe_mmio_tile_write64(mmio, tile, offset +
> GGTT_OFFSET_IN_TILE, pte);
> }
> diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
> index f144d4b53..f15017c96 100644
> --- a/lib/xe/xe_mmio.h
> +++ b/lib/xe/xe_mmio.h
> @@ -29,13 +29,17 @@ uint64_t xe_mmio_read64(struct xe_mmio *mmio,
> uint32_t offset);
> void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, uint32_t
> val);
> void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t
> val);
>
> -uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t
> offset);
> -uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t
> offset);
> -
> -void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset,
> uint32_t val);
> -void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset,
> uint64_t val);
> -
> -xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t
> pte_offset);
> -void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t
> pte_offset, xe_ggtt_pte_t pte);
> +uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile,
> uint32_t offset);
> +uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile,
> uint32_t offset);
> +void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t
> offset, uint32_t val);
> +void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t
> offset, uint64_t val);
> +
> +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, uint8_t gt, uint32_t
> offset);
> +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, uint8_t gt, uint32_t
> offset);
> +void xe_mmio_gt_write32(struct xe_mmio *mmio, uint8_t gt, uint32_t
> offset, uint32_t val);
> +void xe_mmio_gt_write64(struct xe_mmio *mmio, uint8_t gt, uint32_t
> offset, uint64_t val);
> +
> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile,
> uint32_t pte_offset);
> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t
> pte_offset, xe_ggtt_pte_t pte);
>
> #endif /* XE_MMIO_H */
> diff --git a/lib/xe/xe_sriov_provisioning.c b/lib/xe/xe_sriov_provisioning.c
> index ff9d1f7d2..2ca73d2ef 100644
> --- a/lib/xe/xe_sriov_provisioning.c
> +++ b/lib/xe/xe_sriov_provisioning.c
> @@ -90,7 +90,7 @@ static int append_range(struct
> xe_sriov_provisioned_range **ranges,
> /**
> * xe_sriov_find_ggtt_provisioned_pte_offsets - Find GGTT provisioned PTE
> offsets
> * @pf_fd: File descriptor for the Physical Function
> - * @gt: GT identifier
> + * @tile: Tile id
> * @mmio: Pointer to the MMIO structure
> * @ranges: Pointer to the array of provisioned ranges
> * @nr_ranges: Pointer to the number of provisioned ranges
> @@ -106,7 +106,7 @@ static int append_range(struct
> xe_sriov_provisioned_range **ranges,
> *
> * Returns 0 on success, or a negative error code on failure.
> */
> -int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct
> xe_mmio *mmio,
> +int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile,
> struct xe_mmio *mmio,
> struct
> xe_sriov_provisioned_range **ranges,
> unsigned int *nr_ranges)
> {
> @@ -122,7 +122,7 @@ int xe_sriov_find_ggtt_provisioned_pte_offsets(int
> pf_fd, int gt, struct xe_mmio
>
> for (uint32_t offset = START_PTE_OFFSET; offset <
> MAX_PTE_OFFSET;
> offset += sizeof(xe_ggtt_pte_t)) {
> - pte = xe_mmio_ggtt_read(mmio, gt, offset);
> + pte = xe_mmio_ggtt_read(mmio, tile, offset);
> vf_id = (pte & vfid_mask) >> GGTT_PTE_VFID_SHIFT;
>
> if (vf_id != current_vf_id) {
> diff --git a/lib/xe/xe_sriov_provisioning.h b/lib/xe/xe_sriov_provisioning.h
> index e1a9d0a63..1e1dca866 100644
> --- a/lib/xe/xe_sriov_provisioning.h
> +++ b/lib/xe/xe_sriov_provisioning.h
> @@ -92,7 +92,7 @@ struct xe_sriov_provisioned_range {
>
> const char *xe_sriov_shared_res_to_string(enum xe_sriov_shared_res
> res);
> bool xe_sriov_is_shared_res_provisionable(int pf, enum
> xe_sriov_shared_res res, unsigned int gt);
> -int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct
> xe_mmio *mmio,
> +int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile,
> struct xe_mmio *mmio,
> struct
> xe_sriov_provisioned_range **ranges,
> unsigned int *nr_ranges);
> const char *xe_sriov_shared_res_attr_name(enum xe_sriov_shared_res
> res,
> diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
> index aabbd8c05..59e4d215c 100644
> --- a/tests/intel/xe_sriov_flr.c
> +++ b/tests/intel/xe_sriov_flr.c
> @@ -493,20 +493,20 @@ struct ggtt_data {
>
> static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t
> pte_offset)
> {
> - return xe_mmio_ggtt_read(mmio, gt, pte_offset);
> + return xe_mmio_ggtt_read(mmio, 0, pte_offset);
> }
>
> static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> xe_ggtt_pte_t pte)
> {
> - xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
> + xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
> }
>
> static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t
> pte_offset, xe_ggtt_pte_t pte)
> {
> - xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
> + xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
>
> /* force flush by read some MMIO register */
> - xe_mmio_gt_read32(mmio, gt, GEN12_VF_CAP_REG);
> + xe_mmio_tile_read32(mmio, 0, GEN12_VF_CAP_REG);
> }
>
> static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt,
> uint32_t pte_offset,
> @@ -548,7 +548,7 @@ static int populate_ggtt_pte_offsets(struct ggtt_data
> *gdata)
> gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata-
> >pte_offsets));
> igt_assert(gdata->pte_offsets);
>
> - ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, gt, gdata-
> >mmio,
> + ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, 0, gdata-
> >mmio,
> &ranges,
> &nr_ranges);
> if (ret) {
> set_skip_reason(&gdata->base, "Failed to scan GGTT PTE
> offset ranges on gt%u (%d)\n",
Is that message still valid and relevant after changing gt to tile 0 in xe_sriov_find_ggtt_provisioned_pte_offsets?
> --
> 2.34.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH v1 2/3] lib/xe_mmio: Add init flag and helper to check initialization
2025-10-20 16:26 ` [PATCH v1 2/3] lib/xe_mmio: Add init flag and helper to check initialization Piórkowski, Piotr
@ 2025-10-22 11:55 ` Sokolowski, Jan
0 siblings, 0 replies; 14+ messages in thread
From: Sokolowski, Jan @ 2025-10-22 11:55 UTC (permalink / raw)
To: Piorkowski, Piotr, igt-dev@lists.freedesktop.org
Cc: Piorkowski, Piotr, Laguna, Lukasz, Marcin Bernatowicz
> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of
> Piórkowski, Piotr
> Sent: Monday, October 20, 2025 6:27 PM
> To: igt-dev@lists.freedesktop.org
> Cc: Piorkowski, Piotr <piotr.piorkowski@intel.com>; Laguna, Lukasz
> <lukasz.laguna@intel.com>; Marcin Bernatowicz
> <marcin.bernatowicz@linux.intel.com>
> Subject: [PATCH v1 2/3] lib/xe_mmio: Add init flag and helper to check
> initialization
>
> From: Piotr Piórkowski <piotr.piorkowski@intel.com>
>
> Track MMIO initialization state via a new `init` flag and expose it
> through xe_mmio_is_initialized().
>
> Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
> Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> ---
> lib/xe/xe_mmio.c | 14 ++++++++++++++
> lib/xe/xe_mmio.h | 2 ++
> 2 files changed, 16 insertions(+)
>
> diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
> index 8bc446fb9..43aa354ff 100644
> --- a/lib/xe/xe_mmio.c
> +++ b/lib/xe/xe_mmio.c
> @@ -25,6 +25,7 @@ void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct
> xe_mmio *mmio)
>
> intel_register_access_init(&mmio->intel_mmio, pci_dev, false);
> mmio->fd = pf_fd;
> + mmio->init = true;
> }
>
> /**
> @@ -39,6 +40,18 @@ void xe_mmio_access_init(int pf_fd, struct xe_mmio
> *mmio)
> xe_mmio_vf_access_init(pf_fd, 0, mmio);
> }
>
> +/**
> + * xe_mmio_is_initialized:
> + * @mmio: xe mmio structure for IO operations
> + *
> + * Returns:
> + * Non-zero if the xe mmio structure is initialized.
> + */
> +bool xe_mmio_is_initialized(const struct xe_mmio *mmio)
> +{
> + return mmio->init;
> +}
> +
> /**
> * xe_mmio_access_fini:
> * @mmio: xe mmio structure for IO operations
> @@ -49,6 +62,7 @@ void xe_mmio_access_init(int pf_fd, struct xe_mmio
> *mmio)
> void xe_mmio_access_fini(struct xe_mmio *mmio)
> {
> intel_register_access_fini(&mmio->intel_mmio);
> + mmio->init = false;
> }
>
> /**
> diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
> index f15017c96..1710a384f 100644
> --- a/lib/xe/xe_mmio.h
> +++ b/lib/xe/xe_mmio.h
> @@ -16,11 +16,13 @@ typedef uint64_t xe_ggtt_pte_t;
>
> struct xe_mmio {
> int fd;
> + bool init;
> struct intel_mmio_data intel_mmio;
> };
>
> void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio);
> void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio);
> +bool xe_mmio_is_initialized(const struct xe_mmio *mmio);
> void xe_mmio_access_fini(struct xe_mmio *mmio);
>
> uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t offset);
> --
> 2.34.1
Reviewed-by: Jan Sokolowski <jan.sokolowski@intel.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 3/3] tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices
2025-10-20 16:26 ` [PATCH v1 3/3] tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices Piórkowski, Piotr
@ 2025-10-23 10:43 ` Bernatowicz, Marcin
2025-10-23 11:56 ` Bernatowicz, Marcin
2025-10-23 14:43 ` Bernatowicz, Marcin
2 siblings, 0 replies; 14+ messages in thread
From: Bernatowicz, Marcin @ 2025-10-23 10:43 UTC (permalink / raw)
To: Piórkowski, Piotr, igt-dev; +Cc: Lukasz Laguna
On 10/20/2025 6:26 PM, Piórkowski, Piotr wrote:
> From: Piotr Piórkowski <piotr.piorkowski@intel.com>
>
> Let's introduce tile-level iteration and per-tile resource management
> for GGTT, LMEM, and register subchecks.
>
> Key updates:
> - Add xe_number_tiles() and xe_tile_get_main_gt_id() helpers.
> - Introduce xe_for_each_tile() macro for tile iteration.
> - Refactor subcheck callbacks to include tile-aware arguments.
> - Replace GT-based logic with per-tile handling for GGTT and LMEM.
>
> Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
> Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> ---
> lib/xe/xe_query.c | 45 ++++
> lib/xe/xe_query.h | 6 +
> tests/intel/xe_sriov_flr.c | 513 ++++++++++++++++++++-----------------
> 3 files changed, 334 insertions(+), 230 deletions(-)
>
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index a89e0b980..14677e862 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -515,6 +515,22 @@ unsigned int xe_dev_max_gt(int fd)
> return igt_fls(xe_dev->gt_mask) - 1;
> }
>
> +/**
> + * xe_number_tiles
> + * @fd: xe device fd
> + *
> + * Return number of tiles for xe device fd.
> + */
> +uint8_t xe_number_tiles(int fd)
> +{
> + struct xe_device *xe_dev;
> +
> + xe_dev = find_in_cache(fd);
> + igt_assert(xe_dev);
> +
> + return (uint8_t)__builtin_popcountll(xe_dev->tile_mask);
> +}
> +
> /**
> * all_memory_regions:
> * @fd: xe device fd
> @@ -995,6 +1011,35 @@ uint16_t xe_gt_get_tile_id(int fd, int gt)
> return xe_dev->gt_list->gt_list[gt].tile_id;
> }
>
> +/**
> + * xe_tile_get_main_gt_id:
> + * @fd: xe device fd
> + * @tile: tile id
> + *
> + * Returns main GT ID for given @tile.
> + */
> +uint16_t xe_tile_get_main_gt_id(int fd, uint8_t tile)
> +{
> + struct xe_device *xe_dev;
> + int gt_id = -1;
> +
> + xe_dev = find_in_cache(fd);
> + igt_assert(xe_dev);
> +
> + for (int i = 0; i < xe_dev->gt_list->num_gt; i++) {
> + const struct drm_xe_gt *gt_data = &xe_dev->gt_list->gt_list[i];
> +
> + if (gt_data->tile_id == tile && gt_data->type == DRM_XE_QUERY_GT_TYPE_MAIN) {
> + gt_id = gt_data->gt_id;
> + break;
> + }
> + }
> +
> + igt_assert_f(gt_id >= 0, "No main GT found for tile %d\n", tile);
> +
> + return gt_id;
> +}
> +
> /**
> * xe_hwconfig_lookup_value:
> * @fd: xe device fd
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index 715b64e2f..e1ed61675 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -86,6 +86,10 @@ struct xe_device {
> for (uint64_t igt_unique(__mask) = xe_device_get(__fd)->gt_mask; \
> __gt = ffsll(igt_unique(__mask)) - 1, igt_unique(__mask) != 0; \
> igt_unique(__mask) &= ~(1ull << __gt))
> +#define xe_for_each_tile(__fd, __tile) \
> + for (uint8_t igt_unique(__mask) = xe_device_get(__fd)->tile_mask; \
> + __tile = ffsll(igt_unique(__mask)) - 1, igt_unique(__mask) != 0; \
> + igt_unique(__mask) &= ~(1ull << __tile))
> #define xe_for_each_mem_region(__fd, __memreg, __r) \
> for (uint64_t igt_unique(__i) = 0; igt_unique(__i) < igt_fls(__memreg); igt_unique(__i)++) \
> for_if(__r = (__memreg & (1ull << igt_unique(__i))))
> @@ -101,6 +105,7 @@ struct xe_device {
>
> unsigned int xe_number_gt(int fd);
> unsigned int xe_dev_max_gt(int fd);
> +uint8_t xe_number_tiles(int fd);
> uint64_t all_memory_regions(int fd);
> uint64_t system_memory(int fd);
> const struct drm_xe_gt *drm_xe_get_gt(struct xe_device *xe_dev, int gt_id);
> @@ -135,6 +140,7 @@ uint16_t xe_gt_type(int fd, int gt);
> bool xe_is_media_gt(int fd, int gt);
> bool xe_is_main_gt(int fd, int gt);
> uint16_t xe_gt_get_tile_id(int fd, int gt);
> +uint16_t xe_tile_get_main_gt_id(int fd, uint8_t tile);
> uint32_t *xe_hwconfig_lookup_value(int fd, enum intel_hwconfig attribute, uint32_t *len);
> int xe_query_pxp_status(int fd);
> int xe_wait_for_pxp_init(int fd);
> diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
> index 59e4d215c..b58545384 100644
> --- a/tests/intel/xe_sriov_flr.c
> +++ b/tests/intel/xe_sriov_flr.c
> @@ -53,7 +53,9 @@
>
> IGT_TEST_DESCRIPTION("Xe tests for SR-IOV VF FLR (Functional Level Reset)");
>
> -const char *SKIP_REASON = "SKIP";
> +#define STOP_REASON_ABORT "ABORT"
> +#define STOP_REASON_FAIL "FAIL"
> +#define STOP_REASON_SKIP "SKIP"
>
> /**
> * struct subcheck_data - Base structure for subcheck data.
> @@ -66,8 +68,6 @@ const char *SKIP_REASON = "SKIP";
> * @pf_fd: File descriptor for the Physical Function.
> * @num_vfs: Number of Virtual Functions (VFs) enabled and under test. This count is
> * used to iterate over and manage the VFs during the testing process.
> - * @gt: GT under test. This identifier is used to specify a particular GT
> - * for operations when GT-specific testing is required.
> * @stop_reason: Pointer to a string that indicates why a subcheck should skip or fail.
> * This field is crucial for controlling the flow of subcheck execution.
> * If set, it should prevent further execution of the current subcheck,
> @@ -79,12 +79,11 @@ const char *SKIP_REASON = "SKIP";
> * Example usage:
> * A typical use of this structure involves initializing it with the necessary test setup
> * parameters, checking the `stop_reason` field before proceeding with each subcheck operation,
> - * and using `pf_fd`, `num_vfs`, and `gt` as needed based on the specific subcheck requirements.
> + * and using `pf_fd` and `num_vfs` as needed based on the specific subcheck requirements.
> */
> struct subcheck_data {
> int pf_fd;
> - int num_vfs;
> - int gt;
> + unsigned int num_vfs;
> char *stop_reason;
> };
>
> @@ -100,37 +99,48 @@ struct subcheck_data {
> *
> * @name: Name of the subcheck operation, used for identification and reporting.
> *
> + * @alloc: Allocate resources for the subcheck.
> + * @param data: Shared data needed for allocation.
> + * @param num_tiles: Number of tiles in the device (for multi-tile devices).
> + * @param num_vfs: Number of VFs enabled on the PF.
> + *
> * @init: Initialize the subcheck environment.
> * Sets up the initial state required for the subcheck, including preparing
> * resources and ensuring the system is ready for testing.
> * @param data: Shared data needed for initialization.
> + * @param tile: Tile index for multi-tile devices.
> *
> * @prepare_vf: Prepare subcheck data for a specific VF.
> * Called for each VF before FLR is performed. It might involve marking
> * specific memory regions or setting up PTE addresses.
> - * @param vf_id: Identifier of the VF being prepared.
> * @param data: Shared common data.
> + * @param tile: Tile index for multi-tile devices.
> + * @param vf_id: Identifier of the VF being prepared.
> *
> * @verify_vf: Verify the state of a VF after FLR.
> * Checks the VF's state post FLR to ensure the expected results,
> * such as verifying that only the FLRed VF has its state reset.
> + * @param data: Shared common data.
> + * @param flr_vf_id: Identifier of the VF that underwent FLR.
> + *
flr_vf_id twice, should be tile ? remove space
> * @param vf_id: Identifier of the VF to verify.
> * @param flr_vf_id: Identifier of the VF that underwent FLR.
> - * @param data: Shared common data.
> *
> * @cleanup: Clean up the subcheck environment.
> * Releases resources and restores the system to its original state
> * after the subchecks, ensuring no resource leaks and preparing the system
> * for subsequent tests.
> * @param data: Shared common data.
> + * @param num_tiles: Number of tiles in the device (for multi-tile devices).
> */
> struct subcheck {
> struct subcheck_data *data;
> const char *name;
> - void (*init)(struct subcheck_data *data);
> - void (*prepare_vf)(int vf_id, struct subcheck_data *data);
> - void (*verify_vf)(int vf_id, int flr_vf_id, struct subcheck_data *data);
> - void (*cleanup)(struct subcheck_data *data);
> + void (*alloc)(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs);
> + void (*init)(struct subcheck_data *data, uint8_t tile);
> + void (*prepare_vf)(struct subcheck_data *data, uint8_t tile, int vf_id);
> + void (*verify_vf)(struct subcheck_data *data, uint8_t tile, int vf_id, int flr_vf_id);
> + void (*cleanup)(struct subcheck_data *data, uint8_t num_tiles);
> };
>
> __attribute__((format(printf, 3, 0)))
> @@ -154,12 +164,12 @@ static void set_stop_reason_v(struct subcheck_data *data, const char *prefix,
> }
>
> __attribute__((format(printf, 2, 3)))
> -static void set_skip_reason(struct subcheck_data *data, const char *format, ...)
> +static void set_abort_reason(struct subcheck_data *data, const char *format, ...)
> {
> va_list args;
>
> va_start(args, format);
> - set_stop_reason_v(data, SKIP_REASON, format, args);
> + set_stop_reason_v(data, STOP_REASON_ABORT, format, args);
> va_end(args);
> }
>
> @@ -169,7 +179,17 @@ static void set_fail_reason(struct subcheck_data *data, const char *format, ...)
> va_list args;
>
> va_start(args, format);
> - set_stop_reason_v(data, "FAIL", format, args);
> + set_stop_reason_v(data, STOP_REASON_FAIL, format, args);
> + va_end(args);
> +}
> +
> +__attribute__((format(printf, 2, 3)))
> +static void set_skip_reason(struct subcheck_data *data, const char *format, ...)
> +{
> + va_list args;
> +
> + va_start(args, format);
> + set_stop_reason_v(data, STOP_REASON_SKIP, format, args);
> va_end(args);
> }
>
> @@ -197,7 +217,7 @@ static bool no_subchecks_can_proceed(struct subcheck *checks, int num_checks)
> static bool is_subcheck_skipped(struct subcheck *subcheck)
> {
> return subcheck->data && subcheck->data->stop_reason &&
> - !strncmp(SKIP_REASON, subcheck->data->stop_reason, strlen(SKIP_REASON));
> + !strncmp(STOP_REASON_SKIP, subcheck->data->stop_reason, strlen(STOP_REASON_SKIP));
> }
>
> static void subchecks_report_results(struct subcheck *checks, int num_checks)
> @@ -269,10 +289,12 @@ typedef int (*flr_exec_strategy)(int pf_fd, int num_vfs,
> * A timeout is used to wait for FLR operations to complete.
> */
> static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
> - int num_checks, flr_exec_strategy exec_strategy)
> + size_t num_checks, flr_exec_strategy exec_strategy)
> {
> const int wait_flr_ms = 200;
> int i, vf_id, flr_vf_id = -1;
> + uint8_t num_tiles = xe_number_tiles(pf_fd);
> + uint8_t tile;
>
> igt_sriov_disable_driver_autoprobe(pf_fd);
> igt_sriov_enable_vfs(pf_fd, num_vfs);
> @@ -284,12 +306,19 @@ static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
> goto disable_vfs;
>
> for (i = 0; i < num_checks; ++i)
> - checks[i].init(checks[i].data);
> + if (checks[i].alloc)
> + checks[i].alloc(checks[i].data, num_tiles, num_vfs);
>
> - for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> + xe_for_each_tile(pf_fd, tile) {
> for (i = 0; i < num_checks; ++i)
> if (subcheck_can_proceed(&checks[i]))
> - checks[i].prepare_vf(vf_id, checks[i].data);
> + checks[i].init(checks[i].data, tile);
> +
> + for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> + for (i = 0; i < num_checks; ++i)
> + if (subcheck_can_proceed(&checks[i]))
> + checks[i].prepare_vf(checks[i].data, tile, vf_id);
> + }
>
> if (no_subchecks_can_proceed(checks, num_checks))
> goto cleanup;
> @@ -299,7 +328,7 @@ static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
>
> cleanup:
> for (i = 0; i < num_checks; ++i)
> - checks[i].cleanup(checks[i].data);
> + checks[i].cleanup(checks[i].data, num_tiles);
>
> disable_vfs:
> igt_sriov_disable_vfs(pf_fd);
> @@ -315,6 +344,7 @@ static int execute_sequential_flr(int pf_fd, int num_vfs,
> const int wait_flr_ms)
> {
> int i, vf_id, flr_vf_id = 1;
> + uint8_t tile;
>
> do {
> if (igt_warn_on_f(!igt_sriov_device_reset(pf_fd, flr_vf_id),
> @@ -324,16 +354,20 @@ static int execute_sequential_flr(int pf_fd, int num_vfs,
> /* Assume FLR is finished after wait_flr_ms */
> usleep(wait_flr_ms * 1000);
>
> - for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> - for (i = 0; i < num_checks; ++i)
> - if (subcheck_can_proceed(&checks[i]))
> - checks[i].verify_vf(vf_id, flr_vf_id, checks[i].data);
> -
> - /* Reinitialize test data for the FLRed VF */
> - if (flr_vf_id < num_vfs)
> - for (i = 0; i < num_checks; ++i)
> - if (subcheck_can_proceed(&checks[i]))
> - checks[i].prepare_vf(flr_vf_id, checks[i].data);
> + xe_for_each_tile(pf_fd, tile) {
> + for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> + for (i = 0; i < num_checks; ++i)
> + if (subcheck_can_proceed(&checks[i]))
> + checks[i].verify_vf(checks[i].data, tile, vf_id,
> + flr_vf_id);
> +
> + /* Reinitialize test data for the FLRed VF */
> + if (flr_vf_id < num_vfs)
> + for (i = 0; i < num_checks; ++i)
> + if (subcheck_can_proceed(&checks[i]))
> + checks[i].prepare_vf(checks[i].data, tile,
> + flr_vf_id);
With this approach we will stop verification on first tile with
"problem" for given subcheck
> + }
>
> if (no_subchecks_can_proceed(checks, num_checks))
> break;
> @@ -431,15 +465,19 @@ cleanup_threads:
>
> /* Verify results */
> for (i = 0; i < created_threads; ++i) {
> + uint8_t tile;
> +
> vf_id = thread_data[i].vf_id;
>
> /* Skip already checked VF or if the FLR initiation failed */
> if (vf_id == last_vf_id || thread_data[i].result != 0)
> continue;
>
> - for (k = 0; k < num_checks; ++k)
> - if (subcheck_can_proceed(&checks[k]))
> - checks[k].verify_vf(vf_id, vf_id, checks[k].data);
> + xe_for_each_tile(pf_fd, tile) {
> + for (k = 0; k < num_checks; ++k)
> + if (subcheck_can_proceed(&checks[k]))
> + checks[k].verify_vf(checks[k].data, tile, vf_id, vf_id);
> + }
>
> if (no_subchecks_can_proceed(checks, num_checks))
> break;
> @@ -470,8 +508,8 @@ static int execute_parallel_flr_twice(int pf_fd, int num_vfs,
> #define GGTT_PTE_ADDR_SHIFT 12
>
> struct ggtt_ops {
> - void (*set_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
> - xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
> + void (*set_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
> + xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
> };
>
> struct ggtt_provisioned_offset_range {
> @@ -486,74 +524,89 @@ struct ggtt_provisioned_offset_range {
>
> struct ggtt_data {
> struct subcheck_data base;
> - struct ggtt_provisioned_offset_range *pte_offsets;
> + struct ggtt_provisioned_offset_range **pte_offsets;
> struct xe_mmio *mmio;
> struct ggtt_ops ggtt;
> };
>
> -static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
> +static void ggtt_subcheck_alloc(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs)
> {
> - return xe_mmio_ggtt_read(mmio, 0, pte_offset);
> + struct ggtt_data *gdata = (struct ggtt_data *)data;
> +
> + gdata->pte_offsets = calloc(num_tiles, sizeof(*gdata->pte_offsets));
> + if (!gdata->pte_offsets) {
> + set_abort_reason(data, "Failed to allocate memory for pte_offsets array\n");
> + return;
> + }
> +
> + for (uint8_t tile = 0; tile < num_tiles; tile++) {
> + gdata->pte_offsets[tile] = calloc(num_vfs + 1, sizeof(**gdata->pte_offsets));
> + if (!gdata->pte_offsets[tile]) {
> + set_abort_reason(data, "Failed to allocate memory for pte_offsets[%u]\n",
> + tile);
> + return;
> + }
> + }
> }
>
> -static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
> +static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset)
> {
> - xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
> + return xe_mmio_ggtt_read(mmio, tile, pte_offset);
> }
>
> -static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
> +static void intel_set_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset,
> + xe_ggtt_pte_t pte)
> {
> - xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
> + xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
> +}
> +
> +static void intel_mtl_set_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset,
> + xe_ggtt_pte_t pte)
> +{
> + xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
>
> /* force flush by read some MMIO register */
> - xe_mmio_tile_read32(mmio, 0, GEN12_VF_CAP_REG);
> + xe_mmio_tile_read32(mmio, tile, GEN12_VF_CAP_REG);
> }
>
> -static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> - uint8_t gpa, xe_ggtt_pte_t *out)
> +static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
> + uint32_t pte_offset, uint8_t gpa, xe_ggtt_pte_t *out)
> {
> xe_ggtt_pte_t pte;
>
> - pte = ggtt->get_pte(mmio, gt, pte_offset);
> + pte = ggtt->get_pte(mmio, tile, pte_offset);
> pte &= ~GGTT_PTE_TEST_FIELD_MASK;
> pte |= ((xe_ggtt_pte_t)gpa << GGTT_PTE_ADDR_SHIFT) & GGTT_PTE_TEST_FIELD_MASK;
> - ggtt->set_pte(mmio, gt, pte_offset, pte);
> - *out = ggtt->get_pte(mmio, gt, pte_offset);
> + ggtt->set_pte(mmio, tile, pte_offset, pte);
> + *out = ggtt->get_pte(mmio, tile, pte_offset);
>
> return *out == pte;
> }
>
> -static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> - uint8_t expected_gpa, xe_ggtt_pte_t *out)
> +static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
> + uint32_t pte_offset, uint8_t expected_gpa, xe_ggtt_pte_t *out)
> {
> uint8_t val;
>
> - *out = ggtt->get_pte(mmio, gt, pte_offset);
> + *out = ggtt->get_pte(mmio, tile, pte_offset);
> val = (uint8_t)((*out & GGTT_PTE_TEST_FIELD_MASK) >> GGTT_PTE_ADDR_SHIFT);
>
> return val == expected_gpa;
> }
>
> -static bool is_intel_mmio_initialized(const struct intel_mmio_data *mmio)
> -{
> - return mmio->dev;
> -}
> -
> -static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
> +static void populate_ggtt_pte_offsets(struct ggtt_data *gdata, uint8_t tile)
> {
> int ret, pf_fd = gdata->base.pf_fd, num_vfs = gdata->base.num_vfs;
> struct xe_sriov_provisioned_range *ranges;
> - unsigned int nr_ranges, gt = gdata->base.gt;
> + unsigned int nr_ranges;
>
> - gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
> - igt_assert(gdata->pte_offsets);
> -
> - ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, 0, gdata->mmio,
> + ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, tile, gdata->mmio,
> &ranges, &nr_ranges);
> if (ret) {
> - set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
> - gt, ret);
> - return -1;
> + set_abort_reason(&gdata->base,
> + "Tile%u: Failed to scan GGTT PTE offset ranges (%d)\n",
> + tile, ret);
> + return;
> }
>
> for (unsigned int i = 0; i < nr_ranges; ++i) {
> @@ -563,46 +616,38 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
> continue;
>
> if (vf_id < 1 || vf_id > num_vfs) {
> - set_skip_reason(&gdata->base, "Unexpected VF%u at range entry %u [%#" PRIx64 "-%#" PRIx64 "], num_vfs=%u\n",
> - vf_id, i, ranges[i].start, ranges[i].end, num_vfs);
> - free(ranges);
> - return -1;
> + set_abort_reason(&gdata->base,
> + "Tile%u: Unexpected VF%u at range entry %u [%#" PRIx64 "-%#" PRIx64 "], num_vfs=%u\n",
> + tile, vf_id, i, ranges[i].start, ranges[i].end, num_vfs);
> + goto out;
> }
>
> - if (gdata->pte_offsets[vf_id].end) {
> - set_skip_reason(&gdata->base, "Duplicate GGTT PTE offset range for VF%u\n",
> - vf_id);
> - free(ranges);
> - return -1;
> + if (gdata->pte_offsets[tile][vf_id].end) {
> + set_abort_reason(&gdata->base,
> + "Tile%u: Duplicate GGTT PTE offset range for VF%u\n",
> + tile, vf_id);
> + goto out;
> }
>
> - gdata->pte_offsets[vf_id].start = ranges[i].start;
> - gdata->pte_offsets[vf_id].end = ranges[i].end;
> + gdata->pte_offsets[tile][vf_id].start = ranges[i].start;
> + gdata->pte_offsets[tile][vf_id].end = ranges[i].end;
> }
>
> - free(ranges);
> -
> for (int vf_id = 1; vf_id <= num_vfs; ++vf_id)
> - if (!gdata->pte_offsets[vf_id].end) {
> - set_skip_reason(&gdata->base,
> - "Failed to find VF%u provisioned GGTT PTE offset range\n",
> - vf_id);
> - return -1;
> + if (!gdata->pte_offsets[tile][vf_id].end) {
> + set_abort_reason(&gdata->base,
> + "Tile%u: Failed to find VF%u provisioned GGTT PTE offset range\n",
> + tile, vf_id);
> + goto out;
> }
> -
> - return 0;
> +out:
> + free(ranges);
> }
>
> -static void ggtt_subcheck_init(struct subcheck_data *data)
> +static void ggtt_subcheck_init(struct subcheck_data *data, uint8_t tile)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
>
> - if (!xe_is_main_gt(data->pf_fd, data->gt)) {
> - set_skip_reason(data, "GGTT provisioning not exposed on GT%d (non-MAIN)\n",
> - data->gt);
> - return;
> - }
> -
> gdata->ggtt.get_pte = intel_get_pte;
> if (IS_METEORLAKE(intel_get_drm_devid(data->pf_fd)))
> gdata->ggtt.set_pte = intel_mtl_set_pte;
> @@ -610,16 +655,16 @@ static void ggtt_subcheck_init(struct subcheck_data *data)
> gdata->ggtt.set_pte = intel_set_pte;
>
> if (gdata->mmio) {
> - if (!is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
> - xe_mmio_vf_access_init(data->pf_fd, 0 /*PF*/, gdata->mmio);
> + if (!xe_mmio_is_initialized(gdata->mmio))
> + xe_mmio_access_init(data->pf_fd, gdata->mmio);
>
> - populate_ggtt_pte_offsets(gdata);
> + populate_ggtt_pte_offsets(gdata, tile);
> } else {
> - set_skip_reason(data, "xe_mmio is NULL\n");
> + set_abort_reason(data, "xe_mmio is NULL\n");
> }
> }
>
> -static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> +static void ggtt_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
> xe_ggtt_pte_t pte;
> @@ -628,22 +673,23 @@ static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> if (data->stop_reason)
> return;
>
> - igt_debug("Prepare gpa on VF%u offset range [%#x-%#x]\n", vf_id,
> - gdata->pte_offsets[vf_id].start,
> - gdata->pte_offsets[vf_id].end);
> + igt_debug("Tile%u: Prepare gpa on VF%u offset range [%#x-%#x]\n", tile, vf_id,
> + gdata->pte_offsets[tile][vf_id].start,
> + gdata->pte_offsets[tile][vf_id].end);
>
> - for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
> - if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
> + for_each_pte_offset(pte_offset, &gdata->pte_offsets[tile][vf_id]) {
> + if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, tile, pte_offset,
> (uint8_t)vf_id, &pte)) {
> set_skip_reason(data,
> - "Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x\n",
> - vf_id, pte, pte_offset);
> + "Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x on tile%u\n",
> + vf_id, pte, pte_offset, tile);
> return;
> }
> }
> }
>
> -static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
> +static void ggtt_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
> + int flr_vf_id)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
> uint8_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
> @@ -653,33 +699,62 @@ static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> if (data->stop_reason)
> return;
>
> - for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
> - if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
> + for_each_pte_offset(pte_offset, &gdata->pte_offsets[tile][vf_id]) {
> + if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, tile, pte_offset,
> expected, &pte)) {
> set_fail_reason(data,
> - "GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
> - flr_vf_id, vf_id, pte, pte_offset);
> + "Tile%u: GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
> + tile, flr_vf_id, vf_id, pte, pte_offset);
> return;
> }
> }
> }
>
> -static void ggtt_subcheck_cleanup(struct subcheck_data *data)
> +static void ggtt_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
>
> - free(gdata->pte_offsets);
> - if (gdata->mmio && is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
> + if (gdata->pte_offsets) {
> + for (uint8_t tile = 0; tile < num_tiles; tile++)
> + free(gdata->pte_offsets[tile]);
> + free(gdata->pte_offsets);
> + }
> +
> + if (gdata->mmio && xe_mmio_is_initialized(gdata->mmio))
> xe_mmio_access_fini(gdata->mmio);
> }
> -
> struct lmem_data {
> struct subcheck_data base;
> - size_t *vf_lmem_size;
> + size_t **vf_lmem_size;
> };
>
> const size_t STEP = SZ_1M;
>
> +static void lmem_subcheck_alloc(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs)
> +{
> + struct lmem_data *ldata = (struct lmem_data *)data;
> +
> + if (!xe_has_vram(data->pf_fd)) {
> + set_skip_reason(data, "No LMEM\n");
> + return;
> + }
> +
> + ldata->vf_lmem_size = calloc(num_vfs + 1, sizeof(size_t *));
> + if (!ldata->vf_lmem_size) {
> + set_abort_reason(data, "Failed to allocate memory for vf_lmem_size array\n");
> + return;
> + }
> +
> + for (uint8_t tile = 0; tile < num_tiles; tile++) {
> + ldata->vf_lmem_size[tile] = calloc(num_vfs + 1, sizeof(**ldata->vf_lmem_size));
> + if (!ldata->vf_lmem_size[tile]) {
> + set_abort_reason(data, "Failed to allocate memory for vf_lmem_size[%u]\n",
> + tile);
> + return;
> + }
> + }
> +}
> +
> static bool lmem_write_pattern(struct vram_mapping *m, uint8_t value, size_t start, size_t step)
> {
> uint8_t read;
> @@ -735,66 +810,51 @@ static bool lmem_mmap_write_munmap(int pf_fd, int vf_num, size_t length, char va
> return result;
> }
>
> -static int populate_vf_lmem_sizes(struct subcheck_data *data)
> +static void populate_vf_lmem_sizes(struct subcheck_data *data, uint8_t tile)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
> + unsigned int main_gt = xe_tile_get_main_gt_id(data->pf_fd, tile);
> struct xe_sriov_provisioned_range *ranges;
> - unsigned int nr_ranges, gt;
> + unsigned int nr_ranges;
> int ret;
>
> - ldata->vf_lmem_size = calloc(data->num_vfs + 1, sizeof(size_t));
> - igt_assert(ldata->vf_lmem_size);
> -
> - xe_for_each_gt(data->pf_fd, gt) {
> - if (!xe_is_main_gt(data->pf_fd, gt))
> - continue;
> -
> - ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd,
> - XE_SRIOV_SHARED_RES_LMEM,
> - gt, &ranges, &nr_ranges);
> - if (ret) {
> - set_skip_reason(data, "Failed read %s on gt%u (%d)\n",
> - xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
> - gt, ret);
> - return -1;
> - }
> -
> - for (unsigned int i = 0; i < nr_ranges; ++i) {
> - const unsigned int vf_id = ranges[i].vf_id;
> + ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd, XE_SRIOV_SHARED_RES_LMEM,
> + main_gt, &ranges, &nr_ranges);
> + if (ret) {
> + set_abort_reason(data, "Tile%u: Failed read %s on main GT (%d)\n", tile,
> + xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
> + ret);
> + return;
> + }
>
> - igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
> - /* Sum the allocation for vf_id (inclusive range) */
> - ldata->vf_lmem_size[vf_id] += ranges[i].end - ranges[i].start + 1;
> - }
> + for (unsigned int i = 0; i < nr_ranges; ++i) {
> + const unsigned int vf_id = ranges[i].vf_id;
>
> - free(ranges);
> + igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
> + /* Sum the allocation for vf_id (inclusive range) */
> + ldata->vf_lmem_size[tile][vf_id] += ranges[i].end - ranges[i].start + 1;
> }
>
> + free(ranges);
> +
> for (int vf_id = 1; vf_id <= data->num_vfs; ++vf_id)
> - if (!ldata->vf_lmem_size[vf_id]) {
> - set_skip_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
> - return -1;
> + if (!ldata->vf_lmem_size[tile][vf_id]) {
> + set_abort_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
> + return;
> }
>
> - return 0;
> + return;
> }
>
> -static void lmem_subcheck_init(struct subcheck_data *data)
> +static void lmem_subcheck_init(struct subcheck_data *data, uint8_t tile)
> {
> igt_assert_fd(data->pf_fd);
> igt_assert(data->num_vfs);
>
> - if (!xe_has_vram(data->pf_fd)) {
> - set_skip_reason(data, "No LMEM\n");
> - return;
> - }
> -
> - if (populate_vf_lmem_sizes(data))
> - /* skip reason set in populate_vf_lmem_sizes */
> - return;
> + populate_vf_lmem_sizes(data, tile);
> }
>
> -static void lmem_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> +static void lmem_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
>
> @@ -804,12 +864,13 @@ static void lmem_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> igt_assert(vf_id > 0 && vf_id <= data->num_vfs);
>
> if (!lmem_mmap_write_munmap(data->pf_fd, vf_id,
> - ldata->vf_lmem_size[vf_id], vf_id)) {
> - set_skip_reason(data, "LMEM write failed on VF%u\n", vf_id);
> + ldata->vf_lmem_size[tile][vf_id], vf_id)) {
> + set_abort_reason(data, "LMEM write failed on VF%u\n", vf_id);
> }
> }
>
> -static void lmem_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
> +static void lmem_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
> + int flr_vf_id)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
> char expected = (vf_id == flr_vf_id) ? 0 : vf_id;
> @@ -818,14 +879,14 @@ static void lmem_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> return;
>
> if (!lmem_contains_expected_values(data->pf_fd, vf_id,
> - ldata->vf_lmem_size[vf_id], expected)) {
> + ldata->vf_lmem_size[tile][vf_id], expected)) {
> set_fail_reason(data,
> "LMEM check after VF%u FLR failed on VF%u\n",
> flr_vf_id, vf_id);
> }
> }
>
> -static void lmem_subcheck_cleanup(struct subcheck_data *data)
> +static void lmem_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
>
> @@ -839,12 +900,12 @@ static void lmem_subcheck_cleanup(struct subcheck_data *data)
>
> struct regs_data {
> struct subcheck_data base;
> - struct intel_mmio_data *mmio;
> + struct xe_mmio *mmio;
> uint32_t reg_addr;
> int reg_count;
> };
>
> -static void regs_subcheck_init(struct subcheck_data *data)
> +static void regs_subcheck_init(struct subcheck_data *data, uint8_t tile)
> {
> struct regs_data *rdata = (struct regs_data *)data;
>
> @@ -854,7 +915,7 @@ static void regs_subcheck_init(struct subcheck_data *data)
> }
> }
>
> -static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> +static void regs_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
> {
> struct regs_data *rdata = (struct regs_data *)data;
> uint32_t reg;
> @@ -863,32 +924,22 @@ static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> if (data->stop_reason)
> return;
>
> - if (!is_intel_mmio_initialized(&rdata->mmio[vf_id])) {
> - struct pci_device *pci_dev = __igt_device_get_pci_device(data->pf_fd, vf_id);
> -
> - if (!pci_dev) {
> - set_skip_reason(data, "No PCI device found for VF%u\n", vf_id);
> - return;
> - }
> -
> - if (intel_register_access_init(&rdata->mmio[vf_id], pci_dev, false)) {
> - set_skip_reason(data, "Failed to get access to VF%u MMIO\n", vf_id);
> - return;
> - }
> - }
> + if (!xe_mmio_is_initialized(&rdata->mmio[vf_id]))
> + xe_mmio_vf_access_init(data->pf_fd, vf_id, &rdata->mmio[vf_id]);
>
> for (i = 0; i < rdata->reg_count; i++) {
> reg = rdata->reg_addr + i * 4;
>
> - intel_register_write(&rdata->mmio[vf_id], reg, vf_id);
> - if (intel_register_read(&rdata->mmio[vf_id], reg) != vf_id) {
> + xe_mmio_tile_write32(&rdata->mmio[vf_id], tile, reg, vf_id);
> + if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != vf_id) {
> set_skip_reason(data, "Registers write/read check failed on VF%u\n", vf_id);
> return;
> }
> }
> }
>
> -static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
> +static void regs_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
> + int flr_vf_id)
> {
> struct regs_data *rdata = (struct regs_data *)data;
> uint32_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
> @@ -901,7 +952,7 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> for (i = 0; i < rdata->reg_count; i++) {
> reg = rdata->reg_addr + i * 4;
>
> - if (intel_register_read(&rdata->mmio[vf_id], reg) != expected) {
> + if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != expected) {
> set_fail_reason(data,
> "Registers check after VF%u FLR failed on VF%u\n",
> flr_vf_id, vf_id);
> @@ -910,84 +961,86 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> }
> }
>
> -static void regs_subcheck_cleanup(struct subcheck_data *data)
> +static void regs_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
> {
> struct regs_data *rdata = (struct regs_data *)data;
> int i;
>
> if (rdata->mmio)
> for (i = 1; i <= data->num_vfs; ++i)
> - if (is_intel_mmio_initialized(&rdata->mmio[i]))
> - intel_register_access_fini(&rdata->mmio[i]);
> + if (xe_mmio_is_initialized(&rdata->mmio[i]))
> + xe_mmio_access_fini(&rdata->mmio[i]);
> }
>
> -static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
> +static void clear_tests(const int pf_fd, const unsigned int num_vfs,
> + const flr_exec_strategy exec_strategy)
> {
> - struct xe_mmio xemmio = { };
> - const unsigned int num_gts = xe_number_gt(pf_fd);
> - struct ggtt_data gdata[num_gts];
> + struct subcheck_data base = { .pf_fd = pf_fd, .num_vfs = num_vfs };
> + struct xe_mmio *mmio = calloc(1 + num_vfs, sizeof(*mmio));
> + struct ggtt_data gdata = {
> + .base = base,
> + .mmio = mmio,
> + };
> struct lmem_data ldata = {
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs }
> + .base = base,
> };
> - struct intel_mmio_data mmio[num_vfs + 1];
> struct regs_data scratch_data = {
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
> + .base = base,
> .mmio = mmio,
> .reg_addr = SCRATCH_REG,
> .reg_count = SCRATCH_REG_COUNT
> };
> struct regs_data media_scratch_data = {
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
> + .base = base,
> .mmio = mmio,
> .reg_addr = MED_SCRATCH_REG,
> .reg_count = MED_SCRATCH_REG_COUNT
> };
> - const unsigned int num_checks = num_gts + 3;
> - struct subcheck checks[num_checks];
> - int i = 0, gt_id;
> -
> - memset(mmio, 0, sizeof(mmio));
> -
> - xe_for_each_gt(pf_fd, gt_id) {
> - gdata[i] = (struct ggtt_data){
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs, .gt = gt_id },
> - .mmio = &xemmio
> - };
> - checks[i] = (struct subcheck){
> - .data = (struct subcheck_data *)&gdata[i],
> + struct subcheck checks[] = {
> + {
> + .data = (struct subcheck_data *)&gdata,
> .name = "clear-ggtt",
> + .alloc = ggtt_subcheck_alloc,
> .init = ggtt_subcheck_init,
> .prepare_vf = ggtt_subcheck_prepare_vf,
> .verify_vf = ggtt_subcheck_verify_vf,
> .cleanup = ggtt_subcheck_cleanup
> - };
> - i++;
> - }
> - checks[i++] = (struct subcheck) {
> - .data = (struct subcheck_data *)&ldata,
> - .name = "clear-lmem",
> - .init = lmem_subcheck_init,
> - .prepare_vf = lmem_subcheck_prepare_vf,
> - .verify_vf = lmem_subcheck_verify_vf,
> - .cleanup = lmem_subcheck_cleanup };
> - checks[i++] = (struct subcheck) {
> - .data = (struct subcheck_data *)&scratch_data,
> - .name = "clear-scratch-regs",
> - .init = regs_subcheck_init,
> - .prepare_vf = regs_subcheck_prepare_vf,
> - .verify_vf = regs_subcheck_verify_vf,
> - .cleanup = regs_subcheck_cleanup };
> - checks[i++] = (struct subcheck) {
> - .data = (struct subcheck_data *)&media_scratch_data,
> - .name = "clear-media-scratch-regs",
> - .init = regs_subcheck_init,
> - .prepare_vf = regs_subcheck_prepare_vf,
> - .verify_vf = regs_subcheck_verify_vf,
> - .cleanup = regs_subcheck_cleanup
> + },
> + {
> + .data = (struct subcheck_data *)&ldata,
> + .name = "clear-lmem",
> + .alloc = lmem_subcheck_alloc,
> + .init = lmem_subcheck_init,
> + .prepare_vf = lmem_subcheck_prepare_vf,
> + .verify_vf = lmem_subcheck_verify_vf,
> + .cleanup = lmem_subcheck_cleanup
> + },
> + {
> + .data = (struct subcheck_data *)&scratch_data,
> + .name = "clear-scratch-regs",
> + .alloc = NULL,
> + .init = regs_subcheck_init,
> + .prepare_vf = regs_subcheck_prepare_vf,
> + .verify_vf = regs_subcheck_verify_vf,
> + .cleanup = regs_subcheck_cleanup
> + },
> + {
> + .data = (struct subcheck_data *)&media_scratch_data,
> + .name = "clear-media-scratch-regs",
> + .alloc = NULL,
> + .init = regs_subcheck_init,
> + .prepare_vf = regs_subcheck_prepare_vf,
> + .verify_vf = regs_subcheck_verify_vf,
> + .cleanup = regs_subcheck_cleanup
> + }
> +
> };
> - igt_assert_eq(i, num_checks);
>
> - verify_flr(pf_fd, num_vfs, checks, num_checks, exec_strategy);
> + igt_abort_on_f(!mmio, "Failed to allocate memory for mmio array\n");
> +
> + verify_flr(pf_fd, num_vfs, checks, ARRAY_SIZE(checks), exec_strategy);
> +
> + free(mmio);
> }
>
> igt_main
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 3/3] tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices
2025-10-20 16:26 ` [PATCH v1 3/3] tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices Piórkowski, Piotr
2025-10-23 10:43 ` Bernatowicz, Marcin
@ 2025-10-23 11:56 ` Bernatowicz, Marcin
2025-10-23 14:43 ` Bernatowicz, Marcin
2 siblings, 0 replies; 14+ messages in thread
From: Bernatowicz, Marcin @ 2025-10-23 11:56 UTC (permalink / raw)
To: Piórkowski, Piotr, igt-dev; +Cc: Lukasz Laguna
On 10/20/2025 6:26 PM, Piórkowski, Piotr wrote:
> From: Piotr Piórkowski <piotr.piorkowski@intel.com>
>
> Let's introduce tile-level iteration and per-tile resource management
> for GGTT, LMEM, and register subchecks.
>
> Key updates:
> - Add xe_number_tiles() and xe_tile_get_main_gt_id() helpers.
> - Introduce xe_for_each_tile() macro for tile iteration.
> - Refactor subcheck callbacks to include tile-aware arguments.
> - Replace GT-based logic with per-tile handling for GGTT and LMEM.
>
> Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
> Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> ---
> lib/xe/xe_query.c | 45 ++++
> lib/xe/xe_query.h | 6 +
> tests/intel/xe_sriov_flr.c | 513 ++++++++++++++++++++-----------------
> 3 files changed, 334 insertions(+), 230 deletions(-)
>
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index a89e0b980..14677e862 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -515,6 +515,22 @@ unsigned int xe_dev_max_gt(int fd)
> return igt_fls(xe_dev->gt_mask) - 1;
> }
>
> +/**
> + * xe_number_tiles
> + * @fd: xe device fd
> + *
> + * Return number of tiles for xe device fd.
> + */
> +uint8_t xe_number_tiles(int fd)
> +{
> + struct xe_device *xe_dev;
> +
> + xe_dev = find_in_cache(fd);
> + igt_assert(xe_dev);
> +
> + return (uint8_t)__builtin_popcountll(xe_dev->tile_mask);
use igt_hweight
> +}
> +
> /**
> * all_memory_regions:
> * @fd: xe device fd
> @@ -995,6 +1011,35 @@ uint16_t xe_gt_get_tile_id(int fd, int gt)
> return xe_dev->gt_list->gt_list[gt].tile_id;
> }
>
> +/**
> + * xe_tile_get_main_gt_id:
> + * @fd: xe device fd
> + * @tile: tile id
> + *
> + * Returns main GT ID for given @tile.
> + */
> +uint16_t xe_tile_get_main_gt_id(int fd, uint8_t tile)
> +{
> + struct xe_device *xe_dev;
> + int gt_id = -1;
> +
> + xe_dev = find_in_cache(fd);
> + igt_assert(xe_dev);
> +
> + for (int i = 0; i < xe_dev->gt_list->num_gt; i++) {
> + const struct drm_xe_gt *gt_data = &xe_dev->gt_list->gt_list[i];
> +
> + if (gt_data->tile_id == tile && gt_data->type == DRM_XE_QUERY_GT_TYPE_MAIN) {
> + gt_id = gt_data->gt_id;
> + break;
> + }
> + }
> +
> + igt_assert_f(gt_id >= 0, "No main GT found for tile %d\n", tile);
> +
> + return gt_id;
> +}
> +
> /**
> * xe_hwconfig_lookup_value:
> * @fd: xe device fd
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index 715b64e2f..e1ed61675 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -86,6 +86,10 @@ struct xe_device {
> for (uint64_t igt_unique(__mask) = xe_device_get(__fd)->gt_mask; \
> __gt = ffsll(igt_unique(__mask)) - 1, igt_unique(__mask) != 0; \
> igt_unique(__mask) &= ~(1ull << __gt))
> +#define xe_for_each_tile(__fd, __tile) \
> + for (uint8_t igt_unique(__mask) = xe_device_get(__fd)->tile_mask; \
> + __tile = ffsll(igt_unique(__mask)) - 1, igt_unique(__mask) != 0; \
> + igt_unique(__mask) &= ~(1ull << __tile))
> #define xe_for_each_mem_region(__fd, __memreg, __r) \
> for (uint64_t igt_unique(__i) = 0; igt_unique(__i) < igt_fls(__memreg); igt_unique(__i)++) \
> for_if(__r = (__memreg & (1ull << igt_unique(__i))))
> @@ -101,6 +105,7 @@ struct xe_device {
>
> unsigned int xe_number_gt(int fd);
> unsigned int xe_dev_max_gt(int fd);
> +uint8_t xe_number_tiles(int fd);
> uint64_t all_memory_regions(int fd);
> uint64_t system_memory(int fd);
> const struct drm_xe_gt *drm_xe_get_gt(struct xe_device *xe_dev, int gt_id);
> @@ -135,6 +140,7 @@ uint16_t xe_gt_type(int fd, int gt);
> bool xe_is_media_gt(int fd, int gt);
> bool xe_is_main_gt(int fd, int gt);
> uint16_t xe_gt_get_tile_id(int fd, int gt);
> +uint16_t xe_tile_get_main_gt_id(int fd, uint8_t tile);
> uint32_t *xe_hwconfig_lookup_value(int fd, enum intel_hwconfig attribute, uint32_t *len);
> int xe_query_pxp_status(int fd);
> int xe_wait_for_pxp_init(int fd);
> diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
> index 59e4d215c..b58545384 100644
> --- a/tests/intel/xe_sriov_flr.c
> +++ b/tests/intel/xe_sriov_flr.c
> @@ -53,7 +53,9 @@
>
> IGT_TEST_DESCRIPTION("Xe tests for SR-IOV VF FLR (Functional Level Reset)");
>
> -const char *SKIP_REASON = "SKIP";
> +#define STOP_REASON_ABORT "ABORT"
> +#define STOP_REASON_FAIL "FAIL"
> +#define STOP_REASON_SKIP "SKIP"
>
> /**
> * struct subcheck_data - Base structure for subcheck data.
> @@ -66,8 +68,6 @@ const char *SKIP_REASON = "SKIP";
> * @pf_fd: File descriptor for the Physical Function.
> * @num_vfs: Number of Virtual Functions (VFs) enabled and under test. This count is
> * used to iterate over and manage the VFs during the testing process.
> - * @gt: GT under test. This identifier is used to specify a particular GT
> - * for operations when GT-specific testing is required.
> * @stop_reason: Pointer to a string that indicates why a subcheck should skip or fail.
> * This field is crucial for controlling the flow of subcheck execution.
> * If set, it should prevent further execution of the current subcheck,
> @@ -79,12 +79,11 @@ const char *SKIP_REASON = "SKIP";
> * Example usage:
> * A typical use of this structure involves initializing it with the necessary test setup
> * parameters, checking the `stop_reason` field before proceeding with each subcheck operation,
> - * and using `pf_fd`, `num_vfs`, and `gt` as needed based on the specific subcheck requirements.
> + * and using `pf_fd` and `num_vfs` as needed based on the specific subcheck requirements.
> */
> struct subcheck_data {
> int pf_fd;
> - int num_vfs;
> - int gt;
> + unsigned int num_vfs;
> char *stop_reason;
> };
>
> @@ -100,37 +99,48 @@ struct subcheck_data {
> *
> * @name: Name of the subcheck operation, used for identification and reporting.
> *
> + * @alloc: Allocate resources for the subcheck.
> + * @param data: Shared data needed for allocation.
> + * @param num_tiles: Number of tiles in the device (for multi-tile devices).
> + * @param num_vfs: Number of VFs enabled on the PF.
> + *
> * @init: Initialize the subcheck environment.
> * Sets up the initial state required for the subcheck, including preparing
> * resources and ensuring the system is ready for testing.
> * @param data: Shared data needed for initialization.
> + * @param tile: Tile index for multi-tile devices.
> *
> * @prepare_vf: Prepare subcheck data for a specific VF.
> * Called for each VF before FLR is performed. It might involve marking
> * specific memory regions or setting up PTE addresses.
> - * @param vf_id: Identifier of the VF being prepared.
> * @param data: Shared common data.
> + * @param tile: Tile index for multi-tile devices.
> + * @param vf_id: Identifier of the VF being prepared.
> *
> * @verify_vf: Verify the state of a VF after FLR.
> * Checks the VF's state post FLR to ensure the expected results,
> * such as verifying that only the FLRed VF has its state reset.
> + * @param data: Shared common data.
> + * @param flr_vf_id: Identifier of the VF that underwent FLR.
> + *
> * @param vf_id: Identifier of the VF to verify.
> * @param flr_vf_id: Identifier of the VF that underwent FLR.
> - * @param data: Shared common data.
> *
> * @cleanup: Clean up the subcheck environment.
> * Releases resources and restores the system to its original state
> * after the subchecks, ensuring no resource leaks and preparing the system
> * for subsequent tests.
> * @param data: Shared common data.
> + * @param num_tiles: Number of tiles in the device (for multi-tile devices).
> */
> struct subcheck {
> struct subcheck_data *data;
> const char *name;
> - void (*init)(struct subcheck_data *data);
> - void (*prepare_vf)(int vf_id, struct subcheck_data *data);
> - void (*verify_vf)(int vf_id, int flr_vf_id, struct subcheck_data *data);
> - void (*cleanup)(struct subcheck_data *data);
> + void (*alloc)(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs);
> + void (*init)(struct subcheck_data *data, uint8_t tile);
> + void (*prepare_vf)(struct subcheck_data *data, uint8_t tile, int vf_id);
> + void (*verify_vf)(struct subcheck_data *data, uint8_t tile, int vf_id, int flr_vf_id);
> + void (*cleanup)(struct subcheck_data *data, uint8_t num_tiles);
> };
>
> __attribute__((format(printf, 3, 0)))
> @@ -154,12 +164,12 @@ static void set_stop_reason_v(struct subcheck_data *data, const char *prefix,
> }
>
> __attribute__((format(printf, 2, 3)))
> -static void set_skip_reason(struct subcheck_data *data, const char *format, ...)
> +static void set_abort_reason(struct subcheck_data *data, const char *format, ...)
> {
> va_list args;
>
> va_start(args, format);
> - set_stop_reason_v(data, SKIP_REASON, format, args);
> + set_stop_reason_v(data, STOP_REASON_ABORT, format, args);
> va_end(args);
> }
>
> @@ -169,7 +179,17 @@ static void set_fail_reason(struct subcheck_data *data, const char *format, ...)
> va_list args;
>
> va_start(args, format);
> - set_stop_reason_v(data, "FAIL", format, args);
> + set_stop_reason_v(data, STOP_REASON_FAIL, format, args);
> + va_end(args);
> +}
> +
> +__attribute__((format(printf, 2, 3)))
> +static void set_skip_reason(struct subcheck_data *data, const char *format, ...)
> +{
> + va_list args;
> +
> + va_start(args, format);
> + set_stop_reason_v(data, STOP_REASON_SKIP, format, args);
> va_end(args);
> }
>
> @@ -197,7 +217,7 @@ static bool no_subchecks_can_proceed(struct subcheck *checks, int num_checks)
> static bool is_subcheck_skipped(struct subcheck *subcheck)
> {
> return subcheck->data && subcheck->data->stop_reason &&
> - !strncmp(SKIP_REASON, subcheck->data->stop_reason, strlen(SKIP_REASON));
> + !strncmp(STOP_REASON_SKIP, subcheck->data->stop_reason, strlen(STOP_REASON_SKIP));
> }
>
> static void subchecks_report_results(struct subcheck *checks, int num_checks)
> @@ -269,10 +289,12 @@ typedef int (*flr_exec_strategy)(int pf_fd, int num_vfs,
> * A timeout is used to wait for FLR operations to complete.
> */
> static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
> - int num_checks, flr_exec_strategy exec_strategy)
> + size_t num_checks, flr_exec_strategy exec_strategy)
> {
> const int wait_flr_ms = 200;
> int i, vf_id, flr_vf_id = -1;
> + uint8_t num_tiles = xe_number_tiles(pf_fd);
> + uint8_t tile;
>
> igt_sriov_disable_driver_autoprobe(pf_fd);
> igt_sriov_enable_vfs(pf_fd, num_vfs);
> @@ -284,12 +306,19 @@ static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
> goto disable_vfs;
>
> for (i = 0; i < num_checks; ++i)
> - checks[i].init(checks[i].data);
> + if (checks[i].alloc)
> + checks[i].alloc(checks[i].data, num_tiles, num_vfs);
>
> - for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> + xe_for_each_tile(pf_fd, tile) {
> for (i = 0; i < num_checks; ++i)
> if (subcheck_can_proceed(&checks[i]))
> - checks[i].prepare_vf(vf_id, checks[i].data);
> + checks[i].init(checks[i].data, tile);
> +
> + for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> + for (i = 0; i < num_checks; ++i)
> + if (subcheck_can_proceed(&checks[i]))
> + checks[i].prepare_vf(checks[i].data, tile, vf_id);
> + }
>
> if (no_subchecks_can_proceed(checks, num_checks))
> goto cleanup;
> @@ -299,7 +328,7 @@ static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
>
> cleanup:
> for (i = 0; i < num_checks; ++i)
> - checks[i].cleanup(checks[i].data);
> + checks[i].cleanup(checks[i].data, num_tiles);
>
> disable_vfs:
> igt_sriov_disable_vfs(pf_fd);
> @@ -315,6 +344,7 @@ static int execute_sequential_flr(int pf_fd, int num_vfs,
> const int wait_flr_ms)
> {
> int i, vf_id, flr_vf_id = 1;
> + uint8_t tile;
>
> do {
> if (igt_warn_on_f(!igt_sriov_device_reset(pf_fd, flr_vf_id),
> @@ -324,16 +354,20 @@ static int execute_sequential_flr(int pf_fd, int num_vfs,
> /* Assume FLR is finished after wait_flr_ms */
> usleep(wait_flr_ms * 1000);
>
> - for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> - for (i = 0; i < num_checks; ++i)
> - if (subcheck_can_proceed(&checks[i]))
> - checks[i].verify_vf(vf_id, flr_vf_id, checks[i].data);
> -
> - /* Reinitialize test data for the FLRed VF */
> - if (flr_vf_id < num_vfs)
> - for (i = 0; i < num_checks; ++i)
> - if (subcheck_can_proceed(&checks[i]))
> - checks[i].prepare_vf(flr_vf_id, checks[i].data);
> + xe_for_each_tile(pf_fd, tile) {
> + for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> + for (i = 0; i < num_checks; ++i)
> + if (subcheck_can_proceed(&checks[i]))
> + checks[i].verify_vf(checks[i].data, tile, vf_id,
> + flr_vf_id);
> +
> + /* Reinitialize test data for the FLRed VF */
> + if (flr_vf_id < num_vfs)
> + for (i = 0; i < num_checks; ++i)
> + if (subcheck_can_proceed(&checks[i]))
> + checks[i].prepare_vf(checks[i].data, tile,
> + flr_vf_id);
> + }
>
> if (no_subchecks_can_proceed(checks, num_checks))
> break;
> @@ -431,15 +465,19 @@ cleanup_threads:
>
> /* Verify results */
> for (i = 0; i < created_threads; ++i) {
> + uint8_t tile;
> +
> vf_id = thread_data[i].vf_id;
>
> /* Skip already checked VF or if the FLR initiation failed */
> if (vf_id == last_vf_id || thread_data[i].result != 0)
> continue;
>
> - for (k = 0; k < num_checks; ++k)
> - if (subcheck_can_proceed(&checks[k]))
> - checks[k].verify_vf(vf_id, vf_id, checks[k].data);
> + xe_for_each_tile(pf_fd, tile) {
> + for (k = 0; k < num_checks; ++k)
> + if (subcheck_can_proceed(&checks[k]))
> + checks[k].verify_vf(checks[k].data, tile, vf_id, vf_id);
> + }
>
> if (no_subchecks_can_proceed(checks, num_checks))
> break;
> @@ -470,8 +508,8 @@ static int execute_parallel_flr_twice(int pf_fd, int num_vfs,
> #define GGTT_PTE_ADDR_SHIFT 12
>
> struct ggtt_ops {
> - void (*set_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
> - xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
> + void (*set_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
> + xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
> };
>
> struct ggtt_provisioned_offset_range {
> @@ -486,74 +524,89 @@ struct ggtt_provisioned_offset_range {
>
> struct ggtt_data {
> struct subcheck_data base;
> - struct ggtt_provisioned_offset_range *pte_offsets;
> + struct ggtt_provisioned_offset_range **pte_offsets;
> struct xe_mmio *mmio;
> struct ggtt_ops ggtt;
> };
>
> -static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
> +static void ggtt_subcheck_alloc(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs)
> {
> - return xe_mmio_ggtt_read(mmio, 0, pte_offset);
> + struct ggtt_data *gdata = (struct ggtt_data *)data;
> +
> + gdata->pte_offsets = calloc(num_tiles, sizeof(*gdata->pte_offsets));
> + if (!gdata->pte_offsets) {
> + set_abort_reason(data, "Failed to allocate memory for pte_offsets array\n");
> + return;
> + }
> +
> + for (uint8_t tile = 0; tile < num_tiles; tile++) {
> + gdata->pte_offsets[tile] = calloc(num_vfs + 1, sizeof(**gdata->pte_offsets));
> + if (!gdata->pte_offsets[tile]) {
> + set_abort_reason(data, "Failed to allocate memory for pte_offsets[%u]\n",
> + tile);
> + return;
> + }
> + }
> }
>
> -static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
> +static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset)
> {
> - xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
> + return xe_mmio_ggtt_read(mmio, tile, pte_offset);
> }
>
> -static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
> +static void intel_set_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset,
> + xe_ggtt_pte_t pte)
> {
> - xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
> + xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
> +}
> +
> +static void intel_mtl_set_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset,
> + xe_ggtt_pte_t pte)
> +{
> + xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
>
> /* force flush by read some MMIO register */
> - xe_mmio_tile_read32(mmio, 0, GEN12_VF_CAP_REG);
> + xe_mmio_tile_read32(mmio, tile, GEN12_VF_CAP_REG);
> }
>
> -static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> - uint8_t gpa, xe_ggtt_pte_t *out)
> +static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
> + uint32_t pte_offset, uint8_t gpa, xe_ggtt_pte_t *out)
> {
> xe_ggtt_pte_t pte;
>
> - pte = ggtt->get_pte(mmio, gt, pte_offset);
> + pte = ggtt->get_pte(mmio, tile, pte_offset);
> pte &= ~GGTT_PTE_TEST_FIELD_MASK;
> pte |= ((xe_ggtt_pte_t)gpa << GGTT_PTE_ADDR_SHIFT) & GGTT_PTE_TEST_FIELD_MASK;
> - ggtt->set_pte(mmio, gt, pte_offset, pte);
> - *out = ggtt->get_pte(mmio, gt, pte_offset);
> + ggtt->set_pte(mmio, tile, pte_offset, pte);
> + *out = ggtt->get_pte(mmio, tile, pte_offset);
>
> return *out == pte;
> }
>
> -static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> - uint8_t expected_gpa, xe_ggtt_pte_t *out)
> +static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
> + uint32_t pte_offset, uint8_t expected_gpa, xe_ggtt_pte_t *out)
> {
> uint8_t val;
>
> - *out = ggtt->get_pte(mmio, gt, pte_offset);
> + *out = ggtt->get_pte(mmio, tile, pte_offset);
> val = (uint8_t)((*out & GGTT_PTE_TEST_FIELD_MASK) >> GGTT_PTE_ADDR_SHIFT);
>
> return val == expected_gpa;
> }
>
> -static bool is_intel_mmio_initialized(const struct intel_mmio_data *mmio)
> -{
> - return mmio->dev;
> -}
> -
> -static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
> +static void populate_ggtt_pte_offsets(struct ggtt_data *gdata, uint8_t tile)
> {
> int ret, pf_fd = gdata->base.pf_fd, num_vfs = gdata->base.num_vfs;
> struct xe_sriov_provisioned_range *ranges;
> - unsigned int nr_ranges, gt = gdata->base.gt;
> + unsigned int nr_ranges;
>
> - gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
> - igt_assert(gdata->pte_offsets);
> -
> - ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, 0, gdata->mmio,
> + ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, tile, gdata->mmio,
> &ranges, &nr_ranges);
> if (ret) {
> - set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
> - gt, ret);
> - return -1;
> + set_abort_reason(&gdata->base,
> + "Tile%u: Failed to scan GGTT PTE offset ranges (%d)\n",
> + tile, ret);
> + return;
> }
>
> for (unsigned int i = 0; i < nr_ranges; ++i) {
> @@ -563,46 +616,38 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
> continue;
>
> if (vf_id < 1 || vf_id > num_vfs) {
> - set_skip_reason(&gdata->base, "Unexpected VF%u at range entry %u [%#" PRIx64 "-%#" PRIx64 "], num_vfs=%u\n",
> - vf_id, i, ranges[i].start, ranges[i].end, num_vfs);
> - free(ranges);
> - return -1;
> + set_abort_reason(&gdata->base,
> + "Tile%u: Unexpected VF%u at range entry %u [%#" PRIx64 "-%#" PRIx64 "], num_vfs=%u\n",
> + tile, vf_id, i, ranges[i].start, ranges[i].end, num_vfs);
> + goto out;
> }
>
> - if (gdata->pte_offsets[vf_id].end) {
> - set_skip_reason(&gdata->base, "Duplicate GGTT PTE offset range for VF%u\n",
> - vf_id);
> - free(ranges);
> - return -1;
> + if (gdata->pte_offsets[tile][vf_id].end) {
> + set_abort_reason(&gdata->base,
> + "Tile%u: Duplicate GGTT PTE offset range for VF%u\n",
> + tile, vf_id);
> + goto out;
> }
>
> - gdata->pte_offsets[vf_id].start = ranges[i].start;
> - gdata->pte_offsets[vf_id].end = ranges[i].end;
> + gdata->pte_offsets[tile][vf_id].start = ranges[i].start;
> + gdata->pte_offsets[tile][vf_id].end = ranges[i].end;
> }
>
> - free(ranges);
> -
> for (int vf_id = 1; vf_id <= num_vfs; ++vf_id)
> - if (!gdata->pte_offsets[vf_id].end) {
> - set_skip_reason(&gdata->base,
> - "Failed to find VF%u provisioned GGTT PTE offset range\n",
> - vf_id);
> - return -1;
> + if (!gdata->pte_offsets[tile][vf_id].end) {
> + set_abort_reason(&gdata->base,
> + "Tile%u: Failed to find VF%u provisioned GGTT PTE offset range\n",
> + tile, vf_id);
> + goto out;
> }
> -
> - return 0;
> +out:
> + free(ranges);
> }
>
> -static void ggtt_subcheck_init(struct subcheck_data *data)
> +static void ggtt_subcheck_init(struct subcheck_data *data, uint8_t tile)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
>
> - if (!xe_is_main_gt(data->pf_fd, data->gt)) {
> - set_skip_reason(data, "GGTT provisioning not exposed on GT%d (non-MAIN)\n",
> - data->gt);
> - return;
> - }
> -
> gdata->ggtt.get_pte = intel_get_pte;
> if (IS_METEORLAKE(intel_get_drm_devid(data->pf_fd)))
> gdata->ggtt.set_pte = intel_mtl_set_pte;
> @@ -610,16 +655,16 @@ static void ggtt_subcheck_init(struct subcheck_data *data)
> gdata->ggtt.set_pte = intel_set_pte;
>
> if (gdata->mmio) {
> - if (!is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
> - xe_mmio_vf_access_init(data->pf_fd, 0 /*PF*/, gdata->mmio);
> + if (!xe_mmio_is_initialized(gdata->mmio))
> + xe_mmio_access_init(data->pf_fd, gdata->mmio);
>
> - populate_ggtt_pte_offsets(gdata);
> + populate_ggtt_pte_offsets(gdata, tile);
> } else {
> - set_skip_reason(data, "xe_mmio is NULL\n");
> + set_abort_reason(data, "xe_mmio is NULL\n");
> }
> }
>
> -static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> +static void ggtt_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
> xe_ggtt_pte_t pte;
> @@ -628,22 +673,23 @@ static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> if (data->stop_reason)
> return;
>
> - igt_debug("Prepare gpa on VF%u offset range [%#x-%#x]\n", vf_id,
> - gdata->pte_offsets[vf_id].start,
> - gdata->pte_offsets[vf_id].end);
> + igt_debug("Tile%u: Prepare gpa on VF%u offset range [%#x-%#x]\n", tile, vf_id,
> + gdata->pte_offsets[tile][vf_id].start,
> + gdata->pte_offsets[tile][vf_id].end);
>
> - for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
> - if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
> + for_each_pte_offset(pte_offset, &gdata->pte_offsets[tile][vf_id]) {
> + if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, tile, pte_offset,
> (uint8_t)vf_id, &pte)) {
> set_skip_reason(data,
> - "Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x\n",
> - vf_id, pte, pte_offset);
> + "Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x on tile%u\n",
> + vf_id, pte, pte_offset, tile);
> return;
> }
> }
> }
>
> -static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
> +static void ggtt_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
> + int flr_vf_id)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
> uint8_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
> @@ -653,33 +699,62 @@ static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> if (data->stop_reason)
> return;
>
> - for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
> - if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
> + for_each_pte_offset(pte_offset, &gdata->pte_offsets[tile][vf_id]) {
> + if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, tile, pte_offset,
> expected, &pte)) {
> set_fail_reason(data,
> - "GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
> - flr_vf_id, vf_id, pte, pte_offset);
> + "Tile%u: GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
> + tile, flr_vf_id, vf_id, pte, pte_offset);
> return;
> }
> }
> }
>
> -static void ggtt_subcheck_cleanup(struct subcheck_data *data)
> +static void ggtt_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
>
> - free(gdata->pte_offsets);
> - if (gdata->mmio && is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
> + if (gdata->pte_offsets) {
> + for (uint8_t tile = 0; tile < num_tiles; tile++)
> + free(gdata->pte_offsets[tile]);
> + free(gdata->pte_offsets);
> + }
> +
> + if (gdata->mmio && xe_mmio_is_initialized(gdata->mmio))
> xe_mmio_access_fini(gdata->mmio);
> }
> -
> struct lmem_data {
> struct subcheck_data base;
> - size_t *vf_lmem_size;
> + size_t **vf_lmem_size;
> };
>
> const size_t STEP = SZ_1M;
>
> +static void lmem_subcheck_alloc(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs)
> +{
> + struct lmem_data *ldata = (struct lmem_data *)data;
> +
> + if (!xe_has_vram(data->pf_fd)) {
> + set_skip_reason(data, "No LMEM\n");
> + return;
> + }
> +
> + ldata->vf_lmem_size = calloc(num_vfs + 1, sizeof(size_t *));
> + if (!ldata->vf_lmem_size) {
> + set_abort_reason(data, "Failed to allocate memory for vf_lmem_size array\n");
> + return;
> + }
> +
> + for (uint8_t tile = 0; tile < num_tiles; tile++) {
> + ldata->vf_lmem_size[tile] = calloc(num_vfs + 1, sizeof(**ldata->vf_lmem_size));
> + if (!ldata->vf_lmem_size[tile]) {
> + set_abort_reason(data, "Failed to allocate memory for vf_lmem_size[%u]\n",
> + tile);
> + return;
> + }
> + }
> +}
> +
> static bool lmem_write_pattern(struct vram_mapping *m, uint8_t value, size_t start, size_t step)
> {
> uint8_t read;
> @@ -735,66 +810,51 @@ static bool lmem_mmap_write_munmap(int pf_fd, int vf_num, size_t length, char va
> return result;
> }
>
> -static int populate_vf_lmem_sizes(struct subcheck_data *data)
> +static void populate_vf_lmem_sizes(struct subcheck_data *data, uint8_t tile)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
> + unsigned int main_gt = xe_tile_get_main_gt_id(data->pf_fd, tile);
> struct xe_sriov_provisioned_range *ranges;
> - unsigned int nr_ranges, gt;
> + unsigned int nr_ranges;
> int ret;
>
> - ldata->vf_lmem_size = calloc(data->num_vfs + 1, sizeof(size_t));
> - igt_assert(ldata->vf_lmem_size);
> -
> - xe_for_each_gt(data->pf_fd, gt) {
> - if (!xe_is_main_gt(data->pf_fd, gt))
> - continue;
> -
> - ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd,
> - XE_SRIOV_SHARED_RES_LMEM,
> - gt, &ranges, &nr_ranges);
> - if (ret) {
> - set_skip_reason(data, "Failed read %s on gt%u (%d)\n",
> - xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
> - gt, ret);
> - return -1;
> - }
> -
> - for (unsigned int i = 0; i < nr_ranges; ++i) {
> - const unsigned int vf_id = ranges[i].vf_id;
> + ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd, XE_SRIOV_SHARED_RES_LMEM,
> + main_gt, &ranges, &nr_ranges);
> + if (ret) {
> + set_abort_reason(data, "Tile%u: Failed read %s on main GT (%d)\n", tile,
> + xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
> + ret);
> + return;
> + }
>
> - igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
> - /* Sum the allocation for vf_id (inclusive range) */
> - ldata->vf_lmem_size[vf_id] += ranges[i].end - ranges[i].start + 1;
> - }
> + for (unsigned int i = 0; i < nr_ranges; ++i) {
> + const unsigned int vf_id = ranges[i].vf_id;
>
> - free(ranges);
> + igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
> + /* Sum the allocation for vf_id (inclusive range) */
> + ldata->vf_lmem_size[tile][vf_id] += ranges[i].end - ranges[i].start + 1;
> }
>
> + free(ranges);
> +
> for (int vf_id = 1; vf_id <= data->num_vfs; ++vf_id)
> - if (!ldata->vf_lmem_size[vf_id]) {
> - set_skip_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
> - return -1;
> + if (!ldata->vf_lmem_size[tile][vf_id]) {
> + set_abort_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
> + return;
> }
>
> - return 0;
> + return;
> }
>
> -static void lmem_subcheck_init(struct subcheck_data *data)
> +static void lmem_subcheck_init(struct subcheck_data *data, uint8_t tile)
> {
> igt_assert_fd(data->pf_fd);
> igt_assert(data->num_vfs);
>
> - if (!xe_has_vram(data->pf_fd)) {
> - set_skip_reason(data, "No LMEM\n");
> - return;
> - }
> -
> - if (populate_vf_lmem_sizes(data))
> - /* skip reason set in populate_vf_lmem_sizes */
> - return;
> + populate_vf_lmem_sizes(data, tile);
> }
>
> -static void lmem_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> +static void lmem_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
>
> @@ -804,12 +864,13 @@ static void lmem_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> igt_assert(vf_id > 0 && vf_id <= data->num_vfs);
>
> if (!lmem_mmap_write_munmap(data->pf_fd, vf_id,
> - ldata->vf_lmem_size[vf_id], vf_id)) {
> - set_skip_reason(data, "LMEM write failed on VF%u\n", vf_id);
> + ldata->vf_lmem_size[tile][vf_id], vf_id)) {
> + set_abort_reason(data, "LMEM write failed on VF%u\n", vf_id);
> }
> }
>
> -static void lmem_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
> +static void lmem_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
> + int flr_vf_id)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
> char expected = (vf_id == flr_vf_id) ? 0 : vf_id;
> @@ -818,14 +879,14 @@ static void lmem_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> return;
>
> if (!lmem_contains_expected_values(data->pf_fd, vf_id,
> - ldata->vf_lmem_size[vf_id], expected)) {
> + ldata->vf_lmem_size[tile][vf_id], expected)) {
> set_fail_reason(data,
> "LMEM check after VF%u FLR failed on VF%u\n",
> flr_vf_id, vf_id);
> }
> }
>
> -static void lmem_subcheck_cleanup(struct subcheck_data *data)
> +static void lmem_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
>
> @@ -839,12 +900,12 @@ static void lmem_subcheck_cleanup(struct subcheck_data *data)
>
> struct regs_data {
> struct subcheck_data base;
> - struct intel_mmio_data *mmio;
> + struct xe_mmio *mmio;
> uint32_t reg_addr;
> int reg_count;
> };
>
> -static void regs_subcheck_init(struct subcheck_data *data)
> +static void regs_subcheck_init(struct subcheck_data *data, uint8_t tile)
> {
> struct regs_data *rdata = (struct regs_data *)data;
>
> @@ -854,7 +915,7 @@ static void regs_subcheck_init(struct subcheck_data *data)
> }
> }
>
> -static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> +static void regs_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
> {
> struct regs_data *rdata = (struct regs_data *)data;
> uint32_t reg;
> @@ -863,32 +924,22 @@ static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> if (data->stop_reason)
> return;
>
> - if (!is_intel_mmio_initialized(&rdata->mmio[vf_id])) {
> - struct pci_device *pci_dev = __igt_device_get_pci_device(data->pf_fd, vf_id);
> -
> - if (!pci_dev) {
> - set_skip_reason(data, "No PCI device found for VF%u\n", vf_id);
> - return;
> - }
> -
> - if (intel_register_access_init(&rdata->mmio[vf_id], pci_dev, false)) {
> - set_skip_reason(data, "Failed to get access to VF%u MMIO\n", vf_id);
> - return;
> - }
> - }
> + if (!xe_mmio_is_initialized(&rdata->mmio[vf_id]))
> + xe_mmio_vf_access_init(data->pf_fd, vf_id, &rdata->mmio[vf_id]);
>
> for (i = 0; i < rdata->reg_count; i++) {
> reg = rdata->reg_addr + i * 4;
>
> - intel_register_write(&rdata->mmio[vf_id], reg, vf_id);
> - if (intel_register_read(&rdata->mmio[vf_id], reg) != vf_id) {
> + xe_mmio_tile_write32(&rdata->mmio[vf_id], tile, reg, vf_id);
> + if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != vf_id) {
> set_skip_reason(data, "Registers write/read check failed on VF%u\n", vf_id);
> return;
> }
> }
> }
>
> -static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
> +static void regs_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
> + int flr_vf_id)
> {
> struct regs_data *rdata = (struct regs_data *)data;
> uint32_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
> @@ -901,7 +952,7 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> for (i = 0; i < rdata->reg_count; i++) {
> reg = rdata->reg_addr + i * 4;
>
> - if (intel_register_read(&rdata->mmio[vf_id], reg) != expected) {
> + if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != expected) {
> set_fail_reason(data,
> "Registers check after VF%u FLR failed on VF%u\n",
> flr_vf_id, vf_id);
> @@ -910,84 +961,86 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> }
> }
>
> -static void regs_subcheck_cleanup(struct subcheck_data *data)
> +static void regs_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
> {
> struct regs_data *rdata = (struct regs_data *)data;
> int i;
>
> if (rdata->mmio)
> for (i = 1; i <= data->num_vfs; ++i)
> - if (is_intel_mmio_initialized(&rdata->mmio[i]))
> - intel_register_access_fini(&rdata->mmio[i]);
> + if (xe_mmio_is_initialized(&rdata->mmio[i]))
> + xe_mmio_access_fini(&rdata->mmio[i]);
> }
>
> -static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
> +static void clear_tests(const int pf_fd, const unsigned int num_vfs,
> + const flr_exec_strategy exec_strategy)
> {
> - struct xe_mmio xemmio = { };
> - const unsigned int num_gts = xe_number_gt(pf_fd);
> - struct ggtt_data gdata[num_gts];
> + struct subcheck_data base = { .pf_fd = pf_fd, .num_vfs = num_vfs };
> + struct xe_mmio *mmio = calloc(1 + num_vfs, sizeof(*mmio));
> + struct ggtt_data gdata = {
> + .base = base,
> + .mmio = mmio,
> + };
> struct lmem_data ldata = {
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs }
> + .base = base,
> };
> - struct intel_mmio_data mmio[num_vfs + 1];
> struct regs_data scratch_data = {
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
> + .base = base,
> .mmio = mmio,
> .reg_addr = SCRATCH_REG,
> .reg_count = SCRATCH_REG_COUNT
> };
> struct regs_data media_scratch_data = {
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
> + .base = base,
> .mmio = mmio,
> .reg_addr = MED_SCRATCH_REG,
> .reg_count = MED_SCRATCH_REG_COUNT
> };
> - const unsigned int num_checks = num_gts + 3;
> - struct subcheck checks[num_checks];
> - int i = 0, gt_id;
> -
> - memset(mmio, 0, sizeof(mmio));
> -
> - xe_for_each_gt(pf_fd, gt_id) {
> - gdata[i] = (struct ggtt_data){
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs, .gt = gt_id },
> - .mmio = &xemmio
> - };
> - checks[i] = (struct subcheck){
> - .data = (struct subcheck_data *)&gdata[i],
> + struct subcheck checks[] = {
> + {
> + .data = (struct subcheck_data *)&gdata,
> .name = "clear-ggtt",
> + .alloc = ggtt_subcheck_alloc,
> .init = ggtt_subcheck_init,
> .prepare_vf = ggtt_subcheck_prepare_vf,
> .verify_vf = ggtt_subcheck_verify_vf,
> .cleanup = ggtt_subcheck_cleanup
> - };
> - i++;
> - }
> - checks[i++] = (struct subcheck) {
> - .data = (struct subcheck_data *)&ldata,
> - .name = "clear-lmem",
> - .init = lmem_subcheck_init,
> - .prepare_vf = lmem_subcheck_prepare_vf,
> - .verify_vf = lmem_subcheck_verify_vf,
> - .cleanup = lmem_subcheck_cleanup };
> - checks[i++] = (struct subcheck) {
> - .data = (struct subcheck_data *)&scratch_data,
> - .name = "clear-scratch-regs",
> - .init = regs_subcheck_init,
> - .prepare_vf = regs_subcheck_prepare_vf,
> - .verify_vf = regs_subcheck_verify_vf,
> - .cleanup = regs_subcheck_cleanup };
> - checks[i++] = (struct subcheck) {
> - .data = (struct subcheck_data *)&media_scratch_data,
> - .name = "clear-media-scratch-regs",
> - .init = regs_subcheck_init,
> - .prepare_vf = regs_subcheck_prepare_vf,
> - .verify_vf = regs_subcheck_verify_vf,
> - .cleanup = regs_subcheck_cleanup
> + },
> + {
> + .data = (struct subcheck_data *)&ldata,
> + .name = "clear-lmem",
> + .alloc = lmem_subcheck_alloc,
> + .init = lmem_subcheck_init,
> + .prepare_vf = lmem_subcheck_prepare_vf,
> + .verify_vf = lmem_subcheck_verify_vf,
> + .cleanup = lmem_subcheck_cleanup
> + },
> + {
> + .data = (struct subcheck_data *)&scratch_data,
> + .name = "clear-scratch-regs",
> + .alloc = NULL,
> + .init = regs_subcheck_init,
> + .prepare_vf = regs_subcheck_prepare_vf,
> + .verify_vf = regs_subcheck_verify_vf,
> + .cleanup = regs_subcheck_cleanup
> + },
> + {
> + .data = (struct subcheck_data *)&media_scratch_data,
> + .name = "clear-media-scratch-regs",
> + .alloc = NULL,
> + .init = regs_subcheck_init,
> + .prepare_vf = regs_subcheck_prepare_vf,
> + .verify_vf = regs_subcheck_verify_vf,
> + .cleanup = regs_subcheck_cleanup
> + }
> +
> };
> - igt_assert_eq(i, num_checks);
>
> - verify_flr(pf_fd, num_vfs, checks, num_checks, exec_strategy);
> + igt_abort_on_f(!mmio, "Failed to allocate memory for mmio array\n");
> +
> + verify_flr(pf_fd, num_vfs, checks, ARRAY_SIZE(checks), exec_strategy);
> +
> + free(mmio);
> }
>
> igt_main
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 3/3] tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices
2025-10-20 16:26 ` [PATCH v1 3/3] tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices Piórkowski, Piotr
2025-10-23 10:43 ` Bernatowicz, Marcin
2025-10-23 11:56 ` Bernatowicz, Marcin
@ 2025-10-23 14:43 ` Bernatowicz, Marcin
2 siblings, 0 replies; 14+ messages in thread
From: Bernatowicz, Marcin @ 2025-10-23 14:43 UTC (permalink / raw)
To: Piórkowski, Piotr, igt-dev; +Cc: Lukasz Laguna
On 10/20/2025 6:26 PM, Piórkowski, Piotr wrote:
> From: Piotr Piórkowski <piotr.piorkowski@intel.com>
>
> Let's introduce tile-level iteration and per-tile resource management
> for GGTT, LMEM, and register subchecks.
>
> Key updates:
> - Add xe_number_tiles() and xe_tile_get_main_gt_id() helpers.
> - Introduce xe_for_each_tile() macro for tile iteration.
> - Refactor subcheck callbacks to include tile-aware arguments.
> - Replace GT-based logic with per-tile handling for GGTT and LMEM.
>
> Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
> Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> ---
> lib/xe/xe_query.c | 45 ++++
> lib/xe/xe_query.h | 6 +
> tests/intel/xe_sriov_flr.c | 513 ++++++++++++++++++++-----------------
> 3 files changed, 334 insertions(+), 230 deletions(-)
>
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index a89e0b980..14677e862 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -515,6 +515,22 @@ unsigned int xe_dev_max_gt(int fd)
> return igt_fls(xe_dev->gt_mask) - 1;
> }
>
> +/**
> + * xe_number_tiles
> + * @fd: xe device fd
> + *
> + * Return number of tiles for xe device fd.
> + */
> +uint8_t xe_number_tiles(int fd)
> +{
> + struct xe_device *xe_dev;
> +
> + xe_dev = find_in_cache(fd);
> + igt_assert(xe_dev);
> +
> + return (uint8_t)__builtin_popcountll(xe_dev->tile_mask);
> +}
maybe unsigned int to keep consistent with other helpers
> +
> /**
> * all_memory_regions:
> * @fd: xe device fd
> @@ -995,6 +1011,35 @@ uint16_t xe_gt_get_tile_id(int fd, int gt)
> return xe_dev->gt_list->gt_list[gt].tile_id;
> }
>
> +/**
> + * xe_tile_get_main_gt_id:
> + * @fd: xe device fd
> + * @tile: tile id
> + *
> + * Returns main GT ID for given @tile.
> + */
> +uint16_t xe_tile_get_main_gt_id(int fd, uint8_t tile)
> +{
> + struct xe_device *xe_dev;
> + int gt_id = -1;
> +
> + xe_dev = find_in_cache(fd);
> + igt_assert(xe_dev);
> +
> + for (int i = 0; i < xe_dev->gt_list->num_gt; i++) {
> + const struct drm_xe_gt *gt_data = &xe_dev->gt_list->gt_list[i];
> +
> + if (gt_data->tile_id == tile && gt_data->type == DRM_XE_QUERY_GT_TYPE_MAIN) {
> + gt_id = gt_data->gt_id;
> + break;
> + }
> + }
> +
> + igt_assert_f(gt_id >= 0, "No main GT found for tile %d\n", tile);
> +
> + return gt_id;
> +}
> +
> /**
> * xe_hwconfig_lookup_value:
> * @fd: xe device fd
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index 715b64e2f..e1ed61675 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -86,6 +86,10 @@ struct xe_device {
> for (uint64_t igt_unique(__mask) = xe_device_get(__fd)->gt_mask; \
> __gt = ffsll(igt_unique(__mask)) - 1, igt_unique(__mask) != 0; \
> igt_unique(__mask) &= ~(1ull << __gt))
> +#define xe_for_each_tile(__fd, __tile) \
> + for (uint8_t igt_unique(__mask) = xe_device_get(__fd)->tile_mask; \
> + __tile = ffsll(igt_unique(__mask)) - 1, igt_unique(__mask) != 0; \
> + igt_unique(__mask) &= ~(1ull << __tile))
tile_mask is uint64_t, using uint8_t loop mask truncates to the low 8
bits and will silently break on devices with ≥8 tiles
> #define xe_for_each_mem_region(__fd, __memreg, __r) \
> for (uint64_t igt_unique(__i) = 0; igt_unique(__i) < igt_fls(__memreg); igt_unique(__i)++) \
> for_if(__r = (__memreg & (1ull << igt_unique(__i))))
> @@ -101,6 +105,7 @@ struct xe_device {
>
> unsigned int xe_number_gt(int fd);
> unsigned int xe_dev_max_gt(int fd);
> +uint8_t xe_number_tiles(int fd);
maybe unsigned int to keep consistent with other helpers
> uint64_t all_memory_regions(int fd);
> uint64_t system_memory(int fd);
> const struct drm_xe_gt *drm_xe_get_gt(struct xe_device *xe_dev, int gt_id);
> @@ -135,6 +140,7 @@ uint16_t xe_gt_type(int fd, int gt);
> bool xe_is_media_gt(int fd, int gt);
> bool xe_is_main_gt(int fd, int gt);
> uint16_t xe_gt_get_tile_id(int fd, int gt);
> +uint16_t xe_tile_get_main_gt_id(int fd, uint8_t tile);
> uint32_t *xe_hwconfig_lookup_value(int fd, enum intel_hwconfig attribute, uint32_t *len);
> int xe_query_pxp_status(int fd);
> int xe_wait_for_pxp_init(int fd);
> diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
> index 59e4d215c..b58545384 100644
> --- a/tests/intel/xe_sriov_flr.c
> +++ b/tests/intel/xe_sriov_flr.c
> @@ -53,7 +53,9 @@
>
> IGT_TEST_DESCRIPTION("Xe tests for SR-IOV VF FLR (Functional Level Reset)");
>
> -const char *SKIP_REASON = "SKIP";
> +#define STOP_REASON_ABORT "ABORT"
> +#define STOP_REASON_FAIL "FAIL"
> +#define STOP_REASON_SKIP "SKIP"
>
> /**
> * struct subcheck_data - Base structure for subcheck data.
> @@ -66,8 +68,6 @@ const char *SKIP_REASON = "SKIP";
> * @pf_fd: File descriptor for the Physical Function.
> * @num_vfs: Number of Virtual Functions (VFs) enabled and under test. This count is
> * used to iterate over and manage the VFs during the testing process.
> - * @gt: GT under test. This identifier is used to specify a particular GT
> - * for operations when GT-specific testing is required.
> * @stop_reason: Pointer to a string that indicates why a subcheck should skip or fail.
> * This field is crucial for controlling the flow of subcheck execution.
> * If set, it should prevent further execution of the current subcheck,
> @@ -79,12 +79,11 @@ const char *SKIP_REASON = "SKIP";
> * Example usage:
> * A typical use of this structure involves initializing it with the necessary test setup
> * parameters, checking the `stop_reason` field before proceeding with each subcheck operation,
> - * and using `pf_fd`, `num_vfs`, and `gt` as needed based on the specific subcheck requirements.
> + * and using `pf_fd` and `num_vfs` as needed based on the specific subcheck requirements.
> */
> struct subcheck_data {
> int pf_fd;
> - int num_vfs;
> - int gt;
> + unsigned int num_vfs;
> char *stop_reason;
> };
>
> @@ -100,37 +99,48 @@ struct subcheck_data {
> *
> * @name: Name of the subcheck operation, used for identification and reporting.
> *
> + * @alloc: Allocate resources for the subcheck.
> + * @param data: Shared data needed for allocation.
> + * @param num_tiles: Number of tiles in the device (for multi-tile devices).
> + * @param num_vfs: Number of VFs enabled on the PF.
> + *
> * @init: Initialize the subcheck environment.
> * Sets up the initial state required for the subcheck, including preparing
> * resources and ensuring the system is ready for testing.
> * @param data: Shared data needed for initialization.
> + * @param tile: Tile index for multi-tile devices.
> *
> * @prepare_vf: Prepare subcheck data for a specific VF.
> * Called for each VF before FLR is performed. It might involve marking
> * specific memory regions or setting up PTE addresses.
> - * @param vf_id: Identifier of the VF being prepared.
> * @param data: Shared common data.
> + * @param tile: Tile index for multi-tile devices.
> + * @param vf_id: Identifier of the VF being prepared.
> *
> * @verify_vf: Verify the state of a VF after FLR.
> * Checks the VF's state post FLR to ensure the expected results,
> * such as verifying that only the FLRed VF has its state reset.
> + * @param data: Shared common data.
> + * @param flr_vf_id: Identifier of the VF that underwent FLR.
> + *
> * @param vf_id: Identifier of the VF to verify.
> * @param flr_vf_id: Identifier of the VF that underwent FLR.
> - * @param data: Shared common data.
> *
> * @cleanup: Clean up the subcheck environment.
> * Releases resources and restores the system to its original state
> * after the subchecks, ensuring no resource leaks and preparing the system
> * for subsequent tests.
> * @param data: Shared common data.
> + * @param num_tiles: Number of tiles in the device (for multi-tile devices).
> */
> struct subcheck {
> struct subcheck_data *data;
> const char *name;
> - void (*init)(struct subcheck_data *data);
> - void (*prepare_vf)(int vf_id, struct subcheck_data *data);
> - void (*verify_vf)(int vf_id, int flr_vf_id, struct subcheck_data *data);
> - void (*cleanup)(struct subcheck_data *data);
> + void (*alloc)(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs);
> + void (*init)(struct subcheck_data *data, uint8_t tile);
> + void (*prepare_vf)(struct subcheck_data *data, uint8_t tile, int vf_id);
> + void (*verify_vf)(struct subcheck_data *data, uint8_t tile, int vf_id, int flr_vf_id);
> + void (*cleanup)(struct subcheck_data *data, uint8_t num_tiles);
> };
>
> __attribute__((format(printf, 3, 0)))
> @@ -154,12 +164,12 @@ static void set_stop_reason_v(struct subcheck_data *data, const char *prefix,
> }
>
> __attribute__((format(printf, 2, 3)))
> -static void set_skip_reason(struct subcheck_data *data, const char *format, ...)
> +static void set_abort_reason(struct subcheck_data *data, const char *format, ...)
> {
> va_list args;
>
> va_start(args, format);
> - set_stop_reason_v(data, SKIP_REASON, format, args);
> + set_stop_reason_v(data, STOP_REASON_ABORT, format, args);
> va_end(args);
> }
>
> @@ -169,7 +179,17 @@ static void set_fail_reason(struct subcheck_data *data, const char *format, ...)
> va_list args;
>
> va_start(args, format);
> - set_stop_reason_v(data, "FAIL", format, args);
> + set_stop_reason_v(data, STOP_REASON_FAIL, format, args);
> + va_end(args);
> +}
> +
> +__attribute__((format(printf, 2, 3)))
> +static void set_skip_reason(struct subcheck_data *data, const char *format, ...)
> +{
> + va_list args;
> +
> + va_start(args, format);
> + set_stop_reason_v(data, STOP_REASON_SKIP, format, args);
> va_end(args);
> }
>
> @@ -197,7 +217,7 @@ static bool no_subchecks_can_proceed(struct subcheck *checks, int num_checks)
> static bool is_subcheck_skipped(struct subcheck *subcheck)
> {
> return subcheck->data && subcheck->data->stop_reason &&
> - !strncmp(SKIP_REASON, subcheck->data->stop_reason, strlen(SKIP_REASON));
> + !strncmp(STOP_REASON_SKIP, subcheck->data->stop_reason, strlen(STOP_REASON_SKIP));
> }
>
> static void subchecks_report_results(struct subcheck *checks, int num_checks)
> @@ -269,10 +289,12 @@ typedef int (*flr_exec_strategy)(int pf_fd, int num_vfs,
> * A timeout is used to wait for FLR operations to complete.
> */
> static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
> - int num_checks, flr_exec_strategy exec_strategy)
> + size_t num_checks, flr_exec_strategy exec_strategy)
> {
> const int wait_flr_ms = 200;
> int i, vf_id, flr_vf_id = -1;
> + uint8_t num_tiles = xe_number_tiles(pf_fd);
> + uint8_t tile;
>
> igt_sriov_disable_driver_autoprobe(pf_fd);
> igt_sriov_enable_vfs(pf_fd, num_vfs);
> @@ -284,12 +306,19 @@ static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
> goto disable_vfs;
>
> for (i = 0; i < num_checks; ++i)
> - checks[i].init(checks[i].data);
> + if (checks[i].alloc)
> + checks[i].alloc(checks[i].data, num_tiles, num_vfs);
>
> - for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> + xe_for_each_tile(pf_fd, tile) {
> for (i = 0; i < num_checks; ++i)
> if (subcheck_can_proceed(&checks[i]))
> - checks[i].prepare_vf(vf_id, checks[i].data);
> + checks[i].init(checks[i].data, tile);
> +
> + for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> + for (i = 0; i < num_checks; ++i)
> + if (subcheck_can_proceed(&checks[i]))
> + checks[i].prepare_vf(checks[i].data, tile, vf_id);
> + }
>
> if (no_subchecks_can_proceed(checks, num_checks))
> goto cleanup;
> @@ -299,7 +328,7 @@ static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
>
> cleanup:
> for (i = 0; i < num_checks; ++i)
> - checks[i].cleanup(checks[i].data);
> + checks[i].cleanup(checks[i].data, num_tiles);
>
> disable_vfs:
> igt_sriov_disable_vfs(pf_fd);
> @@ -315,6 +344,7 @@ static int execute_sequential_flr(int pf_fd, int num_vfs,
> const int wait_flr_ms)
> {
> int i, vf_id, flr_vf_id = 1;
> + uint8_t tile;
>
> do {
> if (igt_warn_on_f(!igt_sriov_device_reset(pf_fd, flr_vf_id),
> @@ -324,16 +354,20 @@ static int execute_sequential_flr(int pf_fd, int num_vfs,
> /* Assume FLR is finished after wait_flr_ms */
> usleep(wait_flr_ms * 1000);
>
> - for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> - for (i = 0; i < num_checks; ++i)
> - if (subcheck_can_proceed(&checks[i]))
> - checks[i].verify_vf(vf_id, flr_vf_id, checks[i].data);
> -
> - /* Reinitialize test data for the FLRed VF */
> - if (flr_vf_id < num_vfs)
> - for (i = 0; i < num_checks; ++i)
> - if (subcheck_can_proceed(&checks[i]))
> - checks[i].prepare_vf(flr_vf_id, checks[i].data);
> + xe_for_each_tile(pf_fd, tile) {
> + for (vf_id = 1; vf_id <= num_vfs; ++vf_id)
> + for (i = 0; i < num_checks; ++i)
> + if (subcheck_can_proceed(&checks[i]))
> + checks[i].verify_vf(checks[i].data, tile, vf_id,
> + flr_vf_id);
> +
> + /* Reinitialize test data for the FLRed VF */
> + if (flr_vf_id < num_vfs)
> + for (i = 0; i < num_checks; ++i)
> + if (subcheck_can_proceed(&checks[i]))
> + checks[i].prepare_vf(checks[i].data, tile,
> + flr_vf_id);
> + }
>
> if (no_subchecks_can_proceed(checks, num_checks))
> break;
> @@ -431,15 +465,19 @@ cleanup_threads:
>
> /* Verify results */
> for (i = 0; i < created_threads; ++i) {
> + uint8_t tile;
> +
> vf_id = thread_data[i].vf_id;
>
> /* Skip already checked VF or if the FLR initiation failed */
> if (vf_id == last_vf_id || thread_data[i].result != 0)
> continue;
>
> - for (k = 0; k < num_checks; ++k)
> - if (subcheck_can_proceed(&checks[k]))
> - checks[k].verify_vf(vf_id, vf_id, checks[k].data);
> + xe_for_each_tile(pf_fd, tile) {
> + for (k = 0; k < num_checks; ++k)
> + if (subcheck_can_proceed(&checks[k]))
> + checks[k].verify_vf(checks[k].data, tile, vf_id, vf_id);
> + }
>
> if (no_subchecks_can_proceed(checks, num_checks))
> break;
> @@ -470,8 +508,8 @@ static int execute_parallel_flr_twice(int pf_fd, int num_vfs,
> #define GGTT_PTE_ADDR_SHIFT 12
>
> struct ggtt_ops {
> - void (*set_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
> - xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
> + void (*set_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
> + xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
> };
>
> struct ggtt_provisioned_offset_range {
> @@ -486,74 +524,89 @@ struct ggtt_provisioned_offset_range {
>
> struct ggtt_data {
> struct subcheck_data base;
> - struct ggtt_provisioned_offset_range *pte_offsets;
> + struct ggtt_provisioned_offset_range **pte_offsets;
> struct xe_mmio *mmio;
> struct ggtt_ops ggtt;
> };
>
> -static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
> +static void ggtt_subcheck_alloc(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs)
> {
> - return xe_mmio_ggtt_read(mmio, 0, pte_offset);
> + struct ggtt_data *gdata = (struct ggtt_data *)data;
> +
> + gdata->pte_offsets = calloc(num_tiles, sizeof(*gdata->pte_offsets));
> + if (!gdata->pte_offsets) {
> + set_abort_reason(data, "Failed to allocate memory for pte_offsets array\n");
> + return;
> + }
> +
> + for (uint8_t tile = 0; tile < num_tiles; tile++) {
> + gdata->pte_offsets[tile] = calloc(num_vfs + 1, sizeof(**gdata->pte_offsets));
> + if (!gdata->pte_offsets[tile]) {
> + set_abort_reason(data, "Failed to allocate memory for pte_offsets[%u]\n",
> + tile);
> + return;
> + }
> + }
> }
>
> -static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
> +static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset)
> {
> - xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
> + return xe_mmio_ggtt_read(mmio, tile, pte_offset);
> }
>
> -static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
> +static void intel_set_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset,
> + xe_ggtt_pte_t pte)
> {
> - xe_mmio_ggtt_write(mmio, 0, pte_offset, pte);
> + xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
> +}
> +
> +static void intel_mtl_set_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset,
> + xe_ggtt_pte_t pte)
> +{
> + xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
>
> /* force flush by read some MMIO register */
> - xe_mmio_tile_read32(mmio, 0, GEN12_VF_CAP_REG);
> + xe_mmio_tile_read32(mmio, tile, GEN12_VF_CAP_REG);
> }
>
> -static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> - uint8_t gpa, xe_ggtt_pte_t *out)
> +static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
> + uint32_t pte_offset, uint8_t gpa, xe_ggtt_pte_t *out)
> {
> xe_ggtt_pte_t pte;
>
> - pte = ggtt->get_pte(mmio, gt, pte_offset);
> + pte = ggtt->get_pte(mmio, tile, pte_offset);
> pte &= ~GGTT_PTE_TEST_FIELD_MASK;
> pte |= ((xe_ggtt_pte_t)gpa << GGTT_PTE_ADDR_SHIFT) & GGTT_PTE_TEST_FIELD_MASK;
> - ggtt->set_pte(mmio, gt, pte_offset, pte);
> - *out = ggtt->get_pte(mmio, gt, pte_offset);
> + ggtt->set_pte(mmio, tile, pte_offset, pte);
> + *out = ggtt->get_pte(mmio, tile, pte_offset);
>
> return *out == pte;
> }
>
> -static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> - uint8_t expected_gpa, xe_ggtt_pte_t *out)
> +static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
> + uint32_t pte_offset, uint8_t expected_gpa, xe_ggtt_pte_t *out)
> {
> uint8_t val;
>
> - *out = ggtt->get_pte(mmio, gt, pte_offset);
> + *out = ggtt->get_pte(mmio, tile, pte_offset);
> val = (uint8_t)((*out & GGTT_PTE_TEST_FIELD_MASK) >> GGTT_PTE_ADDR_SHIFT);
>
> return val == expected_gpa;
> }
>
> -static bool is_intel_mmio_initialized(const struct intel_mmio_data *mmio)
> -{
> - return mmio->dev;
> -}
> -
> -static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
> +static void populate_ggtt_pte_offsets(struct ggtt_data *gdata, uint8_t tile)
> {
> int ret, pf_fd = gdata->base.pf_fd, num_vfs = gdata->base.num_vfs;
> struct xe_sriov_provisioned_range *ranges;
> - unsigned int nr_ranges, gt = gdata->base.gt;
> + unsigned int nr_ranges;
>
> - gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
> - igt_assert(gdata->pte_offsets);
> -
> - ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, 0, gdata->mmio,
> + ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, tile, gdata->mmio,
> &ranges, &nr_ranges);
> if (ret) {
> - set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
> - gt, ret);
> - return -1;
> + set_abort_reason(&gdata->base,
> + "Tile%u: Failed to scan GGTT PTE offset ranges (%d)\n",
> + tile, ret);
> + return;
> }
>
> for (unsigned int i = 0; i < nr_ranges; ++i) {
> @@ -563,46 +616,38 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
> continue;
>
> if (vf_id < 1 || vf_id > num_vfs) {
> - set_skip_reason(&gdata->base, "Unexpected VF%u at range entry %u [%#" PRIx64 "-%#" PRIx64 "], num_vfs=%u\n",
> - vf_id, i, ranges[i].start, ranges[i].end, num_vfs);
> - free(ranges);
> - return -1;
> + set_abort_reason(&gdata->base,
> + "Tile%u: Unexpected VF%u at range entry %u [%#" PRIx64 "-%#" PRIx64 "], num_vfs=%u\n",
> + tile, vf_id, i, ranges[i].start, ranges[i].end, num_vfs);
> + goto out;
> }
>
> - if (gdata->pte_offsets[vf_id].end) {
> - set_skip_reason(&gdata->base, "Duplicate GGTT PTE offset range for VF%u\n",
> - vf_id);
> - free(ranges);
> - return -1;
> + if (gdata->pte_offsets[tile][vf_id].end) {
> + set_abort_reason(&gdata->base,
> + "Tile%u: Duplicate GGTT PTE offset range for VF%u\n",
> + tile, vf_id);
> + goto out;
> }
>
> - gdata->pte_offsets[vf_id].start = ranges[i].start;
> - gdata->pte_offsets[vf_id].end = ranges[i].end;
> + gdata->pte_offsets[tile][vf_id].start = ranges[i].start;
> + gdata->pte_offsets[tile][vf_id].end = ranges[i].end;
> }
>
> - free(ranges);
> -
> for (int vf_id = 1; vf_id <= num_vfs; ++vf_id)
> - if (!gdata->pte_offsets[vf_id].end) {
> - set_skip_reason(&gdata->base,
> - "Failed to find VF%u provisioned GGTT PTE offset range\n",
> - vf_id);
> - return -1;
> + if (!gdata->pte_offsets[tile][vf_id].end) {
> + set_abort_reason(&gdata->base,
> + "Tile%u: Failed to find VF%u provisioned GGTT PTE offset range\n",
> + tile, vf_id);
> + goto out;
> }
> -
> - return 0;
> +out:
> + free(ranges);
> }
>
> -static void ggtt_subcheck_init(struct subcheck_data *data)
> +static void ggtt_subcheck_init(struct subcheck_data *data, uint8_t tile)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
>
> - if (!xe_is_main_gt(data->pf_fd, data->gt)) {
> - set_skip_reason(data, "GGTT provisioning not exposed on GT%d (non-MAIN)\n",
> - data->gt);
> - return;
> - }
> -
> gdata->ggtt.get_pte = intel_get_pte;
> if (IS_METEORLAKE(intel_get_drm_devid(data->pf_fd)))
> gdata->ggtt.set_pte = intel_mtl_set_pte;
> @@ -610,16 +655,16 @@ static void ggtt_subcheck_init(struct subcheck_data *data)
> gdata->ggtt.set_pte = intel_set_pte;
>
> if (gdata->mmio) {
> - if (!is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
> - xe_mmio_vf_access_init(data->pf_fd, 0 /*PF*/, gdata->mmio);
> + if (!xe_mmio_is_initialized(gdata->mmio))
> + xe_mmio_access_init(data->pf_fd, gdata->mmio);
>
> - populate_ggtt_pte_offsets(gdata);
> + populate_ggtt_pte_offsets(gdata, tile);
> } else {
> - set_skip_reason(data, "xe_mmio is NULL\n");
> + set_abort_reason(data, "xe_mmio is NULL\n");
> }
> }
>
> -static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> +static void ggtt_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
> xe_ggtt_pte_t pte;
> @@ -628,22 +673,23 @@ static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> if (data->stop_reason)
> return;
>
> - igt_debug("Prepare gpa on VF%u offset range [%#x-%#x]\n", vf_id,
> - gdata->pte_offsets[vf_id].start,
> - gdata->pte_offsets[vf_id].end);
> + igt_debug("Tile%u: Prepare gpa on VF%u offset range [%#x-%#x]\n", tile, vf_id,
> + gdata->pte_offsets[tile][vf_id].start,
> + gdata->pte_offsets[tile][vf_id].end);
>
> - for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
> - if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
> + for_each_pte_offset(pte_offset, &gdata->pte_offsets[tile][vf_id]) {
> + if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, tile, pte_offset,
> (uint8_t)vf_id, &pte)) {
> set_skip_reason(data,
> - "Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x\n",
> - vf_id, pte, pte_offset);
> + "Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x on tile%u\n",
> + vf_id, pte, pte_offset, tile);
> return;
> }
> }
> }
>
> -static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
> +static void ggtt_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
> + int flr_vf_id)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
> uint8_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
> @@ -653,33 +699,62 @@ static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> if (data->stop_reason)
> return;
>
> - for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
> - if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
> + for_each_pte_offset(pte_offset, &gdata->pte_offsets[tile][vf_id]) {
> + if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, tile, pte_offset,
> expected, &pte)) {
> set_fail_reason(data,
> - "GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
> - flr_vf_id, vf_id, pte, pte_offset);
> + "Tile%u: GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
> + tile, flr_vf_id, vf_id, pte, pte_offset);
> return;
> }
> }
> }
>
> -static void ggtt_subcheck_cleanup(struct subcheck_data *data)
> +static void ggtt_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
> {
> struct ggtt_data *gdata = (struct ggtt_data *)data;
>
> - free(gdata->pte_offsets);
> - if (gdata->mmio && is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
> + if (gdata->pte_offsets) {
> + for (uint8_t tile = 0; tile < num_tiles; tile++)
> + free(gdata->pte_offsets[tile]);
> + free(gdata->pte_offsets);
> + }
> +
> + if (gdata->mmio && xe_mmio_is_initialized(gdata->mmio))
> xe_mmio_access_fini(gdata->mmio);
> }
> -
> struct lmem_data {
> struct subcheck_data base;
> - size_t *vf_lmem_size;
> + size_t **vf_lmem_size;
> };
>
> const size_t STEP = SZ_1M;
>
> +static void lmem_subcheck_alloc(struct subcheck_data *data, uint8_t num_tiles, unsigned int num_vfs)
> +{
> + struct lmem_data *ldata = (struct lmem_data *)data;
> +
> + if (!xe_has_vram(data->pf_fd)) {
> + set_skip_reason(data, "No LMEM\n");
> + return;
> + }
> +
> + ldata->vf_lmem_size = calloc(num_vfs + 1, sizeof(size_t *));
first dimension is indexed by tile, shouldn't it be num_tiles ?
> + if (!ldata->vf_lmem_size) {
> + set_abort_reason(data, "Failed to allocate memory for vf_lmem_size array\n");
> + return;
> + }
> +
> + for (uint8_t tile = 0; tile < num_tiles; tile++) {
> + ldata->vf_lmem_size[tile] = calloc(num_vfs + 1, sizeof(**ldata->vf_lmem_size));
> + if (!ldata->vf_lmem_size[tile]) {
> + set_abort_reason(data, "Failed to allocate memory for vf_lmem_size[%u]\n",
> + tile);
> + return;
> + }
> + }
looks the lmem_subcheck_cleanup is not adjusted to the new logic
if (ldata->vf_lmem_size) {
for (uint8_t tile = 0; tile < num_tiles; tile++) {
free(ldata->vf_lmem_size[tile]);
ldata->vf_lmem_size[tile] = NULL;
}
free(ldata->vf_lmem_size);
ldata->vf_lmem_size = NULL;
}
> +}
> +
> static bool lmem_write_pattern(struct vram_mapping *m, uint8_t value, size_t start, size_t step)
> {
> uint8_t read;
> @@ -735,66 +810,51 @@ static bool lmem_mmap_write_munmap(int pf_fd, int vf_num, size_t length, char va
> return result;
> }
>
> -static int populate_vf_lmem_sizes(struct subcheck_data *data)
> +static void populate_vf_lmem_sizes(struct subcheck_data *data, uint8_t tile)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
> + unsigned int main_gt = xe_tile_get_main_gt_id(data->pf_fd, tile);
> struct xe_sriov_provisioned_range *ranges;
> - unsigned int nr_ranges, gt;
> + unsigned int nr_ranges;
> int ret;
>
> - ldata->vf_lmem_size = calloc(data->num_vfs + 1, sizeof(size_t));
> - igt_assert(ldata->vf_lmem_size);
> -
> - xe_for_each_gt(data->pf_fd, gt) {
> - if (!xe_is_main_gt(data->pf_fd, gt))
> - continue;
> -
> - ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd,
> - XE_SRIOV_SHARED_RES_LMEM,
> - gt, &ranges, &nr_ranges);
> - if (ret) {
> - set_skip_reason(data, "Failed read %s on gt%u (%d)\n",
> - xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
> - gt, ret);
> - return -1;
> - }
> -
> - for (unsigned int i = 0; i < nr_ranges; ++i) {
> - const unsigned int vf_id = ranges[i].vf_id;
> + ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd, XE_SRIOV_SHARED_RES_LMEM,
> + main_gt, &ranges, &nr_ranges);
> + if (ret) {
> + set_abort_reason(data, "Tile%u: Failed read %s on main GT (%d)\n", tile,
> + xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
> + ret);
> + return;
> + }
>
> - igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
> - /* Sum the allocation for vf_id (inclusive range) */
> - ldata->vf_lmem_size[vf_id] += ranges[i].end - ranges[i].start + 1;
> - }
> + for (unsigned int i = 0; i < nr_ranges; ++i) {
> + const unsigned int vf_id = ranges[i].vf_id;
>
> - free(ranges);
> + igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
> + /* Sum the allocation for vf_id (inclusive range) */
> + ldata->vf_lmem_size[tile][vf_id] += ranges[i].end - ranges[i].start + 1;
> }
>
> + free(ranges);
> +
> for (int vf_id = 1; vf_id <= data->num_vfs; ++vf_id)
> - if (!ldata->vf_lmem_size[vf_id]) {
> - set_skip_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
> - return -1;
> + if (!ldata->vf_lmem_size[tile][vf_id]) {
> + set_abort_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
> + return;
> }
>
> - return 0;
> + return;
> }
>
> -static void lmem_subcheck_init(struct subcheck_data *data)
> +static void lmem_subcheck_init(struct subcheck_data *data, uint8_t tile)
> {
> igt_assert_fd(data->pf_fd);
> igt_assert(data->num_vfs);
>
> - if (!xe_has_vram(data->pf_fd)) {
> - set_skip_reason(data, "No LMEM\n");
> - return;
> - }
> -
> - if (populate_vf_lmem_sizes(data))
> - /* skip reason set in populate_vf_lmem_sizes */
> - return;
> + populate_vf_lmem_sizes(data, tile);
> }
>
> -static void lmem_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> +static void lmem_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
>
> @@ -804,12 +864,13 @@ static void lmem_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> igt_assert(vf_id > 0 && vf_id <= data->num_vfs);
>
> if (!lmem_mmap_write_munmap(data->pf_fd, vf_id,
> - ldata->vf_lmem_size[vf_id], vf_id)) {
> - set_skip_reason(data, "LMEM write failed on VF%u\n", vf_id);
> + ldata->vf_lmem_size[tile][vf_id], vf_id)) {
> + set_abort_reason(data, "LMEM write failed on VF%u\n", vf_id);
> }
> }
>
> -static void lmem_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
> +static void lmem_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
> + int flr_vf_id)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
> char expected = (vf_id == flr_vf_id) ? 0 : vf_id;
> @@ -818,14 +879,14 @@ static void lmem_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> return;
>
> if (!lmem_contains_expected_values(data->pf_fd, vf_id,
> - ldata->vf_lmem_size[vf_id], expected)) {
> + ldata->vf_lmem_size[tile][vf_id], expected)) {
> set_fail_reason(data,
> "LMEM check after VF%u FLR failed on VF%u\n",
> flr_vf_id, vf_id);
> }
> }
>
> -static void lmem_subcheck_cleanup(struct subcheck_data *data)
> +static void lmem_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
> {
> struct lmem_data *ldata = (struct lmem_data *)data;
>
> @@ -839,12 +900,12 @@ static void lmem_subcheck_cleanup(struct subcheck_data *data)
>
> struct regs_data {
> struct subcheck_data base;
> - struct intel_mmio_data *mmio;
> + struct xe_mmio *mmio;
> uint32_t reg_addr;
> int reg_count;
> };
>
> -static void regs_subcheck_init(struct subcheck_data *data)
> +static void regs_subcheck_init(struct subcheck_data *data, uint8_t tile)
> {
> struct regs_data *rdata = (struct regs_data *)data;
>
> @@ -854,7 +915,7 @@ static void regs_subcheck_init(struct subcheck_data *data)
> }
> }
>
> -static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> +static void regs_subcheck_prepare_vf(struct subcheck_data *data, uint8_t tile, int vf_id)
> {
> struct regs_data *rdata = (struct regs_data *)data;
> uint32_t reg;
> @@ -863,32 +924,22 @@ static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
> if (data->stop_reason)
> return;
>
> - if (!is_intel_mmio_initialized(&rdata->mmio[vf_id])) {
> - struct pci_device *pci_dev = __igt_device_get_pci_device(data->pf_fd, vf_id);
> -
> - if (!pci_dev) {
> - set_skip_reason(data, "No PCI device found for VF%u\n", vf_id);
> - return;
> - }
> -
> - if (intel_register_access_init(&rdata->mmio[vf_id], pci_dev, false)) {
> - set_skip_reason(data, "Failed to get access to VF%u MMIO\n", vf_id);
> - return;
> - }
> - }
> + if (!xe_mmio_is_initialized(&rdata->mmio[vf_id]))
> + xe_mmio_vf_access_init(data->pf_fd, vf_id, &rdata->mmio[vf_id]);
>
> for (i = 0; i < rdata->reg_count; i++) {
> reg = rdata->reg_addr + i * 4;
>
> - intel_register_write(&rdata->mmio[vf_id], reg, vf_id);
> - if (intel_register_read(&rdata->mmio[vf_id], reg) != vf_id) {
> + xe_mmio_tile_write32(&rdata->mmio[vf_id], tile, reg, vf_id);
> + if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != vf_id) {
> set_skip_reason(data, "Registers write/read check failed on VF%u\n", vf_id);
> return;
> }
> }
> }
>
> -static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
> +static void regs_subcheck_verify_vf(struct subcheck_data *data, uint8_t tile, int vf_id,
> + int flr_vf_id)
> {
> struct regs_data *rdata = (struct regs_data *)data;
> uint32_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
> @@ -901,7 +952,7 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> for (i = 0; i < rdata->reg_count; i++) {
> reg = rdata->reg_addr + i * 4;
>
> - if (intel_register_read(&rdata->mmio[vf_id], reg) != expected) {
> + if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != expected) {
> set_fail_reason(data,
> "Registers check after VF%u FLR failed on VF%u\n",
> flr_vf_id, vf_id);
> @@ -910,84 +961,86 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
> }
> }
>
> -static void regs_subcheck_cleanup(struct subcheck_data *data)
> +static void regs_subcheck_cleanup(struct subcheck_data *data, uint8_t num_tiles)
> {
> struct regs_data *rdata = (struct regs_data *)data;
> int i;
>
> if (rdata->mmio)
> for (i = 1; i <= data->num_vfs; ++i)
> - if (is_intel_mmio_initialized(&rdata->mmio[i]))
> - intel_register_access_fini(&rdata->mmio[i]);
> + if (xe_mmio_is_initialized(&rdata->mmio[i]))
> + xe_mmio_access_fini(&rdata->mmio[i]);
> }
>
> -static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
> +static void clear_tests(const int pf_fd, const unsigned int num_vfs,
> + const flr_exec_strategy exec_strategy)
> {
> - struct xe_mmio xemmio = { };
> - const unsigned int num_gts = xe_number_gt(pf_fd);
> - struct ggtt_data gdata[num_gts];
> + struct subcheck_data base = { .pf_fd = pf_fd, .num_vfs = num_vfs };
> + struct xe_mmio *mmio = calloc(1 + num_vfs, sizeof(*mmio));
> + struct ggtt_data gdata = {
> + .base = base,
> + .mmio = mmio,
> + };
> struct lmem_data ldata = {
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs }
> + .base = base,
> };
> - struct intel_mmio_data mmio[num_vfs + 1];
> struct regs_data scratch_data = {
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
> + .base = base,
> .mmio = mmio,
> .reg_addr = SCRATCH_REG,
> .reg_count = SCRATCH_REG_COUNT
> };
> struct regs_data media_scratch_data = {
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
> + .base = base,
> .mmio = mmio,
> .reg_addr = MED_SCRATCH_REG,
> .reg_count = MED_SCRATCH_REG_COUNT
> };
> - const unsigned int num_checks = num_gts + 3;
> - struct subcheck checks[num_checks];
> - int i = 0, gt_id;
> -
> - memset(mmio, 0, sizeof(mmio));
> -
> - xe_for_each_gt(pf_fd, gt_id) {
> - gdata[i] = (struct ggtt_data){
> - .base = { .pf_fd = pf_fd, .num_vfs = num_vfs, .gt = gt_id },
> - .mmio = &xemmio
> - };
> - checks[i] = (struct subcheck){
> - .data = (struct subcheck_data *)&gdata[i],
> + struct subcheck checks[] = {
> + {
> + .data = (struct subcheck_data *)&gdata,
> .name = "clear-ggtt",
> + .alloc = ggtt_subcheck_alloc,
> .init = ggtt_subcheck_init,
> .prepare_vf = ggtt_subcheck_prepare_vf,
> .verify_vf = ggtt_subcheck_verify_vf,
> .cleanup = ggtt_subcheck_cleanup
> - };
> - i++;
> - }
> - checks[i++] = (struct subcheck) {
> - .data = (struct subcheck_data *)&ldata,
> - .name = "clear-lmem",
> - .init = lmem_subcheck_init,
> - .prepare_vf = lmem_subcheck_prepare_vf,
> - .verify_vf = lmem_subcheck_verify_vf,
> - .cleanup = lmem_subcheck_cleanup };
> - checks[i++] = (struct subcheck) {
> - .data = (struct subcheck_data *)&scratch_data,
> - .name = "clear-scratch-regs",
> - .init = regs_subcheck_init,
> - .prepare_vf = regs_subcheck_prepare_vf,
> - .verify_vf = regs_subcheck_verify_vf,
> - .cleanup = regs_subcheck_cleanup };
> - checks[i++] = (struct subcheck) {
> - .data = (struct subcheck_data *)&media_scratch_data,
> - .name = "clear-media-scratch-regs",
> - .init = regs_subcheck_init,
> - .prepare_vf = regs_subcheck_prepare_vf,
> - .verify_vf = regs_subcheck_verify_vf,
> - .cleanup = regs_subcheck_cleanup
> + },
> + {
> + .data = (struct subcheck_data *)&ldata,
> + .name = "clear-lmem",
> + .alloc = lmem_subcheck_alloc,
> + .init = lmem_subcheck_init,
> + .prepare_vf = lmem_subcheck_prepare_vf,
> + .verify_vf = lmem_subcheck_verify_vf,
> + .cleanup = lmem_subcheck_cleanup
> + },
> + {
> + .data = (struct subcheck_data *)&scratch_data,
> + .name = "clear-scratch-regs",
> + .alloc = NULL,
> + .init = regs_subcheck_init,
> + .prepare_vf = regs_subcheck_prepare_vf,
> + .verify_vf = regs_subcheck_verify_vf,
> + .cleanup = regs_subcheck_cleanup
> + },
> + {
> + .data = (struct subcheck_data *)&media_scratch_data,
> + .name = "clear-media-scratch-regs",
> + .alloc = NULL,
> + .init = regs_subcheck_init,
> + .prepare_vf = regs_subcheck_prepare_vf,
> + .verify_vf = regs_subcheck_verify_vf,
> + .cleanup = regs_subcheck_cleanup
> + }
> +
> };
> - igt_assert_eq(i, num_checks);
>
> - verify_flr(pf_fd, num_vfs, checks, num_checks, exec_strategy);
> + igt_abort_on_f(!mmio, "Failed to allocate memory for mmio array\n");
> +
> + verify_flr(pf_fd, num_vfs, checks, ARRAY_SIZE(checks), exec_strategy);
> +
> + free(mmio);
> }
>
> igt_main
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2025-10-23 14:43 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
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2025-10-20 16:26 [PATCH v1 0/3] Multi-tile support for xe_sriov_flr and other MMIO improvements Piórkowski, Piotr
2025-10-20 16:26 ` [PATCH v1 1/3] lib/xe_mmio: Introduce tile-level XE MMIO access helpers Piórkowski, Piotr
2025-10-22 11:54 ` Sokolowski, Jan
2025-10-20 16:26 ` [PATCH v1 2/3] lib/xe_mmio: Add init flag and helper to check initialization Piórkowski, Piotr
2025-10-22 11:55 ` Sokolowski, Jan
2025-10-20 16:26 ` [PATCH v1 3/3] tests/xe_sriov_flr: extend VF FLR test for multi-tile Xe devices Piórkowski, Piotr
2025-10-23 10:43 ` Bernatowicz, Marcin
2025-10-23 11:56 ` Bernatowicz, Marcin
2025-10-23 14:43 ` Bernatowicz, Marcin
2025-10-21 2:23 ` ✓ i915.CI.BAT: success for Multi-tile support for xe_sriov_flr and other MMIO improvements Patchwork
2025-10-21 4:20 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-21 5:50 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-21 12:15 ` Patchwork
2025-10-21 17:29 ` ✗ i915.CI.Full: " Patchwork
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