[igt-dev] [PATCH i-g-t] igt/i915/i915_pm_lpsp enable pm_lpsp for platforms till Gen11.

* [igt-dev] [PATCH i-g-t] igt/i915/i915_pm_lpsp enable pm_lpsp for platforms till Gen11.
@ 2019-03-15 10:58 Anshuman Gupta
  2019-03-18  8:33 ` [igt-dev] ✓ Fi.CI.BAT: success for igt/i915/i915_pm_lpsp enable pm_lpsp for platforms till Gen11. (rev2) Patchwork
  2019-03-18 10:20 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
  0 siblings, 2 replies; 4+ messages in thread
From: Anshuman Gupta @ 2019-03-15 10:58 UTC (permalink / raw)
  To: intel-gfx, igt-dev

Enabling pm_lpsp igt tests for Gen11 as well as for all platforms
at least gen9, earlier these test were enabled only haswell and broadwell
platforms.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/i915/i915_pm_lpsp.c | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/tests/i915/i915_pm_lpsp.c b/tests/i915/i915_pm_lpsp.c
index b319dbe..f7037ce 100644
--- a/tests/i915/i915_pm_lpsp.c
+++ b/tests/i915/i915_pm_lpsp.c
@@ -30,18 +30,42 @@
 #include <fcntl.h>
 #include <unistd.h>
 
+#define   HSW_PW_CTL_IDX_GLOBAL                 15
+#define   SKL_PW_CTL_IDX_PW_2                   15
+#define   ICL_PW_CTL_IDX_PW_3                   2
+
+#define   HSW_PWR_WELL_CTL_REQ(pw_idx)          (0x2 << ((pw_idx) * 2))
+#define   HSW_PWR_WELL_CTL_STATE(pw_idx)        (0x1 << ((pw_idx) * 2))
+
+int no_lpsp_pw_idx;
 
 static bool supports_lpsp(uint32_t devid)
 {
-	return IS_HASWELL(devid) || IS_BROADWELL(devid);
+	return IS_HASWELL(devid) || IS_BROADWELL(devid) || AT_LEAST_GEN(devid, 9);
+}
+
+static bool get_no_lpsp_pw_idx(uint32_t devid)
+{
+	if (IS_HASWELL(devid) || IS_BROADWELL(devid))
+		no_lpsp_pw_idx = HSW_PW_CTL_IDX_GLOBAL;
+	else if (IS_GEN(devid, 11))
+		no_lpsp_pw_idx = ICL_PW_CTL_IDX_PW_3;
+	else if (AT_LEAST_GEN(devid, 9))
+		no_lpsp_pw_idx = SKL_PW_CTL_IDX_PW_2;
+	else
+		return false;
+
+	return true;
 }
 
 static bool lpsp_is_enabled(int drm_fd)
 {
 	uint32_t val;
+	uint32_t mask = HSW_PWR_WELL_CTL_REQ(no_lpsp_pw_idx) |
+			HSW_PWR_WELL_CTL_STATE(no_lpsp_pw_idx);
 
 	val = INREG(HSW_PWR_WELL_CTL2);
-	return !(val & HSW_PWR_WELL_STATE_ENABLED);
+	return !((val & mask) == mask);
 }
 
 /* The LPSP mode is all about an enabled pipe, but we expect to also be in the
@@ -212,6 +236,7 @@ igt_main
 
 		intel_register_access_init(intel_get_pci_device(), 0, drm_fd);
 
+		igt_require(get_no_lpsp_pw_idx(devid));
 		kmstest_set_vt_graphics_mode();
 	}
 
-- 
2.7.4

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