* [igt-dev] [PATCH i-g-t 0/2] Engine discovery tests
@ 2019-05-01 11:42 Tvrtko Ursulin
2019-05-01 11:42 ` [igt-dev] [PATCH i-g-t 1/2] headers: bump Tvrtko Ursulin
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Tvrtko Ursulin @ 2019-05-01 11:42 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx, Tvrtko Ursulin
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
As usual, second patch is the only one to be looked at.
Tvrtko Ursulin (2):
headers: bump
tests/i915_query: Engine discovery tests
include/drm-uapi/amdgpu_drm.h | 52 ++++++-
include/drm-uapi/drm.h | 36 +++++
include/drm-uapi/drm_mode.h | 4 +-
include/drm-uapi/i915_drm.h | 42 ++++++
include/drm-uapi/lima_drm.h | 169 ++++++++++++++++++++++
include/drm-uapi/msm_drm.h | 14 ++
include/drm-uapi/nouveau_drm.h | 51 +++++++
include/drm-uapi/panfrost_drm.h | 142 ++++++++++++++++++
include/drm-uapi/v3d_drm.h | 28 ++++
tests/i915/i915_query.c | 247 ++++++++++++++++++++++++++++++++
10 files changed, 782 insertions(+), 3 deletions(-)
create mode 100644 include/drm-uapi/lima_drm.h
create mode 100644 include/drm-uapi/panfrost_drm.h
--
2.19.1
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^ permalink raw reply [flat|nested] 8+ messages in thread* [igt-dev] [PATCH i-g-t 1/2] headers: bump 2019-05-01 11:42 [igt-dev] [PATCH i-g-t 0/2] Engine discovery tests Tvrtko Ursulin @ 2019-05-01 11:42 ` Tvrtko Ursulin 2019-05-01 11:42 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests Tvrtko Ursulin ` (2 subsequent siblings) 3 siblings, 0 replies; 8+ messages in thread From: Tvrtko Ursulin @ 2019-05-01 11:42 UTC (permalink / raw) To: igt-dev; +Cc: Intel-gfx, Tvrtko Ursulin From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Catch up to drm-tip headers. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- include/drm-uapi/amdgpu_drm.h | 52 +++++++++- include/drm-uapi/drm.h | 36 +++++++ include/drm-uapi/drm_mode.h | 4 +- include/drm-uapi/i915_drm.h | 42 ++++++++ include/drm-uapi/lima_drm.h | 169 ++++++++++++++++++++++++++++++++ include/drm-uapi/msm_drm.h | 14 +++ include/drm-uapi/nouveau_drm.h | 51 ++++++++++ include/drm-uapi/panfrost_drm.h | 142 +++++++++++++++++++++++++++ include/drm-uapi/v3d_drm.h | 28 ++++++ 9 files changed, 535 insertions(+), 3 deletions(-) create mode 100644 include/drm-uapi/lima_drm.h create mode 100644 include/drm-uapi/panfrost_drm.h diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h index be84e43c1e19..4788730dbe78 100644 --- a/include/drm-uapi/amdgpu_drm.h +++ b/include/drm-uapi/amdgpu_drm.h @@ -210,6 +210,9 @@ union drm_amdgpu_bo_list { #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) /* indicate some job from this context once cause gpu hang */ #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) +/* indicate some errors are detected by RAS */ +#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) +#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) /* Context priority level */ #define AMDGPU_CTX_PRIORITY_UNSET -2048 @@ -272,13 +275,14 @@ union drm_amdgpu_vm { /* sched ioctl */ #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 +#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 struct drm_amdgpu_sched_in { /* AMDGPU_SCHED_OP_* */ __u32 op; __u32 fd; __s32 priority; - __u32 flags; + __u32 ctx_id; }; union drm_amdgpu_sched { @@ -523,6 +527,9 @@ struct drm_amdgpu_gem_va { #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 +#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 +#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 +#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 struct drm_amdgpu_cs_chunk { __u32 chunk_id; @@ -565,6 +572,11 @@ union drm_amdgpu_cs { * caches (L2/vL1/sL1/I$). */ #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) +/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. + * This will reset wave ID counters for the IB. + */ +#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) + struct drm_amdgpu_cs_chunk_ib { __u32 _pad; /** AMDGPU_IB_FLAG_* */ @@ -598,6 +610,12 @@ struct drm_amdgpu_cs_chunk_sem { __u32 handle; }; +struct drm_amdgpu_cs_chunk_syncobj { + __u32 handle; + __u32 flags; + __u64 point; +}; + #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 @@ -673,6 +691,7 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 /* Subquery id: Query DMCU firmware version */ #define AMDGPU_INFO_FW_DMCU 0x12 + #define AMDGPU_INFO_FW_TA 0x13 /* number of bytes moved for TTM migration */ #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f /* the used VRAM size */ @@ -726,6 +745,37 @@ struct drm_amdgpu_cs_chunk_data { /* Number of VRAM page faults on CPU access. */ #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F +/* query ras mask of enabled features*/ +#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 + +/* RAS MASK: UMC (VRAM) */ +#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) +/* RAS MASK: SDMA */ +#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) +/* RAS MASK: GFX */ +#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) +/* RAS MASK: MMHUB */ +#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) +/* RAS MASK: ATHUB */ +#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) +/* RAS MASK: PCIE */ +#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) +/* RAS MASK: HDP */ +#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) +/* RAS MASK: XGMI */ +#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) +/* RAS MASK: DF */ +#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) +/* RAS MASK: SMN */ +#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) +/* RAS MASK: SEM */ +#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) +/* RAS MASK: MP0 */ +#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) +/* RAS MASK: MP1 */ +#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) +/* RAS MASK: FUSE */ +#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/drm.h index 85c685a2075e..c893f3b4a895 100644 --- a/include/drm-uapi/drm.h +++ b/include/drm-uapi/drm.h @@ -729,8 +729,18 @@ struct drm_syncobj_handle { __u32 pad; }; +struct drm_syncobj_transfer { + __u32 src_handle; + __u32 dst_handle; + __u64 src_point; + __u64 dst_point; + __u32 flags; + __u32 pad; +}; + #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) +#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */ struct drm_syncobj_wait { __u64 handles; /* absolute timeout */ @@ -741,12 +751,33 @@ struct drm_syncobj_wait { __u32 pad; }; +struct drm_syncobj_timeline_wait { + __u64 handles; + /* wait on specific timeline point for every handles*/ + __u64 points; + /* absolute timeout */ + __s64 timeout_nsec; + __u32 count_handles; + __u32 flags; + __u32 first_signaled; /* only valid when not waiting all */ + __u32 pad; +}; + + struct drm_syncobj_array { __u64 handles; __u32 count_handles; __u32 pad; }; +struct drm_syncobj_timeline_array { + __u64 handles; + __u64 points; + __u32 count_handles; + __u32 pad; +}; + + /* Query current scanout sequence number */ struct drm_crtc_get_sequence { __u32 crtc_id; /* requested crtc_id */ @@ -903,6 +934,11 @@ extern "C" { #define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) +#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) +#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) +#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) +#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) + /** * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x9f. diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h index a439c2e67896..83cd1636b9be 100644 --- a/include/drm-uapi/drm_mode.h +++ b/include/drm-uapi/drm_mode.h @@ -33,7 +33,6 @@ extern "C" { #endif -#define DRM_DISPLAY_INFO_LEN 32 #define DRM_CONNECTOR_NAME_LEN 32 #define DRM_DISPLAY_MODE_LEN 32 #define DRM_PROP_NAME_LEN 32 @@ -622,7 +621,8 @@ struct drm_color_ctm { struct drm_color_lut { /* - * Data is U0.16 fixed point format. + * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and + * 0xffff == 1.0. */ __u16 red; __u16 green; diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h index e01b3e1fd6d6..dff8504a4e1b 100644 --- a/include/drm-uapi/i915_drm.h +++ b/include/drm-uapi/i915_drm.h @@ -1821,6 +1821,7 @@ struct drm_i915_perf_oa_config { struct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1 +#define DRM_I915_QUERY_ENGINE_INFO 2 /* Must be kept compact -- no holes and well documented */ /* @@ -1919,6 +1920,47 @@ struct drm_i915_query_topology_info { __u8 data[]; }; +/** + * struct drm_i915_engine_info + * + * Describes one engine and it's capabilities as known to the driver. + */ +struct drm_i915_engine_info { + /** Engine class and instance. */ + struct i915_engine_class_instance engine; + + /** Reserved field. */ + __u32 rsvd0; + + /** Engine flags. */ + __u64 flags; + + /** Capabilities of this engine. */ + __u64 capabilities; +#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) +#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) + + /** Reserved fields. */ + __u64 rsvd1[4]; +}; + +/** + * struct drm_i915_query_engine_info + * + * Engine info query enumerates all engines known to the driver by filling in + * an array of struct drm_i915_engine_info structures. + */ +struct drm_i915_query_engine_info { + /** Number of struct drm_i915_engine_info structs following. */ + __u32 num_engines; + + /** MBZ */ + __u32 rsvd[3]; + + /** Marker for drm_i915_engine_info structures. */ + struct drm_i915_engine_info engines[]; +}; + #if defined(__cplusplus) } #endif diff --git a/include/drm-uapi/lima_drm.h b/include/drm-uapi/lima_drm.h new file mode 100644 index 000000000000..95a00fb867e6 --- /dev/null +++ b/include/drm-uapi/lima_drm.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */ +/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */ + +#ifndef __LIMA_DRM_H__ +#define __LIMA_DRM_H__ + +#include "drm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +enum drm_lima_param_gpu_id { + DRM_LIMA_PARAM_GPU_ID_UNKNOWN, + DRM_LIMA_PARAM_GPU_ID_MALI400, + DRM_LIMA_PARAM_GPU_ID_MALI450, +}; + +enum drm_lima_param { + DRM_LIMA_PARAM_GPU_ID, + DRM_LIMA_PARAM_NUM_PP, + DRM_LIMA_PARAM_GP_VERSION, + DRM_LIMA_PARAM_PP_VERSION, +}; + +/** + * get various information of the GPU + */ +struct drm_lima_get_param { + __u32 param; /* in, value in enum drm_lima_param */ + __u32 pad; /* pad, must be zero */ + __u64 value; /* out, parameter value */ +}; + +/** + * create a buffer for used by GPU + */ +struct drm_lima_gem_create { + __u32 size; /* in, buffer size */ + __u32 flags; /* in, currently no flags, must be zero */ + __u32 handle; /* out, GEM buffer handle */ + __u32 pad; /* pad, must be zero */ +}; + +/** + * get information of a buffer + */ +struct drm_lima_gem_info { + __u32 handle; /* in, GEM buffer handle */ + __u32 va; /* out, virtual address mapped into GPU MMU */ + __u64 offset; /* out, used to mmap this buffer to CPU */ +}; + +#define LIMA_SUBMIT_BO_READ 0x01 +#define LIMA_SUBMIT_BO_WRITE 0x02 + +/* buffer information used by one task */ +struct drm_lima_gem_submit_bo { + __u32 handle; /* in, GEM buffer handle */ + __u32 flags; /* in, buffer read/write by GPU */ +}; + +#define LIMA_GP_FRAME_REG_NUM 6 + +/* frame used to setup GP for each task */ +struct drm_lima_gp_frame { + __u32 frame[LIMA_GP_FRAME_REG_NUM]; +}; + +#define LIMA_PP_FRAME_REG_NUM 23 +#define LIMA_PP_WB_REG_NUM 12 + +/* frame used to setup mali400 GPU PP for each task */ +struct drm_lima_m400_pp_frame { + __u32 frame[LIMA_PP_FRAME_REG_NUM]; + __u32 num_pp; + __u32 wb[3 * LIMA_PP_WB_REG_NUM]; + __u32 plbu_array_address[4]; + __u32 fragment_stack_address[4]; +}; + +/* frame used to setup mali450 GPU PP for each task */ +struct drm_lima_m450_pp_frame { + __u32 frame[LIMA_PP_FRAME_REG_NUM]; + __u32 num_pp; + __u32 wb[3 * LIMA_PP_WB_REG_NUM]; + __u32 use_dlbu; + __u32 _pad; + union { + __u32 plbu_array_address[8]; + __u32 dlbu_regs[4]; + }; + __u32 fragment_stack_address[8]; +}; + +#define LIMA_PIPE_GP 0x00 +#define LIMA_PIPE_PP 0x01 + +#define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0) + +/** + * submit a task to GPU + * + * User can always merge multi sync_file and drm_syncobj + * into one drm_syncobj as in_sync[0], but we reserve + * in_sync[1] for another task's out_sync to avoid the + * export/import/merge pass when explicit sync. + */ +struct drm_lima_gem_submit { + __u32 ctx; /* in, context handle task is submitted to */ + __u32 pipe; /* in, which pipe to use, GP/PP */ + __u32 nr_bos; /* in, array length of bos field */ + __u32 frame_size; /* in, size of frame field */ + __u64 bos; /* in, array of drm_lima_gem_submit_bo */ + __u64 frame; /* in, GP/PP frame */ + __u32 flags; /* in, submit flags */ + __u32 out_sync; /* in, drm_syncobj handle used to wait task finish after submission */ + __u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */ +}; + +#define LIMA_GEM_WAIT_READ 0x01 +#define LIMA_GEM_WAIT_WRITE 0x02 + +/** + * wait pending GPU task finish of a buffer + */ +struct drm_lima_gem_wait { + __u32 handle; /* in, GEM buffer handle */ + __u32 op; /* in, CPU want to read/write this buffer */ + __s64 timeout_ns; /* in, wait timeout in absulute time */ +}; + +/** + * create a context + */ +struct drm_lima_ctx_create { + __u32 id; /* out, context handle */ + __u32 _pad; /* pad, must be zero */ +}; + +/** + * free a context + */ +struct drm_lima_ctx_free { + __u32 id; /* in, context handle */ + __u32 _pad; /* pad, must be zero */ +}; + +#define DRM_LIMA_GET_PARAM 0x00 +#define DRM_LIMA_GEM_CREATE 0x01 +#define DRM_LIMA_GEM_INFO 0x02 +#define DRM_LIMA_GEM_SUBMIT 0x03 +#define DRM_LIMA_GEM_WAIT 0x04 +#define DRM_LIMA_CTX_CREATE 0x05 +#define DRM_LIMA_CTX_FREE 0x06 + +#define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param) +#define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create) +#define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info) +#define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit) +#define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait) +#define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create) +#define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free) + +#if defined(__cplusplus) +} +#endif + +#endif /* __LIMA_DRM_H__ */ diff --git a/include/drm-uapi/msm_drm.h b/include/drm-uapi/msm_drm.h index 91a16b333c69..0b85ed6a3710 100644 --- a/include/drm-uapi/msm_drm.h +++ b/include/drm-uapi/msm_drm.h @@ -74,6 +74,8 @@ struct drm_msm_timespec { #define MSM_PARAM_TIMESTAMP 0x05 #define MSM_PARAM_GMEM_BASE 0x06 #define MSM_PARAM_NR_RINGS 0x07 +#define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */ +#define MSM_PARAM_FAULTS 0x09 struct drm_msm_param { __u32 pipe; /* in, MSM_PIPE_x */ @@ -286,6 +288,16 @@ struct drm_msm_submitqueue { __u32 id; /* out, identifier */ }; +#define MSM_SUBMITQUEUE_PARAM_FAULTS 0 + +struct drm_msm_submitqueue_query { + __u64 data; + __u32 id; + __u32 param; + __u32 len; + __u32 pad; +}; + #define DRM_MSM_GET_PARAM 0x00 /* placeholder: #define DRM_MSM_SET_PARAM 0x01 @@ -302,6 +314,7 @@ struct drm_msm_submitqueue { */ #define DRM_MSM_SUBMITQUEUE_NEW 0x0A #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B +#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) @@ -313,6 +326,7 @@ struct drm_msm_submitqueue { #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) +#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) #if defined(__cplusplus) } diff --git a/include/drm-uapi/nouveau_drm.h b/include/drm-uapi/nouveau_drm.h index 259588a4b61b..9459a6e3bc1f 100644 --- a/include/drm-uapi/nouveau_drm.h +++ b/include/drm-uapi/nouveau_drm.h @@ -133,12 +133,63 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */ #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */ #define DRM_NOUVEAU_NVIF 0x07 +#define DRM_NOUVEAU_SVM_INIT 0x08 +#define DRM_NOUVEAU_SVM_BIND 0x09 #define DRM_NOUVEAU_GEM_NEW 0x40 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 #define DRM_NOUVEAU_GEM_INFO 0x44 +struct drm_nouveau_svm_init { + __u64 unmanaged_addr; + __u64 unmanaged_size; +}; + +struct drm_nouveau_svm_bind { + __u64 header; + __u64 va_start; + __u64 va_end; + __u64 npages; + __u64 stride; + __u64 result; + __u64 reserved0; + __u64 reserved1; +}; + +#define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0 +#define NOUVEAU_SVM_BIND_COMMAND_BITS 8 +#define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1) +#define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8 +#define NOUVEAU_SVM_BIND_PRIORITY_BITS 8 +#define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1) +#define NOUVEAU_SVM_BIND_TARGET_SHIFT 16 +#define NOUVEAU_SVM_BIND_TARGET_BITS 32 +#define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff + +/* + * Below is use to validate ioctl argument, userspace can also use it to make + * sure that no bit are set beyond known fields for a given kernel version. + */ +#define NOUVEAU_SVM_BIND_VALID_BITS 48 +#define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1) + + +/* + * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory. + * result: number of page successfuly migrate to the target memory. + */ +#define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0 + +/* + * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory. + */ +#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31) + + +#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init) +#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind) + #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) diff --git a/include/drm-uapi/panfrost_drm.h b/include/drm-uapi/panfrost_drm.h new file mode 100644 index 000000000000..a52e0283b90d --- /dev/null +++ b/include/drm-uapi/panfrost_drm.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2014-2018 Broadcom + * Copyright © 2019 Collabora ltd. + */ +#ifndef _PANFROST_DRM_H_ +#define _PANFROST_DRM_H_ + +#include "drm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define DRM_PANFROST_SUBMIT 0x00 +#define DRM_PANFROST_WAIT_BO 0x01 +#define DRM_PANFROST_CREATE_BO 0x02 +#define DRM_PANFROST_MMAP_BO 0x03 +#define DRM_PANFROST_GET_PARAM 0x04 +#define DRM_PANFROST_GET_BO_OFFSET 0x05 + +#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit) +#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo) +#define DRM_IOCTL_PANFROST_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_CREATE_BO, struct drm_panfrost_create_bo) +#define DRM_IOCTL_PANFROST_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MMAP_BO, struct drm_panfrost_mmap_bo) +#define DRM_IOCTL_PANFROST_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, struct drm_panfrost_get_param) +#define DRM_IOCTL_PANFROST_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset) + +#define PANFROST_JD_REQ_FS (1 << 0) +/** + * struct drm_panfrost_submit - ioctl argument for submitting commands to the 3D + * engine. + * + * This asks the kernel to have the GPU execute a render command list. + */ +struct drm_panfrost_submit { + + /** Address to GPU mapping of job descriptor */ + __u64 jc; + + /** An optional array of sync objects to wait on before starting this job. */ + __u64 in_syncs; + + /** Number of sync objects to wait on before starting this job. */ + __u32 in_sync_count; + + /** An optional sync object to place the completion fence in. */ + __u32 out_sync; + + /** Pointer to a u32 array of the BOs that are referenced by the job. */ + __u64 bo_handles; + + /** Number of BO handles passed in (size is that times 4). */ + __u32 bo_handle_count; + + /** A combination of PANFROST_JD_REQ_* */ + __u32 requirements; +}; + +/** + * struct drm_panfrost_wait_bo - ioctl argument for waiting for + * completion of the last DRM_PANFROST_SUBMIT on a BO. + * + * This is useful for cases where multiple processes might be + * rendering to a BO and you want to wait for all rendering to be + * completed. + */ +struct drm_panfrost_wait_bo { + __u32 handle; + __u32 pad; + __s64 timeout_ns; /* absolute */ +}; + +/** + * struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs. + * + * There are currently no values for the flags argument, but it may be + * used in a future extension. + */ +struct drm_panfrost_create_bo { + __u32 size; + __u32 flags; + /** Returned GEM handle for the BO. */ + __u32 handle; + /* Pad, must be zero-filled. */ + __u32 pad; + /** + * Returned offset for the BO in the GPU address space. This offset + * is private to the DRM fd and is valid for the lifetime of the GEM + * handle. + * + * This offset value will always be nonzero, since various HW + * units treat 0 specially. + */ + __u64 offset; +}; + +/** + * struct drm_panfrost_mmap_bo - ioctl argument for mapping Panfrost BOs. + * + * This doesn't actually perform an mmap. Instead, it returns the + * offset you need to use in an mmap on the DRM device node. This + * means that tools like valgrind end up knowing about the mapped + * memory. + * + * There are currently no values for the flags argument, but it may be + * used in a future extension. + */ +struct drm_panfrost_mmap_bo { + /** Handle for the object being mapped. */ + __u32 handle; + __u32 flags; + /** offset into the drm node to use for subsequent mmap call. */ + __u64 offset; +}; + +enum drm_panfrost_param { + DRM_PANFROST_PARAM_GPU_PROD_ID, +}; + +struct drm_panfrost_get_param { + __u32 param; + __u32 pad; + __u64 value; +}; + +/** + * Returns the offset for the BO in the GPU address space for this DRM fd. + * This is the same value returned by drm_panfrost_create_bo, if that was called + * from this DRM fd. + */ +struct drm_panfrost_get_bo_offset { + __u32 handle; + __u32 pad; + __u64 offset; +}; + +#if defined(__cplusplus) +} +#endif + +#endif /* _PANFROST_DRM_H_ */ diff --git a/include/drm-uapi/v3d_drm.h b/include/drm-uapi/v3d_drm.h index ea70669d2138..58fbe48c91e9 100644 --- a/include/drm-uapi/v3d_drm.h +++ b/include/drm-uapi/v3d_drm.h @@ -37,6 +37,7 @@ extern "C" { #define DRM_V3D_GET_PARAM 0x04 #define DRM_V3D_GET_BO_OFFSET 0x05 #define DRM_V3D_SUBMIT_TFU 0x06 +#define DRM_V3D_SUBMIT_CSD 0x07 #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl) #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo) @@ -45,6 +46,7 @@ extern "C" { #define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param) #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset) #define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu) +#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd) /** * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D @@ -190,6 +192,7 @@ enum drm_v3d_param { DRM_V3D_PARAM_V3D_CORE0_IDENT1, DRM_V3D_PARAM_V3D_CORE0_IDENT2, DRM_V3D_PARAM_SUPPORTS_TFU, + DRM_V3D_PARAM_SUPPORTS_CSD, }; struct drm_v3d_get_param { @@ -230,6 +233,31 @@ struct drm_v3d_submit_tfu { __u32 out_sync; }; +/* Submits a compute shader for dispatch. This job will block on any + * previous compute shaders submitted on this fd, and any other + * synchronization must be performed with in_sync/out_sync. + */ +struct drm_v3d_submit_csd { + __u32 cfg[7]; + __u32 coef[4]; + + /* Pointer to a u32 array of the BOs that are referenced by the job. + */ + __u64 bo_handles; + + /* Number of BO handles passed in (size is that times 4). */ + __u32 bo_handle_count; + + /* sync object to block on before running the CSD job. Each + * CSD job will execute in the order submitted to its FD. + * Synchronization against rendering/TFU jobs or CSD from + * other fds requires using sync objects. + */ + __u32 in_sync; + /* Sync object to signal when the CSD job is done. */ + __u32 out_sync; +}; + #if defined(__cplusplus) } #endif -- 2.19.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests 2019-05-01 11:42 [igt-dev] [PATCH i-g-t 0/2] Engine discovery tests Tvrtko Ursulin 2019-05-01 11:42 ` [igt-dev] [PATCH i-g-t 1/2] headers: bump Tvrtko Ursulin @ 2019-05-01 11:42 ` Tvrtko Ursulin 2019-05-01 11:52 ` [igt-dev] [Intel-gfx] " Chris Wilson 2019-05-01 12:02 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork 2019-05-02 2:51 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 3 siblings, 1 reply; 8+ messages in thread From: Tvrtko Ursulin @ 2019-05-01 11:42 UTC (permalink / raw) To: igt-dev; +Cc: Intel-gfx, Tvrtko Ursulin From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Test the new engine discovery query. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- tests/i915/i915_query.c | 247 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index 7d0c0e3a061c..ecbec3ae141d 100644 --- a/tests/i915/i915_query.c +++ b/tests/i915/i915_query.c @@ -483,6 +483,241 @@ test_query_topology_known_pci_ids(int fd, int devid) free(topo_info); } +static bool query_engine_info_supported(int fd) +{ + struct drm_i915_query_item item = { + .query_id = DRM_I915_QUERY_ENGINE_INFO, + }; + + return __i915_query_items(fd, &item, 1) == 0 && item.length > 0; +} + +static void engines_invalid(int fd) +{ + struct drm_i915_query_engine_info *engines; + struct drm_i915_query_item item; + unsigned int len; + + /* Flags is MBZ. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.flags = 1; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + /* Length not zero and not greater or equal required size. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = 1; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + /* Query correct length. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + i915_query_items(fd, &item, 1); + igt_assert(item.length >= 0); + len = item.length; + + engines = malloc(len); + igt_assert(engines); + + /* Ivalid pointer. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + + /* All fields in engines query are MBZ and only filled by the kernel. */ + + memset(engines, 0, len); + engines->num_engines = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[0] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[1] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[2] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + free(engines); + + igt_assert(len <= 4096); + engines = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, + -1, 0); + igt_assert(engines != MAP_FAILED); + + /* PROT_NONE is similar to unmapped area. */ + memset(engines, 0, len); + igt_assert_eq(mprotect(engines, len, PROT_NONE), 0); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + igt_assert_eq(mprotect(engines, len, PROT_WRITE), 0); + + /* Read-only so kernel cannot fill the data back. */ + memset(engines, 0, len); + igt_assert_eq(mprotect(engines, len, PROT_READ), 0); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + + munmap(engines, 4096); +} + +static bool +has_engine(struct drm_i915_query_engine_info *engines, + unsigned class, unsigned instance) +{ + unsigned int i; + + for (i = 0; i < engines->num_engines; i++) { + struct drm_i915_engine_info *engine = + (struct drm_i915_engine_info *)&engines->engines[i]; + + if (engine->engine.engine_class == class && + engine->engine.engine_instance == instance) + return true; + } + + return false; +} + +static void engines(int fd) +{ + struct drm_i915_query_engine_info *engines; + struct drm_i915_query_item item; + unsigned int len, i; + + engines = malloc(4096); + igt_assert(engines); + + /* Query required buffer length. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert(item.length >= 0); + igt_assert(item.length <= 4096); + len = item.length; + + /* Check length larger than required works and reports same length. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = 4096; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, len); + + /* Actual query. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, len); + + /* Every GPU has at least one engine. */ + igt_assert(engines->num_engines > 0); + + /* MBZ fields. */ + igt_assert_eq(engines->rsvd[0], 0); + igt_assert_eq(engines->rsvd[1], 0); + igt_assert_eq(engines->rsvd[2], 0); + + /* Check results match the legacy GET_PARAM (where we can). */ + for (i = 0; i < engines->num_engines; i++) { + struct drm_i915_engine_info *engine = + (struct drm_i915_engine_info *)&engines->engines[i]; + + igt_debug("%u: class=%u instance=%u flags=%llx capabilities=%llx\n", + i, + engine->engine.engine_class, + engine->engine.engine_instance, + engine->flags, + engine->capabilities); + + /* MBZ fields. */ + igt_assert_eq(engine->rsvd0, 0); + igt_assert_eq(engine->rsvd1[0], 0); + igt_assert_eq(engine->rsvd1[1], 0); + + switch (engine->engine.engine_class) { + case I915_ENGINE_CLASS_RENDER: + /* Will be tested later. */ + break; + case I915_ENGINE_CLASS_COPY: + igt_assert(gem_has_blt(fd)); + break; + case I915_ENGINE_CLASS_VIDEO: + switch (engine->engine.engine_instance) { + case 0: + igt_assert(gem_has_bsd(fd)); + break; + case 1: + igt_assert(gem_has_bsd2(fd)); + break; + } + break; + case I915_ENGINE_CLASS_VIDEO_ENHANCE: + igt_assert(gem_has_vebox(fd)); + break; + default: + igt_assert(0); + } + } + + /* Reverse check to the above - all GET_PARAM engines are present. */ + igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0)); + if (gem_has_blt(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0)); + if (gem_has_bsd(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0)); + if (gem_has_bsd2(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1)); + if (gem_has_vebox(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE, + 0)); + + free(engines); +} + igt_main { int fd = -1; @@ -530,6 +765,18 @@ igt_main test_query_topology_known_pci_ids(fd, devid); } + igt_subtest_group { + igt_fixture { + igt_require(query_engine_info_supported(fd)); + } + + igt_subtest("engine-info-invalid") + engines_invalid(fd); + + igt_subtest("engine-info") + engines(fd); + } + igt_fixture { close(fd); } -- 2.19.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests 2019-05-01 11:42 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests Tvrtko Ursulin @ 2019-05-01 11:52 ` Chris Wilson 2019-05-01 15:56 ` Tvrtko Ursulin 0 siblings, 1 reply; 8+ messages in thread From: Chris Wilson @ 2019-05-01 11:52 UTC (permalink / raw) To: Tvrtko Ursulin, igt-dev; +Cc: Intel-gfx Quoting Tvrtko Ursulin (2019-05-01 12:42:59) > + switch (engine->engine.engine_class) { > + case I915_ENGINE_CLASS_RENDER: > + /* Will be tested later. */ > + break; > + case I915_ENGINE_CLASS_COPY: > + igt_assert(gem_has_blt(fd)); > + break; > + case I915_ENGINE_CLASS_VIDEO: > + switch (engine->engine.engine_instance) { > + case 0: > + igt_assert(gem_has_bsd(fd)); > + break; > + case 1: > + igt_assert(gem_has_bsd2(fd)); > + break; Is that relationship a given? One could argue that gem_has_blt() means that I915_EXEC_BLT works, but without !gem_has_blt() we could still access CLASS_COPY:0 via ctx->engines[]. > + } > + break; > + case I915_ENGINE_CLASS_VIDEO_ENHANCE: > + igt_assert(gem_has_vebox(fd)); > + break; > + default: > + igt_assert(0); > + } > + } > + > + /* Reverse check to the above - all GET_PARAM engines are present. */ > + igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0)); > + if (gem_has_blt(fd)) > + igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0)); > + if (gem_has_bsd(fd)) > + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0)); > + if (gem_has_bsd2(fd)) > + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1)); > + if (gem_has_vebox(fd)) > + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE, > + 0)); Whereas this should always make sense, given the legacy interface and the modern interface, the modern interface should be a superset of the legacy. Just thinking aloud. -Chris _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests 2019-05-01 11:52 ` [igt-dev] [Intel-gfx] " Chris Wilson @ 2019-05-01 15:56 ` Tvrtko Ursulin 0 siblings, 0 replies; 8+ messages in thread From: Tvrtko Ursulin @ 2019-05-01 15:56 UTC (permalink / raw) To: Chris Wilson, igt-dev; +Cc: Intel-gfx On 01/05/2019 12:52, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2019-05-01 12:42:59) >> + switch (engine->engine.engine_class) { >> + case I915_ENGINE_CLASS_RENDER: >> + /* Will be tested later. */ >> + break; >> + case I915_ENGINE_CLASS_COPY: >> + igt_assert(gem_has_blt(fd)); >> + break; >> + case I915_ENGINE_CLASS_VIDEO: >> + switch (engine->engine.engine_instance) { >> + case 0: >> + igt_assert(gem_has_bsd(fd)); >> + break; >> + case 1: >> + igt_assert(gem_has_bsd2(fd)); >> + break; > > > Is that relationship a given? > > One could argue that gem_has_blt() means that I915_EXEC_BLT works, but > without !gem_has_blt() we could still access CLASS_COPY:0 via > ctx->engines[]. "without !gem_has_blt()".. hmmm what do you mean? If you mean gem_has_blt() is false but bcs:0 is still accessible via ctx->engines[] then how? >> + } >> + break; >> + case I915_ENGINE_CLASS_VIDEO_ENHANCE: >> + igt_assert(gem_has_vebox(fd)); >> + break; >> + default: >> + igt_assert(0); >> + } >> + } >> + >> + /* Reverse check to the above - all GET_PARAM engines are present. */ >> + igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0)); >> + if (gem_has_blt(fd)) >> + igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0)); >> + if (gem_has_bsd(fd)) >> + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0)); >> + if (gem_has_bsd2(fd)) >> + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1)); >> + if (gem_has_vebox(fd)) >> + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE, >> + 0)); > > Whereas this should always make sense, given the legacy interface and > the modern interface, the modern interface should be a superset of the > legacy. > > Just thinking aloud. Sure, no harm in looking at it again. The test was written long time ago. Regards, Tvrtko _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Engine discovery tests 2019-05-01 11:42 [igt-dev] [PATCH i-g-t 0/2] Engine discovery tests Tvrtko Ursulin 2019-05-01 11:42 ` [igt-dev] [PATCH i-g-t 1/2] headers: bump Tvrtko Ursulin 2019-05-01 11:42 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests Tvrtko Ursulin @ 2019-05-01 12:02 ` Patchwork 2019-05-02 2:51 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 3 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2019-05-01 12:02 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: igt-dev == Series Details == Series: Engine discovery tests URL : https://patchwork.freedesktop.org/series/60152/ State : success == Summary == CI Bug Log - changes from CI_DRM_6021 -> IGTPW_2938 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60152/revisions/1/mbox/ Known issues ------------ Here are the changes found in IGTPW_2938 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@i915_selftest@live_hangcheck: - fi-icl-y: [INCOMPLETE][1] ([fdo#107713] / [fdo#108569]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-icl-y/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/fi-icl-y/igt@i915_selftest@live_hangcheck.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html #### Warnings #### * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][5] ([fdo#109271]) -> [INCOMPLETE][6] ([fdo#107807]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (52 -> 46) ------------------------------ Additional (1): fi-pnv-d510 Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * IGT: IGT_4971 -> IGTPW_2938 CI_DRM_6021: 850aa4220e8bf7609b03bf89bce146305704bec6 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_2938: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/ IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Testlist changes == +igt@i915_query@engine-info +igt@i915_query@engine-info-invalid == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/ _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Engine discovery tests 2019-05-01 11:42 [igt-dev] [PATCH i-g-t 0/2] Engine discovery tests Tvrtko Ursulin ` (2 preceding siblings ...) 2019-05-01 12:02 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork @ 2019-05-02 2:51 ` Patchwork 3 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2019-05-02 2:51 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: igt-dev == Series Details == Series: Engine discovery tests URL : https://patchwork.freedesktop.org/series/60152/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6021_full -> IGTPW_2938_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_2938_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_2938_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/60152/revisions/1/mbox/ Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_2938_full: ### IGT changes ### #### Possible regressions #### * {igt@i915_query@engine-info} (NEW): - shard-iclb: NOTRUN -> [SKIP][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb8/igt@i915_query@engine-info.html * igt@kms_plane_cursor@pipe-a-viewport-size-128: - shard-iclb: NOTRUN -> [FAIL][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb6/igt@kms_plane_cursor@pipe-a-viewport-size-128.html New tests --------- New tests have been introduced between CI_DRM_6021_full and IGTPW_2938_full: ### New IGT tests (2) ### * igt@i915_query@engine-info: - Statuses : 6 skip(s) - Exec time: [0.0] s * igt@i915_query@engine-info-invalid: - Statuses : 6 skip(s) - Exec time: [0.0] s Known issues ------------ Here are the changes found in IGTPW_2938_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_fence_thrash@bo-write-verify-threaded-x: - shard-glk: [PASS][3] -> [INCOMPLETE][4] ([fdo#103359] / [k.org#198133]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-glk1/igt@gem_fence_thrash@bo-write-verify-threaded-x.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-glk2/igt@gem_fence_thrash@bo-write-verify-threaded-x.html * igt@gem_pwrite@big-cpu-fbr: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-iclb1/igt@gem_pwrite@big-cpu-fbr.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb5/igt@gem_pwrite@big-cpu-fbr.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([fdo#108686]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-glk7/igt@gem_tiled_swapping@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-glk9/igt@gem_tiled_swapping@non-threaded.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-apl8/igt@i915_suspend@debugfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-apl6/igt@i915_suspend@debugfs-reader.html * igt@kms_cursor_crc@cursor-128x42-onscreen: - shard-apl: [PASS][11] -> [FAIL][12] ([fdo#103232]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-apl3/igt@kms_cursor_crc@cursor-128x42-onscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-apl2/igt@kms_cursor_crc@cursor-128x42-onscreen.html - shard-kbl: [PASS][13] -> [FAIL][14] ([fdo#103232]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-kbl1/igt@kms_cursor_crc@cursor-128x42-onscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-kbl3/igt@kms_cursor_crc@cursor-128x42-onscreen.html * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-kbl2/igt@kms_cursor_crc@cursor-256x256-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-kbl1/igt@kms_cursor_crc@cursor-256x256-suspend.html * igt@kms_flip@2x-flip-vs-suspend: - shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([fdo#103540]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-hsw4/igt@kms_flip@2x-flip-vs-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-hsw1/igt@kms_flip@2x-flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-stridechange.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-stridechange.html * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713] / [fdo#110036 ]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-iclb8/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb1/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103665]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: - shard-glk: [PASS][25] -> [SKIP][26] ([fdo#109271] / [fdo#109278]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-glk9/igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-glk7/igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109642]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-iclb2/igt@kms_psr2_su@frontbuffer.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb6/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html * igt@perf_pmu@busy-accuracy-98-vecs0: - shard-apl: [PASS][31] -> [INCOMPLETE][32] ([fdo#103927]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-apl4/igt@perf_pmu@busy-accuracy-98-vecs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-apl4/igt@perf_pmu@busy-accuracy-98-vecs0.html #### Possible fixes #### * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34] +5 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html * igt@gem_ctx_switch@basic-all-light: - shard-iclb: [INCOMPLETE][35] ([fdo#107713] / [fdo#109100]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-iclb1/igt@gem_ctx_switch@basic-all-light.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb3/igt@gem_ctx_switch@basic-all-light.html * igt@gem_exec_blt@dumb-buf-min: - shard-hsw: [INCOMPLETE][37] ([fdo#103540]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-hsw6/igt@gem_exec_blt@dumb-buf-min.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-hsw1/igt@gem_exec_blt@dumb-buf-min.html * igt@gem_softpin@noreloc-s3: - shard-kbl: [DMESG-WARN][39] ([fdo#108566]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-kbl1/igt@gem_softpin@noreloc-s3.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-kbl3/igt@gem_softpin@noreloc-s3.html * igt@kms_flip@2x-flip-vs-suspend: - shard-glk: [INCOMPLETE][41] ([fdo#103359] / [k.org#198133]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-glk9/igt@kms_flip@2x-flip-vs-suspend.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-glk4/igt@kms_flip@2x-flip-vs-suspend.html * igt@kms_flip@dpms-off-confusion-interruptible: - shard-iclb: [INCOMPLETE][43] ([fdo#107713]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-iclb1/igt@kms_flip@dpms-off-confusion-interruptible.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb4/igt@kms_flip@dpms-off-confusion-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-iclb: [FAIL][45] ([fdo#103167]) -> [PASS][46] +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping: - shard-glk: [SKIP][47] ([fdo#109271]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-glk8/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-glk9/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [FAIL][49] ([fdo#103166]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html * igt@kms_psr@no_drrs: - shard-iclb: [FAIL][51] ([fdo#108341]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/shard-iclb1/igt@kms_psr@no_drrs.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/shard-iclb8/igt@kms_psr@no_drrs.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110036 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110036 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (10 -> 6) ------------------------------ Missing (4): pig-skl-6260u shard-skl pig-hsw-4770r pig-glk-j5005 Build changes ------------- * IGT: IGT_4971 -> IGTPW_2938 * Piglit: piglit_4509 -> None CI_DRM_6021: 850aa4220e8bf7609b03bf89bce146305704bec6 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_2938: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/ IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2938/ _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] drm-uapi: Import i915_drm.h upto c5d3e39caa456b1e061644b739131f2b54c84c08
@ 2019-05-22 13:32 Tvrtko Ursulin
2019-05-22 13:32 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests Tvrtko Ursulin
0 siblings, 1 reply; 8+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:32 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx, Tvrtko Ursulin
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
commit c5d3e39caa456b1e061644b739131f2b54c84c08
Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Wed May 22 10:00:54 2019 +0100
drm/i915: Engine discovery query
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
include/drm-uapi/i915_drm.h | 42 +++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index de7be1bc6b04..761517f15368 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1982,6 +1982,7 @@ struct drm_i915_perf_oa_config {
struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
+#define DRM_I915_QUERY_ENGINE_INFO 2
/* Must be kept compact -- no holes and well documented */
/*
@@ -2080,6 +2081,47 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+ /** Engine class and instance. */
+ struct i915_engine_class_instance engine;
+
+ /** Reserved field. */
+ __u32 rsvd0;
+
+ /** Engine flags. */
+ __u64 flags;
+
+ /** Capabilities of this engine. */
+ __u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
+
+ /** Reserved fields. */
+ __u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+ /** Number of struct drm_i915_engine_info structs following. */
+ __u32 num_engines;
+
+ /** MBZ */
+ __u32 rsvd[3];
+
+ /** Marker for drm_i915_engine_info structures. */
+ struct drm_i915_engine_info engines[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.20.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [igt-dev] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests 2019-05-22 13:32 [igt-dev] [PATCH i-g-t 1/2] drm-uapi: Import i915_drm.h upto c5d3e39caa456b1e061644b739131f2b54c84c08 Tvrtko Ursulin @ 2019-05-22 13:32 ` Tvrtko Ursulin 0 siblings, 0 replies; 8+ messages in thread From: Tvrtko Ursulin @ 2019-05-22 13:32 UTC (permalink / raw) To: igt-dev; +Cc: Intel-gfx, Tvrtko Ursulin From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Test the new engine discovery query. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Andi Shyti <andi.shyti@intel.com> --- tests/i915/i915_query.c | 247 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index 7d0c0e3a061c..ecbec3ae141d 100644 --- a/tests/i915/i915_query.c +++ b/tests/i915/i915_query.c @@ -483,6 +483,241 @@ test_query_topology_known_pci_ids(int fd, int devid) free(topo_info); } +static bool query_engine_info_supported(int fd) +{ + struct drm_i915_query_item item = { + .query_id = DRM_I915_QUERY_ENGINE_INFO, + }; + + return __i915_query_items(fd, &item, 1) == 0 && item.length > 0; +} + +static void engines_invalid(int fd) +{ + struct drm_i915_query_engine_info *engines; + struct drm_i915_query_item item; + unsigned int len; + + /* Flags is MBZ. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.flags = 1; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + /* Length not zero and not greater or equal required size. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = 1; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + /* Query correct length. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + i915_query_items(fd, &item, 1); + igt_assert(item.length >= 0); + len = item.length; + + engines = malloc(len); + igt_assert(engines); + + /* Ivalid pointer. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + + /* All fields in engines query are MBZ and only filled by the kernel. */ + + memset(engines, 0, len); + engines->num_engines = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[0] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[1] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[2] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + free(engines); + + igt_assert(len <= 4096); + engines = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, + -1, 0); + igt_assert(engines != MAP_FAILED); + + /* PROT_NONE is similar to unmapped area. */ + memset(engines, 0, len); + igt_assert_eq(mprotect(engines, len, PROT_NONE), 0); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + igt_assert_eq(mprotect(engines, len, PROT_WRITE), 0); + + /* Read-only so kernel cannot fill the data back. */ + memset(engines, 0, len); + igt_assert_eq(mprotect(engines, len, PROT_READ), 0); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + + munmap(engines, 4096); +} + +static bool +has_engine(struct drm_i915_query_engine_info *engines, + unsigned class, unsigned instance) +{ + unsigned int i; + + for (i = 0; i < engines->num_engines; i++) { + struct drm_i915_engine_info *engine = + (struct drm_i915_engine_info *)&engines->engines[i]; + + if (engine->engine.engine_class == class && + engine->engine.engine_instance == instance) + return true; + } + + return false; +} + +static void engines(int fd) +{ + struct drm_i915_query_engine_info *engines; + struct drm_i915_query_item item; + unsigned int len, i; + + engines = malloc(4096); + igt_assert(engines); + + /* Query required buffer length. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert(item.length >= 0); + igt_assert(item.length <= 4096); + len = item.length; + + /* Check length larger than required works and reports same length. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = 4096; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, len); + + /* Actual query. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, len); + + /* Every GPU has at least one engine. */ + igt_assert(engines->num_engines > 0); + + /* MBZ fields. */ + igt_assert_eq(engines->rsvd[0], 0); + igt_assert_eq(engines->rsvd[1], 0); + igt_assert_eq(engines->rsvd[2], 0); + + /* Check results match the legacy GET_PARAM (where we can). */ + for (i = 0; i < engines->num_engines; i++) { + struct drm_i915_engine_info *engine = + (struct drm_i915_engine_info *)&engines->engines[i]; + + igt_debug("%u: class=%u instance=%u flags=%llx capabilities=%llx\n", + i, + engine->engine.engine_class, + engine->engine.engine_instance, + engine->flags, + engine->capabilities); + + /* MBZ fields. */ + igt_assert_eq(engine->rsvd0, 0); + igt_assert_eq(engine->rsvd1[0], 0); + igt_assert_eq(engine->rsvd1[1], 0); + + switch (engine->engine.engine_class) { + case I915_ENGINE_CLASS_RENDER: + /* Will be tested later. */ + break; + case I915_ENGINE_CLASS_COPY: + igt_assert(gem_has_blt(fd)); + break; + case I915_ENGINE_CLASS_VIDEO: + switch (engine->engine.engine_instance) { + case 0: + igt_assert(gem_has_bsd(fd)); + break; + case 1: + igt_assert(gem_has_bsd2(fd)); + break; + } + break; + case I915_ENGINE_CLASS_VIDEO_ENHANCE: + igt_assert(gem_has_vebox(fd)); + break; + default: + igt_assert(0); + } + } + + /* Reverse check to the above - all GET_PARAM engines are present. */ + igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0)); + if (gem_has_blt(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0)); + if (gem_has_bsd(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0)); + if (gem_has_bsd2(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1)); + if (gem_has_vebox(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE, + 0)); + + free(engines); +} + igt_main { int fd = -1; @@ -530,6 +765,18 @@ igt_main test_query_topology_known_pci_ids(fd, devid); } + igt_subtest_group { + igt_fixture { + igt_require(query_engine_info_supported(fd)); + } + + igt_subtest("engine-info-invalid") + engines_invalid(fd); + + igt_subtest("engine-info") + engines(fd); + } + igt_fixture { close(fd); } -- 2.20.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-05-22 13:32 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-05-01 11:42 [igt-dev] [PATCH i-g-t 0/2] Engine discovery tests Tvrtko Ursulin 2019-05-01 11:42 ` [igt-dev] [PATCH i-g-t 1/2] headers: bump Tvrtko Ursulin 2019-05-01 11:42 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests Tvrtko Ursulin 2019-05-01 11:52 ` [igt-dev] [Intel-gfx] " Chris Wilson 2019-05-01 15:56 ` Tvrtko Ursulin 2019-05-01 12:02 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork 2019-05-02 2:51 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2019-05-22 13:32 [igt-dev] [PATCH i-g-t 1/2] drm-uapi: Import i915_drm.h upto c5d3e39caa456b1e061644b739131f2b54c84c08 Tvrtko Ursulin 2019-05-22 13:32 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests Tvrtko Ursulin
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