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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: igt-dev@lists.freedesktop.org
Cc: Intel-gfx@lists.freedesktop.org,
	Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Subject: [igt-dev] [PATCH i-g-t 23/27] gem_wsim: Consolidate engine assignments into helpers
Date: Mon, 20 May 2019 15:47:35 +0100	[thread overview]
Message-ID: <20190520144739.13111-24-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20190520144739.13111-1-tvrtko.ursulin@linux.intel.com>

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This will allow applying the discovered engine configuration from a single
place.

v2:
 * Consolidate enum to ci conversion.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 benchmarks/gem_wsim.c | 163 ++++++++++++++++++++++++------------------
 1 file changed, 94 insertions(+), 69 deletions(-)

diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index fe70e7719d88..02c3e9d655d8 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -365,6 +365,66 @@ static int str_to_engine(const char *str)
 	return -1;
 }
 
+static unsigned int num_engines_in_class(enum intel_engine_id class)
+{
+	igt_assert(class == VCS);
+
+	return 2;
+}
+
+static void
+fill_engines_class(struct i915_engine_class_instance *ci,
+		   enum intel_engine_id class)
+{
+	igt_assert(class == VCS);
+
+	ci[0].engine_class = I915_ENGINE_CLASS_VIDEO;
+	ci[0].engine_instance = 0;
+
+	ci[1].engine_class = I915_ENGINE_CLASS_VIDEO;
+	ci[1].engine_instance = 1;
+}
+
+static void
+fill_engines_id_class(enum intel_engine_id *list,
+		      enum intel_engine_id class)
+{
+	igt_assert(class == VCS);
+
+	list[0] = VCS1;
+	list[1] = VCS2;
+}
+
+static struct i915_engine_class_instance
+get_engine(enum intel_engine_id engine)
+{
+	struct i915_engine_class_instance ci;
+
+	switch (engine) {
+	case RCS:
+		ci.engine_class = I915_ENGINE_CLASS_RENDER;
+		ci.engine_instance = 0;
+		break;
+	case BCS:
+		ci.engine_class = I915_ENGINE_CLASS_COPY;
+		ci.engine_instance = 0;
+		break;
+	case VCS1:
+	case VCS2:
+		ci.engine_class = I915_ENGINE_CLASS_VIDEO;
+		ci.engine_instance = engine - VCS1;
+		break;
+	case VECS:
+		ci.engine_class = I915_ENGINE_CLASS_VIDEO_ENHANCE;
+		ci.engine_instance = 0;
+		break;
+	default:
+		igt_assert(0);
+	};
+
+	return ci;
+}
+
 static int parse_engine_map(struct w_step *step, const char *_str)
 {
 	char *token, *tctx = NULL, *tstart = (char *)_str;
@@ -386,18 +446,16 @@ static int parse_engine_map(struct w_step *step, const char *_str)
 		    engine != RCS)
 			return -1; /* TODO */
 
-		add = engine == VCS ? 2 : 1;
+		add = engine == VCS ? num_engines_in_class(VCS) : 1;
 		step->engine_map_count += add;
 		step->engine_map = realloc(step->engine_map,
 					   step->engine_map_count *
 					   sizeof(step->engine_map[0]));
 
-		if (engine != VCS) {
-			step->engine_map[step->engine_map_count - 1] = engine;
-		} else {
-			step->engine_map[step->engine_map_count - 2] = VCS1;
-			step->engine_map[step->engine_map_count - 1] = VCS2;
-		}
+		if (engine != VCS)
+			step->engine_map[step->engine_map_count - add] = engine;
+		else
+			fill_engines_id_class(&step->engine_map[step->engine_map_count - add], VCS);
 	}
 
 	return 0;
@@ -1148,20 +1206,11 @@ static unsigned int
 find_engine(struct i915_engine_class_instance *ci, unsigned int count,
 	    enum intel_engine_id engine)
 {
-	static struct i915_engine_class_instance map[] = {
-		[RCS] = { I915_ENGINE_CLASS_RENDER, 0 },
-		[BCS] = { I915_ENGINE_CLASS_COPY, 0 },
-		[VCS1] = { I915_ENGINE_CLASS_VIDEO, 0 },
-		[VCS2] = { I915_ENGINE_CLASS_VIDEO, 1 },
-		[VECS] = { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0 },
-	};
+	struct i915_engine_class_instance e = get_engine(engine);
 	unsigned int i;
 
-	igt_assert(engine < ARRAY_SIZE(map));
-	igt_assert(engine == RCS || map[engine].engine_class);
-
 	for (i = 0; i < count; i++, ci++) {
-		if (!memcmp(&map[engine], ci, sizeof(*ci)))
+		if (!memcmp(&e, ci, sizeof(*ci)))
 			return i;
 	}
 
@@ -1465,19 +1514,9 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
 				load_balance.num_siblings =
 					ctx->engine_map_count;
 
-				for (j = 0; j < ctx->engine_map_count; j++) {
-					if (ctx->engine_map[j] == RCS) {
-						load_balance.engines[j].engine_class =
-							I915_ENGINE_CLASS_RENDER;
-						load_balance.engines[j].engine_instance =
-							0; /* FIXME */
-					} else {
-						load_balance.engines[j].engine_class =
-							I915_ENGINE_CLASS_VIDEO; /* FIXME */
-						load_balance.engines[j].engine_instance =
-							ctx->engine_map[j] - VCS1; /* FIXME */
-					}
-				}
+				for (j = 0; j < ctx->engine_map_count; j++)
+					load_balance.engines[j] =
+						get_engine(ctx->engine_map[j]);
 			} else {
 				set_engines.extensions = 0;
 			}
@@ -1488,18 +1527,9 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
 			set_engines.engines[0].engine_instance =
 				I915_ENGINE_CLASS_INVALID_NONE;
 
-			for (j = 1; j <= ctx->engine_map_count; j++) {
-				if (ctx->engine_map[j - 1] == RCS) {
-					set_engines.engines[j].engine_class =
-						I915_ENGINE_CLASS_RENDER;
-					set_engines.engines[j].engine_instance = 0; /* FIXME */
-				} else {
-					set_engines.engines[j].engine_class =
-						I915_ENGINE_CLASS_VIDEO; /* FIXME */
-					set_engines.engines[j].engine_instance =
-						ctx->engine_map[j - 1] - VCS1; /* FIXME */
-				}
-			}
+			for (j = 1; j <= ctx->engine_map_count; j++)
+				set_engines.engines[j] =
+					get_engine(ctx->engine_map[j - 1]);
 
 			for (j = 0; j < ctx->bond_count; j++) {
 				unsigned long mask = ctx->bonds[j].mask;
@@ -1522,10 +1552,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
 
 				p->base.name = I915_CONTEXT_ENGINES_EXT_BOND;
 				p->virtual_index = 0;
-				p->master.engine_class =
-					I915_ENGINE_CLASS_VIDEO;
-				p->master.engine_instance =
-					ctx->bonds[j].master - VCS1;
+				p->master = get_engine(ctx->bonds[j].master);
 
 				for (b = 0, e = 0; mask; e++, mask >>= 1) {
 					unsigned int idx;
@@ -1543,28 +1570,11 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
 
 			gem_context_set_param(fd, &param);
 		} else if (ctx->wants_balance) {
-			I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(load_balance, 2) = {
-				.base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
-				.num_siblings = 2,
-				.engines = {
-					{ .engine_class = I915_ENGINE_CLASS_VIDEO,
-					  .engine_instance = 0 },
-					{ .engine_class = I915_ENGINE_CLASS_VIDEO,
-					  .engine_instance = 1 },
-				},
-			};
-			I915_DEFINE_CONTEXT_PARAM_ENGINES(set_engines, 3) = {
-				.extensions = to_user_pointer(&load_balance),
-				.engines = {
-					{ .engine_class = I915_ENGINE_CLASS_INVALID,
-					  .engine_instance = I915_ENGINE_CLASS_INVALID_NONE },
-					{ .engine_class = I915_ENGINE_CLASS_VIDEO,
-					  .engine_instance = 0 },
-					{ .engine_class = I915_ENGINE_CLASS_VIDEO,
-					  .engine_instance = 1 },
-				},
-			};
-
+			const unsigned int count = num_engines_in_class(VCS);
+			I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(load_balance,
+								 count);
+			I915_DEFINE_CONTEXT_PARAM_ENGINES(set_engines,
+							  count + 1);
 			struct drm_i915_gem_context_param param = {
 				.ctx_id = ctx_id,
 				.param = I915_CONTEXT_PARAM_ENGINES,
@@ -1572,6 +1582,21 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
 				.value = to_user_pointer(&set_engines),
 			};
 
+			set_engines.extensions = to_user_pointer(&load_balance);
+
+			set_engines.engines[0].engine_class =
+				I915_ENGINE_CLASS_INVALID;
+			set_engines.engines[0].engine_instance =
+				I915_ENGINE_CLASS_INVALID_NONE;
+			fill_engines_class(&set_engines.engines[1], VCS);
+
+			memset(&load_balance, 0, sizeof(load_balance));
+			load_balance.base.name =
+				I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
+			load_balance.num_siblings = count;
+
+			fill_engines_class(&load_balance.engines[0], VCS);
+
 			gem_context_set_param(fd, &param);
 		}
 
-- 
2.20.1

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  parent reply	other threads:[~2019-05-20 14:47 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-20 14:47 [igt-dev] [PATCH i-g-t 00/27] Media scalability tooling Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 01/27] scripts/trace.pl: Fix after intel_engine_notify removal Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 02/27] trace.pl: Ignore signaling on non i915 fences Tvrtko Ursulin
2019-05-21  7:57   ` Chris Wilson
2019-05-21 13:22     ` Tvrtko Ursulin
2019-05-21 15:29       ` Chris Wilson
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 03/27] headers: bump Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 04/27] trace.pl: Virtual engine support Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 05/27] trace.pl: Virtual engine preemption support Tvrtko Ursulin
2019-05-20 14:47 ` [Intel-gfx] [PATCH i-g-t 06/27] wsim/media-bench: i915 balancing Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 07/27] gem_wsim: Use IGT uapi headers Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 08/27] gem_wsim: Factor out common error handling Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 09/27] gem_wsim: More wsim_err Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 10/27] gem_wsim: Submit fence support Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 11/27] gem_wsim: Extract str to engine lookup Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 12/27] gem_wsim: Engine map support Tvrtko Ursulin
2019-05-21  8:14   ` Chris Wilson
2019-05-21  8:29     ` Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 13/27] gem_wsim: Save some lines by changing to implicit NULL checking Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 14/27] gem_wsim: Compact int command parsing with a macro Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 15/27] gem_wsim: Engine map load balance command Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 16/27] gem_wsim: Engine bond command Tvrtko Ursulin
2019-05-20 14:47 ` [Intel-gfx] [PATCH i-g-t 17/27] gem_wsim: Some more example workloads Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 18/27] gem_wsim: Infinite batch support Tvrtko Ursulin
2019-05-20 14:47 ` [Intel-gfx] [PATCH i-g-t 19/27] gem_wsim: Command line switch for specifying low slice count workloads Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 20/27] gem_wsim: Per context SSEU control Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 21/27] gem_wsim: Allow RCS virtual engine with " Tvrtko Ursulin
2019-05-20 14:47 ` [Intel-gfx] [PATCH i-g-t 22/27] tests/i915_query: Engine discovery tests Tvrtko Ursulin
2019-05-22  8:23   ` [igt-dev] " Andi Shyti
2019-05-20 14:47 ` Tvrtko Ursulin [this message]
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 24/27] gem_wsim: Discover engines Tvrtko Ursulin
2019-05-21 13:54   ` Andi Shyti
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 25/27] gem_wsim: Support Icelake parts Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 26/27] gem_wsim: Fix prng usage Tvrtko Ursulin
2019-05-20 14:47 ` [igt-dev] [PATCH i-g-t 27/27] gem_wsim: Allow random seed control Tvrtko Ursulin
2019-05-21  9:22 ` [igt-dev] ✓ Fi.CI.BAT: success for Media scalability tooling (rev6) Patchwork
2019-05-21 13:10 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork

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