[igt-dev] [PATCH i-g-t v7 0/5] Enabling PC8+ residency for all GEN9+ platforms v7

[igt-dev] [PATCH i-g-t v7 0/5] Enabling PC8+ residency for all GEN9+ platforms v7

[Anshuman Gupta]

This patch series enable PC8+ residency test, earlier these tests
were only enabled for Haswell and Broadwell.

Addressed minor review comment provided by Ram on revision 5.

Added a debug test to validate pc8 with all planes and all pipes
enabled in order confirm platform can enter to pc8 with all screen on.

Earlier pc8-residency sub-test were failing on most of Gen 9
platforms, so trying pc8-residency sub test after setting up powertop
and dumping the pmc sysfs attributes.

Anshuman Gupta (5):
  tests/i915/i915_pm_rpm: Enable PC8+ residency test for all Gen9+
  tests/i915/i915_pm_rpm: modeset-pc8-residency-stress
  DEBUG: invoke powertop and pmc ltr_ignore when pc8 tests fails.
  DEBUG:sub-test to check pc8 after enabling all planes on all pipes.
  DO_NOT_MERGE: adding i915_pm_rpm pc8 subtest to fast feedback list.

 tests/i915/i915_pm_rpm.c              | 430 +++++++++++++++++++++++++-
 tests/intel-ci/fast-feedback.testlist |   4 +
 2 files changed, 424 insertions(+), 10 deletions(-)

-- 
2.21.0

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[igt-dev] [PATCH i-g-t v7 1/5] tests/i915/i915_pm_rpm: Enable PC8+ residency test for all Gen9+

[Anshuman Gupta]

Enabled has_pc8 global for ICL and Gen9+.
Modified PC8+ residency sub-test with all screen enabled.

v2:Fixed the issue of skipped test on HSW.
   Improved the code comment for MSR_PKG_CST_CONFIG_CONTROL mask and PC8
   bits, it holds good for SKL/ICL and Goldmont microarchitecture.
   Code readability improvement.

v3:Removed the connected_screens global. [Ram]
   Removed pc8_needs_screen_off from mode_set_data structure,
   made it global, aligning to has_pc8 and has_runtime_pm global. [Ram]
   Reuse connector local variable in init_modeset_params_for_all_screen(). [Ram]
   Addressed Coding guide lines comments. [Ram]

v4:Improved the code comment for MSR_PKG_CST_CONFIG_CONTROL mask and PC8 bits. [Ram]
   Introduced set_screens_mode_params() function to fix warning of line exceeding
   80 char, fixed this warning at other places too. [Ram]
   Using ms_data modset_data global structure. [Ram]
   Introduced macros for timeout values, given to PC8+ residency check function. [Ram]

v5:Addressed minor review comment by changing macro name and by removing
   irrelevant change with respect to this series. [Ram]

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/i915/i915_pm_rpm.c | 88 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 81 insertions(+), 7 deletions(-)

diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index a2c9d0ed..5a585544 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -52,7 +52,11 @@
 #include "igt_device.h"
 
 #define MSR_PKG_CST_CONFIG_CONTROL	0xE2
-/* HSW/BDW: */
+/*
+ * Below PKG CST limit mask and PC8 bits are meant for
+ * HSW,BDW SKL,ICL and Goldmont Microarch.
+ * Refer IA S/W developers manual vol3c part3 chapter:35
+ */
 #define  PKG_CST_LIMIT_MASK		0xF
 #define  PKG_CST_LIMIT_C8		0x6
 
@@ -64,6 +68,9 @@
 #define MAX_ENCODERS	32
 #define MAX_CRTCS	16
 
+#define IGT_TIME_OUT_SEC_5   5
+#define IGT_TIME_OUT_SEC_10 10
+
 enum pc8_status {
 	PC8_ENABLED,
 	PC8_DISABLED
@@ -90,7 +97,7 @@ enum plane_type {
 
 int drm_fd, msr_fd, pc8_status_fd;
 int debugfs;
-bool has_runtime_pm, has_pc8;
+bool has_runtime_pm, has_pc8, pc8_needs_screen_off;
 struct mode_set_data ms_data;
 
 /* Stuff used when creating FBs and mode setting. */
@@ -121,9 +128,25 @@ struct modeset_params {
 struct modeset_params lpsp_mode_params;
 struct modeset_params non_lpsp_mode_params;
 struct modeset_params *default_mode_params;
+struct modeset_params *screens_mode_params[MAX_CONNECTORS];
 
 static int8_t *pm_data = NULL;
 
+static inline void set_screens_mode_param(drmModeConnectorPtr connector,
+					  struct modeset_params *params)
+{
+	drmModeModeInfoPtr mode = NULL;
+
+	mode = &connector->modes[0];
+	igt_create_pattern_fb(drm_fd, mode->hdisplay, mode->vdisplay,
+			      DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE,
+			      &params->fb);
+	params->crtc_id = kmstest_find_crtc_for_connector(drm_fd, ms_data.res,
+							  connector, 0);
+	params->connector_id = connector->connector_id;
+	params->mode = mode;
+}
+
 static int modprobe(const char *driver)
 {
 	return igt_kmod_load(driver, NULL);
@@ -297,6 +320,28 @@ static bool init_modeset_params_for_type(struct mode_set_data *data,
 	return true;
 }
 
+static void init_modeset_params_for_all_screen(void)
+{
+	drmModeConnectorPtr connector = NULL;
+	int screen = 0;
+
+	if (!ms_data.res)
+		return;
+
+	for (int i = 0; i < ms_data.res->count_connectors; i++) {
+		connector = ms_data.connectors[i];
+
+		if (connector->connection == DRM_MODE_CONNECTED
+		    && connector->count_modes) {
+			screens_mode_params[screen] =
+				malloc(sizeof(struct modeset_params));
+			set_screens_mode_param(connector,
+					       screens_mode_params[screen]);
+			screen++;
+		}
+	}
+}
+
 static void init_modeset_cached_params(struct mode_set_data *data)
 {
 	bool lpsp, non_lpsp;
@@ -305,6 +350,7 @@ static void init_modeset_cached_params(struct mode_set_data *data)
 					    SCREEN_TYPE_LPSP);
 	non_lpsp = init_modeset_params_for_type(data, &non_lpsp_mode_params,
 						SCREEN_TYPE_NON_LPSP);
+	init_modeset_params_for_all_screen();
 
 	if (lpsp)
 		default_mode_params = &lpsp_mode_params;
@@ -353,6 +399,22 @@ static bool enable_one_screen_with_type(struct mode_set_data *data,
 	return set_mode_for_params(params);
 }
 
+static void enable_all_screens(void)
+{
+	struct modeset_params *params = NULL;
+
+	/* SKIP if there are no connected screens. */
+	igt_require(screens_mode_params[0]);
+
+	for (int i = 0; i < MAX_CONNECTORS ; i++) {
+		params = screens_mode_params[i];
+		if (params)
+			set_mode_for_params(params);
+		else
+			break;
+	}
+}
+
 static void enable_one_screen(struct mode_set_data *data)
 {
 	/* SKIP if there are no connected screens. */
@@ -685,8 +747,12 @@ static void setup_pc8(void)
 {
 	has_pc8 = false;
 
-	/* Only Haswell supports the PC8 feature. */
-	if (!IS_HASWELL(ms_data.devid) && !IS_BROADWELL(ms_data.devid))
+	if (IS_HASWELL(ms_data.devid) || IS_BROADWELL(ms_data.devid))
+		pc8_needs_screen_off = true;
+	else if (AT_LEAST_GEN(ms_data.devid, 9))
+		pc8_needs_screen_off = false;
+	/* Only Haswell supports the PC8 feature on lesser than GEN9. */
+	else
 		return;
 
 	/* Make sure our Kernel supports MSR and the module is loaded. */
@@ -808,9 +874,17 @@ static void pc8_residency_subtest(void)
 		     "configuration.\n");
 
 	/* Make sure PC8+ residencies stop! */
-	enable_one_screen(&ms_data);
-	igt_assert_f(!pc8_plus_residency_changed(10),
-		     "PC8+ residency didn't stop with screen enabled.\n");
+	if (pc8_needs_screen_off) {
+		enable_one_screen(&ms_data);
+		igt_assert_f(!pc8_plus_residency_changed(IGT_TIME_OUT_SEC_10),
+			     "PC8+ residency didn't stop with "
+			     "screen enabled.\n");
+	} else {
+		enable_all_screens();
+		igt_assert_f(pc8_plus_residency_changed(IGT_TIME_OUT_SEC_10),
+			     "Machine is not reaching PC8+ states "
+			     "with all screen enabled.\n");
+	}
 }
 
 static void modeset_subtest(enum screen_type type, int rounds, int wait_flags)
-- 
2.21.0

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[igt-dev] [PATCH i-g-t v7 2/5] tests/i915/i915_pm_rpm: modeset-pc8-residency-stress

[Anshuman Gupta]

Introduced pc8_needs_screen_off flag in order to differentiate
between HASWELL/BROADWELL and AT_LEAST_GEN9. GEN9 onward
PC8+ residency does't require display to be turned on.

v3:Removed pc8_needs_screen_off from mode_set_data structure,
   made it global, aligning to has_pc8 and has_runtime_pm global. [Ram]
   Made modeset_subtest() to tests PC8+ residency after enabling a screen,
   earlier it expects PC8+ residency to stop on HSW/BDW.

v4:Fixed conditional code for pc8_needs_screen_off. [Ram]
   Used macros for timeout values, given to PC8+ residency check function. [Ram]
   Changed the screen on timeout to check pc8+ residency to 10 seconds.

v5:Addressed minor review comment by changing macro name and by removing
   irrelevant change with respect to this series. [Ram]

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/i915/i915_pm_rpm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 5a585544..6ebbb30a 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -916,7 +916,13 @@ static void modeset_subtest(enum screen_type type, int rounds, int wait_flags)
 		if (wait_flags & WAIT_STATUS)
 			igt_assert(wait_for_active());
 		if (wait_flags & WAIT_PC8_RES)
-			igt_assert(!pc8_plus_residency_changed(5));
+			if (pc8_needs_screen_off)
+				igt_assert(!pc8_plus_residency_changed
+					   (IGT_TIME_OUT_SEC_5));
+			else
+				igt_assert(pc8_plus_residency_changed
+					   (IGT_TIME_OUT_SEC_10));
+
 		if (wait_flags & WAIT_EXTRA)
 			sleep(5);
 	}
-- 
2.21.0

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[igt-dev] [PATCH i-g-t v7 3/5] DEBUG: invoke powertop and pmc ltr_ignore when pc8 tests fails.

[Anshuman Gupta]

When pc8_residency test fails, try pc8 residency subtest after
setting powertop --auto-tune and further try sub-test with
pmc ltr_ignore attributes.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/i915/i915_pm_rpm.c | 130 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 129 insertions(+), 1 deletion(-)

diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 6ebbb30a..0c9a7890 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -99,6 +99,37 @@ int drm_fd, msr_fd, pc8_status_fd;
 int debugfs;
 bool has_runtime_pm, has_pc8, pc8_needs_screen_off;
 struct mode_set_data ms_data;
+int pmc_debugfs, max_ltr;
+bool pmc_loaded;
+
+#define ICL_MAX_LTR 20
+#define CNL_MAX_LTR 19
+#define SKL_MAX_LTR 17
+#define SIZE_PCH_IP_ARR 21
+
+const char *pch_ip[SIZE_PCH_IP_ARR] = {
+	"SOUTHPORT_A",
+	"SOUTHPORT_B",
+	"SATA",
+	"GIGABIT_ETHERNET",
+	"XHCI",
+	"Reserved",
+	"ME",
+	"EVA",
+	"SOUTHPORT_C",
+	"HD_AUDIO",
+	"CNV",
+	"LPSS",
+	"SOUTHPORT_D",
+	"SOUTHPORT_E",
+	"CAMERA",
+	"ESPI",
+	"SCC",
+	"ISH",
+	"UFSX2",
+	"EMMC",
+	"WIGIG"
+};
 
 /* Stuff used when creating FBs and mode setting. */
 struct mode_set_data {
@@ -776,6 +807,69 @@ static void setup_pc8(void)
 	has_pc8 = true;
 }
 
+static void pmc_ignore_ltr(int ip)
+{
+	char tmp[10];
+	int len, fd;
+
+	if (!pmc_loaded)
+		return;
+
+	len = snprintf(tmp, sizeof(tmp), "%d", ip);
+	fd = openat(pmc_debugfs, "ltr_ignore", O_WRONLY);
+	if (fd >= 0) {
+		igt_assert_eq(write(fd, tmp, len), len);
+		close(fd);
+	}
+}
+
+static bool setup_powertop(void)
+{
+	FILE *fp;
+	char tmp[512];
+
+	fp = popen("powertop --auto-tune", "r");
+	if (fp == NULL) {
+		igt_info("Failed to run powertop\n");
+		perror("popen");
+		return false;
+	}
+
+	while (fgets(tmp, sizeof(tmp), fp) != NULL)
+		igt_info("%s\n", tmp);
+
+	pclose(fp);
+	return true;
+}
+
+static bool setup_pmc(void)
+{
+	const char *debugfs_root;
+	char path[200];
+
+	/* Make sure our intel_pmc_core module is loaded. */
+	pmc_loaded = modprobe("intel_pmc_core") == 0;
+
+	if (!pmc_loaded) {
+		igt_info("intel_pmc_core module not loaded\n");
+		return;
+	}
+
+	if (IS_ICELAKE(ms_data.devid))
+		max_ltr = ICL_MAX_LTR;
+	else if (IS_CANNONLAKE(ms_data.devid))
+		max_ltr = CNL_MAX_LTR;
+	else if (AT_LEAST_GEN(ms_data.devid, 9) && !IS_BROXTON(ms_data.devid) &&
+		 !IS_GEMINILAKE(ms_data.devid))
+		max_ltr = SKL_MAX_LTR;
+
+	debugfs_root = igt_debugfs_mount();
+	igt_assert(debugfs_root);
+	snprintf(path, sizeof(path), "%s/pmc_core", debugfs_root);
+	pmc_debugfs = open(path, O_RDONLY);
+	igt_require(pmc_debugfs != -1);
+}
+
 static bool dmc_loaded(void)
 {
 	char buf[15];
@@ -803,6 +897,14 @@ static void dump_file(int dir, const char *filename)
 	free(contents);
 }
 
+static void pmc_dump_file(int fd, const char *file)
+{
+	if (!pmc_loaded)
+		return;
+
+	dump_file(fd, file);
+}
+
 static bool setup_environment(void)
 {
 	if (has_runtime_pm)
@@ -820,6 +922,7 @@ static bool setup_environment(void)
 	pm_data = igt_pm_enable_sata_link_power_management();
 
 	has_runtime_pm = igt_setup_runtime_pm();
+	setup_pmc();
 	setup_pc8();
 
 	igt_info("Runtime PM support: %d\n", has_runtime_pm);
@@ -865,11 +968,36 @@ static void basic_subtest(void)
 
 static void pc8_residency_subtest(void)
 {
+	bool passed;
+	int i;
 	igt_require(has_pc8);
 
 	/* Make sure PC8+ residencies move! */
 	disable_all_screens(&ms_data);
-	igt_assert_f(pc8_plus_residency_changed(30),
+	passed = pc8_plus_residency_changed(30);
+
+	/* Try With powertop --auto-tune */
+	if (!passed) {
+		igt_info("pc8+ residencies byyefore powertop --auto-tune\n");
+		pmc_dump_file(pmc_debugfs, "package_cstate_show");
+		igt_require(setup_powertop());
+		passed = pc8_plus_residency_changed(IGT_TIME_OUT_SEC_10);
+
+		if (!passed) {
+			igt_info("pc8+ residencies after powertop --auto-tune\n");
+			pmc_dump_file(pmc_debugfs, "package_cstate_show");
+		} else {
+			igt_info("pc8+ residencies subtest passed "
+				 "after running powertop --auto-tune\n");
+		}
+	}
+	/* dump ltr_show and pch_ip_power_gating_status */
+	igt_info("pch i/p latency tolerance reporting\n");
+	pmc_dump_file(pmc_debugfs, "ltr_show");
+	igt_info("pch i/p power gating status\n");
+	pmc_dump_file(pmc_debugfs, "pch_ip_power_gating_status");
+
+	igt_assert_f(passed,
 		     "Machine is not reaching PC8+ states, please check its "
 		     "configuration.\n");
 
-- 
2.21.0

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[igt-dev] [PATCH i-g-t v7 4/5] DEBUG:sub-test to check pc8 after enabling all planes on all pipes.

[Anshuman Gupta]

B.Specs doesn't specify that how many output can be enabled
in order to attain pc8 state. This is just to check whether
a platform can reach pc8 state with all planes enabled on
all pipes.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/i915/i915_pm_rpm.c | 204 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 203 insertions(+), 1 deletion(-)

diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 0c9a7890..e2b7e1ab 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -95,6 +95,9 @@ enum plane_type {
 #define WAIT_EXTRA	4
 #define USE_DPMS	8
 
+#define SIZE_PLANE      256
+#define SIZE_CURSOR     128
+
 int drm_fd, msr_fd, pc8_status_fd;
 int debugfs;
 bool has_runtime_pm, has_pc8, pc8_needs_screen_off;
@@ -131,12 +134,22 @@ const char *pch_ip[SIZE_PCH_IP_ARR] = {
 	"WIGIG"
 };
 
+typedef struct {
+	float red;
+	float green;
+	float blue;
+} color_t;
+
 /* Stuff used when creating FBs and mode setting. */
 struct mode_set_data {
 	drmModeResPtr res;
 	drmModeConnectorPtr connectors[MAX_CONNECTORS];
 	drmModePropertyBlobPtr edids[MAX_CONNECTORS];
-
+	drmModeModeInfo *mode;
+	igt_plane_t **plane;
+	struct igt_fb *fb_white;
+	igt_display_t display;
+	igt_output_t *output;
 	uint32_t devid;
 };
 
@@ -182,6 +195,184 @@ static int modprobe(const char *driver)
 {
 	return igt_kmod_load(driver, NULL);
 }
+static void
+create_fb_for_mode_position(struct mode_set_data *data, igt_output_t *output,
+			    drmModeModeInfo *mode, color_t *color, int *rect_x,
+			    int *rect_y, int *rect_w, int *rect_h,
+			    uint64_t tiling, int max_planes)
+{
+	unsigned int fb_id;
+	cairo_t *cr;
+	igt_plane_t *primary;
+
+	primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+
+	igt_skip_on(!igt_display_has_format_mod(&data->display,
+						DRM_FORMAT_XRGB8888,
+						tiling));
+
+	fb_id = igt_create_fb(drm_fd,
+			      mode->hdisplay, mode->vdisplay,
+			      DRM_FORMAT_XRGB8888,
+			      tiling,
+			      &data->fb_white[primary->index]);
+	igt_assert(fb_id);
+
+	cr = igt_get_cairo_ctx(drm_fd, &data->fb_white[primary->index]);
+	igt_paint_color(cr, rect_x[0], rect_y[0],
+			mode->hdisplay, mode->vdisplay,
+			color->red, color->green, color->blue);
+
+	for (int i = 0; i < max_planes; i++) {
+		if (data->plane[i]->type == DRM_PLANE_TYPE_PRIMARY)
+			continue;
+		igt_paint_color(cr, rect_x[i], rect_y[i],
+				rect_w[i], rect_h[i], 0.0, 0.0, 0.0);
+		}
+
+	igt_put_cairo_ctx(drm_fd, &data->fb_white[primary->index], cr);
+	}
+
+
+static void
+prepare_planes(struct mode_set_data *data, enum pipe pipe_id, color_t *color,
+	       uint64_t tiling, int max_planes, igt_output_t *output)
+{
+	drmModeModeInfo *mode;
+	igt_pipe_t *pipe;
+	igt_plane_t *primary;
+	int *x;
+	int *y;
+	int *size;
+	int i;
+
+	igt_output_set_pipe(output, pipe_id);
+	primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+	pipe = primary->pipe;
+
+	x = malloc(pipe->n_planes * sizeof(*x));
+	igt_assert_f(x, "Failed to allocate %ld bytes for variable x\n",
+		     (long)(pipe->n_planes * sizeof(*x)));
+	y = malloc(pipe->n_planes * sizeof(*y));
+	igt_assert_f(y, "Failed to allocate %ld bytes for variable y\n",
+		     (long)(pipe->n_planes * sizeof(*y)));
+	size = malloc(pipe->n_planes * sizeof(*size));
+	igt_assert_f(size, "Failed to allocate %ld bytes for variable size\n",
+		     (long)(pipe->n_planes * sizeof(*size)));
+
+	mode = igt_output_get_mode(output);
+
+	/* planes with random positions */
+	x[primary->index] = 0;
+	y[primary->index] = 0;
+	for (i = 0; i < max_planes; i++) {
+		igt_plane_t *plane = igt_output_get_plane(output, i);
+		uint32_t plane_format;
+		uint64_t plane_tiling;
+
+		if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+			continue;
+		else if (plane->type == DRM_PLANE_TYPE_CURSOR)
+			size[i] = SIZE_CURSOR;
+		else
+			size[i] = SIZE_PLANE;
+
+		x[i] = rand() % (mode->hdisplay - size[i]);
+		y[i] = rand() % (mode->vdisplay - size[i]);
+
+		data->plane[i] = plane;
+
+		plane_format = data->plane[i]->type == DRM_PLANE_TYPE_CURSOR ?
+			       DRM_FORMAT_ARGB8888 : DRM_FORMAT_XRGB8888;
+		plane_tiling = data->plane[i]->type == DRM_PLANE_TYPE_CURSOR ?
+			       LOCAL_DRM_FORMAT_MOD_NONE : tiling;
+
+		igt_skip_on(!igt_plane_has_format_mod(plane, plane_format,
+						      plane_tiling));
+
+		igt_create_color_fb(drm_fd,
+				    size[i], size[i],
+				    plane_format,
+				    plane_tiling,
+				    color->red, color->green, color->blue,
+				    &data->fb_white[i]);
+
+		igt_plane_set_position(data->plane[i], x[i], y[i]);
+		igt_plane_set_fb(data->plane[i], &data->fb_white[i]);
+	}
+
+	/* primary plane */
+	data->plane[primary->index] = primary;
+	create_fb_for_mode_position(data, output, mode, color, x, y,
+				    size, size, tiling, max_planes);
+	igt_plane_set_fb(data->plane[primary->index],
+			 &data->fb_white[primary->index]);
+}
+
+static void setup_output(struct mode_set_data *data)
+{
+	igt_display_t *display = &data->display;
+	igt_output_t *output;
+	igt_plane_t *primary;
+	enum pipe pipe;
+	color_t white  = { 1.0f, 1.0f, 1.0f };
+
+	for_each_pipe(display, pipe) {
+		int n_planes = data->display.pipes[pipe].n_planes;
+
+		data->plane = calloc(n_planes, sizeof(*data->plane));
+		igt_assert_f(data->plane != NULL,
+			     "Failed to allocate memory for planes\n");
+		data->fb_white = calloc(n_planes, sizeof(struct igt_fb));
+		igt_assert_f(data->fb_white != NULL,
+			     "Failed to allocate memory for FBs\n");
+		output = igt_get_single_output_for_pipe(&data->display, pipe);
+		igt_require(output);
+		prepare_planes(data, pipe, &white,
+			       LOCAL_DRM_FORMAT_MOD_NONE, n_planes, output);
+		igt_display_commit(&data->display);
+	}
+		return;
+}
+
+static void display_init(struct mode_set_data *data)
+{
+	igt_display_require(&data->display, drm_fd);
+	setup_output(data);
+}
+
+static void display_fini(struct mode_set_data *data)
+{
+	igt_display_fini(&data->display);
+}
+
+static void cleanup(struct mode_set_data *data)
+{
+	enum pipe pipe;
+
+	for_each_pipe(&data->display, pipe) {
+		int n_planes = data->display.pipes[pipe].n_planes;
+
+		for (int i = 0; i < n_planes; i++) {
+			igt_plane_t *plane = data->plane[i];
+
+			if (!plane)
+				continue;
+
+			if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+				continue;
+
+			igt_plane_set_fb(plane, NULL);
+			data->plane[i] = NULL;
+		}
+	}
+
+	free(data->plane);
+	data->plane = NULL;
+	igt_remove_fb(drm_fd, data->fb_white);
+	free(data->fb_white);
+	display_fini(data);
+}
 
 /* If the read fails, then the machine doesn't support PC8+ residencies. */
 static bool supports_pc8_plus_residencies(void)
@@ -1015,6 +1206,15 @@ static void pc8_residency_subtest(void)
 	}
 }
 
+static void pc8_residency_subtest_all_pipes_all_plain(void)
+{
+	display_init(&ms_data);
+	igt_assert_f(pc8_plus_residency_changed(10),
+		     "Machine is not reaching PC8+ states "
+		     "with all pipes and planes enabled.\n");
+	cleanup(&ms_data);
+}
+
 static void modeset_subtest(enum screen_type type, int rounds, int wait_flags)
 {
 	int i;
@@ -2244,6 +2444,8 @@ int main(int argc, char *argv[])
 		i2c_subtest();
 	igt_subtest("pc8-residency")
 		pc8_residency_subtest();
+	igt_subtest("pc8-residency-all-pipes-planes")
+		pc8_residency_subtest_all_pipes_all_plain();
 	igt_subtest("debugfs-read")
 		debugfs_read_subtest();
 	igt_subtest("debugfs-forcewake-user")
-- 
2.21.0

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[igt-dev] [PATCH i-g-t v7 5/5] DO_NOT_MERGE: adding i915_pm_rpm pc8 subtest to fast feedback list.

[Anshuman Gupta]

Forcing CI to test below sub-test on ICL.
pc8-residency
modeset-pc8-residency-stress
gem-execbuf-stress-pc8

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 tests/intel-ci/fast-feedback.testlist | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index 40475b1a..81291dfe 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -218,6 +218,10 @@ igt@kms_setmode@basic-clone-single-crtc
 igt@i915_pm_backlight@basic-brightness
 igt@i915_pm_rpm@basic-pci-d3-state
 igt@i915_pm_rpm@basic-rte
+igt@i915_pm_rpm@pc8-residency
+igt@i915_pm_rpm@pc8-residency-all-pipes-planes
+igt@i915_pm_rpm@gem-execbuf-stress-pc8
+igt@i915_pm_rpm@modeset-pc8-residency-stress
 igt@i915_pm_rps@basic-api
 igt@prime_busy@basic-after-default
 igt@prime_busy@basic-before-default
-- 
2.21.0

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[igt-dev] ✗ Fi.CI.BAT: failure for Enabling PC8+ residency for all GEN9+ platforms (rev7)

[Patchwork]

== Series Details ==

Series: Enabling PC8+ residency for all GEN9+ platforms (rev7)
URL   : https://patchwork.freedesktop.org/series/57640/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6187 -> IGTPW_3107
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3107 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3107, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/57640/revisions/7/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3107:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_rpm@modeset-pc8-residency-stress:
    - fi-icl-u2:          NOTRUN -> [FAIL][1] +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-icl-u2/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
    - fi-kbl-8809g:       NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-kbl-8809g/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
    - fi-skl-6600u:       NOTRUN -> [FAIL][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-skl-6600u/igt@i915_pm_rpm@modeset-pc8-residency-stress.html

  * igt@i915_pm_rpm@pc8-residency:
    - fi-cfl-8109u:       NOTRUN -> [FAIL][4] +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-cfl-8109u/igt@i915_pm_rpm@pc8-residency.html
    - fi-kbl-8809g:       NOTRUN -> [DMESG-FAIL][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-kbl-8809g/igt@i915_pm_rpm@pc8-residency.html
    - fi-icl-y:           NOTRUN -> [DMESG-WARN][6]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-icl-y/igt@i915_pm_rpm@pc8-residency.html
    - fi-cml-u2:          NOTRUN -> [DMESG-WARN][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-cml-u2/igt@i915_pm_rpm@pc8-residency.html
    - fi-cml-u:           NOTRUN -> [DMESG-WARN][8]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-cml-u/igt@i915_pm_rpm@pc8-residency.html

  * {igt@i915_pm_rpm@pc8-residency-all-pipes-planes} (NEW):
    - fi-kbl-7500u:       NOTRUN -> [FAIL][9]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-kbl-7500u/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html
    - fi-cfl-8700k:       NOTRUN -> [FAIL][10]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-cfl-8700k/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html
    - fi-kbl-x1275:       NOTRUN -> [FAIL][11]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-kbl-x1275/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html
    - {fi-skl-guc}:       NOTRUN -> [FAIL][12]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-skl-guc/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html
    - fi-kbl-7567u:       NOTRUN -> [FAIL][13] +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-kbl-7567u/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html
    - fi-skl-iommu:       NOTRUN -> [FAIL][14]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-skl-iommu/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html
    - {fi-cfl-guc}:       NOTRUN -> [FAIL][15]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-cfl-guc/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html
    - fi-skl-6260u:       NOTRUN -> [FAIL][16]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-skl-6260u/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html
    - fi-skl-lmem:        NOTRUN -> [FAIL][17]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-skl-lmem/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html
    - fi-skl-6770hq:      NOTRUN -> [FAIL][18]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-skl-6770hq/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html
    - fi-skl-6700k2:      NOTRUN -> [FAIL][19]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-skl-6700k2/igt@i915_pm_rpm@pc8-residency-all-pipes-planes.html

  * igt@i915_selftest@live_timelines:
    - fi-cfl-8109u:       [PASS][20] -> [INCOMPLETE][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-cfl-8109u/igt@i915_selftest@live_timelines.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-cfl-8109u/igt@i915_selftest@live_timelines.html

  
New tests
---------

  New tests have been introduced between CI_DRM_6187 and IGTPW_3107:

### New IGT tests (1) ###

  * igt@i915_pm_rpm@pc8-residency-all-pipes-planes:
    - Statuses : 15 fail(s) 5 pass(s) 25 skip(s)
    - Exec time: [0.0, 22.68] s

  

Known issues
------------

  Here are the changes found in IGTPW_3107 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_auth@basic-auth:
    - fi-icl-u3:          [PASS][22] -> [DMESG-WARN][23] ([fdo#107724])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-icl-u3/igt@core_auth@basic-auth.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-icl-u3/igt@core_auth@basic-auth.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-hsw-4770r:       [PASS][24] -> [SKIP][25] ([fdo#109271]) +2 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-hsw-4770r/igt@i915_pm_rpm@basic-pci-d3-state.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-hsw-4770r/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-glk-dsi:         [PASS][26] -> [SKIP][27] ([fdo#109271]) +2 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-glk-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-glk-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-bdw-5557u:       [PASS][28] -> [SKIP][29] ([fdo#109271]) +2 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-bdw-5557u/igt@i915_pm_rpm@basic-pci-d3-state.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-bdw-5557u/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-hsw-4770:        [PASS][30] -> [SKIP][31] ([fdo#109271]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-bxt-dsi:         [PASS][32] -> [SKIP][33] ([fdo#109271]) +2 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-bxt-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-bxt-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-bsw-n3050:       [PASS][34] -> [SKIP][35] ([fdo#109271]) +2 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-byt-n2820:       [PASS][36] -> [SKIP][37] ([fdo#109271]) +2 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-byt-n2820/igt@i915_pm_rpm@basic-rte.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-byt-n2820/igt@i915_pm_rpm@basic-rte.html
    - fi-hsw-peppy:       [PASS][38] -> [SKIP][39] ([fdo#109271]) +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-hsw-peppy/igt@i915_pm_rpm@basic-rte.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-hsw-peppy/igt@i915_pm_rpm@basic-rte.html
    - fi-byt-j1900:       [PASS][40] -> [SKIP][41] ([fdo#109271]) +2 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-byt-j1900/igt@i915_pm_rpm@basic-rte.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-byt-j1900/igt@i915_pm_rpm@basic-rte.html
    - fi-bxt-j4205:       [PASS][42] -> [SKIP][43] ([fdo#109271]) +2 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-bxt-j4205/igt@i915_pm_rpm@basic-rte.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-bxt-j4205/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
    - fi-bsw-kefka:       [PASS][44] -> [SKIP][45] ([fdo#109271]) +2 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-bsw-kefka/igt@i915_pm_rpm@module-reload.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-bsw-kefka/igt@i915_pm_rpm@module-reload.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - fi-icl-u3:          [DMESG-WARN][46] ([fdo#107724]) -> [PASS][47] +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-icl-u3/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-icl-u3/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-blb-e6850:       [INCOMPLETE][48] ([fdo#107718]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#110829]: https://bugs.freedesktop.org/show_bug.cgi?id=110829


Participating hosts (54 -> 46)
------------------------------

  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * IGT: IGT_5037 -> IGTPW_3107

  CI_DRM_6187: 201dda6b2f7138214cdba69211c7504ce7b8b96e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3107: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/
  IGT_5037: a98c9cd50aa48933217ca41055279ccb1680d25b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@i915_pm_rpm@pc8-residency-all-pipes-planes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3107/
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