* [igt-dev] [PATCH 01/10] lib: sync i915_pciids.h with kernel
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
@ 2019-07-15 21:51 ` Lucas De Marchi
2019-07-19 6:20 ` Arkadiusz Hiler
2019-07-15 21:51 ` [igt-dev] [PATCH 02/10] lib/tgl: Add Tigerlake platform definition Lucas De Marchi
` (9 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-15 21:51 UTC (permalink / raw)
To: igt-dev
Straight copy from the kernel file, aligned with drm-intel-next-queued
commit cb823ed9915b ("drm/i915/gt: Use intel_gt as the primary object
for handling resets")
By Stuart: Add the mobile vs non-mobile pineview platforms to device
info to match what is in the kernel.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
lib/i915_pciids.h | 191 +++++++++++++++++++++++++++++-----------
lib/intel_device_info.c | 12 ++-
2 files changed, 149 insertions(+), 54 deletions(-)
diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
index 0adce335..a70c982d 100644
--- a/lib/i915_pciids.h
+++ b/lib/i915_pciids.h
@@ -108,8 +108,10 @@
INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
-#define INTEL_PINEVIEW_IDS(info) \
- INTEL_VGA_DEVICE(0xa001, info), \
+#define INTEL_PINEVIEW_G_IDS(info) \
+ INTEL_VGA_DEVICE(0xa001, info)
+
+#define INTEL_PINEVIEW_M_IDS(info) \
INTEL_VGA_DEVICE(0xa011, info)
#define INTEL_IRONLAKE_D_IDS(info) \
@@ -166,7 +168,18 @@
#define INTEL_IVB_Q_IDS(info) \
INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
+#define INTEL_HSW_ULT_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
+ INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */
+
+#define INTEL_HSW_ULX_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
+
#define INTEL_HSW_GT1_IDS(info) \
+ INTEL_HSW_ULT_GT1_IDS(info), \
+ INTEL_HSW_ULX_GT1_IDS(info), \
INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
@@ -175,20 +188,26 @@
INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
- INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
+#define INTEL_HSW_ULT_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
+ INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */
+
+#define INTEL_HSW_ULX_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
+
#define INTEL_HSW_GT2_IDS(info) \
+ INTEL_HSW_ULT_GT2_IDS(info), \
+ INTEL_HSW_ULX_GT2_IDS(info), \
INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
@@ -197,9 +216,6 @@
INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
- INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
- INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
@@ -207,11 +223,17 @@
INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
+#define INTEL_HSW_ULT_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
+ INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+ INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
+
#define INTEL_HSW_GT3_IDS(info) \
+ INTEL_HSW_ULT_GT3_IDS(info), \
INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
@@ -220,16 +242,11 @@
INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
- INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
- INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
- INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
- INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
#define INTEL_HSW_IDS(info) \
@@ -245,35 +262,59 @@
INTEL_VGA_DEVICE(0x0157, info), \
INTEL_VGA_DEVICE(0x0155, info)
-#define INTEL_BDW_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
+#define INTEL_BDW_ULT_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
- INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
- INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
+ INTEL_VGA_DEVICE(0x160B, info) /* GT1 Iris */
+
+#define INTEL_BDW_ULX_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */
+
+#define INTEL_BDW_GT1_IDS(info) \
+ INTEL_BDW_ULT_GT1_IDS(info), \
+ INTEL_BDW_ULX_GT1_IDS(info), \
+ INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
-#define INTEL_BDW_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
+#define INTEL_BDW_ULT_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
- INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
- INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
+ INTEL_VGA_DEVICE(0x161B, info) /* GT2 ULT */
+
+#define INTEL_BDW_ULX_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
+
+#define INTEL_BDW_GT2_IDS(info) \
+ INTEL_BDW_ULT_GT2_IDS(info), \
+ INTEL_BDW_ULX_GT2_IDS(info), \
+ INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
+#define INTEL_BDW_ULT_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x162B, info) /* Iris */ \
+
+#define INTEL_BDW_ULX_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x162E, info) /* ULX */
+
#define INTEL_BDW_GT3_IDS(info) \
+ INTEL_BDW_ULT_GT3_IDS(info), \
+ INTEL_BDW_ULX_GT3_IDS(info), \
INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
- INTEL_VGA_DEVICE(0x162E, info), /* ULX */\
INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
+#define INTEL_BDW_ULT_RSVD_IDS(info) \
+ INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x163B, info) /* Iris */
+
+#define INTEL_BDW_ULX_RSVD_IDS(info) \
+ INTEL_VGA_DEVICE(0x163E, info) /* ULX */
+
#define INTEL_BDW_RSVD_IDS(info) \
+ INTEL_BDW_ULT_RSVD_IDS(info), \
+ INTEL_BDW_ULX_RSVD_IDS(info), \
INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
- INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \
INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
@@ -289,25 +330,40 @@
INTEL_VGA_DEVICE(0x22b2, info), \
INTEL_VGA_DEVICE(0x22b3, info)
+#define INTEL_SKL_ULT_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
+
+#define INTEL_SKL_ULX_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
+
#define INTEL_SKL_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
- INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+ INTEL_SKL_ULT_GT1_IDS(info), \
+ INTEL_SKL_ULX_GT1_IDS(info), \
INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
-#define INTEL_SKL_GT2_IDS(info) \
+#define INTEL_SKL_ULT_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
- INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
- INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x1921, info) /* ULT GT2F */
+
+#define INTEL_SKL_ULX_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */
+
+#define INTEL_SKL_GT2_IDS(info) \
+ INTEL_SKL_ULT_GT2_IDS(info), \
+ INTEL_SKL_ULX_GT2_IDS(info), \
INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
+#define INTEL_SKL_ULT_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
+
#define INTEL_SKL_GT3_IDS(info) \
+ INTEL_SKL_ULT_GT3_IDS(info), \
INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */
@@ -336,29 +392,44 @@
INTEL_VGA_DEVICE(0x3184, info), \
INTEL_VGA_DEVICE(0x3185, info)
-#define INTEL_KBL_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
- INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
+#define INTEL_KBL_ULT_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+ INTEL_VGA_DEVICE(0x5913, info) /* ULT GT1.5 */
+
+#define INTEL_KBL_ULX_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x5915, info) /* ULX GT1.5 */
+
+#define INTEL_KBL_GT1_IDS(info) \
+ INTEL_KBL_ULT_GT1_IDS(info), \
+ INTEL_KBL_ULX_GT1_IDS(info), \
INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
-#define INTEL_KBL_GT2_IDS(info) \
+#define INTEL_KBL_ULT_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+ INTEL_VGA_DEVICE(0x5921, info) /* ULT GT2F */
+
+#define INTEL_KBL_ULX_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x591E, info) /* ULX GT2 */
+
+#define INTEL_KBL_GT2_IDS(info) \
+ INTEL_KBL_ULT_GT2_IDS(info), \
+ INTEL_KBL_ULX_GT2_IDS(info), \
INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
- INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
- INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
+#define INTEL_KBL_ULT_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */
+
#define INTEL_KBL_GT3_IDS(info) \
+ INTEL_KBL_ULT_GT3_IDS(info), \
INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
#define INTEL_KBL_GT4_IDS(info) \
@@ -465,7 +536,14 @@
INTEL_CML_GT2_IDS(info)
/* CNL */
+#define INTEL_CNL_PORT_F_IDS(info) \
+ INTEL_VGA_DEVICE(0x5A54, info), \
+ INTEL_VGA_DEVICE(0x5A5C, info), \
+ INTEL_VGA_DEVICE(0x5A44, info), \
+ INTEL_VGA_DEVICE(0x5A4C, info)
+
#define INTEL_CNL_IDS(info) \
+ INTEL_CNL_PORT_F_IDS(info), \
INTEL_VGA_DEVICE(0x5A51, info), \
INTEL_VGA_DEVICE(0x5A59, info), \
INTEL_VGA_DEVICE(0x5A41, info), \
@@ -475,18 +553,12 @@
INTEL_VGA_DEVICE(0x5A42, info), \
INTEL_VGA_DEVICE(0x5A4A, info), \
INTEL_VGA_DEVICE(0x5A50, info), \
- INTEL_VGA_DEVICE(0x5A40, info), \
- INTEL_VGA_DEVICE(0x5A54, info), \
- INTEL_VGA_DEVICE(0x5A5C, info), \
- INTEL_VGA_DEVICE(0x5A44, info), \
- INTEL_VGA_DEVICE(0x5A4C, info)
+ INTEL_VGA_DEVICE(0x5A40, info)
/* ICL */
-#define INTEL_ICL_11_IDS(info) \
+#define INTEL_ICL_PORT_F_IDS(info) \
INTEL_VGA_DEVICE(0x8A50, info), \
- INTEL_VGA_DEVICE(0x8A51, info), \
INTEL_VGA_DEVICE(0x8A5C, info), \
- INTEL_VGA_DEVICE(0x8A5D, info), \
INTEL_VGA_DEVICE(0x8A59, info), \
INTEL_VGA_DEVICE(0x8A58, info), \
INTEL_VGA_DEVICE(0x8A52, info), \
@@ -499,6 +571,11 @@
INTEL_VGA_DEVICE(0x8A53, info), \
INTEL_VGA_DEVICE(0x8A54, info)
+#define INTEL_ICL_11_IDS(info) \
+ INTEL_ICL_PORT_F_IDS(info), \
+ INTEL_VGA_DEVICE(0x8A51, info), \
+ INTEL_VGA_DEVICE(0x8A5D, info)
+
/* EHL */
#define INTEL_EHL_IDS(info) \
INTEL_VGA_DEVICE(0x4500, info), \
@@ -506,4 +583,14 @@
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4541, info)
+/* TGL */
+#define INTEL_TGL_12_IDS(info) \
+ INTEL_VGA_DEVICE(0x9A49, info), \
+ INTEL_VGA_DEVICE(0x9A40, info), \
+ INTEL_VGA_DEVICE(0x9A59, info), \
+ INTEL_VGA_DEVICE(0x9A60, info), \
+ INTEL_VGA_DEVICE(0x9A68, info), \
+ INTEL_VGA_DEVICE(0x9A70, info), \
+ INTEL_VGA_DEVICE(0x9A78, info)
+
#endif /* _I915_PCIIDS_H */
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index be192b61..f4d9d9e1 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -69,7 +69,14 @@ static const struct intel_device_info intel_g33_info = {
.is_bearlake = true,
.codename = "bearlake"
};
-static const struct intel_device_info intel_pineview_info = {
+
+static const struct intel_device_info intel_pineview_g_info = {
+ .gen = BIT(2),
+ .is_pineview = true,
+ .codename = "pineview"
+};
+
+static const struct intel_device_info intel_pineview_m_info = {
.gen = BIT(2),
.is_mobile = true,
.is_pineview = true,
@@ -317,7 +324,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_I945GM_IDS(&intel_i945m_info),
INTEL_G33_IDS(&intel_g33_info),
- INTEL_PINEVIEW_IDS(&intel_pineview_info),
+ INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
+ INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
INTEL_I965G_IDS(&intel_i965_info),
INTEL_I965GM_IDS(&intel_i965m_info),
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [igt-dev] [PATCH 02/10] lib/tgl: Add Tigerlake platform definition
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
2019-07-15 21:51 ` [igt-dev] [PATCH 01/10] lib: sync i915_pciids.h with kernel Lucas De Marchi
@ 2019-07-15 21:51 ` Lucas De Marchi
2019-07-19 6:21 ` Arkadiusz Hiler
2019-07-15 21:51 ` [igt-dev] [PATCH 03/10] gem_ctx_isolation.c/tgl - Gen12 enabling for context isolation test Lucas De Marchi
` (8 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-15 21:51 UTC (permalink / raw)
To: igt-dev; +Cc: Javier Villavicencio, Rodrigo Vivi
From: Javier Villavicencio <javier.villavicencio@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Javier Villavicencio <javier.villavicencio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
lib/intel_chipset.h | 3 +++
lib/intel_device_info.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 74a40a46..781486d0 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -71,6 +71,7 @@ struct intel_device_info {
bool is_cometlake : 1;
bool is_cannonlake : 1;
bool is_icelake : 1;
+ bool is_tigerlake : 1;
const char *codename;
};
@@ -168,6 +169,7 @@ void intel_check_pch(void);
#define IS_COFFEELAKE(devid) (intel_get_device_info(devid)->is_coffeelake)
#define IS_CANNONLAKE(devid) (intel_get_device_info(devid)->is_cannonlake)
#define IS_ICELAKE(devid) (intel_get_device_info(devid)->is_icelake)
+#define IS_TIGERLAKE(devid) (intel_get_device_info(devid)->is_tigerlake)
#define IS_GEN(devid, x) (intel_get_device_info(devid)->gen & (1u << ((x)-1)))
#define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->gen & -(1u << ((x)-1)))
@@ -182,6 +184,7 @@ void intel_check_pch(void);
#define IS_GEN9(devid) IS_GEN(devid, 9)
#define IS_GEN10(devid) IS_GEN(devid, 10)
#define IS_GEN11(devid) IS_GEN(devid, 11)
+#define IS_GEN12(devid) IS_GEN(devid, 12)
#define IS_MOBILE(devid) (intel_get_device_info(devid)->is_mobile)
#define IS_965(devid) AT_LEAST_GEN(devid, 4)
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index f4d9d9e1..cb6973f0 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -309,6 +309,12 @@ static const struct intel_device_info intel_icelake_info = {
.codename = "icelake"
};
+static const struct intel_device_info intel_tigerlake_info = {
+ .gen = BIT(11),
+ .is_tigerlake = true,
+ .codename = "tigerlake"
+};
+
static const struct pci_id_match intel_device_match[] = {
INTEL_I810_IDS(&intel_i810_info),
INTEL_I815_IDS(&intel_i815_info),
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [igt-dev] [PATCH 03/10] gem_ctx_isolation.c/tgl - Gen12 enabling for context isolation test
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
2019-07-15 21:51 ` [igt-dev] [PATCH 01/10] lib: sync i915_pciids.h with kernel Lucas De Marchi
2019-07-15 21:51 ` [igt-dev] [PATCH 02/10] lib/tgl: Add Tigerlake platform definition Lucas De Marchi
@ 2019-07-15 21:51 ` Lucas De Marchi
2019-07-15 21:51 ` [igt-dev] [PATCH 04/10] lib/tgl: Add TGL PCI IDs to match table Lucas De Marchi
` (7 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-15 21:51 UTC (permalink / raw)
To: igt-dev
From: Dale B Stimson <dale.b.stimson@intel.com>
For Gen12:
Enable test execution.
Tests have been disabled for registers which Gen12 made privileged
and which are not in the kernel whitelist.
Tests have been added for context register(s) added to the kernel
whitelist for Gen12.
Previously present registers that are no longer in the render context
have been removed.
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
tests/i915/gem_ctx_isolation.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index c4302394..cd0c836e 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -55,10 +55,11 @@ enum {
#define GEN9 (ALL << 9)
#define GEN10 (ALL << 10)
#define GEN11 (ALL << 11)
+#define GEN12 (ALL << 12)
#define NOCTX 0
-#define LAST_KNOWN_GEN 11
+#define LAST_KNOWN_GEN 12
static const struct named_register {
const char *name;
@@ -116,9 +117,12 @@ static const struct named_register {
{ "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
{ "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
{ "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
- { "L3_Config", GEN8, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff },
- { "TD_CTL2", GEN8, RCS0, 0xe404 },
+
+ /* Gen12: these registers became privileged, are not in whitelist. */
+ { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
+ { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff },
+ { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
+
{ "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
{ "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
{ "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
@@ -145,6 +149,8 @@ static const struct named_register {
{ "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
{ "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
{ "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true },
+ { "COMMON_SLICE_CHICKEN2", GEN_RANGE(12, 12), RCS0, 0x7014, .masked = true },
+ /* SAMPLER_MODE - Gen12 - In whitelist, but no longer in context. */
{ "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },
{ "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [igt-dev] [PATCH 04/10] lib/tgl: Add TGL PCI IDs to match table
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
` (2 preceding siblings ...)
2019-07-15 21:51 ` [igt-dev] [PATCH 03/10] gem_ctx_isolation.c/tgl - Gen12 enabling for context isolation test Lucas De Marchi
@ 2019-07-15 21:51 ` Lucas De Marchi
2019-07-19 6:21 ` Arkadiusz Hiler
2019-07-15 21:51 ` [igt-dev] [PATCH 05/10] lib/instdone.c/tgl: Add Gen12 support Lucas De Marchi
` (6 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-15 21:51 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
lib/intel_device_info.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index cb6973f0..4f96577d 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -396,6 +396,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_EHL_IDS(&intel_icelake_info),
+ INTEL_TGL_12_IDS(&intel_tigerlake_info),
+
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
};
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [igt-dev] [PATCH 05/10] lib/instdone.c/tgl: Add Gen12 support
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
` (3 preceding siblings ...)
2019-07-15 21:51 ` [igt-dev] [PATCH 04/10] lib/tgl: Add TGL PCI IDs to match table Lucas De Marchi
@ 2019-07-15 21:51 ` Lucas De Marchi
2019-07-15 21:51 ` [igt-dev] [PATCH 06/10] lib/gpgpu_fill/tgl: Implement gpgpu_fillfunc for TGL Lucas De Marchi
` (5 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-15 21:51 UTC (permalink / raw)
To: igt-dev; +Cc: Javier Villavicencio
From: Javier Villavicencio <javier.villavicencio@intel.com>
Same as GEN11.
Signed-off-by: Javier Villavicencio <javier.villavicencio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
lib/instdone.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/instdone.c b/lib/instdone.c
index a83f8836..aa6436c6 100644
--- a/lib/instdone.c
+++ b/lib/instdone.c
@@ -428,7 +428,7 @@ init_gen11_instdone(void)
bool
init_instdone_definitions(uint32_t devid)
{
- if (IS_GEN11(devid)) {
+ if (IS_GEN11(devid) || IS_GEN12(devid)) {
init_gen11_instdone();
} else if (IS_GEN8(devid) || IS_GEN9(devid) || IS_GEN10(devid)) {
init_gen8_instdone();
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [igt-dev] [PATCH 06/10] lib/gpgpu_fill/tgl: Implement gpgpu_fillfunc for TGL
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
` (4 preceding siblings ...)
2019-07-15 21:51 ` [igt-dev] [PATCH 05/10] lib/instdone.c/tgl: Add Gen12 support Lucas De Marchi
@ 2019-07-15 21:51 ` Lucas De Marchi
2019-07-15 21:51 ` [igt-dev] [PATCH 07/10] lib/media_fill/tgl: Implement media_fillfunc " Lucas De Marchi
` (4 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-15 21:51 UTC (permalink / raw)
To: igt-dev
From: Katarzyna Dec <katarzyna.dec@intel.com>
Adding gen12p1_gpgpu_fillfunc to have gpgpu_fill running on TGL.
Gpgpu shader was generated using IGA (Intel Graphics Assembler)
based on Gen11 binary adding necessary SWSB dependencies and
changes in SEND instruction.
Shader source code and array containing its assembled version
have same names now to avoid ambiguity.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Signed-off-by: Katarzyna Dec <katarzyna.dec@intel.com>
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
lib/gpgpu_fill.c | 22 +++++++++++++++++++
lib/gpgpu_fill.h | 7 ++++++
lib/i915/shaders/README | 2 ++
.../shaders/gpgpu/gen12p1_gpgpu_kernel.asm | 12 ++++++++++
lib/intel_batchbuffer.c | 2 ++
5 files changed, 45 insertions(+)
create mode 100644 lib/i915/shaders/gpgpu/gen12p1_gpgpu_kernel.asm
diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
index 003f4616..ec7204b8 100644
--- a/lib/gpgpu_fill.c
+++ b/lib/gpgpu_fill.c
@@ -87,6 +87,19 @@ static const uint32_t gen11_gpgpu_kernel[][4] = {
{ 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 },
};
+static const uint32_t gen12p1_gpgpu_kernel[][4] = {
+ { 0x00020061, 0x01050000, 0x00000104, 0x00000000 },
+ { 0x00000069, 0x02058220, 0x02000024, 0x00000004 },
+ { 0x00000061, 0x02250220, 0x000000c4, 0x00000000 },
+ { 0x00030061, 0x04050220, 0x00460005, 0x00000000 },
+ { 0x00010261, 0x04050220, 0x00220205, 0x00000000 },
+ { 0x00000061, 0x04454220, 0x00000000, 0x0000000f },
+ { 0x00040661, 0x05050220, 0x00000104, 0x00000000 },
+ { 0x00049031, 0x00000000, 0xc0000414, 0x02a00000 },
+ { 0x00030061, 0x70050220, 0x00460005, 0x00000000 },
+ { 0x00040131, 0x00000004, 0x7020700c, 0x10000000 },
+};
+
/*
* This sets up the gpgpu pipeline,
*
@@ -282,3 +295,12 @@ void gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch,
__gen9_gpgpu_fillfunc(batch, dst, x, y, width, height, color,
gen11_gpgpu_kernel, sizeof(gen11_gpgpu_kernel));
}
+void gen12p1_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+ const struct igt_buf *dst,
+ unsigned int x, unsigned int y,
+ unsigned int width, unsigned int height,
+ uint8_t color)
+{
+ __gen9_gpgpu_fillfunc(batch, dst, x, y, width, height, color,
+ gen12p1_gpgpu_kernel, sizeof(gen12p1_gpgpu_kernel));
+}
diff --git a/lib/gpgpu_fill.h b/lib/gpgpu_fill.h
index e405df3e..91c7ef71 100644
--- a/lib/gpgpu_fill.h
+++ b/lib/gpgpu_fill.h
@@ -57,4 +57,11 @@ gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch,
unsigned int width, unsigned int height,
uint8_t color);
+void
+gen12p1_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+ const struct igt_buf *dst,
+ unsigned int x, unsigned int y,
+ unsigned int width, unsigned int height,
+ uint8_t color);
+
#endif /* GPGPU_FILL_H */
diff --git a/lib/i915/shaders/README b/lib/i915/shaders/README
index 06b9883c..6f80111b 100644
--- a/lib/i915/shaders/README
+++ b/lib/i915/shaders/README
@@ -23,3 +23,5 @@ Commands used to generate the shader on gen8
$> m4 media_fill.gxa > media_fill.gxm
$> intel-gen4asm -g 8 -o <output> media_fill.gxm
+Gen11+ shader is generated using IGA (Intel Graphics Assembler).
+Binary can no longer be generated using intel-gen4asm.
diff --git a/lib/i915/shaders/gpgpu/gen12p1_gpgpu_kernel.asm b/lib/i915/shaders/gpgpu/gen12p1_gpgpu_kernel.asm
new file mode 100644
index 00000000..ede87a05
--- /dev/null
+++ b/lib/i915/shaders/gpgpu/gen12p1_gpgpu_kernel.asm
@@ -0,0 +1,12 @@
+L0:
+ mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub
+ shl (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud 0x4:ud
+ mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud
+ mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud
+ mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud {@2}
+ mov (1|M0) r4.2<1>:ud 0xF:ud
+ mov (16|M0) r5.0<1>:ud r1.0<0;1,0>:ud {@6}
+ send.dc1 (16|M0) null r4 null 0x0 0x40A8000 {@1, $0} // wr:2h+0, rd:0, Media Block Write msc:0, to #0
+ mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud
+ send.ts (16|M0) null r112 null 0x10000000 0x2000010 {EOT, @1} // wr:1+0, rd:0, fc: 0x10
+L160:
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 07de5cbb..7fac25b8 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -901,6 +901,8 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid)
fill = gen9_gpgpu_fillfunc;
else if (IS_GEN11(devid))
fill = gen11_gpgpu_fillfunc;
+ else if (IS_TIGERLAKE(devid))
+ fill = gen12p1_gpgpu_fillfunc;
return fill;
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [igt-dev] [PATCH 07/10] lib/media_fill/tgl: Implement media_fillfunc for TGL
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
` (5 preceding siblings ...)
2019-07-15 21:51 ` [igt-dev] [PATCH 06/10] lib/gpgpu_fill/tgl: Implement gpgpu_fillfunc for TGL Lucas De Marchi
@ 2019-07-15 21:51 ` Lucas De Marchi
2019-07-15 21:51 ` [igt-dev] [PATCH 08/10] tests/fb/tgl: Yf tiling does not exist on gen-12 Lucas De Marchi
` (3 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-15 21:51 UTC (permalink / raw)
To: igt-dev
From: Katarzyna Dec <katarzyna.dec@intel.com>
Adding gen12p1_media_fillfunc to have media_fill running on TGL.
Media shader was generated using IGA (Intel Graphics Assembler)
based on binary found in lib/media_fill_gen9.c to match the
changes in TGL HW. Main change was made in SEND instructions
and adding SWSB dependencies.
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Katarzyna Dec <katarzyna.dec@intel.com>
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../shaders/media/gen12p1_media_kernel.asm | 13 ++++++++++
lib/intel_batchbuffer.c | 4 ++-
lib/media_fill.c | 25 +++++++++++++++++++
lib/media_fill.h | 7 ++++++
4 files changed, 48 insertions(+), 1 deletion(-)
create mode 100644 lib/i915/shaders/media/gen12p1_media_kernel.asm
diff --git a/lib/i915/shaders/media/gen12p1_media_kernel.asm b/lib/i915/shaders/media/gen12p1_media_kernel.asm
new file mode 100644
index 00000000..5be229b2
--- /dev/null
+++ b/lib/i915/shaders/media/gen12p1_media_kernel.asm
@@ -0,0 +1,13 @@
+L0:
+ mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub
+ mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud
+ mov (8|M0) r4.0<1>:ud r2.0<2;2,1>:ud
+ mov (1|M0) r4.2<1>:ud 0xF000F:ud
+ mov (16|M0) r5.0<1>:ud r1.0<0;1,0>:ud {@4}
+ mov (16|M0) r7.0<1>:ud r1.0<0;1,0>:ud {@5}
+ mov (16|M0) r9.0<1>:ud r1.0<0;1,0>:ud {@6}
+ mov (16|M0) r11.0<1>:ud r1.0<0;1,0>:ud {@7}
+ send.dc1 (16|M0) null r4 null 0x10000000 0x120A8000 {@1, $0} // wr:9h+0, rd:0, Media Block Write msc:0, to #0
+ mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud
+ send.ts (16|M0) null r112 null 0x10000000 0x2000010 {EOT, @1} // wr:1+0, rd:0, fc: 0x10
+L176:
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 7fac25b8..ed5e92b8 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -861,7 +861,9 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid)
{
igt_fillfunc_t fill = NULL;
- if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid))
+ if (IS_TIGERLAKE(devid))
+ fill = gen12p1_media_fillfunc;
+ else if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid))
fill = gen9_media_fillfunc;
else if (IS_GEN8(devid))
fill = gen8_media_fillfunc;
diff --git a/lib/media_fill.c b/lib/media_fill.c
index 03b5e71e..1a356cba 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -101,6 +101,20 @@ static const uint32_t gen11_media_vme_kernel[][4] = {
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
};
+static const uint32_t gen12p1_media_kernel[][4] = {
+ { 0x00020061, 0x01050000, 0x00000104, 0x00000000 },
+ { 0x00030061, 0x04050220, 0x00460005, 0x00000000 },
+ { 0x00030061, 0x04050220, 0x00220205, 0x00000000 },
+ { 0x00000061, 0x04454220, 0x00000000, 0x000f000f },
+ { 0x00040461, 0x05050220, 0x00000104, 0x00000000 },
+ { 0x00040561, 0x07050220, 0x00000104, 0x00000000 },
+ { 0x00040661, 0x09050220, 0x00000104, 0x00000000 },
+ { 0x00040761, 0x0b050220, 0x00000104, 0x00000000 },
+ { 0x00049031, 0x00000000, 0xc000044c, 0x12a00000 },
+ { 0x00030061, 0x70050220, 0x00460005, 0x00000000 },
+ { 0x00040131, 0x00000004, 0x7020700c, 0x10000000 },
+};
+
/*
* This sets up the media pipeline,
*
@@ -355,3 +369,14 @@ gen11_media_vme_func(struct intel_batchbuffer *batch,
gen11_media_vme_kernel,
sizeof(gen11_media_vme_kernel));
}
+
+void
+gen12p1_media_fillfunc(struct intel_batchbuffer *batch,
+ const struct igt_buf *dst,
+ unsigned int x, unsigned int y,
+ unsigned int width, unsigned int height,
+ uint8_t color)
+{
+ __gen9_media_fillfunc(batch, dst, x, y, width, height, color,
+ gen12p1_media_kernel, sizeof(gen12p1_media_kernel));
+}
diff --git a/lib/media_fill.h b/lib/media_fill.h
index 1d5c5fa8..a29c4043 100644
--- a/lib/media_fill.h
+++ b/lib/media_fill.h
@@ -55,4 +55,11 @@ gen11_media_vme_func(struct intel_batchbuffer *batch,
unsigned int width, unsigned int height,
const struct igt_buf *dst);
+void
+gen12p1_media_fillfunc(struct intel_batchbuffer *batch,
+ const struct igt_buf *dst,
+ unsigned int x, unsigned int y,
+ unsigned int width, unsigned int height,
+ uint8_t color);
+
#endif /* RENDE_MEDIA_FILL_H */
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [igt-dev] [PATCH 08/10] tests/fb/tgl: Yf tiling does not exist on gen-12
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
` (6 preceding siblings ...)
2019-07-15 21:51 ` [igt-dev] [PATCH 07/10] lib/media_fill/tgl: Implement media_fillfunc " Lucas De Marchi
@ 2019-07-15 21:51 ` Lucas De Marchi
2019-07-19 12:27 ` Ville Syrjälä
2019-07-15 21:51 ` [igt-dev] [PATCH 09/10] tests/kms_plane_multiple/tgl: PCU messaging test Lucas De Marchi
` (2 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-15 21:51 UTC (permalink / raw)
To: igt-dev; +Cc: Dhinakaran Pandiyan
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Fix test to check for addfb failure instead.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
tests/kms_addfb_basic.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index d5dc3eff..20dfd4f2 100644
--- a/tests/kms_addfb_basic.c
+++ b/tests/kms_addfb_basic.c
@@ -527,7 +527,7 @@ static void addfb25_tests(int fd)
gem_close(fd, gem_bo);
}
-static int addfb_expected_ret(int fd)
+static int addfb_expected_ret(int fd, uint64_t modifier)
{
int gen;
@@ -535,6 +535,9 @@ static int addfb_expected_ret(int fd)
return 0;
gen = intel_gen(intel_get_drm_devid(fd));
+
+ if (modifier == LOCAL_I915_FORMAT_MOD_Yf_TILED)
+ return gen >= 9 && gen < 12 ? 0 : -1;
return gen >= 9 ? 0 : -1;
}
@@ -568,8 +571,8 @@ static void addfb25_ytile(int fd)
f.modifier[0] = LOCAL_I915_FORMAT_MOD_Y_TILED;
igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) ==
- addfb_expected_ret(fd));
- if (!addfb_expected_ret(fd))
+ addfb_expected_ret(fd, f.modifier[0]));
+ if (!addfb_expected_ret(fd, f.modifier[0]))
igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, &f.fb_id) == 0);
f.fb_id = 0;
}
@@ -579,8 +582,8 @@ static void addfb25_ytile(int fd)
f.modifier[0] = LOCAL_I915_FORMAT_MOD_Yf_TILED;
igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) ==
- addfb_expected_ret(fd));
- if (!addfb_expected_ret(fd))
+ addfb_expected_ret(fd, f.modifier[0]));
+ if (!addfb_expected_ret(fd, f.modifier[0]))
igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, &f.fb_id) == 0);
f.fb_id = 0;
}
--
2.21.0
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [igt-dev] [PATCH 08/10] tests/fb/tgl: Yf tiling does not exist on gen-12
2019-07-15 21:51 ` [igt-dev] [PATCH 08/10] tests/fb/tgl: Yf tiling does not exist on gen-12 Lucas De Marchi
@ 2019-07-19 12:27 ` Ville Syrjälä
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjälä @ 2019-07-19 12:27 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: igt-dev, Dhinakaran Pandiyan
On Mon, Jul 15, 2019 at 02:51:34PM -0700, Lucas De Marchi wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>
> Fix test to check for addfb failure instead.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> tests/kms_addfb_basic.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
> index d5dc3eff..20dfd4f2 100644
> --- a/tests/kms_addfb_basic.c
> +++ b/tests/kms_addfb_basic.c
> @@ -527,7 +527,7 @@ static void addfb25_tests(int fd)
> gem_close(fd, gem_bo);
> }
>
> -static int addfb_expected_ret(int fd)
> +static int addfb_expected_ret(int fd, uint64_t modifier)
> {
> int gen;
>
> @@ -535,6 +535,9 @@ static int addfb_expected_ret(int fd)
> return 0;
>
> gen = intel_gen(intel_get_drm_devid(fd));
> +
> + if (modifier == LOCAL_I915_FORMAT_MOD_Yf_TILED)
> + return gen >= 9 && gen < 12 ? 0 : -1;
> return gen >= 9 ? 0 : -1;
> }
>
> @@ -568,8 +571,8 @@ static void addfb25_ytile(int fd)
>
> f.modifier[0] = LOCAL_I915_FORMAT_MOD_Y_TILED;
> igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) ==
> - addfb_expected_ret(fd));
> - if (!addfb_expected_ret(fd))
> + addfb_expected_ret(fd, f.modifier[0]));
> + if (!addfb_expected_ret(fd, f.modifier[0]))
> igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, &f.fb_id) == 0);
> f.fb_id = 0;
> }
> @@ -579,8 +582,8 @@ static void addfb25_ytile(int fd)
>
> f.modifier[0] = LOCAL_I915_FORMAT_MOD_Yf_TILED;
> igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) ==
> - addfb_expected_ret(fd));
> - if (!addfb_expected_ret(fd))
> + addfb_expected_ret(fd, f.modifier[0]));
> + if (!addfb_expected_ret(fd, f.modifier[0]))
> igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, &f.fb_id) == 0);
> f.fb_id = 0;
> }
> --
> 2.21.0
--
Ville Syrjälä
Intel
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
* [igt-dev] [PATCH 09/10] tests/kms_plane_multiple/tgl: PCU messaging test
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
` (7 preceding siblings ...)
2019-07-15 21:51 ` [igt-dev] [PATCH 08/10] tests/fb/tgl: Yf tiling does not exist on gen-12 Lucas De Marchi
@ 2019-07-15 21:51 ` Lucas De Marchi
2019-07-19 12:54 ` Ville Syrjälä
2019-08-02 10:43 ` Kahola, Mika
2019-07-15 21:51 ` [igt-dev] [PATCH 10/10] tests/kms_plane_multiple/tgl: Set highest mode for " Lucas De Marchi
2019-07-15 22:42 ` [igt-dev] ✗ Fi.CI.BAT: failure for Add support for Tiger Lake Patchwork
10 siblings, 2 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-15 21:51 UTC (permalink / raw)
To: igt-dev
From: Karthik B S <karthik.b.s@intel.com>
Add a subtest that gives flips which alternate between least bandwidth
requirement and highest bandwidth requirement.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
tests/kms_plane_multiple.c | 178 ++++++++++++++++++++++++++++++-------
1 file changed, 148 insertions(+), 30 deletions(-)
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
index 81ed45dd..2c726fda 100644
--- a/tests/kms_plane_multiple.c
+++ b/tests/kms_plane_multiple.c
@@ -34,6 +34,11 @@ IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes.");
#define SIZE_PLANE 256
#define SIZE_CURSOR 128
+#define SIZE_PLANE_LOW 10
+#define SIZE_PANE 5
+#define SMALL_SCREEN 0
+#define FULL_SCREEN 1
+#define TEST_PCU_ALGO 1
#define LOOP_FOREVER -1
typedef struct {
@@ -48,9 +53,17 @@ typedef struct {
igt_crc_t ref_crc;
igt_pipe_crc_t *pipe_crc;
igt_plane_t **plane;
+ unsigned int flag;
struct igt_fb *fb;
} data_t;
+enum bandwidth {
+ BW_PRIMARY_LOW,
+ BW_PRIMARY_HIGH,
+ BW_PRIMARY_LOW2,
+ BW_HIGH,
+ BW_INVALID,
+};
/* Command line parameters. */
struct {
int iterations;
@@ -97,7 +110,7 @@ static void test_fini(data_t *data, igt_output_t *output, int n_planes)
static void
get_reference_crc(data_t *data, igt_output_t *output, enum pipe pipe,
- color_t *color, uint64_t tiling)
+ color_t *color, uint64_t tiling, int BW)
{
drmModeModeInfo *mode;
igt_plane_t *primary;
@@ -110,7 +123,9 @@ get_reference_crc(data_t *data, igt_output_t *output, enum pipe pipe,
mode = igt_output_get_mode(output);
- igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ igt_create_color_fb(data->drm_fd,
+ BW ? mode->hdisplay : SIZE_PLANE_LOW,
+ BW ? mode->vdisplay : SIZE_PLANE_LOW,
DRM_FORMAT_XRGB8888,
LOCAL_DRM_FORMAT_MOD_NONE,
color->red, color->green, color->blue,
@@ -281,6 +296,76 @@ prepare_planes(data_t *data, enum pipe pipe_id, color_t *color,
* The resulting CRC should be identical to the reference CRC
*/
+static void
+prepare_planes2(data_t *data, enum pipe pipe_id, color_t *color,
+ uint64_t tiling, int max_planes, igt_output_t *output,
+ enum bandwidth bandwidth)
+{
+ drmModeModeInfo *mode;
+ int hsize, vsize;
+ int i;
+ cairo_t *cr;
+
+ igt_output_set_pipe(output, pipe_id);
+ mode = igt_output_get_mode(output);
+
+ switch (bandwidth) {
+ case BW_PRIMARY_LOW:
+ case BW_PRIMARY_LOW2:
+ hsize = SIZE_PLANE_LOW;
+ vsize = SIZE_PLANE_LOW;
+ break;
+ case BW_PRIMARY_HIGH:
+ case BW_HIGH:
+ hsize = mode->hdisplay;
+ vsize = mode->vdisplay;
+ break;
+ default:
+ igt_warn("Invalid BW\n");
+ }
+
+ for (i = 0; i < max_planes; i++) {
+ igt_plane_t *plane = igt_output_get_plane(output, i);
+ uint32_t format = DRM_FORMAT_XRGB8888;
+
+ if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+ format = DRM_FORMAT_ARGB8888;
+ tiling = LOCAL_DRM_FORMAT_MOD_NONE;
+ hsize = SIZE_CURSOR;
+ vsize = SIZE_CURSOR;
+ }
+
+ data->plane[i] = plane;
+ igt_create_color_fb(data->drm_fd,
+ hsize, vsize,
+ format, tiling,
+ color->red, color->green,
+ color->blue,
+ &data->fb[i]);
+ igt_plane_set_position(data->plane[i], 0, 0);
+
+ hsize -= SIZE_PANE;
+
+ /* Create black color holes in all planes other than the cursor
+ * and the topmost plane, so that all planes put together
+ * produces a solid blue screen that matches with
+ * the reference CRC.
+ */
+ if (i < (max_planes - 2) && bandwidth == BW_HIGH) {
+ cr = igt_get_cairo_ctx(data->drm_fd, &data->fb[i]);
+ igt_paint_color(cr, 0, 0, hsize, vsize, 0.0, 0.0, 0.0);
+ igt_put_cairo_ctx(data->drm_fd, &data->fb[i], cr);
+ }
+
+ igt_plane_set_fb(data->plane[i], &data->fb[i]);
+
+ if (bandwidth != BW_HIGH &&
+ plane->type == DRM_PLANE_TYPE_PRIMARY)
+ break;
+
+ }
+}
+
static void
test_plane_position_with_output(data_t *data, enum pipe pipe,
igt_output_t *output, int n_planes,
@@ -306,46 +391,67 @@ test_plane_position_with_output(data_t *data, enum pipe pipe,
test_init(data, pipe, n_planes);
- get_reference_crc(data, output, pipe, &blue, tiling);
+ if (data->flag == TEST_PCU_ALGO) {
+ for (i = BW_PRIMARY_LOW; i < BW_INVALID; i++) {
+ if (i == BW_PRIMARY_LOW || i == BW_PRIMARY_LOW2)
+ get_reference_crc(data, output, pipe, &blue,
+ tiling, SMALL_SCREEN);
+ else
+ get_reference_crc(data, output, pipe, &blue,
+ tiling, FULL_SCREEN);
+
+ /* Find out how many planes are allowed simultaneously */
+ do {
+ c++;
+ prepare_planes(data, pipe, &blue, tiling, c, output);
+ err = igt_display_try_commit2(&data->display, COMMIT_ATOMIC);
- /* Find out how many planes are allowed simultaneously */
- do {
- c++;
- prepare_planes(data, pipe, &blue, tiling, c, output);
- err = igt_display_try_commit2(&data->display, COMMIT_ATOMIC);
+ for_each_plane_on_pipe(&data->display, pipe, plane)
+ igt_plane_set_fb(plane, NULL);
- for_each_plane_on_pipe(&data->display, pipe, plane)
- igt_plane_set_fb(plane, NULL);
+ for (int x = 0; x < c; x++)
+ igt_remove_fb(data->drm_fd, &data->fb[x]);
+ } while (!err && c < n_planes);
- for (int x = 0; x < c; x++)
- igt_remove_fb(data->drm_fd, &data->fb[x]);
- } while (!err && c < n_planes);
+ if (err)
+ c--;
- if (err)
- c--;
+ igt_info("Testing connector %s using pipe %s with %d planes %s with seed %d\n",
+ igt_output_name(output), kmstest_pipe_name(pipe), c,
+ info, opt.seed);
- igt_info("Testing connector %s using pipe %s with %d planes %s with seed %d\n",
- igt_output_name(output), kmstest_pipe_name(pipe), c,
- info, opt.seed);
+ prepare_planes2(data, pipe, &blue, tiling,
+ n_planes, output, i);
+ igt_display_commit2(&data->display, COMMIT_ATOMIC);
- i = 0;
- while (i < iterations || loop_forever) {
- /* randomize planes and set up the holes */
- prepare_planes(data, pipe, &blue, tiling, c, output);
+ igt_pipe_crc_get_current(data->display.drm_fd,
+ data->pipe_crc, &crc);
- igt_display_commit2(&data->display, COMMIT_ATOMIC);
+ igt_assert_crc_equal(&data->ref_crc, &crc);
+ }
+ } else {
+ i = 0;
+ get_reference_crc(data, output, pipe, &blue, tiling, FULL_SCREEN);
+
+ while (i < iterations || loop_forever) {
+ prepare_planes(data, pipe, &blue, tiling,
+ n_planes, output);
- igt_pipe_crc_get_current(data->display.drm_fd, data->pipe_crc, &crc);
+ igt_display_commit2(&data->display, COMMIT_ATOMIC);
- for_each_plane_on_pipe(&data->display, pipe, plane)
- igt_plane_set_fb(plane, NULL);
+ igt_pipe_crc_get_current(data->display.drm_fd,
+ data->pipe_crc, &crc);
- for (int x = 0; x < c; x++)
- igt_remove_fb(data->drm_fd, &data->fb[x]);
+ for_each_plane_on_pipe(&data->display, pipe, plane)
+ igt_plane_set_fb(plane, NULL);
- igt_assert_crc_equal(&data->ref_crc, &crc);
+ for (int x = 0; x < c; x++)
+ igt_remove_fb(data->drm_fd, &data->fb[x]);
- i++;
+ igt_assert_crc_equal(&data->ref_crc, &crc);
+
+ i++;
+ }
}
test_fini(data, output, n_planes);
@@ -355,8 +461,12 @@ static void
test_plane_position(data_t *data, enum pipe pipe, uint64_t tiling)
{
igt_output_t *output;
+ int devid = intel_get_drm_devid(data->drm_fd);
int n_planes = data->display.pipes[pipe].n_planes;
+ if (data->flag == TEST_PCU_ALGO)
+ igt_require(AT_LEAST_GEN(devid, 12));
+
output = igt_get_single_output_for_pipe(&data->display, pipe);
igt_require(output);
@@ -377,6 +487,14 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
igt_require(data->display.pipes[pipe].n_planes > 0);
}
+
+ data->flag = TEST_PCU_ALGO;
+
+ igt_subtest_f("atomic-pipe-%s-tiling-none_pcu", kmstest_pipe_name(pipe))
+ test_plane_position(data, pipe, LOCAL_DRM_FORMAT_MOD_NONE);
+
+ data->flag = 0;
+
igt_subtest_f("atomic-pipe-%s-tiling-x", kmstest_pipe_name(pipe))
test_plane_position(data, pipe, LOCAL_I915_FORMAT_MOD_X_TILED);
--
2.21.0
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [igt-dev] [PATCH 09/10] tests/kms_plane_multiple/tgl: PCU messaging test
2019-07-15 21:51 ` [igt-dev] [PATCH 09/10] tests/kms_plane_multiple/tgl: PCU messaging test Lucas De Marchi
@ 2019-07-19 12:54 ` Ville Syrjälä
2019-07-22 8:37 ` B S, Karthik
2019-08-02 10:43 ` Kahola, Mika
1 sibling, 1 reply; 22+ messages in thread
From: Ville Syrjälä @ 2019-07-19 12:54 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: igt-dev
On Mon, Jul 15, 2019 at 02:51:35PM -0700, Lucas De Marchi wrote:
> From: Karthik B S <karthik.b.s@intel.com>
>
> Add a subtest that gives flips which alternate between least bandwidth
> requirement and highest bandwidth requirement.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> tests/kms_plane_multiple.c | 178 ++++++++++++++++++++++++++++++-------
> 1 file changed, 148 insertions(+), 30 deletions(-)
>
> diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
> index 81ed45dd..2c726fda 100644
> --- a/tests/kms_plane_multiple.c
> +++ b/tests/kms_plane_multiple.c
> @@ -34,6 +34,11 @@ IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes.");
>
> #define SIZE_PLANE 256
> #define SIZE_CURSOR 128
> +#define SIZE_PLANE_LOW 10
> +#define SIZE_PANE 5
> +#define SMALL_SCREEN 0
> +#define FULL_SCREEN 1
> +#define TEST_PCU_ALGO 1
That's way too i915 specific. Such a test should be totally generic.
> #define LOOP_FOREVER -1
>
> typedef struct {
> @@ -48,9 +53,17 @@ typedef struct {
> igt_crc_t ref_crc;
> igt_pipe_crc_t *pipe_crc;
> igt_plane_t **plane;
> + unsigned int flag;
> struct igt_fb *fb;
> } data_t;
>
> +enum bandwidth {
> + BW_PRIMARY_LOW,
> + BW_PRIMARY_HIGH,
> + BW_PRIMARY_LOW2,
> + BW_HIGH,
> + BW_INVALID,
> +};
> /* Command line parameters. */
> struct {
> int iterations;
> @@ -97,7 +110,7 @@ static void test_fini(data_t *data, igt_output_t *output, int n_planes)
>
> static void
> get_reference_crc(data_t *data, igt_output_t *output, enum pipe pipe,
> - color_t *color, uint64_t tiling)
> + color_t *color, uint64_t tiling, int BW)
> {
> drmModeModeInfo *mode;
> igt_plane_t *primary;
> @@ -110,7 +123,9 @@ get_reference_crc(data_t *data, igt_output_t *output, enum pipe pipe,
>
> mode = igt_output_get_mode(output);
>
> - igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> + igt_create_color_fb(data->drm_fd,
> + BW ? mode->hdisplay : SIZE_PLANE_LOW,
> + BW ? mode->vdisplay : SIZE_PLANE_LOW,
> DRM_FORMAT_XRGB8888,
> LOCAL_DRM_FORMAT_MOD_NONE,
> color->red, color->green, color->blue,
> @@ -281,6 +296,76 @@ prepare_planes(data_t *data, enum pipe pipe_id, color_t *color,
> * The resulting CRC should be identical to the reference CRC
> */
>
> +static void
> +prepare_planes2(data_t *data, enum pipe pipe_id, color_t *color,
> + uint64_t tiling, int max_planes, igt_output_t *output,
> + enum bandwidth bandwidth)
> +{
> + drmModeModeInfo *mode;
> + int hsize, vsize;
> + int i;
> + cairo_t *cr;
> +
> + igt_output_set_pipe(output, pipe_id);
> + mode = igt_output_get_mode(output);
> +
> + switch (bandwidth) {
> + case BW_PRIMARY_LOW:
> + case BW_PRIMARY_LOW2:
> + hsize = SIZE_PLANE_LOW;
> + vsize = SIZE_PLANE_LOW;
> + break;
> + case BW_PRIMARY_HIGH:
> + case BW_HIGH:
> + hsize = mode->hdisplay;
> + vsize = mode->vdisplay;
> + break;
> + default:
> + igt_warn("Invalid BW\n");
> + }
> +
> + for (i = 0; i < max_planes; i++) {
> + igt_plane_t *plane = igt_output_get_plane(output, i);
> + uint32_t format = DRM_FORMAT_XRGB8888;
> +
> + if (plane->type == DRM_PLANE_TYPE_CURSOR) {
> + format = DRM_FORMAT_ARGB8888;
> + tiling = LOCAL_DRM_FORMAT_MOD_NONE;
> + hsize = SIZE_CURSOR;
> + vsize = SIZE_CURSOR;
> + }
> +
> + data->plane[i] = plane;
> + igt_create_color_fb(data->drm_fd,
> + hsize, vsize,
> + format, tiling,
> + color->red, color->green,
> + color->blue,
> + &data->fb[i]);
> + igt_plane_set_position(data->plane[i], 0, 0);
> +
> + hsize -= SIZE_PANE;
> +
> + /* Create black color holes in all planes other than the cursor
> + * and the topmost plane, so that all planes put together
> + * produces a solid blue screen that matches with
> + * the reference CRC.
> + */
> + if (i < (max_planes - 2) && bandwidth == BW_HIGH) {
> + cr = igt_get_cairo_ctx(data->drm_fd, &data->fb[i]);
> + igt_paint_color(cr, 0, 0, hsize, vsize, 0.0, 0.0, 0.0);
> + igt_put_cairo_ctx(data->drm_fd, &data->fb[i], cr);
> + }
> +
> + igt_plane_set_fb(data->plane[i], &data->fb[i]);
> +
> + if (bandwidth != BW_HIGH &&
> + plane->type == DRM_PLANE_TYPE_PRIMARY)
> + break;
> +
> + }
> +}
> +
> static void
> test_plane_position_with_output(data_t *data, enum pipe pipe,
> igt_output_t *output, int n_planes,
> @@ -306,46 +391,67 @@ test_plane_position_with_output(data_t *data, enum pipe pipe,
>
> test_init(data, pipe, n_planes);
>
> - get_reference_crc(data, output, pipe, &blue, tiling);
> + if (data->flag == TEST_PCU_ALGO) {
> + for (i = BW_PRIMARY_LOW; i < BW_INVALID; i++) {
> + if (i == BW_PRIMARY_LOW || i == BW_PRIMARY_LOW2)
> + get_reference_crc(data, output, pipe, &blue,
> + tiling, SMALL_SCREEN);
> + else
> + get_reference_crc(data, output, pipe, &blue,
> + tiling, FULL_SCREEN);
> +
> + /* Find out how many planes are allowed simultaneously */
> + do {
> + c++;
> + prepare_planes(data, pipe, &blue, tiling, c, output);
> + err = igt_display_try_commit2(&data->display, COMMIT_ATOMIC);
>
> - /* Find out how many planes are allowed simultaneously */
> - do {
> - c++;
> - prepare_planes(data, pipe, &blue, tiling, c, output);
> - err = igt_display_try_commit2(&data->display, COMMIT_ATOMIC);
> + for_each_plane_on_pipe(&data->display, pipe, plane)
> + igt_plane_set_fb(plane, NULL);
>
> - for_each_plane_on_pipe(&data->display, pipe, plane)
> - igt_plane_set_fb(plane, NULL);
> + for (int x = 0; x < c; x++)
> + igt_remove_fb(data->drm_fd, &data->fb[x]);
> + } while (!err && c < n_planes);
>
> - for (int x = 0; x < c; x++)
> - igt_remove_fb(data->drm_fd, &data->fb[x]);
> - } while (!err && c < n_planes);
> + if (err)
> + c--;
>
> - if (err)
> - c--;
> + igt_info("Testing connector %s using pipe %s with %d planes %s with seed %d\n",
> + igt_output_name(output), kmstest_pipe_name(pipe), c,
> + info, opt.seed);
>
> - igt_info("Testing connector %s using pipe %s with %d planes %s with seed %d\n",
> - igt_output_name(output), kmstest_pipe_name(pipe), c,
> - info, opt.seed);
> + prepare_planes2(data, pipe, &blue, tiling,
> + n_planes, output, i);
> + igt_display_commit2(&data->display, COMMIT_ATOMIC);
>
> - i = 0;
> - while (i < iterations || loop_forever) {
> - /* randomize planes and set up the holes */
> - prepare_planes(data, pipe, &blue, tiling, c, output);
> + igt_pipe_crc_get_current(data->display.drm_fd,
> + data->pipe_crc, &crc);
>
> - igt_display_commit2(&data->display, COMMIT_ATOMIC);
> + igt_assert_crc_equal(&data->ref_crc, &crc);
> + }
> + } else {
> + i = 0;
> + get_reference_crc(data, output, pipe, &blue, tiling, FULL_SCREEN);
> +
> + while (i < iterations || loop_forever) {
> + prepare_planes(data, pipe, &blue, tiling,
> + n_planes, output);
>
> - igt_pipe_crc_get_current(data->display.drm_fd, data->pipe_crc, &crc);
> + igt_display_commit2(&data->display, COMMIT_ATOMIC);
>
> - for_each_plane_on_pipe(&data->display, pipe, plane)
> - igt_plane_set_fb(plane, NULL);
> + igt_pipe_crc_get_current(data->display.drm_fd,
> + data->pipe_crc, &crc);
>
> - for (int x = 0; x < c; x++)
> - igt_remove_fb(data->drm_fd, &data->fb[x]);
> + for_each_plane_on_pipe(&data->display, pipe, plane)
> + igt_plane_set_fb(plane, NULL);
>
> - igt_assert_crc_equal(&data->ref_crc, &crc);
> + for (int x = 0; x < c; x++)
> + igt_remove_fb(data->drm_fd, &data->fb[x]);
>
> - i++;
> + igt_assert_crc_equal(&data->ref_crc, &crc);
> +
> + i++;
> + }
> }
>
> test_fini(data, output, n_planes);
> @@ -355,8 +461,12 @@ static void
> test_plane_position(data_t *data, enum pipe pipe, uint64_t tiling)
> {
> igt_output_t *output;
> + int devid = intel_get_drm_devid(data->drm_fd);
> int n_planes = data->display.pipes[pipe].n_planes;
>
> + if (data->flag == TEST_PCU_ALGO)
> + igt_require(AT_LEAST_GEN(devid, 12));
> +
> output = igt_get_single_output_for_pipe(&data->display, pipe);
> igt_require(output);
>
> @@ -377,6 +487,14 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
> igt_require(data->display.pipes[pipe].n_planes > 0);
> }
>
> +
> + data->flag = TEST_PCU_ALGO;
> +
> + igt_subtest_f("atomic-pipe-%s-tiling-none_pcu", kmstest_pipe_name(pipe))
> + test_plane_position(data, pipe, LOCAL_DRM_FORMAT_MOD_NONE);
> +
> + data->flag = 0;
> +
> igt_subtest_f("atomic-pipe-%s-tiling-x", kmstest_pipe_name(pipe))
> test_plane_position(data, pipe, LOCAL_I915_FORMAT_MOD_X_TILED);
>
> --
> 2.21.0
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
--
Ville Syrjälä
Intel
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [igt-dev] [PATCH 09/10] tests/kms_plane_multiple/tgl: PCU messaging test
2019-07-19 12:54 ` Ville Syrjälä
@ 2019-07-22 8:37 ` B S, Karthik
2019-07-22 16:46 ` Lucas De Marchi
0 siblings, 1 reply; 22+ messages in thread
From: B S, Karthik @ 2019-07-22 8:37 UTC (permalink / raw)
To: Ville Syrjälä, Lucas De Marchi; +Cc: igt-dev
On 7/19/2019 6:24 PM, Ville Syrjälä wrote:
> On Mon, Jul 15, 2019 at 02:51:35PM -0700, Lucas De Marchi wrote:
>> From: Karthik B S <karthik.b.s@intel.com>
>>
>> Add a subtest that gives flips which alternate between least bandwidth
>> requirement and highest bandwidth requirement.
>>
>> Cc: Mika Kahola <mika.kahola@intel.com>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> tests/kms_plane_multiple.c | 178 ++++++++++++++++++++++++++++++-------
>> 1 file changed, 148 insertions(+), 30 deletions(-)
>>
>> diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
>> index 81ed45dd..2c726fda 100644
>> --- a/tests/kms_plane_multiple.c
>> +++ b/tests/kms_plane_multiple.c
>> @@ -34,6 +34,11 @@ IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes.");
>>
>> #define SIZE_PLANE 256
>> #define SIZE_CURSOR 128
>> +#define SIZE_PLANE_LOW 10
>> +#define SIZE_PANE 5
>> +#define SMALL_SCREEN 0
>> +#define FULL_SCREEN 1
>> +#define TEST_PCU_ALGO 1
> That's way too i915 specific. Such a test should be totally generic.
Sure. I'll update TEST_PCU_ALGO to TEST_BANDWIDTH. Would that be fine?
I'll also change the test name from *_pcu to *_bw?
Also to make it more generic, shall I remove the Gen12+ check for this
test, as this test is expected to work on other platforms as well.
>
>> #define LOOP_FOREVER -1
>>
>> typedef struct {
>> @@ -48,9 +53,17 @@ typedef struct {
>> igt_crc_t ref_crc;
>> igt_pipe_crc_t *pipe_crc;
>> igt_plane_t **plane;
>> + unsigned int flag;
>> struct igt_fb *fb;
>> } data_t;
>>
>> +enum bandwidth {
>> + BW_PRIMARY_LOW,
>> + BW_PRIMARY_HIGH,
>> + BW_PRIMARY_LOW2,
>> + BW_HIGH,
>> + BW_INVALID,
>> +};
>> /* Command line parameters. */
>> struct {
>> int iterations;
>> @@ -97,7 +110,7 @@ static void test_fini(data_t *data, igt_output_t *output, int n_planes)
>>
>> static void
>> get_reference_crc(data_t *data, igt_output_t *output, enum pipe pipe,
>> - color_t *color, uint64_t tiling)
>> + color_t *color, uint64_t tiling, int BW)
>> {
>> drmModeModeInfo *mode;
>> igt_plane_t *primary;
>> @@ -110,7 +123,9 @@ get_reference_crc(data_t *data, igt_output_t *output, enum pipe pipe,
>>
>> mode = igt_output_get_mode(output);
>>
>> - igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
>> + igt_create_color_fb(data->drm_fd,
>> + BW ? mode->hdisplay : SIZE_PLANE_LOW,
>> + BW ? mode->vdisplay : SIZE_PLANE_LOW,
>> DRM_FORMAT_XRGB8888,
>> LOCAL_DRM_FORMAT_MOD_NONE,
>> color->red, color->green, color->blue,
>> @@ -281,6 +296,76 @@ prepare_planes(data_t *data, enum pipe pipe_id, color_t *color,
>> * The resulting CRC should be identical to the reference CRC
>> */
>>
>> +static void
>> +prepare_planes2(data_t *data, enum pipe pipe_id, color_t *color,
>> + uint64_t tiling, int max_planes, igt_output_t *output,
>> + enum bandwidth bandwidth)
>> +{
>> + drmModeModeInfo *mode;
>> + int hsize, vsize;
>> + int i;
>> + cairo_t *cr;
>> +
>> + igt_output_set_pipe(output, pipe_id);
>> + mode = igt_output_get_mode(output);
>> +
>> + switch (bandwidth) {
>> + case BW_PRIMARY_LOW:
>> + case BW_PRIMARY_LOW2:
>> + hsize = SIZE_PLANE_LOW;
>> + vsize = SIZE_PLANE_LOW;
>> + break;
>> + case BW_PRIMARY_HIGH:
>> + case BW_HIGH:
>> + hsize = mode->hdisplay;
>> + vsize = mode->vdisplay;
>> + break;
>> + default:
>> + igt_warn("Invalid BW\n");
>> + }
>> +
>> + for (i = 0; i < max_planes; i++) {
>> + igt_plane_t *plane = igt_output_get_plane(output, i);
>> + uint32_t format = DRM_FORMAT_XRGB8888;
>> +
>> + if (plane->type == DRM_PLANE_TYPE_CURSOR) {
>> + format = DRM_FORMAT_ARGB8888;
>> + tiling = LOCAL_DRM_FORMAT_MOD_NONE;
>> + hsize = SIZE_CURSOR;
>> + vsize = SIZE_CURSOR;
>> + }
>> +
>> + data->plane[i] = plane;
>> + igt_create_color_fb(data->drm_fd,
>> + hsize, vsize,
>> + format, tiling,
>> + color->red, color->green,
>> + color->blue,
>> + &data->fb[i]);
>> + igt_plane_set_position(data->plane[i], 0, 0);
>> +
>> + hsize -= SIZE_PANE;
>> +
>> + /* Create black color holes in all planes other than the cursor
>> + * and the topmost plane, so that all planes put together
>> + * produces a solid blue screen that matches with
>> + * the reference CRC.
>> + */
>> + if (i < (max_planes - 2) && bandwidth == BW_HIGH) {
>> + cr = igt_get_cairo_ctx(data->drm_fd, &data->fb[i]);
>> + igt_paint_color(cr, 0, 0, hsize, vsize, 0.0, 0.0, 0.0);
>> + igt_put_cairo_ctx(data->drm_fd, &data->fb[i], cr);
>> + }
>> +
>> + igt_plane_set_fb(data->plane[i], &data->fb[i]);
>> +
>> + if (bandwidth != BW_HIGH &&
>> + plane->type == DRM_PLANE_TYPE_PRIMARY)
>> + break;
>> +
>> + }
>> +}
>> +
>> static void
>> test_plane_position_with_output(data_t *data, enum pipe pipe,
>> igt_output_t *output, int n_planes,
>> @@ -306,46 +391,67 @@ test_plane_position_with_output(data_t *data, enum pipe pipe,
>>
>> test_init(data, pipe, n_planes);
>>
>> - get_reference_crc(data, output, pipe, &blue, tiling);
>> + if (data->flag == TEST_PCU_ALGO) {
>> + for (i = BW_PRIMARY_LOW; i < BW_INVALID; i++) {
>> + if (i == BW_PRIMARY_LOW || i == BW_PRIMARY_LOW2)
>> + get_reference_crc(data, output, pipe, &blue,
>> + tiling, SMALL_SCREEN);
>> + else
>> + get_reference_crc(data, output, pipe, &blue,
>> + tiling, FULL_SCREEN);
>> +
>> + /* Find out how many planes are allowed simultaneously */
>> + do {
>> + c++;
>> + prepare_planes(data, pipe, &blue, tiling, c, output);
>> + err = igt_display_try_commit2(&data->display, COMMIT_ATOMIC);
>>
>> - /* Find out how many planes are allowed simultaneously */
>> - do {
>> - c++;
>> - prepare_planes(data, pipe, &blue, tiling, c, output);
>> - err = igt_display_try_commit2(&data->display, COMMIT_ATOMIC);
>> + for_each_plane_on_pipe(&data->display, pipe, plane)
>> + igt_plane_set_fb(plane, NULL);
>>
>> - for_each_plane_on_pipe(&data->display, pipe, plane)
>> - igt_plane_set_fb(plane, NULL);
>> + for (int x = 0; x < c; x++)
>> + igt_remove_fb(data->drm_fd, &data->fb[x]);
>> + } while (!err && c < n_planes);
>>
>> - for (int x = 0; x < c; x++)
>> - igt_remove_fb(data->drm_fd, &data->fb[x]);
>> - } while (!err && c < n_planes);
>> + if (err)
>> + c--;
>>
>> - if (err)
>> - c--;
>> + igt_info("Testing connector %s using pipe %s with %d planes %s with seed %d\n",
>> + igt_output_name(output), kmstest_pipe_name(pipe), c,
>> + info, opt.seed);
>>
>> - igt_info("Testing connector %s using pipe %s with %d planes %s with seed %d\n",
>> - igt_output_name(output), kmstest_pipe_name(pipe), c,
>> - info, opt.seed);
>> + prepare_planes2(data, pipe, &blue, tiling,
>> + n_planes, output, i);
>> + igt_display_commit2(&data->display, COMMIT_ATOMIC);
>>
>> - i = 0;
>> - while (i < iterations || loop_forever) {
>> - /* randomize planes and set up the holes */
>> - prepare_planes(data, pipe, &blue, tiling, c, output);
>> + igt_pipe_crc_get_current(data->display.drm_fd,
>> + data->pipe_crc, &crc);
>>
>> - igt_display_commit2(&data->display, COMMIT_ATOMIC);
>> + igt_assert_crc_equal(&data->ref_crc, &crc);
>> + }
>> + } else {
>> + i = 0;
>> + get_reference_crc(data, output, pipe, &blue, tiling, FULL_SCREEN);
>> +
>> + while (i < iterations || loop_forever) {
>> + prepare_planes(data, pipe, &blue, tiling,
>> + n_planes, output);
>>
>> - igt_pipe_crc_get_current(data->display.drm_fd, data->pipe_crc, &crc);
>> + igt_display_commit2(&data->display, COMMIT_ATOMIC);
>>
>> - for_each_plane_on_pipe(&data->display, pipe, plane)
>> - igt_plane_set_fb(plane, NULL);
>> + igt_pipe_crc_get_current(data->display.drm_fd,
>> + data->pipe_crc, &crc);
>>
>> - for (int x = 0; x < c; x++)
>> - igt_remove_fb(data->drm_fd, &data->fb[x]);
>> + for_each_plane_on_pipe(&data->display, pipe, plane)
>> + igt_plane_set_fb(plane, NULL);
>>
>> - igt_assert_crc_equal(&data->ref_crc, &crc);
>> + for (int x = 0; x < c; x++)
>> + igt_remove_fb(data->drm_fd, &data->fb[x]);
>>
>> - i++;
>> + igt_assert_crc_equal(&data->ref_crc, &crc);
>> +
>> + i++;
>> + }
>> }
>>
>> test_fini(data, output, n_planes);
>> @@ -355,8 +461,12 @@ static void
>> test_plane_position(data_t *data, enum pipe pipe, uint64_t tiling)
>> {
>> igt_output_t *output;
>> + int devid = intel_get_drm_devid(data->drm_fd);
>> int n_planes = data->display.pipes[pipe].n_planes;
>>
>> + if (data->flag == TEST_PCU_ALGO)
>> + igt_require(AT_LEAST_GEN(devid, 12));
>> +
>> output = igt_get_single_output_for_pipe(&data->display, pipe);
>> igt_require(output);
>>
>> @@ -377,6 +487,14 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
>> igt_require(data->display.pipes[pipe].n_planes > 0);
>> }
>>
>> +
>> + data->flag = TEST_PCU_ALGO;
>> +
>> + igt_subtest_f("atomic-pipe-%s-tiling-none_pcu", kmstest_pipe_name(pipe))
>> + test_plane_position(data, pipe, LOCAL_DRM_FORMAT_MOD_NONE);
>> +
>> + data->flag = 0;
>> +
>> igt_subtest_f("atomic-pipe-%s-tiling-x", kmstest_pipe_name(pipe))
>> test_plane_position(data, pipe, LOCAL_I915_FORMAT_MOD_X_TILED);
>>
>> --
>> 2.21.0
>>
>> _______________________________________________
>> igt-dev mailing list
>> igt-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [igt-dev] [PATCH 09/10] tests/kms_plane_multiple/tgl: PCU messaging test
2019-07-22 8:37 ` B S, Karthik
@ 2019-07-22 16:46 ` Lucas De Marchi
2019-07-23 2:44 ` B S, Karthik
0 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-22 16:46 UTC (permalink / raw)
To: B S, Karthik; +Cc: igt-dev
On Mon, Jul 22, 2019 at 02:07:36PM +0530, Karthik B S wrote:
>
>On 7/19/2019 6:24 PM, Ville Syrjälä wrote:
>>On Mon, Jul 15, 2019 at 02:51:35PM -0700, Lucas De Marchi wrote:
>>>From: Karthik B S <karthik.b.s@intel.com>
>>>
>>>Add a subtest that gives flips which alternate between least bandwidth
>>>requirement and highest bandwidth requirement.
>>>
>>>Cc: Mika Kahola <mika.kahola@intel.com>
>>>Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>---
>>> tests/kms_plane_multiple.c | 178 ++++++++++++++++++++++++++++++-------
>>> 1 file changed, 148 insertions(+), 30 deletions(-)
>>>
>>>diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
>>>index 81ed45dd..2c726fda 100644
>>>--- a/tests/kms_plane_multiple.c
>>>+++ b/tests/kms_plane_multiple.c
>>>@@ -34,6 +34,11 @@ IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes.");
>>> #define SIZE_PLANE 256
>>> #define SIZE_CURSOR 128
>>>+#define SIZE_PLANE_LOW 10
>>>+#define SIZE_PANE 5
>>>+#define SMALL_SCREEN 0
>>>+#define FULL_SCREEN 1
>>>+#define TEST_PCU_ALGO 1
>>That's way too i915 specific. Such a test should be totally generic.
>Sure. I'll update TEST_PCU_ALGO to TEST_BANDWIDTH. Would that be fine?
>I'll also change the test name from *_pcu to *_bw?
>
>Also to make it more generic, shall I remove the Gen12+ check for this
>test, as this test is expected to work on other platforms as well.
Karthik, I'll remove this patch from my series and let you handle the
comments and send an updated version, ok?
Lucas De Marchi
>>
>>> #define LOOP_FOREVER -1
>>> typedef struct {
>>>@@ -48,9 +53,17 @@ typedef struct {
>>> igt_crc_t ref_crc;
>>> igt_pipe_crc_t *pipe_crc;
>>> igt_plane_t **plane;
>>>+ unsigned int flag;
>>> struct igt_fb *fb;
>>> } data_t;
>>>+enum bandwidth {
>>>+ BW_PRIMARY_LOW,
>>>+ BW_PRIMARY_HIGH,
>>>+ BW_PRIMARY_LOW2,
>>>+ BW_HIGH,
>>>+ BW_INVALID,
>>>+};
>>> /* Command line parameters. */
>>> struct {
>>> int iterations;
>>>@@ -97,7 +110,7 @@ static void test_fini(data_t *data, igt_output_t *output, int n_planes)
>>> static void
>>> get_reference_crc(data_t *data, igt_output_t *output, enum pipe pipe,
>>>- color_t *color, uint64_t tiling)
>>>+ color_t *color, uint64_t tiling, int BW)
>>> {
>>> drmModeModeInfo *mode;
>>> igt_plane_t *primary;
>>>@@ -110,7 +123,9 @@ get_reference_crc(data_t *data, igt_output_t *output, enum pipe pipe,
>>> mode = igt_output_get_mode(output);
>>>- igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
>>>+ igt_create_color_fb(data->drm_fd,
>>>+ BW ? mode->hdisplay : SIZE_PLANE_LOW,
>>>+ BW ? mode->vdisplay : SIZE_PLANE_LOW,
>>> DRM_FORMAT_XRGB8888,
>>> LOCAL_DRM_FORMAT_MOD_NONE,
>>> color->red, color->green, color->blue,
>>>@@ -281,6 +296,76 @@ prepare_planes(data_t *data, enum pipe pipe_id, color_t *color,
>>> * The resulting CRC should be identical to the reference CRC
>>> */
>>>+static void
>>>+prepare_planes2(data_t *data, enum pipe pipe_id, color_t *color,
>>>+ uint64_t tiling, int max_planes, igt_output_t *output,
>>>+ enum bandwidth bandwidth)
>>>+{
>>>+ drmModeModeInfo *mode;
>>>+ int hsize, vsize;
>>>+ int i;
>>>+ cairo_t *cr;
>>>+
>>>+ igt_output_set_pipe(output, pipe_id);
>>>+ mode = igt_output_get_mode(output);
>>>+
>>>+ switch (bandwidth) {
>>>+ case BW_PRIMARY_LOW:
>>>+ case BW_PRIMARY_LOW2:
>>>+ hsize = SIZE_PLANE_LOW;
>>>+ vsize = SIZE_PLANE_LOW;
>>>+ break;
>>>+ case BW_PRIMARY_HIGH:
>>>+ case BW_HIGH:
>>>+ hsize = mode->hdisplay;
>>>+ vsize = mode->vdisplay;
>>>+ break;
>>>+ default:
>>>+ igt_warn("Invalid BW\n");
>>>+ }
>>>+
>>>+ for (i = 0; i < max_planes; i++) {
>>>+ igt_plane_t *plane = igt_output_get_plane(output, i);
>>>+ uint32_t format = DRM_FORMAT_XRGB8888;
>>>+
>>>+ if (plane->type == DRM_PLANE_TYPE_CURSOR) {
>>>+ format = DRM_FORMAT_ARGB8888;
>>>+ tiling = LOCAL_DRM_FORMAT_MOD_NONE;
>>>+ hsize = SIZE_CURSOR;
>>>+ vsize = SIZE_CURSOR;
>>>+ }
>>>+
>>>+ data->plane[i] = plane;
>>>+ igt_create_color_fb(data->drm_fd,
>>>+ hsize, vsize,
>>>+ format, tiling,
>>>+ color->red, color->green,
>>>+ color->blue,
>>>+ &data->fb[i]);
>>>+ igt_plane_set_position(data->plane[i], 0, 0);
>>>+
>>>+ hsize -= SIZE_PANE;
>>>+
>>>+ /* Create black color holes in all planes other than the cursor
>>>+ * and the topmost plane, so that all planes put together
>>>+ * produces a solid blue screen that matches with
>>>+ * the reference CRC.
>>>+ */
>>>+ if (i < (max_planes - 2) && bandwidth == BW_HIGH) {
>>>+ cr = igt_get_cairo_ctx(data->drm_fd, &data->fb[i]);
>>>+ igt_paint_color(cr, 0, 0, hsize, vsize, 0.0, 0.0, 0.0);
>>>+ igt_put_cairo_ctx(data->drm_fd, &data->fb[i], cr);
>>>+ }
>>>+
>>>+ igt_plane_set_fb(data->plane[i], &data->fb[i]);
>>>+
>>>+ if (bandwidth != BW_HIGH &&
>>>+ plane->type == DRM_PLANE_TYPE_PRIMARY)
>>>+ break;
>>>+
>>>+ }
>>>+}
>>>+
>>> static void
>>> test_plane_position_with_output(data_t *data, enum pipe pipe,
>>> igt_output_t *output, int n_planes,
>>>@@ -306,46 +391,67 @@ test_plane_position_with_output(data_t *data, enum pipe pipe,
>>> test_init(data, pipe, n_planes);
>>>- get_reference_crc(data, output, pipe, &blue, tiling);
>>>+ if (data->flag == TEST_PCU_ALGO) {
>>>+ for (i = BW_PRIMARY_LOW; i < BW_INVALID; i++) {
>>>+ if (i == BW_PRIMARY_LOW || i == BW_PRIMARY_LOW2)
>>>+ get_reference_crc(data, output, pipe, &blue,
>>>+ tiling, SMALL_SCREEN);
>>>+ else
>>>+ get_reference_crc(data, output, pipe, &blue,
>>>+ tiling, FULL_SCREEN);
>>>+
>>>+ /* Find out how many planes are allowed simultaneously */
>>>+ do {
>>>+ c++;
>>>+ prepare_planes(data, pipe, &blue, tiling, c, output);
>>>+ err = igt_display_try_commit2(&data->display, COMMIT_ATOMIC);
>>>- /* Find out how many planes are allowed simultaneously */
>>>- do {
>>>- c++;
>>>- prepare_planes(data, pipe, &blue, tiling, c, output);
>>>- err = igt_display_try_commit2(&data->display, COMMIT_ATOMIC);
>>>+ for_each_plane_on_pipe(&data->display, pipe, plane)
>>>+ igt_plane_set_fb(plane, NULL);
>>>- for_each_plane_on_pipe(&data->display, pipe, plane)
>>>- igt_plane_set_fb(plane, NULL);
>>>+ for (int x = 0; x < c; x++)
>>>+ igt_remove_fb(data->drm_fd, &data->fb[x]);
>>>+ } while (!err && c < n_planes);
>>>- for (int x = 0; x < c; x++)
>>>- igt_remove_fb(data->drm_fd, &data->fb[x]);
>>>- } while (!err && c < n_planes);
>>>+ if (err)
>>>+ c--;
>>>- if (err)
>>>- c--;
>>>+ igt_info("Testing connector %s using pipe %s with %d planes %s with seed %d\n",
>>>+ igt_output_name(output), kmstest_pipe_name(pipe), c,
>>>+ info, opt.seed);
>>>- igt_info("Testing connector %s using pipe %s with %d planes %s with seed %d\n",
>>>- igt_output_name(output), kmstest_pipe_name(pipe), c,
>>>- info, opt.seed);
>>>+ prepare_planes2(data, pipe, &blue, tiling,
>>>+ n_planes, output, i);
>>>+ igt_display_commit2(&data->display, COMMIT_ATOMIC);
>>>- i = 0;
>>>- while (i < iterations || loop_forever) {
>>>- /* randomize planes and set up the holes */
>>>- prepare_planes(data, pipe, &blue, tiling, c, output);
>>>+ igt_pipe_crc_get_current(data->display.drm_fd,
>>>+ data->pipe_crc, &crc);
>>>- igt_display_commit2(&data->display, COMMIT_ATOMIC);
>>>+ igt_assert_crc_equal(&data->ref_crc, &crc);
>>>+ }
>>>+ } else {
>>>+ i = 0;
>>>+ get_reference_crc(data, output, pipe, &blue, tiling, FULL_SCREEN);
>>>+
>>>+ while (i < iterations || loop_forever) {
>>>+ prepare_planes(data, pipe, &blue, tiling,
>>>+ n_planes, output);
>>>- igt_pipe_crc_get_current(data->display.drm_fd, data->pipe_crc, &crc);
>>>+ igt_display_commit2(&data->display, COMMIT_ATOMIC);
>>>- for_each_plane_on_pipe(&data->display, pipe, plane)
>>>- igt_plane_set_fb(plane, NULL);
>>>+ igt_pipe_crc_get_current(data->display.drm_fd,
>>>+ data->pipe_crc, &crc);
>>>- for (int x = 0; x < c; x++)
>>>- igt_remove_fb(data->drm_fd, &data->fb[x]);
>>>+ for_each_plane_on_pipe(&data->display, pipe, plane)
>>>+ igt_plane_set_fb(plane, NULL);
>>>- igt_assert_crc_equal(&data->ref_crc, &crc);
>>>+ for (int x = 0; x < c; x++)
>>>+ igt_remove_fb(data->drm_fd, &data->fb[x]);
>>>- i++;
>>>+ igt_assert_crc_equal(&data->ref_crc, &crc);
>>>+
>>>+ i++;
>>>+ }
>>> }
>>> test_fini(data, output, n_planes);
>>>@@ -355,8 +461,12 @@ static void
>>> test_plane_position(data_t *data, enum pipe pipe, uint64_t tiling)
>>> {
>>> igt_output_t *output;
>>>+ int devid = intel_get_drm_devid(data->drm_fd);
>>> int n_planes = data->display.pipes[pipe].n_planes;
>>>+ if (data->flag == TEST_PCU_ALGO)
>>>+ igt_require(AT_LEAST_GEN(devid, 12));
>>>+
>>> output = igt_get_single_output_for_pipe(&data->display, pipe);
>>> igt_require(output);
>>>@@ -377,6 +487,14 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
>>> igt_require(data->display.pipes[pipe].n_planes > 0);
>>> }
>>>+
>>>+ data->flag = TEST_PCU_ALGO;
>>>+
>>>+ igt_subtest_f("atomic-pipe-%s-tiling-none_pcu", kmstest_pipe_name(pipe))
>>>+ test_plane_position(data, pipe, LOCAL_DRM_FORMAT_MOD_NONE);
>>>+
>>>+ data->flag = 0;
>>>+
>>> igt_subtest_f("atomic-pipe-%s-tiling-x", kmstest_pipe_name(pipe))
>>> test_plane_position(data, pipe, LOCAL_I915_FORMAT_MOD_X_TILED);
>>>--
>>>2.21.0
>>>
>>>_______________________________________________
>>>igt-dev mailing list
>>>igt-dev@lists.freedesktop.org
>>>https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [igt-dev] [PATCH 09/10] tests/kms_plane_multiple/tgl: PCU messaging test
2019-07-22 16:46 ` Lucas De Marchi
@ 2019-07-23 2:44 ` B S, Karthik
0 siblings, 0 replies; 22+ messages in thread
From: B S, Karthik @ 2019-07-23 2:44 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: igt-dev
On 7/22/2019 10:16 PM, Lucas De Marchi wrote:
> On Mon, Jul 22, 2019 at 02:07:36PM +0530, Karthik B S wrote:
>>
>> On 7/19/2019 6:24 PM, Ville Syrjälä wrote:
>>> On Mon, Jul 15, 2019 at 02:51:35PM -0700, Lucas De Marchi wrote:
>>>> From: Karthik B S <karthik.b.s@intel.com>
>>>>
>>>> Add a subtest that gives flips which alternate between least bandwidth
>>>> requirement and highest bandwidth requirement.
>>>>
>>>> Cc: Mika Kahola <mika.kahola@intel.com>
>>>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>> ---
>>>> tests/kms_plane_multiple.c | 178
>>>> ++++++++++++++++++++++++++++++-------
>>>> 1 file changed, 148 insertions(+), 30 deletions(-)
>>>>
>>>> diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
>>>> index 81ed45dd..2c726fda 100644
>>>> --- a/tests/kms_plane_multiple.c
>>>> +++ b/tests/kms_plane_multiple.c
>>>> @@ -34,6 +34,11 @@ IGT_TEST_DESCRIPTION("Test atomic mode setting
>>>> with multiple planes.");
>>>> #define SIZE_PLANE 256
>>>> #define SIZE_CURSOR 128
>>>> +#define SIZE_PLANE_LOW 10
>>>> +#define SIZE_PANE 5
>>>> +#define SMALL_SCREEN 0
>>>> +#define FULL_SCREEN 1
>>>> +#define TEST_PCU_ALGO 1
>>> That's way too i915 specific. Such a test should be totally generic.
>> Sure. I'll update TEST_PCU_ALGO to TEST_BANDWIDTH. Would that be
>> fine? I'll also change the test name from *_pcu to *_bw?
>>
>> Also to make it more generic, shall I remove the Gen12+ check for
>> this test, as this test is expected to work on other platforms as well.
>
> Karthik, I'll remove this patch from my series and let you handle the
> comments and send an updated version, ok?
Sure. I'll do it.
Karthik B S
>
> Lucas De Marchi
>
>>>
>>>> #define LOOP_FOREVER -1
>>>> typedef struct {
>>>> @@ -48,9 +53,17 @@ typedef struct {
>>>> igt_crc_t ref_crc;
>>>> igt_pipe_crc_t *pipe_crc;
>>>> igt_plane_t **plane;
>>>> + unsigned int flag;
>>>> struct igt_fb *fb;
>>>> } data_t;
>>>> +enum bandwidth {
>>>> + BW_PRIMARY_LOW,
>>>> + BW_PRIMARY_HIGH,
>>>> + BW_PRIMARY_LOW2,
>>>> + BW_HIGH,
>>>> + BW_INVALID,
>>>> +};
>>>> /* Command line parameters. */
>>>> struct {
>>>> int iterations;
>>>> @@ -97,7 +110,7 @@ static void test_fini(data_t *data, igt_output_t
>>>> *output, int n_planes)
>>>> static void
>>>> get_reference_crc(data_t *data, igt_output_t *output, enum pipe pipe,
>>>> - color_t *color, uint64_t tiling)
>>>> + color_t *color, uint64_t tiling, int BW)
>>>> {
>>>> drmModeModeInfo *mode;
>>>> igt_plane_t *primary;
>>>> @@ -110,7 +123,9 @@ get_reference_crc(data_t *data, igt_output_t
>>>> *output, enum pipe pipe,
>>>> mode = igt_output_get_mode(output);
>>>> - igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
>>>> + igt_create_color_fb(data->drm_fd,
>>>> + BW ? mode->hdisplay : SIZE_PLANE_LOW,
>>>> + BW ? mode->vdisplay : SIZE_PLANE_LOW,
>>>> DRM_FORMAT_XRGB8888,
>>>> LOCAL_DRM_FORMAT_MOD_NONE,
>>>> color->red, color->green, color->blue,
>>>> @@ -281,6 +296,76 @@ prepare_planes(data_t *data, enum pipe
>>>> pipe_id, color_t *color,
>>>> * The resulting CRC should be identical to the reference CRC
>>>> */
>>>> +static void
>>>> +prepare_planes2(data_t *data, enum pipe pipe_id, color_t *color,
>>>> + uint64_t tiling, int max_planes, igt_output_t *output,
>>>> + enum bandwidth bandwidth)
>>>> +{
>>>> + drmModeModeInfo *mode;
>>>> + int hsize, vsize;
>>>> + int i;
>>>> + cairo_t *cr;
>>>> +
>>>> + igt_output_set_pipe(output, pipe_id);
>>>> + mode = igt_output_get_mode(output);
>>>> +
>>>> + switch (bandwidth) {
>>>> + case BW_PRIMARY_LOW:
>>>> + case BW_PRIMARY_LOW2:
>>>> + hsize = SIZE_PLANE_LOW;
>>>> + vsize = SIZE_PLANE_LOW;
>>>> + break;
>>>> + case BW_PRIMARY_HIGH:
>>>> + case BW_HIGH:
>>>> + hsize = mode->hdisplay;
>>>> + vsize = mode->vdisplay;
>>>> + break;
>>>> + default:
>>>> + igt_warn("Invalid BW\n");
>>>> + }
>>>> +
>>>> + for (i = 0; i < max_planes; i++) {
>>>> + igt_plane_t *plane = igt_output_get_plane(output, i);
>>>> + uint32_t format = DRM_FORMAT_XRGB8888;
>>>> +
>>>> + if (plane->type == DRM_PLANE_TYPE_CURSOR) {
>>>> + format = DRM_FORMAT_ARGB8888;
>>>> + tiling = LOCAL_DRM_FORMAT_MOD_NONE;
>>>> + hsize = SIZE_CURSOR;
>>>> + vsize = SIZE_CURSOR;
>>>> + }
>>>> +
>>>> + data->plane[i] = plane;
>>>> + igt_create_color_fb(data->drm_fd,
>>>> + hsize, vsize,
>>>> + format, tiling,
>>>> + color->red, color->green,
>>>> + color->blue,
>>>> + &data->fb[i]);
>>>> + igt_plane_set_position(data->plane[i], 0, 0);
>>>> +
>>>> + hsize -= SIZE_PANE;
>>>> +
>>>> + /* Create black color holes in all planes other than the
>>>> cursor
>>>> + * and the topmost plane, so that all planes put together
>>>> + * produces a solid blue screen that matches with
>>>> + * the reference CRC.
>>>> + */
>>>> + if (i < (max_planes - 2) && bandwidth == BW_HIGH) {
>>>> + cr = igt_get_cairo_ctx(data->drm_fd, &data->fb[i]);
>>>> + igt_paint_color(cr, 0, 0, hsize, vsize, 0.0, 0.0, 0.0);
>>>> + igt_put_cairo_ctx(data->drm_fd, &data->fb[i], cr);
>>>> + }
>>>> +
>>>> + igt_plane_set_fb(data->plane[i], &data->fb[i]);
>>>> +
>>>> + if (bandwidth != BW_HIGH &&
>>>> + plane->type == DRM_PLANE_TYPE_PRIMARY)
>>>> + break;
>>>> +
>>>> + }
>>>> +}
>>>> +
>>>> static void
>>>> test_plane_position_with_output(data_t *data, enum pipe pipe,
>>>> igt_output_t *output, int n_planes,
>>>> @@ -306,46 +391,67 @@ test_plane_position_with_output(data_t *data,
>>>> enum pipe pipe,
>>>> test_init(data, pipe, n_planes);
>>>> - get_reference_crc(data, output, pipe, &blue, tiling);
>>>> + if (data->flag == TEST_PCU_ALGO) {
>>>> + for (i = BW_PRIMARY_LOW; i < BW_INVALID; i++) {
>>>> + if (i == BW_PRIMARY_LOW || i == BW_PRIMARY_LOW2)
>>>> + get_reference_crc(data, output, pipe, &blue,
>>>> + tiling, SMALL_SCREEN);
>>>> + else
>>>> + get_reference_crc(data, output, pipe, &blue,
>>>> + tiling, FULL_SCREEN);
>>>> +
>>>> + /* Find out how many planes are allowed simultaneously */
>>>> + do {
>>>> + c++;
>>>> + prepare_planes(data, pipe, &blue, tiling, c, output);
>>>> + err = igt_display_try_commit2(&data->display,
>>>> COMMIT_ATOMIC);
>>>> - /* Find out how many planes are allowed simultaneously */
>>>> - do {
>>>> - c++;
>>>> - prepare_planes(data, pipe, &blue, tiling, c, output);
>>>> - err = igt_display_try_commit2(&data->display, COMMIT_ATOMIC);
>>>> + for_each_plane_on_pipe(&data->display, pipe, plane)
>>>> + igt_plane_set_fb(plane, NULL);
>>>> - for_each_plane_on_pipe(&data->display, pipe, plane)
>>>> - igt_plane_set_fb(plane, NULL);
>>>> + for (int x = 0; x < c; x++)
>>>> + igt_remove_fb(data->drm_fd, &data->fb[x]);
>>>> + } while (!err && c < n_planes);
>>>> - for (int x = 0; x < c; x++)
>>>> - igt_remove_fb(data->drm_fd, &data->fb[x]);
>>>> - } while (!err && c < n_planes);
>>>> + if (err)
>>>> + c--;
>>>> - if (err)
>>>> - c--;
>>>> + igt_info("Testing connector %s using pipe %s with %d
>>>> planes %s with seed %d\n",
>>>> + igt_output_name(output),
>>>> kmstest_pipe_name(pipe), c,
>>>> + info, opt.seed);
>>>> - igt_info("Testing connector %s using pipe %s with %d planes %s
>>>> with seed %d\n",
>>>> - igt_output_name(output), kmstest_pipe_name(pipe), c,
>>>> - info, opt.seed);
>>>> + prepare_planes2(data, pipe, &blue, tiling,
>>>> + n_planes, output, i);
>>>> + igt_display_commit2(&data->display, COMMIT_ATOMIC);
>>>> - i = 0;
>>>> - while (i < iterations || loop_forever) {
>>>> - /* randomize planes and set up the holes */
>>>> - prepare_planes(data, pipe, &blue, tiling, c, output);
>>>> + igt_pipe_crc_get_current(data->display.drm_fd,
>>>> + data->pipe_crc, &crc);
>>>> - igt_display_commit2(&data->display, COMMIT_ATOMIC);
>>>> + igt_assert_crc_equal(&data->ref_crc, &crc);
>>>> + }
>>>> + } else {
>>>> + i = 0;
>>>> + get_reference_crc(data, output, pipe, &blue, tiling,
>>>> FULL_SCREEN);
>>>> +
>>>> + while (i < iterations || loop_forever) {
>>>> + prepare_planes(data, pipe, &blue, tiling,
>>>> + n_planes, output);
>>>> - igt_pipe_crc_get_current(data->display.drm_fd,
>>>> data->pipe_crc, &crc);
>>>> + igt_display_commit2(&data->display, COMMIT_ATOMIC);
>>>> - for_each_plane_on_pipe(&data->display, pipe, plane)
>>>> - igt_plane_set_fb(plane, NULL);
>>>> + igt_pipe_crc_get_current(data->display.drm_fd,
>>>> + data->pipe_crc, &crc);
>>>> - for (int x = 0; x < c; x++)
>>>> - igt_remove_fb(data->drm_fd, &data->fb[x]);
>>>> + for_each_plane_on_pipe(&data->display, pipe, plane)
>>>> + igt_plane_set_fb(plane, NULL);
>>>> - igt_assert_crc_equal(&data->ref_crc, &crc);
>>>> + for (int x = 0; x < c; x++)
>>>> + igt_remove_fb(data->drm_fd, &data->fb[x]);
>>>> - i++;
>>>> + igt_assert_crc_equal(&data->ref_crc, &crc);
>>>> +
>>>> + i++;
>>>> + }
>>>> }
>>>> test_fini(data, output, n_planes);
>>>> @@ -355,8 +461,12 @@ static void
>>>> test_plane_position(data_t *data, enum pipe pipe, uint64_t tiling)
>>>> {
>>>> igt_output_t *output;
>>>> + int devid = intel_get_drm_devid(data->drm_fd);
>>>> int n_planes = data->display.pipes[pipe].n_planes;
>>>> + if (data->flag == TEST_PCU_ALGO)
>>>> + igt_require(AT_LEAST_GEN(devid, 12));
>>>> +
>>>> output = igt_get_single_output_for_pipe(&data->display, pipe);
>>>> igt_require(output);
>>>> @@ -377,6 +487,14 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
>>>> igt_require(data->display.pipes[pipe].n_planes > 0);
>>>> }
>>>> +
>>>> + data->flag = TEST_PCU_ALGO;
>>>> +
>>>> + igt_subtest_f("atomic-pipe-%s-tiling-none_pcu",
>>>> kmstest_pipe_name(pipe))
>>>> + test_plane_position(data, pipe, LOCAL_DRM_FORMAT_MOD_NONE);
>>>> +
>>>> + data->flag = 0;
>>>> +
>>>> igt_subtest_f("atomic-pipe-%s-tiling-x", kmstest_pipe_name(pipe))
>>>> test_plane_position(data, pipe,
>>>> LOCAL_I915_FORMAT_MOD_X_TILED);
>>>> --
>>>> 2.21.0
>>>>
>>>> _______________________________________________
>>>> igt-dev mailing list
>>>> igt-dev@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH 09/10] tests/kms_plane_multiple/tgl: PCU messaging test
2019-07-15 21:51 ` [igt-dev] [PATCH 09/10] tests/kms_plane_multiple/tgl: PCU messaging test Lucas De Marchi
2019-07-19 12:54 ` Ville Syrjälä
@ 2019-08-02 10:43 ` Kahola, Mika
1 sibling, 0 replies; 22+ messages in thread
From: Kahola, Mika @ 2019-08-02 10:43 UTC (permalink / raw)
To: igt-dev@lists.freedesktop.org, De Marchi, Lucas
On Mon, 2019-07-15 at 14:51 -0700, Lucas De Marchi wrote:
> From: Karthik B S <karthik.b.s@intel.com>
>
> Add a subtest that gives flips which alternate between least
> bandwidth
> requirement and highest bandwidth requirement.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> tests/kms_plane_multiple.c | 178 ++++++++++++++++++++++++++++++-----
> --
> 1 file changed, 148 insertions(+), 30 deletions(-)
>
> diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
> index 81ed45dd..2c726fda 100644
> --- a/tests/kms_plane_multiple.c
> +++ b/tests/kms_plane_multiple.c
> @@ -34,6 +34,11 @@ IGT_TEST_DESCRIPTION("Test atomic mode setting
> with multiple planes.");
>
> #define SIZE_PLANE 256
> #define SIZE_CURSOR 128
> +#define SIZE_PLANE_LOW 10
> +#define SIZE_PANE 5
> +#define SMALL_SCREEN 0
> +#define FULL_SCREEN 1
> +#define TEST_PCU_ALGO 1
> #define LOOP_FOREVER -1
>
> typedef struct {
> @@ -48,9 +53,17 @@ typedef struct {
> igt_crc_t ref_crc;
> igt_pipe_crc_t *pipe_crc;
> igt_plane_t **plane;
> + unsigned int flag;
> struct igt_fb *fb;
> } data_t;
>
> +enum bandwidth {
> + BW_PRIMARY_LOW,
> + BW_PRIMARY_HIGH,
> + BW_PRIMARY_LOW2,
> + BW_HIGH,
> + BW_INVALID,
> +};
> /* Command line parameters. */
> struct {
> int iterations;
> @@ -97,7 +110,7 @@ static void test_fini(data_t *data, igt_output_t
> *output, int n_planes)
>
> static void
> get_reference_crc(data_t *data, igt_output_t *output, enum pipe
> pipe,
> - color_t *color, uint64_t tiling)
> + color_t *color, uint64_t tiling, int BW)
> {
> drmModeModeInfo *mode;
> igt_plane_t *primary;
> @@ -110,7 +123,9 @@ get_reference_crc(data_t *data, igt_output_t
> *output, enum pipe pipe,
>
> mode = igt_output_get_mode(output);
>
> - igt_create_color_fb(data->drm_fd, mode->hdisplay, mode-
> >vdisplay,
> + igt_create_color_fb(data->drm_fd,
> + BW ? mode->hdisplay : SIZE_PLANE_LOW,
> + BW ? mode->vdisplay : SIZE_PLANE_LOW,
> DRM_FORMAT_XRGB8888,
> LOCAL_DRM_FORMAT_MOD_NONE,
> color->red, color->green, color->blue,
> @@ -281,6 +296,76 @@ prepare_planes(data_t *data, enum pipe pipe_id,
> color_t *color,
> * The resulting CRC should be identical to the reference CRC
> */
>
> +static void
> +prepare_planes2(data_t *data, enum pipe pipe_id, color_t *color,
> + uint64_t tiling, int max_planes, igt_output_t *output,
> + enum bandwidth bandwidth)
> +{
> + drmModeModeInfo *mode;
> + int hsize, vsize;
> + int i;
> + cairo_t *cr;
> +
> + igt_output_set_pipe(output, pipe_id);
> + mode = igt_output_get_mode(output);
> +
> + switch (bandwidth) {
> + case BW_PRIMARY_LOW:
> + case BW_PRIMARY_LOW2:
> + hsize = SIZE_PLANE_LOW;
> + vsize = SIZE_PLANE_LOW;
> + break;
> + case BW_PRIMARY_HIGH:
> + case BW_HIGH:
> + hsize = mode->hdisplay;
> + vsize = mode->vdisplay;
> + break;
> + default:
> + igt_warn("Invalid BW\n");
> + }
> +
> + for (i = 0; i < max_planes; i++) {
> + igt_plane_t *plane = igt_output_get_plane(output, i);
> + uint32_t format = DRM_FORMAT_XRGB8888;
> +
> + if (plane->type == DRM_PLANE_TYPE_CURSOR) {
> + format = DRM_FORMAT_ARGB8888;
> + tiling = LOCAL_DRM_FORMAT_MOD_NONE;
> + hsize = SIZE_CURSOR;
> + vsize = SIZE_CURSOR;
> + }
> +
> + data->plane[i] = plane;
> + igt_create_color_fb(data->drm_fd,
> + hsize, vsize,
> + format, tiling,
> + color->red, color->green,
> + color->blue,
> + &data->fb[i]);
> + igt_plane_set_position(data->plane[i], 0, 0);
> +
> + hsize -= SIZE_PANE;
> +
> + /* Create black color holes in all planes other than
> the cursor
> + * and the topmost plane, so that all planes put
> together
> + * produces a solid blue screen that matches with
> + * the reference CRC.
> + */
> + if (i < (max_planes - 2) && bandwidth == BW_HIGH) {
> + cr = igt_get_cairo_ctx(data->drm_fd, &data-
> >fb[i]);
> + igt_paint_color(cr, 0, 0, hsize, vsize, 0.0,
> 0.0, 0.0);
> + igt_put_cairo_ctx(data->drm_fd, &data->fb[i],
> cr);
> + }
> +
> + igt_plane_set_fb(data->plane[i], &data->fb[i]);
> +
> + if (bandwidth != BW_HIGH &&
> + plane->type == DRM_PLANE_TYPE_PRIMARY)
> + break;
> +
> + }
> +}
> +
> static void
> test_plane_position_with_output(data_t *data, enum pipe pipe,
> igt_output_t *output, int n_planes,
> @@ -306,46 +391,67 @@ test_plane_position_with_output(data_t *data,
> enum pipe pipe,
>
> test_init(data, pipe, n_planes);
>
> - get_reference_crc(data, output, pipe, &blue, tiling);
> + if (data->flag == TEST_PCU_ALGO) {
> + for (i = BW_PRIMARY_LOW; i < BW_INVALID; i++) {
> + if (i == BW_PRIMARY_LOW || i ==
> BW_PRIMARY_LOW2)
> + get_reference_crc(data, output, pipe,
> &blue,
> + tiling, SMALL_SCREEN);
> + else
> + get_reference_crc(data, output, pipe,
> &blue,
> + tiling, FULL_SCREEN);
> +
> + /* Find out how many planes are allowed
> simultaneously */
> + do {
> + c++;
> + prepare_planes(data, pipe, &blue,
> tiling, c, output);
> + err = igt_display_try_commit2(&data-
> >display, COMMIT_ATOMIC);
>
> - /* Find out how many planes are allowed simultaneously */
> - do {
> - c++;
> - prepare_planes(data, pipe, &blue, tiling, c, output);
> - err = igt_display_try_commit2(&data->display,
> COMMIT_ATOMIC);
> + for_each_plane_on_pipe(&data->display,
> pipe, plane)
> + igt_plane_set_fb(plane, NULL);
>
> - for_each_plane_on_pipe(&data->display, pipe, plane)
> - igt_plane_set_fb(plane, NULL);
> + for (int x = 0; x < c; x++)
> + igt_remove_fb(data->drm_fd,
> &data->fb[x]);
> + } while (!err && c < n_planes);
>
> - for (int x = 0; x < c; x++)
> - igt_remove_fb(data->drm_fd, &data->fb[x]);
> - } while (!err && c < n_planes);
> + if (err)
> + c--;
>
> - if (err)
> - c--;
> + igt_info("Testing connector %s using pipe %s
> with %d planes %s with seed %d\n",
> + igt_output_name(output),
> kmstest_pipe_name(pipe), c,
> + info, opt.seed);
>
> - igt_info("Testing connector %s using pipe %s with %d planes %s
> with seed %d\n",
> - igt_output_name(output), kmstest_pipe_name(pipe), c,
> - info, opt.seed);
> + prepare_planes2(data, pipe, &blue, tiling,
> + n_planes, output, i);
> + igt_display_commit2(&data->display,
> COMMIT_ATOMIC);
>
> - i = 0;
> - while (i < iterations || loop_forever) {
> - /* randomize planes and set up the holes */
> - prepare_planes(data, pipe, &blue, tiling, c, output);
> + igt_pipe_crc_get_current(data->display.drm_fd,
> + data->pipe_crc, &crc);
>
> - igt_display_commit2(&data->display, COMMIT_ATOMIC);
> + igt_assert_crc_equal(&data->ref_crc, &crc);
> + }
> + } else {
> + i = 0;
> + get_reference_crc(data, output, pipe, &blue, tiling,
> FULL_SCREEN);
> +
> + while (i < iterations || loop_forever) {
> + prepare_planes(data, pipe, &blue, tiling,
> + n_planes, output);
>
> - igt_pipe_crc_get_current(data->display.drm_fd, data-
> >pipe_crc, &crc);
> + igt_display_commit2(&data->display,
> COMMIT_ATOMIC);
>
> - for_each_plane_on_pipe(&data->display, pipe, plane)
> - igt_plane_set_fb(plane, NULL);
> + igt_pipe_crc_get_current(data->display.drm_fd,
> + data->pipe_crc, &crc);
>
> - for (int x = 0; x < c; x++)
> - igt_remove_fb(data->drm_fd, &data->fb[x]);
> + for_each_plane_on_pipe(&data->display, pipe,
> plane)
> + igt_plane_set_fb(plane, NULL);
>
> - igt_assert_crc_equal(&data->ref_crc, &crc);
> + for (int x = 0; x < c; x++)
> + igt_remove_fb(data->drm_fd, &data-
> >fb[x]);
>
> - i++;
> + igt_assert_crc_equal(&data->ref_crc, &crc);
> +
> + i++;
> + }
> }
>
> test_fini(data, output, n_planes);
> @@ -355,8 +461,12 @@ static void
> test_plane_position(data_t *data, enum pipe pipe, uint64_t tiling)
> {
> igt_output_t *output;
> + int devid = intel_get_drm_devid(data->drm_fd);
> int n_planes = data->display.pipes[pipe].n_planes;
>
> + if (data->flag == TEST_PCU_ALGO)
> + igt_require(AT_LEAST_GEN(devid, 12));
> +
> output = igt_get_single_output_for_pipe(&data->display, pipe);
> igt_require(output);
>
> @@ -377,6 +487,14 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
> igt_require(data->display.pipes[pipe].n_planes > 0);
> }
>
> +
> + data->flag = TEST_PCU_ALGO;
> +
> + igt_subtest_f("atomic-pipe-%s-tiling-none_pcu",
> kmstest_pipe_name(pipe))
> + test_plane_position(data, pipe,
> LOCAL_DRM_FORMAT_MOD_NONE);
> +
> + data->flag = 0;
> +
> igt_subtest_f("atomic-pipe-%s-tiling-x",
> kmstest_pipe_name(pipe))
> test_plane_position(data, pipe,
> LOCAL_I915_FORMAT_MOD_X_TILED);
>
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
* [igt-dev] [PATCH 10/10] tests/kms_plane_multiple/tgl: Set highest mode for PCU messaging test
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
` (8 preceding siblings ...)
2019-07-15 21:51 ` [igt-dev] [PATCH 09/10] tests/kms_plane_multiple/tgl: PCU messaging test Lucas De Marchi
@ 2019-07-15 21:51 ` Lucas De Marchi
2019-08-02 10:44 ` Kahola, Mika
2019-07-15 22:42 ` [igt-dev] ✗ Fi.CI.BAT: failure for Add support for Tiger Lake Patchwork
10 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2019-07-15 21:51 UTC (permalink / raw)
To: igt-dev
From: Karthik B S <karthik.b.s@intel.com>
Set the highest mode allows for the stress test for PCU messaging, as
the BW requirement is the highest in this case.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
tests/kms_plane_multiple.c | 68 ++++++++++++++++++++++++++++++++------
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
index 2c726fda..1bf44005 100644
--- a/tests/kms_plane_multiple.c
+++ b/tests/kms_plane_multiple.c
@@ -285,16 +285,45 @@ prepare_planes(data_t *data, enum pipe pipe_id, color_t *color,
free((void*)suffle);
}
-/*
- * Multiple plane position test.
- * - We start by grabbing a reference CRC of a full blue fb being scanned
- * out on the primary plane
- * - Then we scannout number of planes:
- * * the primary plane uses a blue fb with a black rectangle holes
- * * planes, on top of the primary plane, with a blue fb that is set-up
- * to cover the black rectangles of the primary plane
- * The resulting CRC should be identical to the reference CRC
- */
+static drmModeModeInfo
+get_highest_mode(int drmfd, int connector_id)
+{
+ drmModeRes *mode_resources = drmModeGetResources(drmfd);
+ drmModeModeInfo highestmode;
+ drmModeConnector *connector;
+ int i;
+ bool highestmodefound = false;
+
+ igt_require(mode_resources);
+
+ for (i = 0; i < mode_resources->count_connectors; i++) {
+ connector = drmModeGetConnectorCurrent(drmfd,
+ mode_resources->connectors[i]);
+ if (!connector) {
+ igt_warn("could not get connector %i: %s\n",
+ mode_resources->connectors[i], strerror(errno));
+ continue;
+ }
+
+ if (connector->connector_id != connector_id)
+ continue;
+
+ if (!connector->count_modes)
+ continue;
+
+ /* First mode has the highest pixel rate */
+ highestmodefound = true;
+ highestmode = connector->modes[0];
+ break;
+ }
+
+ if (connector)
+ drmModeFreeConnector(connector);
+ drmModeFreeResources(mode_resources);
+
+ igt_require(highestmodefound);
+ return highestmode;
+}
static void
prepare_planes2(data_t *data, enum pipe pipe_id, color_t *color,
@@ -366,11 +395,22 @@ prepare_planes2(data_t *data, enum pipe pipe_id, color_t *color,
}
}
+/*
+ * Multiple plane position test.
+ * - We start by grabbing a reference CRC of a full blue fb being scanned
+ * out on the primary plane
+ * - Then we scannout number of planes:
+ * * the primary plane uses a blue fb with a black rectangle holes
+ * * planes, on top of the primary plane, with a blue fb that is set-up
+ * to cover the black rectangles of the primary plane
+ * The resulting CRC should be identical to the reference CRC
+ */
static void
test_plane_position_with_output(data_t *data, enum pipe pipe,
igt_output_t *output, int n_planes,
uint64_t tiling)
{
+ drmModeModeInfo mode_highres;
color_t blue = { 0.0f, 0.0f, 1.0f };
igt_crc_t crc;
igt_plane_t *plane;
@@ -392,6 +432,11 @@ test_plane_position_with_output(data_t *data, enum pipe pipe,
test_init(data, pipe, n_planes);
if (data->flag == TEST_PCU_ALGO) {
+ mode_highres = get_highest_mode(data->drm_fd, output->id);
+
+ /* switch to highest resolution */
+ igt_output_override_mode(output, &mode_highres);
+
for (i = BW_PRIMARY_LOW; i < BW_INVALID; i++) {
if (i == BW_PRIMARY_LOW || i == BW_PRIMARY_LOW2)
get_reference_crc(data, output, pipe, &blue,
@@ -429,6 +474,9 @@ test_plane_position_with_output(data_t *data, enum pipe pipe,
igt_assert_crc_equal(&data->ref_crc, &crc);
}
+
+ /* switch back to default mode */
+ igt_output_override_mode(output, NULL);
} else {
i = 0;
get_reference_crc(data, output, pipe, &blue, tiling, FULL_SCREEN);
--
2.21.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [igt-dev] [PATCH 10/10] tests/kms_plane_multiple/tgl: Set highest mode for PCU messaging test
2019-07-15 21:51 ` [igt-dev] [PATCH 10/10] tests/kms_plane_multiple/tgl: Set highest mode for " Lucas De Marchi
@ 2019-08-02 10:44 ` Kahola, Mika
0 siblings, 0 replies; 22+ messages in thread
From: Kahola, Mika @ 2019-08-02 10:44 UTC (permalink / raw)
To: igt-dev@lists.freedesktop.org, De Marchi, Lucas
On Mon, 2019-07-15 at 14:51 -0700, Lucas De Marchi wrote:
> From: Karthik B S <karthik.b.s@intel.com>
>
> Set the highest mode allows for the stress test for PCU messaging, as
> the BW requirement is the highest in this case.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> tests/kms_plane_multiple.c | 68 ++++++++++++++++++++++++++++++++--
> ----
> 1 file changed, 58 insertions(+), 10 deletions(-)
>
> diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
> index 2c726fda..1bf44005 100644
> --- a/tests/kms_plane_multiple.c
> +++ b/tests/kms_plane_multiple.c
> @@ -285,16 +285,45 @@ prepare_planes(data_t *data, enum pipe pipe_id,
> color_t *color,
> free((void*)suffle);
> }
>
> -/*
> - * Multiple plane position test.
> - * - We start by grabbing a reference CRC of a full blue fb being
> scanned
> - * out on the primary plane
> - * - Then we scannout number of planes:
> - * * the primary plane uses a blue fb with a black rectangle
> holes
> - * * planes, on top of the primary plane, with a blue fb that
> is set-up
> - * to cover the black rectangles of the primary plane
> - * The resulting CRC should be identical to the reference CRC
> - */
> +static drmModeModeInfo
> +get_highest_mode(int drmfd, int connector_id)
> +{
> + drmModeRes *mode_resources = drmModeGetResources(drmfd);
> + drmModeModeInfo highestmode;
> + drmModeConnector *connector;
> + int i;
> + bool highestmodefound = false;
> +
> + igt_require(mode_resources);
> +
> + for (i = 0; i < mode_resources->count_connectors; i++) {
> + connector = drmModeGetConnectorCurrent(drmfd,
> + mode_resources-
> >connectors[i]);
> + if (!connector) {
> + igt_warn("could not get connector %i: %s\n",
> + mode_resources->connectors[i],
> strerror(errno));
> + continue;
> + }
> +
> + if (connector->connector_id != connector_id)
> + continue;
> +
> + if (!connector->count_modes)
> + continue;
> +
> + /* First mode has the highest pixel rate */
> + highestmodefound = true;
> + highestmode = connector->modes[0];
> + break;
> + }
> +
> + if (connector)
> + drmModeFreeConnector(connector);
> + drmModeFreeResources(mode_resources);
> +
> + igt_require(highestmodefound);
> + return highestmode;
> +}
>
> static void
> prepare_planes2(data_t *data, enum pipe pipe_id, color_t *color,
> @@ -366,11 +395,22 @@ prepare_planes2(data_t *data, enum pipe
> pipe_id, color_t *color,
> }
> }
>
> +/*
> + * Multiple plane position test.
> + * - We start by grabbing a reference CRC of a full blue fb being
> scanned
> + * out on the primary plane
> + * - Then we scannout number of planes:
> + * * the primary plane uses a blue fb with a black rectangle
> holes
> + * * planes, on top of the primary plane, with a blue fb that
> is set-up
> + * to cover the black rectangles of the primary plane
> + * The resulting CRC should be identical to the reference CRC
> + */
> static void
> test_plane_position_with_output(data_t *data, enum pipe pipe,
> igt_output_t *output, int n_planes,
> uint64_t tiling)
> {
> + drmModeModeInfo mode_highres;
> color_t blue = { 0.0f, 0.0f, 1.0f };
> igt_crc_t crc;
> igt_plane_t *plane;
> @@ -392,6 +432,11 @@ test_plane_position_with_output(data_t *data,
> enum pipe pipe,
> test_init(data, pipe, n_planes);
>
> if (data->flag == TEST_PCU_ALGO) {
> + mode_highres = get_highest_mode(data->drm_fd, output-
> >id);
> +
> + /* switch to highest resolution */
> + igt_output_override_mode(output, &mode_highres);
> +
> for (i = BW_PRIMARY_LOW; i < BW_INVALID; i++) {
> if (i == BW_PRIMARY_LOW || i ==
> BW_PRIMARY_LOW2)
> get_reference_crc(data, output, pipe,
> &blue,
> @@ -429,6 +474,9 @@ test_plane_position_with_output(data_t *data,
> enum pipe pipe,
>
> igt_assert_crc_equal(&data->ref_crc, &crc);
> }
> +
> + /* switch back to default mode */
> + igt_output_override_mode(output, NULL);
> } else {
> i = 0;
> get_reference_crc(data, output, pipe, &blue, tiling,
> FULL_SCREEN);
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
* [igt-dev] ✗ Fi.CI.BAT: failure for Add support for Tiger Lake
2019-07-15 21:51 [igt-dev] [PATCH 00/10] Add support for Tiger Lake Lucas De Marchi
` (9 preceding siblings ...)
2019-07-15 21:51 ` [igt-dev] [PATCH 10/10] tests/kms_plane_multiple/tgl: Set highest mode for " Lucas De Marchi
@ 2019-07-15 22:42 ` Patchwork
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-07-15 22:42 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: igt-dev
== Series Details ==
Series: Add support for Tiger Lake
URL : https://patchwork.freedesktop.org/series/63726/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6488 -> IGTPW_3271
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_3271 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_3271, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/63726/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_3271:
### IGT changes ###
#### Possible regressions ####
* igt@kms_chamelium@dp-hpd-fast:
- fi-icl-u2: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-icl-u2/igt@kms_chamelium@dp-hpd-fast.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/fi-icl-u2/igt@kms_chamelium@dp-hpd-fast.html
Known issues
------------
Here are the changes found in IGTPW_3271 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][3] -> [INCOMPLETE][4] ([fdo#111050])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-kbl-7500u/igt@kms_busy@basic-flip-c.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/fi-kbl-7500u/igt@kms_busy@basic-flip-c.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [DMESG-WARN][8] ([fdo#103558] / [fdo#105602])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-kbl-7500u/igt@kms_chamelium@dp-hpd-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/fi-kbl-7500u/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#109635 ])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-icl-u3/igt@gem_ctx_exec@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/fi-icl-u3/igt@gem_ctx_exec@basic.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][13] ([fdo#111108]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [FAIL][15] ([fdo#109635 ]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
- fi-cml-u2: [FAIL][17] ([fdo#110627]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [DMESG-WARN][19] ([fdo#106387]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108
Participating hosts (54 -> 45)
------------------------------
Missing (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-guc fi-icl-dsi fi-bdw-samus
Build changes
-------------
* IGT: IGT_5098 -> IGTPW_3271
CI_DRM_6488: bbf4d95db6732b16547dc9d849701ccf4189aa0d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3271: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/
IGT_5098: 41ff022b62b45a5b84504daa3537fa1b295b97c9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@kms_plane_multiple@atomic-pipe-a-tiling-none_pcu
+igt@kms_plane_multiple@atomic-pipe-b-tiling-none_pcu
+igt@kms_plane_multiple@atomic-pipe-c-tiling-none_pcu
+igt@kms_plane_multiple@atomic-pipe-d-tiling-none_pcu
+igt@kms_plane_multiple@atomic-pipe-e-tiling-none_pcu
+igt@kms_plane_multiple@atomic-pipe-f-tiling-none_pcu
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3271/
_______________________________________________
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