* [igt-dev] [PATCH i-g-t v6 0/3] Remove global igt_global_mmio
@ 2019-07-24 12:32 Daniel Mrzyglod
2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 1/3] lib/igt_device: add igt_device_get_pci_addr by fd Daniel Mrzyglod
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Daniel Mrzyglod @ 2019-07-24 12:32 UTC (permalink / raw)
To: igt-dev
This patchset remove need for global igt_global_mmio pointer and structures.
In the end igt_global_mmio was kept for legacy reason.
Right now every device could have their own *igt_mmio pointer.
Current behaviour limit number of concurrent PCI device.
There is a need to run multiple devices.
v2: fixed bugs pointed out in review
v3: divide series to more patches - fix bugs
v4: reword fix bugs
v5: removed patch 03/06 from the previous series due to sugestions
add fd to gem_mappable_aperture_size()
v6: remove not needed patches. leave igt_global mmio for legacy reason.
Daniel Mrzyglod (2):
lib/intel_mmio: add funtions for read/write register funtions
lib/intel_mmio: add additional api for multiple devices
Michał Winiarski (1):
lib/igt_device: add igt_device_get_pci_addr by fd
benchmarks/gem_latency.c | 3 +-
benchmarks/gem_wsim.c | 3 +-
lib/igt_device.c | 124 +++++++++++++++++++
lib/igt_device.h | 1 +
lib/intel_io.h | 89 +++++++++-----
lib/intel_iosf.c | 74 +++++++-----
lib/intel_mmio.c | 217 +++++++++++++++++++++++++---------
tests/i915/gem_exec_latency.c | 4 +-
tests/i915/gem_exec_parse.c | 13 +-
tests/i915/gem_workarounds.c | 3 +-
tests/i915/i915_pm_lpsp.c | 6 +-
tools/intel_audio_dump.c | 6 +-
tools/intel_backlight.c | 4 +-
tools/intel_display_poller.c | 5 +-
tools/intel_forcewaked.c | 15 +--
tools/intel_gpu_time.c | 3 +-
tools/intel_infoframes.c | 5 +-
tools/intel_l3_parity.c | 11 +-
tools/intel_lid.c | 3 +-
tools/intel_panel_fitter.c | 5 +-
tools/intel_perf_counters.c | 10 +-
tools/intel_reg.c | 23 ++--
tools/intel_reg_checker.c | 3 +-
tools/intel_watermark.c | 42 ++++---
24 files changed, 489 insertions(+), 183 deletions(-)
--
2.20.1
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^ permalink raw reply [flat|nested] 10+ messages in thread* [igt-dev] [PATCH i-g-t v6 1/3] lib/igt_device: add igt_device_get_pci_addr by fd 2019-07-24 12:32 [igt-dev] [PATCH i-g-t v6 0/3] Remove global igt_global_mmio Daniel Mrzyglod @ 2019-07-24 12:32 ` Daniel Mrzyglod 2019-07-24 15:11 ` Zbigniew Kempczyński 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 2/3] lib/intel_mmio: add funtions for read/write register funtions Daniel Mrzyglod ` (4 subsequent siblings) 5 siblings, 1 reply; 10+ messages in thread From: Daniel Mrzyglod @ 2019-07-24 12:32 UTC (permalink / raw) To: igt-dev From: Michał Winiarski <michal.winiarski@intel.com> This function get us pci address based by fd. It allows us to make things a little bit more generic. Also, we now require fd rather than doing guesswork when it comes to pci address. v4: close sysfs fd Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> CC: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Signed-off-by: Daniel Mrzyglod <daniel.t.mrzyglod@intel.com> --- lib/igt_device.c | 124 +++++++++++++++++++++++++++++++++++++++++++++++ lib/igt_device.h | 1 + 2 files changed, 125 insertions(+) diff --git a/lib/igt_device.c b/lib/igt_device.c index 9469e5de..07bb0a0d 100644 --- a/lib/igt_device.c +++ b/lib/igt_device.c @@ -21,11 +21,14 @@ * IN THE SOFTWARE. * */ +#include <sys/types.h> +#include <fcntl.h> #include <sys/stat.h> #include <sys/sysmacros.h> #include "igt.h" #include "igt_device.h" +#include "igt_sysfs.h" int __igt_device_set_master(int fd) { @@ -112,3 +115,124 @@ int igt_device_get_card_index(int fd) return minor(st.st_rdev); } + +#define IGT_DEV_PATH_LEN 80 + +static bool igt_device_is_pci(int fd) +{ + char path[IGT_DEV_PATH_LEN]; + char *subsystem; + int sysfs; + int len; + + sysfs = igt_sysfs_open(fd); + if (sysfs == -1) + return false; + + len = readlinkat(sysfs, "device/subsystem", path, sizeof(path) - 1); + close(sysfs); + if (len == -1) + return false; + path[len] = '\0'; + + subsystem = strrchr(path, '/'); + if (!subsystem) + return false; + + return strcmp(subsystem, "/pci") == 0; +} + +struct igt_pci_addr { + unsigned int domain; + unsigned int bus; + unsigned int device; + unsigned int function; +}; + +static int igt_device_get_pci_addr(int fd, struct igt_pci_addr *pci) +{ + char path[IGT_DEV_PATH_LEN]; + char *buf; + int sysfs; + int len; + + if (!igt_device_is_pci(fd)) + return -ENODEV; + + sysfs = igt_sysfs_open(fd); + if (sysfs == -1) + return -ENOENT; + + len = readlinkat(sysfs, "device", path, sizeof(path) - 1); + close(sysfs); + if (len == -1) + return -ENOENT; + path[len] = '\0'; + + buf = strrchr(path, '/'); + if (!buf) + return -ENOENT; + + if (sscanf(buf, "/%4x:%2x:%2x.%2x", + &pci->domain, &pci->bus, + &pci->device, &pci->function) != 4) { + igt_warn("Unable to extract PCI device address from '%s'\n", buf); + return -ENOENT; + } + + return 0; +} + +static struct pci_device *__igt_device_get_pci_device(int fd) +{ + struct igt_pci_addr pci_addr; + struct pci_device *pci_dev; + + if (igt_device_get_pci_addr(fd, &pci_addr)) { + igt_warn("Unable to find device PCI address\n"); + return NULL; + } + + if (pci_system_init()) { + igt_warn("Couldn't initialize PCI system\n"); + return NULL; + } + + pci_dev = pci_device_find_by_slot(pci_addr.domain, + pci_addr.bus, + pci_addr.device, + pci_addr.function); + if (!pci_dev) { + igt_warn("Couldn't find PCI device %04x:%02x:%02x:%02x\n", + pci_addr.domain, pci_addr.bus, + pci_addr.device, pci_addr.function); + return NULL; + } + + if (pci_device_probe(pci_dev)) { + igt_warn("Couldn't probe PCI device\n"); + return NULL; + } + + return pci_dev; +} + +/** + * igt_device_get_pci_device: + * + * @fd: the device + * + * Looks up the main graphics pci device using libpciaccess. + * + * Returns: + * The pci_device, skips the test on any failures. + */ +struct pci_device *igt_device_get_pci_device(int fd) +{ + struct pci_device *pci_dev; + + pci_dev = __igt_device_get_pci_device(fd); + igt_require(pci_dev); + + return pci_dev; +} diff --git a/lib/igt_device.h b/lib/igt_device.h index 9d7dc2c3..278ba7a9 100644 --- a/lib/igt_device.h +++ b/lib/igt_device.h @@ -32,5 +32,6 @@ int __igt_device_drop_master(int fd); void igt_device_drop_master(int fd); int igt_device_get_card_index(int fd); +struct pci_device *igt_device_get_pci_device(int fd); #endif /* __IGT_DEVICE_H__ */ -- 2.20.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v6 1/3] lib/igt_device: add igt_device_get_pci_addr by fd 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 1/3] lib/igt_device: add igt_device_get_pci_addr by fd Daniel Mrzyglod @ 2019-07-24 15:11 ` Zbigniew Kempczyński 0 siblings, 0 replies; 10+ messages in thread From: Zbigniew Kempczyński @ 2019-07-24 15:11 UTC (permalink / raw) To: Daniel Mrzyglod; +Cc: igt-dev On Wed, Jul 24, 2019 at 02:32:54PM +0200, Daniel Mrzyglod wrote: > From: Michał Winiarski <michal.winiarski@intel.com> > > This function get us pci address based by fd. > It allows us to make things a little bit more generic. > Also, we now require fd rather than doing guesswork when it comes to pci address. > > v4: close sysfs fd > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > CC: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > Signed-off-by: Daniel Mrzyglod <daniel.t.mrzyglod@intel.com> <cut> > +struct igt_pci_addr { > + unsigned int domain; > + unsigned int bus; > + unsigned int device; > + unsigned int function; > +}; > + > +static int igt_device_get_pci_addr(int fd, struct igt_pci_addr *pci) > +{ > + char path[IGT_DEV_PATH_LEN]; > + char *buf; > + int sysfs; > + int len; > + > + if (!igt_device_is_pci(fd)) > + return -ENODEV; > + > + sysfs = igt_sysfs_open(fd); > + if (sysfs == -1) > + return -ENOENT; > + > + len = readlinkat(sysfs, "device", path, sizeof(path) - 1); > + close(sysfs); > + if (len == -1) > + return -ENOENT; > + path[len] = '\0'; > + > + buf = strrchr(path, '/'); > + if (!buf) > + return -ENOENT; > + > + if (sscanf(buf, "/%4x:%2x:%2x.%2x", > + &pci->domain, &pci->bus, > + &pci->device, &pci->function) != 4) { > + igt_warn("Unable to extract PCI device address from '%s'\n", buf); > + return -ENOENT; > + } > + > + return 0; > +} According to kernel: drivers/pci/probe.c, pci_setup_device() device is formatted using "%04x:%02x:%02x.%d". Anyway your code will work properly for our case because there's no %02x on the pci function position. Acked-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > + > +static struct pci_device *__igt_device_get_pci_device(int fd) > +{ > + struct igt_pci_addr pci_addr; > + struct pci_device *pci_dev; > + > + if (igt_device_get_pci_addr(fd, &pci_addr)) { > + igt_warn("Unable to find device PCI address\n"); > + return NULL; > + } > + > + if (pci_system_init()) { > + igt_warn("Couldn't initialize PCI system\n"); > + return NULL; > + } > + > + pci_dev = pci_device_find_by_slot(pci_addr.domain, > + pci_addr.bus, > + pci_addr.device, > + pci_addr.function); > + if (!pci_dev) { > + igt_warn("Couldn't find PCI device %04x:%02x:%02x:%02x\n", > + pci_addr.domain, pci_addr.bus, > + pci_addr.device, pci_addr.function); > + return NULL; > + } > + > + if (pci_device_probe(pci_dev)) { > + igt_warn("Couldn't probe PCI device\n"); > + return NULL; > + } > + > + return pci_dev; > +} > + > +/** > + * igt_device_get_pci_device: > + * > + * @fd: the device > + * > + * Looks up the main graphics pci device using libpciaccess. > + * > + * Returns: > + * The pci_device, skips the test on any failures. > + */ > +struct pci_device *igt_device_get_pci_device(int fd) > +{ > + struct pci_device *pci_dev; > + > + pci_dev = __igt_device_get_pci_device(fd); > + igt_require(pci_dev); > + > + return pci_dev; > +} > diff --git a/lib/igt_device.h b/lib/igt_device.h > index 9d7dc2c3..278ba7a9 100644 > --- a/lib/igt_device.h > +++ b/lib/igt_device.h > @@ -32,5 +32,6 @@ int __igt_device_drop_master(int fd); > void igt_device_drop_master(int fd); > > int igt_device_get_card_index(int fd); > +struct pci_device *igt_device_get_pci_device(int fd); > > #endif /* __IGT_DEVICE_H__ */ > -- > 2.20.1 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 10+ messages in thread
* [igt-dev] [PATCH i-g-t v6 2/3] lib/intel_mmio: add funtions for read/write register funtions 2019-07-24 12:32 [igt-dev] [PATCH i-g-t v6 0/3] Remove global igt_global_mmio Daniel Mrzyglod 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 1/3] lib/igt_device: add igt_device_get_pci_addr by fd Daniel Mrzyglod @ 2019-07-24 12:32 ` Daniel Mrzyglod 2019-08-13 11:11 ` Kempczynski, Zbigniew 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 3/3] lib/intel_mmio: add additional api for multiple devices Daniel Mrzyglod ` (3 subsequent siblings) 5 siblings, 1 reply; 10+ messages in thread From: Daniel Mrzyglod @ 2019-07-24 12:32 UTC (permalink / raw) To: igt-dev This patch is first move to extend functionality of intel_mmio library. There was limitation for 1 device, adding pointer for IO functions to mmaped area gives us possibility to use those IO functions for other mmaped devices. v4: reword commitmsg, spelling errors Signed-off-by: Daniel Mrzyglod <daniel.t.mrzyglod@intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- lib/intel_io.h | 7 ++++ lib/intel_mmio.c | 107 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) diff --git a/lib/intel_io.h b/lib/intel_io.h index 6014c485..99cb1829 100644 --- a/lib/intel_io.h +++ b/lib/intel_io.h @@ -49,6 +49,13 @@ void OUTREG(uint32_t reg, uint32_t val); void OUTREG16(uint32_t reg, uint16_t val); void OUTREG8(uint32_t reg, uint8_t val); +uint32_t INREG_DEV(void *igt_mmio, uint32_t reg); +uint16_t INREG16_DEV(void *igt_mmio, uint32_t reg); +uint8_t INREG8_DEV(void *igt_mmio, uint32_t reg); +void OUTREG_DEV(void *igt_mmio, uint32_t reg, uint32_t val); +void OUTREG16_DEV(void *igt_mmio, uint32_t reg, uint16_t val); +void OUTREG8_DEV(void *igt_mmio, uint32_t reg, uint8_t val); + /* sideband access functions from intel_iosf.c */ uint32_t intel_dpio_reg_read(uint32_t reg, int phy); void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy); diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c index a5458aeb..01411c37 100644 --- a/lib/intel_mmio.c +++ b/lib/intel_mmio.c @@ -405,3 +405,110 @@ void OUTREG8(uint32_t reg, uint8_t val) { *((volatile uint8_t *)igt_global_mmio + reg) = val; } + + +/** + * INREG_DEV: + * @igt_mmio maped memory pointer + * @reg: register offset + * + * 32-bit read of the register at offset @reg. This function only works when the + * new register access helper is initialized with intel_register_access_init(). + * + * This function directly accesses the igt_mmio without safety checks. + * + * Returns: + * The value read from the register. + */ +uint32_t INREG_DEV(void *igt_mmio, uint32_t reg) +{ + return *(volatile uint32_t *)((volatile char *)igt_mmio + reg); +} + +/** + * INREG16_DEV: + * @igt_mmio maped memory pointer + * @reg: register offset + * + * 16-bit read of the register at offset @reg. This function only works when the + * new register access helper is initialized with intel_register_access_init(). + * + * This function directly accesses the igt_mmio without safety checks. + * + * Returns: + * The value read from the register. + */ +uint16_t INREG16_DEV(void *igt_mmio, uint32_t reg) +{ + return *(volatile uint16_t *)((volatile char *)igt_mmio + reg); +} + +/** + * INREG8_DEV: + * @igt_mmio maped memory pointer + * @reg: register offset + * + * 8-bit read of the register at offset @reg. This function only works when the + * new register access helper is initialized with intel_register_access_init(). + * + * This function directly accesses the igt_mmio without safety checks. + * + * Returns: + * The value read from the register. + */ +uint8_t INREG8_DEV(void *igt_mmio, uint32_t reg) +{ + return *((volatile uint8_t *)igt_mmio + reg); +} + +/** + * OUTREG_DEV: + * @igt_mmio maped memory pointer + * @reg: register offset + * @val: value to write + * + * 32-bit write of @val to the register at offset @reg. This function only works + * when the new register access helper is initialized with + * intel_register_access_init(). + * + * This function directly accesses the igt_mmio without safety checks. + */ +void OUTREG_DEV(void *igt_mmio, uint32_t reg, uint32_t val) +{ + *(volatile uint32_t *)((volatile char *)igt_mmio + reg) = val; +} + +/** + * OUTREG16_DEV: + * @igt_mmio maped memory pointer + * @reg: register offset + * @val: value to write + * + * 16-bit write of @val to the register at offset @reg. This function only works + * when the new register access helper is initialized with + * intel_register_access_init(). + * + * This function directly accesses the igt_mmio without safety checks. + */ +void OUTREG16_DEV(void *igt_mmio, uint32_t reg, uint16_t val) +{ + *(volatile uint16_t *)((volatile char *)igt_mmio + reg) = val; +} + +/** + * OUTREG8_DEV: + * @igt_mmio maped memory pointer + * @reg: register offset + * @val: value to write + * + * 8-bit write of @val to the register at offset @reg. This function only works + * when the new register access helper is initialized with + * intel_register_access_init(). + * + * This function directly accesses the igt_mmio without safety checks. + */ +void OUTREG8_DEV(void *igt_mmio, uint32_t reg, uint8_t val) +{ + *((volatile uint8_t *)igt_mmio + reg) = val; +} + -- 2.20.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v6 2/3] lib/intel_mmio: add funtions for read/write register funtions 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 2/3] lib/intel_mmio: add funtions for read/write register funtions Daniel Mrzyglod @ 2019-08-13 11:11 ` Kempczynski, Zbigniew 0 siblings, 0 replies; 10+ messages in thread From: Kempczynski, Zbigniew @ 2019-08-13 11:11 UTC (permalink / raw) To: Mrzyglod, Daniel T, igt-dev@lists.freedesktop.org On Wed, 2019-07-24 at 14:32 +0200, Daniel Mrzyglod wrote: > This patch is first move to extend functionality of intel_mmio library. > There was limitation for 1 device, adding pointer for IO functions to > mmaped area gives us possibility to use those IO functions for other > mmaped > devices. > > v4: reword commitmsg, spelling errors > > Signed-off-by: Daniel Mrzyglod <daniel.t.mrzyglod@intel.com> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > --- > lib/intel_io.h | 7 ++++ > lib/intel_mmio.c | 107 +++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 114 insertions(+) > > diff --git a/lib/intel_io.h b/lib/intel_io.h > index 6014c485..99cb1829 100644 > --- a/lib/intel_io.h > +++ b/lib/intel_io.h > @@ -49,6 +49,13 @@ void OUTREG(uint32_t reg, uint32_t val); > void OUTREG16(uint32_t reg, uint16_t val); > void OUTREG8(uint32_t reg, uint8_t val); > > +uint32_t INREG_DEV(void *igt_mmio, uint32_t reg); > +uint16_t INREG16_DEV(void *igt_mmio, uint32_t reg); > +uint8_t INREG8_DEV(void *igt_mmio, uint32_t reg); > +void OUTREG_DEV(void *igt_mmio, uint32_t reg, uint32_t val); > +void OUTREG16_DEV(void *igt_mmio, uint32_t reg, uint16_t val); > +void OUTREG8_DEV(void *igt_mmio, uint32_t reg, uint8_t val); > + > /* sideband access functions from intel_iosf.c */ > uint32_t intel_dpio_reg_read(uint32_t reg, int phy); > void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy); > diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c > index a5458aeb..01411c37 100644 > --- a/lib/intel_mmio.c > +++ b/lib/intel_mmio.c > @@ -405,3 +405,110 @@ void OUTREG8(uint32_t reg, uint8_t val) > { > *((volatile uint8_t *)igt_global_mmio + reg) = val; > } > + > + > +/** > + * INREG_DEV: > + * @igt_mmio maped memory pointer > + * @reg: register offset > + * > + * 32-bit read of the register at offset @reg. This function only works > when the > + * new register access helper is initialized with > intel_register_access_init(). > + * > + * This function directly accesses the igt_mmio without safety checks. > + * > + * Returns: > + * The value read from the register. > + */ > +uint32_t INREG_DEV(void *igt_mmio, uint32_t reg) > +{ > + return *(volatile uint32_t *)((volatile char *)igt_mmio + reg); > +} > + > +/** > + * INREG16_DEV: > + * @igt_mmio maped memory pointer > + * @reg: register offset > + * > + * 16-bit read of the register at offset @reg. This function only works > when the > + * new register access helper is initialized with > intel_register_access_init(). > + * > + * This function directly accesses the igt_mmio without safety checks. > + * > + * Returns: > + * The value read from the register. > + */ > +uint16_t INREG16_DEV(void *igt_mmio, uint32_t reg) > +{ > + return *(volatile uint16_t *)((volatile char *)igt_mmio + reg); > +} > + > +/** > + * INREG8_DEV: > + * @igt_mmio maped memory pointer > + * @reg: register offset > + * > + * 8-bit read of the register at offset @reg. This function only works when > the > + * new register access helper is initialized with > intel_register_access_init(). > + * > + * This function directly accesses the igt_mmio without safety checks. > + * > + * Returns: > + * The value read from the register. > + */ > +uint8_t INREG8_DEV(void *igt_mmio, uint32_t reg) > +{ > + return *((volatile uint8_t *)igt_mmio + reg); > +} > + > +/** > + * OUTREG_DEV: > + * @igt_mmio maped memory pointer > + * @reg: register offset > + * @val: value to write > + * > + * 32-bit write of @val to the register at offset @reg. This function only > works > + * when the new register access helper is initialized with > + * intel_register_access_init(). > + * > + * This function directly accesses the igt_mmio without safety checks. > + */ > +void OUTREG_DEV(void *igt_mmio, uint32_t reg, uint32_t val) > +{ > + *(volatile uint32_t *)((volatile char *)igt_mmio + reg) = val; > +} > + > +/** > + * OUTREG16_DEV: > + * @igt_mmio maped memory pointer > + * @reg: register offset > + * @val: value to write > + * > + * 16-bit write of @val to the register at offset @reg. This function only > works > + * when the new register access helper is initialized with > + * intel_register_access_init(). > + * > + * This function directly accesses the igt_mmio without safety checks. > + */ > +void OUTREG16_DEV(void *igt_mmio, uint32_t reg, uint16_t val) > +{ > + *(volatile uint16_t *)((volatile char *)igt_mmio + reg) = val; > +} > + > +/** > + * OUTREG8_DEV: > + * @igt_mmio maped memory pointer > + * @reg: register offset > + * @val: value to write > + * > + * 8-bit write of @val to the register at offset @reg. This function only > works > + * when the new register access helper is initialized with > + * intel_register_access_init(). > + * > + * This function directly accesses the igt_mmio without safety checks. > + */ > +void OUTREG8_DEV(void *igt_mmio, uint32_t reg, uint8_t val) > +{ > + *((volatile uint8_t *)igt_mmio + reg) = val; > +} > + LGTM, RB. Zbigniew _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 10+ messages in thread
* [igt-dev] [PATCH i-g-t v6 3/3] lib/intel_mmio: add additional api for multiple devices 2019-07-24 12:32 [igt-dev] [PATCH i-g-t v6 0/3] Remove global igt_global_mmio Daniel Mrzyglod 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 1/3] lib/igt_device: add igt_device_get_pci_addr by fd Daniel Mrzyglod 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 2/3] lib/intel_mmio: add funtions for read/write register funtions Daniel Mrzyglod @ 2019-07-24 12:32 ` Daniel Mrzyglod 2019-08-13 11:21 ` Kempczynski, Zbigniew 2019-07-24 12:48 ` [igt-dev] ✗ GitLab.Pipeline: warning for Remove global igt_global_mmio (rev6) Patchwork ` (2 subsequent siblings) 5 siblings, 1 reply; 10+ messages in thread From: Daniel Mrzyglod @ 2019-07-24 12:32 UTC (permalink / raw) To: igt-dev this patch extend intel_mmio library by new structure that can keep local igt_mmio pointer. The reason that we extend functionality is the idea to support multiple devices at once. Signed-off-by: Daniel Mrzyglod <daniel.t.mrzyglod@intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- benchmarks/gem_latency.c | 3 +- benchmarks/gem_wsim.c | 3 +- lib/intel_io.h | 82 +++++++++++++++---------- lib/intel_iosf.c | 74 +++++++++++++---------- lib/intel_mmio.c | 110 ++++++++++++++++++---------------- tests/i915/gem_exec_latency.c | 4 +- tests/i915/gem_exec_parse.c | 13 ++-- tests/i915/gem_workarounds.c | 3 +- tests/i915/i915_pm_lpsp.c | 6 +- tools/intel_audio_dump.c | 6 +- tools/intel_backlight.c | 4 +- tools/intel_display_poller.c | 5 +- tools/intel_forcewaked.c | 15 ++--- tools/intel_gpu_time.c | 3 +- tools/intel_infoframes.c | 5 +- tools/intel_l3_parity.c | 11 ++-- tools/intel_lid.c | 3 +- tools/intel_panel_fitter.c | 5 +- tools/intel_perf_counters.c | 10 ++-- tools/intel_reg.c | 23 +++---- tools/intel_reg_checker.c | 3 +- tools/intel_watermark.c | 42 +++++++------ 22 files changed, 250 insertions(+), 183 deletions(-) diff --git a/benchmarks/gem_latency.c b/benchmarks/gem_latency.c index c3fc4bf0..569faa58 100644 --- a/benchmarks/gem_latency.c +++ b/benchmarks/gem_latency.c @@ -55,6 +55,7 @@ static int done; static int fd; static volatile uint32_t *timestamp_reg; +static struct mmio_data mmio_data; #define REG(x) (volatile uint32_t *)((volatile char *)igt_global_mmio + x) #define REG_OFFSET(x) ((volatile char *)(x) - (volatile char *)igt_global_mmio) @@ -456,7 +457,7 @@ static int run(int seconds, if (gen < 6) return IGT_EXIT_SKIP; /* Needs BCS timestamp */ - intel_register_access_init(intel_get_pci_device(), false, fd); + intel_register_access_init(&mmio_data, intel_get_pci_device(), false, fd); if (gen == 6) timestamp_reg = REG(RCS_TIMESTAMP); diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index a76fdbfe..3c7401df 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -238,6 +238,7 @@ struct workload } busy_balancer; }; +struct mmio_data mmio_data; static const unsigned int nop_calibration_us = 1000; static unsigned long nop_calibration; @@ -3071,7 +3072,7 @@ static void init_clocks(void) uint32_t rcs_start, rcs_end; double overhead, t; - intel_register_access_init(intel_get_pci_device(), false, fd); + intel_register_access_init(&mmio_data, intel_get_pci_device(), false, fd); if (verbose <= 1) return; diff --git a/lib/intel_io.h b/lib/intel_io.h index 99cb1829..370a9ab1 100644 --- a/lib/intel_io.h +++ b/lib/intel_io.h @@ -30,17 +30,43 @@ #include <stdint.h> #include <pciaccess.h> +#include <stdbool.h> -/* register access helpers from intel_mmio.c */ extern void *igt_global_mmio; -void intel_mmio_use_pci_bar(struct pci_device *pci_dev); -void intel_mmio_use_dump_file(char *file); -int intel_register_access_init(struct pci_device *pci_dev, int safe, int fd); -void intel_register_access_fini(void); -uint32_t intel_register_read(uint32_t reg); -void intel_register_write(uint32_t reg, uint32_t val); -int intel_register_access_needs_fakewake(void); +/* register access helpers from intel_mmio.c */ +struct intel_register_range { + uint32_t base; + uint32_t size; + uint32_t flags; +}; + +struct intel_register_map { + struct intel_register_range *map; + uint32_t top; + uint32_t alignment_mask; +}; + +struct mmio_data { + int inited; + bool safe; + uint32_t i915_devid; + struct intel_register_map map; + int key; + void *igt_mmio; +}; + +void intel_mmio_use_pci_bar(struct mmio_data *mmio_data, + struct pci_device *pci_dev); +void intel_mmio_use_dump_file(struct mmio_data *mmio_data, char *file); + +int intel_register_access_init(struct mmio_data *mmio_data, + struct pci_device *pci_dev, int safe, int fd); +void intel_register_access_fini(struct mmio_data *mmio_data); +uint32_t intel_register_read(struct mmio_data *mmio_data, uint32_t reg); +void intel_register_write(struct mmio_data *mmio_data, uint32_t reg, + uint32_t val); +int intel_register_access_needs_fakewake(struct mmio_data *mmio_data); uint32_t INREG(uint32_t reg); uint16_t INREG16(uint32_t reg); @@ -57,17 +83,24 @@ void OUTREG16_DEV(void *igt_mmio, uint32_t reg, uint16_t val); void OUTREG8_DEV(void *igt_mmio, uint32_t reg, uint8_t val); /* sideband access functions from intel_iosf.c */ -uint32_t intel_dpio_reg_read(uint32_t reg, int phy); -void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy); -uint32_t intel_flisdsi_reg_read(uint32_t reg); -void intel_flisdsi_reg_write(uint32_t reg, uint32_t val); -uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg); -void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val); - -int intel_punit_read(uint32_t addr, uint32_t *val); -int intel_punit_write(uint32_t addr, uint32_t val); -int intel_nc_read(uint32_t addr, uint32_t *val); -int intel_nc_write(uint32_t addr, uint32_t val); +uint32_t intel_dpio_reg_read(struct mmio_data *mmio_data, uint32_t reg, + int phy); +void intel_dpio_reg_write(struct mmio_data *mmio_data, uint32_t reg, + uint32_t val, int phy); +uint32_t intel_flisdsi_reg_read(struct mmio_data *mmio_data, uint32_t reg); +void intel_flisdsi_reg_write(struct mmio_data *mmio_data, uint32_t reg, + uint32_t val); +uint32_t intel_iosf_sb_read(struct mmio_data *mmio_data, uint32_t port, + uint32_t reg); +void intel_iosf_sb_write(struct mmio_data *mmio_data, uint32_t port, + uint32_t reg, uint32_t val); + +int intel_punit_read(struct mmio_data *mmio_data, uint32_t addr, + uint32_t *val); +int intel_punit_write(struct mmio_data *mmio_data, uint32_t addr, + uint32_t val); +int intel_nc_read(struct mmio_data *mmio_data, uint32_t addr, uint32_t *val); +int intel_nc_write(struct mmio_data *mmio_data, uint32_t addr, uint32_t val); /* register maps from intel_reg_map.c */ #ifndef __GTK_DOC_IGNORE__ @@ -78,17 +111,6 @@ int intel_nc_write(uint32_t addr, uint32_t val); #define INTEL_RANGE_RW (INTEL_RANGE_READ | INTEL_RANGE_WRITE) #define INTEL_RANGE_END (1<<31) -struct intel_register_range { - uint32_t base; - uint32_t size; - uint32_t flags; -}; - -struct intel_register_map { - struct intel_register_range *map; - uint32_t top; - uint32_t alignment_mask; -}; struct intel_register_map intel_get_register_map(uint32_t devid); struct intel_register_range *intel_get_register_range(struct intel_register_map map, uint32_t offset, uint32_t mode); #endif /* __GTK_DOC_IGNORE__ */ diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c index 3b5a1370..e7a89953 100644 --- a/lib/intel_iosf.c +++ b/lib/intel_iosf.c @@ -19,8 +19,8 @@ /* Private register write, double-word addressing, non-posted */ #define SB_CRWRDA_NP 0x07 -static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr, - uint32_t *val) +static int vlv_sideband_rw(struct mmio_data *mmio_data, uint32_t port, + uint8_t opcode, uint32_t addr, uint32_t *val) { int timeout = 0; uint32_t cmd, devfn, be, bar; @@ -34,22 +34,24 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr, (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | (bar << IOSF_BAR_SHIFT); - if (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) { + if (intel_register_read(mmio_data, VLV_IOSF_DOORBELL_REQ) & + IOSF_SB_BUSY) { igt_warn("warning: pcode (%s) mailbox access failed\n", is_read ? "read" : "write"); return -EAGAIN; } - intel_register_write(VLV_IOSF_ADDR, addr); + intel_register_write(mmio_data, VLV_IOSF_ADDR, addr); if (!is_read) - intel_register_write(VLV_IOSF_DATA, *val); + intel_register_write(mmio_data, VLV_IOSF_DATA, *val); - intel_register_write(VLV_IOSF_DOORBELL_REQ, cmd); + intel_register_write(mmio_data, VLV_IOSF_DOORBELL_REQ, cmd); do { usleep(1); timeout++; - } while (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY && - timeout < TIMEOUT_US); + } while (intel_register_read(mmio_data->igt_mmio, + VLV_IOSF_DOORBELL_REQ) & + IOSF_SB_BUSY && timeout < TIMEOUT_US); if (timeout >= TIMEOUT_US) { igt_warn("timeout waiting for pcode %s (%d) to finish\n", is_read ? "read" : "write", addr); @@ -57,8 +59,8 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr, } if (is_read) - *val = intel_register_read(VLV_IOSF_DATA); - intel_register_write(VLV_IOSF_DATA, 0); + *val = intel_register_read(mmio_data->igt_mmio, VLV_IOSF_DATA); + intel_register_write(mmio_data->igt_mmio, VLV_IOSF_DATA, 0); return 0; } @@ -73,9 +75,10 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr, * Returns: * 0 when the register access succeeded, negative errno code on failure. */ -int intel_punit_read(uint32_t addr, uint32_t *val) +int intel_punit_read(struct mmio_data *mmio_data, uint32_t addr, uint32_t *val) { - return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr, val); + return vlv_sideband_rw(mmio_data, IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr, + val); } /** @@ -88,9 +91,10 @@ int intel_punit_read(uint32_t addr, uint32_t *val) * Returns: * 0 when the register access succeeded, negative errno code on failure. */ -int intel_punit_write(uint32_t addr, uint32_t val) +int intel_punit_write(struct mmio_data *mmio_data, uint32_t addr, uint32_t val) { - return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr, &val); + return vlv_sideband_rw(mmio_data, IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr, + &val); } /** @@ -103,9 +107,10 @@ int intel_punit_write(uint32_t addr, uint32_t val) * Returns: * 0 when the register access succeeded, negative errno code on failure. */ -int intel_nc_read(uint32_t addr, uint32_t *val) +int intel_nc_read(struct mmio_data *mmio_data, uint32_t addr, uint32_t *val) { - return vlv_sideband_rw(IOSF_PORT_NC, SB_CRRDDA_NP, addr, val); + return vlv_sideband_rw(mmio_data, IOSF_PORT_NC, SB_CRRDDA_NP, addr, + val); } /** @@ -118,9 +123,10 @@ int intel_nc_read(uint32_t addr, uint32_t *val) * Returns: * 0 when the register access succeeded, negative errno code on failure. */ -int intel_nc_write(uint32_t addr, uint32_t val) +int intel_nc_write(struct mmio_data *mmio_data, uint32_t addr, uint32_t val) { - return vlv_sideband_rw(IOSF_PORT_NC, SB_CRWRDA_NP, addr, &val); + return vlv_sideband_rw(mmio_data, IOSF_PORT_NC, SB_CRWRDA_NP, addr, + &val); } /** @@ -133,14 +139,16 @@ int intel_nc_write(uint32_t addr, uint32_t val) * Returns: * The value read from the register. */ -uint32_t intel_dpio_reg_read(uint32_t reg, int phy) +uint32_t intel_dpio_reg_read(struct mmio_data *mmio_data, uint32_t reg, int phy) { uint32_t val; if (phy == 0) - vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val); + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO, SB_MRD_NP, reg, + &val); else - vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MRD_NP, reg, &val); + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO_2, SB_MRD_NP, reg, + &val); return val; } @@ -152,38 +160,40 @@ uint32_t intel_dpio_reg_read(uint32_t reg, int phy) * * 32-bit write of the register at @offset through the DPIO sideband port. */ -void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy) +void intel_dpio_reg_write(struct mmio_data *mmio_data, uint32_t reg, uint32_t val, int phy) { if (phy == 0) - vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val); + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO, SB_MWR_NP, reg, &val); else - vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MWR_NP, reg, &val); + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO_2, SB_MWR_NP, reg, + &val); } -uint32_t intel_flisdsi_reg_read(uint32_t reg) +uint32_t intel_flisdsi_reg_read(struct mmio_data *mmio_data, uint32_t reg) { uint32_t val = 0; - vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val); + vlv_sideband_rw(mmio_data, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val); return val; } -void intel_flisdsi_reg_write(uint32_t reg, uint32_t val) +void intel_flisdsi_reg_write(struct mmio_data *mmio_data, uint32_t reg, uint32_t val) { - vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val); + vlv_sideband_rw(mmio_data, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val); } -uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg) +uint32_t intel_iosf_sb_read(struct mmio_data *mmio_data, uint32_t port, uint32_t reg) { uint32_t val; - vlv_sideband_rw(port, SB_CRRDDA_NP, reg, &val); + vlv_sideband_rw(mmio_data, port, SB_CRRDDA_NP, reg, &val); return val; } -void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val) +void intel_iosf_sb_write(struct mmio_data *mmio_data, uint32_t port, + uint32_t reg, uint32_t val) { - vlv_sideband_rw(port, SB_CRWRDA_NP, reg, &val); + vlv_sideband_rw(mmio_data, port, SB_CRWRDA_NP, reg, &val); } diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c index 01411c37..d77aaba8 100644 --- a/lib/intel_mmio.c +++ b/lib/intel_mmio.c @@ -73,54 +73,53 @@ */ void *igt_global_mmio; -static struct _mmio_data { - int inited; - bool safe; - uint32_t i915_devid; - struct intel_register_map map; - int key; -} mmio_data; - /** * intel_mmio_use_dump_file: + * @mmio_data: mmio structure for IO operations * @file: name of the register dump file to open * - * Sets up #igt_global_mmio to point at the data contained in @file. This allows - * the same code to get reused for dumping and decoding from running hardware as - * from register dumps. + * Sets also up mmio_data->igt_mmio to point at the data contained + * in @file. This allows the same code to get reused for dumping and decoding + * from running hardware as from register dumps. */ void -intel_mmio_use_dump_file(char *file) +intel_mmio_use_dump_file(struct mmio_data *mmio_data, char *file) { int fd; struct stat st; + memset(mmio_data, 0, sizeof(struct mmio_data)); fd = open(file, O_RDWR); igt_fail_on_f(fd == -1, "Couldn't open %s\n", file); fstat(fd, &st); - igt_global_mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0); - igt_fail_on_f(igt_global_mmio == MAP_FAILED, + mmio_data->igt_mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0); + igt_fail_on_f(mmio_data->igt_mmio == MAP_FAILED, "Couldn't mmap %s\n", file); + + igt_global_mmio = mmio_data->igt_mmio; + close(fd); } /** * intel_mmio_use_pci_bar: + * @mmio_data: mmio structure for IO operations * @pci_dev: intel gracphis pci device * - * Sets up #igt_global_mmio to point at the mmio bar. + * Fill a mmio_data stucture with igt_mmio to point at the mmio bar. * * @pci_dev can be obtained from intel_get_pci_device(). */ void -intel_mmio_use_pci_bar(struct pci_device *pci_dev) +intel_mmio_use_pci_bar(struct mmio_data *mmio_data, struct pci_device *pci_dev) { uint32_t devid, gen; int mmio_bar, mmio_size; int error; + memset(mmio_data, 0, sizeof(struct mmio_data)); devid = pci_dev->device_id; if (IS_GEN2(devid)) mmio_bar = 1; @@ -139,7 +138,9 @@ intel_mmio_use_pci_bar(struct pci_device *pci_dev) pci_dev->regions[mmio_bar].base_addr, mmio_size, PCI_DEV_MAP_FLAG_WRITABLE, - &igt_global_mmio); + &mmio_data->igt_mmio); + + igt_global_mmio = mmio_data->igt_mmio; igt_fail_on_f(error != 0, "Couldn't map MMIO region\n"); @@ -153,6 +154,7 @@ release_forcewake_lock(int fd) /** * intel_register_access_init: + * @mmio_data: mmio structure for IO operations * @pci_dev: intel graphics pci device * @safe: use safe register access tables * @@ -160,76 +162,77 @@ release_forcewake_lock(int fd) * handling and also allows register access to be checked with an explicit * whitelist. * - * It also initializes #igt_global_mmio like intel_mmio_use_pci_bar(). + * It also initializes mmio_data->igt_mmio like intel_mmio_use_pci_bar(). * * @pci_dev can be obtained from intel_get_pci_device(). */ int -intel_register_access_init(struct pci_device *pci_dev, int safe, int fd) +intel_register_access_init(struct mmio_data *mmio_data, struct pci_device *pci_dev, int safe, int fd) { int ret; - /* after old API is deprecated, remove this */ - if (igt_global_mmio == NULL) - intel_mmio_use_pci_bar(pci_dev); + intel_mmio_use_pci_bar(mmio_data, pci_dev); - igt_assert(igt_global_mmio != NULL); + igt_assert(mmio_data->igt_mmio != NULL); - if (mmio_data.inited) + if (mmio_data->inited) return -1; - mmio_data.safe = (safe != 0 && + mmio_data->safe = (safe != 0 && intel_gen(pci_dev->device_id) >= 4) ? true : false; - mmio_data.i915_devid = pci_dev->device_id; - if (mmio_data.safe) - mmio_data.map = intel_get_register_map(mmio_data.i915_devid); + mmio_data->i915_devid = pci_dev->device_id; + if (mmio_data->safe) + mmio_data->map = intel_get_register_map(mmio_data->i915_devid); /* Find where the forcewake lock is. Forcewake doesn't exist * gen < 6, but the debugfs should do the right things for us. */ ret = igt_open_forcewake_handle(fd); if (ret == -1) - mmio_data.key = FAKEKEY; + mmio_data->key = FAKEKEY; else - mmio_data.key = ret; + mmio_data->key = ret; - mmio_data.inited++; + mmio_data->inited++; return 0; } static int -intel_register_access_needs_wake(void) +intel_register_access_needs_wake(struct mmio_data *mmio_data) { - return mmio_data.key != FAKEKEY; + return mmio_data->key != FAKEKEY; } /** * intel_register_access_needs_fakewake: + * @mmio_data: mmio structure for IO operations * * Returns: * Non-zero when forcewake initialization failed. */ -int intel_register_access_needs_fakewake(void) +int intel_register_access_needs_fakewake(struct mmio_data *mmio_data) { - return mmio_data.key == FAKEKEY; + return mmio_data->key == FAKEKEY; } /** * intel_register_access_fini: + * @mmio_data: mmio structure for IO operations * * Clean up the register access helper initialized with * intel_register_access_init(). */ void -intel_register_access_fini(void) +intel_register_access_fini(struct mmio_data *mmio_data) { - if (mmio_data.key && intel_register_access_needs_wake()) - release_forcewake_lock(mmio_data.key); - mmio_data.inited--; + if (mmio_data->key && intel_register_access_needs_wake(mmio_data)) + release_forcewake_lock(mmio_data->key); + mmio_data->inited--; } /** * intel_register_read: + * @mmio_data: mmio structure for IO operations * @reg: register offset * * 32-bit read of the register at @offset. This function only works when the new @@ -242,20 +245,20 @@ intel_register_access_fini(void) * The value read from the register. */ uint32_t -intel_register_read(uint32_t reg) +intel_register_read(struct mmio_data *mmio_data, uint32_t reg) { struct intel_register_range *range; uint32_t ret; - igt_assert(mmio_data.inited); + igt_assert(mmio_data->inited); - if (intel_gen(mmio_data.i915_devid) >= 6) - igt_assert(mmio_data.key != -1); + if (intel_gen(mmio_data->i915_devid) >= 6) + igt_assert(mmio_data->key != -1); - if (!mmio_data.safe) + if (!mmio_data->safe) goto read_out; - range = intel_get_register_range(mmio_data.map, + range = intel_get_register_range(mmio_data->map, reg, INTEL_RANGE_READ); @@ -266,13 +269,14 @@ intel_register_read(uint32_t reg) } read_out: - ret = *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg); + ret = *(volatile uint32_t *)((volatile char *)mmio_data->igt_mmio + reg); out: return ret; } /** * intel_register_write: + * @mmio_data: mmio structure for IO operations * @reg: register offset * @val: value to write * @@ -283,19 +287,19 @@ out: * white lists. */ void -intel_register_write(uint32_t reg, uint32_t val) +intel_register_write(struct mmio_data *mmio_data, uint32_t reg, uint32_t val) { struct intel_register_range *range; - igt_assert(mmio_data.inited); + igt_assert(mmio_data->inited); - if (intel_gen(mmio_data.i915_devid) >= 6) - igt_assert(mmio_data.key != -1); + if (intel_gen(mmio_data->i915_devid) >= 6) + igt_assert(mmio_data->key != -1); - if (!mmio_data.safe) + if (!mmio_data->safe) goto write_out; - range = intel_get_register_range(mmio_data.map, + range = intel_get_register_range(mmio_data->map, reg, INTEL_RANGE_WRITE); @@ -303,7 +307,7 @@ intel_register_write(uint32_t reg, uint32_t val) "Register write blocked for safety ""(*0x%08x = 0x%x)\n", reg, val); write_out: - *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg) = val; + *(volatile uint32_t *)((volatile char *)mmio_data->igt_mmio + reg) = val; } diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c index e56d6278..b96a8409 100644 --- a/tests/i915/gem_exec_latency.c +++ b/tests/i915/gem_exec_latency.c @@ -61,6 +61,8 @@ static unsigned int ring_size; static double rcs_clock; +static struct mmio_data mmio_data; + static void poll_ring(int fd, unsigned ring, const char *name) @@ -667,7 +669,7 @@ igt_main if (ring_size > 1024) ring_size = 1024; - intel_register_access_init(intel_get_pci_device(), false, device); + intel_register_access_init(&mmio_data, intel_get_pci_device(), false, device); rcs_clock = clockrate(device, RCS_TIMESTAMP); igt_info("RCS timestamp clock: %.0fKHz, %.1fns\n", rcs_clock / 1e3, 1e9 / rcs_clock); diff --git a/tests/i915/gem_exec_parse.c b/tests/i915/gem_exec_parse.c index 62e8d0a5..ef97ff4f 100644 --- a/tests/i915/gem_exec_parse.c +++ b/tests/i915/gem_exec_parse.c @@ -58,6 +58,9 @@ static int parser_version; +struct mmio_data mmio_data; + + static int command_parser_version(int fd) { int version = -1; @@ -284,9 +287,9 @@ test_lri(int fd, uint32_t handle, struct test_lri *test) test->name, test->reg, test->test_val, expected_errno, expect); - intel_register_write(test->reg, test->init_val); + intel_register_write(&mmio_data, test->reg, test->init_val); - igt_assert_eq_u32((intel_register_read(test->reg) & + igt_assert_eq_u32((intel_register_read(&mmio_data, test->reg) & test->read_mask), test->init_val); @@ -296,7 +299,7 @@ test_lri(int fd, uint32_t handle, struct test_lri *test) expected_errno); gem_sync(fd, handle); - igt_assert_eq_u32((intel_register_read(test->reg) & + igt_assert_eq_u32((intel_register_read(&mmio_data, test->reg) & test->read_mask), expect); } @@ -530,7 +533,7 @@ igt_main #undef REG igt_fixture { - intel_register_access_init(intel_get_pci_device(), 0, fd); + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, fd); } for (int i = 0; i < ARRAY_SIZE(lris); i++) { @@ -543,7 +546,7 @@ igt_main } igt_fixture { - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); } } diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c index 81c356f0..631fdf8f 100644 --- a/tests/i915/gem_workarounds.c +++ b/tests/i915/gem_workarounds.c @@ -225,6 +225,7 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags) igt_main { + struct mmio_data mmio_data; int device = -1; const struct { const char *name; @@ -256,7 +257,7 @@ igt_main device = drm_open_driver(DRIVER_INTEL); igt_require_gem(device); - intel_mmio_use_pci_bar(intel_get_pci_device()); + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device()); gen = intel_gen(intel_get_drm_devid(device)); diff --git a/tests/i915/i915_pm_lpsp.c b/tests/i915/i915_pm_lpsp.c index b319dbe9..3b486d30 100644 --- a/tests/i915/i915_pm_lpsp.c +++ b/tests/i915/i915_pm_lpsp.c @@ -187,7 +187,7 @@ int drm_fd; uint32_t devid; drmModeResPtr drm_res; drmModeConnectorPtr drm_connectors[MAX_CONNECTORS]; - +struct mmio_data mmio_data; igt_main { igt_fixture { @@ -210,7 +210,7 @@ igt_main igt_require(supports_lpsp(devid)); - intel_register_access_init(intel_get_pci_device(), 0, drm_fd); + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, drm_fd); kmstest_set_vt_graphics_mode(); } @@ -227,7 +227,7 @@ igt_main igt_fixture { int i; - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); for (i = 0; i < drm_res->count_connectors; i++) drmModeFreeConnector(drm_connectors[i]); drmModeFreeResources(drm_res); diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c index 726bb4b6..25ba918f 100644 --- a/tools/intel_audio_dump.c +++ b/tools/intel_audio_dump.c @@ -42,6 +42,7 @@ static uint32_t devid; static int aud_reg_base = 0; /* base address of audio registers */ static int disp_reg_base = 0; /* base address of display registers */ + #define IS_HASWELL_PLUS(devid) (IS_HASWELL(devid) || IS_BROADWELL(devid)) #define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1) @@ -2464,6 +2465,7 @@ static void dump_braswell(void) int main(int argc, char **argv) { struct pci_device *pci_dev; + struct mmio_data mmio_data; pci_dev = intel_get_pci_device(); devid = pci_dev->device_id; /* XXX not true when mapping! */ @@ -2471,9 +2473,9 @@ int main(int argc, char **argv) do_self_tests(); if (argc == 2) - intel_mmio_use_dump_file(argv[1]); + intel_mmio_use_dump_file(&mmio_data, argv[1]); else - intel_mmio_use_pci_bar(pci_dev); + intel_mmio_use_pci_bar(&mmio_data, pci_dev); printf("%s audio registers:\n\n", intel_get_device_info(devid)->codename); if (IS_VALLEYVIEW(devid)) { diff --git a/tools/intel_backlight.c b/tools/intel_backlight.c index 067fd418..2cdb5276 100644 --- a/tools/intel_backlight.c +++ b/tools/intel_backlight.c @@ -38,9 +38,11 @@ int main(int argc, char** argv) { + struct mmio_data mmio_data; uint32_t current, max; - intel_mmio_use_pci_bar(intel_get_pci_device()); + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device()); + igt_global_mmio = mmio_data.igt_mmio; current = INREG(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; max = INREG(BLC_PWM_PCH_CTL2) >> 16; diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c index 51f5b9a5..4ac97766 100644 --- a/tools/intel_display_poller.c +++ b/tools/intel_display_poller.c @@ -962,6 +962,7 @@ static void __attribute__((noreturn)) usage(const char *name) int main(int argc, char *argv[]) { + struct mmio_data mmio_data; int i; int pipe = 0, bit = 0, target_scanline = 0, target_fuzz = 1; bool test_pixelcount = false; @@ -1187,7 +1188,7 @@ int main(int argc, char *argv[]) break; } - intel_register_access_init(intel_get_pci_device(), 0, -1); + intel_register_access_init(&mmio_data ,intel_get_pci_device(), 0, -1); printf("%s?\n", test_name(test, pipe, bit, test_pixelcount)); @@ -1262,7 +1263,7 @@ int main(int argc, char *argv[]) assert(0); } - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); if (quit) return 0; diff --git a/tools/intel_forcewaked.c b/tools/intel_forcewaked.c index 02fbf888..f4114612 100644 --- a/tools/intel_forcewaked.c +++ b/tools/intel_forcewaked.c @@ -57,14 +57,15 @@ help(char *prog) { } static int -is_alive(void) { +is_alive(struct mmio_data *mmio_data) { /* Read the timestamp, which should *almost* always be !0 */ - return (intel_register_read(0x2358) != 0); + return (intel_register_read(mmio_data, 0x2358) != 0); } int main(int argc, char *argv[]) { int ret; + struct mmio_data mmio_data; if (argc > 2 || (argc == 2 && !strncmp(argv[1], "-h", 2))) { help(argv[1]); @@ -80,7 +81,7 @@ int main(int argc, char *argv[]) INFO_PRINT("started daemon"); } - ret = intel_register_access_init(intel_get_pci_device(), 1, -1); + ret = intel_register_access_init(&mmio_data, intel_get_pci_device(), 1, -1); if (ret) { INFO_PRINT("Couldn't init register access\n"); exit(1); @@ -88,16 +89,16 @@ int main(int argc, char *argv[]) INFO_PRINT("Forcewake locked\n"); } while(1) { - if (!is_alive()) { + if (!is_alive(&mmio_data)) { INFO_PRINT("gpu reset? restarting daemon\n"); - intel_register_access_fini(); - ret = intel_register_access_init(intel_get_pci_device(), 1, -1); + intel_register_access_fini(&mmio_data); + ret = intel_register_access_init(&mmio_data, intel_get_pci_device(), 1, -1); if (ret) INFO_PRINT("Reg access init fail\n"); } sleep(1); } - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); INFO_PRINT("Forcewake unlock\n"); if (daemonized) { diff --git a/tools/intel_gpu_time.c b/tools/intel_gpu_time.c index 56d65fe0..15aa0041 100644 --- a/tools/intel_gpu_time.c +++ b/tools/intel_gpu_time.c @@ -65,9 +65,10 @@ int main(int argc, char **argv) uint64_t ring_idle = 0, ring_time = 0; struct timeval start, end; static struct rusage rusage; + struct mmio_data mmio_data; int status; - intel_mmio_use_pci_bar(intel_get_pci_device()); + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device()); if (argc == 1) { fprintf(stderr, "usage: %s cmd [args...]\n", argv[0]); diff --git a/tools/intel_infoframes.c b/tools/intel_infoframes.c index 2ef5d4fd..fbf53c23 100644 --- a/tools/intel_infoframes.c +++ b/tools/intel_infoframes.c @@ -264,6 +264,7 @@ const char *dip_frequency_names[] = { struct pci_device *pci_dev; int gen = 0; +struct mmio_data mmio_data; static const char *spd_source_to_string(SourceDevice source) { @@ -1108,7 +1109,7 @@ int main(int argc, char *argv[]) " perfectly: the Kernel might undo our changes.\n"); pci_dev = intel_get_pci_device(); - intel_register_access_init(pci_dev, 0, -1); + intel_register_access_init(&mmio_data, pci_dev, 0, -1); intel_check_pch(); if (IS_GEN4(pci_dev->device_id)) @@ -1256,6 +1257,6 @@ int main(int argc, char *argv[]) } out: - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); return ret; } diff --git a/tools/intel_l3_parity.c b/tools/intel_l3_parity.c index 4179c5ae..712de230 100644 --- a/tools/intel_l3_parity.c +++ b/tools/intel_l3_parity.c @@ -176,6 +176,7 @@ static void usage(const char *name) int main(int argc, char *argv[]) { + struct mmio_data mmio_data; const char *path[REAL_MAX_SLICES] = {"l3_parity", "l3_parity_slice_1"}; int row = 0, bank = 0, sbank = 0; int fd[REAL_MAX_SLICES] = {0}, ret, i; @@ -189,7 +190,7 @@ int main(int argc, char *argv[]) if (intel_gen(devid) < 7 || IS_VALLEYVIEW(devid)) exit(77); - assert(intel_register_access_init(intel_get_pci_device(), 0, device) == 0); + assert(intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, device) == 0); dir = igt_sysfs_open(device); @@ -217,7 +218,7 @@ int main(int argc, char *argv[]) * now. Just be aware of this if for some reason a hang is reported * when using this tool. */ - dft = intel_register_read(0xb038); + dft = intel_register_read(&mmio_data, 0xb038); while (1) { int c, option_index = 0; @@ -366,10 +367,10 @@ int main(int argc, char *argv[]) assert(i < 2); dft |= i << 1; /* slice */ dft |= 1 << 0; /* enable */ - intel_register_write(0xb038, dft); + intel_register_write(&mmio_data, 0xb038, dft); break; case 'u': - intel_register_write(0xb038, dft & ~(1<<0)); + intel_register_write(&mmio_data ,0xb038, dft & ~(1<<0)); break; case 'L': break; @@ -378,7 +379,7 @@ int main(int argc, char *argv[]) } } - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); if (action == 'l') exit(EXIT_SUCCESS); diff --git a/tools/intel_lid.c b/tools/intel_lid.c index 37c6ba5e..52176833 100644 --- a/tools/intel_lid.c +++ b/tools/intel_lid.c @@ -117,9 +117,10 @@ out: int main(int argc, char **argv) { + struct mmio_data mmio_data; int swf14, acpi_lid; - intel_mmio_use_pci_bar(intel_get_pci_device()); + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device()); while (1) { swf14 = INREG(SWF14); diff --git a/tools/intel_panel_fitter.c b/tools/intel_panel_fitter.c index 137ef61a..03b42596 100644 --- a/tools/intel_panel_fitter.c +++ b/tools/intel_panel_fitter.c @@ -273,6 +273,7 @@ int main (int argc, char *argv[]) bool do_disable = false, do_dump = false, do_usage = false; struct pci_device *pci_dev; uint32_t devid; + struct mmio_data mmio_data; printf("WARNING:\n" "This tool is a workaround for people that don't have a Kernel " @@ -280,7 +281,7 @@ int main (int argc, char *argv[]) "solution that may or may not work. Use it at your own risk.\n"); pci_dev = intel_get_pci_device(); - intel_register_access_init(pci_dev, 0, -1); + intel_register_access_init(&mmio_data, pci_dev, 0, -1); devid = pci_dev->device_id; if (!HAS_PCH_SPLIT(devid)) { @@ -342,6 +343,6 @@ int main (int argc, char *argv[]) } out: - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); return ret; } diff --git a/tools/intel_perf_counters.c b/tools/intel_perf_counters.c index 50c4bce6..a29ef1b2 100644 --- a/tools/intel_perf_counters.c +++ b/tools/intel_perf_counters.c @@ -441,6 +441,7 @@ gen7_get_counters(void) int main(int argc, char **argv) { + struct mmio_data mmio_data; uint32_t devid; int counter_format; int counter_count; @@ -483,10 +484,11 @@ main(int argc, char **argv) if (oacontrol) { /* Forcewake */ - intel_register_access_init(intel_get_pci_device(), 0, fd); + intel_register_access_init(&mmio_data, intel_get_pci_device(), + 0, fd); /* Enable performance counters */ - intel_register_write(OACONTROL, + intel_register_write(&mmio_data, OACONTROL, counter_format << OACONTROL_COUNTER_SELECT_SHIFT | PERFORMANCE_COUNTER_ENABLE); } @@ -520,10 +522,10 @@ main(int argc, char **argv) if (oacontrol) { /* Disable performance counters */ - intel_register_write(OACONTROL, 0); + intel_register_write(&mmio_data, OACONTROL, 0); /* Forcewake */ - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); } free(totals); diff --git a/tools/intel_reg.c b/tools/intel_reg.c index e517956b..c8cdb377 100644 --- a/tools/intel_reg.c +++ b/tools/intel_reg.c @@ -57,6 +57,7 @@ static inline int _not_supported(void) struct config { struct pci_device *pci_dev; + struct mmio_data mmio_data; char *mmiofile; uint32_t devid; @@ -387,7 +388,7 @@ static int read_register(struct config *config, struct reg *reg, uint32_t *valp) reg->port_desc.name); return -1; } - val = intel_iosf_sb_read(reg->port_desc.port, reg->addr); + val = intel_iosf_sb_read(&config->mmio_data, reg->port_desc.port, reg->addr); break; default: fprintf(stderr, "port %d not supported\n", reg->port_desc.port); @@ -458,7 +459,7 @@ static int write_register(struct config *config, struct reg *reg, uint32_t val) reg->port_desc.name); return -1; } - intel_iosf_sb_write(reg->port_desc.port, reg->addr, val); + intel_iosf_sb_write(&config->mmio_data, reg->port_desc.port, reg->addr, val); break; default: fprintf(stderr, "port %d not supported\n", reg->port_desc.port); @@ -552,9 +553,9 @@ static int intel_reg_read(struct config *config, int argc, char *argv[]) } if (config->mmiofile) - intel_mmio_use_dump_file(config->mmiofile); + intel_mmio_use_dump_file(&config->mmio_data, config->mmiofile); else - intel_register_access_init(config->pci_dev, 0, -1); + intel_register_access_init(&config->mmio_data, config->pci_dev, 0, -1); for (i = 1; i < argc; i++) { struct reg reg; @@ -570,7 +571,7 @@ static int intel_reg_read(struct config *config, int argc, char *argv[]) } } - intel_register_access_fini(); + intel_register_access_fini(&config->mmio_data); return EXIT_SUCCESS; } @@ -584,7 +585,7 @@ static int intel_reg_write(struct config *config, int argc, char *argv[]) return EXIT_FAILURE; } - intel_register_access_init(config->pci_dev, 0, -1); + intel_register_access_init(&config->mmio_data, config->pci_dev, 0, -1); for (i = 1; i < argc; i += 2) { struct reg reg; @@ -609,7 +610,7 @@ static int intel_reg_write(struct config *config, int argc, char *argv[]) write_register(config, ®, val); } - intel_register_access_fini(); + intel_register_access_fini(&config->mmio_data); return EXIT_SUCCESS; } @@ -620,9 +621,9 @@ static int intel_reg_dump(struct config *config, int argc, char *argv[]) int i; if (config->mmiofile) - intel_mmio_use_dump_file(config->mmiofile); + intel_mmio_use_dump_file(&config->mmio_data, config->mmiofile); else - intel_register_access_init(config->pci_dev, 0, -1); + intel_register_access_init(&config->mmio_data, config->pci_dev, 0, -1); for (i = 0; i < config->regcount; i++) { reg = &config->regs[i]; @@ -634,7 +635,7 @@ static int intel_reg_dump(struct config *config, int argc, char *argv[]) dump_register(config, &config->regs[i]); } - intel_register_access_fini(); + intel_register_access_fini(&config->mmio_data); return EXIT_SUCCESS; } @@ -648,7 +649,7 @@ static int intel_reg_snapshot(struct config *config, int argc, char *argv[]) return EXIT_FAILURE; } - intel_mmio_use_pci_bar(config->pci_dev); + intel_mmio_use_pci_bar(&config->mmio_data, config->pci_dev); /* XXX: error handling */ if (write(1, igt_global_mmio, config->pci_dev->regions[mmio_bar].size) == -1) diff --git a/tools/intel_reg_checker.c b/tools/intel_reg_checker.c index 6bde63ec..73404d02 100644 --- a/tools/intel_reg_checker.c +++ b/tools/intel_reg_checker.c @@ -342,10 +342,11 @@ check_dpfc_control_sa(void) int main(int argc, char** argv) { struct pci_device *dev; + struct mmio_data mmio_data; dev = intel_get_pci_device(); devid = dev->device_id; - intel_mmio_use_pci_bar(dev); + intel_mmio_use_pci_bar(&mmio_data, dev); if (IS_GEN7(devid)) gen = 7; diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c index e71c3d9c..09e9bf36 100644 --- a/tools/intel_watermark.c +++ b/tools/intel_watermark.c @@ -237,6 +237,7 @@ static const char *skl_nv12_buf_cfg_reg_name(int pipe, int plane) static void skl_wm_dump(void) { + struct mmio_data mmio_data; int pipe, plane, level; int num_pipes = 3; int max_planes = skl_max_planes(devid); @@ -249,7 +250,7 @@ static void skl_wm_dump(void) uint32_t plane_ctl[num_pipes][max_planes]; uint32_t wm_linetime[num_pipes]; - intel_register_access_init(intel_get_pci_device(), 0, -1); + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); for (pipe = 0; pipe < num_pipes; pipe++) { int num_planes = skl_num_planes(devid, pipe); @@ -458,6 +459,7 @@ static void skl_wm_dump(void) static void ilk_wm_dump(void) { + struct mmio_data mmio_data; int i; uint32_t dspcntr[3]; uint32_t spcntr[3]; @@ -469,7 +471,7 @@ static void ilk_wm_dump(void) int num_pipes = intel_gen(devid) >= 7 ? 3 : 2; struct ilk_wm wm = {}; - intel_register_access_init(intel_get_pci_device(), 0, -1); + intel_register_access_init(&mmio_data,intel_get_pci_device(), 0, -1); for (i = 0; i < num_pipes; i++) { dspcntr[i] = read_reg(0x70180 + i * 0x1000); @@ -505,7 +507,7 @@ static void ilk_wm_dump(void) if (IS_BROADWELL(devid) || IS_HASWELL(devid)) wm_misc = read_reg(0x45260); - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); for (i = 0; i < num_pipes; i++) printf(" WM_PIPE_%c = 0x%08x\n", pipe_name(i), wm_pipe[i]); @@ -610,6 +612,7 @@ static void ilk_wm_dump(void) static void vlv_wm_dump(void) { + struct mmio_data mmio_data; int i; unsigned int num_pipes = IS_CHERRYVIEW(devid) ? 3 : 2; uint32_t dsparb, dsparb2, dsparb3; @@ -619,7 +622,7 @@ static void vlv_wm_dump(void) uint32_t dsp_ss_pm, ddr_setup2; struct gmch_wm wms[MAX_PLANE] = {}; - intel_register_access_init(intel_get_pci_device(), 0, -1); + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); dsparb = read_reg(0x70030); dsparb2 = read_reg(0x70060); @@ -650,13 +653,13 @@ static void vlv_wm_dump(void) ddl3 = read_reg(0x70058); - intel_punit_read(0x36, &dsp_ss_pm); - intel_punit_read(0x139, &ddr_setup2); + intel_punit_read(&mmio_data, 0x36, &dsp_ss_pm); + intel_punit_read(&mmio_data, 0x139, &ddr_setup2); } else { fw7 = read_reg(0x7007c); } - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); printf(" FW1 = 0x%08x\n", fw1); printf(" FW2 = 0x%08x\n", fw2); @@ -827,6 +830,7 @@ static void vlv_wm_dump(void) static void g4x_wm_dump(void) { + struct mmio_data mmio_data; int i; uint32_t dspacntr, dspbcntr; uint32_t dsparb; @@ -835,7 +839,7 @@ static void g4x_wm_dump(void) uint32_t mi_arb_state; struct gmch_wm wms[MAX_PLANE] = {}; - intel_register_access_init(intel_get_pci_device(), 0, -1); + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); dspacntr = read_reg(0x70180); dspbcntr = read_reg(0x71180); @@ -846,7 +850,7 @@ static void g4x_wm_dump(void) mi_display_power_down = read_reg(0x20e0); mi_arb_state = read_reg(0x20e4); - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); printf(" DSPACNTR = 0x%08x\n", dspacntr); printf(" DSPBCNTR = 0x%08x\n", dspbcntr); @@ -913,6 +917,7 @@ static void g4x_wm_dump(void) static void gen4_wm_dump(void) { + struct mmio_data mmio_data; int i; int totalsize = IS_CRESTLINE(devid) ? 128 : 96; uint32_t dsparb; @@ -921,7 +926,7 @@ static void gen4_wm_dump(void) uint32_t mi_arb_state; struct gmch_wm wms[MAX_PLANE] = {}; - intel_register_access_init(intel_get_pci_device(), 0, -1); + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); dsparb = read_reg(0x70030); fw1 = read_reg(0x70034); @@ -930,7 +935,7 @@ static void gen4_wm_dump(void) mi_display_power_down = read_reg(0x20e0); mi_arb_state = read_reg(0x20e4); - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); printf(" FW1 = 0x%08x\n", fw1); printf(" FW2 = 0x%08x\n", fw2); @@ -983,6 +988,7 @@ static void gen4_wm_dump(void) static void pnv_wm_dump(void) { + struct mmio_data mmio_data; int i; int totalsize = 96; /* FIXME? */ uint32_t dsparb; @@ -992,7 +998,7 @@ static void pnv_wm_dump(void) uint32_t cbr; struct gmch_wm wms[MAX_PLANE] = {}; - intel_register_access_init(intel_get_pci_device(), 0, -1); + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); dsparb = read_reg(0x70030); fw1 = read_reg(0x70034); @@ -1002,7 +1008,7 @@ static void pnv_wm_dump(void) mi_display_power_down = read_reg(0x20e0); mi_arb_state = read_reg(0x20e4); - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); printf(" DSPARB = 0x%08x\n", dsparb); printf(" FW1 = 0x%08x\n", fw1); @@ -1073,6 +1079,7 @@ static void pnv_wm_dump(void) static void gen3_wm_dump(void) { + struct mmio_data mmio_data; int i; int totalsize = IS_945GM(devid) ? 128 : 96; /* FIXME? */ uint32_t dsparb; @@ -1082,7 +1089,7 @@ static void gen3_wm_dump(void) uint32_t mi_arb_state; struct gmch_wm wms[MAX_PLANE] = {}; - intel_register_access_init(intel_get_pci_device(), 0, -1); + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); dsparb = read_reg(0x70030); instpm = read_reg(0x20c0); @@ -1090,7 +1097,7 @@ static void gen3_wm_dump(void) fw_blc_self = read_reg(0x20e0); mi_arb_state = read_reg(0x20e4); - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); printf(" DSPARB = 0x%08x\n", dsparb); printf(" FW_BLC = 0x%016" PRIx64 "\n", fw_blc); @@ -1142,6 +1149,7 @@ static void gen3_wm_dump(void) static void gen2_wm_dump(void) { + struct mmio_data mmio_data; int i; int totalsize; uint32_t dsparb; @@ -1151,7 +1159,7 @@ static void gen2_wm_dump(void) uint32_t mi_state; struct gmch_wm wms[MAX_PLANE] = {}; - intel_register_access_init(intel_get_pci_device(), 0, -1); + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); dsparb = read_reg(0x70030); mem_mode = read_reg(0x20cc); @@ -1159,7 +1167,7 @@ static void gen2_wm_dump(void) fw_blc_self = read_reg(0x20e0); mi_state = read_reg(0x20e4); - intel_register_access_fini(); + intel_register_access_fini(&mmio_data); printf(" DSPARB = 0x%08x\n", dsparb); printf(" MEM_MODE = 0x%08x\n", mem_mode); -- 2.20.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v6 3/3] lib/intel_mmio: add additional api for multiple devices 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 3/3] lib/intel_mmio: add additional api for multiple devices Daniel Mrzyglod @ 2019-08-13 11:21 ` Kempczynski, Zbigniew 0 siblings, 0 replies; 10+ messages in thread From: Kempczynski, Zbigniew @ 2019-08-13 11:21 UTC (permalink / raw) To: Mrzyglod, Daniel T, igt-dev@lists.freedesktop.org On Wed, 2019-07-24 at 14:32 +0200, Daniel Mrzyglod wrote: > this patch extend intel_mmio library by new structure that can keep > local igt_mmio pointer. > The reason that we extend functionality is the idea to support multiple > devices at once. > > Signed-off-by: Daniel Mrzyglod <daniel.t.mrzyglod@intel.com> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > --- > benchmarks/gem_latency.c | 3 +- > benchmarks/gem_wsim.c | 3 +- > lib/intel_io.h | 82 +++++++++++++++---------- > lib/intel_iosf.c | 74 +++++++++++++---------- > lib/intel_mmio.c | 110 ++++++++++++++++++---------------- > tests/i915/gem_exec_latency.c | 4 +- > tests/i915/gem_exec_parse.c | 13 ++-- > tests/i915/gem_workarounds.c | 3 +- > tests/i915/i915_pm_lpsp.c | 6 +- > tools/intel_audio_dump.c | 6 +- > tools/intel_backlight.c | 4 +- > tools/intel_display_poller.c | 5 +- > tools/intel_forcewaked.c | 15 ++--- > tools/intel_gpu_time.c | 3 +- > tools/intel_infoframes.c | 5 +- > tools/intel_l3_parity.c | 11 ++-- > tools/intel_lid.c | 3 +- > tools/intel_panel_fitter.c | 5 +- > tools/intel_perf_counters.c | 10 ++-- > tools/intel_reg.c | 23 +++---- > tools/intel_reg_checker.c | 3 +- > tools/intel_watermark.c | 42 +++++++------ > 22 files changed, 250 insertions(+), 183 deletions(-) > > diff --git a/benchmarks/gem_latency.c b/benchmarks/gem_latency.c > index c3fc4bf0..569faa58 100644 > --- a/benchmarks/gem_latency.c > +++ b/benchmarks/gem_latency.c > @@ -55,6 +55,7 @@ > static int done; > static int fd; > static volatile uint32_t *timestamp_reg; > +static struct mmio_data mmio_data; > > #define REG(x) (volatile uint32_t *)((volatile char *)igt_global_mmio + x) > #define REG_OFFSET(x) ((volatile char *)(x) - (volatile char > *)igt_global_mmio) > @@ -456,7 +457,7 @@ static int run(int seconds, > if (gen < 6) > return IGT_EXIT_SKIP; /* Needs BCS timestamp */ > > - intel_register_access_init(intel_get_pci_device(), false, fd); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), false, > fd); > > if (gen == 6) > timestamp_reg = REG(RCS_TIMESTAMP); > diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c > index a76fdbfe..3c7401df 100644 > --- a/benchmarks/gem_wsim.c > +++ b/benchmarks/gem_wsim.c > @@ -238,6 +238,7 @@ struct workload > } busy_balancer; > }; > > +struct mmio_data mmio_data; > static const unsigned int nop_calibration_us = 1000; > static unsigned long nop_calibration; > > @@ -3071,7 +3072,7 @@ static void init_clocks(void) > uint32_t rcs_start, rcs_end; > double overhead, t; > > - intel_register_access_init(intel_get_pci_device(), false, fd); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), false, > fd); > > if (verbose <= 1) > return; > diff --git a/lib/intel_io.h b/lib/intel_io.h > index 99cb1829..370a9ab1 100644 > --- a/lib/intel_io.h > +++ b/lib/intel_io.h > @@ -30,17 +30,43 @@ > > #include <stdint.h> > #include <pciaccess.h> > +#include <stdbool.h> > > -/* register access helpers from intel_mmio.c */ > extern void *igt_global_mmio; > -void intel_mmio_use_pci_bar(struct pci_device *pci_dev); > -void intel_mmio_use_dump_file(char *file); > > -int intel_register_access_init(struct pci_device *pci_dev, int safe, int > fd); > -void intel_register_access_fini(void); > -uint32_t intel_register_read(uint32_t reg); > -void intel_register_write(uint32_t reg, uint32_t val); > -int intel_register_access_needs_fakewake(void); > +/* register access helpers from intel_mmio.c */ > +struct intel_register_range { > + uint32_t base; > + uint32_t size; > + uint32_t flags; > +}; > + > +struct intel_register_map { > + struct intel_register_range *map; > + uint32_t top; > + uint32_t alignment_mask; > +}; > + > +struct mmio_data { > + int inited; > + bool safe; > + uint32_t i915_devid; > + struct intel_register_map map; > + int key; > + void *igt_mmio; > +}; > + > +void intel_mmio_use_pci_bar(struct mmio_data *mmio_data, > + struct pci_device *pci_dev); > +void intel_mmio_use_dump_file(struct mmio_data *mmio_data, char *file); > + > +int intel_register_access_init(struct mmio_data *mmio_data, > + struct pci_device *pci_dev, int safe, int fd); > +void intel_register_access_fini(struct mmio_data *mmio_data); > +uint32_t intel_register_read(struct mmio_data *mmio_data, uint32_t reg); > +void intel_register_write(struct mmio_data *mmio_data, uint32_t reg, > + uint32_t val); > +int intel_register_access_needs_fakewake(struct mmio_data *mmio_data); > > uint32_t INREG(uint32_t reg); > uint16_t INREG16(uint32_t reg); > @@ -57,17 +83,24 @@ void OUTREG16_DEV(void *igt_mmio, uint32_t reg, uint16_t > val); > void OUTREG8_DEV(void *igt_mmio, uint32_t reg, uint8_t val); > > /* sideband access functions from intel_iosf.c */ > -uint32_t intel_dpio_reg_read(uint32_t reg, int phy); > -void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy); > -uint32_t intel_flisdsi_reg_read(uint32_t reg); > -void intel_flisdsi_reg_write(uint32_t reg, uint32_t val); > -uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg); > -void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val); > - > -int intel_punit_read(uint32_t addr, uint32_t *val); > -int intel_punit_write(uint32_t addr, uint32_t val); > -int intel_nc_read(uint32_t addr, uint32_t *val); > -int intel_nc_write(uint32_t addr, uint32_t val); > +uint32_t intel_dpio_reg_read(struct mmio_data *mmio_data, uint32_t reg, > + int phy); > +void intel_dpio_reg_write(struct mmio_data *mmio_data, uint32_t reg, > + uint32_t val, int phy); > +uint32_t intel_flisdsi_reg_read(struct mmio_data *mmio_data, uint32_t reg); > +void intel_flisdsi_reg_write(struct mmio_data *mmio_data, uint32_t reg, > + uint32_t val); > +uint32_t intel_iosf_sb_read(struct mmio_data *mmio_data, uint32_t port, > + uint32_t reg); > +void intel_iosf_sb_write(struct mmio_data *mmio_data, uint32_t port, > + uint32_t reg, uint32_t val); > + > +int intel_punit_read(struct mmio_data *mmio_data, uint32_t addr, > + uint32_t *val); > +int intel_punit_write(struct mmio_data *mmio_data, uint32_t addr, > + uint32_t val); > +int intel_nc_read(struct mmio_data *mmio_data, uint32_t addr, uint32_t > *val); > +int intel_nc_write(struct mmio_data *mmio_data, uint32_t addr, uint32_t > val); > > /* register maps from intel_reg_map.c */ > #ifndef __GTK_DOC_IGNORE__ > @@ -78,17 +111,6 @@ int intel_nc_write(uint32_t addr, uint32_t val); > #define INTEL_RANGE_RW (INTEL_RANGE_READ | INTEL_RANGE_WRITE) > #define INTEL_RANGE_END (1<<31) > > -struct intel_register_range { > - uint32_t base; > - uint32_t size; > - uint32_t flags; > -}; > - > -struct intel_register_map { > - struct intel_register_range *map; > - uint32_t top; > - uint32_t alignment_mask; > -}; > struct intel_register_map intel_get_register_map(uint32_t devid); > struct intel_register_range *intel_get_register_range(struct > intel_register_map map, uint32_t offset, uint32_t mode); > #endif /* __GTK_DOC_IGNORE__ */ > diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c > index 3b5a1370..e7a89953 100644 > --- a/lib/intel_iosf.c > +++ b/lib/intel_iosf.c > @@ -19,8 +19,8 @@ > /* Private register write, double-word addressing, non-posted */ > #define SB_CRWRDA_NP 0x07 > > -static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr, > - uint32_t *val) > +static int vlv_sideband_rw(struct mmio_data *mmio_data, uint32_t port, > + uint8_t opcode, uint32_t addr, uint32_t *val) > { > int timeout = 0; > uint32_t cmd, devfn, be, bar; > @@ -34,22 +34,24 @@ static int vlv_sideband_rw(uint32_t port, uint8_t > opcode, uint32_t addr, > (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | > (bar << IOSF_BAR_SHIFT); > > - if (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) { > + if (intel_register_read(mmio_data, VLV_IOSF_DOORBELL_REQ) & > + IOSF_SB_BUSY) { > igt_warn("warning: pcode (%s) mailbox access failed\n", > is_read ? "read" : "write"); > return -EAGAIN; > } > > - intel_register_write(VLV_IOSF_ADDR, addr); > + intel_register_write(mmio_data, VLV_IOSF_ADDR, addr); > if (!is_read) > - intel_register_write(VLV_IOSF_DATA, *val); > + intel_register_write(mmio_data, VLV_IOSF_DATA, *val); > > - intel_register_write(VLV_IOSF_DOORBELL_REQ, cmd); > + intel_register_write(mmio_data, VLV_IOSF_DOORBELL_REQ, cmd); > > do { > usleep(1); > timeout++; > - } while (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY && > - timeout < TIMEOUT_US); > + } while (intel_register_read(mmio_data->igt_mmio, > + VLV_IOSF_DOORBELL_REQ) & > + IOSF_SB_BUSY && timeout < TIMEOUT_US); > > if (timeout >= TIMEOUT_US) { > igt_warn("timeout waiting for pcode %s (%d) to finish\n", > is_read ? "read" : "write", addr); > @@ -57,8 +59,8 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, > uint32_t addr, > } > > if (is_read) > - *val = intel_register_read(VLV_IOSF_DATA); > - intel_register_write(VLV_IOSF_DATA, 0); > + *val = intel_register_read(mmio_data->igt_mmio, > VLV_IOSF_DATA); > + intel_register_write(mmio_data->igt_mmio, VLV_IOSF_DATA, 0); > > return 0; > } > @@ -73,9 +75,10 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, > uint32_t addr, > * Returns: > * 0 when the register access succeeded, negative errno code on failure. > */ > -int intel_punit_read(uint32_t addr, uint32_t *val) > +int intel_punit_read(struct mmio_data *mmio_data, uint32_t addr, uint32_t > *val) > { > - return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr, val); > + return vlv_sideband_rw(mmio_data, IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr, > + val); > } > > /** > @@ -88,9 +91,10 @@ int intel_punit_read(uint32_t addr, uint32_t *val) > * Returns: > * 0 when the register access succeeded, negative errno code on failure. > */ > -int intel_punit_write(uint32_t addr, uint32_t val) > +int intel_punit_write(struct mmio_data *mmio_data, uint32_t addr, uint32_t > val) > { > - return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr, &val); > + return vlv_sideband_rw(mmio_data, IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr, > + &val); > } > > /** > @@ -103,9 +107,10 @@ int intel_punit_write(uint32_t addr, uint32_t val) > * Returns: > * 0 when the register access succeeded, negative errno code on failure. > */ > -int intel_nc_read(uint32_t addr, uint32_t *val) > +int intel_nc_read(struct mmio_data *mmio_data, uint32_t addr, uint32_t > *val) > { > - return vlv_sideband_rw(IOSF_PORT_NC, SB_CRRDDA_NP, addr, val); > + return vlv_sideband_rw(mmio_data, IOSF_PORT_NC, SB_CRRDDA_NP, addr, > + val); > } > > /** > @@ -118,9 +123,10 @@ int intel_nc_read(uint32_t addr, uint32_t *val) > * Returns: > * 0 when the register access succeeded, negative errno code on failure. > */ > -int intel_nc_write(uint32_t addr, uint32_t val) > +int intel_nc_write(struct mmio_data *mmio_data, uint32_t addr, uint32_t > val) > { > - return vlv_sideband_rw(IOSF_PORT_NC, SB_CRWRDA_NP, addr, &val); > + return vlv_sideband_rw(mmio_data, IOSF_PORT_NC, SB_CRWRDA_NP, addr, > + &val); > } > > /** > @@ -133,14 +139,16 @@ int intel_nc_write(uint32_t addr, uint32_t val) > * Returns: > * The value read from the register. > */ > -uint32_t intel_dpio_reg_read(uint32_t reg, int phy) > +uint32_t intel_dpio_reg_read(struct mmio_data *mmio_data, uint32_t reg, int > phy) > { > uint32_t val; > > if (phy == 0) > - vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val); > + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO, SB_MRD_NP, reg, > + &val); > else > - vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MRD_NP, reg, &val); > + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO_2, SB_MRD_NP, reg, > + &val); > return val; > } > > @@ -152,38 +160,40 @@ uint32_t intel_dpio_reg_read(uint32_t reg, int phy) > * > * 32-bit write of the register at @offset through the DPIO sideband port. > */ > -void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy) > +void intel_dpio_reg_write(struct mmio_data *mmio_data, uint32_t reg, > uint32_t val, int phy) > { > if (phy == 0) > - vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val); > + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO, SB_MWR_NP, reg, > &val); > else > - vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MWR_NP, reg, &val); > + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO_2, SB_MWR_NP, reg, > + &val); > } > > -uint32_t intel_flisdsi_reg_read(uint32_t reg) > +uint32_t intel_flisdsi_reg_read(struct mmio_data *mmio_data, uint32_t reg) > { > uint32_t val = 0; > > - vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val); > + vlv_sideband_rw(mmio_data, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, > &val); > > return val; > } > > -void intel_flisdsi_reg_write(uint32_t reg, uint32_t val) > +void intel_flisdsi_reg_write(struct mmio_data *mmio_data, uint32_t reg, > uint32_t val) > { > - vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val); > + vlv_sideband_rw(mmio_data, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, > &val); > } > > -uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg) > +uint32_t intel_iosf_sb_read(struct mmio_data *mmio_data, uint32_t port, > uint32_t reg) > { > uint32_t val; > > - vlv_sideband_rw(port, SB_CRRDDA_NP, reg, &val); > + vlv_sideband_rw(mmio_data, port, SB_CRRDDA_NP, reg, &val); > > return val; > } > > -void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val) > +void intel_iosf_sb_write(struct mmio_data *mmio_data, uint32_t port, > + uint32_t reg, uint32_t val) > { > - vlv_sideband_rw(port, SB_CRWRDA_NP, reg, &val); > + vlv_sideband_rw(mmio_data, port, SB_CRWRDA_NP, reg, &val); > } > diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c > index 01411c37..d77aaba8 100644 > --- a/lib/intel_mmio.c > +++ b/lib/intel_mmio.c > @@ -73,54 +73,53 @@ > */ > void *igt_global_mmio; > > -static struct _mmio_data { > - int inited; > - bool safe; > - uint32_t i915_devid; > - struct intel_register_map map; > - int key; > -} mmio_data; > - > /** > * intel_mmio_use_dump_file: > + * @mmio_data: mmio structure for IO operations > * @file: name of the register dump file to open > * > - * Sets up #igt_global_mmio to point at the data contained in @file. This > allows > - * the same code to get reused for dumping and decoding from running > hardware as > - * from register dumps. > + * Sets also up mmio_data->igt_mmio to point at the data contained > + * in @file. This allows the same code to get reused for dumping and > decoding > + * from running hardware as from register dumps. > */ > void > -intel_mmio_use_dump_file(char *file) > +intel_mmio_use_dump_file(struct mmio_data *mmio_data, char *file) > { > int fd; > struct stat st; > > + memset(mmio_data, 0, sizeof(struct mmio_data)); > fd = open(file, O_RDWR); > igt_fail_on_f(fd == -1, > "Couldn't open %s\n", file); > > fstat(fd, &st); > - igt_global_mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, > MAP_PRIVATE, fd, 0); > - igt_fail_on_f(igt_global_mmio == MAP_FAILED, > + mmio_data->igt_mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, > MAP_PRIVATE, fd, 0); > + igt_fail_on_f(mmio_data->igt_mmio == MAP_FAILED, > "Couldn't mmap %s\n", file); > + > + igt_global_mmio = mmio_data->igt_mmio; > + > close(fd); > } > > /** > * intel_mmio_use_pci_bar: > + * @mmio_data: mmio structure for IO operations > * @pci_dev: intel gracphis pci device > * > - * Sets up #igt_global_mmio to point at the mmio bar. > + * Fill a mmio_data stucture with igt_mmio to point at the mmio bar. > * > * @pci_dev can be obtained from intel_get_pci_device(). > */ > void > -intel_mmio_use_pci_bar(struct pci_device *pci_dev) > +intel_mmio_use_pci_bar(struct mmio_data *mmio_data, struct pci_device > *pci_dev) > { > uint32_t devid, gen; > int mmio_bar, mmio_size; > int error; > > + memset(mmio_data, 0, sizeof(struct mmio_data)); > devid = pci_dev->device_id; > if (IS_GEN2(devid)) > mmio_bar = 1; > @@ -139,7 +138,9 @@ intel_mmio_use_pci_bar(struct pci_device *pci_dev) > pci_dev->regions[mmio_bar].base_addr, > mmio_size, > PCI_DEV_MAP_FLAG_WRITABLE, > - &igt_global_mmio); > + &mmio_data->igt_mmio); > + > + igt_global_mmio = mmio_data->igt_mmio; > > igt_fail_on_f(error != 0, > "Couldn't map MMIO region\n"); > @@ -153,6 +154,7 @@ release_forcewake_lock(int fd) > > /** > * intel_register_access_init: > + * @mmio_data: mmio structure for IO operations > * @pci_dev: intel graphics pci device > * @safe: use safe register access tables > * > @@ -160,76 +162,77 @@ release_forcewake_lock(int fd) > * handling and also allows register access to be checked with an explicit > * whitelist. > * > - * It also initializes #igt_global_mmio like intel_mmio_use_pci_bar(). > + * It also initializes mmio_data->igt_mmio like intel_mmio_use_pci_bar(). > * > * @pci_dev can be obtained from intel_get_pci_device(). > */ > int > -intel_register_access_init(struct pci_device *pci_dev, int safe, int fd) > +intel_register_access_init(struct mmio_data *mmio_data, struct pci_device > *pci_dev, int safe, int fd) > { > int ret; > > - /* after old API is deprecated, remove this */ > - if (igt_global_mmio == NULL) > - intel_mmio_use_pci_bar(pci_dev); > + intel_mmio_use_pci_bar(mmio_data, pci_dev); > > - igt_assert(igt_global_mmio != NULL); > + igt_assert(mmio_data->igt_mmio != NULL); > > - if (mmio_data.inited) > + if (mmio_data->inited) > return -1; > > - mmio_data.safe = (safe != 0 && > + mmio_data->safe = (safe != 0 && > intel_gen(pci_dev->device_id) >= 4) ? true : false; > - mmio_data.i915_devid = pci_dev->device_id; > - if (mmio_data.safe) > - mmio_data.map = intel_get_register_map(mmio_data.i915_devid); > + mmio_data->i915_devid = pci_dev->device_id; > + if (mmio_data->safe) > + mmio_data->map = intel_get_register_map(mmio_data- > >i915_devid); > > /* Find where the forcewake lock is. Forcewake doesn't exist > * gen < 6, but the debugfs should do the right things for us. > */ > ret = igt_open_forcewake_handle(fd); > if (ret == -1) > - mmio_data.key = FAKEKEY; > + mmio_data->key = FAKEKEY; > else > - mmio_data.key = ret; > + mmio_data->key = ret; > > - mmio_data.inited++; > + mmio_data->inited++; > return 0; > } > > static int > -intel_register_access_needs_wake(void) > +intel_register_access_needs_wake(struct mmio_data *mmio_data) > { > - return mmio_data.key != FAKEKEY; > + return mmio_data->key != FAKEKEY; > } > > /** > * intel_register_access_needs_fakewake: > + * @mmio_data: mmio structure for IO operations > * > * Returns: > * Non-zero when forcewake initialization failed. > */ > -int intel_register_access_needs_fakewake(void) > +int intel_register_access_needs_fakewake(struct mmio_data *mmio_data) > { > - return mmio_data.key == FAKEKEY; > + return mmio_data->key == FAKEKEY; > } > > /** > * intel_register_access_fini: > + * @mmio_data: mmio structure for IO operations > * > * Clean up the register access helper initialized with > * intel_register_access_init(). > */ > void > -intel_register_access_fini(void) > +intel_register_access_fini(struct mmio_data *mmio_data) > { > - if (mmio_data.key && intel_register_access_needs_wake()) > - release_forcewake_lock(mmio_data.key); > - mmio_data.inited--; > + if (mmio_data->key && intel_register_access_needs_wake(mmio_data)) > + release_forcewake_lock(mmio_data->key); > + mmio_data->inited--; > } > > /** > * intel_register_read: > + * @mmio_data: mmio structure for IO operations > * @reg: register offset > * > * 32-bit read of the register at @offset. This function only works when > the new > @@ -242,20 +245,20 @@ intel_register_access_fini(void) > * The value read from the register. > */ > uint32_t > -intel_register_read(uint32_t reg) > +intel_register_read(struct mmio_data *mmio_data, uint32_t reg) > { > struct intel_register_range *range; > uint32_t ret; > > - igt_assert(mmio_data.inited); > + igt_assert(mmio_data->inited); > > - if (intel_gen(mmio_data.i915_devid) >= 6) > - igt_assert(mmio_data.key != -1); > + if (intel_gen(mmio_data->i915_devid) >= 6) > + igt_assert(mmio_data->key != -1); > > - if (!mmio_data.safe) > + if (!mmio_data->safe) > goto read_out; > > - range = intel_get_register_range(mmio_data.map, > + range = intel_get_register_range(mmio_data->map, > reg, > INTEL_RANGE_READ); > > @@ -266,13 +269,14 @@ intel_register_read(uint32_t reg) > } > > read_out: > - ret = *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg); > + ret = *(volatile uint32_t *)((volatile char *)mmio_data->igt_mmio + > reg); > out: > return ret; > } > > /** > * intel_register_write: > + * @mmio_data: mmio structure for IO operations > * @reg: register offset > * @val: value to write > * > @@ -283,19 +287,19 @@ out: > * white lists. > */ > void > -intel_register_write(uint32_t reg, uint32_t val) > +intel_register_write(struct mmio_data *mmio_data, uint32_t reg, uint32_t > val) > { > struct intel_register_range *range; > > - igt_assert(mmio_data.inited); > + igt_assert(mmio_data->inited); > > - if (intel_gen(mmio_data.i915_devid) >= 6) > - igt_assert(mmio_data.key != -1); > + if (intel_gen(mmio_data->i915_devid) >= 6) > + igt_assert(mmio_data->key != -1); > > - if (!mmio_data.safe) > + if (!mmio_data->safe) > goto write_out; > > - range = intel_get_register_range(mmio_data.map, > + range = intel_get_register_range(mmio_data->map, > reg, > INTEL_RANGE_WRITE); > > @@ -303,7 +307,7 @@ intel_register_write(uint32_t reg, uint32_t val) > "Register write blocked for safety ""(*0x%08x = > 0x%x)\n", reg, val); > > write_out: > - *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg) = val; > + *(volatile uint32_t *)((volatile char *)mmio_data->igt_mmio + reg) = > val; > } > > > diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c > index e56d6278..b96a8409 100644 > --- a/tests/i915/gem_exec_latency.c > +++ b/tests/i915/gem_exec_latency.c > @@ -61,6 +61,8 @@ > > static unsigned int ring_size; > static double rcs_clock; > +static struct mmio_data mmio_data; > + > > static void > poll_ring(int fd, unsigned ring, const char *name) > @@ -667,7 +669,7 @@ igt_main > if (ring_size > 1024) > ring_size = 1024; > > - intel_register_access_init(intel_get_pci_device(), false, > device); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), > false, device); > rcs_clock = clockrate(device, RCS_TIMESTAMP); > igt_info("RCS timestamp clock: %.0fKHz, %.1fns\n", > rcs_clock / 1e3, 1e9 / rcs_clock); > diff --git a/tests/i915/gem_exec_parse.c b/tests/i915/gem_exec_parse.c > index 62e8d0a5..ef97ff4f 100644 > --- a/tests/i915/gem_exec_parse.c > +++ b/tests/i915/gem_exec_parse.c > @@ -58,6 +58,9 @@ > > static int parser_version; > > +struct mmio_data mmio_data; > + > + > static int command_parser_version(int fd) > { > int version = -1; > @@ -284,9 +287,9 @@ test_lri(int fd, uint32_t handle, struct test_lri *test) > test->name, test->reg, test->test_val, > expected_errno, expect); > > - intel_register_write(test->reg, test->init_val); > + intel_register_write(&mmio_data, test->reg, test->init_val); > > - igt_assert_eq_u32((intel_register_read(test->reg) & > + igt_assert_eq_u32((intel_register_read(&mmio_data, test->reg) & > test->read_mask), > test->init_val); > > @@ -296,7 +299,7 @@ test_lri(int fd, uint32_t handle, struct test_lri *test) > expected_errno); > gem_sync(fd, handle); > > - igt_assert_eq_u32((intel_register_read(test->reg) & > + igt_assert_eq_u32((intel_register_read(&mmio_data, test->reg) & > test->read_mask), > expect); > } > @@ -530,7 +533,7 @@ igt_main > #undef REG > > igt_fixture { > - intel_register_access_init(intel_get_pci_device(), 0, > fd); > + intel_register_access_init(&mmio_data, > intel_get_pci_device(), 0, fd); > } > > for (int i = 0; i < ARRAY_SIZE(lris); i++) { > @@ -543,7 +546,7 @@ igt_main > } > > igt_fixture { > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > } > } > > diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c > index 81c356f0..631fdf8f 100644 > --- a/tests/i915/gem_workarounds.c > +++ b/tests/i915/gem_workarounds.c > @@ -225,6 +225,7 @@ static void check_workarounds(int fd, enum operation op, > unsigned int flags) > > igt_main > { > + struct mmio_data mmio_data; > int device = -1; > const struct { > const char *name; > @@ -256,7 +257,7 @@ igt_main > device = drm_open_driver(DRIVER_INTEL); > igt_require_gem(device); > > - intel_mmio_use_pci_bar(intel_get_pci_device()); > + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device()); > > gen = intel_gen(intel_get_drm_devid(device)); > > diff --git a/tests/i915/i915_pm_lpsp.c b/tests/i915/i915_pm_lpsp.c > index b319dbe9..3b486d30 100644 > --- a/tests/i915/i915_pm_lpsp.c > +++ b/tests/i915/i915_pm_lpsp.c > @@ -187,7 +187,7 @@ int drm_fd; > uint32_t devid; > drmModeResPtr drm_res; > drmModeConnectorPtr drm_connectors[MAX_CONNECTORS]; > - > +struct mmio_data mmio_data; > igt_main > { > igt_fixture { > @@ -210,7 +210,7 @@ igt_main > > igt_require(supports_lpsp(devid)); > > - intel_register_access_init(intel_get_pci_device(), 0, drm_fd); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), > 0, drm_fd); > > kmstest_set_vt_graphics_mode(); > } > @@ -227,7 +227,7 @@ igt_main > igt_fixture { > int i; > > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > for (i = 0; i < drm_res->count_connectors; i++) > drmModeFreeConnector(drm_connectors[i]); > drmModeFreeResources(drm_res); > diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c > index 726bb4b6..25ba918f 100644 > --- a/tools/intel_audio_dump.c > +++ b/tools/intel_audio_dump.c > @@ -42,6 +42,7 @@ static uint32_t devid; > static int aud_reg_base = 0; /* base address of audio registers */ > static int disp_reg_base = 0; /* base address of display registers > */ > > + > #define IS_HASWELL_PLUS(devid) (IS_HASWELL(devid) || IS_BROADWELL(devid)) > > #define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - > 1) > @@ -2464,6 +2465,7 @@ static void dump_braswell(void) > int main(int argc, char **argv) > { > struct pci_device *pci_dev; > + struct mmio_data mmio_data; > > pci_dev = intel_get_pci_device(); > devid = pci_dev->device_id; /* XXX not true when mapping! */ > @@ -2471,9 +2473,9 @@ int main(int argc, char **argv) > do_self_tests(); > > if (argc == 2) > - intel_mmio_use_dump_file(argv[1]); > + intel_mmio_use_dump_file(&mmio_data, argv[1]); > else > - intel_mmio_use_pci_bar(pci_dev); > + intel_mmio_use_pci_bar(&mmio_data, pci_dev); > > printf("%s audio registers:\n\n", intel_get_device_info(devid)- > >codename); > if (IS_VALLEYVIEW(devid)) { > diff --git a/tools/intel_backlight.c b/tools/intel_backlight.c > index 067fd418..2cdb5276 100644 > --- a/tools/intel_backlight.c > +++ b/tools/intel_backlight.c > @@ -38,9 +38,11 @@ > > int main(int argc, char** argv) > { > + struct mmio_data mmio_data; > uint32_t current, max; > > - intel_mmio_use_pci_bar(intel_get_pci_device()); > + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device()); > + igt_global_mmio = mmio_data.igt_mmio; As intel_mmio_use_pci_bar() set igt_global_mmio from default to mmio_data.igt_mmio this assignment is not necessary. > > current = INREG(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; > max = INREG(BLC_PWM_PCH_CTL2) >> 16; > diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c > index 51f5b9a5..4ac97766 100644 > --- a/tools/intel_display_poller.c > +++ b/tools/intel_display_poller.c > @@ -962,6 +962,7 @@ static void __attribute__((noreturn)) usage(const char > *name) > > int main(int argc, char *argv[]) > { > + struct mmio_data mmio_data; > int i; > int pipe = 0, bit = 0, target_scanline = 0, target_fuzz = 1; > bool test_pixelcount = false; > @@ -1187,7 +1188,7 @@ int main(int argc, char *argv[]) > break; > } > > - intel_register_access_init(intel_get_pci_device(), 0, -1); > + intel_register_access_init(&mmio_data ,intel_get_pci_device(), 0, -1); > > printf("%s?\n", test_name(test, pipe, bit, test_pixelcount)); > > @@ -1262,7 +1263,7 @@ int main(int argc, char *argv[]) > assert(0); > } > > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > > if (quit) > return 0; > diff --git a/tools/intel_forcewaked.c b/tools/intel_forcewaked.c > index 02fbf888..f4114612 100644 > --- a/tools/intel_forcewaked.c > +++ b/tools/intel_forcewaked.c > @@ -57,14 +57,15 @@ help(char *prog) { > } > > static int > -is_alive(void) { > +is_alive(struct mmio_data *mmio_data) { > /* Read the timestamp, which should *almost* always be !0 */ > - return (intel_register_read(0x2358) != 0); > + return (intel_register_read(mmio_data, 0x2358) != 0); > } > > int main(int argc, char *argv[]) > { > int ret; > + struct mmio_data mmio_data; > > if (argc > 2 || (argc == 2 && !strncmp(argv[1], "-h", 2))) { > help(argv[1]); > @@ -80,7 +81,7 @@ int main(int argc, char *argv[]) > INFO_PRINT("started daemon"); > } > > - ret = intel_register_access_init(intel_get_pci_device(), 1, -1); > + ret = intel_register_access_init(&mmio_data, intel_get_pci_device(), > 1, -1); > if (ret) { > INFO_PRINT("Couldn't init register access\n"); > exit(1); > @@ -88,16 +89,16 @@ int main(int argc, char *argv[]) > INFO_PRINT("Forcewake locked\n"); > } > while(1) { > - if (!is_alive()) { > + if (!is_alive(&mmio_data)) { > INFO_PRINT("gpu reset? restarting daemon\n"); > - intel_register_access_fini(); > - ret = > intel_register_access_init(intel_get_pci_device(), 1, -1); > + intel_register_access_fini(&mmio_data); > + ret = intel_register_access_init(&mmio_data, > intel_get_pci_device(), 1, -1); > if (ret) > INFO_PRINT("Reg access init fail\n"); > } > sleep(1); > } > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > INFO_PRINT("Forcewake unlock\n"); > > if (daemonized) { > diff --git a/tools/intel_gpu_time.c b/tools/intel_gpu_time.c > index 56d65fe0..15aa0041 100644 > --- a/tools/intel_gpu_time.c > +++ b/tools/intel_gpu_time.c > @@ -65,9 +65,10 @@ int main(int argc, char **argv) > uint64_t ring_idle = 0, ring_time = 0; > struct timeval start, end; > static struct rusage rusage; > + struct mmio_data mmio_data; > int status; > > - intel_mmio_use_pci_bar(intel_get_pci_device()); > + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device()); > > if (argc == 1) { > fprintf(stderr, "usage: %s cmd [args...]\n", argv[0]); > diff --git a/tools/intel_infoframes.c b/tools/intel_infoframes.c > index 2ef5d4fd..fbf53c23 100644 > --- a/tools/intel_infoframes.c > +++ b/tools/intel_infoframes.c > @@ -264,6 +264,7 @@ const char *dip_frequency_names[] = { > > struct pci_device *pci_dev; > int gen = 0; > +struct mmio_data mmio_data; > > static const char *spd_source_to_string(SourceDevice source) > { > @@ -1108,7 +1109,7 @@ int main(int argc, char *argv[]) > " perfectly: the Kernel might undo our changes.\n"); > > pci_dev = intel_get_pci_device(); > - intel_register_access_init(pci_dev, 0, -1); > + intel_register_access_init(&mmio_data, pci_dev, 0, -1); > intel_check_pch(); > > if (IS_GEN4(pci_dev->device_id)) > @@ -1256,6 +1257,6 @@ int main(int argc, char *argv[]) > } > > out: > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > return ret; > } > diff --git a/tools/intel_l3_parity.c b/tools/intel_l3_parity.c > index 4179c5ae..712de230 100644 > --- a/tools/intel_l3_parity.c > +++ b/tools/intel_l3_parity.c > @@ -176,6 +176,7 @@ static void usage(const char *name) > > int main(int argc, char *argv[]) > { > + struct mmio_data mmio_data; > const char *path[REAL_MAX_SLICES] = {"l3_parity", > "l3_parity_slice_1"}; > int row = 0, bank = 0, sbank = 0; > int fd[REAL_MAX_SLICES] = {0}, ret, i; > @@ -189,7 +190,7 @@ int main(int argc, char *argv[]) > if (intel_gen(devid) < 7 || IS_VALLEYVIEW(devid)) > exit(77); > > - assert(intel_register_access_init(intel_get_pci_device(), 0, device) > == 0); > + assert(intel_register_access_init(&mmio_data, intel_get_pci_device(), > 0, device) == 0); > > dir = igt_sysfs_open(device); > > @@ -217,7 +218,7 @@ int main(int argc, char *argv[]) > * now. Just be aware of this if for some reason a hang is reported > * when using this tool. > */ > - dft = intel_register_read(0xb038); > + dft = intel_register_read(&mmio_data, 0xb038); > > while (1) { > int c, option_index = 0; > @@ -366,10 +367,10 @@ int main(int argc, char *argv[]) > assert(i < 2); > dft |= i << 1; /* slice */ > dft |= 1 << 0; /* enable */ > - intel_register_write(0xb038, dft); > + intel_register_write(&mmio_data, 0xb038, dft); > break; > case 'u': > - intel_register_write(0xb038, dft & ~(1<<0)); > + intel_register_write(&mmio_data ,0xb038, dft & > ~(1<<0)); > break; > case 'L': > break; > @@ -378,7 +379,7 @@ int main(int argc, char *argv[]) > } > } > > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > if (action == 'l') > exit(EXIT_SUCCESS); > > diff --git a/tools/intel_lid.c b/tools/intel_lid.c > index 37c6ba5e..52176833 100644 > --- a/tools/intel_lid.c > +++ b/tools/intel_lid.c > @@ -117,9 +117,10 @@ out: > > int main(int argc, char **argv) > { > + struct mmio_data mmio_data; > int swf14, acpi_lid; > > - intel_mmio_use_pci_bar(intel_get_pci_device()); > + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device()); > > while (1) { > swf14 = INREG(SWF14); > diff --git a/tools/intel_panel_fitter.c b/tools/intel_panel_fitter.c > index 137ef61a..03b42596 100644 > --- a/tools/intel_panel_fitter.c > +++ b/tools/intel_panel_fitter.c > @@ -273,6 +273,7 @@ int main (int argc, char *argv[]) > bool do_disable = false, do_dump = false, do_usage = false; > struct pci_device *pci_dev; > uint32_t devid; > + struct mmio_data mmio_data; > > printf("WARNING:\n" > "This tool is a workaround for people that don't have a Kernel > " > @@ -280,7 +281,7 @@ int main (int argc, char *argv[]) > "solution that may or may not work. Use it at your own > risk.\n"); > > pci_dev = intel_get_pci_device(); > - intel_register_access_init(pci_dev, 0, -1); > + intel_register_access_init(&mmio_data, pci_dev, 0, -1); > devid = pci_dev->device_id; > > if (!HAS_PCH_SPLIT(devid)) { > @@ -342,6 +343,6 @@ int main (int argc, char *argv[]) > } > > out: > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > return ret; > } > diff --git a/tools/intel_perf_counters.c b/tools/intel_perf_counters.c > index 50c4bce6..a29ef1b2 100644 > --- a/tools/intel_perf_counters.c > +++ b/tools/intel_perf_counters.c > @@ -441,6 +441,7 @@ gen7_get_counters(void) > int > main(int argc, char **argv) > { > + struct mmio_data mmio_data; > uint32_t devid; > int counter_format; > int counter_count; > @@ -483,10 +484,11 @@ main(int argc, char **argv) > > if (oacontrol) { > /* Forcewake */ > - intel_register_access_init(intel_get_pci_device(), 0, fd); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), > + 0, fd); > > /* Enable performance counters */ > - intel_register_write(OACONTROL, > + intel_register_write(&mmio_data, OACONTROL, > counter_format << OACONTROL_COUNTER_SELECT_SHIFT | > PERFORMANCE_COUNTER_ENABLE); > } > @@ -520,10 +522,10 @@ main(int argc, char **argv) > > if (oacontrol) { > /* Disable performance counters */ > - intel_register_write(OACONTROL, 0); > + intel_register_write(&mmio_data, OACONTROL, 0); > > /* Forcewake */ > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > } > > free(totals); > diff --git a/tools/intel_reg.c b/tools/intel_reg.c > index e517956b..c8cdb377 100644 > --- a/tools/intel_reg.c > +++ b/tools/intel_reg.c > @@ -57,6 +57,7 @@ static inline int _not_supported(void) > > struct config { > struct pci_device *pci_dev; > + struct mmio_data mmio_data; > char *mmiofile; > uint32_t devid; > > @@ -387,7 +388,7 @@ static int read_register(struct config *config, struct > reg *reg, uint32_t *valp) > reg->port_desc.name); > return -1; > } > - val = intel_iosf_sb_read(reg->port_desc.port, reg->addr); > + val = intel_iosf_sb_read(&config->mmio_data, reg- > >port_desc.port, reg->addr); > break; > default: > fprintf(stderr, "port %d not supported\n", reg- > >port_desc.port); > @@ -458,7 +459,7 @@ static int write_register(struct config *config, struct > reg *reg, uint32_t val) > reg->port_desc.name); > return -1; > } > - intel_iosf_sb_write(reg->port_desc.port, reg->addr, val); > + intel_iosf_sb_write(&config->mmio_data, reg->port_desc.port, > reg->addr, val); > break; > default: > fprintf(stderr, "port %d not supported\n", reg- > >port_desc.port); > @@ -552,9 +553,9 @@ static int intel_reg_read(struct config *config, int > argc, char *argv[]) > } > > if (config->mmiofile) > - intel_mmio_use_dump_file(config->mmiofile); > + intel_mmio_use_dump_file(&config->mmio_data, config- > >mmiofile); > else > - intel_register_access_init(config->pci_dev, 0, -1); > + intel_register_access_init(&config->mmio_data, config- > >pci_dev, 0, -1); > > for (i = 1; i < argc; i++) { > struct reg reg; > @@ -570,7 +571,7 @@ static int intel_reg_read(struct config *config, int > argc, char *argv[]) > } > } > > - intel_register_access_fini(); > + intel_register_access_fini(&config->mmio_data); > > return EXIT_SUCCESS; > } > @@ -584,7 +585,7 @@ static int intel_reg_write(struct config *config, int > argc, char *argv[]) > return EXIT_FAILURE; > } > > - intel_register_access_init(config->pci_dev, 0, -1); > + intel_register_access_init(&config->mmio_data, config->pci_dev, 0, > -1); > > for (i = 1; i < argc; i += 2) { > struct reg reg; > @@ -609,7 +610,7 @@ static int intel_reg_write(struct config *config, int > argc, char *argv[]) > write_register(config, ®, val); > } > > - intel_register_access_fini(); > + intel_register_access_fini(&config->mmio_data); > > return EXIT_SUCCESS; > } > @@ -620,9 +621,9 @@ static int intel_reg_dump(struct config *config, int > argc, char *argv[]) > int i; > > if (config->mmiofile) > - intel_mmio_use_dump_file(config->mmiofile); > + intel_mmio_use_dump_file(&config->mmio_data, config- > >mmiofile); > else > - intel_register_access_init(config->pci_dev, 0, -1); > + intel_register_access_init(&config->mmio_data, config- > >pci_dev, 0, -1); > > for (i = 0; i < config->regcount; i++) { > reg = &config->regs[i]; > @@ -634,7 +635,7 @@ static int intel_reg_dump(struct config *config, int > argc, char *argv[]) > dump_register(config, &config->regs[i]); > } > > - intel_register_access_fini(); > + intel_register_access_fini(&config->mmio_data); > > return EXIT_SUCCESS; > } > @@ -648,7 +649,7 @@ static int intel_reg_snapshot(struct config *config, int > argc, char *argv[]) > return EXIT_FAILURE; > } > > - intel_mmio_use_pci_bar(config->pci_dev); > + intel_mmio_use_pci_bar(&config->mmio_data, config->pci_dev); > > /* XXX: error handling */ > if (write(1, igt_global_mmio, config->pci_dev->regions[mmio_bar].size) > == -1) > diff --git a/tools/intel_reg_checker.c b/tools/intel_reg_checker.c > index 6bde63ec..73404d02 100644 > --- a/tools/intel_reg_checker.c > +++ b/tools/intel_reg_checker.c > @@ -342,10 +342,11 @@ check_dpfc_control_sa(void) > int main(int argc, char** argv) > { > struct pci_device *dev; > + struct mmio_data mmio_data; > > dev = intel_get_pci_device(); > devid = dev->device_id; > - intel_mmio_use_pci_bar(dev); > + intel_mmio_use_pci_bar(&mmio_data, dev); > > if (IS_GEN7(devid)) > gen = 7; > diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c > index e71c3d9c..09e9bf36 100644 > --- a/tools/intel_watermark.c > +++ b/tools/intel_watermark.c > @@ -237,6 +237,7 @@ static const char *skl_nv12_buf_cfg_reg_name(int pipe, > int plane) > > static void skl_wm_dump(void) > { > + struct mmio_data mmio_data; > int pipe, plane, level; > int num_pipes = 3; > int max_planes = skl_max_planes(devid); > @@ -249,7 +250,7 @@ static void skl_wm_dump(void) > uint32_t plane_ctl[num_pipes][max_planes]; > uint32_t wm_linetime[num_pipes]; > > - intel_register_access_init(intel_get_pci_device(), 0, -1); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); > > for (pipe = 0; pipe < num_pipes; pipe++) { > int num_planes = skl_num_planes(devid, pipe); > @@ -458,6 +459,7 @@ static void skl_wm_dump(void) > > static void ilk_wm_dump(void) > { > + struct mmio_data mmio_data; > int i; > uint32_t dspcntr[3]; > uint32_t spcntr[3]; > @@ -469,7 +471,7 @@ static void ilk_wm_dump(void) > int num_pipes = intel_gen(devid) >= 7 ? 3 : 2; > struct ilk_wm wm = {}; > > - intel_register_access_init(intel_get_pci_device(), 0, -1); > + intel_register_access_init(&mmio_data,intel_get_pci_device(), 0, -1); Add space after coma to better readibility. > > for (i = 0; i < num_pipes; i++) { > dspcntr[i] = read_reg(0x70180 + i * 0x1000); > @@ -505,7 +507,7 @@ static void ilk_wm_dump(void) > if (IS_BROADWELL(devid) || IS_HASWELL(devid)) > wm_misc = read_reg(0x45260); > > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > > for (i = 0; i < num_pipes; i++) > printf(" WM_PIPE_%c = 0x%08x\n", pipe_name(i), wm_pipe[i]); > @@ -610,6 +612,7 @@ static void ilk_wm_dump(void) > > static void vlv_wm_dump(void) > { > + struct mmio_data mmio_data; > int i; > unsigned int num_pipes = IS_CHERRYVIEW(devid) ? 3 : 2; > uint32_t dsparb, dsparb2, dsparb3; > @@ -619,7 +622,7 @@ static void vlv_wm_dump(void) > uint32_t dsp_ss_pm, ddr_setup2; > struct gmch_wm wms[MAX_PLANE] = {}; > > - intel_register_access_init(intel_get_pci_device(), 0, -1); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); > > dsparb = read_reg(0x70030); > dsparb2 = read_reg(0x70060); > @@ -650,13 +653,13 @@ static void vlv_wm_dump(void) > > ddl3 = read_reg(0x70058); > > - intel_punit_read(0x36, &dsp_ss_pm); > - intel_punit_read(0x139, &ddr_setup2); > + intel_punit_read(&mmio_data, 0x36, &dsp_ss_pm); > + intel_punit_read(&mmio_data, 0x139, &ddr_setup2); > } else { > fw7 = read_reg(0x7007c); > } > > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > > printf(" FW1 = 0x%08x\n", fw1); > printf(" FW2 = 0x%08x\n", fw2); > @@ -827,6 +830,7 @@ static void vlv_wm_dump(void) > > static void g4x_wm_dump(void) > { > + struct mmio_data mmio_data; > int i; > uint32_t dspacntr, dspbcntr; > uint32_t dsparb; > @@ -835,7 +839,7 @@ static void g4x_wm_dump(void) > uint32_t mi_arb_state; > struct gmch_wm wms[MAX_PLANE] = {}; > > - intel_register_access_init(intel_get_pci_device(), 0, -1); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); > > dspacntr = read_reg(0x70180); > dspbcntr = read_reg(0x71180); > @@ -846,7 +850,7 @@ static void g4x_wm_dump(void) > mi_display_power_down = read_reg(0x20e0); > mi_arb_state = read_reg(0x20e4); > > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > > printf(" DSPACNTR = 0x%08x\n", dspacntr); > printf(" DSPBCNTR = 0x%08x\n", dspbcntr); > @@ -913,6 +917,7 @@ static void g4x_wm_dump(void) > > static void gen4_wm_dump(void) > { > + struct mmio_data mmio_data; > int i; > int totalsize = IS_CRESTLINE(devid) ? 128 : 96; > uint32_t dsparb; > @@ -921,7 +926,7 @@ static void gen4_wm_dump(void) > uint32_t mi_arb_state; > struct gmch_wm wms[MAX_PLANE] = {}; > > - intel_register_access_init(intel_get_pci_device(), 0, -1); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); > > dsparb = read_reg(0x70030); > fw1 = read_reg(0x70034); > @@ -930,7 +935,7 @@ static void gen4_wm_dump(void) > mi_display_power_down = read_reg(0x20e0); > mi_arb_state = read_reg(0x20e4); > > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > > printf(" FW1 = 0x%08x\n", fw1); > printf(" FW2 = 0x%08x\n", fw2); > @@ -983,6 +988,7 @@ static void gen4_wm_dump(void) > > static void pnv_wm_dump(void) > { > + struct mmio_data mmio_data; > int i; > int totalsize = 96; /* FIXME? */ > uint32_t dsparb; > @@ -992,7 +998,7 @@ static void pnv_wm_dump(void) > uint32_t cbr; > struct gmch_wm wms[MAX_PLANE] = {}; > > - intel_register_access_init(intel_get_pci_device(), 0, -1); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); > > dsparb = read_reg(0x70030); > fw1 = read_reg(0x70034); > @@ -1002,7 +1008,7 @@ static void pnv_wm_dump(void) > mi_display_power_down = read_reg(0x20e0); > mi_arb_state = read_reg(0x20e4); > > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > > printf(" DSPARB = 0x%08x\n", dsparb); > printf(" FW1 = 0x%08x\n", fw1); > @@ -1073,6 +1079,7 @@ static void pnv_wm_dump(void) > > static void gen3_wm_dump(void) > { > + struct mmio_data mmio_data; > int i; > int totalsize = IS_945GM(devid) ? 128 : 96; /* FIXME? */ > uint32_t dsparb; > @@ -1082,7 +1089,7 @@ static void gen3_wm_dump(void) > uint32_t mi_arb_state; > struct gmch_wm wms[MAX_PLANE] = {}; > > - intel_register_access_init(intel_get_pci_device(), 0, -1); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); > > dsparb = read_reg(0x70030); > instpm = read_reg(0x20c0); > @@ -1090,7 +1097,7 @@ static void gen3_wm_dump(void) > fw_blc_self = read_reg(0x20e0); > mi_arb_state = read_reg(0x20e4); > > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > > printf(" DSPARB = 0x%08x\n", dsparb); > printf(" FW_BLC = 0x%016" PRIx64 "\n", fw_blc); > @@ -1142,6 +1149,7 @@ static void gen3_wm_dump(void) > > static void gen2_wm_dump(void) > { > + struct mmio_data mmio_data; > int i; > int totalsize; > uint32_t dsparb; > @@ -1151,7 +1159,7 @@ static void gen2_wm_dump(void) > uint32_t mi_state; > struct gmch_wm wms[MAX_PLANE] = {}; > > - intel_register_access_init(intel_get_pci_device(), 0, -1); > + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1); > > dsparb = read_reg(0x70030); > mem_mode = read_reg(0x20cc); > @@ -1159,7 +1167,7 @@ static void gen2_wm_dump(void) > fw_blc_self = read_reg(0x20e0); > mi_state = read_reg(0x20e4); > > - intel_register_access_fini(); > + intel_register_access_fini(&mmio_data); > > printf(" DSPARB = 0x%08x\n", dsparb); > printf(" MEM_MODE = 0x%08x\n", mem_mode); LGTM, fix two issues pointed above. Then RB. Zbigniew _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 10+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: warning for Remove global igt_global_mmio (rev6) 2019-07-24 12:32 [igt-dev] [PATCH i-g-t v6 0/3] Remove global igt_global_mmio Daniel Mrzyglod ` (2 preceding siblings ...) 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 3/3] lib/intel_mmio: add additional api for multiple devices Daniel Mrzyglod @ 2019-07-24 12:48 ` Patchwork 2019-07-24 14:21 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork 2019-07-24 16:54 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 5 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-07-24 12:48 UTC (permalink / raw) To: Daniel Mrzyglod; +Cc: igt-dev == Series Details == Series: Remove global igt_global_mmio (rev6) URL : https://patchwork.freedesktop.org/series/59008/ State : warning == Summary == Pipeline status: FAILED. See https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/50917 for more details. == Logs == For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/50917 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 10+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Remove global igt_global_mmio (rev6) 2019-07-24 12:32 [igt-dev] [PATCH i-g-t v6 0/3] Remove global igt_global_mmio Daniel Mrzyglod ` (3 preceding siblings ...) 2019-07-24 12:48 ` [igt-dev] ✗ GitLab.Pipeline: warning for Remove global igt_global_mmio (rev6) Patchwork @ 2019-07-24 14:21 ` Patchwork 2019-07-24 16:54 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 5 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-07-24 14:21 UTC (permalink / raw) To: Daniel Mrzyglod; +Cc: igt-dev == Series Details == Series: Remove global igt_global_mmio (rev6) URL : https://patchwork.freedesktop.org/series/59008/ State : success == Summary == CI Bug Log - changes from CI_DRM_6545 -> IGTPW_3291 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59008/revisions/6/mbox/ Known issues ------------ Here are the changes found in IGTPW_3291 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_fence@basic-wait-default: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@gem_exec_fence@basic-wait-default.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/fi-icl-u3/igt@gem_exec_fence@basic-wait-default.html * igt@kms_flip@basic-flip-vs-wf_vblank: - fi-bsw-kefka: [PASS][3] -> [FAIL][4] ([fdo#100368]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-bsw-kefka/igt@kms_flip@basic-flip-vs-wf_vblank.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/fi-bsw-kefka/igt@kms_flip@basic-flip-vs-wf_vblank.html #### Possible fixes #### * igt@gem_ctx_create@basic-files: - fi-icl-u2: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u2/igt@gem_ctx_create@basic-files.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/fi-icl-u2/igt@gem_ctx_create@basic-files.html * igt@i915_selftest@live_hangcheck: - fi-kbl-guc: [INCOMPLETE][7] ([fdo#108744]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [WARN][9] ([fdo#109380]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: [FAIL][11] ([fdo#103167]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [SKIP][13] ([fdo#109271]) -> [PASS][14] +23 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368 [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049 Participating hosts (52 -> 44) ------------------------------ Additional (1): fi-skl-gvtdvm Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5109 -> IGTPW_3291 CI-20190529: 20190529 CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3291: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/ IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/ _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 10+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Remove global igt_global_mmio (rev6) 2019-07-24 12:32 [igt-dev] [PATCH i-g-t v6 0/3] Remove global igt_global_mmio Daniel Mrzyglod ` (4 preceding siblings ...) 2019-07-24 14:21 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork @ 2019-07-24 16:54 ` Patchwork 5 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-07-24 16:54 UTC (permalink / raw) To: Daniel Mrzyglod; +Cc: igt-dev == Series Details == Series: Remove global igt_global_mmio (rev6) URL : https://patchwork.freedesktop.org/series/59008/ State : success == Summary == CI Bug Log - changes from CI_DRM_6545_full -> IGTPW_3291_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59008/revisions/6/mbox/ Known issues ------------ Here are the changes found in IGTPW_3291_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_tiled_swapping@non-threaded: - shard-kbl: [PASS][1] -> [FAIL][2] ([fdo#108686]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@gem_tiled_swapping@non-threaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-kbl3/igt@gem_tiled_swapping@non-threaded.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-snb: [PASS][3] -> [SKIP][4] ([fdo#109271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-snb6/igt@i915_pm_rc6_residency@rc6-accuracy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-snb2/igt@i915_pm_rc6_residency@rc6-accuracy.html * igt@i915_selftest@mock_fence: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@i915_selftest@mock_fence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-iclb7/igt@i915_selftest@mock_fence.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl3/igt@i915_suspend@fence-restore-untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-apl7/igt@i915_suspend@fence-restore-untiled.html * igt@i915_suspend@forcewake: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl4/igt@i915_suspend@forcewake.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-kbl4/igt@i915_suspend@forcewake.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-kbl: [PASS][11] -> [FAIL][12] ([fdo#103232]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-kbl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html - shard-apl: [PASS][13] -> [FAIL][14] ([fdo#103232]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109642] / [fdo#111068]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr2_su@page_flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-iclb8/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html #### Possible fixes #### * igt@kms_color@pipe-c-ctm-blue-to-red: - shard-kbl: [FAIL][21] ([fdo#107201]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl6/igt@kms_color@pipe-c-ctm-blue-to-red.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-kbl2/igt@kms_color@pipe-c-ctm-blue-to-red.html - shard-apl: [FAIL][23] ([fdo#107201]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl1/igt@kms_color@pipe-c-ctm-blue-to-red.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-apl5/igt@kms_color@pipe-c-ctm-blue-to-red.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding: - shard-apl: [FAIL][25] ([fdo#103232]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html - shard-kbl: [FAIL][27] ([fdo#103232]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [FAIL][29] ([fdo#103167]) -> [PASS][30] +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_psr@cursor_plane_onoff: - shard-iclb: [INCOMPLETE][31] ([fdo#107713]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb1/igt@kms_psr@cursor_plane_onoff.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-iclb6/igt@kms_psr@cursor_plane_onoff.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][33] ([fdo#109441]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-apl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +6 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-apl8/igt@kms_vblank@pipe-c-ts-continuation-suspend.html #### Warnings #### * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][37] ([fdo#109349]) -> [DMESG-WARN][38] ([fdo#107724]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_dp_dsc@basic-dsc-enable-edp.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 Participating hosts (9 -> 6) ------------------------------ Missing (3): pig-skl-6260u shard-skl pig-glk-j5005 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5109 -> IGTPW_3291 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3291: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/ IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3291/ _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-08-13 11:22 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-07-24 12:32 [igt-dev] [PATCH i-g-t v6 0/3] Remove global igt_global_mmio Daniel Mrzyglod 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 1/3] lib/igt_device: add igt_device_get_pci_addr by fd Daniel Mrzyglod 2019-07-24 15:11 ` Zbigniew Kempczyński 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 2/3] lib/intel_mmio: add funtions for read/write register funtions Daniel Mrzyglod 2019-08-13 11:11 ` Kempczynski, Zbigniew 2019-07-24 12:32 ` [igt-dev] [PATCH i-g-t v6 3/3] lib/intel_mmio: add additional api for multiple devices Daniel Mrzyglod 2019-08-13 11:21 ` Kempczynski, Zbigniew 2019-07-24 12:48 ` [igt-dev] ✗ GitLab.Pipeline: warning for Remove global igt_global_mmio (rev6) Patchwork 2019-07-24 14:21 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork 2019-07-24 16:54 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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