From: Imre Deak <imre.deak@intel.com>
To: igt-dev@lists.freedesktop.org
Subject: [igt-dev] [PATCH i-g-t] tests/i915_pm_dc: Increase timeout and poll interval
Date: Wed, 23 Oct 2019 22:10:02 +0300 [thread overview]
Message-ID: <20191023191002.8220-1-imre.deak@intel.com> (raw)
The eDP panel power cycle delay prevents DC entry after a full modeset,
which makes the test fail on some panels. Let's increase the timeout to
take into account that delay (atm in the worst case the power cycle
delay is 3 seconds) and also increase the polling interval to give more
time for the device to enter a low power state.
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
tests/i915/i915_pm_dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index ce3319b7..ef96a86e 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -153,7 +153,7 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
{
return igt_wait(read_dc_counter(drm_fd, dc_flag) >
- prev_dc_count, 3000, 100);
+ prev_dc_count, 6000, 1000);
}
static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
--
2.17.1
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next reply other threads:[~2019-10-23 19:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-23 19:10 Imre Deak [this message]
2019-10-23 20:45 ` [igt-dev] ✓ Fi.CI.BAT: success for tests/i915_pm_dc: Increase timeout and poll interval Patchwork
2019-10-24 15:27 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2019-11-13 10:35 ` [igt-dev] [PATCH i-g-t] " Anshuamn Gupta
2019-11-13 12:33 ` Imre Deak
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