[igt-dev] [PATCH i-g-t 1/2] lib/i915/gem_mman: Add functions to get mmap and gtt versions

[igt-dev] [PATCH i-g-t 1/2] lib/i915/gem_mman: Add functions to get mmap and gtt versions

[Stuart Summers]

Move these checks out to separate functions to make the code
more readable and reuseable.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 lib/i915/gem_mman.c | 42 +++++++++++++++++++++++++++---------------
 1 file changed, 27 insertions(+), 15 deletions(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 6256627b..a0e34aef 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -101,29 +101,41 @@ int gem_munmap(void *ptr, uint64_t size)
 	return ret;
 }
 
+static int get_gtt_version(int fd)
+{
+	struct drm_i915_getparam gp;
+	int gtt_version = -1;
+
+	memset(&gp, 0, sizeof(gp));
+	gp.param = I915_PARAM_MMAP_GTT_VERSION;
+	gp.value = &gtt_version;
+	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+	return gtt_version;
+}
+
+static int get_mmap_version(int fd)
+{
+	struct drm_i915_getparam gp;
+	int mmap_version = -1;
+
+	memset(&gp, 0, sizeof(gp));
+	gp.param = I915_PARAM_MMAP_VERSION;
+	gp.value = &mmap_version;
+	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+	return mmap_version;
+}
+
 bool gem_mmap__has_wc(int fd)
 {
 	static int has_wc = -1;
 
 	if (has_wc == -1) {
-		struct drm_i915_getparam gp;
-		int mmap_version = -1;
-		int gtt_version = -1;
-
 		has_wc = 0;
 
-		memset(&gp, 0, sizeof(gp));
-		gp.param = I915_PARAM_MMAP_GTT_VERSION;
-		gp.value = &gtt_version;
-		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
-		memset(&gp, 0, sizeof(gp));
-		gp.param = I915_PARAM_MMAP_VERSION;
-		gp.value = &mmap_version;
-		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
 		/* Do we have the new mmap_ioctl with DOMAIN_WC? */
-		if (mmap_version >= 1 && gtt_version >= 2) {
+		if (get_mmap_version(fd) >= 1 && get_gtt_version(fd) >= 2) {
 			struct drm_i915_gem_mmap arg;
 
 			/* Does this device support wc-mmaps ? */
-- 
2.21.0.5.gaeb582a983

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[igt-dev] [PATCH i-g-t 2/2] lib/i915/gem_mman: mmap to the CPU instead of the GTT in some tests

[Stuart Summers]

Do not limit to the GTT for tests which are not specifically testing
capability in the GTT.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 lib/i915/gem_mman.c            | 19 +++++++++++++++++++
 lib/i915/gem_mman.h            |  1 +
 tests/i915/gem_ctx_shared.c    | 20 +++++---------------
 tests/i915/gem_exec_schedule.c |  3 +--
 4 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index a0e34aef..d37840f7 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -40,6 +40,25 @@
 #define VG(x) do {} while (0)
 #endif
 
+void *gem_mmap_host(int fd, uint32_t handle, uint64_t size, unsigned prot)
+{
+	void *ptr;
+	uint32_t domain;
+
+	if (gem_has_mappable_ggtt(fd)) {
+		ptr = gem_mmap__gtt(fd, handle, size, prot);
+		domain = I915_GEM_DOMAIN_GTT;
+	} else {
+		ptr = gem_mmap__cpu(fd, handle, 0, size, prot);
+		domain = I915_GEM_DOMAIN_CPU;
+	}
+
+	gem_set_domain(fd, handle, /* no write hazard lies! */
+		       domain, domain);
+
+	return ptr;
+}
+
 /**
  * __gem_mmap__gtt:
  * @fd: open i915 drm file descriptor
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index 096ff592..e1714360 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -25,6 +25,7 @@
 #ifndef GEM_MMAN_H
 #define GEM_MMAN_H
 
+void *gem_mmap_host(int fd, uint32_t handle, uint64_t size, unsigned prot);
 void *gem_mmap__gtt(int fd, uint32_t handle, uint64_t size, unsigned prot);
 void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 
diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
index a6eee16d..74fccd95 100644
--- a/tests/i915/gem_ctx_shared.c
+++ b/tests/i915/gem_ctx_shared.c
@@ -613,9 +613,7 @@ static void independent(int i915, unsigned ring, unsigned flags)
 	for (int i = 0; i < ARRAY_SIZE(priorities); i++) {
 		uint32_t *ptr;
 
-		ptr = gem_mmap__gtt(i915, handle[i], 4096, PROT_READ);
-		gem_set_domain(i915, handle[i], /* no write hazard lies! */
-			       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+		ptr = gem_mmap_host(i915, handle[i], 4096, PROT_READ);
 		gem_close(i915, handle[i]);
 
 		handle[i] = ptr[TIMESTAMP];
@@ -658,9 +656,7 @@ static void reorder(int i915, unsigned ring, unsigned flags)
 	gem_context_destroy(i915, ctx[LO]);
 	gem_context_destroy(i915, ctx[HI]);
 
-	ptr = gem_mmap__gtt(i915, scratch, 4096, PROT_READ);
-	gem_set_domain(i915, scratch, /* no write hazard lies! */
-		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+	ptr = gem_mmap_host(i915, scratch, 4096, PROT_READ);
 	gem_close(i915, scratch);
 
 	if (flags & EQUAL) /* equal priority, result will be fifo */
@@ -713,17 +709,13 @@ static void promotion(int i915, unsigned ring)
 	gem_context_destroy(i915, ctx[LO]);
 	gem_context_destroy(i915, ctx[HI]);
 
-	ptr = gem_mmap__gtt(i915, dep, 4096, PROT_READ);
-	gem_set_domain(i915, dep, /* no write hazard lies! */
-			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+	ptr = gem_mmap_host(i915, dep, 4096, PROT_READ);
 	gem_close(i915, dep);
 
 	igt_assert_eq_u32(ptr[0], ctx[HI]);
 	munmap(ptr, 4096);
 
-	ptr = gem_mmap__gtt(i915, result, 4096, PROT_READ);
-	gem_set_domain(i915, result, /* no write hazard lies! */
-			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+	ptr = gem_mmap_host(i915, result, 4096, PROT_READ);
 	gem_close(i915, result);
 
 	igt_assert_eq_u32(ptr[0], ctx[NOISE]);
@@ -776,9 +768,7 @@ static void smoketest(int i915, unsigned ring, unsigned timeout)
 	}
 	igt_waitchildren();
 
-	ptr = gem_mmap__gtt(i915, scratch, 4096, PROT_READ);
-	gem_set_domain(i915, scratch, /* no write hazard lies! */
-			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+	ptr = gem_mmap_host(i915, scratch, 4096, PROT_READ);
 	gem_close(i915, scratch);
 
 	for (unsigned n = 0; n < ncpus; n++) {
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index dc1c3a92..7f55a0a8 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -1404,8 +1404,7 @@ static void reorder_wide(int fd, unsigned ring)
 		gem_context_set_priority(fd, execbuf.rsvd1, n);
 
 		obj[1].handle = gem_create(fd, sz);
-		batch = gem_mmap__gtt(fd, obj[1].handle, sz, PROT_WRITE);
-		gem_set_domain(fd, obj[1].handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+		gem_mmap_host(fd, obj[1].handle, sz, PROT_WRITE);
 
 		for (int m = 0; m < ring_size; m++) {
 			uint64_t addr;
-- 
2.21.0.5.gaeb582a983

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Re: [igt-dev] [PATCH i-g-t 2/2] lib/i915/gem_mman: mmap to the CPU instead of the GTT in some tests

[Chris Wilson]

Quoting Stuart Summers (2019-11-19 18:16:19)
> Do not limit to the GTT for tests which are not specifically testing
> capability in the GTT.
> 
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
>  lib/i915/gem_mman.c            | 19 +++++++++++++++++++
>  lib/i915/gem_mman.h            |  1 +
>  tests/i915/gem_ctx_shared.c    | 20 +++++---------------
>  tests/i915/gem_exec_schedule.c |  3 +--
>  4 files changed, 26 insertions(+), 17 deletions(-)
> 
> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> index a0e34aef..d37840f7 100644
> --- a/lib/i915/gem_mman.c
> +++ b/lib/i915/gem_mman.c
> @@ -40,6 +40,25 @@
>  #define VG(x) do {} while (0)
>  #endif
>  
> +void *gem_mmap_host(int fd, uint32_t handle, uint64_t size, unsigned prot)
> +{
> +       void *ptr;
> +       uint32_t domain;
> +
> +       if (gem_has_mappable_ggtt(fd)) {
> +               ptr = gem_mmap__gtt(fd, handle, size, prot);
> +               domain = I915_GEM_DOMAIN_GTT;
> +       } else {
> +               ptr = gem_mmap__cpu(fd, handle, 0, size, prot);
> +               domain = I915_GEM_DOMAIN_CPU;
> +       }
> +
> +       gem_set_domain(fd, handle, /* no write hazard lies! */
> +                      domain, domain);

Ah, no. There's a huge difference in coherency between these 2 modes.
The test has to be prepared for handle to be snoopable.

> +       return ptr;
> +}
> +
>  /**
>   * __gem_mmap__gtt:
>   * @fd: open i915 drm file descriptor
> diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
> index 096ff592..e1714360 100644
> --- a/lib/i915/gem_mman.h
> +++ b/lib/i915/gem_mman.h
> @@ -25,6 +25,7 @@
>  #ifndef GEM_MMAN_H
>  #define GEM_MMAN_H
>  
> +void *gem_mmap_host(int fd, uint32_t handle, uint64_t size, unsigned prot);
>  void *gem_mmap__gtt(int fd, uint32_t handle, uint64_t size, unsigned prot);
>  void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
>  
> diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
> index a6eee16d..74fccd95 100644
> --- a/tests/i915/gem_ctx_shared.c
> +++ b/tests/i915/gem_ctx_shared.c
> @@ -613,9 +613,7 @@ static void independent(int i915, unsigned ring, unsigned flags)
>         for (int i = 0; i < ARRAY_SIZE(priorities); i++) {
>                 uint32_t *ptr;
>  
> -               ptr = gem_mmap__gtt(i915, handle[i], 4096, PROT_READ);
> -               gem_set_domain(i915, handle[i], /* no write hazard lies! */
> -                              I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> +               ptr = gem_mmap_host(i915, handle[i], 4096, PROT_READ);
>                 gem_close(i915, handle[i]);

There's also fun side-effects for test like these where mixing GTT vma
with ppGTT may be interesting.

>                 handle[i] = ptr[TIMESTAMP];
> @@ -658,9 +656,7 @@ static void reorder(int i915, unsigned ring, unsigned flags)
>         gem_context_destroy(i915, ctx[LO]);
>         gem_context_destroy(i915, ctx[HI]);
>  
> -       ptr = gem_mmap__gtt(i915, scratch, 4096, PROT_READ);
> -       gem_set_domain(i915, scratch, /* no write hazard lies! */
> -                      I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> +       ptr = gem_mmap_host(i915, scratch, 4096, PROT_READ);
>         gem_close(i915, scratch);
>  
>         if (flags & EQUAL) /* equal priority, result will be fifo */
> @@ -713,17 +709,13 @@ static void promotion(int i915, unsigned ring)
>         gem_context_destroy(i915, ctx[LO]);
>         gem_context_destroy(i915, ctx[HI]);
>  
> -       ptr = gem_mmap__gtt(i915, dep, 4096, PROT_READ);
> -       gem_set_domain(i915, dep, /* no write hazard lies! */
> -                       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> +       ptr = gem_mmap_host(i915, dep, 4096, PROT_READ);
>         gem_close(i915, dep);
>  
>         igt_assert_eq_u32(ptr[0], ctx[HI]);
>         munmap(ptr, 4096);
>  
> -       ptr = gem_mmap__gtt(i915, result, 4096, PROT_READ);
> -       gem_set_domain(i915, result, /* no write hazard lies! */
> -                       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> +       ptr = gem_mmap_host(i915, result, 4096, PROT_READ);
>         gem_close(i915, result);
>  
>         igt_assert_eq_u32(ptr[0], ctx[NOISE]);
> @@ -776,9 +768,7 @@ static void smoketest(int i915, unsigned ring, unsigned timeout)
>         }
>         igt_waitchildren();
>  
> -       ptr = gem_mmap__gtt(i915, scratch, 4096, PROT_READ);
> -       gem_set_domain(i915, scratch, /* no write hazard lies! */
> -                       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> +       ptr = gem_mmap_host(i915, scratch, 4096, PROT_READ);
>         gem_close(i915, scratch);

I can't think of any immediate reason why this couldn't be gem_mmap__wc.

> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> index dc1c3a92..7f55a0a8 100644
> --- a/tests/i915/gem_exec_schedule.c
> +++ b/tests/i915/gem_exec_schedule.c
> @@ -1404,8 +1404,7 @@ static void reorder_wide(int fd, unsigned ring)
>                 gem_context_set_priority(fd, execbuf.rsvd1, n);
>  
>                 obj[1].handle = gem_create(fd, sz);
> -               batch = gem_mmap__gtt(fd, obj[1].handle, sz, PROT_WRITE);
> -               gem_set_domain(fd, obj[1].handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> +               gem_mmap_host(fd, obj[1].handle, sz, PROT_WRITE);

But this one rings alarms bells that we tried and failed to make it WC,
but I can't remember what went wrong.

However, WB is definitely wrong for these tests across all current
platforms.
-Chris
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Re: [igt-dev] [PATCH i-g-t 2/2] lib/i915/gem_mman: mmap to the CPU instead of the GTT in some tests

[Vanshidhar Konda]

On Tue, Nov 19, 2019 at 10:16:19AM -0800, Stuart Summers wrote:
>Do not limit to the GTT for tests which are not specifically testing
>capability in the GTT.
>
>Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>---
> lib/i915/gem_mman.c            | 19 +++++++++++++++++++
> lib/i915/gem_mman.h            |  1 +
> tests/i915/gem_ctx_shared.c    | 20 +++++---------------
> tests/i915/gem_exec_schedule.c |  3 +--
> 4 files changed, 26 insertions(+), 17 deletions(-)
>
>diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
>index a0e34aef..d37840f7 100644
>--- a/lib/i915/gem_mman.c
>+++ b/lib/i915/gem_mman.c
>@@ -40,6 +40,25 @@
> #define VG(x) do {} while (0)
> #endif
>
>+void *gem_mmap_host(int fd, uint32_t handle, uint64_t size, unsigned prot)

Seems like gem_mmap methods are named gem_mmap__wc/cpu/gtt. So may be
keep that consistent. Other than that LGTM.

Acked-by: Vanshidhar Konda <vanshidhar.r.konda@intel.com>

>+{
>+	void *ptr;
>+	uint32_t domain;
>+
>+	if (gem_has_mappable_ggtt(fd)) {
>+		ptr = gem_mmap__gtt(fd, handle, size, prot);
>+		domain = I915_GEM_DOMAIN_GTT;
>+	} else {
>+		ptr = gem_mmap__cpu(fd, handle, 0, size, prot);
>+		domain = I915_GEM_DOMAIN_CPU;
>+	}
>+
>+	gem_set_domain(fd, handle, /* no write hazard lies! */
>+		       domain, domain);
>+
>+	return ptr;
>+}
>+
> /**
>  * __gem_mmap__gtt:
>  * @fd: open i915 drm file descriptor
>diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
>index 096ff592..e1714360 100644
>--- a/lib/i915/gem_mman.h
>+++ b/lib/i915/gem_mman.h
>@@ -25,6 +25,7 @@
> #ifndef GEM_MMAN_H
> #define GEM_MMAN_H
>
>+void *gem_mmap_host(int fd, uint32_t handle, uint64_t size, unsigned prot);
> void *gem_mmap__gtt(int fd, uint32_t handle, uint64_t size, unsigned prot);
> void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
>
>diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
>index a6eee16d..74fccd95 100644
>--- a/tests/i915/gem_ctx_shared.c
>+++ b/tests/i915/gem_ctx_shared.c
>@@ -613,9 +613,7 @@ static void independent(int i915, unsigned ring, unsigned flags)
> 	for (int i = 0; i < ARRAY_SIZE(priorities); i++) {
> 		uint32_t *ptr;
>
>-		ptr = gem_mmap__gtt(i915, handle[i], 4096, PROT_READ);
>-		gem_set_domain(i915, handle[i], /* no write hazard lies! */
>-			       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>+		ptr = gem_mmap_host(i915, handle[i], 4096, PROT_READ);
> 		gem_close(i915, handle[i]);
>
> 		handle[i] = ptr[TIMESTAMP];
>@@ -658,9 +656,7 @@ static void reorder(int i915, unsigned ring, unsigned flags)
> 	gem_context_destroy(i915, ctx[LO]);
> 	gem_context_destroy(i915, ctx[HI]);
>
>-	ptr = gem_mmap__gtt(i915, scratch, 4096, PROT_READ);
>-	gem_set_domain(i915, scratch, /* no write hazard lies! */
>-		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>+	ptr = gem_mmap_host(i915, scratch, 4096, PROT_READ);
> 	gem_close(i915, scratch);
>
> 	if (flags & EQUAL) /* equal priority, result will be fifo */
>@@ -713,17 +709,13 @@ static void promotion(int i915, unsigned ring)
> 	gem_context_destroy(i915, ctx[LO]);
> 	gem_context_destroy(i915, ctx[HI]);
>
>-	ptr = gem_mmap__gtt(i915, dep, 4096, PROT_READ);
>-	gem_set_domain(i915, dep, /* no write hazard lies! */
>-			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>+	ptr = gem_mmap_host(i915, dep, 4096, PROT_READ);
> 	gem_close(i915, dep);
>
> 	igt_assert_eq_u32(ptr[0], ctx[HI]);
> 	munmap(ptr, 4096);
>
>-	ptr = gem_mmap__gtt(i915, result, 4096, PROT_READ);
>-	gem_set_domain(i915, result, /* no write hazard lies! */
>-			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>+	ptr = gem_mmap_host(i915, result, 4096, PROT_READ);
> 	gem_close(i915, result);
>
> 	igt_assert_eq_u32(ptr[0], ctx[NOISE]);
>@@ -776,9 +768,7 @@ static void smoketest(int i915, unsigned ring, unsigned timeout)
> 	}
> 	igt_waitchildren();
>
>-	ptr = gem_mmap__gtt(i915, scratch, 4096, PROT_READ);
>-	gem_set_domain(i915, scratch, /* no write hazard lies! */
>-			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>+	ptr = gem_mmap_host(i915, scratch, 4096, PROT_READ);
> 	gem_close(i915, scratch);
>
> 	for (unsigned n = 0; n < ncpus; n++) {
>diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
>index dc1c3a92..7f55a0a8 100644
>--- a/tests/i915/gem_exec_schedule.c
>+++ b/tests/i915/gem_exec_schedule.c
>@@ -1404,8 +1404,7 @@ static void reorder_wide(int fd, unsigned ring)
> 		gem_context_set_priority(fd, execbuf.rsvd1, n);
>
> 		obj[1].handle = gem_create(fd, sz);
>-		batch = gem_mmap__gtt(fd, obj[1].handle, sz, PROT_WRITE);
>-		gem_set_domain(fd, obj[1].handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>+		gem_mmap_host(fd, obj[1].handle, sz, PROT_WRITE);
>
> 		for (int m = 0; m < ring_size; m++) {
> 			uint64_t addr;
>-- 
>2.21.0.5.gaeb582a983
>
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Re: [igt-dev] [PATCH i-g-t 2/2] lib/i915/gem_mman: mmap to the CPU instead of the GTT in some tests

[Chris Wilson]

Quoting Stuart Summers (2019-11-19 18:16:19)
> Do not limit to the GTT for tests which are not specifically testing
> capability in the GTT.
> 
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
>  lib/i915/gem_mman.c            | 19 +++++++++++++++++++
>  lib/i915/gem_mman.h            |  1 +
>  tests/i915/gem_ctx_shared.c    | 20 +++++---------------
>  tests/i915/gem_exec_schedule.c |  3 +--
>  4 files changed, 26 insertions(+), 17 deletions(-)
> 
> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> index a0e34aef..d37840f7 100644
> --- a/lib/i915/gem_mman.c
> +++ b/lib/i915/gem_mman.c
> @@ -40,6 +40,25 @@
>  #define VG(x) do {} while (0)
>  #endif
>  
> +void *gem_mmap_host(int fd, uint32_t handle, uint64_t size, unsigned prot)
> +{
> +       void *ptr;
> +       uint32_t domain;
> +
> +       if (gem_has_mappable_ggtt(fd)) {
> +               ptr = gem_mmap__gtt(fd, handle, size, prot);
> +               domain = I915_GEM_DOMAIN_GTT;
> +       } else {
> +               ptr = gem_mmap__cpu(fd, handle, 0, size, prot);
> +               domain = I915_GEM_DOMAIN_CPU;
> +       }
> +
> +       gem_set_domain(fd, handle, /* no write hazard lies! */
> +                      domain, domain);

And be very careful putting the set-domain in here; as the lies are
integral to the test and not suitable for libraries. Domain handling is
sadly of paramount importance for most tests.
-Chris
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Re: [igt-dev] [PATCH i-g-t 2/2] lib/i915/gem_mman: mmap to the CPU instead of the GTT in some tests

[Summers, Stuart]

[-- Attachment #1.1: Type: text/plain, Size: 1935 bytes --]

On Tue, 2019-11-19 at 18:25 +0000, Chris Wilson wrote:
> Quoting Stuart Summers (2019-11-19 18:16:19)
> > Do not limit to the GTT for tests which are not specifically
> > testing
> > capability in the GTT.
> > 
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> >  lib/i915/gem_mman.c            | 19 +++++++++++++++++++
> >  lib/i915/gem_mman.h            |  1 +
> >  tests/i915/gem_ctx_shared.c    | 20 +++++---------------
> >  tests/i915/gem_exec_schedule.c |  3 +--
> >  4 files changed, 26 insertions(+), 17 deletions(-)
> > 
> > diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> > index a0e34aef..d37840f7 100644
> > --- a/lib/i915/gem_mman.c
> > +++ b/lib/i915/gem_mman.c
> > @@ -40,6 +40,25 @@
> >  #define VG(x) do {} while (0)
> >  #endif
> >  
> > +void *gem_mmap_host(int fd, uint32_t handle, uint64_t size,
> > unsigned prot)
> > +{
> > +       void *ptr;
> > +       uint32_t domain;
> > +
> > +       if (gem_has_mappable_ggtt(fd)) {
> > +               ptr = gem_mmap__gtt(fd, handle, size, prot);
> > +               domain = I915_GEM_DOMAIN_GTT;
> > +       } else {
> > +               ptr = gem_mmap__cpu(fd, handle, 0, size, prot);
> > +               domain = I915_GEM_DOMAIN_CPU;
> > +       }
> > +
> > +       gem_set_domain(fd, handle, /* no write hazard lies! */
> > +                      domain, domain);
> 
> And be very careful putting the set-domain in here; as the lies are
> integral to the test and not suitable for libraries. Domain handling
> is
> sadly of paramount importance for most tests.

Hm.. so maybe a little more in the kernel to safeguard here. I was
thinking of doing that anyway. Then we can adopt the tests as needed.

And for these, maybe the right way to go is to use the new mmap_offset
Zbigniew is implementing. The IOCTL posted by Abdiel already has a WC
case for that.

Thanks,
Stuart

> -Chris

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[igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] lib/i915/gem_mman: Add functions to get mmap and gtt versions

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/2] lib/i915/gem_mman: Add functions to get mmap and gtt versions
URL   : https://patchwork.freedesktop.org/series/69692/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7377 -> IGTPW_3729
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/index.html

Known issues
------------

  Here are the changes found in IGTPW_3729 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-nick:        [PASS][1] -> [INCOMPLETE][2] ([fdo# 111542])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-u2:          [PASS][3] -> [FAIL][4] ([fdo#109635 ] / [fdo#110387])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-guc:         [INCOMPLETE][5] ([fdo#106070] / [fdo#111700]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#111407]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111700]: https://bugs.freedesktop.org/show_bug.cgi?id=111700


Participating hosts (49 -> 44)
------------------------------

  Additional (1): fi-skl-6600u 
  Missing    (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5295 -> IGTPW_3729

  CI-20190529: 20190529
  CI_DRM_7377: d96d9a85806e971f5b294e9e3894d847e46a7b5e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3729: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/index.html
  IGT_5295: 9211e4794e40135d797e6d056d6d8d40076acb92 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/index.html
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Re: [igt-dev] [PATCH i-g-t 2/2] lib/i915/gem_mman: mmap to the CPU instead of the GTT in some tests

[Chris Wilson]

Quoting Summers, Stuart (2019-11-19 18:58:31)
> On Tue, 2019-11-19 at 18:25 +0000, Chris Wilson wrote:
> > Quoting Stuart Summers (2019-11-19 18:16:19)
> > > Do not limit to the GTT for tests which are not specifically
> > > testing
> > > capability in the GTT.
> > > 
> > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > ---
> > >  lib/i915/gem_mman.c            | 19 +++++++++++++++++++
> > >  lib/i915/gem_mman.h            |  1 +
> > >  tests/i915/gem_ctx_shared.c    | 20 +++++---------------
> > >  tests/i915/gem_exec_schedule.c |  3 +--
> > >  4 files changed, 26 insertions(+), 17 deletions(-)
> > > 
> > > diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> > > index a0e34aef..d37840f7 100644
> > > --- a/lib/i915/gem_mman.c
> > > +++ b/lib/i915/gem_mman.c
> > > @@ -40,6 +40,25 @@
> > >  #define VG(x) do {} while (0)
> > >  #endif
> > >  
> > > +void *gem_mmap_host(int fd, uint32_t handle, uint64_t size,
> > > unsigned prot)
> > > +{
> > > +       void *ptr;
> > > +       uint32_t domain;
> > > +
> > > +       if (gem_has_mappable_ggtt(fd)) {
> > > +               ptr = gem_mmap__gtt(fd, handle, size, prot);
> > > +               domain = I915_GEM_DOMAIN_GTT;
> > > +       } else {
> > > +               ptr = gem_mmap__cpu(fd, handle, 0, size, prot);
> > > +               domain = I915_GEM_DOMAIN_CPU;
> > > +       }
> > > +
> > > +       gem_set_domain(fd, handle, /* no write hazard lies! */
> > > +                      domain, domain);
> > 
> > And be very careful putting the set-domain in here; as the lies are
> > integral to the test and not suitable for libraries. Domain handling
> > is
> > sadly of paramount importance for most tests.
> 
> Hm.. so maybe a little more in the kernel to safeguard here. I was
> thinking of doing that anyway. Then we can adopt the tests as needed.

/* no write hazard lies! */

is all about how we are circumventing the kernel's opinion on correct
behaviour to get at the behaviour we require ;)

> And for these, maybe the right way to go is to use the new mmap_offset
> Zbigniew is implementing. The IOCTL posted by Abdiel already has a WC
> case for that.

Yes. Pretty much all of these should be using gem_mmap__wc(), and
whether that is implemented using mmap_offset_ioctl or mmap_ioctl is
immaterial. The CPUs / platforms that cannot use WC are immaterial to
most of these tests (these test in particular are only applicable to
recent gen), but for a select few tests we will need to make sure that
they are still usable with gem_mmap__gtt.

So a possible gem_mmap__device_coherent() {
	ptr = gem_mmap__offset(.type = WC);
	if (ptr)
		return ptr;

	ptr = gem_mmap__wc();
	if (ptr)
		return ptr;

	return gem_mmap__gt();
}
Names and details left to the reader. We did decide that library
functions like gem_mmap__wc() could use either mmap_offset_ioctl or
mmap_ioctl as they saw fit; and tests that required exact ioctls would
call those ioctls explicitly.
-Chris
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Re: [igt-dev] [PATCH i-g-t 2/2] lib/i915/gem_mman: mmap to the CPU instead of the GTT in some tests

[Summers, Stuart]

[-- Attachment #1.1: Type: text/plain, Size: 3729 bytes --]

On Tue, 2019-11-19 at 19:20 +0000, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-11-19 18:58:31)
> > On Tue, 2019-11-19 at 18:25 +0000, Chris Wilson wrote:
> > > Quoting Stuart Summers (2019-11-19 18:16:19)
> > > > Do not limit to the GTT for tests which are not specifically
> > > > testing
> > > > capability in the GTT.
> > > > 
> > > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > > ---
> > > >  lib/i915/gem_mman.c            | 19 +++++++++++++++++++
> > > >  lib/i915/gem_mman.h            |  1 +
> > > >  tests/i915/gem_ctx_shared.c    | 20 +++++---------------
> > > >  tests/i915/gem_exec_schedule.c |  3 +--
> > > >  4 files changed, 26 insertions(+), 17 deletions(-)
> > > > 
> > > > diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> > > > index a0e34aef..d37840f7 100644
> > > > --- a/lib/i915/gem_mman.c
> > > > +++ b/lib/i915/gem_mman.c
> > > > @@ -40,6 +40,25 @@
> > > >  #define VG(x) do {} while (0)
> > > >  #endif
> > > >  
> > > > +void *gem_mmap_host(int fd, uint32_t handle, uint64_t size,
> > > > unsigned prot)
> > > > +{
> > > > +       void *ptr;
> > > > +       uint32_t domain;
> > > > +
> > > > +       if (gem_has_mappable_ggtt(fd)) {
> > > > +               ptr = gem_mmap__gtt(fd, handle, size, prot);
> > > > +               domain = I915_GEM_DOMAIN_GTT;
> > > > +       } else {
> > > > +               ptr = gem_mmap__cpu(fd, handle, 0, size, prot);
> > > > +               domain = I915_GEM_DOMAIN_CPU;
> > > > +       }
> > > > +
> > > > +       gem_set_domain(fd, handle, /* no write hazard lies! */
> > > > +                      domain, domain);
> > > 
> > > And be very careful putting the set-domain in here; as the lies
> > > are
> > > integral to the test and not suitable for libraries. Domain
> > > handling
> > > is
> > > sadly of paramount importance for most tests.
> > 
> > Hm.. so maybe a little more in the kernel to safeguard here. I was
> > thinking of doing that anyway. Then we can adopt the tests as
> > needed.
> 
> /* no write hazard lies! */
> 
> is all about how we are circumventing the kernel's opinion on correct
> behaviour to get at the behaviour we require ;)
> 
> > And for these, maybe the right way to go is to use the new
> > mmap_offset
> > Zbigniew is implementing. The IOCTL posted by Abdiel already has a
> > WC
> > case for that.
> 
> Yes. Pretty much all of these should be using gem_mmap__wc(), and
> whether that is implemented using mmap_offset_ioctl or mmap_ioctl is
> immaterial. The CPUs / platforms that cannot use WC are immaterial to
> most of these tests (these test in particular are only applicable to
> recent gen), but for a select few tests we will need to make sure
> that
> they are still usable with gem_mmap__gtt.
> 
> So a possible gem_mmap__device_coherent() {
> 	ptr = gem_mmap__offset(.type = WC);
> 	if (ptr)
> 		return ptr;
> 
> 	ptr = gem_mmap__wc();
> 	if (ptr)
> 		return ptr;
> 
> 	return gem_mmap__gt();
> }

Yeah I've been playing around locally with something like this (or at
least with the mmap_offset/mmap_gtt, your suggestion is cleaner). The
problem is in application. Do we apply this to all tests which aren't
expliclity doing GGTT testing? Or do we start with something like the
gem_ctx_shared and expand over time? I don't have all of the history
across the tests, so really appreciate the feedback here Chris.

Thanks,
Stuart

> Names and details left to the reader. We did decide that library
> functions like gem_mmap__wc() could use either mmap_offset_ioctl or
> mmap_ioctl as they saw fit; and tests that required exact ioctls
> would
> call those ioctls explicitly.
> -Chris

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Re: [igt-dev] [PATCH i-g-t 2/2] lib/i915/gem_mman: mmap to the CPU instead of the GTT in some tests

[Chris Wilson]

Quoting Summers, Stuart (2019-11-19 22:00:17)
> On Tue, 2019-11-19 at 19:20 +0000, Chris Wilson wrote:
> > So a possible gem_mmap__device_coherent() {
> >       ptr = gem_mmap__offset(.type = WC);
> >       if (ptr)
> >               return ptr;
> > 
> >       ptr = gem_mmap__wc();
> >       if (ptr)
> >               return ptr;
> > 
> >       return gem_mmap__gt();
> > }
> 
> Yeah I've been playing around locally with something like this (or at
> least with the mmap_offset/mmap_gtt, your suggestion is cleaner). The
> problem is in application. Do we apply this to all tests which aren't
> expliclity doing GGTT testing? Or do we start with something like the
> gem_ctx_shared and expand over time? I don't have all of the history
> across the tests, so really appreciate the feedback here Chris.

In almost all cases, gtt was being used only because it provided
coherent [uncached] access. There are a few tests that are explicitly
testing GTT features (and they are easy to spot). The other day I think
I counted around 100 test.c using gem_mmap__gtt of which a quick
inspection said only 10% of those were looking at GTT features.

The biggest challenge is choosing the name and semantics of the
replacement: device/pci_coherent or something like that. And then define
whether or not we use gem_sync() + manual clflush for nonspecific
testing, or stick with gem_set_domain(GTT) as the lowest common
denominator. There's pros/cons for either choice (and there will always
be corner cases that explicitly need one or the other) , just patches
need to be written.
-Chris
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Re: [igt-dev] [PATCH i-g-t 2/2] lib/i915/gem_mman: mmap to the CPU instead of the GTT in some tests

[Summers, Stuart]

[-- Attachment #1.1: Type: text/plain, Size: 2253 bytes --]

On Tue, 2019-11-19 at 22:28 +0000, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-11-19 22:00:17)
> > On Tue, 2019-11-19 at 19:20 +0000, Chris Wilson wrote:
> > > So a possible gem_mmap__device_coherent() {
> > >       ptr = gem_mmap__offset(.type = WC);
> > >       if (ptr)
> > >               return ptr;
> > > 
> > >       ptr = gem_mmap__wc();
> > >       if (ptr)
> > >               return ptr;
> > > 
> > >       return gem_mmap__gt();
> > > }
> > 
> > Yeah I've been playing around locally with something like this (or
> > at
> > least with the mmap_offset/mmap_gtt, your suggestion is cleaner).
> > The
> > problem is in application. Do we apply this to all tests which
> > aren't
> > expliclity doing GGTT testing? Or do we start with something like
> > the
> > gem_ctx_shared and expand over time? I don't have all of the
> > history
> > across the tests, so really appreciate the feedback here Chris.
> 
> In almost all cases, gtt was being used only because it provided
> coherent [uncached] access. There are a few tests that are explicitly
> testing GTT features (and they are easy to spot). The other day I
> think
> I counted around 100 test.c using gem_mmap__gtt of which a quick
> inspection said only 10% of those were looking at GTT features.
> 
> The biggest challenge is choosing the name and semantics of the
> replacement: device/pci_coherent or something like that. And then
> define
> whether or not we use gem_sync() + manual clflush for nonspecific
> testing, or stick with gem_set_domain(GTT) as the lowest common
> denominator. There's pros/cons for either choice (and there will
> always
> be corner cases that explicitly need one or the other) , just patches
> need to be written.

Adding Zbigniew here too for visibility in case I don't get to this.

But corner cases should be covered by specific test cases I'd think.
And if we're trying to push userspace away from gem_set_domain
generally, it seems like the better approach is to model what we want
for the UMDs to use, of course keeping specific cases for backwards
compatibility testing.

Anyway, I'll give another shot similar to what you have above when I
get a chance.

Thanks,
Stuart

> -Chris

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[igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/2] lib/i915/gem_mman: Add functions to get mmap and gtt versions

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/2] lib/i915/gem_mman: Add functions to get mmap and gtt versions
URL   : https://patchwork.freedesktop.org/series/69692/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7377_full -> IGTPW_3729_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3729_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3729_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3729_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_schedule@reorder-wide-blt:
    - shard-glk:          [PASS][1] -> [CRASH][2] +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-glk5/igt@gem_exec_schedule@reorder-wide-blt.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-glk5/igt@gem_exec_schedule@reorder-wide-blt.html
    - shard-apl:          [PASS][3] -> [CRASH][4] +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-apl3/igt@gem_exec_schedule@reorder-wide-blt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-apl3/igt@gem_exec_schedule@reorder-wide-blt.html
    - shard-tglb:         [PASS][5] -> [CRASH][6] +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb3/igt@gem_exec_schedule@reorder-wide-blt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb3/igt@gem_exec_schedule@reorder-wide-blt.html

  * igt@gem_exec_schedule@reorder-wide-render:
    - shard-iclb:         NOTRUN -> [CRASH][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb8/igt@gem_exec_schedule@reorder-wide-render.html

  * igt@gem_exec_schedule@reorder-wide-vebox:
    - shard-kbl:          [PASS][8] -> [CRASH][9] +4 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-kbl2/igt@gem_exec_schedule@reorder-wide-vebox.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-kbl4/igt@gem_exec_schedule@reorder-wide-vebox.html
    - shard-tglb:         NOTRUN -> [CRASH][10]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb4/igt@gem_exec_schedule@reorder-wide-vebox.html
    - shard-iclb:         [PASS][11] -> [CRASH][12] +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb3/igt@gem_exec_schedule@reorder-wide-vebox.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb7/igt@gem_exec_schedule@reorder-wide-vebox.html

  
#### Warnings ####

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [SKIP][13] ([fdo#112146]) -> [CRASH][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html

  
Known issues
------------

  Here are the changes found in IGTPW_3729_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@vcs1-cleanup:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#109276] / [fdo#112080])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb1/igt@gem_ctx_persistence@vcs1-cleanup.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb7/igt@gem_ctx_persistence@vcs1-cleanup.html

  * igt@gem_eio@suspend:
    - shard-tglb:         [PASS][17] -> [INCOMPLETE][18] ([fdo#111850]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb2/igt@gem_eio@suspend.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb8/igt@gem_eio@suspend.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#110854])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb4/igt@gem_exec_balancer@smoke.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb6/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_parallel@vcs1-fds:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#112080]) +11 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb6/igt@gem_exec_parallel@vcs1-fds.html

  * igt@gem_exec_schedule@preempt-queue-bsd:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#112146]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd.html

  * igt@gem_exec_schedule@preempt-queue-contexts-render:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([fdo#111606] / [fdo#111677])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb3/igt@gem_exec_schedule@preempt-queue-contexts-render.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-render.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [PASS][27] -> [INCOMPLETE][28] ([fdo#111832])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb1/igt@gem_exec_suspend@basic-s0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb4/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [PASS][29] -> [DMESG-WARN][30] ([fdo#111870]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-snb7/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-glk:          [PASS][31] -> [FAIL][32] ([fdo#100368])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
    - shard-iclb:         [PASS][33] -> [FAIL][34] ([fdo#103167]) +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
    - shard-tglb:         [PASS][35] -> [FAIL][36] ([fdo#103167]) +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][37] -> [DMESG-WARN][38] ([fdo#108566]) +4 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109441])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb3/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_setmode@basic:
    - shard-glk:          [PASS][41] -> [FAIL][42] ([fdo#99912])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-glk4/igt@kms_setmode@basic.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-glk7/igt@kms_setmode@basic.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][43] -> [SKIP][44] ([fdo#109276]) +15 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [DMESG-WARN][45] ([fdo#108566]) -> [PASS][46] +5 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-kbl6/igt@gem_ctx_isolation@rcs0-s3.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-clean:
    - shard-iclb:         [SKIP][47] ([fdo#109276] / [fdo#112080]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb7/igt@gem_ctx_isolation@vcs1-clean.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb2/igt@gem_ctx_isolation@vcs1-clean.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][49] ([fdo#110841]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_basic@basic-vcs1:
    - shard-iclb:         [SKIP][51] ([fdo#112080]) -> [PASS][52] +5 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb5/igt@gem_exec_basic@basic-vcs1.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb2/igt@gem_exec_basic@basic-vcs1.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][53] ([fdo#112146]) -> [PASS][54] +6 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_pipe_control_store_loop@reused-buffer:
    - shard-tglb:         [INCOMPLETE][55] ([fdo#111998]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb6/igt@gem_pipe_control_store_loop@reused-buffer.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb5/igt@gem_pipe_control_store_loop@reused-buffer.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-snb:          [DMESG-WARN][57] ([fdo#111870]) -> [PASS][58] +3 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [DMESG-WARN][59] ([fdo#111870]) -> [PASS][60] +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-tglb:         [INCOMPLETE][61] ([fdo#111832] / [fdo#111850]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb2/igt@gem_workarounds@suspend-resume-context.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb3/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [INCOMPLETE][63] ([fdo#107713]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb1/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
    - shard-apl:          [FAIL][65] ([fdo#103232]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
    - shard-kbl:          [FAIL][67] ([fdo#103232]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-tglb:         [FAIL][69] ([fdo#103167]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
    - shard-iclb:         [FAIL][71] ([fdo#103167]) -> [PASS][72] +2 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-tglb:         [FAIL][73] ([fdo#112275]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb4/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb2/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
    - shard-iclb:         [FAIL][75] ([fdo#112213]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb8/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb3/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-apl:          [DMESG-WARN][77] ([fdo#108566]) -> [PASS][78] +2 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [SKIP][79] ([fdo#109441]) -> [PASS][80] +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb3/igt@kms_psr@psr2_primary_page_flip.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][81] ([fdo#109276]) -> [PASS][82] +6 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb5/igt@prime_busy@hang-bsd2.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb4/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv-switch:
    - shard-iclb:         [FAIL][83] ([fdo#111329]) -> [SKIP][84] ([fdo#109276] / [fdo#112080])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html

  * igt@gem_eio@kms:
    - shard-snb:          [DMESG-WARN][85] ([fdo#111781]) -> [INCOMPLETE][86] ([fdo#105411])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-snb1/igt@gem_eio@kms.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-snb6/igt@gem_eio@kms.html

  * igt@gem_exec_schedule@deep-bsd2:
    - shard-tglb:         [FAIL][87] ([fdo#111646]) -> [INCOMPLETE][88] ([fdo#111671])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb3/igt@gem_exec_schedule@deep-bsd2.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb7/igt@gem_exec_schedule@deep-bsd2.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglb:         [SKIP][89] ([fdo#111865]) -> [FAIL][90] ([fdo#111830 ])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7377/shard-tglb6/igt@i915_pm_dc@dc6-dpms.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/shard-tglb1/igt@i915_pm_dc@dc6-dpms.html

  
  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
  [fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
  [fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
  [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111865]: https://bugs.freedesktop.org/show_bug.cgi?id=111865
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111998]: https://bugs.freedesktop.org/show_bug.cgi?id=111998
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112213]: https://bugs.freedesktop.org/show_bug.cgi?id=112213
  [fdo#112275]: https://bugs.freedesktop.org/show_bug.cgi?id=112275
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (11 -> 8)
------------------------------

  Missing    (3): pig-skl-6260u pig-glk-j5005 pig-hsw-4770r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5295 -> IGTPW_3729
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_7377: d96d9a85806e971f5b294e9e3894d847e46a7b5e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3729: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/index.html
  IGT_5295: 9211e4794e40135d797e6d056d6d8d40076acb92 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3729/index.html
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