* [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats
@ 2019-12-30 3:40 Imre Deak
2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 01/10] lib/igt_buf: Use compression type consistently Imre Deak
` (15 more replies)
0 siblings, 16 replies; 33+ messages in thread
From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw)
To: igt-dev
For a reasonable test coverage of the display's media decompression
functionality this patchset adds support and subtests for media
compressed YUV formats (using the Vebox engine).
Cc: Mika Kahola <mika.kahola@intel.com>
Imre Deak (9):
lib/igt_buf: Use compression type consistently
lib/igt_buf: Extend igt_buf to include two CCS surfaces
lib/igt_buf: Extend igt_buf to include two color surfaces
lib: Add engine copy support for YUV formats
Revert "tests/kms_plane: Disable GEN12 media compression YUV tests"
tests/kms_ccs: Add support for testing multiple formats
tests/kms_ccs: Work around CRC mismatch when mixing SDR/HDR planes
tests/kms_ccs: Test YUV formats too
tests/kms_ccs: Add option to check the CCS planes
Mika Kahola (1):
tests/kms_ccs: Add GEN12 CCS media compression format modifier
lib/gpu_cmds.c | 4 +-
lib/igt_draw.c | 8 +-
lib/igt_fb.c | 99 ++++++++++++++++++--
lib/igt_fb.h | 4 +
lib/intel_aux_pgtable.c | 130 +++++++++++++++++++++++----
lib/intel_batchbuffer.c | 8 +-
lib/intel_batchbuffer.h | 17 +++-
lib/rendercopy_gen4.c | 4 +-
lib/rendercopy_gen6.c | 4 +-
lib/rendercopy_gen7.c | 4 +-
lib/rendercopy_gen8.c | 4 +-
lib/rendercopy_gen9.c | 18 ++--
lib/rendercopy_i830.c | 8 +-
lib/rendercopy_i915.c | 8 +-
lib/veboxcopy_gen12.c | 64 +++++++++++--
tests/i915/gem_concurrent_all.c | 10 ++-
tests/i915/gem_gpgpu_fill.c | 4 +-
tests/i915/gem_media_fill.c | 4 +-
tests/i915/gem_media_vme.c | 6 +-
tests/i915/gem_ppgtt.c | 8 +-
tests/i915/gem_read_read_speed.c | 10 ++-
tests/i915/gem_render_copy.c | 43 ++++-----
tests/i915/gem_render_copy_redux.c | 4 +-
tests/i915/gem_render_linear_blits.c | 24 ++---
tests/i915/gem_render_tiled_blits.c | 8 +-
tests/i915/gem_ring_sync_copy.c | 4 +-
tests/i915/gem_stress.c | 59 ++++++------
tests/i915/i915_pm_sseu.c | 7 +-
tests/kms_big_fb.c | 10 ++-
tests/kms_ccs.c | 120 ++++++++++++++++++++++---
tests/kms_plane.c | 7 --
tests/kms_psr.c | 4 +-
tests/perf.c | 4 +-
33 files changed, 540 insertions(+), 180 deletions(-)
--
2.23.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 33+ messages in thread* [igt-dev] [PATCH i-g-t 01/10] lib/igt_buf: Use compression type consistently 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak @ 2019-12-30 3:40 ` Imre Deak 2019-12-30 12:00 ` Kahola, Mika 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 02/10] lib/igt_buf: Extend igt_buf to include two CCS surfaces Imre Deak ` (14 subsequent siblings) 15 siblings, 1 reply; 33+ messages in thread From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw) To: igt-dev Use the igt_buf compression field to determine the compression type for a buffer, instead of the fact that AUX stride is set. We need to look at the former one anyway to distinguish between compression types. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- lib/igt_fb.c | 5 +++++ lib/intel_aux_pgtable.c | 8 ++++---- lib/intel_batchbuffer.h | 5 +++++ lib/rendercopy_gen9.c | 6 +++++- 4 files changed, 19 insertions(+), 5 deletions(-) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index e6eb39ac..7e99abb3 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -1989,6 +1989,11 @@ static void init_buf(struct fb_blit_upload *blit, else igt_assert_eq(fb->strides[1] & 127, 0); + if (is_gen12_mc_ccs_modifier(fb->modifier)) + buf->compression = I915_COMPRESSION_MEDIA; + else + buf->compression = I915_COMPRESSION_RENDER; + buf->aux.offset = fb->offsets[1]; buf->aux.stride = fb->strides[1]; } diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index cbb3c320..f8ce6754 100644 --- a/lib/intel_aux_pgtable.c +++ b/lib/intel_aux_pgtable.c @@ -434,7 +434,7 @@ aux_pgtable_reserve_range(const struct igt_buf **bufs, int buf_count, { int i; - if (new_buf->aux.stride) { + if (igt_buf_compressed(new_buf)) { uint64_t pin_offset = new_buf->bo->offset64; if (!pin_offset) @@ -465,7 +465,7 @@ gen12_aux_pgtable_init(struct aux_pgtable_info *info, int reserved_buf_count; int i; - if (!src_buf->aux.stride && !dst_buf->aux.stride) + if (!igt_buf_compressed(src_buf) && !igt_buf_compressed(dst_buf)) return; bufs[0] = src_buf; @@ -492,7 +492,7 @@ gen12_aux_pgtable_init(struct aux_pgtable_info *info, /* Next, reserve space for unbound bufs with an AUX surface. */ for (i = 0; i < ARRAY_SIZE(bufs); i++) - if (!bufs[i]->bo->offset64 && bufs[i]->aux.stride) + if (!bufs[i]->bo->offset64 && igt_buf_compressed(bufs[i])) aux_pgtable_reserve_range(reserved_bufs, reserved_buf_count++, bufs[i]); @@ -500,7 +500,7 @@ gen12_aux_pgtable_init(struct aux_pgtable_info *info, /* Create AUX pgtable entries only for bufs with an AUX surface */ info->buf_count = 0; for (i = 0; i < reserved_buf_count; i++) { - if (!reserved_bufs[i]->aux.stride) + if (!igt_buf_compressed(reserved_bufs[i])) continue; info->bufs[info->buf_count] = reserved_bufs[i]; diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index 37e3affe..c3028343 100644 --- a/lib/intel_batchbuffer.h +++ b/lib/intel_batchbuffer.h @@ -249,6 +249,11 @@ struct igt_buf { unsigned num_tiles; }; +static inline bool igt_buf_compressed(const struct igt_buf *buf) +{ + return buf->compression != I915_COMPRESSION_NONE; +} + unsigned igt_buf_width(const struct igt_buf *buf); unsigned igt_buf_height(const struct igt_buf *buf); diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index 63b1023d..88a94cbe 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -259,7 +259,9 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, if (buf->compression == I915_COMPRESSION_MEDIA) ss->ss7.tgl.media_compression = 1; - else if (buf->aux.stride) { + else if (buf->compression == I915_COMPRESSION_RENDER) { + igt_assert(buf->aux.stride); + ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */ ss->ss6.aux_pitch = (buf->aux.stride / 128) - 1; @@ -274,6 +276,8 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, } if (buf->cc.offset) { + igt_assert(buf->compression == I915_COMPRESSION_RENDER); + ss->ss12.clear_address = buf->bo->offset64 + buf->cc.offset; ss->ss13.clear_address_hi = (buf->bo->offset64 + buf->cc.offset) >> 32; -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 01/10] lib/igt_buf: Use compression type consistently 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 01/10] lib/igt_buf: Use compression type consistently Imre Deak @ 2019-12-30 12:00 ` Kahola, Mika 0 siblings, 0 replies; 33+ messages in thread From: Kahola, Mika @ 2019-12-30 12:00 UTC (permalink / raw) To: igt-dev@lists.freedesktop.org, Deak, Imre On Mon, 2019-12-30 at 05:40 +0200, Imre Deak wrote: > Use the igt_buf compression field to determine the compression type > for > a buffer, instead of the fact that AUX stride is set. We need to look > at > the former one anyway to distinguish between compression types. > > Cc: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> > --- > lib/igt_fb.c | 5 +++++ > lib/intel_aux_pgtable.c | 8 ++++---- > lib/intel_batchbuffer.h | 5 +++++ > lib/rendercopy_gen9.c | 6 +++++- > 4 files changed, 19 insertions(+), 5 deletions(-) > > diff --git a/lib/igt_fb.c b/lib/igt_fb.c > index e6eb39ac..7e99abb3 100644 > --- a/lib/igt_fb.c > +++ b/lib/igt_fb.c > @@ -1989,6 +1989,11 @@ static void init_buf(struct fb_blit_upload > *blit, > else > igt_assert_eq(fb->strides[1] & 127, 0); > > + if (is_gen12_mc_ccs_modifier(fb->modifier)) > + buf->compression = I915_COMPRESSION_MEDIA; > + else > + buf->compression = I915_COMPRESSION_RENDER; > + > buf->aux.offset = fb->offsets[1]; > buf->aux.stride = fb->strides[1]; > } > diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c > index cbb3c320..f8ce6754 100644 > --- a/lib/intel_aux_pgtable.c > +++ b/lib/intel_aux_pgtable.c > @@ -434,7 +434,7 @@ aux_pgtable_reserve_range(const struct igt_buf > **bufs, int buf_count, > { > int i; > > - if (new_buf->aux.stride) { > + if (igt_buf_compressed(new_buf)) { > uint64_t pin_offset = new_buf->bo->offset64; > > if (!pin_offset) > @@ -465,7 +465,7 @@ gen12_aux_pgtable_init(struct aux_pgtable_info > *info, > int reserved_buf_count; > int i; > > - if (!src_buf->aux.stride && !dst_buf->aux.stride) > + if (!igt_buf_compressed(src_buf) && > !igt_buf_compressed(dst_buf)) > return; > > bufs[0] = src_buf; > @@ -492,7 +492,7 @@ gen12_aux_pgtable_init(struct aux_pgtable_info > *info, > > /* Next, reserve space for unbound bufs with an AUX surface. */ > for (i = 0; i < ARRAY_SIZE(bufs); i++) > - if (!bufs[i]->bo->offset64 && bufs[i]->aux.stride) > + if (!bufs[i]->bo->offset64 && > igt_buf_compressed(bufs[i])) > aux_pgtable_reserve_range(reserved_bufs, > reserved_buf_count++, > bufs[i]); > @@ -500,7 +500,7 @@ gen12_aux_pgtable_init(struct aux_pgtable_info > *info, > /* Create AUX pgtable entries only for bufs with an AUX surface > */ > info->buf_count = 0; > for (i = 0; i < reserved_buf_count; i++) { > - if (!reserved_bufs[i]->aux.stride) > + if (!igt_buf_compressed(reserved_bufs[i])) > continue; > > info->bufs[info->buf_count] = reserved_bufs[i]; > diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h > index 37e3affe..c3028343 100644 > --- a/lib/intel_batchbuffer.h > +++ b/lib/intel_batchbuffer.h > @@ -249,6 +249,11 @@ struct igt_buf { > unsigned num_tiles; > }; > > +static inline bool igt_buf_compressed(const struct igt_buf *buf) > +{ > + return buf->compression != I915_COMPRESSION_NONE; > +} > + > unsigned igt_buf_width(const struct igt_buf *buf); > unsigned igt_buf_height(const struct igt_buf *buf); > > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c > index 63b1023d..88a94cbe 100644 > --- a/lib/rendercopy_gen9.c > +++ b/lib/rendercopy_gen9.c > @@ -259,7 +259,9 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > > if (buf->compression == I915_COMPRESSION_MEDIA) > ss->ss7.tgl.media_compression = 1; > - else if (buf->aux.stride) { > + else if (buf->compression == I915_COMPRESSION_RENDER) { > + igt_assert(buf->aux.stride); > + > ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */ > ss->ss6.aux_pitch = (buf->aux.stride / 128) - 1; > > @@ -274,6 +276,8 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > } > > if (buf->cc.offset) { > + igt_assert(buf->compression == > I915_COMPRESSION_RENDER); > + > ss->ss12.clear_address = buf->bo->offset64 + buf- > >cc.offset; > ss->ss13.clear_address_hi = (buf->bo->offset64 + buf- > >cc.offset) >> 32; > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t 02/10] lib/igt_buf: Extend igt_buf to include two CCS surfaces 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 01/10] lib/igt_buf: Use compression type consistently Imre Deak @ 2019-12-30 3:40 ` Imre Deak 2019-12-30 12:02 ` Kahola, Mika 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 03/10] lib/igt_buf: Extend igt_buf to include two color surfaces Imre Deak ` (13 subsequent siblings) 15 siblings, 1 reply; 33+ messages in thread From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw) To: igt-dev YUV FBs have two CCS surfaces so extend the igt_buf struct accordingly to support blitting such FBs. The patch is produced with the coccinelle patch below, along with some w/s fixup. No functional change. @@ @@ struct igt_buf { ... struct { uint32_t offset; uint32_t stride; - } aux; + } ccs[2]; ... }; @@ struct igt_buf *b; @@ ( - b->aux.offset + b->ccs[0].offset | - b->aux.stride + b->ccs[0].stride ) @@ struct igt_buf b; @@ ( - b.aux.offset + b.ccs[0].offset | - b.aux.stride + b.ccs[0].stride ) Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- lib/igt_fb.c | 4 ++-- lib/intel_aux_pgtable.c | 2 +- lib/intel_batchbuffer.h | 2 +- lib/rendercopy_gen9.c | 10 +++++----- tests/i915/gem_render_copy.c | 10 +++++----- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 7e99abb3..0e1b8493 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -1994,8 +1994,8 @@ static void init_buf(struct fb_blit_upload *blit, else buf->compression = I915_COMPRESSION_RENDER; - buf->aux.offset = fb->offsets[1]; - buf->aux.stride = fb->strides[1]; + buf->ccs[0].offset = fb->offsets[1]; + buf->ccs[0].stride = fb->strides[1]; } if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index f8ce6754..dab83a9a 100644 --- a/lib/intel_aux_pgtable.c +++ b/lib/intel_aux_pgtable.c @@ -256,7 +256,7 @@ pgt_populate_entries_for_buf(struct pgtable *pgt, { uint64_t surface_addr = buf->bo->offset64; uint64_t surface_end = surface_addr + buf->size; - uint64_t aux_addr = buf->bo->offset64 + buf->aux.offset; + uint64_t aux_addr = buf->bo->offset64 + buf->ccs[0].offset; uint64_t l1_flags = pgt_get_l1_flags(buf); uint64_t lx_flags = pgt_get_lx_flags(); diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index c3028343..63d32188 100644 --- a/lib/intel_batchbuffer.h +++ b/lib/intel_batchbuffer.h @@ -241,7 +241,7 @@ struct igt_buf { struct { uint32_t offset; uint32_t stride; - } aux; + } ccs[2]; struct { uint32_t offset; } cc; diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index 88a94cbe..4d4541e3 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -260,17 +260,17 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, if (buf->compression == I915_COMPRESSION_MEDIA) ss->ss7.tgl.media_compression = 1; else if (buf->compression == I915_COMPRESSION_RENDER) { - igt_assert(buf->aux.stride); + igt_assert(buf->ccs[0].stride); ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */ - ss->ss6.aux_pitch = (buf->aux.stride / 128) - 1; + ss->ss6.aux_pitch = (buf->ccs[0].stride / 128) - 1; - ss->ss10.aux_base_addr = buf->bo->offset64 + buf->aux.offset; - ss->ss11.aux_base_addr_hi = (buf->bo->offset64 + buf->aux.offset) >> 32; + ss->ss10.aux_base_addr = buf->bo->offset64 + buf->ccs[0].offset; + ss->ss11.aux_base_addr_hi = (buf->bo->offset64 + buf->ccs[0].offset) >> 32; ret = drm_intel_bo_emit_reloc(batch->bo, intel_batchbuffer_subdata_offset(batch, &ss->ss10), - buf->bo, buf->aux.offset, + buf->bo, buf->ccs[0].offset, read_domain, write_domain); assert(ret == 0); } diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c index 137c7c18..df0d045e 100644 --- a/tests/i915/gem_render_copy.c +++ b/tests/i915/gem_render_copy.c @@ -279,7 +279,7 @@ static void *linear_copy_aux(data_t *data, struct igt_buf *buf) map = gem_mmap__gtt(data->drm_fd, buf->bo->handle, buf->bo->size, PROT_READ); - igt_memcpy_from_wc(linear, map + buf->aux.offset, aux_size); + igt_memcpy_from_wc(linear, map + buf->ccs[0].offset, aux_size); munmap(map, buf->bo->size); @@ -300,7 +300,7 @@ static void scratch_buf_aux_write_to_png(data_t *data, CAIRO_FORMAT_A8, scratch_buf_aux_width(data->devid, buf), scratch_buf_aux_height(data->devid, buf), - buf->aux.stride); + buf->ccs[0].stride); ret = cairo_surface_write_to_png(surface, make_filename(filename)); igt_assert(ret == CAIRO_STATUS_SUCCESS); cairo_surface_destroy(surface); @@ -473,10 +473,10 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, aux_height = scratch_buf_aux_height(data->devid, buf); buf->compression = compression; - buf->aux.offset = buf->stride * ALIGN(height, 32); - buf->aux.stride = aux_width; + buf->ccs[0].offset = buf->stride * ALIGN(height, 32); + buf->ccs[0].stride = aux_width; - size = buf->aux.offset + aux_width * aux_height; + size = buf->ccs[0].offset + aux_width * aux_height; buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, 4096); -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 02/10] lib/igt_buf: Extend igt_buf to include two CCS surfaces 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 02/10] lib/igt_buf: Extend igt_buf to include two CCS surfaces Imre Deak @ 2019-12-30 12:02 ` Kahola, Mika 0 siblings, 0 replies; 33+ messages in thread From: Kahola, Mika @ 2019-12-30 12:02 UTC (permalink / raw) To: igt-dev@lists.freedesktop.org, Deak, Imre On Mon, 2019-12-30 at 05:40 +0200, Imre Deak wrote: > YUV FBs have two CCS surfaces so extend the igt_buf struct > accordingly > to support blitting such FBs. > > The patch is produced with the coccinelle patch below, along with > some > w/s fixup. > > No functional change. > > @@ > @@ > > struct igt_buf { > ... > struct { > uint32_t offset; > uint32_t stride; > - } aux; > + } ccs[2]; > ... > }; > > @@ > struct igt_buf *b; > @@ > > ( > - b->aux.offset > + b->ccs[0].offset > > > > - b->aux.stride > + b->ccs[0].stride > ) > > @@ > struct igt_buf b; > @@ > > ( > - b.aux.offset > + b.ccs[0].offset > > > > - b.aux.stride > + b.ccs[0].stride > ) > > Cc: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> > --- > lib/igt_fb.c | 4 ++-- > lib/intel_aux_pgtable.c | 2 +- > lib/intel_batchbuffer.h | 2 +- > lib/rendercopy_gen9.c | 10 +++++----- > tests/i915/gem_render_copy.c | 10 +++++----- > 5 files changed, 14 insertions(+), 14 deletions(-) > > diff --git a/lib/igt_fb.c b/lib/igt_fb.c > index 7e99abb3..0e1b8493 100644 > --- a/lib/igt_fb.c > +++ b/lib/igt_fb.c > @@ -1994,8 +1994,8 @@ static void init_buf(struct fb_blit_upload > *blit, > else > buf->compression = I915_COMPRESSION_RENDER; > > - buf->aux.offset = fb->offsets[1]; > - buf->aux.stride = fb->strides[1]; > + buf->ccs[0].offset = fb->offsets[1]; > + buf->ccs[0].stride = fb->strides[1]; > } > > if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c > index f8ce6754..dab83a9a 100644 > --- a/lib/intel_aux_pgtable.c > +++ b/lib/intel_aux_pgtable.c > @@ -256,7 +256,7 @@ pgt_populate_entries_for_buf(struct pgtable *pgt, > { > uint64_t surface_addr = buf->bo->offset64; > uint64_t surface_end = surface_addr + buf->size; > - uint64_t aux_addr = buf->bo->offset64 + buf->aux.offset; > + uint64_t aux_addr = buf->bo->offset64 + buf->ccs[0].offset; > uint64_t l1_flags = pgt_get_l1_flags(buf); > uint64_t lx_flags = pgt_get_lx_flags(); > > diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h > index c3028343..63d32188 100644 > --- a/lib/intel_batchbuffer.h > +++ b/lib/intel_batchbuffer.h > @@ -241,7 +241,7 @@ struct igt_buf { > struct { > uint32_t offset; > uint32_t stride; > - } aux; > + } ccs[2]; > struct { > uint32_t offset; > } cc; > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c > index 88a94cbe..4d4541e3 100644 > --- a/lib/rendercopy_gen9.c > +++ b/lib/rendercopy_gen9.c > @@ -260,17 +260,17 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > if (buf->compression == I915_COMPRESSION_MEDIA) > ss->ss7.tgl.media_compression = 1; > else if (buf->compression == I915_COMPRESSION_RENDER) { > - igt_assert(buf->aux.stride); > + igt_assert(buf->ccs[0].stride); > > ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */ > - ss->ss6.aux_pitch = (buf->aux.stride / 128) - 1; > + ss->ss6.aux_pitch = (buf->ccs[0].stride / 128) - 1; > > - ss->ss10.aux_base_addr = buf->bo->offset64 + buf- > >aux.offset; > - ss->ss11.aux_base_addr_hi = (buf->bo->offset64 + buf- > >aux.offset) >> 32; > + ss->ss10.aux_base_addr = buf->bo->offset64 + buf- > >ccs[0].offset; > + ss->ss11.aux_base_addr_hi = (buf->bo->offset64 + buf- > >ccs[0].offset) >> 32; > > ret = drm_intel_bo_emit_reloc(batch->bo, > intel_batchbuffer_subdata > _offset(batch, &ss->ss10), > - buf->bo, buf->aux.offset, > + buf->bo, buf- > >ccs[0].offset, > read_domain, > write_domain); > assert(ret == 0); > } > diff --git a/tests/i915/gem_render_copy.c > b/tests/i915/gem_render_copy.c > index 137c7c18..df0d045e 100644 > --- a/tests/i915/gem_render_copy.c > +++ b/tests/i915/gem_render_copy.c > @@ -279,7 +279,7 @@ static void *linear_copy_aux(data_t *data, struct > igt_buf *buf) > map = gem_mmap__gtt(data->drm_fd, buf->bo->handle, > buf->bo->size, PROT_READ); > > - igt_memcpy_from_wc(linear, map + buf->aux.offset, aux_size); > + igt_memcpy_from_wc(linear, map + buf->ccs[0].offset, aux_size); > > munmap(map, buf->bo->size); > > @@ -300,7 +300,7 @@ static void scratch_buf_aux_write_to_png(data_t > *data, > CAIRO_FORMAT_A8, > scratch_buf_aux_w > idth(data->devid, buf), > scratch_buf_aux_h > eight(data->devid, buf), > - buf->aux.stride); > + buf- > >ccs[0].stride); > ret = cairo_surface_write_to_png(surface, > make_filename(filename)); > igt_assert(ret == CAIRO_STATUS_SUCCESS); > cairo_surface_destroy(surface); > @@ -473,10 +473,10 @@ static void scratch_buf_init(data_t *data, > struct igt_buf *buf, > aux_height = scratch_buf_aux_height(data->devid, buf); > > buf->compression = compression; > - buf->aux.offset = buf->stride * ALIGN(height, 32); > - buf->aux.stride = aux_width; > + buf->ccs[0].offset = buf->stride * ALIGN(height, 32); > + buf->ccs[0].stride = aux_width; > > - size = buf->aux.offset + aux_width * aux_height; > + size = buf->ccs[0].offset + aux_width * aux_height; > > buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, > 4096); > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t 03/10] lib/igt_buf: Extend igt_buf to include two color surfaces 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 01/10] lib/igt_buf: Use compression type consistently Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 02/10] lib/igt_buf: Extend igt_buf to include two CCS surfaces Imre Deak @ 2019-12-30 3:40 ` Imre Deak 2019-12-30 12:06 ` Kahola, Mika 2019-12-30 17:58 ` [igt-dev] [PATCH i-g-t v2 " Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 04/10] lib: Add engine copy support for YUV formats Imre Deak ` (12 subsequent siblings) 15 siblings, 2 replies; 33+ messages in thread From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw) To: igt-dev UV FBs have two color surfaces so extend the igt_buf struct accordingly to support blitting such FBs. The patch is produced with the coccinelle patch below. No functional changes. @@ @@ struct igt_buf { ... - uint32_t stride; ... - uint32_t size; + struct { + uint32_t stride; + uint32_t size; + } surface[2]; ... }; @@ struct igt_buf b; @@ <... ( - b.stride + b.surface[0].stride | - b.size + b.surface[0].size ) ...> @@ struct igt_buf *b; @@ <... ( - b->size + b->surface[0].size | - b->stride + b->surface[0].stride ) ...> @@ identifier I; expression E1; expression E2; @@ ( struct igt_buf I = { - .size = E1, - .stride = E2, + .surface[0] = { + .size = E1, + .stride = E2, + }, }; | struct igt_buf I = { - .size = E1, + .surface[0] = { + .size = E1, + }, }; | struct igt_buf I = { - .stride = E1, + .surface[0] = { + .stride = E1, + }, }; ) Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- lib/gpu_cmds.c | 4 +- lib/igt_draw.c | 8 ++-- lib/igt_fb.c | 4 +- lib/intel_aux_pgtable.c | 5 ++- lib/intel_batchbuffer.c | 8 ++-- lib/intel_batchbuffer.h | 6 ++- lib/rendercopy_gen4.c | 4 +- lib/rendercopy_gen6.c | 4 +- lib/rendercopy_gen7.c | 4 +- lib/rendercopy_gen8.c | 4 +- lib/rendercopy_gen9.c | 4 +- lib/rendercopy_i830.c | 8 ++-- lib/rendercopy_i915.c | 8 ++-- lib/veboxcopy_gen12.c | 6 ++- tests/i915/gem_concurrent_all.c | 10 +++-- tests/i915/gem_gpgpu_fill.c | 4 +- tests/i915/gem_media_fill.c | 4 +- tests/i915/gem_media_vme.c | 6 +-- tests/i915/gem_ppgtt.c | 8 ++-- tests/i915/gem_read_read_speed.c | 10 +++-- tests/i915/gem_render_copy.c | 35 +++++++++-------- tests/i915/gem_render_copy_redux.c | 4 +- tests/i915/gem_render_linear_blits.c | 24 +++++------ tests/i915/gem_render_tiled_blits.c | 8 ++-- tests/i915/gem_ring_sync_copy.c | 4 +- tests/i915/gem_stress.c | 59 +++++++++++++++------------- tests/i915/i915_pm_sseu.c | 7 ++-- tests/kms_big_fb.c | 10 +++-- tests/kms_psr.c | 4 +- tests/perf.c | 4 +- 30 files changed, 149 insertions(+), 129 deletions(-) diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c index 8d270ee8..79412725 100644 --- a/lib/gpu_cmds.c +++ b/lib/gpu_cmds.c @@ -119,7 +119,7 @@ gen7_fill_surface_state(struct intel_batchbuffer *batch, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss7.shader_chanel_select_r = 4; ss->ss7.shader_chanel_select_g = 5; @@ -422,7 +422,7 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss7.shader_chanel_select_r = 4; ss->ss7.shader_chanel_select_g = 5; diff --git a/lib/igt_draw.c b/lib/igt_draw.c index 7e0edec1..6950bc49 100644 --- a/lib/igt_draw.c +++ b/lib/igt_draw.c @@ -603,14 +603,14 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data, igt_assert(dst); src_buf.bo = src; - src_buf.stride = tmp.stride; + src_buf.surface[0].stride = tmp.stride; src_buf.tiling = I915_TILING_NONE; - src_buf.size = tmp.size; + src_buf.surface[0].size = tmp.size; src_buf.bpp = tmp.bpp; dst_buf.bo = dst; - dst_buf.stride = buf->stride; + dst_buf.surface[0].stride = buf->stride; dst_buf.tiling = tiling; - dst_buf.size = buf->size; + dst_buf.surface[0].size = buf->size; dst_buf.bpp = buf->bpp; batch = intel_batchbuffer_alloc(cmd_data->bufmgr, devid); diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 0e1b8493..cc0fb373 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -1977,9 +1977,9 @@ static void init_buf(struct fb_blit_upload *blit, buf->bo = gem_handle_to_libdrm_bo(blit->bufmgr, blit->fd, name, fb->gem_handle); buf->tiling = igt_fb_mod_to_tiling(fb->modifier); - buf->stride = fb->strides[0]; + buf->surface[0].stride = fb->strides[0]; buf->bpp = fb->plane_bpp[0]; - buf->size = fb->size; + buf->surface[0].size = fb->size; if (is_ccs_modifier(fb->modifier)) { igt_assert_eq(fb->strides[0] & 127, 0); diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index dab83a9a..5addb2e2 100644 --- a/lib/intel_aux_pgtable.c +++ b/lib/intel_aux_pgtable.c @@ -77,7 +77,8 @@ pgt_table_count(int address_bits, const struct igt_buf **bufs, int buf_count) /* Avoid double counting for overlapping aligned bufs. */ start = max(start, end); - end = ALIGN(buf->bo->offset64 + buf->size, 1UL << address_bits); + end = ALIGN(buf->bo->offset64 + buf->surface[0].size, + 1UL << address_bits); igt_assert(end >= start); count += (end - start) >> address_bits; @@ -255,7 +256,7 @@ pgt_populate_entries_for_buf(struct pgtable *pgt, uint64_t top_table) { uint64_t surface_addr = buf->bo->offset64; - uint64_t surface_end = surface_addr + buf->size; + uint64_t surface_end = surface_addr + buf->surface[0].size; uint64_t aux_addr = buf->bo->offset64 + buf->ccs[0].offset; uint64_t l1_flags = pgt_get_l1_flags(buf); uint64_t lx_flags = pgt_get_lx_flags(); diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index 51aae4dc..3dc89024 100644 --- a/lib/intel_batchbuffer.c +++ b/lib/intel_batchbuffer.c @@ -512,7 +512,7 @@ intel_copy_bo(struct intel_batchbuffer *batch, */ unsigned igt_buf_width(const struct igt_buf *buf) { - return buf->stride/(buf->bpp / 8); + return buf->surface[0].stride/(buf->bpp / 8); } /** @@ -526,7 +526,7 @@ unsigned igt_buf_width(const struct igt_buf *buf) */ unsigned igt_buf_height(const struct igt_buf *buf) { - return buf->size/buf->stride; + return buf->surface[0].size/buf->surface[0].stride; } /* @@ -785,8 +785,8 @@ void igt_blitter_fast_copy(struct intel_batchbuffer *batch, igt_assert(src->bpp == dst->bpp); - src_pitch = fast_copy_pitch(src->stride, src->tiling); - dst_pitch = fast_copy_pitch(dst->stride, src->tiling); + src_pitch = fast_copy_pitch(src->surface[0].stride, src->tiling); + dst_pitch = fast_copy_pitch(dst->surface[0].stride, src->tiling); dword0 = fast_copy_dword0(src->tiling, dst->tiling); dword1 = fast_copy_dword1(src->tiling, dst->tiling, dst->bpp); diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index 63d32188..69580839 100644 --- a/lib/intel_batchbuffer.h +++ b/lib/intel_batchbuffer.h @@ -232,12 +232,14 @@ enum i915_compression { */ struct igt_buf { drm_intel_bo *bo; - uint32_t stride; uint32_t tiling; enum i915_compression compression; uint32_t bpp; uint32_t *data; - uint32_t size; + struct { + uint32_t stride; + uint32_t size; + } surface[2]; struct { uint32_t offset; uint32_t stride; diff --git a/lib/rendercopy_gen4.c b/lib/rendercopy_gen4.c index 42de77f9..d07b8e48 100644 --- a/lib/rendercopy_gen4.c +++ b/lib/rendercopy_gen4.c @@ -142,7 +142,7 @@ gen4_bind_buf(struct intel_batchbuffer *batch, uint32_t write_domain, read_domain; int ret; - igt_assert_lte(buf->stride, 128*1024); + igt_assert_lte(buf->surface[0].stride, 128*1024); igt_assert_lte(igt_buf_width(buf), 8192); igt_assert_lte(igt_buf_height(buf), 8192); @@ -176,7 +176,7 @@ gen4_bind_buf(struct intel_batchbuffer *batch, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c index 83c7d694..87034774 100644 --- a/lib/rendercopy_gen6.c +++ b/lib/rendercopy_gen6.c @@ -79,7 +79,7 @@ gen6_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, uint32_t write_domain, read_domain; int ret; - igt_assert_lte(buf->stride, 128*1024); + igt_assert_lte(buf->surface[0].stride, 128*1024); igt_assert_lte(igt_buf_width(buf), 8192); igt_assert_lte(igt_buf_height(buf), 8192); @@ -113,7 +113,7 @@ gen6_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c index a3c8b7f3..b88b75e9 100644 --- a/lib/rendercopy_gen7.c +++ b/lib/rendercopy_gen7.c @@ -65,7 +65,7 @@ gen7_bind_buf(struct intel_batchbuffer *batch, uint32_t write_domain, read_domain; int ret; - igt_assert_lte(buf->stride, 256*1024); + igt_assert_lte(buf->surface[0].stride, 256*1024); igt_assert_lte(igt_buf_width(buf), 16384); igt_assert_lte(igt_buf_height(buf), 16384); @@ -92,7 +92,7 @@ gen7_bind_buf(struct intel_batchbuffer *batch, ss[1] = buf->bo->offset; ss[2] = ((igt_buf_width(buf) - 1) << GEN7_SURFACE_WIDTH_SHIFT | (igt_buf_height(buf) - 1) << GEN7_SURFACE_HEIGHT_SHIFT); - ss[3] = (buf->stride - 1) << GEN7_SURFACE_PITCH_SHIFT; + ss[3] = (buf->surface[0].stride - 1) << GEN7_SURFACE_PITCH_SHIFT; ss[4] = 0; if (IS_VALLEYVIEW(batch->devid)) ss[5] = VLV_MOCS_L3 << 16; diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c index e22d8501..8e02d846 100644 --- a/lib/rendercopy_gen8.c +++ b/lib/rendercopy_gen8.c @@ -151,7 +151,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, uint32_t write_domain, read_domain, offset; int ret; - igt_assert_lte(buf->stride, 256*1024); + igt_assert_lte(buf->surface[0].stride, 256*1024); igt_assert_lte(igt_buf_width(buf), 16384); igt_assert_lte(igt_buf_height(buf), 16384); @@ -199,7 +199,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss7.shader_chanel_select_r = 4; ss->ss7.shader_chanel_select_g = 5; diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index 4d4541e3..835c8d80 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -199,7 +199,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, uint32_t write_domain, read_domain, offset; int ret; - igt_assert_lte(buf->stride, 256*1024); + igt_assert_lte(buf->surface[0].stride, 256*1024); igt_assert_lte(igt_buf_width(buf), 16384); igt_assert_lte(igt_buf_height(buf), 16384); @@ -250,7 +250,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss7.skl.shader_chanel_select_r = 4; ss->ss7.skl.shader_chanel_select_g = 5; diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c index e8c04718..ca815122 100644 --- a/lib/rendercopy_i830.c +++ b/lib/rendercopy_i830.c @@ -138,7 +138,7 @@ static void gen2_emit_target(struct intel_batchbuffer *batch, uint32_t tiling; uint32_t format; - igt_assert_lte(dst->stride, 8192); + igt_assert_lte(dst->surface[0].stride, 8192); igt_assert_lte(igt_buf_width(dst), 2048); igt_assert_lte(igt_buf_height(dst), 2048); @@ -156,7 +156,7 @@ static void gen2_emit_target(struct intel_batchbuffer *batch, tiling |= BUF_3D_TILE_WALK_Y; OUT_BATCH(_3DSTATE_BUF_INFO_CMD); - OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst->stride)); + OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst->surface[0].stride)); OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); @@ -179,7 +179,7 @@ static void gen2_emit_texture(struct intel_batchbuffer *batch, uint32_t tiling; uint32_t format; - igt_assert_lte(src->stride, 8192); + igt_assert_lte(src->surface[0].stride, 8192); igt_assert_lte(igt_buf_width(src), 2048); igt_assert_lte(igt_buf_height(src), 2048); @@ -201,7 +201,7 @@ static void gen2_emit_texture(struct intel_batchbuffer *batch, OUT_BATCH((igt_buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT | (igt_buf_width(src) - 1) << TM0S1_WIDTH_SHIFT | format | tiling); - OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D); + OUT_BATCH((src->surface[0].stride / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D); OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT | FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT | MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT); diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c index 1baa7a1b..56e1863e 100644 --- a/lib/rendercopy_i915.c +++ b/lib/rendercopy_i915.c @@ -88,7 +88,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch, #define TEX_COUNT 1 uint32_t format_bits, tiling_bits = 0; - igt_assert_lte(src->stride, 8192); + igt_assert_lte(src->surface[0].stride, 8192); igt_assert_lte(igt_buf_width(src), 2048); igt_assert_lte(igt_buf_height(src), 2048); @@ -110,7 +110,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch, OUT_BATCH(format_bits | tiling_bits | (igt_buf_height(src) - 1) << MS3_HEIGHT_SHIFT | (igt_buf_width(src) - 1) << MS3_WIDTH_SHIFT); - OUT_BATCH((src->stride/4-1) << MS4_PITCH_SHIFT); + OUT_BATCH((src->surface[0].stride/4-1) << MS4_PITCH_SHIFT); OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT)); OUT_BATCH((1 << TEX_COUNT) - 1); @@ -128,7 +128,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch, uint32_t tiling_bits = 0; uint32_t format_bits; - igt_assert_lte(dst->stride, 8192); + igt_assert_lte(dst->surface[0].stride, 8192); igt_assert_lte(igt_buf_width(dst), 2048); igt_assert_lte(igt_buf_height(dst), 2048); @@ -146,7 +146,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch, OUT_BATCH(_3DSTATE_BUF_INFO_CMD); OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits | - BUF_3D_PITCH(dst->stride)); + BUF_3D_PITCH(dst->surface[0].stride)); OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c index 87800941..2f017514 100644 --- a/lib/veboxcopy_gen12.c +++ b/lib/veboxcopy_gen12.c @@ -248,12 +248,14 @@ void gen12_vebox_copyfunc(struct intel_batchbuffer *batch, /* TODO: add support for more formats */ igt_assert(src->bpp == 32); emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT, - width, height, src->bpp, src->stride, + width, height, src->bpp, + src->surface[0].stride, src->tiling, R8G8B8A8_UNORM); igt_assert(dst->bpp == 32); emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT, - width, height, dst->bpp, dst->stride, + width, height, dst->bpp, + dst->surface[0].stride, dst->tiling, R8G8B8A8_UNORM); emit_tiling_convert_cmd(batch, diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c index 6486bebf..f1be4a85 100644 --- a/tests/i915/gem_concurrent_all.c +++ b/tests/i915/gem_concurrent_all.c @@ -851,15 +851,17 @@ static void render_copy_bo(struct buffers *b, drm_intel_bo *dst, drm_intel_bo *s { struct igt_buf d = { .bo = dst, - .size = b->npixels * 4, .num_tiles = b->npixels * 4, - .stride = b->width * 4, + .surface[0] = { + .size = b->npixels * 4, .stride = b->width * 4, + }, .bpp = 32, }, s = { .bo = src, - .size = b->npixels * 4, .num_tiles = b->npixels * 4, - .stride = b->width * 4, + .surface[0] = { + .size = b->npixels * 4, .stride = b->width * 4, + }, .bpp = 32, }; uint32_t swizzle; diff --git a/tests/i915/gem_gpgpu_fill.c b/tests/i915/gem_gpgpu_fill.c index 68918c3e..b2d401d6 100644 --- a/tests/i915/gem_gpgpu_fill.c +++ b/tests/i915/gem_gpgpu_fill.c @@ -75,9 +75,9 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = stride; + buf->surface[0].stride = stride; buf->tiling = I915_TILING_NONE; - buf->size = SIZE; + buf->surface[0].size = SIZE; buf->bpp = 32; } diff --git a/tests/i915/gem_media_fill.c b/tests/i915/gem_media_fill.c index a7d7708c..c880bae9 100644 --- a/tests/i915/gem_media_fill.c +++ b/tests/i915/gem_media_fill.c @@ -78,9 +78,9 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = stride; + buf->surface[0].stride = stride; buf->tiling = I915_TILING_NONE; - buf->size = SIZE; + buf->surface[0].size = SIZE; buf->bpp = 32; } diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c index d5045ad1..20f5ca35 100644 --- a/tests/i915/gem_media_vme.c +++ b/tests/i915/gem_media_vme.c @@ -58,7 +58,7 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, buf->bo = bo; buf->tiling = I915_TILING_NONE; - buf->size = size; + buf->surface[0].size = size; } static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf) @@ -71,14 +71,14 @@ static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf) * with this vme kernel. */ - buf->stride = STRIDE; + buf->surface[0].stride = STRIDE; } static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf) { scratch_buf_init(bufmgr, buf, OUTPUT_SIZE); - buf->stride = 1; + buf->surface[0].stride = 1; } static uint64_t switch_off_n_bits(uint64_t mask, unsigned int n) diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c index 89cdc4db..4c7d3ba2 100644 --- a/tests/i915/gem_ppgtt.c +++ b/tests/i915/gem_ppgtt.c @@ -73,9 +73,9 @@ static void scratch_buf_init(struct igt_buf *buf, memset(buf, 0, sizeof(*buf)); buf->bo = create_bo(bufmgr, pixel); - buf->stride = STRIDE; + buf->surface[0].stride = STRIDE; buf->tiling = I915_TILING_NONE; - buf->size = SIZE; + buf->surface[0].size = SIZE; buf->bpp = 32; } @@ -140,9 +140,9 @@ static void fork_rcs_copy(int timeout, uint32_t final, } buf.bo = dst[child]; - buf.stride = STRIDE; + buf.surface[0].stride = STRIDE; buf.tiling = I915_TILING_NONE; - buf.size = SIZE; + buf.surface[0].size = SIZE; buf.bpp = 32; i = 0; diff --git a/tests/i915/gem_read_read_speed.c b/tests/i915/gem_read_read_speed.c index 8b5ba8f7..2aab2204 100644 --- a/tests/i915/gem_read_read_speed.c +++ b/tests/i915/gem_read_read_speed.c @@ -53,15 +53,17 @@ static drm_intel_bo *rcs_copy_bo(drm_intel_bo *dst, drm_intel_bo *src) { struct igt_buf d = { .bo = dst, - .size = width * height * 4, .num_tiles = width * height * 4, - .stride = width * 4, + .surface[0] = { + .size = width * height * 4, .stride = width * 4, + }, .bpp = 32, }, s = { .bo = src, - .size = width * height * 4, .num_tiles = width * height * 4, - .stride = width * 4, + .surface[0] = { + .size = width * height * 4, .stride = width * 4, + }, .bpp = 32, }; uint32_t swizzle; diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c index df0d045e..5abb2036 100644 --- a/tests/i915/gem_render_copy.c +++ b/tests/i915/gem_render_copy.c @@ -118,7 +118,8 @@ static void copy_linear_to_yf(data_t *data, struct igt_buf *buf, for (int y = 0; y < height; y++) { for (int x = 0; x < width; x++) { uint32_t *ptr = yf_ptr(map, x, y, - buf->stride, buf->bpp / 8); + buf->surface[0].stride, + buf->bpp / 8); *ptr = linear[y * width + x]; } @@ -142,7 +143,8 @@ static void copy_yf_to_linear(data_t *data, struct igt_buf *buf, for (int y = 0; y < height; y++) { for (int x = 0; x < width; x++) { uint32_t *ptr = yf_ptr(map, x, y, - buf->stride, buf->bpp / 8); + buf->surface[0].stride, + buf->bpp / 8); linear[y * width + x] = *ptr; } @@ -231,7 +233,7 @@ static void scratch_buf_write_to_png(data_t *data, struct igt_buf *buf, CAIRO_FORMAT_RGB24, igt_buf_width(buf), igt_buf_height(buf), - buf->stride); + buf->surface[0].stride); ret = cairo_surface_write_to_png(surface, make_filename(filename)); igt_assert(ret == CAIRO_STATUS_SUCCESS); cairo_surface_destroy(surface); @@ -324,7 +326,7 @@ static void scratch_buf_draw_pattern(data_t *data, struct igt_buf *buf, CAIRO_FORMAT_RGB24, igt_buf_width(buf), igt_buf_height(buf), - buf->stride); + buf->surface[0].stride); cr = cairo_create(surface); @@ -403,7 +405,7 @@ scratch_buf_copy(data_t *data, for (int y = 0; y < h; y++) { for (int x = 0; x < w; x++) { const uint32_t *ptr = yf_ptr(map, sx+x, sy+y, - src->stride, + src->surface[0].stride, src->bpp / 8); linear_dst[(dy+y) * width + dx+x] = *ptr; @@ -458,14 +460,14 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, * turn mapped by one L1 AUX page table entry. */ if (intel_gen(data->devid) >= 12) - buf->stride = ALIGN(width * (bpp / 8), 128 * 4); + buf->surface[0].stride = ALIGN(width * (bpp / 8), 128 * 4); else - buf->stride = ALIGN(width * (bpp / 8), 128); + buf->surface[0].stride = ALIGN(width * (bpp / 8), 128); if (intel_gen(data->devid) >= 12) height = ALIGN(height, 4 * 32); - buf->size = buf->stride * height; + buf->surface[0].size = buf->surface[0].stride * height; buf->tiling = tiling; buf->bpp = bpp; @@ -473,7 +475,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, aux_height = scratch_buf_aux_height(data->devid, buf); buf->compression = compression; - buf->ccs[0].offset = buf->stride * ALIGN(height, 32); + buf->ccs[0].offset = buf->surface[0].stride * ALIGN(height, 32); buf->ccs[0].stride = aux_width; size = buf->ccs[0].offset + aux_width * aux_height; @@ -481,18 +483,19 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, 4096); if (tiling == I915_TILING_Y) { - drm_intel_bo_set_tiling(buf->bo, &tiling, buf->stride); + drm_intel_bo_set_tiling(buf->bo, &tiling, + buf->surface[0].stride); igt_assert_eq(tiling, req_tiling); } } else if (req_tiling == I915_TILING_Yf) { int size; - buf->stride = ALIGN(width * (bpp / 8), 128); - buf->size = buf->stride * height; + buf->surface[0].stride = ALIGN(width * (bpp / 8), 128); + buf->surface[0].size = buf->surface[0].stride * height; buf->tiling = tiling; buf->bpp = bpp; - size = buf->stride * ALIGN(height, 32); + size = buf->surface[0].stride * ALIGN(height, 32); buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, 4096); } else { @@ -501,9 +504,9 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, &tiling, &pitch, 0); igt_assert_eq(tiling, req_tiling); - buf->stride = pitch; + buf->surface[0].stride = pitch; buf->tiling = tiling; - buf->size = pitch * height; + buf->surface[0].size = pitch * height; buf->bpp = bpp; } @@ -806,7 +809,7 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling, 0, 0, igt_buf_width(&dst), igt_buf_height(&dst), AUB_DUMP_BMP_FORMAT_ARGB_8888, - dst.stride, 0); + dst.surface[0].stride, 0); drm_intel_bufmgr_gem_set_aub_dump(data->bufmgr, false); } else if (check_all_pixels) { scratch_buf_check_all(data, &dst, &ref); diff --git a/tests/i915/gem_render_copy_redux.c b/tests/i915/gem_render_copy_redux.c index ef601c22..2388fc24 100644 --- a/tests/i915/gem_render_copy_redux.c +++ b/tests/i915/gem_render_copy_redux.c @@ -106,9 +106,9 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = stride; + buf->surface[0].stride = stride; buf->tiling = I915_TILING_NONE; - buf->size = SIZE; + buf->surface[0].size = SIZE; buf->bpp = 32; } diff --git a/tests/i915/gem_render_linear_blits.c b/tests/i915/gem_render_linear_blits.c index a726652b..666a43cd 100644 --- a/tests/i915/gem_render_linear_blits.c +++ b/tests/i915/gem_render_linear_blits.c @@ -108,15 +108,15 @@ static void run_test (int fd, int count) struct igt_buf src = {}, dst = {}; src.bo = bo[i % count]; - src.stride = STRIDE; + src.surface[0].stride = STRIDE; src.tiling = I915_TILING_NONE; - src.size = SIZE; + src.surface[0].size = SIZE; src.bpp = 32; dst.bo = bo[(i + 1) % count]; - dst.stride = STRIDE; + dst.surface[0].stride = STRIDE; dst.tiling = I915_TILING_NONE; - dst.size = SIZE; + dst.surface[0].size = SIZE; dst.bpp = 32; render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, &dst, 0, 0); @@ -133,15 +133,15 @@ static void run_test (int fd, int count) struct igt_buf src = {}, dst = {}; src.bo = bo[(i + 1) % count]; - src.stride = STRIDE; + src.surface[0].stride = STRIDE; src.tiling = I915_TILING_NONE; - src.size = SIZE; + src.surface[0].size = SIZE; src.bpp = 32; dst.bo = bo[i % count]; - dst.stride = STRIDE; + dst.surface[0].stride = STRIDE; dst.tiling = I915_TILING_NONE; - dst.size = SIZE; + dst.surface[0].size = SIZE; dst.bpp = 32; render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, &dst, 0, 0); @@ -160,15 +160,15 @@ static void run_test (int fd, int count) continue; src.bo = bo[s]; - src.stride = STRIDE; + src.surface[0].stride = STRIDE; src.tiling = I915_TILING_NONE; - src.size = SIZE; + src.surface[0].size = SIZE; src.bpp = 32; dst.bo = bo[d]; - dst.stride = STRIDE; + dst.surface[0].stride = STRIDE; dst.tiling = I915_TILING_NONE; - dst.size = SIZE; + dst.surface[0].size = SIZE; dst.bpp = 32; render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, &dst, 0, 0); diff --git a/tests/i915/gem_render_tiled_blits.c b/tests/i915/gem_render_tiled_blits.c index 14018329..1de1b72c 100644 --- a/tests/i915/gem_render_tiled_blits.c +++ b/tests/i915/gem_render_tiled_blits.c @@ -66,9 +66,9 @@ check_bo(struct intel_batchbuffer *batch, struct igt_buf *buf, uint32_t val) int i; tmp.bo = linear; - tmp.stride = STRIDE; + tmp.surface[0].stride = STRIDE; tmp.tiling = I915_TILING_NONE; - tmp.size = SIZE; + tmp.surface[0].size = SIZE; tmp.bpp = 32; render_copy(batch, NULL, buf, 0, 0, WIDTH, HEIGHT, &tmp, 0, 0); @@ -132,9 +132,9 @@ static void run_test (int fd, int count) buf[i].bo = drm_intel_bo_alloc_tiled(bufmgr, "", WIDTH, HEIGHT, 4, &tiling, &pitch, 0); - buf[i].stride = pitch; + buf[i].surface[0].stride = pitch; buf[i].tiling = tiling; - buf[i].size = SIZE; + buf[i].surface[0].size = SIZE; buf[i].bpp = 32; start_val[i] = start; diff --git a/tests/i915/gem_ring_sync_copy.c b/tests/i915/gem_ring_sync_copy.c index 1e5728bc..ddf5f750 100644 --- a/tests/i915/gem_ring_sync_copy.c +++ b/tests/i915/gem_ring_sync_copy.c @@ -134,9 +134,9 @@ static void scratch_buf_init_from_bo(struct igt_buf *buf, drm_intel_bo *bo) memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = 4 * WIDTH; + buf->surface[0].stride = 4 * WIDTH; buf->tiling = I915_TILING_NONE; - buf->size = 4 * WIDTH * HEIGHT; + buf->surface[0].size = 4 * WIDTH * HEIGHT; buf->bpp = 32; } diff --git a/tests/i915/gem_stress.c b/tests/i915/gem_stress.c index 57e2909c..50245b93 100644 --- a/tests/i915/gem_stress.c +++ b/tests/i915/gem_stress.c @@ -155,8 +155,8 @@ struct { static void tile2xy(struct igt_buf *buf, unsigned tile, unsigned *x, unsigned *y) { igt_assert(tile < buf->num_tiles); - *x = (tile*options.tile_size) % (buf->stride/sizeof(uint32_t)); - *y = ((tile*options.tile_size) / (buf->stride/sizeof(uint32_t))) * options.tile_size; + *x = (tile*options.tile_size) % (buf->surface[0].stride/sizeof(uint32_t)); + *y = ((tile*options.tile_size) / (buf->surface[0].stride/sizeof(uint32_t))) * options.tile_size; } static void emit_blt(drm_intel_bo *src_bo, uint32_t src_tiling, unsigned src_pitch, @@ -268,8 +268,10 @@ static void cpu_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y, set_to_cpu_domain(dst, 1); } - cpucpy2d(src->data, src->stride/sizeof(uint32_t), src_x, src_y, - dst->data, dst->stride/sizeof(uint32_t), dst_x, dst_y, + cpucpy2d(src->data, src->surface[0].stride/sizeof(uint32_t), src_x, + src_y, + dst->data, dst->surface[0].stride/sizeof(uint32_t), dst_x, + dst_y, logical_tile_no); } @@ -287,7 +289,7 @@ static void prw_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y, if (src->tiling == I915_TILING_NONE) { for (i = 0; i < options.tile_size; i++) { - unsigned ofs = src_x*sizeof(uint32_t) + src->stride*(src_y + i); + unsigned ofs = src_x*sizeof(uint32_t) + src->surface[0].stride*(src_y + i); drm_intel_bo_get_subdata(src->bo, ofs, options.tile_size*sizeof(uint32_t), tmp_tile + options.tile_size*i); @@ -296,13 +298,14 @@ static void prw_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y, if (options.use_cpu_maps) set_to_cpu_domain(src, 0); - cpucpy2d(src->data, src->stride/sizeof(uint32_t), src_x, src_y, + cpucpy2d(src->data, src->surface[0].stride/sizeof(uint32_t), + src_x, src_y, tmp_tile, options.tile_size, 0, 0, logical_tile_no); } if (dst->tiling == I915_TILING_NONE) { for (i = 0; i < options.tile_size; i++) { - unsigned ofs = dst_x*sizeof(uint32_t) + dst->stride*(dst_y + i); + unsigned ofs = dst_x*sizeof(uint32_t) + dst->surface[0].stride*(dst_y + i); drm_intel_bo_subdata(dst->bo, ofs, options.tile_size*sizeof(uint32_t), tmp_tile + options.tile_size*i); @@ -312,7 +315,8 @@ static void prw_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y, set_to_cpu_domain(dst, 1); cpucpy2d(tmp_tile, options.tile_size, 0, 0, - dst->data, dst->stride/sizeof(uint32_t), dst_x, dst_y, + dst->data, dst->surface[0].stride/sizeof(uint32_t), + dst_x, dst_y, logical_tile_no); } } @@ -327,9 +331,9 @@ static void blitter_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y if (keep_gpu_busy_counter & 1 && !fence_storm) keep_gpu_busy(); - emit_blt(src->bo, src->tiling, src->stride, src_x, src_y, + emit_blt(src->bo, src->tiling, src->surface[0].stride, src_x, src_y, options.tile_size, options.tile_size, - dst->bo, dst->tiling, dst->stride, dst_x, dst_y); + dst->bo, dst->tiling, dst->surface[0].stride, dst_x, dst_y); if (!(keep_gpu_busy_counter & 1) && !fence_storm) keep_gpu_busy(); @@ -441,7 +445,7 @@ static void fan_out(void) cpucpy2d(tmp_tile, options.tile_size, 0, 0, buffers[current_set][buf_idx].data, - buffers[current_set][buf_idx].stride / sizeof(uint32_t), + buffers[current_set][buf_idx].surface[0].stride / sizeof(uint32_t), x, y, i); } @@ -465,7 +469,7 @@ static void fan_in_and_check(void) set_to_cpu_domain(&buffers[current_set][buf_idx], 0); cpucpy2d(buffers[current_set][buf_idx].data, - buffers[current_set][buf_idx].stride / sizeof(uint32_t), + buffers[current_set][buf_idx].surface[0].stride / sizeof(uint32_t), x, y, tmp_tile, options.tile_size, 0, 0, i); @@ -476,15 +480,15 @@ static void sanitize_stride(struct igt_buf *buf) { if (igt_buf_height(buf) > options.max_dimension) - buf->stride = buf->size / options.max_dimension; + buf->surface[0].stride = buf->surface[0].size / options.max_dimension; if (igt_buf_height(buf) < options.tile_size) - buf->stride = buf->size / options.tile_size; + buf->surface[0].stride = buf->surface[0].size / options.tile_size; if (igt_buf_width(buf) < options.tile_size) - buf->stride = options.tile_size * sizeof(uint32_t); + buf->surface[0].stride = options.tile_size * sizeof(uint32_t); - igt_assert(buf->stride <= 8192); + igt_assert(buf->surface[0].stride <= 8192); igt_assert(igt_buf_width(buf) <= options.max_dimension); igt_assert(igt_buf_height(buf) <= options.max_dimension); @@ -498,10 +502,10 @@ static void init_buffer(struct igt_buf *buf, unsigned size) memset(buf, 0, sizeof(*buf)); buf->bo = drm_intel_bo_alloc(bufmgr, "tiled bo", size, 4096); - buf->size = size; + buf->surface[0].size = size; igt_assert(buf->bo); buf->tiling = I915_TILING_NONE; - buf->stride = 4096; + buf->surface[0].stride = 4096; buf->bpp = 32; sanitize_stride(buf); @@ -560,25 +564,26 @@ static void init_set(unsigned set) if (buffers[set][i].tiling == I915_TILING_NONE) { /* min 64 byte stride */ r %= 8; - buffers[set][i].stride = 64 * (1 << r); + buffers[set][i].surface[0].stride = 64 * (1 << r); } else if (IS_GEN2(devid)) { /* min 128 byte stride */ r %= 7; - buffers[set][i].stride = 128 * (1 << r); + buffers[set][i].surface[0].stride = 128 * (1 << r); } else { /* min 512 byte stride */ r %= 5; - buffers[set][i].stride = 512 * (1 << r); + buffers[set][i].surface[0].stride = 512 * (1 << r); } sanitize_stride(&buffers[set][i]); gem_set_tiling(drm_fd, buffers[set][i].bo->handle, buffers[set][i].tiling, - buffers[set][i].stride); + buffers[set][i].surface[0].stride); if (options.trace_tile != -1 && i == options.trace_tile/options.tiles_per_buf) - igt_info("changing buffer %i containing tile %i: tiling %i, stride %i\n", i, options.trace_tile, buffers[set][i].tiling, buffers[set][i].stride); + igt_info("changing buffer %i containing tile %i: tiling %i, stride %i\n", i, options.trace_tile, buffers[set][i].tiling, + buffers[set][i].surface[0].stride); } } @@ -616,10 +621,10 @@ static void copy_tiles(unsigned *permutation) if (options.no_hw) { cpucpy2d(src_buf->data, - src_buf->stride / sizeof(uint32_t), + src_buf->surface[0].stride / sizeof(uint32_t), src_x, src_y, dst_buf->data, - dst_buf->stride / sizeof(uint32_t), + dst_buf->surface[0].stride / sizeof(uint32_t), dst_x, dst_y, i); } else { @@ -808,7 +813,7 @@ static void check_render_copyfunc(void) memset(src.data, 0xff, options.scratch_buf_size); for (j = 0; j < options.tile_size; j++) { - ptr = (uint32_t*)((char *)src.data + sx*4 + (sy+j) * src.stride); + ptr = (uint32_t*)((char *)src.data + sx*4 + (sy+j) * src.surface[0].stride); for (i = 0; i < options.tile_size; i++) ptr[i] = j * options.tile_size + i; } @@ -819,7 +824,7 @@ static void check_render_copyfunc(void) set_to_cpu_domain(&dst, 0); for (j = 0; j < options.tile_size; j++) { - ptr = (uint32_t*)((char *)dst.data + dx*4 + (dy+j) * dst.stride); + ptr = (uint32_t*)((char *)dst.data + dx*4 + (dy+j) * dst.surface[0].stride); for (i = 0; i < options.tile_size; i++) if (ptr[i] != j * options.tile_size + i) { igt_info("render copyfunc mismatch at (%d, %d): found %d, expected %d\n", i, j, ptr[i], j * options.tile_size + i); diff --git a/tests/i915/i915_pm_sseu.c b/tests/i915/i915_pm_sseu.c index e671e190..c2dee118 100644 --- a/tests/i915/i915_pm_sseu.c +++ b/tests/i915/i915_pm_sseu.c @@ -299,10 +299,11 @@ gem_init(void) igt_assert(gem.batch); gem.init = 3; - gem.buf.stride = sizeof(uint32_t); + gem.buf.surface[0].stride = sizeof(uint32_t); gem.buf.tiling = I915_TILING_NONE; - gem.buf.size = gem.buf.stride; - gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", gem.buf.size, 4096); + gem.buf.surface[0].size = gem.buf.surface[0].stride; + gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", + gem.buf.surface[0].size, 4096); gem.buf.bpp = 32; igt_assert(gem.buf.bo); gem.init = 4; diff --git a/tests/kms_big_fb.c b/tests/kms_big_fb.c index c5d002ca..eb144da9 100644 --- a/tests/kms_big_fb.c +++ b/tests/kms_big_fb.c @@ -60,9 +60,9 @@ static void init_buf(data_t *data, buf->bo = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, name, fb->gem_handle); buf->tiling = igt_fb_mod_to_tiling(fb->modifier); - buf->stride = fb->strides[0]; + buf->surface[0].stride = fb->strides[0]; buf->bpp = fb->plane_bpp[0]; - buf->size = fb->size; + buf->surface[0].size = fb->size; } static void fini_buf(struct igt_buf *buf) @@ -99,8 +99,10 @@ static void copy_pattern(data_t *data, h = min(h, src_fb->height - sy); h = min(h, dst_fb->height - dy); - intel_blt_copy(data->batch, src.bo, sx, sy, src.stride, - dst.bo, dx, dy, dst.stride, w, h, dst.bpp); + intel_blt_copy(data->batch, src.bo, sx, sy, + src.surface[0].stride, + dst.bo, dx, dy, dst.surface[0].stride, w, h, + dst.bpp); } fini_buf(&dst); diff --git a/tests/kms_psr.c b/tests/kms_psr.c index 232c80aa..d9be87d9 100644 --- a/tests/kms_psr.c +++ b/tests/kms_psr.c @@ -153,9 +153,9 @@ static void scratch_buf_init(struct igt_buf *buf, drm_intel_bo *bo, memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = stride; + buf->surface[0].stride = stride; buf->tiling = I915_TILING_X; - buf->size = size; + buf->surface[0].size = size; buf->bpp = 32; } diff --git a/tests/perf.c b/tests/perf.c index f5dd6051..982277df 100644 --- a/tests/perf.c +++ b/tests/perf.c @@ -506,9 +506,9 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = stride; + buf->surface[0].stride = stride; buf->tiling = I915_TILING_NONE; - buf->size = size; + buf->surface[0].size = size; buf->bpp = 32; } -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 03/10] lib/igt_buf: Extend igt_buf to include two color surfaces 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 03/10] lib/igt_buf: Extend igt_buf to include two color surfaces Imre Deak @ 2019-12-30 12:06 ` Kahola, Mika 2019-12-30 12:58 ` Imre Deak 2019-12-30 17:58 ` [igt-dev] [PATCH i-g-t v2 " Imre Deak 1 sibling, 1 reply; 33+ messages in thread From: Kahola, Mika @ 2019-12-30 12:06 UTC (permalink / raw) To: igt-dev@lists.freedesktop.org, Deak, Imre On Mon, 2019-12-30 at 05:40 +0200, Imre Deak wrote: > UV FBs have two color surfaces so extend the igt_buf struct > accordingly > to support blitting such FBs. > > The patch is produced with the coccinelle patch below. > > No functional changes. When applying this patch, the compiler started to nag about [75/672] Compiling C object 'tests/59830eb@@kms_cursor_crc@exe/kms_curs or_crc.c.o'. FAILED: tests/59830eb@@kms_cursor_crc@exe/kms_cursor_crc.c.o ccache cc -Itests/59830eb@@kms_cursor_crc@exe -Itests -I../tests -I../include/drm-uapi -Ilib -I../lib -I../lib/stubs/syscalls -I. -I../ -I/usr/include/cairo -I/usr/include/glib-2.0 -I/usr/lib/x86_64-linux- gnu/glib-2.0/include -I/usr/include/pixman-1 -I/usr/include/freetype2 -I/usr/include/libpng16 -I/usr/include/libdrm -I/usr/include/x86_64- linux-gnu -I/usr/include/alsa -I/usr/include/libdrm/nouveau -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Wextra -std=gnu11 -O2 -g -D_GNU_SOURCE -include config.h -D_FORTIFY_SOURCE=2 -Wbad-function-cast -Wdeclaration-after-statement -Wformat=2 -Wimplicit-fallthrough=0 -Wlogical-op -Wmissing-declarations -Wmissing-format-attribute -Wmissing-noreturn -Wmissing-prototypes -Wnested-externs -Wold-style-definition -Wpointer-arith -Wredundant- decls -Wshadow -Wstrict-prototypes -Wuninitialized -Wunused -Wno- clobbered -Wno-maybe-uninitialized -Wno-missing-field-initializers -Wno-pointer-arith -Wno-sign-compare -Wno-type-limits -Wno-unused- parameter -Wno-unused-result -Werror=address -Werror=array-bounds -Werror=implicit -Werror=init-self -Werror=int-to-pointer-cast -Werror=main -Werror=missing-braces -Werror=nonnull -Werror=pointer-to- int-cast -Werror=return-type -Werror=sequence-point -Werror=trigraphs -Werror=write-strings -fno-builtin-malloc -fno-builtin-calloc -pthread -MD -MQ 'tests/59830eb@@kms_cursor_crc@exe/kms_cursor_crc.c.o ' -MF 'tests/59830eb@@kms_cursor_crc@exe/kms_cursor_crc.c.o.d' -o 'tests/59830eb@@kms_cursor_crc@exe/kms_cursor_crc.c.o' -c ../tests/kms_cursor_crc.c ../tests/kms_cursor_crc.c: In function ‘scratch_buf_init’: ../tests/kms_cursor_crc.c:388:21: error: ‘struct igt_buf’ has no member named ‘stride’ data->igtbo[buffer].stride = data->primary_fb[buffer].strides[0]; ^ ../tests/kms_cursor_crc.c:390:21: error: ‘struct igt_buf’ has no member named ‘size’ data->igtbo[buffer].size = data->primary_fb[buffer].size; ^ [84/672] Compiling C object 'tests/59830eb@@kms_cursor_legacy@exe/kms_c ursor_legacy.c.o'. ninja: build stopped: subcommand failed. > > @@ > @@ > > struct igt_buf { > ... > - uint32_t stride; > ... > - uint32_t size; > + struct { > + uint32_t stride; > + uint32_t size; > + } surface[2]; > ... > }; > > @@ > struct igt_buf b; > @@ > > <... > ( > - b.stride > + b.surface[0].stride > > > > - b.size > + b.surface[0].size > ) > ...> > > @@ > struct igt_buf *b; > @@ > > <... > ( > - b->size > + b->surface[0].size > > > > - b->stride > + b->surface[0].stride > ) > ...> > > @@ > identifier I; > expression E1; > expression E2; > @@ > > ( > struct igt_buf I = { > - .size = E1, > - .stride = E2, > + .surface[0] = { > + .size = E1, > + .stride = E2, > + }, > }; > > > > struct igt_buf I = { > - .size = E1, > + .surface[0] = { > + .size = E1, > + }, > }; > > > > struct igt_buf I = { > - .stride = E1, > + .surface[0] = { > + .stride = E1, > + }, > }; > ) > > Cc: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > lib/gpu_cmds.c | 4 +- > lib/igt_draw.c | 8 ++-- > lib/igt_fb.c | 4 +- > lib/intel_aux_pgtable.c | 5 ++- > lib/intel_batchbuffer.c | 8 ++-- > lib/intel_batchbuffer.h | 6 ++- > lib/rendercopy_gen4.c | 4 +- > lib/rendercopy_gen6.c | 4 +- > lib/rendercopy_gen7.c | 4 +- > lib/rendercopy_gen8.c | 4 +- > lib/rendercopy_gen9.c | 4 +- > lib/rendercopy_i830.c | 8 ++-- > lib/rendercopy_i915.c | 8 ++-- > lib/veboxcopy_gen12.c | 6 ++- > tests/i915/gem_concurrent_all.c | 10 +++-- > tests/i915/gem_gpgpu_fill.c | 4 +- > tests/i915/gem_media_fill.c | 4 +- > tests/i915/gem_media_vme.c | 6 +-- > tests/i915/gem_ppgtt.c | 8 ++-- > tests/i915/gem_read_read_speed.c | 10 +++-- > tests/i915/gem_render_copy.c | 35 +++++++++-------- > tests/i915/gem_render_copy_redux.c | 4 +- > tests/i915/gem_render_linear_blits.c | 24 +++++------ > tests/i915/gem_render_tiled_blits.c | 8 ++-- > tests/i915/gem_ring_sync_copy.c | 4 +- > tests/i915/gem_stress.c | 59 +++++++++++++++----------- > -- > tests/i915/i915_pm_sseu.c | 7 ++-- > tests/kms_big_fb.c | 10 +++-- > tests/kms_psr.c | 4 +- > tests/perf.c | 4 +- > 30 files changed, 149 insertions(+), 129 deletions(-) > > diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c > index 8d270ee8..79412725 100644 > --- a/lib/gpu_cmds.c > +++ b/lib/gpu_cmds.c > @@ -119,7 +119,7 @@ gen7_fill_surface_state(struct intel_batchbuffer > *batch, > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > > ss->ss7.shader_chanel_select_r = 4; > ss->ss7.shader_chanel_select_g = 5; > @@ -422,7 +422,7 @@ gen8_fill_surface_state(struct intel_batchbuffer > *batch, > > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > > ss->ss7.shader_chanel_select_r = 4; > ss->ss7.shader_chanel_select_g = 5; > diff --git a/lib/igt_draw.c b/lib/igt_draw.c > index 7e0edec1..6950bc49 100644 > --- a/lib/igt_draw.c > +++ b/lib/igt_draw.c > @@ -603,14 +603,14 @@ static void draw_rect_render(int fd, struct > cmd_data *cmd_data, > igt_assert(dst); > > src_buf.bo = src; > - src_buf.stride = tmp.stride; > + src_buf.surface[0].stride = tmp.stride; > src_buf.tiling = I915_TILING_NONE; > - src_buf.size = tmp.size; > + src_buf.surface[0].size = tmp.size; > src_buf.bpp = tmp.bpp; > dst_buf.bo = dst; > - dst_buf.stride = buf->stride; > + dst_buf.surface[0].stride = buf->stride; > dst_buf.tiling = tiling; > - dst_buf.size = buf->size; > + dst_buf.surface[0].size = buf->size; > dst_buf.bpp = buf->bpp; > > batch = intel_batchbuffer_alloc(cmd_data->bufmgr, devid); > diff --git a/lib/igt_fb.c b/lib/igt_fb.c > index 0e1b8493..cc0fb373 100644 > --- a/lib/igt_fb.c > +++ b/lib/igt_fb.c > @@ -1977,9 +1977,9 @@ static void init_buf(struct fb_blit_upload > *blit, > buf->bo = gem_handle_to_libdrm_bo(blit->bufmgr, blit->fd, > name, fb->gem_handle); > buf->tiling = igt_fb_mod_to_tiling(fb->modifier); > - buf->stride = fb->strides[0]; > + buf->surface[0].stride = fb->strides[0]; > buf->bpp = fb->plane_bpp[0]; > - buf->size = fb->size; > + buf->surface[0].size = fb->size; > > if (is_ccs_modifier(fb->modifier)) { > igt_assert_eq(fb->strides[0] & 127, 0); > diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c > index dab83a9a..5addb2e2 100644 > --- a/lib/intel_aux_pgtable.c > +++ b/lib/intel_aux_pgtable.c > @@ -77,7 +77,8 @@ pgt_table_count(int address_bits, const struct > igt_buf **bufs, int buf_count) > /* Avoid double counting for overlapping aligned bufs. > */ > start = max(start, end); > > - end = ALIGN(buf->bo->offset64 + buf->size, 1UL << > address_bits); > + end = ALIGN(buf->bo->offset64 + buf->surface[0].size, > + 1UL << address_bits); > igt_assert(end >= start); > > count += (end - start) >> address_bits; > @@ -255,7 +256,7 @@ pgt_populate_entries_for_buf(struct pgtable *pgt, > uint64_t top_table) > { > uint64_t surface_addr = buf->bo->offset64; > - uint64_t surface_end = surface_addr + buf->size; > + uint64_t surface_end = surface_addr + buf->surface[0].size; > uint64_t aux_addr = buf->bo->offset64 + buf->ccs[0].offset; > uint64_t l1_flags = pgt_get_l1_flags(buf); > uint64_t lx_flags = pgt_get_lx_flags(); > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c > index 51aae4dc..3dc89024 100644 > --- a/lib/intel_batchbuffer.c > +++ b/lib/intel_batchbuffer.c > @@ -512,7 +512,7 @@ intel_copy_bo(struct intel_batchbuffer *batch, > */ > unsigned igt_buf_width(const struct igt_buf *buf) > { > - return buf->stride/(buf->bpp / 8); > + return buf->surface[0].stride/(buf->bpp / 8); > } > > /** > @@ -526,7 +526,7 @@ unsigned igt_buf_width(const struct igt_buf *buf) > */ > unsigned igt_buf_height(const struct igt_buf *buf) > { > - return buf->size/buf->stride; > + return buf->surface[0].size/buf->surface[0].stride; > } > > /* > @@ -785,8 +785,8 @@ void igt_blitter_fast_copy(struct > intel_batchbuffer *batch, > > igt_assert(src->bpp == dst->bpp); > > - src_pitch = fast_copy_pitch(src->stride, src->tiling); > - dst_pitch = fast_copy_pitch(dst->stride, src->tiling); > + src_pitch = fast_copy_pitch(src->surface[0].stride, src- > >tiling); > + dst_pitch = fast_copy_pitch(dst->surface[0].stride, src- > >tiling); > dword0 = fast_copy_dword0(src->tiling, dst->tiling); > dword1 = fast_copy_dword1(src->tiling, dst->tiling, dst->bpp); > > diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h > index 63d32188..69580839 100644 > --- a/lib/intel_batchbuffer.h > +++ b/lib/intel_batchbuffer.h > @@ -232,12 +232,14 @@ enum i915_compression { > */ > struct igt_buf { > drm_intel_bo *bo; > - uint32_t stride; > uint32_t tiling; > enum i915_compression compression; > uint32_t bpp; > uint32_t *data; > - uint32_t size; > + struct { > + uint32_t stride; > + uint32_t size; > + } surface[2]; > struct { > uint32_t offset; > uint32_t stride; > diff --git a/lib/rendercopy_gen4.c b/lib/rendercopy_gen4.c > index 42de77f9..d07b8e48 100644 > --- a/lib/rendercopy_gen4.c > +++ b/lib/rendercopy_gen4.c > @@ -142,7 +142,7 @@ gen4_bind_buf(struct intel_batchbuffer *batch, > uint32_t write_domain, read_domain; > int ret; > > - igt_assert_lte(buf->stride, 128*1024); > + igt_assert_lte(buf->surface[0].stride, 128*1024); > igt_assert_lte(igt_buf_width(buf), 8192); > igt_assert_lte(igt_buf_height(buf), 8192); > > @@ -176,7 +176,7 @@ gen4_bind_buf(struct intel_batchbuffer *batch, > > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; > ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; > > diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c > index 83c7d694..87034774 100644 > --- a/lib/rendercopy_gen6.c > +++ b/lib/rendercopy_gen6.c > @@ -79,7 +79,7 @@ gen6_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > uint32_t write_domain, read_domain; > int ret; > > - igt_assert_lte(buf->stride, 128*1024); > + igt_assert_lte(buf->surface[0].stride, 128*1024); > igt_assert_lte(igt_buf_width(buf), 8192); > igt_assert_lte(igt_buf_height(buf), 8192); > > @@ -113,7 +113,7 @@ gen6_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; > ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; > > diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c > index a3c8b7f3..b88b75e9 100644 > --- a/lib/rendercopy_gen7.c > +++ b/lib/rendercopy_gen7.c > @@ -65,7 +65,7 @@ gen7_bind_buf(struct intel_batchbuffer *batch, > uint32_t write_domain, read_domain; > int ret; > > - igt_assert_lte(buf->stride, 256*1024); > + igt_assert_lte(buf->surface[0].stride, 256*1024); > igt_assert_lte(igt_buf_width(buf), 16384); > igt_assert_lte(igt_buf_height(buf), 16384); > > @@ -92,7 +92,7 @@ gen7_bind_buf(struct intel_batchbuffer *batch, > ss[1] = buf->bo->offset; > ss[2] = ((igt_buf_width(buf) - 1) << GEN7_SURFACE_WIDTH_SHIFT > | > (igt_buf_height(buf) - 1) << > GEN7_SURFACE_HEIGHT_SHIFT); > - ss[3] = (buf->stride - 1) << GEN7_SURFACE_PITCH_SHIFT; > + ss[3] = (buf->surface[0].stride - 1) << > GEN7_SURFACE_PITCH_SHIFT; > ss[4] = 0; > if (IS_VALLEYVIEW(batch->devid)) > ss[5] = VLV_MOCS_L3 << 16; > diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c > index e22d8501..8e02d846 100644 > --- a/lib/rendercopy_gen8.c > +++ b/lib/rendercopy_gen8.c > @@ -151,7 +151,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > uint32_t write_domain, read_domain, offset; > int ret; > > - igt_assert_lte(buf->stride, 256*1024); > + igt_assert_lte(buf->surface[0].stride, 256*1024); > igt_assert_lte(igt_buf_width(buf), 16384); > igt_assert_lte(igt_buf_height(buf), 16384); > > @@ -199,7 +199,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > > ss->ss7.shader_chanel_select_r = 4; > ss->ss7.shader_chanel_select_g = 5; > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c > index 4d4541e3..835c8d80 100644 > --- a/lib/rendercopy_gen9.c > +++ b/lib/rendercopy_gen9.c > @@ -199,7 +199,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > uint32_t write_domain, read_domain, offset; > int ret; > > - igt_assert_lte(buf->stride, 256*1024); > + igt_assert_lte(buf->surface[0].stride, 256*1024); > igt_assert_lte(igt_buf_width(buf), 16384); > igt_assert_lte(igt_buf_height(buf), 16384); > > @@ -250,7 +250,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > > ss->ss7.skl.shader_chanel_select_r = 4; > ss->ss7.skl.shader_chanel_select_g = 5; > diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c > index e8c04718..ca815122 100644 > --- a/lib/rendercopy_i830.c > +++ b/lib/rendercopy_i830.c > @@ -138,7 +138,7 @@ static void gen2_emit_target(struct > intel_batchbuffer *batch, > uint32_t tiling; > uint32_t format; > > - igt_assert_lte(dst->stride, 8192); > + igt_assert_lte(dst->surface[0].stride, 8192); > igt_assert_lte(igt_buf_width(dst), 2048); > igt_assert_lte(igt_buf_height(dst), 2048); > > @@ -156,7 +156,7 @@ static void gen2_emit_target(struct > intel_batchbuffer *batch, > tiling |= BUF_3D_TILE_WALK_Y; > > OUT_BATCH(_3DSTATE_BUF_INFO_CMD); > - OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst- > >stride)); > + OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst- > >surface[0].stride)); > OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, > I915_GEM_DOMAIN_RENDER, 0); > > OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); > @@ -179,7 +179,7 @@ static void gen2_emit_texture(struct > intel_batchbuffer *batch, > uint32_t tiling; > uint32_t format; > > - igt_assert_lte(src->stride, 8192); > + igt_assert_lte(src->surface[0].stride, 8192); > igt_assert_lte(igt_buf_width(src), 2048); > igt_assert_lte(igt_buf_height(src), 2048); > > @@ -201,7 +201,7 @@ static void gen2_emit_texture(struct > intel_batchbuffer *batch, > OUT_BATCH((igt_buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT | > (igt_buf_width(src) - 1) << TM0S1_WIDTH_SHIFT | > format | tiling); > - OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | > TM0S2_MAP_2D); > + OUT_BATCH((src->surface[0].stride / 4 - 1) << TM0S2_PITCH_SHIFT > | TM0S2_MAP_2D); > OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT | > FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT | > MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT); > diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c > index 1baa7a1b..56e1863e 100644 > --- a/lib/rendercopy_i915.c > +++ b/lib/rendercopy_i915.c > @@ -88,7 +88,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer > *batch, > #define TEX_COUNT 1 > uint32_t format_bits, tiling_bits = 0; > > - igt_assert_lte(src->stride, 8192); > + igt_assert_lte(src->surface[0].stride, 8192); > igt_assert_lte(igt_buf_width(src), 2048); > igt_assert_lte(igt_buf_height(src), 2048); > > @@ -110,7 +110,7 @@ void gen3_render_copyfunc(struct > intel_batchbuffer *batch, > OUT_BATCH(format_bits | tiling_bits | > (igt_buf_height(src) - 1) << MS3_HEIGHT_SHIFT > | > (igt_buf_width(src) - 1) << MS3_WIDTH_SHIFT); > - OUT_BATCH((src->stride/4-1) << MS4_PITCH_SHIFT); > + OUT_BATCH((src->surface[0].stride/4-1) << > MS4_PITCH_SHIFT); > > OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT)); > OUT_BATCH((1 << TEX_COUNT) - 1); > @@ -128,7 +128,7 @@ void gen3_render_copyfunc(struct > intel_batchbuffer *batch, > uint32_t tiling_bits = 0; > uint32_t format_bits; > > - igt_assert_lte(dst->stride, 8192); > + igt_assert_lte(dst->surface[0].stride, 8192); > igt_assert_lte(igt_buf_width(dst), 2048); > igt_assert_lte(igt_buf_height(dst), 2048); > > @@ -146,7 +146,7 @@ void gen3_render_copyfunc(struct > intel_batchbuffer *batch, > > OUT_BATCH(_3DSTATE_BUF_INFO_CMD); > OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits | > - BUF_3D_PITCH(dst->stride)); > + BUF_3D_PITCH(dst->surface[0].stride)); > OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, > I915_GEM_DOMAIN_RENDER, 0); > > OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); > diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c > index 87800941..2f017514 100644 > --- a/lib/veboxcopy_gen12.c > +++ b/lib/veboxcopy_gen12.c > @@ -248,12 +248,14 @@ void gen12_vebox_copyfunc(struct > intel_batchbuffer *batch, > /* TODO: add support for more formats */ > igt_assert(src->bpp == 32); > emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT, > - width, height, src->bpp, src->stride, > + width, height, src->bpp, > + src->surface[0].stride, > src->tiling, R8G8B8A8_UNORM); > > igt_assert(dst->bpp == 32); > emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT, > - width, height, dst->bpp, dst->stride, > + width, height, dst->bpp, > + dst->surface[0].stride, > dst->tiling, R8G8B8A8_UNORM); > > emit_tiling_convert_cmd(batch, > diff --git a/tests/i915/gem_concurrent_all.c > b/tests/i915/gem_concurrent_all.c > index 6486bebf..f1be4a85 100644 > --- a/tests/i915/gem_concurrent_all.c > +++ b/tests/i915/gem_concurrent_all.c > @@ -851,15 +851,17 @@ static void render_copy_bo(struct buffers *b, > drm_intel_bo *dst, drm_intel_bo *s > { > struct igt_buf d = { > .bo = dst, > - .size = b->npixels * 4, > .num_tiles = b->npixels * 4, > - .stride = b->width * 4, > + .surface[0] = { > + .size = b->npixels * 4, .stride = b->width * 4, > + }, > .bpp = 32, > }, s = { > .bo = src, > - .size = b->npixels * 4, > .num_tiles = b->npixels * 4, > - .stride = b->width * 4, > + .surface[0] = { > + .size = b->npixels * 4, .stride = b->width * 4, > + }, > .bpp = 32, > }; > uint32_t swizzle; > diff --git a/tests/i915/gem_gpgpu_fill.c > b/tests/i915/gem_gpgpu_fill.c > index 68918c3e..b2d401d6 100644 > --- a/tests/i915/gem_gpgpu_fill.c > +++ b/tests/i915/gem_gpgpu_fill.c > @@ -75,9 +75,9 @@ static void scratch_buf_init(data_t *data, struct > igt_buf *buf, > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = stride; > + buf->surface[0].stride = stride; > buf->tiling = I915_TILING_NONE; > - buf->size = SIZE; > + buf->surface[0].size = SIZE; > buf->bpp = 32; > } > > diff --git a/tests/i915/gem_media_fill.c > b/tests/i915/gem_media_fill.c > index a7d7708c..c880bae9 100644 > --- a/tests/i915/gem_media_fill.c > +++ b/tests/i915/gem_media_fill.c > @@ -78,9 +78,9 @@ static void scratch_buf_init(data_t *data, struct > igt_buf *buf, > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = stride; > + buf->surface[0].stride = stride; > buf->tiling = I915_TILING_NONE; > - buf->size = SIZE; > + buf->surface[0].size = SIZE; > buf->bpp = 32; > } > > diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c > index d5045ad1..20f5ca35 100644 > --- a/tests/i915/gem_media_vme.c > +++ b/tests/i915/gem_media_vme.c > @@ -58,7 +58,7 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, > > buf->bo = bo; > buf->tiling = I915_TILING_NONE; > - buf->size = size; > + buf->surface[0].size = size; > } > > static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct > igt_buf *buf) > @@ -71,14 +71,14 @@ static void scratch_buf_init_src(drm_intel_bufmgr > *bufmgr, struct igt_buf *buf) > * with this vme kernel. > */ > > - buf->stride = STRIDE; > + buf->surface[0].stride = STRIDE; > } > > static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct > igt_buf *buf) > { > scratch_buf_init(bufmgr, buf, OUTPUT_SIZE); > > - buf->stride = 1; > + buf->surface[0].stride = 1; > } > > static uint64_t switch_off_n_bits(uint64_t mask, unsigned int n) > diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c > index 89cdc4db..4c7d3ba2 100644 > --- a/tests/i915/gem_ppgtt.c > +++ b/tests/i915/gem_ppgtt.c > @@ -73,9 +73,9 @@ static void scratch_buf_init(struct igt_buf *buf, > memset(buf, 0, sizeof(*buf)); > > buf->bo = create_bo(bufmgr, pixel); > - buf->stride = STRIDE; > + buf->surface[0].stride = STRIDE; > buf->tiling = I915_TILING_NONE; > - buf->size = SIZE; > + buf->surface[0].size = SIZE; > buf->bpp = 32; > } > > @@ -140,9 +140,9 @@ static void fork_rcs_copy(int timeout, uint32_t > final, > } > > buf.bo = dst[child]; > - buf.stride = STRIDE; > + buf.surface[0].stride = STRIDE; > buf.tiling = I915_TILING_NONE; > - buf.size = SIZE; > + buf.surface[0].size = SIZE; > buf.bpp = 32; > > i = 0; > diff --git a/tests/i915/gem_read_read_speed.c > b/tests/i915/gem_read_read_speed.c > index 8b5ba8f7..2aab2204 100644 > --- a/tests/i915/gem_read_read_speed.c > +++ b/tests/i915/gem_read_read_speed.c > @@ -53,15 +53,17 @@ static drm_intel_bo *rcs_copy_bo(drm_intel_bo > *dst, drm_intel_bo *src) > { > struct igt_buf d = { > .bo = dst, > - .size = width * height * 4, > .num_tiles = width * height * 4, > - .stride = width * 4, > + .surface[0] = { > + .size = width * height * 4, .stride = width * > 4, > + }, > .bpp = 32, > }, s = { > .bo = src, > - .size = width * height * 4, > .num_tiles = width * height * 4, > - .stride = width * 4, > + .surface[0] = { > + .size = width * height * 4, .stride = width * > 4, > + }, > .bpp = 32, > }; > uint32_t swizzle; > diff --git a/tests/i915/gem_render_copy.c > b/tests/i915/gem_render_copy.c > index df0d045e..5abb2036 100644 > --- a/tests/i915/gem_render_copy.c > +++ b/tests/i915/gem_render_copy.c > @@ -118,7 +118,8 @@ static void copy_linear_to_yf(data_t *data, > struct igt_buf *buf, > for (int y = 0; y < height; y++) { > for (int x = 0; x < width; x++) { > uint32_t *ptr = yf_ptr(map, x, y, > - buf->stride, buf->bpp / > 8); > + buf->surface[0].stride, > + buf->bpp / 8); > > *ptr = linear[y * width + x]; > } > @@ -142,7 +143,8 @@ static void copy_yf_to_linear(data_t *data, > struct igt_buf *buf, > for (int y = 0; y < height; y++) { > for (int x = 0; x < width; x++) { > uint32_t *ptr = yf_ptr(map, x, y, > - buf->stride, buf->bpp / > 8); > + buf->surface[0].stride, > + buf->bpp / 8); > > linear[y * width + x] = *ptr; > } > @@ -231,7 +233,7 @@ static void scratch_buf_write_to_png(data_t > *data, struct igt_buf *buf, > CAIRO_FORMAT_RGB2 > 4, > igt_buf_width(buf > ), > igt_buf_height(bu > f), > - buf->stride); > + buf- > >surface[0].stride); > ret = cairo_surface_write_to_png(surface, > make_filename(filename)); > igt_assert(ret == CAIRO_STATUS_SUCCESS); > cairo_surface_destroy(surface); > @@ -324,7 +326,7 @@ static void scratch_buf_draw_pattern(data_t > *data, struct igt_buf *buf, > CAIRO_FORMAT_RGB2 > 4, > igt_buf_width(buf > ), > igt_buf_height(bu > f), > - buf->stride); > + buf- > >surface[0].stride); > > cr = cairo_create(surface); > > @@ -403,7 +405,7 @@ scratch_buf_copy(data_t *data, > for (int y = 0; y < h; y++) { > for (int x = 0; x < w; x++) { > const uint32_t *ptr = yf_ptr(map, sx+x, > sy+y, > - src- > >stride, > + src- > >surface[0].stride, > src->bpp / > 8); > > linear_dst[(dy+y) * width + dx+x] = > *ptr; > @@ -458,14 +460,14 @@ static void scratch_buf_init(data_t *data, > struct igt_buf *buf, > * turn mapped by one L1 AUX page table entry. > */ > if (intel_gen(data->devid) >= 12) > - buf->stride = ALIGN(width * (bpp / 8), 128 * > 4); > + buf->surface[0].stride = ALIGN(width * (bpp / > 8), 128 * 4); > else > - buf->stride = ALIGN(width * (bpp / 8), 128); > + buf->surface[0].stride = ALIGN(width * (bpp / > 8), 128); > > if (intel_gen(data->devid) >= 12) > height = ALIGN(height, 4 * 32); > > - buf->size = buf->stride * height; > + buf->surface[0].size = buf->surface[0].stride * height; > buf->tiling = tiling; > buf->bpp = bpp; > > @@ -473,7 +475,7 @@ static void scratch_buf_init(data_t *data, struct > igt_buf *buf, > aux_height = scratch_buf_aux_height(data->devid, buf); > > buf->compression = compression; > - buf->ccs[0].offset = buf->stride * ALIGN(height, 32); > + buf->ccs[0].offset = buf->surface[0].stride * > ALIGN(height, 32); > buf->ccs[0].stride = aux_width; > > size = buf->ccs[0].offset + aux_width * aux_height; > @@ -481,18 +483,19 @@ static void scratch_buf_init(data_t *data, > struct igt_buf *buf, > buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, > 4096); > > if (tiling == I915_TILING_Y) { > - drm_intel_bo_set_tiling(buf->bo, &tiling, buf- > >stride); > + drm_intel_bo_set_tiling(buf->bo, &tiling, > + buf- > >surface[0].stride); > igt_assert_eq(tiling, req_tiling); > } > } else if (req_tiling == I915_TILING_Yf) { > int size; > > - buf->stride = ALIGN(width * (bpp / 8), 128); > - buf->size = buf->stride * height; > + buf->surface[0].stride = ALIGN(width * (bpp / 8), 128); > + buf->surface[0].size = buf->surface[0].stride * height; > buf->tiling = tiling; > buf->bpp = bpp; > > - size = buf->stride * ALIGN(height, 32); > + size = buf->surface[0].stride * ALIGN(height, 32); > > buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, > 4096); > } else { > @@ -501,9 +504,9 @@ static void scratch_buf_init(data_t *data, struct > igt_buf *buf, > &tiling, &pitch, 0); > igt_assert_eq(tiling, req_tiling); > > - buf->stride = pitch; > + buf->surface[0].stride = pitch; > buf->tiling = tiling; > - buf->size = pitch * height; > + buf->surface[0].size = pitch * height; > buf->bpp = bpp; > } > > @@ -806,7 +809,7 @@ static void test(data_t *data, uint32_t > src_tiling, uint32_t dst_tiling, > 0, 0, > igt_buf_width(&dst), > igt_buf_height(&dst), > AUB_DUMP_BMP_FORMAT_ARGB_ > 8888, > - dst.stride, 0); > + dst.surface[0].stride, > 0); > drm_intel_bufmgr_gem_set_aub_dump(data->bufmgr, false); > } else if (check_all_pixels) { > scratch_buf_check_all(data, &dst, &ref); > diff --git a/tests/i915/gem_render_copy_redux.c > b/tests/i915/gem_render_copy_redux.c > index ef601c22..2388fc24 100644 > --- a/tests/i915/gem_render_copy_redux.c > +++ b/tests/i915/gem_render_copy_redux.c > @@ -106,9 +106,9 @@ static void scratch_buf_init(data_t *data, struct > igt_buf *buf, > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = stride; > + buf->surface[0].stride = stride; > buf->tiling = I915_TILING_NONE; > - buf->size = SIZE; > + buf->surface[0].size = SIZE; > buf->bpp = 32; > } > > diff --git a/tests/i915/gem_render_linear_blits.c > b/tests/i915/gem_render_linear_blits.c > index a726652b..666a43cd 100644 > --- a/tests/i915/gem_render_linear_blits.c > +++ b/tests/i915/gem_render_linear_blits.c > @@ -108,15 +108,15 @@ static void run_test (int fd, int count) > struct igt_buf src = {}, dst = {}; > > src.bo = bo[i % count]; > - src.stride = STRIDE; > + src.surface[0].stride = STRIDE; > src.tiling = I915_TILING_NONE; > - src.size = SIZE; > + src.surface[0].size = SIZE; > src.bpp = 32; > > dst.bo = bo[(i + 1) % count]; > - dst.stride = STRIDE; > + dst.surface[0].stride = STRIDE; > dst.tiling = I915_TILING_NONE; > - dst.size = SIZE; > + dst.surface[0].size = SIZE; > dst.bpp = 32; > > render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, > &dst, 0, 0); > @@ -133,15 +133,15 @@ static void run_test (int fd, int count) > struct igt_buf src = {}, dst = {}; > > src.bo = bo[(i + 1) % count]; > - src.stride = STRIDE; > + src.surface[0].stride = STRIDE; > src.tiling = I915_TILING_NONE; > - src.size = SIZE; > + src.surface[0].size = SIZE; > src.bpp = 32; > > dst.bo = bo[i % count]; > - dst.stride = STRIDE; > + dst.surface[0].stride = STRIDE; > dst.tiling = I915_TILING_NONE; > - dst.size = SIZE; > + dst.surface[0].size = SIZE; > dst.bpp = 32; > > render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, > &dst, 0, 0); > @@ -160,15 +160,15 @@ static void run_test (int fd, int count) > continue; > > src.bo = bo[s]; > - src.stride = STRIDE; > + src.surface[0].stride = STRIDE; > src.tiling = I915_TILING_NONE; > - src.size = SIZE; > + src.surface[0].size = SIZE; > src.bpp = 32; > > dst.bo = bo[d]; > - dst.stride = STRIDE; > + dst.surface[0].stride = STRIDE; > dst.tiling = I915_TILING_NONE; > - dst.size = SIZE; > + dst.surface[0].size = SIZE; > dst.bpp = 32; > > render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, > &dst, 0, 0); > diff --git a/tests/i915/gem_render_tiled_blits.c > b/tests/i915/gem_render_tiled_blits.c > index 14018329..1de1b72c 100644 > --- a/tests/i915/gem_render_tiled_blits.c > +++ b/tests/i915/gem_render_tiled_blits.c > @@ -66,9 +66,9 @@ check_bo(struct intel_batchbuffer *batch, struct > igt_buf *buf, uint32_t val) > int i; > > tmp.bo = linear; > - tmp.stride = STRIDE; > + tmp.surface[0].stride = STRIDE; > tmp.tiling = I915_TILING_NONE; > - tmp.size = SIZE; > + tmp.surface[0].size = SIZE; > tmp.bpp = 32; > > render_copy(batch, NULL, buf, 0, 0, WIDTH, HEIGHT, &tmp, 0, 0); > @@ -132,9 +132,9 @@ static void run_test (int fd, int count) > buf[i].bo = drm_intel_bo_alloc_tiled(bufmgr, "", > WIDTH, HEIGHT, 4, > &tiling, &pitch, > 0); > - buf[i].stride = pitch; > + buf[i].surface[0].stride = pitch; > buf[i].tiling = tiling; > - buf[i].size = SIZE; > + buf[i].surface[0].size = SIZE; > buf[i].bpp = 32; > > start_val[i] = start; > diff --git a/tests/i915/gem_ring_sync_copy.c > b/tests/i915/gem_ring_sync_copy.c > index 1e5728bc..ddf5f750 100644 > --- a/tests/i915/gem_ring_sync_copy.c > +++ b/tests/i915/gem_ring_sync_copy.c > @@ -134,9 +134,9 @@ static void scratch_buf_init_from_bo(struct > igt_buf *buf, drm_intel_bo *bo) > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = 4 * WIDTH; > + buf->surface[0].stride = 4 * WIDTH; > buf->tiling = I915_TILING_NONE; > - buf->size = 4 * WIDTH * HEIGHT; > + buf->surface[0].size = 4 * WIDTH * HEIGHT; > buf->bpp = 32; > } > > diff --git a/tests/i915/gem_stress.c b/tests/i915/gem_stress.c > index 57e2909c..50245b93 100644 > --- a/tests/i915/gem_stress.c > +++ b/tests/i915/gem_stress.c > @@ -155,8 +155,8 @@ struct { > static void tile2xy(struct igt_buf *buf, unsigned tile, unsigned *x, > unsigned *y) > { > igt_assert(tile < buf->num_tiles); > - *x = (tile*options.tile_size) % (buf->stride/sizeof(uint32_t)); > - *y = ((tile*options.tile_size) / (buf- > >stride/sizeof(uint32_t))) * options.tile_size; > + *x = (tile*options.tile_size) % (buf- > >surface[0].stride/sizeof(uint32_t)); > + *y = ((tile*options.tile_size) / (buf- > >surface[0].stride/sizeof(uint32_t))) * options.tile_size; > } > > static void emit_blt(drm_intel_bo *src_bo, uint32_t src_tiling, > unsigned src_pitch, > @@ -268,8 +268,10 @@ static void cpu_copyfunc(struct igt_buf *src, > unsigned src_x, unsigned src_y, > set_to_cpu_domain(dst, 1); > } > > - cpucpy2d(src->data, src->stride/sizeof(uint32_t), src_x, src_y, > - dst->data, dst->stride/sizeof(uint32_t), dst_x, dst_y, > + cpucpy2d(src->data, src->surface[0].stride/sizeof(uint32_t), > src_x, > + src_y, > + dst->data, dst->surface[0].stride/sizeof(uint32_t), > dst_x, > + dst_y, > logical_tile_no); > } > > @@ -287,7 +289,7 @@ static void prw_copyfunc(struct igt_buf *src, > unsigned src_x, unsigned src_y, > > if (src->tiling == I915_TILING_NONE) { > for (i = 0; i < options.tile_size; i++) { > - unsigned ofs = src_x*sizeof(uint32_t) + src- > >stride*(src_y + i); > + unsigned ofs = src_x*sizeof(uint32_t) + src- > >surface[0].stride*(src_y + i); > drm_intel_bo_get_subdata(src->bo, ofs, > options.tile_size*size > of(uint32_t), > tmp_tile + > options.tile_size*i); > @@ -296,13 +298,14 @@ static void prw_copyfunc(struct igt_buf *src, > unsigned src_x, unsigned src_y, > if (options.use_cpu_maps) > set_to_cpu_domain(src, 0); > > - cpucpy2d(src->data, src->stride/sizeof(uint32_t), > src_x, src_y, > + cpucpy2d(src->data, src- > >surface[0].stride/sizeof(uint32_t), > + src_x, src_y, > tmp_tile, options.tile_size, 0, 0, > logical_tile_no); > } > > if (dst->tiling == I915_TILING_NONE) { > for (i = 0; i < options.tile_size; i++) { > - unsigned ofs = dst_x*sizeof(uint32_t) + dst- > >stride*(dst_y + i); > + unsigned ofs = dst_x*sizeof(uint32_t) + dst- > >surface[0].stride*(dst_y + i); > drm_intel_bo_subdata(dst->bo, ofs, > options.tile_size*sizeof(u > int32_t), > tmp_tile + > options.tile_size*i); > @@ -312,7 +315,8 @@ static void prw_copyfunc(struct igt_buf *src, > unsigned src_x, unsigned src_y, > set_to_cpu_domain(dst, 1); > > cpucpy2d(tmp_tile, options.tile_size, 0, 0, > - dst->data, dst->stride/sizeof(uint32_t), > dst_x, dst_y, > + dst->data, dst- > >surface[0].stride/sizeof(uint32_t), > + dst_x, dst_y, > logical_tile_no); > } > } > @@ -327,9 +331,9 @@ static void blitter_copyfunc(struct igt_buf *src, > unsigned src_x, unsigned src_y > if (keep_gpu_busy_counter & 1 && !fence_storm) > keep_gpu_busy(); > > - emit_blt(src->bo, src->tiling, src->stride, src_x, src_y, > + emit_blt(src->bo, src->tiling, src->surface[0].stride, src_x, > src_y, > options.tile_size, options.tile_size, > - dst->bo, dst->tiling, dst->stride, dst_x, dst_y); > + dst->bo, dst->tiling, dst->surface[0].stride, dst_x, > dst_y); > > if (!(keep_gpu_busy_counter & 1) && !fence_storm) > keep_gpu_busy(); > @@ -441,7 +445,7 @@ static void fan_out(void) > > cpucpy2d(tmp_tile, options.tile_size, 0, 0, > buffers[current_set][buf_idx].data, > - buffers[current_set][buf_idx].stride / > sizeof(uint32_t), > + buffers[current_set][buf_idx].surface[0].strid > e / sizeof(uint32_t), > x, y, i); > } > > @@ -465,7 +469,7 @@ static void fan_in_and_check(void) > set_to_cpu_domain(&buffers[current_set][buf_idx > ], 0); > > cpucpy2d(buffers[current_set][buf_idx].data, > - buffers[current_set][buf_idx].stride / > sizeof(uint32_t), > + buffers[current_set][buf_idx].surface[0].strid > e / sizeof(uint32_t), > x, y, > tmp_tile, options.tile_size, 0, 0, > i); > @@ -476,15 +480,15 @@ static void sanitize_stride(struct igt_buf > *buf) > { > > if (igt_buf_height(buf) > options.max_dimension) > - buf->stride = buf->size / options.max_dimension; > + buf->surface[0].stride = buf->surface[0].size / > options.max_dimension; > > if (igt_buf_height(buf) < options.tile_size) > - buf->stride = buf->size / options.tile_size; > + buf->surface[0].stride = buf->surface[0].size / > options.tile_size; > > if (igt_buf_width(buf) < options.tile_size) > - buf->stride = options.tile_size * sizeof(uint32_t); > + buf->surface[0].stride = options.tile_size * > sizeof(uint32_t); > > - igt_assert(buf->stride <= 8192); > + igt_assert(buf->surface[0].stride <= 8192); > igt_assert(igt_buf_width(buf) <= options.max_dimension); > igt_assert(igt_buf_height(buf) <= options.max_dimension); > > @@ -498,10 +502,10 @@ static void init_buffer(struct igt_buf *buf, > unsigned size) > memset(buf, 0, sizeof(*buf)); > > buf->bo = drm_intel_bo_alloc(bufmgr, "tiled bo", size, 4096); > - buf->size = size; > + buf->surface[0].size = size; > igt_assert(buf->bo); > buf->tiling = I915_TILING_NONE; > - buf->stride = 4096; > + buf->surface[0].stride = 4096; > buf->bpp = 32; > > sanitize_stride(buf); > @@ -560,25 +564,26 @@ static void init_set(unsigned set) > if (buffers[set][i].tiling == I915_TILING_NONE) { > /* min 64 byte stride */ > r %= 8; > - buffers[set][i].stride = 64 * (1 << r); > + buffers[set][i].surface[0].stride = 64 * (1 << > r); > } else if (IS_GEN2(devid)) { > /* min 128 byte stride */ > r %= 7; > - buffers[set][i].stride = 128 * (1 << r); > + buffers[set][i].surface[0].stride = 128 * (1 << > r); > } else { > /* min 512 byte stride */ > r %= 5; > - buffers[set][i].stride = 512 * (1 << r); > + buffers[set][i].surface[0].stride = 512 * (1 << > r); > } > > sanitize_stride(&buffers[set][i]); > > gem_set_tiling(drm_fd, buffers[set][i].bo->handle, > buffers[set][i].tiling, > - buffers[set][i].stride); > + buffers[set][i].surface[0].stride); > > if (options.trace_tile != -1 && i == > options.trace_tile/options.tiles_per_buf) > - igt_info("changing buffer %i containing tile > %i: tiling %i, stride %i\n", i, options.trace_tile, > buffers[set][i].tiling, buffers[set][i].stride); > + igt_info("changing buffer %i containing tile > %i: tiling %i, stride %i\n", i, options.trace_tile, > buffers[set][i].tiling, > + buffers[set][i].surface[0].stride); > } > } > > @@ -616,10 +621,10 @@ static void copy_tiles(unsigned *permutation) > > if (options.no_hw) { > cpucpy2d(src_buf->data, > - src_buf->stride / sizeof(uint32_t), > + src_buf->surface[0].stride / > sizeof(uint32_t), > src_x, src_y, > dst_buf->data, > - dst_buf->stride / sizeof(uint32_t), > + dst_buf->surface[0].stride / > sizeof(uint32_t), > dst_x, dst_y, > i); > } else { > @@ -808,7 +813,7 @@ static void check_render_copyfunc(void) > > memset(src.data, 0xff, options.scratch_buf_size); > for (j = 0; j < options.tile_size; j++) { > - ptr = (uint32_t*)((char *)src.data + sx*4 + > (sy+j) * src.stride); > + ptr = (uint32_t*)((char *)src.data + sx*4 + > (sy+j) * src.surface[0].stride); > for (i = 0; i < options.tile_size; i++) > ptr[i] = j * options.tile_size + i; > } > @@ -819,7 +824,7 @@ static void check_render_copyfunc(void) > set_to_cpu_domain(&dst, 0); > > for (j = 0; j < options.tile_size; j++) { > - ptr = (uint32_t*)((char *)dst.data + dx*4 + > (dy+j) * dst.stride); > + ptr = (uint32_t*)((char *)dst.data + dx*4 + > (dy+j) * dst.surface[0].stride); > for (i = 0; i < options.tile_size; i++) > if (ptr[i] != j * options.tile_size + > i) { > igt_info("render copyfunc > mismatch at (%d, %d): found %d, expected %d\n", i, j, ptr[i], j * > options.tile_size + i); > diff --git a/tests/i915/i915_pm_sseu.c b/tests/i915/i915_pm_sseu.c > index e671e190..c2dee118 100644 > --- a/tests/i915/i915_pm_sseu.c > +++ b/tests/i915/i915_pm_sseu.c > @@ -299,10 +299,11 @@ gem_init(void) > igt_assert(gem.batch); > gem.init = 3; > > - gem.buf.stride = sizeof(uint32_t); > + gem.buf.surface[0].stride = sizeof(uint32_t); > gem.buf.tiling = I915_TILING_NONE; > - gem.buf.size = gem.buf.stride; > - gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", gem.buf.size, > 4096); > + gem.buf.surface[0].size = gem.buf.surface[0].stride; > + gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", > + gem.buf.surface[0].size, 4096); > gem.buf.bpp = 32; > igt_assert(gem.buf.bo); > gem.init = 4; > diff --git a/tests/kms_big_fb.c b/tests/kms_big_fb.c > index c5d002ca..eb144da9 100644 > --- a/tests/kms_big_fb.c > +++ b/tests/kms_big_fb.c > @@ -60,9 +60,9 @@ static void init_buf(data_t *data, > buf->bo = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, > name, fb->gem_handle); > buf->tiling = igt_fb_mod_to_tiling(fb->modifier); > - buf->stride = fb->strides[0]; > + buf->surface[0].stride = fb->strides[0]; > buf->bpp = fb->plane_bpp[0]; > - buf->size = fb->size; > + buf->surface[0].size = fb->size; > } > > static void fini_buf(struct igt_buf *buf) > @@ -99,8 +99,10 @@ static void copy_pattern(data_t *data, > h = min(h, src_fb->height - sy); > h = min(h, dst_fb->height - dy); > > - intel_blt_copy(data->batch, src.bo, sx, sy, src.stride, > - dst.bo, dx, dy, dst.stride, w, h, > dst.bpp); > + intel_blt_copy(data->batch, src.bo, sx, sy, > + src.surface[0].stride, > + dst.bo, dx, dy, dst.surface[0].stride, > w, h, > + dst.bpp); > } > > fini_buf(&dst); > diff --git a/tests/kms_psr.c b/tests/kms_psr.c > index 232c80aa..d9be87d9 100644 > --- a/tests/kms_psr.c > +++ b/tests/kms_psr.c > @@ -153,9 +153,9 @@ static void scratch_buf_init(struct igt_buf *buf, > drm_intel_bo *bo, > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = stride; > + buf->surface[0].stride = stride; > buf->tiling = I915_TILING_X; > - buf->size = size; > + buf->surface[0].size = size; > buf->bpp = 32; > } > > diff --git a/tests/perf.c b/tests/perf.c > index f5dd6051..982277df 100644 > --- a/tests/perf.c > +++ b/tests/perf.c > @@ -506,9 +506,9 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = stride; > + buf->surface[0].stride = stride; > buf->tiling = I915_TILING_NONE; > - buf->size = size; > + buf->surface[0].size = size; > buf->bpp = 32; > } > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 03/10] lib/igt_buf: Extend igt_buf to include two color surfaces 2019-12-30 12:06 ` Kahola, Mika @ 2019-12-30 12:58 ` Imre Deak 0 siblings, 0 replies; 33+ messages in thread From: Imre Deak @ 2019-12-30 12:58 UTC (permalink / raw) To: Kahola, Mika; +Cc: igt-dev@lists.freedesktop.org On Mon, Dec 30, 2019 at 02:06:51PM +0200, Kahola, Mika wrote: > On Mon, 2019-12-30 at 05:40 +0200, Imre Deak wrote: > > UV FBs have two color surfaces so extend the igt_buf struct > > accordingly > > to support blitting such FBs. > > > > The patch is produced with the coccinelle patch below. > > > > No functional changes. > > When applying this patch, the compiler started to nag about Yes, that's due to patch applied recently, this change needs a rebase on that one. I'll resend this with the following change: +@@ tests/kms_cursor_crc.c: static void cleanup_crtc(data_t *data) + static void scratch_buf_init(data_t *data, int buffer) + { + data->igtbo[buffer].bo = data->drmibo[buffer]; +- data->igtbo[buffer].stride = data->primary_fb[buffer].strides[0]; ++ data->igtbo[buffer].surface[0].stride = data->primary_fb[buffer].strides[0]; + data->igtbo[buffer].tiling = data->primary_fb[buffer].modifier; +- data->igtbo[buffer].size = data->primary_fb[buffer].size; ++ data->igtbo[buffer].surface[0].size = data->primary_fb[buffer].size; + data->igtbo[buffer].bpp = data->primary_fb[buffer].plane_bpp[0]; > > [75/672] Compiling C object 'tests/59830eb@@kms_cursor_crc@exe/kms_curs > or_crc.c.o'. > FAILED: tests/59830eb@@kms_cursor_crc@exe/kms_cursor_crc.c.o > ccache cc -Itests/59830eb@@kms_cursor_crc@exe -Itests -I../tests > -I../include/drm-uapi -Ilib -I../lib -I../lib/stubs/syscalls -I. -I../ > -I/usr/include/cairo -I/usr/include/glib-2.0 -I/usr/lib/x86_64-linux- > gnu/glib-2.0/include -I/usr/include/pixman-1 -I/usr/include/freetype2 > -I/usr/include/libpng16 -I/usr/include/libdrm -I/usr/include/x86_64- > linux-gnu -I/usr/include/alsa -I/usr/include/libdrm/nouveau > -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -Wall > -Winvalid-pch -Wextra -std=gnu11 -O2 -g -D_GNU_SOURCE -include config.h > -D_FORTIFY_SOURCE=2 -Wbad-function-cast -Wdeclaration-after-statement > -Wformat=2 -Wimplicit-fallthrough=0 -Wlogical-op -Wmissing-declarations > -Wmissing-format-attribute -Wmissing-noreturn -Wmissing-prototypes > -Wnested-externs -Wold-style-definition -Wpointer-arith -Wredundant- > decls -Wshadow -Wstrict-prototypes -Wuninitialized -Wunused -Wno- > clobbered -Wno-maybe-uninitialized -Wno-missing-field-initializers > -Wno-pointer-arith -Wno-sign-compare -Wno-type-limits -Wno-unused- > parameter -Wno-unused-result -Werror=address -Werror=array-bounds > -Werror=implicit -Werror=init-self -Werror=int-to-pointer-cast > -Werror=main -Werror=missing-braces -Werror=nonnull -Werror=pointer-to- > int-cast -Werror=return-type -Werror=sequence-point -Werror=trigraphs > -Werror=write-strings -fno-builtin-malloc -fno-builtin-calloc > -pthread -MD -MQ 'tests/59830eb@@kms_cursor_crc@exe/kms_cursor_crc.c.o > ' -MF 'tests/59830eb@@kms_cursor_crc@exe/kms_cursor_crc.c.o.d' -o > 'tests/59830eb@@kms_cursor_crc@exe/kms_cursor_crc.c.o' -c > ../tests/kms_cursor_crc.c > ../tests/kms_cursor_crc.c: In function ‘scratch_buf_init’: > ../tests/kms_cursor_crc.c:388:21: error: ‘struct igt_buf’ has no member > named ‘stride’ > data->igtbo[buffer].stride = data->primary_fb[buffer].strides[0]; > ^ > ../tests/kms_cursor_crc.c:390:21: error: ‘struct igt_buf’ has no member > named ‘size’ > data->igtbo[buffer].size = data->primary_fb[buffer].size; > ^ > [84/672] Compiling C object 'tests/59830eb@@kms_cursor_legacy@exe/kms_c > ursor_legacy.c.o'. > ninja: build stopped: subcommand failed. > > > > > @@ > > @@ > > > > struct igt_buf { > > ... > > - uint32_t stride; > > ... > > - uint32_t size; > > + struct { > > + uint32_t stride; > > + uint32_t size; > > + } surface[2]; > > ... > > }; > > > > @@ > > struct igt_buf b; > > @@ > > > > <... > > ( > > - b.stride > > + b.surface[0].stride > > > > > > > - b.size > > + b.surface[0].size > > ) > > ...> > > > > @@ > > struct igt_buf *b; > > @@ > > > > <... > > ( > > - b->size > > + b->surface[0].size > > > > > > > - b->stride > > + b->surface[0].stride > > ) > > ...> > > > > @@ > > identifier I; > > expression E1; > > expression E2; > > @@ > > > > ( > > struct igt_buf I = { > > - .size = E1, > > - .stride = E2, > > + .surface[0] = { > > + .size = E1, > > + .stride = E2, > > + }, > > }; > > > > > > > struct igt_buf I = { > > - .size = E1, > > + .surface[0] = { > > + .size = E1, > > + }, > > }; > > > > > > > struct igt_buf I = { > > - .stride = E1, > > + .surface[0] = { > > + .stride = E1, > > + }, > > }; > > ) > > > > Cc: Mika Kahola <mika.kahola@intel.com> > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > lib/gpu_cmds.c | 4 +- > > lib/igt_draw.c | 8 ++-- > > lib/igt_fb.c | 4 +- > > lib/intel_aux_pgtable.c | 5 ++- > > lib/intel_batchbuffer.c | 8 ++-- > > lib/intel_batchbuffer.h | 6 ++- > > lib/rendercopy_gen4.c | 4 +- > > lib/rendercopy_gen6.c | 4 +- > > lib/rendercopy_gen7.c | 4 +- > > lib/rendercopy_gen8.c | 4 +- > > lib/rendercopy_gen9.c | 4 +- > > lib/rendercopy_i830.c | 8 ++-- > > lib/rendercopy_i915.c | 8 ++-- > > lib/veboxcopy_gen12.c | 6 ++- > > tests/i915/gem_concurrent_all.c | 10 +++-- > > tests/i915/gem_gpgpu_fill.c | 4 +- > > tests/i915/gem_media_fill.c | 4 +- > > tests/i915/gem_media_vme.c | 6 +-- > > tests/i915/gem_ppgtt.c | 8 ++-- > > tests/i915/gem_read_read_speed.c | 10 +++-- > > tests/i915/gem_render_copy.c | 35 +++++++++-------- > > tests/i915/gem_render_copy_redux.c | 4 +- > > tests/i915/gem_render_linear_blits.c | 24 +++++------ > > tests/i915/gem_render_tiled_blits.c | 8 ++-- > > tests/i915/gem_ring_sync_copy.c | 4 +- > > tests/i915/gem_stress.c | 59 +++++++++++++++----------- > > -- > > tests/i915/i915_pm_sseu.c | 7 ++-- > > tests/kms_big_fb.c | 10 +++-- > > tests/kms_psr.c | 4 +- > > tests/perf.c | 4 +- > > 30 files changed, 149 insertions(+), 129 deletions(-) > > > > diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c > > index 8d270ee8..79412725 100644 > > --- a/lib/gpu_cmds.c > > +++ b/lib/gpu_cmds.c > > @@ -119,7 +119,7 @@ gen7_fill_surface_state(struct intel_batchbuffer > > *batch, > > ss->ss2.height = igt_buf_height(buf) - 1; > > ss->ss2.width = igt_buf_width(buf) - 1; > > > > - ss->ss3.pitch = buf->stride - 1; > > + ss->ss3.pitch = buf->surface[0].stride - 1; > > > > ss->ss7.shader_chanel_select_r = 4; > > ss->ss7.shader_chanel_select_g = 5; > > @@ -422,7 +422,7 @@ gen8_fill_surface_state(struct intel_batchbuffer > > *batch, > > > > ss->ss2.height = igt_buf_height(buf) - 1; > > ss->ss2.width = igt_buf_width(buf) - 1; > > - ss->ss3.pitch = buf->stride - 1; > > + ss->ss3.pitch = buf->surface[0].stride - 1; > > > > ss->ss7.shader_chanel_select_r = 4; > > ss->ss7.shader_chanel_select_g = 5; > > diff --git a/lib/igt_draw.c b/lib/igt_draw.c > > index 7e0edec1..6950bc49 100644 > > --- a/lib/igt_draw.c > > +++ b/lib/igt_draw.c > > @@ -603,14 +603,14 @@ static void draw_rect_render(int fd, struct > > cmd_data *cmd_data, > > igt_assert(dst); > > > > src_buf.bo = src; > > - src_buf.stride = tmp.stride; > > + src_buf.surface[0].stride = tmp.stride; > > src_buf.tiling = I915_TILING_NONE; > > - src_buf.size = tmp.size; > > + src_buf.surface[0].size = tmp.size; > > src_buf.bpp = tmp.bpp; > > dst_buf.bo = dst; > > - dst_buf.stride = buf->stride; > > + dst_buf.surface[0].stride = buf->stride; > > dst_buf.tiling = tiling; > > - dst_buf.size = buf->size; > > + dst_buf.surface[0].size = buf->size; > > dst_buf.bpp = buf->bpp; > > > > batch = intel_batchbuffer_alloc(cmd_data->bufmgr, devid); > > diff --git a/lib/igt_fb.c b/lib/igt_fb.c > > index 0e1b8493..cc0fb373 100644 > > --- a/lib/igt_fb.c > > +++ b/lib/igt_fb.c > > @@ -1977,9 +1977,9 @@ static void init_buf(struct fb_blit_upload > > *blit, > > buf->bo = gem_handle_to_libdrm_bo(blit->bufmgr, blit->fd, > > name, fb->gem_handle); > > buf->tiling = igt_fb_mod_to_tiling(fb->modifier); > > - buf->stride = fb->strides[0]; > > + buf->surface[0].stride = fb->strides[0]; > > buf->bpp = fb->plane_bpp[0]; > > - buf->size = fb->size; > > + buf->surface[0].size = fb->size; > > > > if (is_ccs_modifier(fb->modifier)) { > > igt_assert_eq(fb->strides[0] & 127, 0); > > diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c > > index dab83a9a..5addb2e2 100644 > > --- a/lib/intel_aux_pgtable.c > > +++ b/lib/intel_aux_pgtable.c > > @@ -77,7 +77,8 @@ pgt_table_count(int address_bits, const struct > > igt_buf **bufs, int buf_count) > > /* Avoid double counting for overlapping aligned bufs. > > */ > > start = max(start, end); > > > > - end = ALIGN(buf->bo->offset64 + buf->size, 1UL << > > address_bits); > > + end = ALIGN(buf->bo->offset64 + buf->surface[0].size, > > + 1UL << address_bits); > > igt_assert(end >= start); > > > > count += (end - start) >> address_bits; > > @@ -255,7 +256,7 @@ pgt_populate_entries_for_buf(struct pgtable *pgt, > > uint64_t top_table) > > { > > uint64_t surface_addr = buf->bo->offset64; > > - uint64_t surface_end = surface_addr + buf->size; > > + uint64_t surface_end = surface_addr + buf->surface[0].size; > > uint64_t aux_addr = buf->bo->offset64 + buf->ccs[0].offset; > > uint64_t l1_flags = pgt_get_l1_flags(buf); > > uint64_t lx_flags = pgt_get_lx_flags(); > > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c > > index 51aae4dc..3dc89024 100644 > > --- a/lib/intel_batchbuffer.c > > +++ b/lib/intel_batchbuffer.c > > @@ -512,7 +512,7 @@ intel_copy_bo(struct intel_batchbuffer *batch, > > */ > > unsigned igt_buf_width(const struct igt_buf *buf) > > { > > - return buf->stride/(buf->bpp / 8); > > + return buf->surface[0].stride/(buf->bpp / 8); > > } > > > > /** > > @@ -526,7 +526,7 @@ unsigned igt_buf_width(const struct igt_buf *buf) > > */ > > unsigned igt_buf_height(const struct igt_buf *buf) > > { > > - return buf->size/buf->stride; > > + return buf->surface[0].size/buf->surface[0].stride; > > } > > > > /* > > @@ -785,8 +785,8 @@ void igt_blitter_fast_copy(struct > > intel_batchbuffer *batch, > > > > igt_assert(src->bpp == dst->bpp); > > > > - src_pitch = fast_copy_pitch(src->stride, src->tiling); > > - dst_pitch = fast_copy_pitch(dst->stride, src->tiling); > > + src_pitch = fast_copy_pitch(src->surface[0].stride, src- > > >tiling); > > + dst_pitch = fast_copy_pitch(dst->surface[0].stride, src- > > >tiling); > > dword0 = fast_copy_dword0(src->tiling, dst->tiling); > > dword1 = fast_copy_dword1(src->tiling, dst->tiling, dst->bpp); > > > > diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h > > index 63d32188..69580839 100644 > > --- a/lib/intel_batchbuffer.h > > +++ b/lib/intel_batchbuffer.h > > @@ -232,12 +232,14 @@ enum i915_compression { > > */ > > struct igt_buf { > > drm_intel_bo *bo; > > - uint32_t stride; > > uint32_t tiling; > > enum i915_compression compression; > > uint32_t bpp; > > uint32_t *data; > > - uint32_t size; > > + struct { > > + uint32_t stride; > > + uint32_t size; > > + } surface[2]; > > struct { > > uint32_t offset; > > uint32_t stride; > > diff --git a/lib/rendercopy_gen4.c b/lib/rendercopy_gen4.c > > index 42de77f9..d07b8e48 100644 > > --- a/lib/rendercopy_gen4.c > > +++ b/lib/rendercopy_gen4.c > > @@ -142,7 +142,7 @@ gen4_bind_buf(struct intel_batchbuffer *batch, > > uint32_t write_domain, read_domain; > > int ret; > > > > - igt_assert_lte(buf->stride, 128*1024); > > + igt_assert_lte(buf->surface[0].stride, 128*1024); > > igt_assert_lte(igt_buf_width(buf), 8192); > > igt_assert_lte(igt_buf_height(buf), 8192); > > > > @@ -176,7 +176,7 @@ gen4_bind_buf(struct intel_batchbuffer *batch, > > > > ss->ss2.height = igt_buf_height(buf) - 1; > > ss->ss2.width = igt_buf_width(buf) - 1; > > - ss->ss3.pitch = buf->stride - 1; > > + ss->ss3.pitch = buf->surface[0].stride - 1; > > ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; > > ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; > > > > diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c > > index 83c7d694..87034774 100644 > > --- a/lib/rendercopy_gen6.c > > +++ b/lib/rendercopy_gen6.c > > @@ -79,7 +79,7 @@ gen6_bind_buf(struct intel_batchbuffer *batch, > > const struct igt_buf *buf, > > uint32_t write_domain, read_domain; > > int ret; > > > > - igt_assert_lte(buf->stride, 128*1024); > > + igt_assert_lte(buf->surface[0].stride, 128*1024); > > igt_assert_lte(igt_buf_width(buf), 8192); > > igt_assert_lte(igt_buf_height(buf), 8192); > > > > @@ -113,7 +113,7 @@ gen6_bind_buf(struct intel_batchbuffer *batch, > > const struct igt_buf *buf, > > > > ss->ss2.height = igt_buf_height(buf) - 1; > > ss->ss2.width = igt_buf_width(buf) - 1; > > - ss->ss3.pitch = buf->stride - 1; > > + ss->ss3.pitch = buf->surface[0].stride - 1; > > ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; > > ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; > > > > diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c > > index a3c8b7f3..b88b75e9 100644 > > --- a/lib/rendercopy_gen7.c > > +++ b/lib/rendercopy_gen7.c > > @@ -65,7 +65,7 @@ gen7_bind_buf(struct intel_batchbuffer *batch, > > uint32_t write_domain, read_domain; > > int ret; > > > > - igt_assert_lte(buf->stride, 256*1024); > > + igt_assert_lte(buf->surface[0].stride, 256*1024); > > igt_assert_lte(igt_buf_width(buf), 16384); > > igt_assert_lte(igt_buf_height(buf), 16384); > > > > @@ -92,7 +92,7 @@ gen7_bind_buf(struct intel_batchbuffer *batch, > > ss[1] = buf->bo->offset; > > ss[2] = ((igt_buf_width(buf) - 1) << GEN7_SURFACE_WIDTH_SHIFT > > | > > (igt_buf_height(buf) - 1) << > > GEN7_SURFACE_HEIGHT_SHIFT); > > - ss[3] = (buf->stride - 1) << GEN7_SURFACE_PITCH_SHIFT; > > + ss[3] = (buf->surface[0].stride - 1) << > > GEN7_SURFACE_PITCH_SHIFT; > > ss[4] = 0; > > if (IS_VALLEYVIEW(batch->devid)) > > ss[5] = VLV_MOCS_L3 << 16; > > diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c > > index e22d8501..8e02d846 100644 > > --- a/lib/rendercopy_gen8.c > > +++ b/lib/rendercopy_gen8.c > > @@ -151,7 +151,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > > uint32_t write_domain, read_domain, offset; > > int ret; > > > > - igt_assert_lte(buf->stride, 256*1024); > > + igt_assert_lte(buf->surface[0].stride, 256*1024); > > igt_assert_lte(igt_buf_width(buf), 16384); > > igt_assert_lte(igt_buf_height(buf), 16384); > > > > @@ -199,7 +199,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > > > > ss->ss2.height = igt_buf_height(buf) - 1; > > ss->ss2.width = igt_buf_width(buf) - 1; > > - ss->ss3.pitch = buf->stride - 1; > > + ss->ss3.pitch = buf->surface[0].stride - 1; > > > > ss->ss7.shader_chanel_select_r = 4; > > ss->ss7.shader_chanel_select_g = 5; > > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c > > index 4d4541e3..835c8d80 100644 > > --- a/lib/rendercopy_gen9.c > > +++ b/lib/rendercopy_gen9.c > > @@ -199,7 +199,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > > const struct igt_buf *buf, > > uint32_t write_domain, read_domain, offset; > > int ret; > > > > - igt_assert_lte(buf->stride, 256*1024); > > + igt_assert_lte(buf->surface[0].stride, 256*1024); > > igt_assert_lte(igt_buf_width(buf), 16384); > > igt_assert_lte(igt_buf_height(buf), 16384); > > > > @@ -250,7 +250,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > > const struct igt_buf *buf, > > > > ss->ss2.height = igt_buf_height(buf) - 1; > > ss->ss2.width = igt_buf_width(buf) - 1; > > - ss->ss3.pitch = buf->stride - 1; > > + ss->ss3.pitch = buf->surface[0].stride - 1; > > > > ss->ss7.skl.shader_chanel_select_r = 4; > > ss->ss7.skl.shader_chanel_select_g = 5; > > diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c > > index e8c04718..ca815122 100644 > > --- a/lib/rendercopy_i830.c > > +++ b/lib/rendercopy_i830.c > > @@ -138,7 +138,7 @@ static void gen2_emit_target(struct > > intel_batchbuffer *batch, > > uint32_t tiling; > > uint32_t format; > > > > - igt_assert_lte(dst->stride, 8192); > > + igt_assert_lte(dst->surface[0].stride, 8192); > > igt_assert_lte(igt_buf_width(dst), 2048); > > igt_assert_lte(igt_buf_height(dst), 2048); > > > > @@ -156,7 +156,7 @@ static void gen2_emit_target(struct > > intel_batchbuffer *batch, > > tiling |= BUF_3D_TILE_WALK_Y; > > > > OUT_BATCH(_3DSTATE_BUF_INFO_CMD); > > - OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst- > > >stride)); > > + OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst- > > >surface[0].stride)); > > OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, > > I915_GEM_DOMAIN_RENDER, 0); > > > > OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); > > @@ -179,7 +179,7 @@ static void gen2_emit_texture(struct > > intel_batchbuffer *batch, > > uint32_t tiling; > > uint32_t format; > > > > - igt_assert_lte(src->stride, 8192); > > + igt_assert_lte(src->surface[0].stride, 8192); > > igt_assert_lte(igt_buf_width(src), 2048); > > igt_assert_lte(igt_buf_height(src), 2048); > > > > @@ -201,7 +201,7 @@ static void gen2_emit_texture(struct > > intel_batchbuffer *batch, > > OUT_BATCH((igt_buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT | > > (igt_buf_width(src) - 1) << TM0S1_WIDTH_SHIFT | > > format | tiling); > > - OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | > > TM0S2_MAP_2D); > > + OUT_BATCH((src->surface[0].stride / 4 - 1) << TM0S2_PITCH_SHIFT > > | TM0S2_MAP_2D); > > OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT | > > FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT | > > MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT); > > diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c > > index 1baa7a1b..56e1863e 100644 > > --- a/lib/rendercopy_i915.c > > +++ b/lib/rendercopy_i915.c > > @@ -88,7 +88,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer > > *batch, > > #define TEX_COUNT 1 > > uint32_t format_bits, tiling_bits = 0; > > > > - igt_assert_lte(src->stride, 8192); > > + igt_assert_lte(src->surface[0].stride, 8192); > > igt_assert_lte(igt_buf_width(src), 2048); > > igt_assert_lte(igt_buf_height(src), 2048); > > > > @@ -110,7 +110,7 @@ void gen3_render_copyfunc(struct > > intel_batchbuffer *batch, > > OUT_BATCH(format_bits | tiling_bits | > > (igt_buf_height(src) - 1) << MS3_HEIGHT_SHIFT > > | > > (igt_buf_width(src) - 1) << MS3_WIDTH_SHIFT); > > - OUT_BATCH((src->stride/4-1) << MS4_PITCH_SHIFT); > > + OUT_BATCH((src->surface[0].stride/4-1) << > > MS4_PITCH_SHIFT); > > > > OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT)); > > OUT_BATCH((1 << TEX_COUNT) - 1); > > @@ -128,7 +128,7 @@ void gen3_render_copyfunc(struct > > intel_batchbuffer *batch, > > uint32_t tiling_bits = 0; > > uint32_t format_bits; > > > > - igt_assert_lte(dst->stride, 8192); > > + igt_assert_lte(dst->surface[0].stride, 8192); > > igt_assert_lte(igt_buf_width(dst), 2048); > > igt_assert_lte(igt_buf_height(dst), 2048); > > > > @@ -146,7 +146,7 @@ void gen3_render_copyfunc(struct > > intel_batchbuffer *batch, > > > > OUT_BATCH(_3DSTATE_BUF_INFO_CMD); > > OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits | > > - BUF_3D_PITCH(dst->stride)); > > + BUF_3D_PITCH(dst->surface[0].stride)); > > OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, > > I915_GEM_DOMAIN_RENDER, 0); > > > > OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); > > diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c > > index 87800941..2f017514 100644 > > --- a/lib/veboxcopy_gen12.c > > +++ b/lib/veboxcopy_gen12.c > > @@ -248,12 +248,14 @@ void gen12_vebox_copyfunc(struct > > intel_batchbuffer *batch, > > /* TODO: add support for more formats */ > > igt_assert(src->bpp == 32); > > emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT, > > - width, height, src->bpp, src->stride, > > + width, height, src->bpp, > > + src->surface[0].stride, > > src->tiling, R8G8B8A8_UNORM); > > > > igt_assert(dst->bpp == 32); > > emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT, > > - width, height, dst->bpp, dst->stride, > > + width, height, dst->bpp, > > + dst->surface[0].stride, > > dst->tiling, R8G8B8A8_UNORM); > > > > emit_tiling_convert_cmd(batch, > > diff --git a/tests/i915/gem_concurrent_all.c > > b/tests/i915/gem_concurrent_all.c > > index 6486bebf..f1be4a85 100644 > > --- a/tests/i915/gem_concurrent_all.c > > +++ b/tests/i915/gem_concurrent_all.c > > @@ -851,15 +851,17 @@ static void render_copy_bo(struct buffers *b, > > drm_intel_bo *dst, drm_intel_bo *s > > { > > struct igt_buf d = { > > .bo = dst, > > - .size = b->npixels * 4, > > .num_tiles = b->npixels * 4, > > - .stride = b->width * 4, > > + .surface[0] = { > > + .size = b->npixels * 4, .stride = b->width * 4, > > + }, > > .bpp = 32, > > }, s = { > > .bo = src, > > - .size = b->npixels * 4, > > .num_tiles = b->npixels * 4, > > - .stride = b->width * 4, > > + .surface[0] = { > > + .size = b->npixels * 4, .stride = b->width * 4, > > + }, > > .bpp = 32, > > }; > > uint32_t swizzle; > > diff --git a/tests/i915/gem_gpgpu_fill.c > > b/tests/i915/gem_gpgpu_fill.c > > index 68918c3e..b2d401d6 100644 > > --- a/tests/i915/gem_gpgpu_fill.c > > +++ b/tests/i915/gem_gpgpu_fill.c > > @@ -75,9 +75,9 @@ static void scratch_buf_init(data_t *data, struct > > igt_buf *buf, > > memset(buf, 0, sizeof(*buf)); > > > > buf->bo = bo; > > - buf->stride = stride; > > + buf->surface[0].stride = stride; > > buf->tiling = I915_TILING_NONE; > > - buf->size = SIZE; > > + buf->surface[0].size = SIZE; > > buf->bpp = 32; > > } > > > > diff --git a/tests/i915/gem_media_fill.c > > b/tests/i915/gem_media_fill.c > > index a7d7708c..c880bae9 100644 > > --- a/tests/i915/gem_media_fill.c > > +++ b/tests/i915/gem_media_fill.c > > @@ -78,9 +78,9 @@ static void scratch_buf_init(data_t *data, struct > > igt_buf *buf, > > memset(buf, 0, sizeof(*buf)); > > > > buf->bo = bo; > > - buf->stride = stride; > > + buf->surface[0].stride = stride; > > buf->tiling = I915_TILING_NONE; > > - buf->size = SIZE; > > + buf->surface[0].size = SIZE; > > buf->bpp = 32; > > } > > > > diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c > > index d5045ad1..20f5ca35 100644 > > --- a/tests/i915/gem_media_vme.c > > +++ b/tests/i915/gem_media_vme.c > > @@ -58,7 +58,7 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, > > > > buf->bo = bo; > > buf->tiling = I915_TILING_NONE; > > - buf->size = size; > > + buf->surface[0].size = size; > > } > > > > static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct > > igt_buf *buf) > > @@ -71,14 +71,14 @@ static void scratch_buf_init_src(drm_intel_bufmgr > > *bufmgr, struct igt_buf *buf) > > * with this vme kernel. > > */ > > > > - buf->stride = STRIDE; > > + buf->surface[0].stride = STRIDE; > > } > > > > static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct > > igt_buf *buf) > > { > > scratch_buf_init(bufmgr, buf, OUTPUT_SIZE); > > > > - buf->stride = 1; > > + buf->surface[0].stride = 1; > > } > > > > static uint64_t switch_off_n_bits(uint64_t mask, unsigned int n) > > diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c > > index 89cdc4db..4c7d3ba2 100644 > > --- a/tests/i915/gem_ppgtt.c > > +++ b/tests/i915/gem_ppgtt.c > > @@ -73,9 +73,9 @@ static void scratch_buf_init(struct igt_buf *buf, > > memset(buf, 0, sizeof(*buf)); > > > > buf->bo = create_bo(bufmgr, pixel); > > - buf->stride = STRIDE; > > + buf->surface[0].stride = STRIDE; > > buf->tiling = I915_TILING_NONE; > > - buf->size = SIZE; > > + buf->surface[0].size = SIZE; > > buf->bpp = 32; > > } > > > > @@ -140,9 +140,9 @@ static void fork_rcs_copy(int timeout, uint32_t > > final, > > } > > > > buf.bo = dst[child]; > > - buf.stride = STRIDE; > > + buf.surface[0].stride = STRIDE; > > buf.tiling = I915_TILING_NONE; > > - buf.size = SIZE; > > + buf.surface[0].size = SIZE; > > buf.bpp = 32; > > > > i = 0; > > diff --git a/tests/i915/gem_read_read_speed.c > > b/tests/i915/gem_read_read_speed.c > > index 8b5ba8f7..2aab2204 100644 > > --- a/tests/i915/gem_read_read_speed.c > > +++ b/tests/i915/gem_read_read_speed.c > > @@ -53,15 +53,17 @@ static drm_intel_bo *rcs_copy_bo(drm_intel_bo > > *dst, drm_intel_bo *src) > > { > > struct igt_buf d = { > > .bo = dst, > > - .size = width * height * 4, > > .num_tiles = width * height * 4, > > - .stride = width * 4, > > + .surface[0] = { > > + .size = width * height * 4, .stride = width * > > 4, > > + }, > > .bpp = 32, > > }, s = { > > .bo = src, > > - .size = width * height * 4, > > .num_tiles = width * height * 4, > > - .stride = width * 4, > > + .surface[0] = { > > + .size = width * height * 4, .stride = width * > > 4, > > + }, > > .bpp = 32, > > }; > > uint32_t swizzle; > > diff --git a/tests/i915/gem_render_copy.c > > b/tests/i915/gem_render_copy.c > > index df0d045e..5abb2036 100644 > > --- a/tests/i915/gem_render_copy.c > > +++ b/tests/i915/gem_render_copy.c > > @@ -118,7 +118,8 @@ static void copy_linear_to_yf(data_t *data, > > struct igt_buf *buf, > > for (int y = 0; y < height; y++) { > > for (int x = 0; x < width; x++) { > > uint32_t *ptr = yf_ptr(map, x, y, > > - buf->stride, buf->bpp / > > 8); > > + buf->surface[0].stride, > > + buf->bpp / 8); > > > > *ptr = linear[y * width + x]; > > } > > @@ -142,7 +143,8 @@ static void copy_yf_to_linear(data_t *data, > > struct igt_buf *buf, > > for (int y = 0; y < height; y++) { > > for (int x = 0; x < width; x++) { > > uint32_t *ptr = yf_ptr(map, x, y, > > - buf->stride, buf->bpp / > > 8); > > + buf->surface[0].stride, > > + buf->bpp / 8); > > > > linear[y * width + x] = *ptr; > > } > > @@ -231,7 +233,7 @@ static void scratch_buf_write_to_png(data_t > > *data, struct igt_buf *buf, > > CAIRO_FORMAT_RGB2 > > 4, > > igt_buf_width(buf > > ), > > igt_buf_height(bu > > f), > > - buf->stride); > > + buf- > > >surface[0].stride); > > ret = cairo_surface_write_to_png(surface, > > make_filename(filename)); > > igt_assert(ret == CAIRO_STATUS_SUCCESS); > > cairo_surface_destroy(surface); > > @@ -324,7 +326,7 @@ static void scratch_buf_draw_pattern(data_t > > *data, struct igt_buf *buf, > > CAIRO_FORMAT_RGB2 > > 4, > > igt_buf_width(buf > > ), > > igt_buf_height(bu > > f), > > - buf->stride); > > + buf- > > >surface[0].stride); > > > > cr = cairo_create(surface); > > > > @@ -403,7 +405,7 @@ scratch_buf_copy(data_t *data, > > for (int y = 0; y < h; y++) { > > for (int x = 0; x < w; x++) { > > const uint32_t *ptr = yf_ptr(map, sx+x, > > sy+y, > > - src- > > >stride, > > + src- > > >surface[0].stride, > > src->bpp / > > 8); > > > > linear_dst[(dy+y) * width + dx+x] = > > *ptr; > > @@ -458,14 +460,14 @@ static void scratch_buf_init(data_t *data, > > struct igt_buf *buf, > > * turn mapped by one L1 AUX page table entry. > > */ > > if (intel_gen(data->devid) >= 12) > > - buf->stride = ALIGN(width * (bpp / 8), 128 * > > 4); > > + buf->surface[0].stride = ALIGN(width * (bpp / > > 8), 128 * 4); > > else > > - buf->stride = ALIGN(width * (bpp / 8), 128); > > + buf->surface[0].stride = ALIGN(width * (bpp / > > 8), 128); > > > > if (intel_gen(data->devid) >= 12) > > height = ALIGN(height, 4 * 32); > > > > - buf->size = buf->stride * height; > > + buf->surface[0].size = buf->surface[0].stride * height; > > buf->tiling = tiling; > > buf->bpp = bpp; > > > > @@ -473,7 +475,7 @@ static void scratch_buf_init(data_t *data, struct > > igt_buf *buf, > > aux_height = scratch_buf_aux_height(data->devid, buf); > > > > buf->compression = compression; > > - buf->ccs[0].offset = buf->stride * ALIGN(height, 32); > > + buf->ccs[0].offset = buf->surface[0].stride * > > ALIGN(height, 32); > > buf->ccs[0].stride = aux_width; > > > > size = buf->ccs[0].offset + aux_width * aux_height; > > @@ -481,18 +483,19 @@ static void scratch_buf_init(data_t *data, > > struct igt_buf *buf, > > buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, > > 4096); > > > > if (tiling == I915_TILING_Y) { > > - drm_intel_bo_set_tiling(buf->bo, &tiling, buf- > > >stride); > > + drm_intel_bo_set_tiling(buf->bo, &tiling, > > + buf- > > >surface[0].stride); > > igt_assert_eq(tiling, req_tiling); > > } > > } else if (req_tiling == I915_TILING_Yf) { > > int size; > > > > - buf->stride = ALIGN(width * (bpp / 8), 128); > > - buf->size = buf->stride * height; > > + buf->surface[0].stride = ALIGN(width * (bpp / 8), 128); > > + buf->surface[0].size = buf->surface[0].stride * height; > > buf->tiling = tiling; > > buf->bpp = bpp; > > > > - size = buf->stride * ALIGN(height, 32); > > + size = buf->surface[0].stride * ALIGN(height, 32); > > > > buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, > > 4096); > > } else { > > @@ -501,9 +504,9 @@ static void scratch_buf_init(data_t *data, struct > > igt_buf *buf, > > &tiling, &pitch, 0); > > igt_assert_eq(tiling, req_tiling); > > > > - buf->stride = pitch; > > + buf->surface[0].stride = pitch; > > buf->tiling = tiling; > > - buf->size = pitch * height; > > + buf->surface[0].size = pitch * height; > > buf->bpp = bpp; > > } > > > > @@ -806,7 +809,7 @@ static void test(data_t *data, uint32_t > > src_tiling, uint32_t dst_tiling, > > 0, 0, > > igt_buf_width(&dst), > > igt_buf_height(&dst), > > AUB_DUMP_BMP_FORMAT_ARGB_ > > 8888, > > - dst.stride, 0); > > + dst.surface[0].stride, > > 0); > > drm_intel_bufmgr_gem_set_aub_dump(data->bufmgr, false); > > } else if (check_all_pixels) { > > scratch_buf_check_all(data, &dst, &ref); > > diff --git a/tests/i915/gem_render_copy_redux.c > > b/tests/i915/gem_render_copy_redux.c > > index ef601c22..2388fc24 100644 > > --- a/tests/i915/gem_render_copy_redux.c > > +++ b/tests/i915/gem_render_copy_redux.c > > @@ -106,9 +106,9 @@ static void scratch_buf_init(data_t *data, struct > > igt_buf *buf, > > memset(buf, 0, sizeof(*buf)); > > > > buf->bo = bo; > > - buf->stride = stride; > > + buf->surface[0].stride = stride; > > buf->tiling = I915_TILING_NONE; > > - buf->size = SIZE; > > + buf->surface[0].size = SIZE; > > buf->bpp = 32; > > } > > > > diff --git a/tests/i915/gem_render_linear_blits.c > > b/tests/i915/gem_render_linear_blits.c > > index a726652b..666a43cd 100644 > > --- a/tests/i915/gem_render_linear_blits.c > > +++ b/tests/i915/gem_render_linear_blits.c > > @@ -108,15 +108,15 @@ static void run_test (int fd, int count) > > struct igt_buf src = {}, dst = {}; > > > > src.bo = bo[i % count]; > > - src.stride = STRIDE; > > + src.surface[0].stride = STRIDE; > > src.tiling = I915_TILING_NONE; > > - src.size = SIZE; > > + src.surface[0].size = SIZE; > > src.bpp = 32; > > > > dst.bo = bo[(i + 1) % count]; > > - dst.stride = STRIDE; > > + dst.surface[0].stride = STRIDE; > > dst.tiling = I915_TILING_NONE; > > - dst.size = SIZE; > > + dst.surface[0].size = SIZE; > > dst.bpp = 32; > > > > render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, > > &dst, 0, 0); > > @@ -133,15 +133,15 @@ static void run_test (int fd, int count) > > struct igt_buf src = {}, dst = {}; > > > > src.bo = bo[(i + 1) % count]; > > - src.stride = STRIDE; > > + src.surface[0].stride = STRIDE; > > src.tiling = I915_TILING_NONE; > > - src.size = SIZE; > > + src.surface[0].size = SIZE; > > src.bpp = 32; > > > > dst.bo = bo[i % count]; > > - dst.stride = STRIDE; > > + dst.surface[0].stride = STRIDE; > > dst.tiling = I915_TILING_NONE; > > - dst.size = SIZE; > > + dst.surface[0].size = SIZE; > > dst.bpp = 32; > > > > render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, > > &dst, 0, 0); > > @@ -160,15 +160,15 @@ static void run_test (int fd, int count) > > continue; > > > > src.bo = bo[s]; > > - src.stride = STRIDE; > > + src.surface[0].stride = STRIDE; > > src.tiling = I915_TILING_NONE; > > - src.size = SIZE; > > + src.surface[0].size = SIZE; > > src.bpp = 32; > > > > dst.bo = bo[d]; > > - dst.stride = STRIDE; > > + dst.surface[0].stride = STRIDE; > > dst.tiling = I915_TILING_NONE; > > - dst.size = SIZE; > > + dst.surface[0].size = SIZE; > > dst.bpp = 32; > > > > render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, > > &dst, 0, 0); > > diff --git a/tests/i915/gem_render_tiled_blits.c > > b/tests/i915/gem_render_tiled_blits.c > > index 14018329..1de1b72c 100644 > > --- a/tests/i915/gem_render_tiled_blits.c > > +++ b/tests/i915/gem_render_tiled_blits.c > > @@ -66,9 +66,9 @@ check_bo(struct intel_batchbuffer *batch, struct > > igt_buf *buf, uint32_t val) > > int i; > > > > tmp.bo = linear; > > - tmp.stride = STRIDE; > > + tmp.surface[0].stride = STRIDE; > > tmp.tiling = I915_TILING_NONE; > > - tmp.size = SIZE; > > + tmp.surface[0].size = SIZE; > > tmp.bpp = 32; > > > > render_copy(batch, NULL, buf, 0, 0, WIDTH, HEIGHT, &tmp, 0, 0); > > @@ -132,9 +132,9 @@ static void run_test (int fd, int count) > > buf[i].bo = drm_intel_bo_alloc_tiled(bufmgr, "", > > WIDTH, HEIGHT, 4, > > &tiling, &pitch, > > 0); > > - buf[i].stride = pitch; > > + buf[i].surface[0].stride = pitch; > > buf[i].tiling = tiling; > > - buf[i].size = SIZE; > > + buf[i].surface[0].size = SIZE; > > buf[i].bpp = 32; > > > > start_val[i] = start; > > diff --git a/tests/i915/gem_ring_sync_copy.c > > b/tests/i915/gem_ring_sync_copy.c > > index 1e5728bc..ddf5f750 100644 > > --- a/tests/i915/gem_ring_sync_copy.c > > +++ b/tests/i915/gem_ring_sync_copy.c > > @@ -134,9 +134,9 @@ static void scratch_buf_init_from_bo(struct > > igt_buf *buf, drm_intel_bo *bo) > > memset(buf, 0, sizeof(*buf)); > > > > buf->bo = bo; > > - buf->stride = 4 * WIDTH; > > + buf->surface[0].stride = 4 * WIDTH; > > buf->tiling = I915_TILING_NONE; > > - buf->size = 4 * WIDTH * HEIGHT; > > + buf->surface[0].size = 4 * WIDTH * HEIGHT; > > buf->bpp = 32; > > } > > > > diff --git a/tests/i915/gem_stress.c b/tests/i915/gem_stress.c > > index 57e2909c..50245b93 100644 > > --- a/tests/i915/gem_stress.c > > +++ b/tests/i915/gem_stress.c > > @@ -155,8 +155,8 @@ struct { > > static void tile2xy(struct igt_buf *buf, unsigned tile, unsigned *x, > > unsigned *y) > > { > > igt_assert(tile < buf->num_tiles); > > - *x = (tile*options.tile_size) % (buf->stride/sizeof(uint32_t)); > > - *y = ((tile*options.tile_size) / (buf- > > >stride/sizeof(uint32_t))) * options.tile_size; > > + *x = (tile*options.tile_size) % (buf- > > >surface[0].stride/sizeof(uint32_t)); > > + *y = ((tile*options.tile_size) / (buf- > > >surface[0].stride/sizeof(uint32_t))) * options.tile_size; > > } > > > > static void emit_blt(drm_intel_bo *src_bo, uint32_t src_tiling, > > unsigned src_pitch, > > @@ -268,8 +268,10 @@ static void cpu_copyfunc(struct igt_buf *src, > > unsigned src_x, unsigned src_y, > > set_to_cpu_domain(dst, 1); > > } > > > > - cpucpy2d(src->data, src->stride/sizeof(uint32_t), src_x, src_y, > > - dst->data, dst->stride/sizeof(uint32_t), dst_x, dst_y, > > + cpucpy2d(src->data, src->surface[0].stride/sizeof(uint32_t), > > src_x, > > + src_y, > > + dst->data, dst->surface[0].stride/sizeof(uint32_t), > > dst_x, > > + dst_y, > > logical_tile_no); > > } > > > > @@ -287,7 +289,7 @@ static void prw_copyfunc(struct igt_buf *src, > > unsigned src_x, unsigned src_y, > > > > if (src->tiling == I915_TILING_NONE) { > > for (i = 0; i < options.tile_size; i++) { > > - unsigned ofs = src_x*sizeof(uint32_t) + src- > > >stride*(src_y + i); > > + unsigned ofs = src_x*sizeof(uint32_t) + src- > > >surface[0].stride*(src_y + i); > > drm_intel_bo_get_subdata(src->bo, ofs, > > options.tile_size*size > > of(uint32_t), > > tmp_tile + > > options.tile_size*i); > > @@ -296,13 +298,14 @@ static void prw_copyfunc(struct igt_buf *src, > > unsigned src_x, unsigned src_y, > > if (options.use_cpu_maps) > > set_to_cpu_domain(src, 0); > > > > - cpucpy2d(src->data, src->stride/sizeof(uint32_t), > > src_x, src_y, > > + cpucpy2d(src->data, src- > > >surface[0].stride/sizeof(uint32_t), > > + src_x, src_y, > > tmp_tile, options.tile_size, 0, 0, > > logical_tile_no); > > } > > > > if (dst->tiling == I915_TILING_NONE) { > > for (i = 0; i < options.tile_size; i++) { > > - unsigned ofs = dst_x*sizeof(uint32_t) + dst- > > >stride*(dst_y + i); > > + unsigned ofs = dst_x*sizeof(uint32_t) + dst- > > >surface[0].stride*(dst_y + i); > > drm_intel_bo_subdata(dst->bo, ofs, > > options.tile_size*sizeof(u > > int32_t), > > tmp_tile + > > options.tile_size*i); > > @@ -312,7 +315,8 @@ static void prw_copyfunc(struct igt_buf *src, > > unsigned src_x, unsigned src_y, > > set_to_cpu_domain(dst, 1); > > > > cpucpy2d(tmp_tile, options.tile_size, 0, 0, > > - dst->data, dst->stride/sizeof(uint32_t), > > dst_x, dst_y, > > + dst->data, dst- > > >surface[0].stride/sizeof(uint32_t), > > + dst_x, dst_y, > > logical_tile_no); > > } > > } > > @@ -327,9 +331,9 @@ static void blitter_copyfunc(struct igt_buf *src, > > unsigned src_x, unsigned src_y > > if (keep_gpu_busy_counter & 1 && !fence_storm) > > keep_gpu_busy(); > > > > - emit_blt(src->bo, src->tiling, src->stride, src_x, src_y, > > + emit_blt(src->bo, src->tiling, src->surface[0].stride, src_x, > > src_y, > > options.tile_size, options.tile_size, > > - dst->bo, dst->tiling, dst->stride, dst_x, dst_y); > > + dst->bo, dst->tiling, dst->surface[0].stride, dst_x, > > dst_y); > > > > if (!(keep_gpu_busy_counter & 1) && !fence_storm) > > keep_gpu_busy(); > > @@ -441,7 +445,7 @@ static void fan_out(void) > > > > cpucpy2d(tmp_tile, options.tile_size, 0, 0, > > buffers[current_set][buf_idx].data, > > - buffers[current_set][buf_idx].stride / > > sizeof(uint32_t), > > + buffers[current_set][buf_idx].surface[0].strid > > e / sizeof(uint32_t), > > x, y, i); > > } > > > > @@ -465,7 +469,7 @@ static void fan_in_and_check(void) > > set_to_cpu_domain(&buffers[current_set][buf_idx > > ], 0); > > > > cpucpy2d(buffers[current_set][buf_idx].data, > > - buffers[current_set][buf_idx].stride / > > sizeof(uint32_t), > > + buffers[current_set][buf_idx].surface[0].strid > > e / sizeof(uint32_t), > > x, y, > > tmp_tile, options.tile_size, 0, 0, > > i); > > @@ -476,15 +480,15 @@ static void sanitize_stride(struct igt_buf > > *buf) > > { > > > > if (igt_buf_height(buf) > options.max_dimension) > > - buf->stride = buf->size / options.max_dimension; > > + buf->surface[0].stride = buf->surface[0].size / > > options.max_dimension; > > > > if (igt_buf_height(buf) < options.tile_size) > > - buf->stride = buf->size / options.tile_size; > > + buf->surface[0].stride = buf->surface[0].size / > > options.tile_size; > > > > if (igt_buf_width(buf) < options.tile_size) > > - buf->stride = options.tile_size * sizeof(uint32_t); > > + buf->surface[0].stride = options.tile_size * > > sizeof(uint32_t); > > > > - igt_assert(buf->stride <= 8192); > > + igt_assert(buf->surface[0].stride <= 8192); > > igt_assert(igt_buf_width(buf) <= options.max_dimension); > > igt_assert(igt_buf_height(buf) <= options.max_dimension); > > > > @@ -498,10 +502,10 @@ static void init_buffer(struct igt_buf *buf, > > unsigned size) > > memset(buf, 0, sizeof(*buf)); > > > > buf->bo = drm_intel_bo_alloc(bufmgr, "tiled bo", size, 4096); > > - buf->size = size; > > + buf->surface[0].size = size; > > igt_assert(buf->bo); > > buf->tiling = I915_TILING_NONE; > > - buf->stride = 4096; > > + buf->surface[0].stride = 4096; > > buf->bpp = 32; > > > > sanitize_stride(buf); > > @@ -560,25 +564,26 @@ static void init_set(unsigned set) > > if (buffers[set][i].tiling == I915_TILING_NONE) { > > /* min 64 byte stride */ > > r %= 8; > > - buffers[set][i].stride = 64 * (1 << r); > > + buffers[set][i].surface[0].stride = 64 * (1 << > > r); > > } else if (IS_GEN2(devid)) { > > /* min 128 byte stride */ > > r %= 7; > > - buffers[set][i].stride = 128 * (1 << r); > > + buffers[set][i].surface[0].stride = 128 * (1 << > > r); > > } else { > > /* min 512 byte stride */ > > r %= 5; > > - buffers[set][i].stride = 512 * (1 << r); > > + buffers[set][i].surface[0].stride = 512 * (1 << > > r); > > } > > > > sanitize_stride(&buffers[set][i]); > > > > gem_set_tiling(drm_fd, buffers[set][i].bo->handle, > > buffers[set][i].tiling, > > - buffers[set][i].stride); > > + buffers[set][i].surface[0].stride); > > > > if (options.trace_tile != -1 && i == > > options.trace_tile/options.tiles_per_buf) > > - igt_info("changing buffer %i containing tile > > %i: tiling %i, stride %i\n", i, options.trace_tile, > > buffers[set][i].tiling, buffers[set][i].stride); > > + igt_info("changing buffer %i containing tile > > %i: tiling %i, stride %i\n", i, options.trace_tile, > > buffers[set][i].tiling, > > + buffers[set][i].surface[0].stride); > > } > > } > > > > @@ -616,10 +621,10 @@ static void copy_tiles(unsigned *permutation) > > > > if (options.no_hw) { > > cpucpy2d(src_buf->data, > > - src_buf->stride / sizeof(uint32_t), > > + src_buf->surface[0].stride / > > sizeof(uint32_t), > > src_x, src_y, > > dst_buf->data, > > - dst_buf->stride / sizeof(uint32_t), > > + dst_buf->surface[0].stride / > > sizeof(uint32_t), > > dst_x, dst_y, > > i); > > } else { > > @@ -808,7 +813,7 @@ static void check_render_copyfunc(void) > > > > memset(src.data, 0xff, options.scratch_buf_size); > > for (j = 0; j < options.tile_size; j++) { > > - ptr = (uint32_t*)((char *)src.data + sx*4 + > > (sy+j) * src.stride); > > + ptr = (uint32_t*)((char *)src.data + sx*4 + > > (sy+j) * src.surface[0].stride); > > for (i = 0; i < options.tile_size; i++) > > ptr[i] = j * options.tile_size + i; > > } > > @@ -819,7 +824,7 @@ static void check_render_copyfunc(void) > > set_to_cpu_domain(&dst, 0); > > > > for (j = 0; j < options.tile_size; j++) { > > - ptr = (uint32_t*)((char *)dst.data + dx*4 + > > (dy+j) * dst.stride); > > + ptr = (uint32_t*)((char *)dst.data + dx*4 + > > (dy+j) * dst.surface[0].stride); > > for (i = 0; i < options.tile_size; i++) > > if (ptr[i] != j * options.tile_size + > > i) { > > igt_info("render copyfunc > > mismatch at (%d, %d): found %d, expected %d\n", i, j, ptr[i], j * > > options.tile_size + i); > > diff --git a/tests/i915/i915_pm_sseu.c b/tests/i915/i915_pm_sseu.c > > index e671e190..c2dee118 100644 > > --- a/tests/i915/i915_pm_sseu.c > > +++ b/tests/i915/i915_pm_sseu.c > > @@ -299,10 +299,11 @@ gem_init(void) > > igt_assert(gem.batch); > > gem.init = 3; > > > > - gem.buf.stride = sizeof(uint32_t); > > + gem.buf.surface[0].stride = sizeof(uint32_t); > > gem.buf.tiling = I915_TILING_NONE; > > - gem.buf.size = gem.buf.stride; > > - gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", gem.buf.size, > > 4096); > > + gem.buf.surface[0].size = gem.buf.surface[0].stride; > > + gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", > > + gem.buf.surface[0].size, 4096); > > gem.buf.bpp = 32; > > igt_assert(gem.buf.bo); > > gem.init = 4; > > diff --git a/tests/kms_big_fb.c b/tests/kms_big_fb.c > > index c5d002ca..eb144da9 100644 > > --- a/tests/kms_big_fb.c > > +++ b/tests/kms_big_fb.c > > @@ -60,9 +60,9 @@ static void init_buf(data_t *data, > > buf->bo = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, > > name, fb->gem_handle); > > buf->tiling = igt_fb_mod_to_tiling(fb->modifier); > > - buf->stride = fb->strides[0]; > > + buf->surface[0].stride = fb->strides[0]; > > buf->bpp = fb->plane_bpp[0]; > > - buf->size = fb->size; > > + buf->surface[0].size = fb->size; > > } > > > > static void fini_buf(struct igt_buf *buf) > > @@ -99,8 +99,10 @@ static void copy_pattern(data_t *data, > > h = min(h, src_fb->height - sy); > > h = min(h, dst_fb->height - dy); > > > > - intel_blt_copy(data->batch, src.bo, sx, sy, src.stride, > > - dst.bo, dx, dy, dst.stride, w, h, > > dst.bpp); > > + intel_blt_copy(data->batch, src.bo, sx, sy, > > + src.surface[0].stride, > > + dst.bo, dx, dy, dst.surface[0].stride, > > w, h, > > + dst.bpp); > > } > > > > fini_buf(&dst); > > diff --git a/tests/kms_psr.c b/tests/kms_psr.c > > index 232c80aa..d9be87d9 100644 > > --- a/tests/kms_psr.c > > +++ b/tests/kms_psr.c > > @@ -153,9 +153,9 @@ static void scratch_buf_init(struct igt_buf *buf, > > drm_intel_bo *bo, > > memset(buf, 0, sizeof(*buf)); > > > > buf->bo = bo; > > - buf->stride = stride; > > + buf->surface[0].stride = stride; > > buf->tiling = I915_TILING_X; > > - buf->size = size; > > + buf->surface[0].size = size; > > buf->bpp = 32; > > } > > > > diff --git a/tests/perf.c b/tests/perf.c > > index f5dd6051..982277df 100644 > > --- a/tests/perf.c > > +++ b/tests/perf.c > > @@ -506,9 +506,9 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, > > memset(buf, 0, sizeof(*buf)); > > > > buf->bo = bo; > > - buf->stride = stride; > > + buf->surface[0].stride = stride; > > buf->tiling = I915_TILING_NONE; > > - buf->size = size; > > + buf->surface[0].size = size; > > buf->bpp = 32; > > } > > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t v2 03/10] lib/igt_buf: Extend igt_buf to include two color surfaces 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 03/10] lib/igt_buf: Extend igt_buf to include two color surfaces Imre Deak 2019-12-30 12:06 ` Kahola, Mika @ 2019-12-30 17:58 ` Imre Deak 2019-12-31 8:40 ` Kahola, Mika 1 sibling, 1 reply; 33+ messages in thread From: Imre Deak @ 2019-12-30 17:58 UTC (permalink / raw) To: igt-dev UV FBs have two color surfaces so extend the igt_buf struct accordingly to support blitting such FBs. The patch is produced with the coccinelle patch below. No functional changes. @@ @@ struct igt_buf { ... - uint32_t stride; ... - uint32_t size; + struct { + uint32_t stride; + uint32_t size; + } surface[2]; ... }; @@ struct igt_buf b; @@ <... ( - b.stride + b.surface[0].stride | - b.size + b.surface[0].size ) ...> @@ struct igt_buf *b; @@ <... ( - b->size + b->surface[0].size | - b->stride + b->surface[0].stride ) ...> @@ identifier I; expression E1; expression E2; @@ ( struct igt_buf I = { - .size = E1, - .stride = E2, + .surface[0] = { + .size = E1, + .stride = E2, + }, }; | struct igt_buf I = { - .size = E1, + .surface[0] = { + .size = E1, + }, }; | struct igt_buf I = { - .stride = E1, + .surface[0] = { + .stride = E1, + }, }; ) v2: - Rebase on latest upstream. (Mika) Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- lib/gpu_cmds.c | 4 +- lib/igt_draw.c | 8 ++-- lib/igt_fb.c | 4 +- lib/intel_aux_pgtable.c | 5 ++- lib/intel_batchbuffer.c | 8 ++-- lib/intel_batchbuffer.h | 6 ++- lib/rendercopy_gen4.c | 4 +- lib/rendercopy_gen6.c | 4 +- lib/rendercopy_gen7.c | 4 +- lib/rendercopy_gen8.c | 4 +- lib/rendercopy_gen9.c | 4 +- lib/rendercopy_i830.c | 8 ++-- lib/rendercopy_i915.c | 8 ++-- lib/veboxcopy_gen12.c | 6 ++- tests/i915/gem_concurrent_all.c | 10 +++-- tests/i915/gem_gpgpu_fill.c | 4 +- tests/i915/gem_media_fill.c | 4 +- tests/i915/gem_media_vme.c | 6 +-- tests/i915/gem_ppgtt.c | 8 ++-- tests/i915/gem_read_read_speed.c | 10 +++-- tests/i915/gem_render_copy.c | 35 +++++++++-------- tests/i915/gem_render_copy_redux.c | 4 +- tests/i915/gem_render_linear_blits.c | 24 +++++------ tests/i915/gem_render_tiled_blits.c | 8 ++-- tests/i915/gem_ring_sync_copy.c | 4 +- tests/i915/gem_stress.c | 59 +++++++++++++++------------- tests/i915/i915_pm_sseu.c | 7 ++-- tests/kms_big_fb.c | 10 +++-- tests/kms_cursor_crc.c | 4 +- tests/kms_psr.c | 4 +- tests/perf.c | 4 +- 31 files changed, 151 insertions(+), 131 deletions(-) diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c index 8d270ee8..79412725 100644 --- a/lib/gpu_cmds.c +++ b/lib/gpu_cmds.c @@ -119,7 +119,7 @@ gen7_fill_surface_state(struct intel_batchbuffer *batch, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss7.shader_chanel_select_r = 4; ss->ss7.shader_chanel_select_g = 5; @@ -422,7 +422,7 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss7.shader_chanel_select_r = 4; ss->ss7.shader_chanel_select_g = 5; diff --git a/lib/igt_draw.c b/lib/igt_draw.c index 7e0edec1..6950bc49 100644 --- a/lib/igt_draw.c +++ b/lib/igt_draw.c @@ -603,14 +603,14 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data, igt_assert(dst); src_buf.bo = src; - src_buf.stride = tmp.stride; + src_buf.surface[0].stride = tmp.stride; src_buf.tiling = I915_TILING_NONE; - src_buf.size = tmp.size; + src_buf.surface[0].size = tmp.size; src_buf.bpp = tmp.bpp; dst_buf.bo = dst; - dst_buf.stride = buf->stride; + dst_buf.surface[0].stride = buf->stride; dst_buf.tiling = tiling; - dst_buf.size = buf->size; + dst_buf.surface[0].size = buf->size; dst_buf.bpp = buf->bpp; batch = intel_batchbuffer_alloc(cmd_data->bufmgr, devid); diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 0e1b8493..cc0fb373 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -1977,9 +1977,9 @@ static void init_buf(struct fb_blit_upload *blit, buf->bo = gem_handle_to_libdrm_bo(blit->bufmgr, blit->fd, name, fb->gem_handle); buf->tiling = igt_fb_mod_to_tiling(fb->modifier); - buf->stride = fb->strides[0]; + buf->surface[0].stride = fb->strides[0]; buf->bpp = fb->plane_bpp[0]; - buf->size = fb->size; + buf->surface[0].size = fb->size; if (is_ccs_modifier(fb->modifier)) { igt_assert_eq(fb->strides[0] & 127, 0); diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index dab83a9a..5addb2e2 100644 --- a/lib/intel_aux_pgtable.c +++ b/lib/intel_aux_pgtable.c @@ -77,7 +77,8 @@ pgt_table_count(int address_bits, const struct igt_buf **bufs, int buf_count) /* Avoid double counting for overlapping aligned bufs. */ start = max(start, end); - end = ALIGN(buf->bo->offset64 + buf->size, 1UL << address_bits); + end = ALIGN(buf->bo->offset64 + buf->surface[0].size, + 1UL << address_bits); igt_assert(end >= start); count += (end - start) >> address_bits; @@ -255,7 +256,7 @@ pgt_populate_entries_for_buf(struct pgtable *pgt, uint64_t top_table) { uint64_t surface_addr = buf->bo->offset64; - uint64_t surface_end = surface_addr + buf->size; + uint64_t surface_end = surface_addr + buf->surface[0].size; uint64_t aux_addr = buf->bo->offset64 + buf->ccs[0].offset; uint64_t l1_flags = pgt_get_l1_flags(buf); uint64_t lx_flags = pgt_get_lx_flags(); diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index 51aae4dc..3dc89024 100644 --- a/lib/intel_batchbuffer.c +++ b/lib/intel_batchbuffer.c @@ -512,7 +512,7 @@ intel_copy_bo(struct intel_batchbuffer *batch, */ unsigned igt_buf_width(const struct igt_buf *buf) { - return buf->stride/(buf->bpp / 8); + return buf->surface[0].stride/(buf->bpp / 8); } /** @@ -526,7 +526,7 @@ unsigned igt_buf_width(const struct igt_buf *buf) */ unsigned igt_buf_height(const struct igt_buf *buf) { - return buf->size/buf->stride; + return buf->surface[0].size/buf->surface[0].stride; } /* @@ -785,8 +785,8 @@ void igt_blitter_fast_copy(struct intel_batchbuffer *batch, igt_assert(src->bpp == dst->bpp); - src_pitch = fast_copy_pitch(src->stride, src->tiling); - dst_pitch = fast_copy_pitch(dst->stride, src->tiling); + src_pitch = fast_copy_pitch(src->surface[0].stride, src->tiling); + dst_pitch = fast_copy_pitch(dst->surface[0].stride, src->tiling); dword0 = fast_copy_dword0(src->tiling, dst->tiling); dword1 = fast_copy_dword1(src->tiling, dst->tiling, dst->bpp); diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index 63d32188..69580839 100644 --- a/lib/intel_batchbuffer.h +++ b/lib/intel_batchbuffer.h @@ -232,12 +232,14 @@ enum i915_compression { */ struct igt_buf { drm_intel_bo *bo; - uint32_t stride; uint32_t tiling; enum i915_compression compression; uint32_t bpp; uint32_t *data; - uint32_t size; + struct { + uint32_t stride; + uint32_t size; + } surface[2]; struct { uint32_t offset; uint32_t stride; diff --git a/lib/rendercopy_gen4.c b/lib/rendercopy_gen4.c index 42de77f9..d07b8e48 100644 --- a/lib/rendercopy_gen4.c +++ b/lib/rendercopy_gen4.c @@ -142,7 +142,7 @@ gen4_bind_buf(struct intel_batchbuffer *batch, uint32_t write_domain, read_domain; int ret; - igt_assert_lte(buf->stride, 128*1024); + igt_assert_lte(buf->surface[0].stride, 128*1024); igt_assert_lte(igt_buf_width(buf), 8192); igt_assert_lte(igt_buf_height(buf), 8192); @@ -176,7 +176,7 @@ gen4_bind_buf(struct intel_batchbuffer *batch, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c index 83c7d694..87034774 100644 --- a/lib/rendercopy_gen6.c +++ b/lib/rendercopy_gen6.c @@ -79,7 +79,7 @@ gen6_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, uint32_t write_domain, read_domain; int ret; - igt_assert_lte(buf->stride, 128*1024); + igt_assert_lte(buf->surface[0].stride, 128*1024); igt_assert_lte(igt_buf_width(buf), 8192); igt_assert_lte(igt_buf_height(buf), 8192); @@ -113,7 +113,7 @@ gen6_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c index a3c8b7f3..b88b75e9 100644 --- a/lib/rendercopy_gen7.c +++ b/lib/rendercopy_gen7.c @@ -65,7 +65,7 @@ gen7_bind_buf(struct intel_batchbuffer *batch, uint32_t write_domain, read_domain; int ret; - igt_assert_lte(buf->stride, 256*1024); + igt_assert_lte(buf->surface[0].stride, 256*1024); igt_assert_lte(igt_buf_width(buf), 16384); igt_assert_lte(igt_buf_height(buf), 16384); @@ -92,7 +92,7 @@ gen7_bind_buf(struct intel_batchbuffer *batch, ss[1] = buf->bo->offset; ss[2] = ((igt_buf_width(buf) - 1) << GEN7_SURFACE_WIDTH_SHIFT | (igt_buf_height(buf) - 1) << GEN7_SURFACE_HEIGHT_SHIFT); - ss[3] = (buf->stride - 1) << GEN7_SURFACE_PITCH_SHIFT; + ss[3] = (buf->surface[0].stride - 1) << GEN7_SURFACE_PITCH_SHIFT; ss[4] = 0; if (IS_VALLEYVIEW(batch->devid)) ss[5] = VLV_MOCS_L3 << 16; diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c index e22d8501..8e02d846 100644 --- a/lib/rendercopy_gen8.c +++ b/lib/rendercopy_gen8.c @@ -151,7 +151,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, uint32_t write_domain, read_domain, offset; int ret; - igt_assert_lte(buf->stride, 256*1024); + igt_assert_lte(buf->surface[0].stride, 256*1024); igt_assert_lte(igt_buf_width(buf), 16384); igt_assert_lte(igt_buf_height(buf), 16384); @@ -199,7 +199,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss7.shader_chanel_select_r = 4; ss->ss7.shader_chanel_select_g = 5; diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index 4d4541e3..835c8d80 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -199,7 +199,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, uint32_t write_domain, read_domain, offset; int ret; - igt_assert_lte(buf->stride, 256*1024); + igt_assert_lte(buf->surface[0].stride, 256*1024); igt_assert_lte(igt_buf_width(buf), 16384); igt_assert_lte(igt_buf_height(buf), 16384); @@ -250,7 +250,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, ss->ss2.height = igt_buf_height(buf) - 1; ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->stride - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; ss->ss7.skl.shader_chanel_select_r = 4; ss->ss7.skl.shader_chanel_select_g = 5; diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c index e8c04718..ca815122 100644 --- a/lib/rendercopy_i830.c +++ b/lib/rendercopy_i830.c @@ -138,7 +138,7 @@ static void gen2_emit_target(struct intel_batchbuffer *batch, uint32_t tiling; uint32_t format; - igt_assert_lte(dst->stride, 8192); + igt_assert_lte(dst->surface[0].stride, 8192); igt_assert_lte(igt_buf_width(dst), 2048); igt_assert_lte(igt_buf_height(dst), 2048); @@ -156,7 +156,7 @@ static void gen2_emit_target(struct intel_batchbuffer *batch, tiling |= BUF_3D_TILE_WALK_Y; OUT_BATCH(_3DSTATE_BUF_INFO_CMD); - OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst->stride)); + OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst->surface[0].stride)); OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); @@ -179,7 +179,7 @@ static void gen2_emit_texture(struct intel_batchbuffer *batch, uint32_t tiling; uint32_t format; - igt_assert_lte(src->stride, 8192); + igt_assert_lte(src->surface[0].stride, 8192); igt_assert_lte(igt_buf_width(src), 2048); igt_assert_lte(igt_buf_height(src), 2048); @@ -201,7 +201,7 @@ static void gen2_emit_texture(struct intel_batchbuffer *batch, OUT_BATCH((igt_buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT | (igt_buf_width(src) - 1) << TM0S1_WIDTH_SHIFT | format | tiling); - OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D); + OUT_BATCH((src->surface[0].stride / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D); OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT | FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT | MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT); diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c index 1baa7a1b..56e1863e 100644 --- a/lib/rendercopy_i915.c +++ b/lib/rendercopy_i915.c @@ -88,7 +88,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch, #define TEX_COUNT 1 uint32_t format_bits, tiling_bits = 0; - igt_assert_lte(src->stride, 8192); + igt_assert_lte(src->surface[0].stride, 8192); igt_assert_lte(igt_buf_width(src), 2048); igt_assert_lte(igt_buf_height(src), 2048); @@ -110,7 +110,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch, OUT_BATCH(format_bits | tiling_bits | (igt_buf_height(src) - 1) << MS3_HEIGHT_SHIFT | (igt_buf_width(src) - 1) << MS3_WIDTH_SHIFT); - OUT_BATCH((src->stride/4-1) << MS4_PITCH_SHIFT); + OUT_BATCH((src->surface[0].stride/4-1) << MS4_PITCH_SHIFT); OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT)); OUT_BATCH((1 << TEX_COUNT) - 1); @@ -128,7 +128,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch, uint32_t tiling_bits = 0; uint32_t format_bits; - igt_assert_lte(dst->stride, 8192); + igt_assert_lte(dst->surface[0].stride, 8192); igt_assert_lte(igt_buf_width(dst), 2048); igt_assert_lte(igt_buf_height(dst), 2048); @@ -146,7 +146,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch, OUT_BATCH(_3DSTATE_BUF_INFO_CMD); OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits | - BUF_3D_PITCH(dst->stride)); + BUF_3D_PITCH(dst->surface[0].stride)); OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c index 87800941..2f017514 100644 --- a/lib/veboxcopy_gen12.c +++ b/lib/veboxcopy_gen12.c @@ -248,12 +248,14 @@ void gen12_vebox_copyfunc(struct intel_batchbuffer *batch, /* TODO: add support for more formats */ igt_assert(src->bpp == 32); emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT, - width, height, src->bpp, src->stride, + width, height, src->bpp, + src->surface[0].stride, src->tiling, R8G8B8A8_UNORM); igt_assert(dst->bpp == 32); emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT, - width, height, dst->bpp, dst->stride, + width, height, dst->bpp, + dst->surface[0].stride, dst->tiling, R8G8B8A8_UNORM); emit_tiling_convert_cmd(batch, diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c index 6486bebf..f1be4a85 100644 --- a/tests/i915/gem_concurrent_all.c +++ b/tests/i915/gem_concurrent_all.c @@ -851,15 +851,17 @@ static void render_copy_bo(struct buffers *b, drm_intel_bo *dst, drm_intel_bo *s { struct igt_buf d = { .bo = dst, - .size = b->npixels * 4, .num_tiles = b->npixels * 4, - .stride = b->width * 4, + .surface[0] = { + .size = b->npixels * 4, .stride = b->width * 4, + }, .bpp = 32, }, s = { .bo = src, - .size = b->npixels * 4, .num_tiles = b->npixels * 4, - .stride = b->width * 4, + .surface[0] = { + .size = b->npixels * 4, .stride = b->width * 4, + }, .bpp = 32, }; uint32_t swizzle; diff --git a/tests/i915/gem_gpgpu_fill.c b/tests/i915/gem_gpgpu_fill.c index 68918c3e..b2d401d6 100644 --- a/tests/i915/gem_gpgpu_fill.c +++ b/tests/i915/gem_gpgpu_fill.c @@ -75,9 +75,9 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = stride; + buf->surface[0].stride = stride; buf->tiling = I915_TILING_NONE; - buf->size = SIZE; + buf->surface[0].size = SIZE; buf->bpp = 32; } diff --git a/tests/i915/gem_media_fill.c b/tests/i915/gem_media_fill.c index a7d7708c..c880bae9 100644 --- a/tests/i915/gem_media_fill.c +++ b/tests/i915/gem_media_fill.c @@ -78,9 +78,9 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = stride; + buf->surface[0].stride = stride; buf->tiling = I915_TILING_NONE; - buf->size = SIZE; + buf->surface[0].size = SIZE; buf->bpp = 32; } diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c index d5045ad1..20f5ca35 100644 --- a/tests/i915/gem_media_vme.c +++ b/tests/i915/gem_media_vme.c @@ -58,7 +58,7 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, buf->bo = bo; buf->tiling = I915_TILING_NONE; - buf->size = size; + buf->surface[0].size = size; } static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf) @@ -71,14 +71,14 @@ static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf) * with this vme kernel. */ - buf->stride = STRIDE; + buf->surface[0].stride = STRIDE; } static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf) { scratch_buf_init(bufmgr, buf, OUTPUT_SIZE); - buf->stride = 1; + buf->surface[0].stride = 1; } static uint64_t switch_off_n_bits(uint64_t mask, unsigned int n) diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c index 89cdc4db..4c7d3ba2 100644 --- a/tests/i915/gem_ppgtt.c +++ b/tests/i915/gem_ppgtt.c @@ -73,9 +73,9 @@ static void scratch_buf_init(struct igt_buf *buf, memset(buf, 0, sizeof(*buf)); buf->bo = create_bo(bufmgr, pixel); - buf->stride = STRIDE; + buf->surface[0].stride = STRIDE; buf->tiling = I915_TILING_NONE; - buf->size = SIZE; + buf->surface[0].size = SIZE; buf->bpp = 32; } @@ -140,9 +140,9 @@ static void fork_rcs_copy(int timeout, uint32_t final, } buf.bo = dst[child]; - buf.stride = STRIDE; + buf.surface[0].stride = STRIDE; buf.tiling = I915_TILING_NONE; - buf.size = SIZE; + buf.surface[0].size = SIZE; buf.bpp = 32; i = 0; diff --git a/tests/i915/gem_read_read_speed.c b/tests/i915/gem_read_read_speed.c index 8b5ba8f7..2aab2204 100644 --- a/tests/i915/gem_read_read_speed.c +++ b/tests/i915/gem_read_read_speed.c @@ -53,15 +53,17 @@ static drm_intel_bo *rcs_copy_bo(drm_intel_bo *dst, drm_intel_bo *src) { struct igt_buf d = { .bo = dst, - .size = width * height * 4, .num_tiles = width * height * 4, - .stride = width * 4, + .surface[0] = { + .size = width * height * 4, .stride = width * 4, + }, .bpp = 32, }, s = { .bo = src, - .size = width * height * 4, .num_tiles = width * height * 4, - .stride = width * 4, + .surface[0] = { + .size = width * height * 4, .stride = width * 4, + }, .bpp = 32, }; uint32_t swizzle; diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c index df0d045e..5abb2036 100644 --- a/tests/i915/gem_render_copy.c +++ b/tests/i915/gem_render_copy.c @@ -118,7 +118,8 @@ static void copy_linear_to_yf(data_t *data, struct igt_buf *buf, for (int y = 0; y < height; y++) { for (int x = 0; x < width; x++) { uint32_t *ptr = yf_ptr(map, x, y, - buf->stride, buf->bpp / 8); + buf->surface[0].stride, + buf->bpp / 8); *ptr = linear[y * width + x]; } @@ -142,7 +143,8 @@ static void copy_yf_to_linear(data_t *data, struct igt_buf *buf, for (int y = 0; y < height; y++) { for (int x = 0; x < width; x++) { uint32_t *ptr = yf_ptr(map, x, y, - buf->stride, buf->bpp / 8); + buf->surface[0].stride, + buf->bpp / 8); linear[y * width + x] = *ptr; } @@ -231,7 +233,7 @@ static void scratch_buf_write_to_png(data_t *data, struct igt_buf *buf, CAIRO_FORMAT_RGB24, igt_buf_width(buf), igt_buf_height(buf), - buf->stride); + buf->surface[0].stride); ret = cairo_surface_write_to_png(surface, make_filename(filename)); igt_assert(ret == CAIRO_STATUS_SUCCESS); cairo_surface_destroy(surface); @@ -324,7 +326,7 @@ static void scratch_buf_draw_pattern(data_t *data, struct igt_buf *buf, CAIRO_FORMAT_RGB24, igt_buf_width(buf), igt_buf_height(buf), - buf->stride); + buf->surface[0].stride); cr = cairo_create(surface); @@ -403,7 +405,7 @@ scratch_buf_copy(data_t *data, for (int y = 0; y < h; y++) { for (int x = 0; x < w; x++) { const uint32_t *ptr = yf_ptr(map, sx+x, sy+y, - src->stride, + src->surface[0].stride, src->bpp / 8); linear_dst[(dy+y) * width + dx+x] = *ptr; @@ -458,14 +460,14 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, * turn mapped by one L1 AUX page table entry. */ if (intel_gen(data->devid) >= 12) - buf->stride = ALIGN(width * (bpp / 8), 128 * 4); + buf->surface[0].stride = ALIGN(width * (bpp / 8), 128 * 4); else - buf->stride = ALIGN(width * (bpp / 8), 128); + buf->surface[0].stride = ALIGN(width * (bpp / 8), 128); if (intel_gen(data->devid) >= 12) height = ALIGN(height, 4 * 32); - buf->size = buf->stride * height; + buf->surface[0].size = buf->surface[0].stride * height; buf->tiling = tiling; buf->bpp = bpp; @@ -473,7 +475,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, aux_height = scratch_buf_aux_height(data->devid, buf); buf->compression = compression; - buf->ccs[0].offset = buf->stride * ALIGN(height, 32); + buf->ccs[0].offset = buf->surface[0].stride * ALIGN(height, 32); buf->ccs[0].stride = aux_width; size = buf->ccs[0].offset + aux_width * aux_height; @@ -481,18 +483,19 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, 4096); if (tiling == I915_TILING_Y) { - drm_intel_bo_set_tiling(buf->bo, &tiling, buf->stride); + drm_intel_bo_set_tiling(buf->bo, &tiling, + buf->surface[0].stride); igt_assert_eq(tiling, req_tiling); } } else if (req_tiling == I915_TILING_Yf) { int size; - buf->stride = ALIGN(width * (bpp / 8), 128); - buf->size = buf->stride * height; + buf->surface[0].stride = ALIGN(width * (bpp / 8), 128); + buf->surface[0].size = buf->surface[0].stride * height; buf->tiling = tiling; buf->bpp = bpp; - size = buf->stride * ALIGN(height, 32); + size = buf->surface[0].stride * ALIGN(height, 32); buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, 4096); } else { @@ -501,9 +504,9 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, &tiling, &pitch, 0); igt_assert_eq(tiling, req_tiling); - buf->stride = pitch; + buf->surface[0].stride = pitch; buf->tiling = tiling; - buf->size = pitch * height; + buf->surface[0].size = pitch * height; buf->bpp = bpp; } @@ -806,7 +809,7 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling, 0, 0, igt_buf_width(&dst), igt_buf_height(&dst), AUB_DUMP_BMP_FORMAT_ARGB_8888, - dst.stride, 0); + dst.surface[0].stride, 0); drm_intel_bufmgr_gem_set_aub_dump(data->bufmgr, false); } else if (check_all_pixels) { scratch_buf_check_all(data, &dst, &ref); diff --git a/tests/i915/gem_render_copy_redux.c b/tests/i915/gem_render_copy_redux.c index ef601c22..2388fc24 100644 --- a/tests/i915/gem_render_copy_redux.c +++ b/tests/i915/gem_render_copy_redux.c @@ -106,9 +106,9 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = stride; + buf->surface[0].stride = stride; buf->tiling = I915_TILING_NONE; - buf->size = SIZE; + buf->surface[0].size = SIZE; buf->bpp = 32; } diff --git a/tests/i915/gem_render_linear_blits.c b/tests/i915/gem_render_linear_blits.c index a726652b..666a43cd 100644 --- a/tests/i915/gem_render_linear_blits.c +++ b/tests/i915/gem_render_linear_blits.c @@ -108,15 +108,15 @@ static void run_test (int fd, int count) struct igt_buf src = {}, dst = {}; src.bo = bo[i % count]; - src.stride = STRIDE; + src.surface[0].stride = STRIDE; src.tiling = I915_TILING_NONE; - src.size = SIZE; + src.surface[0].size = SIZE; src.bpp = 32; dst.bo = bo[(i + 1) % count]; - dst.stride = STRIDE; + dst.surface[0].stride = STRIDE; dst.tiling = I915_TILING_NONE; - dst.size = SIZE; + dst.surface[0].size = SIZE; dst.bpp = 32; render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, &dst, 0, 0); @@ -133,15 +133,15 @@ static void run_test (int fd, int count) struct igt_buf src = {}, dst = {}; src.bo = bo[(i + 1) % count]; - src.stride = STRIDE; + src.surface[0].stride = STRIDE; src.tiling = I915_TILING_NONE; - src.size = SIZE; + src.surface[0].size = SIZE; src.bpp = 32; dst.bo = bo[i % count]; - dst.stride = STRIDE; + dst.surface[0].stride = STRIDE; dst.tiling = I915_TILING_NONE; - dst.size = SIZE; + dst.surface[0].size = SIZE; dst.bpp = 32; render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, &dst, 0, 0); @@ -160,15 +160,15 @@ static void run_test (int fd, int count) continue; src.bo = bo[s]; - src.stride = STRIDE; + src.surface[0].stride = STRIDE; src.tiling = I915_TILING_NONE; - src.size = SIZE; + src.surface[0].size = SIZE; src.bpp = 32; dst.bo = bo[d]; - dst.stride = STRIDE; + dst.surface[0].stride = STRIDE; dst.tiling = I915_TILING_NONE; - dst.size = SIZE; + dst.surface[0].size = SIZE; dst.bpp = 32; render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, &dst, 0, 0); diff --git a/tests/i915/gem_render_tiled_blits.c b/tests/i915/gem_render_tiled_blits.c index 14018329..1de1b72c 100644 --- a/tests/i915/gem_render_tiled_blits.c +++ b/tests/i915/gem_render_tiled_blits.c @@ -66,9 +66,9 @@ check_bo(struct intel_batchbuffer *batch, struct igt_buf *buf, uint32_t val) int i; tmp.bo = linear; - tmp.stride = STRIDE; + tmp.surface[0].stride = STRIDE; tmp.tiling = I915_TILING_NONE; - tmp.size = SIZE; + tmp.surface[0].size = SIZE; tmp.bpp = 32; render_copy(batch, NULL, buf, 0, 0, WIDTH, HEIGHT, &tmp, 0, 0); @@ -132,9 +132,9 @@ static void run_test (int fd, int count) buf[i].bo = drm_intel_bo_alloc_tiled(bufmgr, "", WIDTH, HEIGHT, 4, &tiling, &pitch, 0); - buf[i].stride = pitch; + buf[i].surface[0].stride = pitch; buf[i].tiling = tiling; - buf[i].size = SIZE; + buf[i].surface[0].size = SIZE; buf[i].bpp = 32; start_val[i] = start; diff --git a/tests/i915/gem_ring_sync_copy.c b/tests/i915/gem_ring_sync_copy.c index 1e5728bc..ddf5f750 100644 --- a/tests/i915/gem_ring_sync_copy.c +++ b/tests/i915/gem_ring_sync_copy.c @@ -134,9 +134,9 @@ static void scratch_buf_init_from_bo(struct igt_buf *buf, drm_intel_bo *bo) memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = 4 * WIDTH; + buf->surface[0].stride = 4 * WIDTH; buf->tiling = I915_TILING_NONE; - buf->size = 4 * WIDTH * HEIGHT; + buf->surface[0].size = 4 * WIDTH * HEIGHT; buf->bpp = 32; } diff --git a/tests/i915/gem_stress.c b/tests/i915/gem_stress.c index 57e2909c..50245b93 100644 --- a/tests/i915/gem_stress.c +++ b/tests/i915/gem_stress.c @@ -155,8 +155,8 @@ struct { static void tile2xy(struct igt_buf *buf, unsigned tile, unsigned *x, unsigned *y) { igt_assert(tile < buf->num_tiles); - *x = (tile*options.tile_size) % (buf->stride/sizeof(uint32_t)); - *y = ((tile*options.tile_size) / (buf->stride/sizeof(uint32_t))) * options.tile_size; + *x = (tile*options.tile_size) % (buf->surface[0].stride/sizeof(uint32_t)); + *y = ((tile*options.tile_size) / (buf->surface[0].stride/sizeof(uint32_t))) * options.tile_size; } static void emit_blt(drm_intel_bo *src_bo, uint32_t src_tiling, unsigned src_pitch, @@ -268,8 +268,10 @@ static void cpu_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y, set_to_cpu_domain(dst, 1); } - cpucpy2d(src->data, src->stride/sizeof(uint32_t), src_x, src_y, - dst->data, dst->stride/sizeof(uint32_t), dst_x, dst_y, + cpucpy2d(src->data, src->surface[0].stride/sizeof(uint32_t), src_x, + src_y, + dst->data, dst->surface[0].stride/sizeof(uint32_t), dst_x, + dst_y, logical_tile_no); } @@ -287,7 +289,7 @@ static void prw_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y, if (src->tiling == I915_TILING_NONE) { for (i = 0; i < options.tile_size; i++) { - unsigned ofs = src_x*sizeof(uint32_t) + src->stride*(src_y + i); + unsigned ofs = src_x*sizeof(uint32_t) + src->surface[0].stride*(src_y + i); drm_intel_bo_get_subdata(src->bo, ofs, options.tile_size*sizeof(uint32_t), tmp_tile + options.tile_size*i); @@ -296,13 +298,14 @@ static void prw_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y, if (options.use_cpu_maps) set_to_cpu_domain(src, 0); - cpucpy2d(src->data, src->stride/sizeof(uint32_t), src_x, src_y, + cpucpy2d(src->data, src->surface[0].stride/sizeof(uint32_t), + src_x, src_y, tmp_tile, options.tile_size, 0, 0, logical_tile_no); } if (dst->tiling == I915_TILING_NONE) { for (i = 0; i < options.tile_size; i++) { - unsigned ofs = dst_x*sizeof(uint32_t) + dst->stride*(dst_y + i); + unsigned ofs = dst_x*sizeof(uint32_t) + dst->surface[0].stride*(dst_y + i); drm_intel_bo_subdata(dst->bo, ofs, options.tile_size*sizeof(uint32_t), tmp_tile + options.tile_size*i); @@ -312,7 +315,8 @@ static void prw_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y, set_to_cpu_domain(dst, 1); cpucpy2d(tmp_tile, options.tile_size, 0, 0, - dst->data, dst->stride/sizeof(uint32_t), dst_x, dst_y, + dst->data, dst->surface[0].stride/sizeof(uint32_t), + dst_x, dst_y, logical_tile_no); } } @@ -327,9 +331,9 @@ static void blitter_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y if (keep_gpu_busy_counter & 1 && !fence_storm) keep_gpu_busy(); - emit_blt(src->bo, src->tiling, src->stride, src_x, src_y, + emit_blt(src->bo, src->tiling, src->surface[0].stride, src_x, src_y, options.tile_size, options.tile_size, - dst->bo, dst->tiling, dst->stride, dst_x, dst_y); + dst->bo, dst->tiling, dst->surface[0].stride, dst_x, dst_y); if (!(keep_gpu_busy_counter & 1) && !fence_storm) keep_gpu_busy(); @@ -441,7 +445,7 @@ static void fan_out(void) cpucpy2d(tmp_tile, options.tile_size, 0, 0, buffers[current_set][buf_idx].data, - buffers[current_set][buf_idx].stride / sizeof(uint32_t), + buffers[current_set][buf_idx].surface[0].stride / sizeof(uint32_t), x, y, i); } @@ -465,7 +469,7 @@ static void fan_in_and_check(void) set_to_cpu_domain(&buffers[current_set][buf_idx], 0); cpucpy2d(buffers[current_set][buf_idx].data, - buffers[current_set][buf_idx].stride / sizeof(uint32_t), + buffers[current_set][buf_idx].surface[0].stride / sizeof(uint32_t), x, y, tmp_tile, options.tile_size, 0, 0, i); @@ -476,15 +480,15 @@ static void sanitize_stride(struct igt_buf *buf) { if (igt_buf_height(buf) > options.max_dimension) - buf->stride = buf->size / options.max_dimension; + buf->surface[0].stride = buf->surface[0].size / options.max_dimension; if (igt_buf_height(buf) < options.tile_size) - buf->stride = buf->size / options.tile_size; + buf->surface[0].stride = buf->surface[0].size / options.tile_size; if (igt_buf_width(buf) < options.tile_size) - buf->stride = options.tile_size * sizeof(uint32_t); + buf->surface[0].stride = options.tile_size * sizeof(uint32_t); - igt_assert(buf->stride <= 8192); + igt_assert(buf->surface[0].stride <= 8192); igt_assert(igt_buf_width(buf) <= options.max_dimension); igt_assert(igt_buf_height(buf) <= options.max_dimension); @@ -498,10 +502,10 @@ static void init_buffer(struct igt_buf *buf, unsigned size) memset(buf, 0, sizeof(*buf)); buf->bo = drm_intel_bo_alloc(bufmgr, "tiled bo", size, 4096); - buf->size = size; + buf->surface[0].size = size; igt_assert(buf->bo); buf->tiling = I915_TILING_NONE; - buf->stride = 4096; + buf->surface[0].stride = 4096; buf->bpp = 32; sanitize_stride(buf); @@ -560,25 +564,26 @@ static void init_set(unsigned set) if (buffers[set][i].tiling == I915_TILING_NONE) { /* min 64 byte stride */ r %= 8; - buffers[set][i].stride = 64 * (1 << r); + buffers[set][i].surface[0].stride = 64 * (1 << r); } else if (IS_GEN2(devid)) { /* min 128 byte stride */ r %= 7; - buffers[set][i].stride = 128 * (1 << r); + buffers[set][i].surface[0].stride = 128 * (1 << r); } else { /* min 512 byte stride */ r %= 5; - buffers[set][i].stride = 512 * (1 << r); + buffers[set][i].surface[0].stride = 512 * (1 << r); } sanitize_stride(&buffers[set][i]); gem_set_tiling(drm_fd, buffers[set][i].bo->handle, buffers[set][i].tiling, - buffers[set][i].stride); + buffers[set][i].surface[0].stride); if (options.trace_tile != -1 && i == options.trace_tile/options.tiles_per_buf) - igt_info("changing buffer %i containing tile %i: tiling %i, stride %i\n", i, options.trace_tile, buffers[set][i].tiling, buffers[set][i].stride); + igt_info("changing buffer %i containing tile %i: tiling %i, stride %i\n", i, options.trace_tile, buffers[set][i].tiling, + buffers[set][i].surface[0].stride); } } @@ -616,10 +621,10 @@ static void copy_tiles(unsigned *permutation) if (options.no_hw) { cpucpy2d(src_buf->data, - src_buf->stride / sizeof(uint32_t), + src_buf->surface[0].stride / sizeof(uint32_t), src_x, src_y, dst_buf->data, - dst_buf->stride / sizeof(uint32_t), + dst_buf->surface[0].stride / sizeof(uint32_t), dst_x, dst_y, i); } else { @@ -808,7 +813,7 @@ static void check_render_copyfunc(void) memset(src.data, 0xff, options.scratch_buf_size); for (j = 0; j < options.tile_size; j++) { - ptr = (uint32_t*)((char *)src.data + sx*4 + (sy+j) * src.stride); + ptr = (uint32_t*)((char *)src.data + sx*4 + (sy+j) * src.surface[0].stride); for (i = 0; i < options.tile_size; i++) ptr[i] = j * options.tile_size + i; } @@ -819,7 +824,7 @@ static void check_render_copyfunc(void) set_to_cpu_domain(&dst, 0); for (j = 0; j < options.tile_size; j++) { - ptr = (uint32_t*)((char *)dst.data + dx*4 + (dy+j) * dst.stride); + ptr = (uint32_t*)((char *)dst.data + dx*4 + (dy+j) * dst.surface[0].stride); for (i = 0; i < options.tile_size; i++) if (ptr[i] != j * options.tile_size + i) { igt_info("render copyfunc mismatch at (%d, %d): found %d, expected %d\n", i, j, ptr[i], j * options.tile_size + i); diff --git a/tests/i915/i915_pm_sseu.c b/tests/i915/i915_pm_sseu.c index e671e190..c2dee118 100644 --- a/tests/i915/i915_pm_sseu.c +++ b/tests/i915/i915_pm_sseu.c @@ -299,10 +299,11 @@ gem_init(void) igt_assert(gem.batch); gem.init = 3; - gem.buf.stride = sizeof(uint32_t); + gem.buf.surface[0].stride = sizeof(uint32_t); gem.buf.tiling = I915_TILING_NONE; - gem.buf.size = gem.buf.stride; - gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", gem.buf.size, 4096); + gem.buf.surface[0].size = gem.buf.surface[0].stride; + gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", + gem.buf.surface[0].size, 4096); gem.buf.bpp = 32; igt_assert(gem.buf.bo); gem.init = 4; diff --git a/tests/kms_big_fb.c b/tests/kms_big_fb.c index c5d002ca..eb144da9 100644 --- a/tests/kms_big_fb.c +++ b/tests/kms_big_fb.c @@ -60,9 +60,9 @@ static void init_buf(data_t *data, buf->bo = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, name, fb->gem_handle); buf->tiling = igt_fb_mod_to_tiling(fb->modifier); - buf->stride = fb->strides[0]; + buf->surface[0].stride = fb->strides[0]; buf->bpp = fb->plane_bpp[0]; - buf->size = fb->size; + buf->surface[0].size = fb->size; } static void fini_buf(struct igt_buf *buf) @@ -99,8 +99,10 @@ static void copy_pattern(data_t *data, h = min(h, src_fb->height - sy); h = min(h, dst_fb->height - dy); - intel_blt_copy(data->batch, src.bo, sx, sy, src.stride, - dst.bo, dx, dy, dst.stride, w, h, dst.bpp); + intel_blt_copy(data->batch, src.bo, sx, sy, + src.surface[0].stride, + dst.bo, dx, dy, dst.surface[0].stride, w, h, + dst.bpp); } fini_buf(&dst); diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c index 630b9be7..f105e295 100644 --- a/tests/kms_cursor_crc.c +++ b/tests/kms_cursor_crc.c @@ -385,9 +385,9 @@ static void cleanup_crtc(data_t *data) static void scratch_buf_init(data_t *data, int buffer) { data->igtbo[buffer].bo = data->drmibo[buffer]; - data->igtbo[buffer].stride = data->primary_fb[buffer].strides[0]; + data->igtbo[buffer].surface[0].stride = data->primary_fb[buffer].strides[0]; data->igtbo[buffer].tiling = data->primary_fb[buffer].modifier; - data->igtbo[buffer].size = data->primary_fb[buffer].size; + data->igtbo[buffer].surface[0].size = data->primary_fb[buffer].size; data->igtbo[buffer].bpp = data->primary_fb[buffer].plane_bpp[0]; } diff --git a/tests/kms_psr.c b/tests/kms_psr.c index 232c80aa..d9be87d9 100644 --- a/tests/kms_psr.c +++ b/tests/kms_psr.c @@ -153,9 +153,9 @@ static void scratch_buf_init(struct igt_buf *buf, drm_intel_bo *bo, memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = stride; + buf->surface[0].stride = stride; buf->tiling = I915_TILING_X; - buf->size = size; + buf->surface[0].size = size; buf->bpp = 32; } diff --git a/tests/perf.c b/tests/perf.c index f5dd6051..982277df 100644 --- a/tests/perf.c +++ b/tests/perf.c @@ -506,9 +506,9 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, memset(buf, 0, sizeof(*buf)); buf->bo = bo; - buf->stride = stride; + buf->surface[0].stride = stride; buf->tiling = I915_TILING_NONE; - buf->size = size; + buf->surface[0].size = size; buf->bpp = 32; } -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 03/10] lib/igt_buf: Extend igt_buf to include two color surfaces 2019-12-30 17:58 ` [igt-dev] [PATCH i-g-t v2 " Imre Deak @ 2019-12-31 8:40 ` Kahola, Mika 0 siblings, 0 replies; 33+ messages in thread From: Kahola, Mika @ 2019-12-31 8:40 UTC (permalink / raw) To: igt-dev@lists.freedesktop.org, Deak, Imre On Mon, 2019-12-30 at 19:58 +0200, Imre Deak wrote: > UV FBs have two color surfaces so extend the igt_buf struct > accordingly > to support blitting such FBs. > > The patch is produced with the coccinelle patch below. > > No functional changes. > > @@ > @@ > > struct igt_buf { > ... > - uint32_t stride; > ... > - uint32_t size; > + struct { > + uint32_t stride; > + uint32_t size; > + } surface[2]; > ... > }; > > @@ > struct igt_buf b; > @@ > > <... > ( > - b.stride > + b.surface[0].stride > > > > - b.size > + b.surface[0].size > ) > ...> > > @@ > struct igt_buf *b; > @@ > > <... > ( > - b->size > + b->surface[0].size > > > > - b->stride > + b->surface[0].stride > ) > ...> > > @@ > identifier I; > expression E1; > expression E2; > @@ > > ( > struct igt_buf I = { > - .size = E1, > - .stride = E2, > + .surface[0] = { > + .size = E1, > + .stride = E2, > + }, > }; > > > > struct igt_buf I = { > - .size = E1, > + .surface[0] = { > + .size = E1, > + }, > }; > > > > struct igt_buf I = { > - .stride = E1, > + .surface[0] = { > + .stride = E1, > + }, > }; > ) > > v2: > - Rebase on latest upstream. (Mika) > > Cc: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> > --- > lib/gpu_cmds.c | 4 +- > lib/igt_draw.c | 8 ++-- > lib/igt_fb.c | 4 +- > lib/intel_aux_pgtable.c | 5 ++- > lib/intel_batchbuffer.c | 8 ++-- > lib/intel_batchbuffer.h | 6 ++- > lib/rendercopy_gen4.c | 4 +- > lib/rendercopy_gen6.c | 4 +- > lib/rendercopy_gen7.c | 4 +- > lib/rendercopy_gen8.c | 4 +- > lib/rendercopy_gen9.c | 4 +- > lib/rendercopy_i830.c | 8 ++-- > lib/rendercopy_i915.c | 8 ++-- > lib/veboxcopy_gen12.c | 6 ++- > tests/i915/gem_concurrent_all.c | 10 +++-- > tests/i915/gem_gpgpu_fill.c | 4 +- > tests/i915/gem_media_fill.c | 4 +- > tests/i915/gem_media_vme.c | 6 +-- > tests/i915/gem_ppgtt.c | 8 ++-- > tests/i915/gem_read_read_speed.c | 10 +++-- > tests/i915/gem_render_copy.c | 35 +++++++++-------- > tests/i915/gem_render_copy_redux.c | 4 +- > tests/i915/gem_render_linear_blits.c | 24 +++++------ > tests/i915/gem_render_tiled_blits.c | 8 ++-- > tests/i915/gem_ring_sync_copy.c | 4 +- > tests/i915/gem_stress.c | 59 +++++++++++++++----------- > -- > tests/i915/i915_pm_sseu.c | 7 ++-- > tests/kms_big_fb.c | 10 +++-- > tests/kms_cursor_crc.c | 4 +- > tests/kms_psr.c | 4 +- > tests/perf.c | 4 +- > 31 files changed, 151 insertions(+), 131 deletions(-) > > diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c > index 8d270ee8..79412725 100644 > --- a/lib/gpu_cmds.c > +++ b/lib/gpu_cmds.c > @@ -119,7 +119,7 @@ gen7_fill_surface_state(struct intel_batchbuffer > *batch, > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > > ss->ss7.shader_chanel_select_r = 4; > ss->ss7.shader_chanel_select_g = 5; > @@ -422,7 +422,7 @@ gen8_fill_surface_state(struct intel_batchbuffer > *batch, > > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > > ss->ss7.shader_chanel_select_r = 4; > ss->ss7.shader_chanel_select_g = 5; > diff --git a/lib/igt_draw.c b/lib/igt_draw.c > index 7e0edec1..6950bc49 100644 > --- a/lib/igt_draw.c > +++ b/lib/igt_draw.c > @@ -603,14 +603,14 @@ static void draw_rect_render(int fd, struct > cmd_data *cmd_data, > igt_assert(dst); > > src_buf.bo = src; > - src_buf.stride = tmp.stride; > + src_buf.surface[0].stride = tmp.stride; > src_buf.tiling = I915_TILING_NONE; > - src_buf.size = tmp.size; > + src_buf.surface[0].size = tmp.size; > src_buf.bpp = tmp.bpp; > dst_buf.bo = dst; > - dst_buf.stride = buf->stride; > + dst_buf.surface[0].stride = buf->stride; > dst_buf.tiling = tiling; > - dst_buf.size = buf->size; > + dst_buf.surface[0].size = buf->size; > dst_buf.bpp = buf->bpp; > > batch = intel_batchbuffer_alloc(cmd_data->bufmgr, devid); > diff --git a/lib/igt_fb.c b/lib/igt_fb.c > index 0e1b8493..cc0fb373 100644 > --- a/lib/igt_fb.c > +++ b/lib/igt_fb.c > @@ -1977,9 +1977,9 @@ static void init_buf(struct fb_blit_upload > *blit, > buf->bo = gem_handle_to_libdrm_bo(blit->bufmgr, blit->fd, > name, fb->gem_handle); > buf->tiling = igt_fb_mod_to_tiling(fb->modifier); > - buf->stride = fb->strides[0]; > + buf->surface[0].stride = fb->strides[0]; > buf->bpp = fb->plane_bpp[0]; > - buf->size = fb->size; > + buf->surface[0].size = fb->size; > > if (is_ccs_modifier(fb->modifier)) { > igt_assert_eq(fb->strides[0] & 127, 0); > diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c > index dab83a9a..5addb2e2 100644 > --- a/lib/intel_aux_pgtable.c > +++ b/lib/intel_aux_pgtable.c > @@ -77,7 +77,8 @@ pgt_table_count(int address_bits, const struct > igt_buf **bufs, int buf_count) > /* Avoid double counting for overlapping aligned bufs. > */ > start = max(start, end); > > - end = ALIGN(buf->bo->offset64 + buf->size, 1UL << > address_bits); > + end = ALIGN(buf->bo->offset64 + buf->surface[0].size, > + 1UL << address_bits); > igt_assert(end >= start); > > count += (end - start) >> address_bits; > @@ -255,7 +256,7 @@ pgt_populate_entries_for_buf(struct pgtable *pgt, > uint64_t top_table) > { > uint64_t surface_addr = buf->bo->offset64; > - uint64_t surface_end = surface_addr + buf->size; > + uint64_t surface_end = surface_addr + buf->surface[0].size; > uint64_t aux_addr = buf->bo->offset64 + buf->ccs[0].offset; > uint64_t l1_flags = pgt_get_l1_flags(buf); > uint64_t lx_flags = pgt_get_lx_flags(); > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c > index 51aae4dc..3dc89024 100644 > --- a/lib/intel_batchbuffer.c > +++ b/lib/intel_batchbuffer.c > @@ -512,7 +512,7 @@ intel_copy_bo(struct intel_batchbuffer *batch, > */ > unsigned igt_buf_width(const struct igt_buf *buf) > { > - return buf->stride/(buf->bpp / 8); > + return buf->surface[0].stride/(buf->bpp / 8); > } > > /** > @@ -526,7 +526,7 @@ unsigned igt_buf_width(const struct igt_buf *buf) > */ > unsigned igt_buf_height(const struct igt_buf *buf) > { > - return buf->size/buf->stride; > + return buf->surface[0].size/buf->surface[0].stride; > } > > /* > @@ -785,8 +785,8 @@ void igt_blitter_fast_copy(struct > intel_batchbuffer *batch, > > igt_assert(src->bpp == dst->bpp); > > - src_pitch = fast_copy_pitch(src->stride, src->tiling); > - dst_pitch = fast_copy_pitch(dst->stride, src->tiling); > + src_pitch = fast_copy_pitch(src->surface[0].stride, src- > >tiling); > + dst_pitch = fast_copy_pitch(dst->surface[0].stride, src- > >tiling); > dword0 = fast_copy_dword0(src->tiling, dst->tiling); > dword1 = fast_copy_dword1(src->tiling, dst->tiling, dst->bpp); > > diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h > index 63d32188..69580839 100644 > --- a/lib/intel_batchbuffer.h > +++ b/lib/intel_batchbuffer.h > @@ -232,12 +232,14 @@ enum i915_compression { > */ > struct igt_buf { > drm_intel_bo *bo; > - uint32_t stride; > uint32_t tiling; > enum i915_compression compression; > uint32_t bpp; > uint32_t *data; > - uint32_t size; > + struct { > + uint32_t stride; > + uint32_t size; > + } surface[2]; > struct { > uint32_t offset; > uint32_t stride; > diff --git a/lib/rendercopy_gen4.c b/lib/rendercopy_gen4.c > index 42de77f9..d07b8e48 100644 > --- a/lib/rendercopy_gen4.c > +++ b/lib/rendercopy_gen4.c > @@ -142,7 +142,7 @@ gen4_bind_buf(struct intel_batchbuffer *batch, > uint32_t write_domain, read_domain; > int ret; > > - igt_assert_lte(buf->stride, 128*1024); > + igt_assert_lte(buf->surface[0].stride, 128*1024); > igt_assert_lte(igt_buf_width(buf), 8192); > igt_assert_lte(igt_buf_height(buf), 8192); > > @@ -176,7 +176,7 @@ gen4_bind_buf(struct intel_batchbuffer *batch, > > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; > ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; > > diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c > index 83c7d694..87034774 100644 > --- a/lib/rendercopy_gen6.c > +++ b/lib/rendercopy_gen6.c > @@ -79,7 +79,7 @@ gen6_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > uint32_t write_domain, read_domain; > int ret; > > - igt_assert_lte(buf->stride, 128*1024); > + igt_assert_lte(buf->surface[0].stride, 128*1024); > igt_assert_lte(igt_buf_width(buf), 8192); > igt_assert_lte(igt_buf_height(buf), 8192); > > @@ -113,7 +113,7 @@ gen6_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; > ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; > > diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c > index a3c8b7f3..b88b75e9 100644 > --- a/lib/rendercopy_gen7.c > +++ b/lib/rendercopy_gen7.c > @@ -65,7 +65,7 @@ gen7_bind_buf(struct intel_batchbuffer *batch, > uint32_t write_domain, read_domain; > int ret; > > - igt_assert_lte(buf->stride, 256*1024); > + igt_assert_lte(buf->surface[0].stride, 256*1024); > igt_assert_lte(igt_buf_width(buf), 16384); > igt_assert_lte(igt_buf_height(buf), 16384); > > @@ -92,7 +92,7 @@ gen7_bind_buf(struct intel_batchbuffer *batch, > ss[1] = buf->bo->offset; > ss[2] = ((igt_buf_width(buf) - 1) << GEN7_SURFACE_WIDTH_SHIFT > | > (igt_buf_height(buf) - 1) << > GEN7_SURFACE_HEIGHT_SHIFT); > - ss[3] = (buf->stride - 1) << GEN7_SURFACE_PITCH_SHIFT; > + ss[3] = (buf->surface[0].stride - 1) << > GEN7_SURFACE_PITCH_SHIFT; > ss[4] = 0; > if (IS_VALLEYVIEW(batch->devid)) > ss[5] = VLV_MOCS_L3 << 16; > diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c > index e22d8501..8e02d846 100644 > --- a/lib/rendercopy_gen8.c > +++ b/lib/rendercopy_gen8.c > @@ -151,7 +151,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > uint32_t write_domain, read_domain, offset; > int ret; > > - igt_assert_lte(buf->stride, 256*1024); > + igt_assert_lte(buf->surface[0].stride, 256*1024); > igt_assert_lte(igt_buf_width(buf), 16384); > igt_assert_lte(igt_buf_height(buf), 16384); > > @@ -199,7 +199,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > > ss->ss7.shader_chanel_select_r = 4; > ss->ss7.shader_chanel_select_g = 5; > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c > index 4d4541e3..835c8d80 100644 > --- a/lib/rendercopy_gen9.c > +++ b/lib/rendercopy_gen9.c > @@ -199,7 +199,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > uint32_t write_domain, read_domain, offset; > int ret; > > - igt_assert_lte(buf->stride, 256*1024); > + igt_assert_lte(buf->surface[0].stride, 256*1024); > igt_assert_lte(igt_buf_width(buf), 16384); > igt_assert_lte(igt_buf_height(buf), 16384); > > @@ -250,7 +250,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, > const struct igt_buf *buf, > > ss->ss2.height = igt_buf_height(buf) - 1; > ss->ss2.width = igt_buf_width(buf) - 1; > - ss->ss3.pitch = buf->stride - 1; > + ss->ss3.pitch = buf->surface[0].stride - 1; > > ss->ss7.skl.shader_chanel_select_r = 4; > ss->ss7.skl.shader_chanel_select_g = 5; > diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c > index e8c04718..ca815122 100644 > --- a/lib/rendercopy_i830.c > +++ b/lib/rendercopy_i830.c > @@ -138,7 +138,7 @@ static void gen2_emit_target(struct > intel_batchbuffer *batch, > uint32_t tiling; > uint32_t format; > > - igt_assert_lte(dst->stride, 8192); > + igt_assert_lte(dst->surface[0].stride, 8192); > igt_assert_lte(igt_buf_width(dst), 2048); > igt_assert_lte(igt_buf_height(dst), 2048); > > @@ -156,7 +156,7 @@ static void gen2_emit_target(struct > intel_batchbuffer *batch, > tiling |= BUF_3D_TILE_WALK_Y; > > OUT_BATCH(_3DSTATE_BUF_INFO_CMD); > - OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst- > >stride)); > + OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst- > >surface[0].stride)); > OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, > I915_GEM_DOMAIN_RENDER, 0); > > OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); > @@ -179,7 +179,7 @@ static void gen2_emit_texture(struct > intel_batchbuffer *batch, > uint32_t tiling; > uint32_t format; > > - igt_assert_lte(src->stride, 8192); > + igt_assert_lte(src->surface[0].stride, 8192); > igt_assert_lte(igt_buf_width(src), 2048); > igt_assert_lte(igt_buf_height(src), 2048); > > @@ -201,7 +201,7 @@ static void gen2_emit_texture(struct > intel_batchbuffer *batch, > OUT_BATCH((igt_buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT | > (igt_buf_width(src) - 1) << TM0S1_WIDTH_SHIFT | > format | tiling); > - OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | > TM0S2_MAP_2D); > + OUT_BATCH((src->surface[0].stride / 4 - 1) << TM0S2_PITCH_SHIFT > | TM0S2_MAP_2D); > OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT | > FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT | > MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT); > diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c > index 1baa7a1b..56e1863e 100644 > --- a/lib/rendercopy_i915.c > +++ b/lib/rendercopy_i915.c > @@ -88,7 +88,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer > *batch, > #define TEX_COUNT 1 > uint32_t format_bits, tiling_bits = 0; > > - igt_assert_lte(src->stride, 8192); > + igt_assert_lte(src->surface[0].stride, 8192); > igt_assert_lte(igt_buf_width(src), 2048); > igt_assert_lte(igt_buf_height(src), 2048); > > @@ -110,7 +110,7 @@ void gen3_render_copyfunc(struct > intel_batchbuffer *batch, > OUT_BATCH(format_bits | tiling_bits | > (igt_buf_height(src) - 1) << MS3_HEIGHT_SHIFT > | > (igt_buf_width(src) - 1) << MS3_WIDTH_SHIFT); > - OUT_BATCH((src->stride/4-1) << MS4_PITCH_SHIFT); > + OUT_BATCH((src->surface[0].stride/4-1) << > MS4_PITCH_SHIFT); > > OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT)); > OUT_BATCH((1 << TEX_COUNT) - 1); > @@ -128,7 +128,7 @@ void gen3_render_copyfunc(struct > intel_batchbuffer *batch, > uint32_t tiling_bits = 0; > uint32_t format_bits; > > - igt_assert_lte(dst->stride, 8192); > + igt_assert_lte(dst->surface[0].stride, 8192); > igt_assert_lte(igt_buf_width(dst), 2048); > igt_assert_lte(igt_buf_height(dst), 2048); > > @@ -146,7 +146,7 @@ void gen3_render_copyfunc(struct > intel_batchbuffer *batch, > > OUT_BATCH(_3DSTATE_BUF_INFO_CMD); > OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits | > - BUF_3D_PITCH(dst->stride)); > + BUF_3D_PITCH(dst->surface[0].stride)); > OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, > I915_GEM_DOMAIN_RENDER, 0); > > OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); > diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c > index 87800941..2f017514 100644 > --- a/lib/veboxcopy_gen12.c > +++ b/lib/veboxcopy_gen12.c > @@ -248,12 +248,14 @@ void gen12_vebox_copyfunc(struct > intel_batchbuffer *batch, > /* TODO: add support for more formats */ > igt_assert(src->bpp == 32); > emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT, > - width, height, src->bpp, src->stride, > + width, height, src->bpp, > + src->surface[0].stride, > src->tiling, R8G8B8A8_UNORM); > > igt_assert(dst->bpp == 32); > emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT, > - width, height, dst->bpp, dst->stride, > + width, height, dst->bpp, > + dst->surface[0].stride, > dst->tiling, R8G8B8A8_UNORM); > > emit_tiling_convert_cmd(batch, > diff --git a/tests/i915/gem_concurrent_all.c > b/tests/i915/gem_concurrent_all.c > index 6486bebf..f1be4a85 100644 > --- a/tests/i915/gem_concurrent_all.c > +++ b/tests/i915/gem_concurrent_all.c > @@ -851,15 +851,17 @@ static void render_copy_bo(struct buffers *b, > drm_intel_bo *dst, drm_intel_bo *s > { > struct igt_buf d = { > .bo = dst, > - .size = b->npixels * 4, > .num_tiles = b->npixels * 4, > - .stride = b->width * 4, > + .surface[0] = { > + .size = b->npixels * 4, .stride = b->width * 4, > + }, > .bpp = 32, > }, s = { > .bo = src, > - .size = b->npixels * 4, > .num_tiles = b->npixels * 4, > - .stride = b->width * 4, > + .surface[0] = { > + .size = b->npixels * 4, .stride = b->width * 4, > + }, > .bpp = 32, > }; > uint32_t swizzle; > diff --git a/tests/i915/gem_gpgpu_fill.c > b/tests/i915/gem_gpgpu_fill.c > index 68918c3e..b2d401d6 100644 > --- a/tests/i915/gem_gpgpu_fill.c > +++ b/tests/i915/gem_gpgpu_fill.c > @@ -75,9 +75,9 @@ static void scratch_buf_init(data_t *data, struct > igt_buf *buf, > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = stride; > + buf->surface[0].stride = stride; > buf->tiling = I915_TILING_NONE; > - buf->size = SIZE; > + buf->surface[0].size = SIZE; > buf->bpp = 32; > } > > diff --git a/tests/i915/gem_media_fill.c > b/tests/i915/gem_media_fill.c > index a7d7708c..c880bae9 100644 > --- a/tests/i915/gem_media_fill.c > +++ b/tests/i915/gem_media_fill.c > @@ -78,9 +78,9 @@ static void scratch_buf_init(data_t *data, struct > igt_buf *buf, > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = stride; > + buf->surface[0].stride = stride; > buf->tiling = I915_TILING_NONE; > - buf->size = SIZE; > + buf->surface[0].size = SIZE; > buf->bpp = 32; > } > > diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c > index d5045ad1..20f5ca35 100644 > --- a/tests/i915/gem_media_vme.c > +++ b/tests/i915/gem_media_vme.c > @@ -58,7 +58,7 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, > > buf->bo = bo; > buf->tiling = I915_TILING_NONE; > - buf->size = size; > + buf->surface[0].size = size; > } > > static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct > igt_buf *buf) > @@ -71,14 +71,14 @@ static void scratch_buf_init_src(drm_intel_bufmgr > *bufmgr, struct igt_buf *buf) > * with this vme kernel. > */ > > - buf->stride = STRIDE; > + buf->surface[0].stride = STRIDE; > } > > static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct > igt_buf *buf) > { > scratch_buf_init(bufmgr, buf, OUTPUT_SIZE); > > - buf->stride = 1; > + buf->surface[0].stride = 1; > } > > static uint64_t switch_off_n_bits(uint64_t mask, unsigned int n) > diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c > index 89cdc4db..4c7d3ba2 100644 > --- a/tests/i915/gem_ppgtt.c > +++ b/tests/i915/gem_ppgtt.c > @@ -73,9 +73,9 @@ static void scratch_buf_init(struct igt_buf *buf, > memset(buf, 0, sizeof(*buf)); > > buf->bo = create_bo(bufmgr, pixel); > - buf->stride = STRIDE; > + buf->surface[0].stride = STRIDE; > buf->tiling = I915_TILING_NONE; > - buf->size = SIZE; > + buf->surface[0].size = SIZE; > buf->bpp = 32; > } > > @@ -140,9 +140,9 @@ static void fork_rcs_copy(int timeout, uint32_t > final, > } > > buf.bo = dst[child]; > - buf.stride = STRIDE; > + buf.surface[0].stride = STRIDE; > buf.tiling = I915_TILING_NONE; > - buf.size = SIZE; > + buf.surface[0].size = SIZE; > buf.bpp = 32; > > i = 0; > diff --git a/tests/i915/gem_read_read_speed.c > b/tests/i915/gem_read_read_speed.c > index 8b5ba8f7..2aab2204 100644 > --- a/tests/i915/gem_read_read_speed.c > +++ b/tests/i915/gem_read_read_speed.c > @@ -53,15 +53,17 @@ static drm_intel_bo *rcs_copy_bo(drm_intel_bo > *dst, drm_intel_bo *src) > { > struct igt_buf d = { > .bo = dst, > - .size = width * height * 4, > .num_tiles = width * height * 4, > - .stride = width * 4, > + .surface[0] = { > + .size = width * height * 4, .stride = width * > 4, > + }, > .bpp = 32, > }, s = { > .bo = src, > - .size = width * height * 4, > .num_tiles = width * height * 4, > - .stride = width * 4, > + .surface[0] = { > + .size = width * height * 4, .stride = width * > 4, > + }, > .bpp = 32, > }; > uint32_t swizzle; > diff --git a/tests/i915/gem_render_copy.c > b/tests/i915/gem_render_copy.c > index df0d045e..5abb2036 100644 > --- a/tests/i915/gem_render_copy.c > +++ b/tests/i915/gem_render_copy.c > @@ -118,7 +118,8 @@ static void copy_linear_to_yf(data_t *data, > struct igt_buf *buf, > for (int y = 0; y < height; y++) { > for (int x = 0; x < width; x++) { > uint32_t *ptr = yf_ptr(map, x, y, > - buf->stride, buf->bpp / > 8); > + buf->surface[0].stride, > + buf->bpp / 8); > > *ptr = linear[y * width + x]; > } > @@ -142,7 +143,8 @@ static void copy_yf_to_linear(data_t *data, > struct igt_buf *buf, > for (int y = 0; y < height; y++) { > for (int x = 0; x < width; x++) { > uint32_t *ptr = yf_ptr(map, x, y, > - buf->stride, buf->bpp / > 8); > + buf->surface[0].stride, > + buf->bpp / 8); > > linear[y * width + x] = *ptr; > } > @@ -231,7 +233,7 @@ static void scratch_buf_write_to_png(data_t > *data, struct igt_buf *buf, > CAIRO_FORMAT_RGB2 > 4, > igt_buf_width(buf > ), > igt_buf_height(bu > f), > - buf->stride); > + buf- > >surface[0].stride); > ret = cairo_surface_write_to_png(surface, > make_filename(filename)); > igt_assert(ret == CAIRO_STATUS_SUCCESS); > cairo_surface_destroy(surface); > @@ -324,7 +326,7 @@ static void scratch_buf_draw_pattern(data_t > *data, struct igt_buf *buf, > CAIRO_FORMAT_RGB2 > 4, > igt_buf_width(buf > ), > igt_buf_height(bu > f), > - buf->stride); > + buf- > >surface[0].stride); > > cr = cairo_create(surface); > > @@ -403,7 +405,7 @@ scratch_buf_copy(data_t *data, > for (int y = 0; y < h; y++) { > for (int x = 0; x < w; x++) { > const uint32_t *ptr = yf_ptr(map, sx+x, > sy+y, > - src- > >stride, > + src- > >surface[0].stride, > src->bpp / > 8); > > linear_dst[(dy+y) * width + dx+x] = > *ptr; > @@ -458,14 +460,14 @@ static void scratch_buf_init(data_t *data, > struct igt_buf *buf, > * turn mapped by one L1 AUX page table entry. > */ > if (intel_gen(data->devid) >= 12) > - buf->stride = ALIGN(width * (bpp / 8), 128 * > 4); > + buf->surface[0].stride = ALIGN(width * (bpp / > 8), 128 * 4); > else > - buf->stride = ALIGN(width * (bpp / 8), 128); > + buf->surface[0].stride = ALIGN(width * (bpp / > 8), 128); > > if (intel_gen(data->devid) >= 12) > height = ALIGN(height, 4 * 32); > > - buf->size = buf->stride * height; > + buf->surface[0].size = buf->surface[0].stride * height; > buf->tiling = tiling; > buf->bpp = bpp; > > @@ -473,7 +475,7 @@ static void scratch_buf_init(data_t *data, struct > igt_buf *buf, > aux_height = scratch_buf_aux_height(data->devid, buf); > > buf->compression = compression; > - buf->ccs[0].offset = buf->stride * ALIGN(height, 32); > + buf->ccs[0].offset = buf->surface[0].stride * > ALIGN(height, 32); > buf->ccs[0].stride = aux_width; > > size = buf->ccs[0].offset + aux_width * aux_height; > @@ -481,18 +483,19 @@ static void scratch_buf_init(data_t *data, > struct igt_buf *buf, > buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, > 4096); > > if (tiling == I915_TILING_Y) { > - drm_intel_bo_set_tiling(buf->bo, &tiling, buf- > >stride); > + drm_intel_bo_set_tiling(buf->bo, &tiling, > + buf- > >surface[0].stride); > igt_assert_eq(tiling, req_tiling); > } > } else if (req_tiling == I915_TILING_Yf) { > int size; > > - buf->stride = ALIGN(width * (bpp / 8), 128); > - buf->size = buf->stride * height; > + buf->surface[0].stride = ALIGN(width * (bpp / 8), 128); > + buf->surface[0].size = buf->surface[0].stride * height; > buf->tiling = tiling; > buf->bpp = bpp; > > - size = buf->stride * ALIGN(height, 32); > + size = buf->surface[0].stride * ALIGN(height, 32); > > buf->bo = drm_intel_bo_alloc(data->bufmgr, "", size, > 4096); > } else { > @@ -501,9 +504,9 @@ static void scratch_buf_init(data_t *data, struct > igt_buf *buf, > &tiling, &pitch, 0); > igt_assert_eq(tiling, req_tiling); > > - buf->stride = pitch; > + buf->surface[0].stride = pitch; > buf->tiling = tiling; > - buf->size = pitch * height; > + buf->surface[0].size = pitch * height; > buf->bpp = bpp; > } > > @@ -806,7 +809,7 @@ static void test(data_t *data, uint32_t > src_tiling, uint32_t dst_tiling, > 0, 0, > igt_buf_width(&dst), > igt_buf_height(&dst), > AUB_DUMP_BMP_FORMAT_ARGB_ > 8888, > - dst.stride, 0); > + dst.surface[0].stride, > 0); > drm_intel_bufmgr_gem_set_aub_dump(data->bufmgr, false); > } else if (check_all_pixels) { > scratch_buf_check_all(data, &dst, &ref); > diff --git a/tests/i915/gem_render_copy_redux.c > b/tests/i915/gem_render_copy_redux.c > index ef601c22..2388fc24 100644 > --- a/tests/i915/gem_render_copy_redux.c > +++ b/tests/i915/gem_render_copy_redux.c > @@ -106,9 +106,9 @@ static void scratch_buf_init(data_t *data, struct > igt_buf *buf, > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = stride; > + buf->surface[0].stride = stride; > buf->tiling = I915_TILING_NONE; > - buf->size = SIZE; > + buf->surface[0].size = SIZE; > buf->bpp = 32; > } > > diff --git a/tests/i915/gem_render_linear_blits.c > b/tests/i915/gem_render_linear_blits.c > index a726652b..666a43cd 100644 > --- a/tests/i915/gem_render_linear_blits.c > +++ b/tests/i915/gem_render_linear_blits.c > @@ -108,15 +108,15 @@ static void run_test (int fd, int count) > struct igt_buf src = {}, dst = {}; > > src.bo = bo[i % count]; > - src.stride = STRIDE; > + src.surface[0].stride = STRIDE; > src.tiling = I915_TILING_NONE; > - src.size = SIZE; > + src.surface[0].size = SIZE; > src.bpp = 32; > > dst.bo = bo[(i + 1) % count]; > - dst.stride = STRIDE; > + dst.surface[0].stride = STRIDE; > dst.tiling = I915_TILING_NONE; > - dst.size = SIZE; > + dst.surface[0].size = SIZE; > dst.bpp = 32; > > render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, > &dst, 0, 0); > @@ -133,15 +133,15 @@ static void run_test (int fd, int count) > struct igt_buf src = {}, dst = {}; > > src.bo = bo[(i + 1) % count]; > - src.stride = STRIDE; > + src.surface[0].stride = STRIDE; > src.tiling = I915_TILING_NONE; > - src.size = SIZE; > + src.surface[0].size = SIZE; > src.bpp = 32; > > dst.bo = bo[i % count]; > - dst.stride = STRIDE; > + dst.surface[0].stride = STRIDE; > dst.tiling = I915_TILING_NONE; > - dst.size = SIZE; > + dst.surface[0].size = SIZE; > dst.bpp = 32; > > render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, > &dst, 0, 0); > @@ -160,15 +160,15 @@ static void run_test (int fd, int count) > continue; > > src.bo = bo[s]; > - src.stride = STRIDE; > + src.surface[0].stride = STRIDE; > src.tiling = I915_TILING_NONE; > - src.size = SIZE; > + src.surface[0].size = SIZE; > src.bpp = 32; > > dst.bo = bo[d]; > - dst.stride = STRIDE; > + dst.surface[0].stride = STRIDE; > dst.tiling = I915_TILING_NONE; > - dst.size = SIZE; > + dst.surface[0].size = SIZE; > dst.bpp = 32; > > render_copy(batch, NULL, &src, 0, 0, WIDTH, HEIGHT, > &dst, 0, 0); > diff --git a/tests/i915/gem_render_tiled_blits.c > b/tests/i915/gem_render_tiled_blits.c > index 14018329..1de1b72c 100644 > --- a/tests/i915/gem_render_tiled_blits.c > +++ b/tests/i915/gem_render_tiled_blits.c > @@ -66,9 +66,9 @@ check_bo(struct intel_batchbuffer *batch, struct > igt_buf *buf, uint32_t val) > int i; > > tmp.bo = linear; > - tmp.stride = STRIDE; > + tmp.surface[0].stride = STRIDE; > tmp.tiling = I915_TILING_NONE; > - tmp.size = SIZE; > + tmp.surface[0].size = SIZE; > tmp.bpp = 32; > > render_copy(batch, NULL, buf, 0, 0, WIDTH, HEIGHT, &tmp, 0, 0); > @@ -132,9 +132,9 @@ static void run_test (int fd, int count) > buf[i].bo = drm_intel_bo_alloc_tiled(bufmgr, "", > WIDTH, HEIGHT, 4, > &tiling, &pitch, > 0); > - buf[i].stride = pitch; > + buf[i].surface[0].stride = pitch; > buf[i].tiling = tiling; > - buf[i].size = SIZE; > + buf[i].surface[0].size = SIZE; > buf[i].bpp = 32; > > start_val[i] = start; > diff --git a/tests/i915/gem_ring_sync_copy.c > b/tests/i915/gem_ring_sync_copy.c > index 1e5728bc..ddf5f750 100644 > --- a/tests/i915/gem_ring_sync_copy.c > +++ b/tests/i915/gem_ring_sync_copy.c > @@ -134,9 +134,9 @@ static void scratch_buf_init_from_bo(struct > igt_buf *buf, drm_intel_bo *bo) > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = 4 * WIDTH; > + buf->surface[0].stride = 4 * WIDTH; > buf->tiling = I915_TILING_NONE; > - buf->size = 4 * WIDTH * HEIGHT; > + buf->surface[0].size = 4 * WIDTH * HEIGHT; > buf->bpp = 32; > } > > diff --git a/tests/i915/gem_stress.c b/tests/i915/gem_stress.c > index 57e2909c..50245b93 100644 > --- a/tests/i915/gem_stress.c > +++ b/tests/i915/gem_stress.c > @@ -155,8 +155,8 @@ struct { > static void tile2xy(struct igt_buf *buf, unsigned tile, unsigned *x, > unsigned *y) > { > igt_assert(tile < buf->num_tiles); > - *x = (tile*options.tile_size) % (buf->stride/sizeof(uint32_t)); > - *y = ((tile*options.tile_size) / (buf- > >stride/sizeof(uint32_t))) * options.tile_size; > + *x = (tile*options.tile_size) % (buf- > >surface[0].stride/sizeof(uint32_t)); > + *y = ((tile*options.tile_size) / (buf- > >surface[0].stride/sizeof(uint32_t))) * options.tile_size; > } > > static void emit_blt(drm_intel_bo *src_bo, uint32_t src_tiling, > unsigned src_pitch, > @@ -268,8 +268,10 @@ static void cpu_copyfunc(struct igt_buf *src, > unsigned src_x, unsigned src_y, > set_to_cpu_domain(dst, 1); > } > > - cpucpy2d(src->data, src->stride/sizeof(uint32_t), src_x, src_y, > - dst->data, dst->stride/sizeof(uint32_t), dst_x, dst_y, > + cpucpy2d(src->data, src->surface[0].stride/sizeof(uint32_t), > src_x, > + src_y, > + dst->data, dst->surface[0].stride/sizeof(uint32_t), > dst_x, > + dst_y, > logical_tile_no); > } > > @@ -287,7 +289,7 @@ static void prw_copyfunc(struct igt_buf *src, > unsigned src_x, unsigned src_y, > > if (src->tiling == I915_TILING_NONE) { > for (i = 0; i < options.tile_size; i++) { > - unsigned ofs = src_x*sizeof(uint32_t) + src- > >stride*(src_y + i); > + unsigned ofs = src_x*sizeof(uint32_t) + src- > >surface[0].stride*(src_y + i); > drm_intel_bo_get_subdata(src->bo, ofs, > options.tile_size*size > of(uint32_t), > tmp_tile + > options.tile_size*i); > @@ -296,13 +298,14 @@ static void prw_copyfunc(struct igt_buf *src, > unsigned src_x, unsigned src_y, > if (options.use_cpu_maps) > set_to_cpu_domain(src, 0); > > - cpucpy2d(src->data, src->stride/sizeof(uint32_t), > src_x, src_y, > + cpucpy2d(src->data, src- > >surface[0].stride/sizeof(uint32_t), > + src_x, src_y, > tmp_tile, options.tile_size, 0, 0, > logical_tile_no); > } > > if (dst->tiling == I915_TILING_NONE) { > for (i = 0; i < options.tile_size; i++) { > - unsigned ofs = dst_x*sizeof(uint32_t) + dst- > >stride*(dst_y + i); > + unsigned ofs = dst_x*sizeof(uint32_t) + dst- > >surface[0].stride*(dst_y + i); > drm_intel_bo_subdata(dst->bo, ofs, > options.tile_size*sizeof(u > int32_t), > tmp_tile + > options.tile_size*i); > @@ -312,7 +315,8 @@ static void prw_copyfunc(struct igt_buf *src, > unsigned src_x, unsigned src_y, > set_to_cpu_domain(dst, 1); > > cpucpy2d(tmp_tile, options.tile_size, 0, 0, > - dst->data, dst->stride/sizeof(uint32_t), > dst_x, dst_y, > + dst->data, dst- > >surface[0].stride/sizeof(uint32_t), > + dst_x, dst_y, > logical_tile_no); > } > } > @@ -327,9 +331,9 @@ static void blitter_copyfunc(struct igt_buf *src, > unsigned src_x, unsigned src_y > if (keep_gpu_busy_counter & 1 && !fence_storm) > keep_gpu_busy(); > > - emit_blt(src->bo, src->tiling, src->stride, src_x, src_y, > + emit_blt(src->bo, src->tiling, src->surface[0].stride, src_x, > src_y, > options.tile_size, options.tile_size, > - dst->bo, dst->tiling, dst->stride, dst_x, dst_y); > + dst->bo, dst->tiling, dst->surface[0].stride, dst_x, > dst_y); > > if (!(keep_gpu_busy_counter & 1) && !fence_storm) > keep_gpu_busy(); > @@ -441,7 +445,7 @@ static void fan_out(void) > > cpucpy2d(tmp_tile, options.tile_size, 0, 0, > buffers[current_set][buf_idx].data, > - buffers[current_set][buf_idx].stride / > sizeof(uint32_t), > + buffers[current_set][buf_idx].surface[0].strid > e / sizeof(uint32_t), > x, y, i); > } > > @@ -465,7 +469,7 @@ static void fan_in_and_check(void) > set_to_cpu_domain(&buffers[current_set][buf_idx > ], 0); > > cpucpy2d(buffers[current_set][buf_idx].data, > - buffers[current_set][buf_idx].stride / > sizeof(uint32_t), > + buffers[current_set][buf_idx].surface[0].strid > e / sizeof(uint32_t), > x, y, > tmp_tile, options.tile_size, 0, 0, > i); > @@ -476,15 +480,15 @@ static void sanitize_stride(struct igt_buf > *buf) > { > > if (igt_buf_height(buf) > options.max_dimension) > - buf->stride = buf->size / options.max_dimension; > + buf->surface[0].stride = buf->surface[0].size / > options.max_dimension; > > if (igt_buf_height(buf) < options.tile_size) > - buf->stride = buf->size / options.tile_size; > + buf->surface[0].stride = buf->surface[0].size / > options.tile_size; > > if (igt_buf_width(buf) < options.tile_size) > - buf->stride = options.tile_size * sizeof(uint32_t); > + buf->surface[0].stride = options.tile_size * > sizeof(uint32_t); > > - igt_assert(buf->stride <= 8192); > + igt_assert(buf->surface[0].stride <= 8192); > igt_assert(igt_buf_width(buf) <= options.max_dimension); > igt_assert(igt_buf_height(buf) <= options.max_dimension); > > @@ -498,10 +502,10 @@ static void init_buffer(struct igt_buf *buf, > unsigned size) > memset(buf, 0, sizeof(*buf)); > > buf->bo = drm_intel_bo_alloc(bufmgr, "tiled bo", size, 4096); > - buf->size = size; > + buf->surface[0].size = size; > igt_assert(buf->bo); > buf->tiling = I915_TILING_NONE; > - buf->stride = 4096; > + buf->surface[0].stride = 4096; > buf->bpp = 32; > > sanitize_stride(buf); > @@ -560,25 +564,26 @@ static void init_set(unsigned set) > if (buffers[set][i].tiling == I915_TILING_NONE) { > /* min 64 byte stride */ > r %= 8; > - buffers[set][i].stride = 64 * (1 << r); > + buffers[set][i].surface[0].stride = 64 * (1 << > r); > } else if (IS_GEN2(devid)) { > /* min 128 byte stride */ > r %= 7; > - buffers[set][i].stride = 128 * (1 << r); > + buffers[set][i].surface[0].stride = 128 * (1 << > r); > } else { > /* min 512 byte stride */ > r %= 5; > - buffers[set][i].stride = 512 * (1 << r); > + buffers[set][i].surface[0].stride = 512 * (1 << > r); > } > > sanitize_stride(&buffers[set][i]); > > gem_set_tiling(drm_fd, buffers[set][i].bo->handle, > buffers[set][i].tiling, > - buffers[set][i].stride); > + buffers[set][i].surface[0].stride); > > if (options.trace_tile != -1 && i == > options.trace_tile/options.tiles_per_buf) > - igt_info("changing buffer %i containing tile > %i: tiling %i, stride %i\n", i, options.trace_tile, > buffers[set][i].tiling, buffers[set][i].stride); > + igt_info("changing buffer %i containing tile > %i: tiling %i, stride %i\n", i, options.trace_tile, > buffers[set][i].tiling, > + buffers[set][i].surface[0].stride); > } > } > > @@ -616,10 +621,10 @@ static void copy_tiles(unsigned *permutation) > > if (options.no_hw) { > cpucpy2d(src_buf->data, > - src_buf->stride / sizeof(uint32_t), > + src_buf->surface[0].stride / > sizeof(uint32_t), > src_x, src_y, > dst_buf->data, > - dst_buf->stride / sizeof(uint32_t), > + dst_buf->surface[0].stride / > sizeof(uint32_t), > dst_x, dst_y, > i); > } else { > @@ -808,7 +813,7 @@ static void check_render_copyfunc(void) > > memset(src.data, 0xff, options.scratch_buf_size); > for (j = 0; j < options.tile_size; j++) { > - ptr = (uint32_t*)((char *)src.data + sx*4 + > (sy+j) * src.stride); > + ptr = (uint32_t*)((char *)src.data + sx*4 + > (sy+j) * src.surface[0].stride); > for (i = 0; i < options.tile_size; i++) > ptr[i] = j * options.tile_size + i; > } > @@ -819,7 +824,7 @@ static void check_render_copyfunc(void) > set_to_cpu_domain(&dst, 0); > > for (j = 0; j < options.tile_size; j++) { > - ptr = (uint32_t*)((char *)dst.data + dx*4 + > (dy+j) * dst.stride); > + ptr = (uint32_t*)((char *)dst.data + dx*4 + > (dy+j) * dst.surface[0].stride); > for (i = 0; i < options.tile_size; i++) > if (ptr[i] != j * options.tile_size + > i) { > igt_info("render copyfunc > mismatch at (%d, %d): found %d, expected %d\n", i, j, ptr[i], j * > options.tile_size + i); > diff --git a/tests/i915/i915_pm_sseu.c b/tests/i915/i915_pm_sseu.c > index e671e190..c2dee118 100644 > --- a/tests/i915/i915_pm_sseu.c > +++ b/tests/i915/i915_pm_sseu.c > @@ -299,10 +299,11 @@ gem_init(void) > igt_assert(gem.batch); > gem.init = 3; > > - gem.buf.stride = sizeof(uint32_t); > + gem.buf.surface[0].stride = sizeof(uint32_t); > gem.buf.tiling = I915_TILING_NONE; > - gem.buf.size = gem.buf.stride; > - gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", gem.buf.size, > 4096); > + gem.buf.surface[0].size = gem.buf.surface[0].stride; > + gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", > + gem.buf.surface[0].size, 4096); > gem.buf.bpp = 32; > igt_assert(gem.buf.bo); > gem.init = 4; > diff --git a/tests/kms_big_fb.c b/tests/kms_big_fb.c > index c5d002ca..eb144da9 100644 > --- a/tests/kms_big_fb.c > +++ b/tests/kms_big_fb.c > @@ -60,9 +60,9 @@ static void init_buf(data_t *data, > buf->bo = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, > name, fb->gem_handle); > buf->tiling = igt_fb_mod_to_tiling(fb->modifier); > - buf->stride = fb->strides[0]; > + buf->surface[0].stride = fb->strides[0]; > buf->bpp = fb->plane_bpp[0]; > - buf->size = fb->size; > + buf->surface[0].size = fb->size; > } > > static void fini_buf(struct igt_buf *buf) > @@ -99,8 +99,10 @@ static void copy_pattern(data_t *data, > h = min(h, src_fb->height - sy); > h = min(h, dst_fb->height - dy); > > - intel_blt_copy(data->batch, src.bo, sx, sy, src.stride, > - dst.bo, dx, dy, dst.stride, w, h, > dst.bpp); > + intel_blt_copy(data->batch, src.bo, sx, sy, > + src.surface[0].stride, > + dst.bo, dx, dy, dst.surface[0].stride, > w, h, > + dst.bpp); > } > > fini_buf(&dst); > diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c > index 630b9be7..f105e295 100644 > --- a/tests/kms_cursor_crc.c > +++ b/tests/kms_cursor_crc.c > @@ -385,9 +385,9 @@ static void cleanup_crtc(data_t *data) > static void scratch_buf_init(data_t *data, int buffer) > { > data->igtbo[buffer].bo = data->drmibo[buffer]; > - data->igtbo[buffer].stride = data- > >primary_fb[buffer].strides[0]; > + data->igtbo[buffer].surface[0].stride = data- > >primary_fb[buffer].strides[0]; > data->igtbo[buffer].tiling = data->primary_fb[buffer].modifier; > - data->igtbo[buffer].size = data->primary_fb[buffer].size; > + data->igtbo[buffer].surface[0].size = data- > >primary_fb[buffer].size; > data->igtbo[buffer].bpp = data- > >primary_fb[buffer].plane_bpp[0]; > } > > diff --git a/tests/kms_psr.c b/tests/kms_psr.c > index 232c80aa..d9be87d9 100644 > --- a/tests/kms_psr.c > +++ b/tests/kms_psr.c > @@ -153,9 +153,9 @@ static void scratch_buf_init(struct igt_buf *buf, > drm_intel_bo *bo, > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = stride; > + buf->surface[0].stride = stride; > buf->tiling = I915_TILING_X; > - buf->size = size; > + buf->surface[0].size = size; > buf->bpp = 32; > } > > diff --git a/tests/perf.c b/tests/perf.c > index f5dd6051..982277df 100644 > --- a/tests/perf.c > +++ b/tests/perf.c > @@ -506,9 +506,9 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, > memset(buf, 0, sizeof(*buf)); > > buf->bo = bo; > - buf->stride = stride; > + buf->surface[0].stride = stride; > buf->tiling = I915_TILING_NONE; > - buf->size = size; > + buf->surface[0].size = size; > buf->bpp = 32; > } > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t 04/10] lib: Add engine copy support for YUV formats 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (2 preceding siblings ...) 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 03/10] lib/igt_buf: Extend igt_buf to include two color surfaces Imre Deak @ 2019-12-30 3:40 ` Imre Deak 2019-12-30 13:23 ` Kahola, Mika 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 05/10] Revert "tests/kms_plane: Disable GEN12 media compression YUV tests" Imre Deak ` (11 subsequent siblings) 15 siblings, 1 reply; 33+ messages in thread From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw) To: igt-dev Add the missing bits to the Vebox copy and AUX pagetable helpers for copying YUV FBs with the Vebox engine. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- lib/igt_fb.c | 79 ++++++++++++++++++++++++-- lib/intel_aux_pgtable.c | 121 ++++++++++++++++++++++++++++++++++++---- lib/intel_batchbuffer.h | 4 ++ lib/veboxcopy_gen12.c | 58 ++++++++++++++++--- 4 files changed, 238 insertions(+), 24 deletions(-) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index cc0fb373..e6a3ff07 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -359,6 +359,13 @@ static const struct format_desc_struct *lookup_drm_format(uint32_t drm_format) return NULL; } +static bool igt_format_is_yuv_semiplanar(uint32_t format) +{ + const struct format_desc_struct *f = lookup_drm_format(format); + + return igt_format_is_yuv(format) && f->num_planes == 2; +} + /** * igt_get_fb_tile_size: * @fd: the DRM file descriptor @@ -1967,19 +1974,56 @@ static bool use_blitter(const struct igt_fb *fb) blitter_ok(fb); } +static void init_buf_ccs(struct igt_buf *buf, int ccs_idx, + uint32_t offset, uint32_t stride) +{ + buf->ccs[ccs_idx].offset = offset; + buf->ccs[ccs_idx].stride = stride; +} + +static void init_buf_surface(struct igt_buf *buf, int surface_idx, + uint32_t offset, uint32_t stride, uint32_t size) +{ + buf->surface[surface_idx].offset = offset; + buf->surface[surface_idx].stride = stride; + buf->surface[surface_idx].size = size; +} + +static int yuv_semiplanar_bpp(uint32_t drm_format) +{ + switch (drm_format) { + case DRM_FORMAT_NV12: + return 8; + case DRM_FORMAT_P010: + return 10; + case DRM_FORMAT_P012: + return 12; + case DRM_FORMAT_P016: + return 16; + default: + igt_assert_f(0, "Unsupported format: %08x\n", drm_format); + } +} + static void init_buf(struct fb_blit_upload *blit, struct igt_buf *buf, const struct igt_fb *fb, const char *name) { + int num_surfaces; + int i; + igt_assert_eq(fb->offsets[0], 0); buf->bo = gem_handle_to_libdrm_bo(blit->bufmgr, blit->fd, name, fb->gem_handle); buf->tiling = igt_fb_mod_to_tiling(fb->modifier); - buf->surface[0].stride = fb->strides[0]; buf->bpp = fb->plane_bpp[0]; - buf->surface[0].size = fb->size; + buf->format_is_yuv = igt_format_is_yuv(fb->drm_format); + buf->format_is_yuv_semiplanar = + igt_format_is_yuv_semiplanar(fb->drm_format); + if (buf->format_is_yuv_semiplanar) + buf->yuv_semiplanar_bpp = yuv_semiplanar_bpp(fb->drm_format); if (is_ccs_modifier(fb->modifier)) { igt_assert_eq(fb->strides[0] & 127, 0); @@ -1994,8 +2038,24 @@ static void init_buf(struct fb_blit_upload *blit, else buf->compression = I915_COMPRESSION_RENDER; - buf->ccs[0].offset = fb->offsets[1]; - buf->ccs[0].stride = fb->strides[1]; + num_surfaces = fb->num_planes / 2; + for (i = 0; i < num_surfaces; i++) + init_buf_ccs(buf, i, + fb->offsets[num_surfaces + i], + fb->strides[num_surfaces + i]); + } else { + num_surfaces = fb->num_planes; + } + + igt_assert(fb->offsets[0] == 0); + for (i = 0; i < num_surfaces; i++) { + uint32_t end = + i == fb->num_planes - 1 ? fb->size : fb->offsets[i + 1]; + + init_buf_surface(buf, i, + fb->offsets[i], + fb->strides[i], + end - fb->offsets[i]); } if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) @@ -2007,6 +2067,15 @@ static void fini_buf(struct igt_buf *buf) drm_intel_bo_unreference(buf->bo); } +static bool use_vebox_copy(const struct igt_fb *src_fb, + const struct igt_fb *dst_fb) +{ + + return is_gen12_mc_ccs_modifier(dst_fb->modifier) || + igt_format_is_yuv(src_fb->drm_format) || + igt_format_is_yuv(dst_fb->drm_format); +} + /** * copy_with_engine: * @blit: context for the copy operation @@ -2029,7 +2098,7 @@ static void copy_with_engine(struct fb_blit_upload *blit, igt_render_copyfunc_t render_copy = NULL; igt_vebox_copyfunc_t vebox_copy = NULL; - if (is_gen12_mc_ccs_modifier(dst_fb->modifier)) + if (use_vebox_copy(src_fb, dst_fb)) vebox_copy = igt_get_vebox_copyfunc(intel_get_drm_devid(blit->fd)); else render_copy = igt_get_render_copyfunc(intel_get_drm_devid(blit->fd)); diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index 5addb2e2..fcd24f08 100644 --- a/lib/intel_aux_pgtable.c +++ b/lib/intel_aux_pgtable.c @@ -33,6 +33,12 @@ #define max(a, b) ((a) > (b) ? (a) : (b)) +#define AUX_FORMAT_YCRCB 0x03 +#define AUX_FORMAT_P010 0x07 +#define AUX_FORMAT_P016 0x08 +#define AUX_FORMAT_ARGB_8B 0x0A +#define AUX_FORMAT_NV12_21 0x0F + struct pgtable_level_desc { int idx_shift; int idx_bits; @@ -55,6 +61,23 @@ struct pgtable { drm_intel_bo *bo; }; +static uint64_t last_buf_surface_end(const struct igt_buf *buf) +{ + uint64_t end_offset = 0; + int num_surfaces = buf->format_is_yuv_semiplanar ? 2 : 1; + int i; + + for (i = 0; i < num_surfaces; i++) { + uint64_t surface_end = buf->surface[i].offset + + buf->surface[i].size; + + if (surface_end > end_offset) + end_offset = surface_end; + } + + return end_offset; +} + static int pgt_table_count(int address_bits, const struct igt_buf **bufs, int buf_count) { @@ -77,7 +100,7 @@ pgt_table_count(int address_bits, const struct igt_buf **bufs, int buf_count) /* Avoid double counting for overlapping aligned bufs. */ start = max(start, end); - end = ALIGN(buf->bo->offset64 + buf->surface[0].size, + end = ALIGN(buf->bo->offset64 + last_buf_surface_end(buf), 1UL << address_bits); igt_assert(end >= start); @@ -189,7 +212,29 @@ pgt_set_l1_entry(struct pgtable *pgt, uint64_t l1_table, *l1_entry_ptr = ptr | flags; } -static uint64_t pgt_get_l1_flags(const struct igt_buf *buf) +#define DEPTH_VAL_RESERVED 3 + +static int bpp_to_depth_val(int bpp) +{ + switch (bpp) { + case 8: + return 4; + case 10: + return 1; + case 12: + return 2; + case 16: + return 0; + case 32: + return 5; + case 64: + return 6; + default: + igt_assert_f(0, "invalid bpp %d\n", bpp); + } +} + +static uint64_t pgt_get_l1_flags(const struct igt_buf *buf, int surface_idx) { /* * The offset of .tile_mode isn't specifed by bspec, it's what Mesa @@ -213,8 +258,6 @@ static uint64_t pgt_get_l1_flags(const struct igt_buf *buf) .e = { .valid = 1, .tile_mode = buf->tiling == I915_TILING_Y ? 1 : 0, - .depth = 5, /* 32bpp */ - .format = 0xA, /* B8G8R8A8_UNORM */ } }; @@ -227,7 +270,49 @@ static uint64_t pgt_get_l1_flags(const struct igt_buf *buf) buf->tiling == I915_TILING_Yf || buf->tiling == I915_TILING_Ys); - igt_assert(buf->bpp == 32); + entry.e.ycr = surface_idx > 0; + + if (buf->format_is_yuv_semiplanar) { + entry.e.depth = bpp_to_depth_val(buf->bpp); + switch (buf->yuv_semiplanar_bpp) { + case 8: + entry.e.format = AUX_FORMAT_NV12_21; + entry.e.depth = DEPTH_VAL_RESERVED; + break; + case 10: + entry.e.format = AUX_FORMAT_P010; + entry.e.depth = bpp_to_depth_val(10); + break; + case 12: + entry.e.format = AUX_FORMAT_P016; + entry.e.depth = bpp_to_depth_val(12); + break; + case 16: + entry.e.format = AUX_FORMAT_P016; + entry.e.depth = bpp_to_depth_val(16); + break; + default: + igt_assert(0); + } + } else if (buf->format_is_yuv) { + switch (buf->bpp) { + case 16: + entry.e.format = AUX_FORMAT_YCRCB; + entry.e.depth = DEPTH_VAL_RESERVED; + break; + default: + igt_assert(0); + } + } else { + switch (buf->bpp) { + case 32: + entry.e.format = AUX_FORMAT_ARGB_8B; + entry.e.depth = bpp_to_depth_val(32); + break; + default: + igt_assert(0); + } + } return entry.l; } @@ -253,14 +338,21 @@ static uint64_t pgt_get_lx_flags(void) static void pgt_populate_entries_for_buf(struct pgtable *pgt, const struct igt_buf *buf, - uint64_t top_table) + uint64_t top_table, + int surface_idx) { - uint64_t surface_addr = buf->bo->offset64; - uint64_t surface_end = surface_addr + buf->surface[0].size; - uint64_t aux_addr = buf->bo->offset64 + buf->ccs[0].offset; - uint64_t l1_flags = pgt_get_l1_flags(buf); + uint64_t surface_addr = buf->bo->offset64 + + buf->surface[surface_idx].offset; + uint64_t surface_end = surface_addr + + buf->surface[surface_idx].size; + uint64_t aux_addr = buf->bo->offset64 + buf->ccs[surface_idx].offset; + uint64_t l1_flags = pgt_get_l1_flags(buf, surface_idx); uint64_t lx_flags = pgt_get_lx_flags(); + igt_assert(!(buf->surface[surface_idx].stride % 512)); + igt_assert_eq(buf->ccs[surface_idx].stride, + buf->surface[surface_idx].stride / 512 * 64); + for (; surface_addr < surface_end; surface_addr += MAIN_SURFACE_BLOCK_SIZE, aux_addr += AUX_CCS_BLOCK_SIZE) { @@ -292,8 +384,13 @@ static void pgt_populate_entries(struct pgtable *pgt, /* Top level table must be at offset 0. */ igt_assert(top_table == 0); - for (i = 0; i < buf_count; i++) - pgt_populate_entries_for_buf(pgt, bufs[i], top_table); + for (i = 0; i < buf_count; i++) { + igt_assert_eq(bufs[i]->surface[0].offset, 0); + + pgt_populate_entries_for_buf(pgt, bufs[i], top_table, 0); + if (bufs[i]->format_is_yuv_semiplanar) + pgt_populate_entries_for_buf(pgt, bufs[i], top_table, 1); + } } static struct pgtable * diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index 69580839..fd7ef03f 100644 --- a/lib/intel_batchbuffer.h +++ b/lib/intel_batchbuffer.h @@ -235,8 +235,12 @@ struct igt_buf { uint32_t tiling; enum i915_compression compression; uint32_t bpp; + uint32_t yuv_semiplanar_bpp; uint32_t *data; + bool format_is_yuv:1; + bool format_is_yuv_semiplanar:1; struct { + uint32_t offset; uint32_t stride; uint32_t size; } surface[2]; diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c index 2f017514..237c43f2 100644 --- a/lib/veboxcopy_gen12.c +++ b/lib/veboxcopy_gen12.c @@ -26,7 +26,10 @@ #include "intel_aux_pgtable.h" #include "veboxcopy.h" +#define YCRCB_NORMAL 0 +#define PLANAR_420_8 4 #define R8G8B8A8_UNORM 8 +#define PLANAR_420_16 12 struct vebox_surface_state { struct { @@ -129,10 +132,23 @@ struct vebox_tiling_convert { }; } __attribute__((packed)); +static bool format_is_interleaved_yuv(int format) +{ + switch (format) { + case YCRCB_NORMAL: + case PLANAR_420_8: + case PLANAR_420_16: + return true; + } + + return false; +} + static void emit_surface_state_cmd(struct intel_batchbuffer *batch, int surface_id, int width, int height, int bpp, - int pitch, uint32_t tiling, int format) + int pitch, uint32_t tiling, int format, + uint32_t uv_offset) { struct vebox_surface_state *ss; @@ -149,11 +165,15 @@ static void emit_surface_state_cmd(struct intel_batchbuffer *batch, ss->ss2.width = width - 1; ss->ss3.surface_format = format; + if (format_is_interleaved_yuv(format)) + ss->ss3.chroma_interleave = 1; ss->ss3.surface_pitch = pitch - 1; ss->ss3.tile_walk = (tiling == I915_TILING_Y) || (tiling == I915_TILING_Yf); ss->ss3.tiled_surface = tiling != I915_TILING_NONE; + ss->ss4.u_y_offset = uv_offset / pitch; + ss->ss7.derived_surface_pitch = pitch - 1; } @@ -226,8 +246,7 @@ void gen12_vebox_copyfunc(struct intel_batchbuffer *batch, { struct aux_pgtable_info aux_pgtable_info = { }; uint32_t aux_pgtable_state; - - igt_assert(src->bpp == dst->bpp); + int format; intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX); @@ -245,18 +264,43 @@ void gen12_vebox_copyfunc(struct intel_batchbuffer *batch, gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, false); + /* The tiling convert command can't convert formats. */ + igt_assert_eq(src->format_is_yuv, dst->format_is_yuv); + igt_assert_eq(src->format_is_yuv_semiplanar, + dst->format_is_yuv_semiplanar); + igt_assert_eq(src->bpp, dst->bpp); + /* TODO: add support for more formats */ - igt_assert(src->bpp == 32); + switch (src->bpp) { + case 8: + igt_assert(src->format_is_yuv_semiplanar); + format = PLANAR_420_8; + break; + case 16: + igt_assert(src->format_is_yuv); + format = src->format_is_yuv_semiplanar ? PLANAR_420_16 : + YCRCB_NORMAL; + break; + case 32: + igt_assert(!src->format_is_yuv && + !src->format_is_yuv_semiplanar); + format = R8G8B8A8_UNORM; + break; + default: + igt_assert_f(0, "Unsupported bpp: %u\n", src->bpp); + } + + igt_assert(!src->format_is_yuv_semiplanar || + (src->surface[1].offset && dst->surface[1].offset)); emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT, width, height, src->bpp, src->surface[0].stride, - src->tiling, R8G8B8A8_UNORM); + src->tiling, format, src->surface[1].offset); - igt_assert(dst->bpp == 32); emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT, width, height, dst->bpp, dst->surface[0].stride, - dst->tiling, R8G8B8A8_UNORM); + dst->tiling, format, dst->surface[1].offset); emit_tiling_convert_cmd(batch, src->bo, src->tiling, src->compression, -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 04/10] lib: Add engine copy support for YUV formats 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 04/10] lib: Add engine copy support for YUV formats Imre Deak @ 2019-12-30 13:23 ` Kahola, Mika 0 siblings, 0 replies; 33+ messages in thread From: Kahola, Mika @ 2019-12-30 13:23 UTC (permalink / raw) To: igt-dev@lists.freedesktop.org, Deak, Imre On Mon, 2019-12-30 at 05:40 +0200, Imre Deak wrote: > Add the missing bits to the Vebox copy and AUX pagetable helpers for > copying YUV FBs with the Vebox engine. > > Cc: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> > --- > lib/igt_fb.c | 79 ++++++++++++++++++++++++-- > lib/intel_aux_pgtable.c | 121 ++++++++++++++++++++++++++++++++++++ > ---- > lib/intel_batchbuffer.h | 4 ++ > lib/veboxcopy_gen12.c | 58 ++++++++++++++++--- > 4 files changed, 238 insertions(+), 24 deletions(-) > > diff --git a/lib/igt_fb.c b/lib/igt_fb.c > index cc0fb373..e6a3ff07 100644 > --- a/lib/igt_fb.c > +++ b/lib/igt_fb.c > @@ -359,6 +359,13 @@ static const struct format_desc_struct > *lookup_drm_format(uint32_t drm_format) > return NULL; > } > > +static bool igt_format_is_yuv_semiplanar(uint32_t format) > +{ > + const struct format_desc_struct *f = lookup_drm_format(format); > + > + return igt_format_is_yuv(format) && f->num_planes == 2; > +} > + > /** > * igt_get_fb_tile_size: > * @fd: the DRM file descriptor > @@ -1967,19 +1974,56 @@ static bool use_blitter(const struct igt_fb > *fb) > blitter_ok(fb); > } > > +static void init_buf_ccs(struct igt_buf *buf, int ccs_idx, > + uint32_t offset, uint32_t stride) > +{ > + buf->ccs[ccs_idx].offset = offset; > + buf->ccs[ccs_idx].stride = stride; > +} > + > +static void init_buf_surface(struct igt_buf *buf, int surface_idx, > + uint32_t offset, uint32_t stride, uint32_t > size) > +{ > + buf->surface[surface_idx].offset = offset; > + buf->surface[surface_idx].stride = stride; > + buf->surface[surface_idx].size = size; > +} > + > +static int yuv_semiplanar_bpp(uint32_t drm_format) > +{ > + switch (drm_format) { > + case DRM_FORMAT_NV12: > + return 8; > + case DRM_FORMAT_P010: > + return 10; > + case DRM_FORMAT_P012: > + return 12; > + case DRM_FORMAT_P016: > + return 16; > + default: > + igt_assert_f(0, "Unsupported format: %08x\n", > drm_format); > + } > +} > + > static void init_buf(struct fb_blit_upload *blit, > struct igt_buf *buf, > const struct igt_fb *fb, > const char *name) > { > + int num_surfaces; > + int i; > + > igt_assert_eq(fb->offsets[0], 0); > > buf->bo = gem_handle_to_libdrm_bo(blit->bufmgr, blit->fd, > name, fb->gem_handle); > buf->tiling = igt_fb_mod_to_tiling(fb->modifier); > - buf->surface[0].stride = fb->strides[0]; > buf->bpp = fb->plane_bpp[0]; > - buf->surface[0].size = fb->size; > + buf->format_is_yuv = igt_format_is_yuv(fb->drm_format); > + buf->format_is_yuv_semiplanar = > + igt_format_is_yuv_semiplanar(fb->drm_format); > + if (buf->format_is_yuv_semiplanar) > + buf->yuv_semiplanar_bpp = yuv_semiplanar_bpp(fb- > >drm_format); > > if (is_ccs_modifier(fb->modifier)) { > igt_assert_eq(fb->strides[0] & 127, 0); > @@ -1994,8 +2038,24 @@ static void init_buf(struct fb_blit_upload > *blit, > else > buf->compression = I915_COMPRESSION_RENDER; > > - buf->ccs[0].offset = fb->offsets[1]; > - buf->ccs[0].stride = fb->strides[1]; > + num_surfaces = fb->num_planes / 2; > + for (i = 0; i < num_surfaces; i++) > + init_buf_ccs(buf, i, > + fb->offsets[num_surfaces + i], > + fb->strides[num_surfaces + i]); > + } else { > + num_surfaces = fb->num_planes; > + } > + > + igt_assert(fb->offsets[0] == 0); > + for (i = 0; i < num_surfaces; i++) { > + uint32_t end = > + i == fb->num_planes - 1 ? fb->size : fb- > >offsets[i + 1]; > + > + init_buf_surface(buf, i, > + fb->offsets[i], > + fb->strides[i], > + end - fb->offsets[i]); > } > > if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > @@ -2007,6 +2067,15 @@ static void fini_buf(struct igt_buf *buf) > drm_intel_bo_unreference(buf->bo); > } > > +static bool use_vebox_copy(const struct igt_fb *src_fb, > + const struct igt_fb *dst_fb) > +{ > + > + return is_gen12_mc_ccs_modifier(dst_fb->modifier) || > + igt_format_is_yuv(src_fb->drm_format) || > + igt_format_is_yuv(dst_fb->drm_format); > +} > + > /** > * copy_with_engine: > * @blit: context for the copy operation > @@ -2029,7 +2098,7 @@ static void copy_with_engine(struct > fb_blit_upload *blit, > igt_render_copyfunc_t render_copy = NULL; > igt_vebox_copyfunc_t vebox_copy = NULL; > > - if (is_gen12_mc_ccs_modifier(dst_fb->modifier)) > + if (use_vebox_copy(src_fb, dst_fb)) > vebox_copy = > igt_get_vebox_copyfunc(intel_get_drm_devid(blit->fd)); > else > render_copy = > igt_get_render_copyfunc(intel_get_drm_devid(blit->fd)); > diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c > index 5addb2e2..fcd24f08 100644 > --- a/lib/intel_aux_pgtable.c > +++ b/lib/intel_aux_pgtable.c > @@ -33,6 +33,12 @@ > > #define max(a, b) ((a) > (b) ? (a) : (b)) > > +#define AUX_FORMAT_YCRCB 0x03 > +#define AUX_FORMAT_P010 0x07 > +#define AUX_FORMAT_P016 0x08 > +#define AUX_FORMAT_ARGB_8B 0x0A > +#define AUX_FORMAT_NV12_21 0x0F > + > struct pgtable_level_desc { > int idx_shift; > int idx_bits; > @@ -55,6 +61,23 @@ struct pgtable { > drm_intel_bo *bo; > }; > > +static uint64_t last_buf_surface_end(const struct igt_buf *buf) > +{ > + uint64_t end_offset = 0; > + int num_surfaces = buf->format_is_yuv_semiplanar ? 2 : 1; > + int i; > + > + for (i = 0; i < num_surfaces; i++) { > + uint64_t surface_end = buf->surface[i].offset + > + buf->surface[i].size; > + > + if (surface_end > end_offset) > + end_offset = surface_end; > + } > + > + return end_offset; > +} > + > static int > pgt_table_count(int address_bits, const struct igt_buf **bufs, int > buf_count) > { > @@ -77,7 +100,7 @@ pgt_table_count(int address_bits, const struct > igt_buf **bufs, int buf_count) > /* Avoid double counting for overlapping aligned bufs. > */ > start = max(start, end); > > - end = ALIGN(buf->bo->offset64 + buf->surface[0].size, > + end = ALIGN(buf->bo->offset64 + > last_buf_surface_end(buf), > 1UL << address_bits); > igt_assert(end >= start); > > @@ -189,7 +212,29 @@ pgt_set_l1_entry(struct pgtable *pgt, uint64_t > l1_table, > *l1_entry_ptr = ptr | flags; > } > > -static uint64_t pgt_get_l1_flags(const struct igt_buf *buf) > +#define DEPTH_VAL_RESERVED 3 > + > +static int bpp_to_depth_val(int bpp) > +{ > + switch (bpp) { > + case 8: > + return 4; > + case 10: > + return 1; > + case 12: > + return 2; > + case 16: > + return 0; > + case 32: > + return 5; > + case 64: > + return 6; > + default: > + igt_assert_f(0, "invalid bpp %d\n", bpp); > + } > +} > + > +static uint64_t pgt_get_l1_flags(const struct igt_buf *buf, int > surface_idx) > { > /* > * The offset of .tile_mode isn't specifed by bspec, it's what > Mesa > @@ -213,8 +258,6 @@ static uint64_t pgt_get_l1_flags(const struct > igt_buf *buf) > .e = { > .valid = 1, > .tile_mode = buf->tiling == I915_TILING_Y ? 1 : > 0, > - .depth = 5, /* 32bpp */ > - .format = 0xA, /* B8G8R8A8_UNORM */ > } > }; > > @@ -227,7 +270,49 @@ static uint64_t pgt_get_l1_flags(const struct > igt_buf *buf) > buf->tiling == I915_TILING_Yf || > buf->tiling == I915_TILING_Ys); > > - igt_assert(buf->bpp == 32); > + entry.e.ycr = surface_idx > 0; > + > + if (buf->format_is_yuv_semiplanar) { > + entry.e.depth = bpp_to_depth_val(buf->bpp); > + switch (buf->yuv_semiplanar_bpp) { > + case 8: > + entry.e.format = AUX_FORMAT_NV12_21; > + entry.e.depth = DEPTH_VAL_RESERVED; > + break; > + case 10: > + entry.e.format = AUX_FORMAT_P010; > + entry.e.depth = bpp_to_depth_val(10); > + break; > + case 12: > + entry.e.format = AUX_FORMAT_P016; > + entry.e.depth = bpp_to_depth_val(12); > + break; > + case 16: > + entry.e.format = AUX_FORMAT_P016; > + entry.e.depth = bpp_to_depth_val(16); > + break; > + default: > + igt_assert(0); > + } > + } else if (buf->format_is_yuv) { > + switch (buf->bpp) { > + case 16: > + entry.e.format = AUX_FORMAT_YCRCB; > + entry.e.depth = DEPTH_VAL_RESERVED; > + break; > + default: > + igt_assert(0); > + } > + } else { > + switch (buf->bpp) { > + case 32: > + entry.e.format = AUX_FORMAT_ARGB_8B; > + entry.e.depth = bpp_to_depth_val(32); > + break; > + default: > + igt_assert(0); > + } > + } > > return entry.l; > } > @@ -253,14 +338,21 @@ static uint64_t pgt_get_lx_flags(void) > static void > pgt_populate_entries_for_buf(struct pgtable *pgt, > const struct igt_buf *buf, > - uint64_t top_table) > + uint64_t top_table, > + int surface_idx) > { > - uint64_t surface_addr = buf->bo->offset64; > - uint64_t surface_end = surface_addr + buf->surface[0].size; > - uint64_t aux_addr = buf->bo->offset64 + buf->ccs[0].offset; > - uint64_t l1_flags = pgt_get_l1_flags(buf); > + uint64_t surface_addr = buf->bo->offset64 + > + buf->surface[surface_idx].offset; > + uint64_t surface_end = surface_addr + > + buf->surface[surface_idx].size; > + uint64_t aux_addr = buf->bo->offset64 + buf- > >ccs[surface_idx].offset; > + uint64_t l1_flags = pgt_get_l1_flags(buf, surface_idx); > uint64_t lx_flags = pgt_get_lx_flags(); > > + igt_assert(!(buf->surface[surface_idx].stride % 512)); > + igt_assert_eq(buf->ccs[surface_idx].stride, > + buf->surface[surface_idx].stride / 512 * 64); > + > for (; surface_addr < surface_end; > surface_addr += MAIN_SURFACE_BLOCK_SIZE, > aux_addr += AUX_CCS_BLOCK_SIZE) { > @@ -292,8 +384,13 @@ static void pgt_populate_entries(struct pgtable > *pgt, > /* Top level table must be at offset 0. */ > igt_assert(top_table == 0); > > - for (i = 0; i < buf_count; i++) > - pgt_populate_entries_for_buf(pgt, bufs[i], top_table); > + for (i = 0; i < buf_count; i++) { > + igt_assert_eq(bufs[i]->surface[0].offset, 0); > + > + pgt_populate_entries_for_buf(pgt, bufs[i], top_table, > 0); > + if (bufs[i]->format_is_yuv_semiplanar) > + pgt_populate_entries_for_buf(pgt, bufs[i], > top_table, 1); > + } > } > > static struct pgtable * > diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h > index 69580839..fd7ef03f 100644 > --- a/lib/intel_batchbuffer.h > +++ b/lib/intel_batchbuffer.h > @@ -235,8 +235,12 @@ struct igt_buf { > uint32_t tiling; > enum i915_compression compression; > uint32_t bpp; > + uint32_t yuv_semiplanar_bpp; > uint32_t *data; > + bool format_is_yuv:1; > + bool format_is_yuv_semiplanar:1; > struct { > + uint32_t offset; > uint32_t stride; > uint32_t size; > } surface[2]; > diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c > index 2f017514..237c43f2 100644 > --- a/lib/veboxcopy_gen12.c > +++ b/lib/veboxcopy_gen12.c > @@ -26,7 +26,10 @@ > #include "intel_aux_pgtable.h" > #include "veboxcopy.h" > > +#define YCRCB_NORMAL 0 > +#define PLANAR_420_8 4 > #define R8G8B8A8_UNORM 8 > +#define PLANAR_420_16 12 > > struct vebox_surface_state { > struct { > @@ -129,10 +132,23 @@ struct vebox_tiling_convert { > }; > } __attribute__((packed)); > > +static bool format_is_interleaved_yuv(int format) > +{ > + switch (format) { > + case YCRCB_NORMAL: > + case PLANAR_420_8: > + case PLANAR_420_16: > + return true; > + } > + > + return false; > +} > + > static void emit_surface_state_cmd(struct intel_batchbuffer *batch, > int surface_id, > int width, int height, int bpp, > - int pitch, uint32_t tiling, int > format) > + int pitch, uint32_t tiling, int > format, > + uint32_t uv_offset) > { > struct vebox_surface_state *ss; > > @@ -149,11 +165,15 @@ static void emit_surface_state_cmd(struct > intel_batchbuffer *batch, > ss->ss2.width = width - 1; > > ss->ss3.surface_format = format; > + if (format_is_interleaved_yuv(format)) > + ss->ss3.chroma_interleave = 1; > ss->ss3.surface_pitch = pitch - 1; > ss->ss3.tile_walk = (tiling == I915_TILING_Y) || > (tiling == I915_TILING_Yf); > ss->ss3.tiled_surface = tiling != I915_TILING_NONE; > > + ss->ss4.u_y_offset = uv_offset / pitch; > + > ss->ss7.derived_surface_pitch = pitch - 1; > } > > @@ -226,8 +246,7 @@ void gen12_vebox_copyfunc(struct > intel_batchbuffer *batch, > { > struct aux_pgtable_info aux_pgtable_info = { }; > uint32_t aux_pgtable_state; > - > - igt_assert(src->bpp == dst->bpp); > + int format; > > intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX); > > @@ -245,18 +264,43 @@ void gen12_vebox_copyfunc(struct > intel_batchbuffer *batch, > > gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, false); > > + /* The tiling convert command can't convert formats. */ > + igt_assert_eq(src->format_is_yuv, dst->format_is_yuv); > + igt_assert_eq(src->format_is_yuv_semiplanar, > + dst->format_is_yuv_semiplanar); > + igt_assert_eq(src->bpp, dst->bpp); > + > /* TODO: add support for more formats */ > - igt_assert(src->bpp == 32); > + switch (src->bpp) { > + case 8: > + igt_assert(src->format_is_yuv_semiplanar); > + format = PLANAR_420_8; > + break; > + case 16: > + igt_assert(src->format_is_yuv); > + format = src->format_is_yuv_semiplanar ? PLANAR_420_16 > : > + YCRCB_NORMAL; > + break; > + case 32: > + igt_assert(!src->format_is_yuv && > + !src->format_is_yuv_semiplanar); > + format = R8G8B8A8_UNORM; > + break; > + default: > + igt_assert_f(0, "Unsupported bpp: %u\n", src->bpp); > + } > + > + igt_assert(!src->format_is_yuv_semiplanar || > + (src->surface[1].offset && dst->surface[1].offset)); > emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT, > width, height, src->bpp, > src->surface[0].stride, > - src->tiling, R8G8B8A8_UNORM); > + src->tiling, format, src- > >surface[1].offset); > > - igt_assert(dst->bpp == 32); > emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT, > width, height, dst->bpp, > dst->surface[0].stride, > - dst->tiling, R8G8B8A8_UNORM); > + dst->tiling, format, dst- > >surface[1].offset); > > emit_tiling_convert_cmd(batch, > src->bo, src->tiling, src->compression, _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t 05/10] Revert "tests/kms_plane: Disable GEN12 media compression YUV tests" 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (3 preceding siblings ...) 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 04/10] lib: Add engine copy support for YUV formats Imre Deak @ 2019-12-30 3:40 ` Imre Deak 2019-12-30 13:24 ` Kahola, Mika 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 06/10] tests/kms_ccs: Add support for testing multiple formats Imre Deak ` (10 subsequent siblings) 15 siblings, 1 reply; 33+ messages in thread From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw) To: igt-dev This reverts commit 0586d205f651674e575351c2d5a7d0760716c9f1. Now that support for YUV engine copy was added, we can re-enable the YUV tests. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- tests/kms_plane.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/tests/kms_plane.c b/tests/kms_plane.c index 6ad7bacc..9ef3a7f3 100644 --- a/tests/kms_plane.c +++ b/tests/kms_plane.c @@ -596,13 +596,6 @@ static bool test_format_plane_yuv(data_t *data, enum pipe pipe, if (!igt_plane_has_prop(plane, IGT_PLANE_COLOR_RANGE)) return true; - /* - * The Vebox blitter backend needed for this can't handle YUV formats - * yet, so skip it for now. - */ - if (modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) - return true; - for (enum igt_color_encoding e = 0; e < IGT_NUM_COLOR_ENCODINGS; e++) { if (!igt_plane_try_prop_enum(plane, IGT_PLANE_COLOR_ENCODING, -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 05/10] Revert "tests/kms_plane: Disable GEN12 media compression YUV tests" 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 05/10] Revert "tests/kms_plane: Disable GEN12 media compression YUV tests" Imre Deak @ 2019-12-30 13:24 ` Kahola, Mika 0 siblings, 0 replies; 33+ messages in thread From: Kahola, Mika @ 2019-12-30 13:24 UTC (permalink / raw) To: igt-dev@lists.freedesktop.org, Deak, Imre On Mon, 2019-12-30 at 05:40 +0200, Imre Deak wrote: > This reverts commit 0586d205f651674e575351c2d5a7d0760716c9f1. > > Now that support for YUV engine copy was added, we can re-enable the > YUV tests. > > Cc: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> > --- > tests/kms_plane.c | 7 ------- > 1 file changed, 7 deletions(-) > > diff --git a/tests/kms_plane.c b/tests/kms_plane.c > index 6ad7bacc..9ef3a7f3 100644 > --- a/tests/kms_plane.c > +++ b/tests/kms_plane.c > @@ -596,13 +596,6 @@ static bool test_format_plane_yuv(data_t *data, > enum pipe pipe, > if (!igt_plane_has_prop(plane, IGT_PLANE_COLOR_RANGE)) > return true; > > - /* > - * The Vebox blitter backend needed for this can't handle YUV > formats > - * yet, so skip it for now. > - */ > - if (modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) > - return true; > - > for (enum igt_color_encoding e = 0; e < > IGT_NUM_COLOR_ENCODINGS; e++) { > if (!igt_plane_try_prop_enum(plane, > IGT_PLANE_COLOR_ENCODING, _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t 06/10] tests/kms_ccs: Add support for testing multiple formats 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (4 preceding siblings ...) 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 05/10] Revert "tests/kms_plane: Disable GEN12 media compression YUV tests" Imre Deak @ 2019-12-30 3:40 ` Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 07/10] tests/kms_ccs: Add GEN12 CCS media compression format modifier Imre Deak ` (9 subsequent siblings) 15 siblings, 0 replies; 33+ messages in thread From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw) To: igt-dev Prepare for testing the media compression functionality with YUV formats. No functional change. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- tests/kms_ccs.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index d5178824..32b69f3b 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -58,6 +58,7 @@ typedef struct { enum test_flags flags; igt_plane_t *plane; igt_pipe_crc_t *pipe_crc; + uint32_t format; uint64_t ccs_modifier; } data_t; @@ -70,6 +71,10 @@ static const struct { {0.0, 1.0, 0.0} }; +static const uint32_t formats[] = { + DRM_FORMAT_XRGB8888, +}; + static const uint64_t ccs_modifiers[] = { LOCAL_I915_FORMAT_MOD_Y_TILED_CCS, LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS, @@ -134,7 +139,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb, if (data->flags & TEST_BAD_PIXEL_FORMAT) format = DRM_FORMAT_RGB565; else - format = DRM_FORMAT_XRGB8888; + format = data->format; igt_create_bo_for_fb(data->drm_fd, width, height, format, modifier, fb); igt_assert(fb->gem_handle > 0); @@ -206,12 +211,12 @@ static bool try_config(data_t *data, enum test_fb_flags fb_flags, primary = igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY); - if (!igt_plane_has_format_mod(primary, DRM_FORMAT_XRGB8888, + if (!igt_plane_has_format_mod(primary, data->format, data->ccs_modifier)) return false; if (data->plane && fb_flags & FB_COMPRESSED) { - if (!igt_plane_has_format_mod(data->plane, DRM_FORMAT_XRGB8888, + if (!igt_plane_has_format_mod(data->plane, data->format, data->ccs_modifier)) return false; @@ -316,8 +321,13 @@ static int __test_output(data_t *data) igt_output_set_pipe(data->output, data->pipe); for (i = 0; i < ARRAY_SIZE(ccs_modifiers); i++) { + int j; + data->ccs_modifier = ccs_modifiers[i]; - valid_tests += test_ccs(data); + for (j = 0; j < ARRAY_SIZE(formats); j++) { + data->format = formats[j]; + valid_tests += test_ccs(data); + } } igt_output_set_pipe(data->output, PIPE_NONE); -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t 07/10] tests/kms_ccs: Add GEN12 CCS media compression format modifier 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (5 preceding siblings ...) 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 06/10] tests/kms_ccs: Add support for testing multiple formats Imre Deak @ 2019-12-30 3:40 ` Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 08/10] tests/kms_ccs: Work around CRC mismatch when mixing SDR/HDR planes Imre Deak ` (8 subsequent siblings) 15 siblings, 0 replies; 33+ messages in thread From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw) To: igt-dev From: Mika Kahola <mika.kahola@intel.com> Add GEN12 CCS format modifier for media compression. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- tests/kms_ccs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index 32b69f3b..60cdd70c 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -80,6 +80,7 @@ static const uint64_t ccs_modifiers[] = { LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS, LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, + LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, }; /* -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t 08/10] tests/kms_ccs: Work around CRC mismatch when mixing SDR/HDR planes 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (6 preceding siblings ...) 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 07/10] tests/kms_ccs: Add GEN12 CCS media compression format modifier Imre Deak @ 2019-12-30 3:40 ` Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 09/10] tests/kms_ccs: Test YUV formats too Imre Deak ` (7 subsequent siblings) 15 siblings, 0 replies; 33+ messages in thread From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw) To: igt-dev When using both an SDR and HDR plane, the CRC of the resulting image will not match the CRC of the reference image where just an HDR plane is used. To avoid this - most probably HW precision issue - make sure all the planes we enable are of the same SDR/HDR type. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- tests/kms_ccs.c | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index 60cdd70c..a86a3470 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -24,6 +24,8 @@ #include "igt.h" +#define SDR_PLANE_BASE 3 + IGT_TEST_DESCRIPTION("Test render compression (RC), in which the main surface " "is complemented by a color control surface (CCS) that " "the display uses to interpret the compressed data."); @@ -195,11 +197,35 @@ static void generate_fb(data_t *data, struct igt_fb *fb, fb->fb_id = f.fb_id; } +static igt_plane_t *first_sdr_plane(data_t *data) +{ + return igt_output_get_plane(data->output, SDR_PLANE_BASE); +} + +static bool is_sdr_plane(const igt_plane_t *plane) +{ + return plane->index >= SDR_PLANE_BASE; +} + +/* + * Mixing SDR and HDR planes results in a CRC mismatch, so use the first + * SDR/HDR plane as the main plane matching the SDR/HDR type of the sprite + * plane under test. + */ +static igt_plane_t *compatible_main_plane(data_t *data) +{ + if (data->plane && is_sdr_plane(data->plane) && + igt_format_is_yuv(data->format)) + return first_sdr_plane(data); + + return igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY); +} + static bool try_config(data_t *data, enum test_fb_flags fb_flags, igt_crc_t *crc) { igt_display_t *display = &data->display; - igt_plane_t *primary; + igt_plane_t *primary = compatible_main_plane(data); drmModeModeInfo *drm_mode = igt_output_get_mode(data->output); enum igt_commit_style commit; struct igt_fb fb, fb_sprite; @@ -210,8 +236,9 @@ static bool try_config(data_t *data, enum test_fb_flags fb_flags, else commit = COMMIT_UNIVERSAL; - primary = igt_output_get_plane_type(data->output, - DRM_PLANE_TYPE_PRIMARY); + if (primary == data->plane) + return false; + if (!igt_plane_has_format_mod(primary, data->format, data->ccs_modifier)) return false; @@ -392,8 +419,6 @@ igt_main igt_display_require_output_on_pipe(&data.display, data.pipe); for_each_plane_on_pipe(&data.display, data.pipe, data.plane) { - if (data.plane->type == DRM_PLANE_TYPE_PRIMARY) - continue; valid_tests += __test_output(&data); } -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t 09/10] tests/kms_ccs: Test YUV formats too 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (7 preceding siblings ...) 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 08/10] tests/kms_ccs: Work around CRC mismatch when mixing SDR/HDR planes Imre Deak @ 2019-12-30 3:40 ` Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 10/10] tests/kms_ccs: Add option to check the CCS planes Imre Deak ` (6 subsequent siblings) 15 siblings, 0 replies; 33+ messages in thread From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw) To: igt-dev Enable testing of packed and semiplanar YUV formats for better coverage of the display's media decompression functionality. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- tests/kms_ccs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index a86a3470..9e5bb559 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -75,6 +75,10 @@ static const struct { static const uint32_t formats[] = { DRM_FORMAT_XRGB8888, + DRM_FORMAT_YUYV, + DRM_FORMAT_NV12, + DRM_FORMAT_P012, + DRM_FORMAT_P016, }; static const uint64_t ccs_modifiers[] = { -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t 10/10] tests/kms_ccs: Add option to check the CCS planes 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (8 preceding siblings ...) 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 09/10] tests/kms_ccs: Test YUV formats too Imre Deak @ 2019-12-30 3:40 ` Imre Deak 2019-12-30 12:47 ` Juha-Pekka Heikkila 2019-12-30 17:58 ` [igt-dev] [PATCH i-g-t v2 " Imre Deak 2019-12-30 4:12 ` [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add support and coverage for MC YUV formats Patchwork ` (5 subsequent siblings) 15 siblings, 2 replies; 33+ messages in thread From: Imre Deak @ 2019-12-30 3:40 UTC (permalink / raw) To: igt-dev Add an option to check whether the framebuffer content was really compressed. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- lib/igt_fb.c | 15 ++++++++++++ lib/igt_fb.h | 4 ++++ tests/kms_ccs.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 80 insertions(+), 1 deletion(-) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index e6a3ff07..c81b9de8 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -502,6 +502,11 @@ static bool is_ccs_plane(const struct igt_fb *fb, int plane) return plane >= fb->num_planes / 2; } +bool igt_fb_is_ccs_plane(const struct igt_fb *fb, int plane) +{ + return is_ccs_plane(fb, plane); +} + static bool is_gen12_ccs_plane(const struct igt_fb *fb, int plane) { return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); @@ -513,6 +518,11 @@ static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) plane == 2; } +bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) +{ + return is_gen12_ccs_cc_plane(fb, plane); +} + static int ccs_to_main_plane(const struct igt_fb *fb, int plane) { if (is_gen12_ccs_cc_plane(fb, plane)) @@ -521,6 +531,11 @@ static int ccs_to_main_plane(const struct igt_fb *fb, int plane) return plane - fb->num_planes / 2; } +int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int plane) +{ + return ccs_to_main_plane(fb, plane); +} + static unsigned fb_plane_width(const struct igt_fb *fb, int plane) { const struct format_desc_struct *format = lookup_drm_format(fb->drm_format); diff --git a/lib/igt_fb.h b/lib/igt_fb.h index 69132b41..5ed9e35a 100644 --- a/lib/igt_fb.h +++ b/lib/igt_fb.h @@ -170,6 +170,10 @@ void igt_fb_calc_crc(struct igt_fb *fb, igt_crc_t *crc); uint64_t igt_fb_mod_to_tiling(uint64_t modifier); uint64_t igt_fb_tiling_to_mod(uint64_t tiling); +bool igt_fb_is_ccs_plane(const struct igt_fb *fb, int plane); +bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane); +int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int ccs_plane); + /* cairo-based painting */ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb); cairo_surface_t *igt_cairo_image_surface_create_from_png(const char *filename); diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index 9e5bb559..34fb0138 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -89,6 +89,8 @@ static const uint64_t ccs_modifiers[] = { LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, }; +static bool check_ccs_planes; + /* * Limit maximum used sprite plane width so this test will not mistakenly * fail on hardware limitations which are not interesting to this test. @@ -115,6 +117,44 @@ static void addfb_init(struct igt_fb *fb, struct drm_mode_fb_cmd2 *f) } } +static void check_ccs_plane(int drm_fd, igt_fb_t *fb, int plane) +{ + void *map; + void *ccs_p; + size_t ccs_size; + int i; + + ccs_size = fb->strides[plane] * fb->plane_height[plane]; + igt_assert(ccs_size); + + gem_set_domain(drm_fd, fb->gem_handle, I915_GEM_DOMAIN_CPU, 0); + + map = gem_mmap__cpu(drm_fd, fb->gem_handle, 0, fb->size, PROT_READ); + + ccs_size = fb->strides[plane] * fb->plane_height[plane]; + ccs_p = map + fb->offsets[plane]; + for (i = 0; i < ccs_size; i += sizeof(uint32_t)) + if (*(uint32_t *)(ccs_p + i)) + break; + + munmap(map, fb->size); + + igt_assert_f(i < ccs_size, + "CCS plane %d (for main plane %d) lacks compression meta-data\n", + plane, igt_fb_ccs_to_main_plane(fb, plane)); +} + +static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb) +{ + int i; + + for (i = 0; i < fb->num_planes; i++) { + if (igt_fb_is_ccs_plane(fb, i) && + !igt_fb_is_gen12_ccs_cc_plane(fb, i)) + check_ccs_plane(drm_fd, fb, i); + } +} + static void generate_fb(data_t *data, struct igt_fb *fb, int width, int height, enum test_fb_flags fb_flags) @@ -198,6 +238,9 @@ static void generate_fb(data_t *data, struct igt_fb *fb, } else igt_assert_eq(ret, 0); + if (check_ccs_planes) + check_all_ccs_planes(data->drm_fd, fb); + fb->fb_id = f.fb_id; } @@ -376,7 +419,24 @@ static void test_output(data_t *data) static data_t data; -igt_main +static int opt_handler(int opt, int opt_index, void *opt_data) +{ + switch (opt) { + case 'c': + check_ccs_planes = true; + break; + default: + return IGT_OPT_HANDLER_ERROR; + } + + return IGT_OPT_HANDLER_SUCCESS; +} + +static const char *help_str = +" -c\tCheck the presence of compression meta-data\n" +; + +igt_main_args("c", NULL, help_str, opt_handler, NULL) { enum pipe pipe; -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 10/10] tests/kms_ccs: Add option to check the CCS planes 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 10/10] tests/kms_ccs: Add option to check the CCS planes Imre Deak @ 2019-12-30 12:47 ` Juha-Pekka Heikkila 2019-12-30 13:12 ` Imre Deak 2019-12-30 17:58 ` [igt-dev] [PATCH i-g-t v2 " Imre Deak 1 sibling, 1 reply; 33+ messages in thread From: Juha-Pekka Heikkila @ 2019-12-30 12:47 UTC (permalink / raw) To: Imre Deak, igt-dev Small nag on this patch number 10 but generally patches 6..10 are Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> On 30.12.2019 5.40, Imre Deak wrote: > Add an option to check whether the framebuffer content was really > compressed. > > Cc: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > lib/igt_fb.c | 15 ++++++++++++ > lib/igt_fb.h | 4 ++++ > tests/kms_ccs.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++- > 3 files changed, 80 insertions(+), 1 deletion(-) > > diff --git a/lib/igt_fb.c b/lib/igt_fb.c > index e6a3ff07..c81b9de8 100644 > --- a/lib/igt_fb.c > +++ b/lib/igt_fb.c > @@ -502,6 +502,11 @@ static bool is_ccs_plane(const struct igt_fb *fb, int plane) > return plane >= fb->num_planes / 2; > } > > +bool igt_fb_is_ccs_plane(const struct igt_fb *fb, int plane) > +{ > + return is_ccs_plane(fb, plane); > +} > + > static bool is_gen12_ccs_plane(const struct igt_fb *fb, int plane) > { > return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); > @@ -513,6 +518,11 @@ static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) > plane == 2; > } > > +bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) > +{ > + return is_gen12_ccs_cc_plane(fb, plane); > +} > + > static int ccs_to_main_plane(const struct igt_fb *fb, int plane) > { > if (is_gen12_ccs_cc_plane(fb, plane)) > @@ -521,6 +531,11 @@ static int ccs_to_main_plane(const struct igt_fb *fb, int plane) > return plane - fb->num_planes / 2; > } > > +int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int plane) > +{ > + return ccs_to_main_plane(fb, plane); > +} > + > static unsigned fb_plane_width(const struct igt_fb *fb, int plane) > { > const struct format_desc_struct *format = lookup_drm_format(fb->drm_format); > diff --git a/lib/igt_fb.h b/lib/igt_fb.h > index 69132b41..5ed9e35a 100644 > --- a/lib/igt_fb.h > +++ b/lib/igt_fb.h > @@ -170,6 +170,10 @@ void igt_fb_calc_crc(struct igt_fb *fb, igt_crc_t *crc); > uint64_t igt_fb_mod_to_tiling(uint64_t modifier); > uint64_t igt_fb_tiling_to_mod(uint64_t tiling); > > +bool igt_fb_is_ccs_plane(const struct igt_fb *fb, int plane); > +bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane); > +int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int ccs_plane); > + > /* cairo-based painting */ > cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb); > cairo_surface_t *igt_cairo_image_surface_create_from_png(const char *filename); > diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c > index 9e5bb559..34fb0138 100644 > --- a/tests/kms_ccs.c > +++ b/tests/kms_ccs.c > @@ -89,6 +89,8 @@ static const uint64_t ccs_modifiers[] = { > LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > }; > > +static bool check_ccs_planes; > + > /* > * Limit maximum used sprite plane width so this test will not mistakenly > * fail on hardware limitations which are not interesting to this test. > @@ -115,6 +117,44 @@ static void addfb_init(struct igt_fb *fb, struct drm_mode_fb_cmd2 *f) > } > } > > +static void check_ccs_plane(int drm_fd, igt_fb_t *fb, int plane) > +{ > + void *map; > + void *ccs_p; > + size_t ccs_size; > + int i; > + > + ccs_size = fb->strides[plane] * fb->plane_height[plane]; > + igt_assert(ccs_size); > + > + gem_set_domain(drm_fd, fb->gem_handle, I915_GEM_DOMAIN_CPU, 0); > + > + map = gem_mmap__cpu(drm_fd, fb->gem_handle, 0, fb->size, PROT_READ); > + > + ccs_size = fb->strides[plane] * fb->plane_height[plane]; > + ccs_p = map + fb->offsets[plane]; > + for (i = 0; i < ccs_size; i += sizeof(uint32_t)) > + if (*(uint32_t *)(ccs_p + i)) > + break; This check for uint32_t zeros myself I'd write more clear what is happening..maybe even with comment why there's wish it's not all zeros since those fbs are coming from elsewhere. But that's just opinion. > + > + munmap(map, fb->size); > + > + igt_assert_f(i < ccs_size, > + "CCS plane %d (for main plane %d) lacks compression meta-data\n", > + plane, igt_fb_ccs_to_main_plane(fb, plane)); > +} > + > +static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb) > +{ > + int i; > + > + for (i = 0; i < fb->num_planes; i++) { > + if (igt_fb_is_ccs_plane(fb, i) && > + !igt_fb_is_gen12_ccs_cc_plane(fb, i)) > + check_ccs_plane(drm_fd, fb, i); > + } > +} > + > static void generate_fb(data_t *data, struct igt_fb *fb, > int width, int height, > enum test_fb_flags fb_flags) > @@ -198,6 +238,9 @@ static void generate_fb(data_t *data, struct igt_fb *fb, > } else > igt_assert_eq(ret, 0); > > + if (check_ccs_planes) > + check_all_ccs_planes(data->drm_fd, fb); > + > fb->fb_id = f.fb_id; > } > > @@ -376,7 +419,24 @@ static void test_output(data_t *data) > > static data_t data; > > -igt_main > +static int opt_handler(int opt, int opt_index, void *opt_data) > +{ > + switch (opt) { > + case 'c': > + check_ccs_planes = true; > + break; > + default: > + return IGT_OPT_HANDLER_ERROR; > + } > + > + return IGT_OPT_HANDLER_SUCCESS; > +} > + > +static const char *help_str = > +" -c\tCheck the presence of compression meta-data\n" > +; > + > +igt_main_args("c", NULL, help_str, opt_handler, NULL) > { > enum pipe pipe; > > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 10/10] tests/kms_ccs: Add option to check the CCS planes 2019-12-30 12:47 ` Juha-Pekka Heikkila @ 2019-12-30 13:12 ` Imre Deak 2019-12-30 13:34 ` Juha-Pekka Heikkila 0 siblings, 1 reply; 33+ messages in thread From: Imre Deak @ 2019-12-30 13:12 UTC (permalink / raw) To: Juha-Pekka Heikkila; +Cc: igt-dev On Mon, Dec 30, 2019 at 02:47:04PM +0200, Juha-Pekka Heikkila wrote: > Small nag on this patch number 10 but generally patches 6..10 are > > Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> > > > On 30.12.2019 5.40, Imre Deak wrote: > > Add an option to check whether the framebuffer content was really > > compressed. > > > > Cc: Mika Kahola <mika.kahola@intel.com> > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > lib/igt_fb.c | 15 ++++++++++++ > > lib/igt_fb.h | 4 ++++ > > tests/kms_ccs.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++- > > 3 files changed, 80 insertions(+), 1 deletion(-) > > > > diff --git a/lib/igt_fb.c b/lib/igt_fb.c > > index e6a3ff07..c81b9de8 100644 > > --- a/lib/igt_fb.c > > +++ b/lib/igt_fb.c > > @@ -502,6 +502,11 @@ static bool is_ccs_plane(const struct igt_fb *fb, int plane) > > return plane >= fb->num_planes / 2; > > } > > +bool igt_fb_is_ccs_plane(const struct igt_fb *fb, int plane) > > +{ > > + return is_ccs_plane(fb, plane); > > +} > > + > > static bool is_gen12_ccs_plane(const struct igt_fb *fb, int plane) > > { > > return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); > > @@ -513,6 +518,11 @@ static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) > > plane == 2; > > } > > +bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) > > +{ > > + return is_gen12_ccs_cc_plane(fb, plane); > > +} > > + > > static int ccs_to_main_plane(const struct igt_fb *fb, int plane) > > { > > if (is_gen12_ccs_cc_plane(fb, plane)) > > @@ -521,6 +531,11 @@ static int ccs_to_main_plane(const struct igt_fb *fb, int plane) > > return plane - fb->num_planes / 2; > > } > > +int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int plane) > > +{ > > + return ccs_to_main_plane(fb, plane); > > +} > > + > > static unsigned fb_plane_width(const struct igt_fb *fb, int plane) > > { > > const struct format_desc_struct *format = lookup_drm_format(fb->drm_format); > > diff --git a/lib/igt_fb.h b/lib/igt_fb.h > > index 69132b41..5ed9e35a 100644 > > --- a/lib/igt_fb.h > > +++ b/lib/igt_fb.h > > @@ -170,6 +170,10 @@ void igt_fb_calc_crc(struct igt_fb *fb, igt_crc_t *crc); > > uint64_t igt_fb_mod_to_tiling(uint64_t modifier); > > uint64_t igt_fb_tiling_to_mod(uint64_t tiling); > > +bool igt_fb_is_ccs_plane(const struct igt_fb *fb, int plane); > > +bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane); > > +int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int ccs_plane); > > + > > /* cairo-based painting */ > > cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb); > > cairo_surface_t *igt_cairo_image_surface_create_from_png(const char *filename); > > diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c > > index 9e5bb559..34fb0138 100644 > > --- a/tests/kms_ccs.c > > +++ b/tests/kms_ccs.c > > @@ -89,6 +89,8 @@ static const uint64_t ccs_modifiers[] = { > > LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > }; > > +static bool check_ccs_planes; > > + > > /* > > * Limit maximum used sprite plane width so this test will not mistakenly > > * fail on hardware limitations which are not interesting to this test. > > @@ -115,6 +117,44 @@ static void addfb_init(struct igt_fb *fb, struct drm_mode_fb_cmd2 *f) > > } > > } > > +static void check_ccs_plane(int drm_fd, igt_fb_t *fb, int plane) > > +{ > > + void *map; > > + void *ccs_p; > > + size_t ccs_size; > > + int i; > > + > > + ccs_size = fb->strides[plane] * fb->plane_height[plane]; > > + igt_assert(ccs_size); > > + > > + gem_set_domain(drm_fd, fb->gem_handle, I915_GEM_DOMAIN_CPU, 0); > > + > > + map = gem_mmap__cpu(drm_fd, fb->gem_handle, 0, fb->size, PROT_READ); > > + > > + ccs_size = fb->strides[plane] * fb->plane_height[plane]; > > + ccs_p = map + fb->offsets[plane]; > > + for (i = 0; i < ccs_size; i += sizeof(uint32_t)) > > + if (*(uint32_t *)(ccs_p + i)) > > + break; > > This check for uint32_t zeros myself I'd write more clear what is > happening.. > maybe even with comment why there's wish it's not all zeros since > those fbs are coming from elsewhere. But that's just opinion. How about the following comment in front of the function?: """ The CCS planes of compressed framebuffers have non-zero bytes if the engine compressed effectively the framebuffer. The actual encoding of these bytes is not specified, but we know that seeing an all-zero CCS plane means that the engine left the FB uncompressed, which is not what we expect in the test. Look for the first non-zero byte in the given CCS plane to get a minimal assurance that compression took place. """ > > > + > > + munmap(map, fb->size); > > + > > + igt_assert_f(i < ccs_size, > > + "CCS plane %d (for main plane %d) lacks compression meta-data\n", > > + plane, igt_fb_ccs_to_main_plane(fb, plane)); > > +} > > + > > +static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb) > > +{ > > + int i; > > + > > + for (i = 0; i < fb->num_planes; i++) { > > + if (igt_fb_is_ccs_plane(fb, i) && > > + !igt_fb_is_gen12_ccs_cc_plane(fb, i)) > > + check_ccs_plane(drm_fd, fb, i); > > + } > > +} > > + > > static void generate_fb(data_t *data, struct igt_fb *fb, > > int width, int height, > > enum test_fb_flags fb_flags) > > @@ -198,6 +238,9 @@ static void generate_fb(data_t *data, struct igt_fb *fb, > > } else > > igt_assert_eq(ret, 0); > > + if (check_ccs_planes) > > + check_all_ccs_planes(data->drm_fd, fb); > > + > > fb->fb_id = f.fb_id; > > } > > @@ -376,7 +419,24 @@ static void test_output(data_t *data) > > static data_t data; > > -igt_main > > +static int opt_handler(int opt, int opt_index, void *opt_data) > > +{ > > + switch (opt) { > > + case 'c': > > + check_ccs_planes = true; > > + break; > > + default: > > + return IGT_OPT_HANDLER_ERROR; > > + } > > + > > + return IGT_OPT_HANDLER_SUCCESS; > > +} > > + > > +static const char *help_str = > > +" -c\tCheck the presence of compression meta-data\n" > > +; > > + > > +igt_main_args("c", NULL, help_str, opt_handler, NULL) > > { > > enum pipe pipe; > > > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 10/10] tests/kms_ccs: Add option to check the CCS planes 2019-12-30 13:12 ` Imre Deak @ 2019-12-30 13:34 ` Juha-Pekka Heikkila 0 siblings, 0 replies; 33+ messages in thread From: Juha-Pekka Heikkila @ 2019-12-30 13:34 UTC (permalink / raw) To: imre.deak; +Cc: igt-dev On 30.12.2019 15.12, Imre Deak wrote: > On Mon, Dec 30, 2019 at 02:47:04PM +0200, Juha-Pekka Heikkila wrote: >> Small nag on this patch number 10 but generally patches 6..10 are >> >> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> >> >> >> On 30.12.2019 5.40, Imre Deak wrote: >>> Add an option to check whether the framebuffer content was really >>> compressed. >>> >>> Cc: Mika Kahola <mika.kahola@intel.com> >>> Signed-off-by: Imre Deak <imre.deak@intel.com> >>> --- >>> lib/igt_fb.c | 15 ++++++++++++ >>> lib/igt_fb.h | 4 ++++ >>> tests/kms_ccs.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++- >>> 3 files changed, 80 insertions(+), 1 deletion(-) >>> >>> diff --git a/lib/igt_fb.c b/lib/igt_fb.c >>> index e6a3ff07..c81b9de8 100644 >>> --- a/lib/igt_fb.c >>> +++ b/lib/igt_fb.c >>> @@ -502,6 +502,11 @@ static bool is_ccs_plane(const struct igt_fb *fb, int plane) >>> return plane >= fb->num_planes / 2; >>> } >>> +bool igt_fb_is_ccs_plane(const struct igt_fb *fb, int plane) >>> +{ >>> + return is_ccs_plane(fb, plane); >>> +} >>> + >>> static bool is_gen12_ccs_plane(const struct igt_fb *fb, int plane) >>> { >>> return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); >>> @@ -513,6 +518,11 @@ static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) >>> plane == 2; >>> } >>> +bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) >>> +{ >>> + return is_gen12_ccs_cc_plane(fb, plane); >>> +} >>> + >>> static int ccs_to_main_plane(const struct igt_fb *fb, int plane) >>> { >>> if (is_gen12_ccs_cc_plane(fb, plane)) >>> @@ -521,6 +531,11 @@ static int ccs_to_main_plane(const struct igt_fb *fb, int plane) >>> return plane - fb->num_planes / 2; >>> } >>> +int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int plane) >>> +{ >>> + return ccs_to_main_plane(fb, plane); >>> +} >>> + >>> static unsigned fb_plane_width(const struct igt_fb *fb, int plane) >>> { >>> const struct format_desc_struct *format = lookup_drm_format(fb->drm_format); >>> diff --git a/lib/igt_fb.h b/lib/igt_fb.h >>> index 69132b41..5ed9e35a 100644 >>> --- a/lib/igt_fb.h >>> +++ b/lib/igt_fb.h >>> @@ -170,6 +170,10 @@ void igt_fb_calc_crc(struct igt_fb *fb, igt_crc_t *crc); >>> uint64_t igt_fb_mod_to_tiling(uint64_t modifier); >>> uint64_t igt_fb_tiling_to_mod(uint64_t tiling); >>> +bool igt_fb_is_ccs_plane(const struct igt_fb *fb, int plane); >>> +bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane); >>> +int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int ccs_plane); >>> + >>> /* cairo-based painting */ >>> cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb); >>> cairo_surface_t *igt_cairo_image_surface_create_from_png(const char *filename); >>> diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c >>> index 9e5bb559..34fb0138 100644 >>> --- a/tests/kms_ccs.c >>> +++ b/tests/kms_ccs.c >>> @@ -89,6 +89,8 @@ static const uint64_t ccs_modifiers[] = { >>> LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, >>> }; >>> +static bool check_ccs_planes; >>> + >>> /* >>> * Limit maximum used sprite plane width so this test will not mistakenly >>> * fail on hardware limitations which are not interesting to this test. >>> @@ -115,6 +117,44 @@ static void addfb_init(struct igt_fb *fb, struct drm_mode_fb_cmd2 *f) >>> } >>> } >>> +static void check_ccs_plane(int drm_fd, igt_fb_t *fb, int plane) >>> +{ >>> + void *map; >>> + void *ccs_p; >>> + size_t ccs_size; >>> + int i; >>> + >>> + ccs_size = fb->strides[plane] * fb->plane_height[plane]; >>> + igt_assert(ccs_size); >>> + >>> + gem_set_domain(drm_fd, fb->gem_handle, I915_GEM_DOMAIN_CPU, 0); >>> + >>> + map = gem_mmap__cpu(drm_fd, fb->gem_handle, 0, fb->size, PROT_READ); >>> + >>> + ccs_size = fb->strides[plane] * fb->plane_height[plane]; >>> + ccs_p = map + fb->offsets[plane]; >>> + for (i = 0; i < ccs_size; i += sizeof(uint32_t)) >>> + if (*(uint32_t *)(ccs_p + i)) >>> + break; >> >> This check for uint32_t zeros myself I'd write more clear what is >> happening.. >> maybe even with comment why there's wish it's not all zeros since >> those fbs are coming from elsewhere. But that's just opinion. > > How about the following comment in front of the function?: > """ > The CCS planes of compressed framebuffers have non-zero bytes if the > engine compressed effectively the framebuffer. The actual encoding of > these bytes is not specified, but we know that seeing an all-zero CCS > plane means that the engine left the FB uncompressed, which is not what > we expect in the test. Look for the first non-zero byte in the given CCS > plane to get a minimal assurance that compression took place. > """ Sound good to me. I don't know how CCS plane content should look like, I only saw there was assumption it's not all zeros on passed in fb data in this test. > >> >>> + >>> + munmap(map, fb->size); >>> + >>> + igt_assert_f(i < ccs_size, >>> + "CCS plane %d (for main plane %d) lacks compression meta-data\n", >>> + plane, igt_fb_ccs_to_main_plane(fb, plane)); >>> +} >>> + >>> +static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb) >>> +{ >>> + int i; >>> + >>> + for (i = 0; i < fb->num_planes; i++) { >>> + if (igt_fb_is_ccs_plane(fb, i) && >>> + !igt_fb_is_gen12_ccs_cc_plane(fb, i)) >>> + check_ccs_plane(drm_fd, fb, i); >>> + } >>> +} >>> + >>> static void generate_fb(data_t *data, struct igt_fb *fb, >>> int width, int height, >>> enum test_fb_flags fb_flags) >>> @@ -198,6 +238,9 @@ static void generate_fb(data_t *data, struct igt_fb *fb, >>> } else >>> igt_assert_eq(ret, 0); >>> + if (check_ccs_planes) >>> + check_all_ccs_planes(data->drm_fd, fb); >>> + >>> fb->fb_id = f.fb_id; >>> } >>> @@ -376,7 +419,24 @@ static void test_output(data_t *data) >>> static data_t data; >>> -igt_main >>> +static int opt_handler(int opt, int opt_index, void *opt_data) >>> +{ >>> + switch (opt) { >>> + case 'c': >>> + check_ccs_planes = true; >>> + break; >>> + default: >>> + return IGT_OPT_HANDLER_ERROR; >>> + } >>> + >>> + return IGT_OPT_HANDLER_SUCCESS; >>> +} >>> + >>> +static const char *help_str = >>> +" -c\tCheck the presence of compression meta-data\n" >>> +; >>> + >>> +igt_main_args("c", NULL, help_str, opt_handler, NULL) >>> { >>> enum pipe pipe; >>> >> _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] [PATCH i-g-t v2 10/10] tests/kms_ccs: Add option to check the CCS planes 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 10/10] tests/kms_ccs: Add option to check the CCS planes Imre Deak 2019-12-30 12:47 ` Juha-Pekka Heikkila @ 2019-12-30 17:58 ` Imre Deak 1 sibling, 0 replies; 33+ messages in thread From: Imre Deak @ 2019-12-30 17:58 UTC (permalink / raw) To: igt-dev Add an option to check whether the framebuffer content was really compressed. v2: - Add code comment explaining the reason and way of the check. (JP) Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- lib/igt_fb.c | 15 +++++++++++ lib/igt_fb.h | 4 +++ tests/kms_ccs.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 88 insertions(+), 1 deletion(-) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index e6a3ff07..c81b9de8 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -502,6 +502,11 @@ static bool is_ccs_plane(const struct igt_fb *fb, int plane) return plane >= fb->num_planes / 2; } +bool igt_fb_is_ccs_plane(const struct igt_fb *fb, int plane) +{ + return is_ccs_plane(fb, plane); +} + static bool is_gen12_ccs_plane(const struct igt_fb *fb, int plane) { return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); @@ -513,6 +518,11 @@ static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) plane == 2; } +bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) +{ + return is_gen12_ccs_cc_plane(fb, plane); +} + static int ccs_to_main_plane(const struct igt_fb *fb, int plane) { if (is_gen12_ccs_cc_plane(fb, plane)) @@ -521,6 +531,11 @@ static int ccs_to_main_plane(const struct igt_fb *fb, int plane) return plane - fb->num_planes / 2; } +int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int plane) +{ + return ccs_to_main_plane(fb, plane); +} + static unsigned fb_plane_width(const struct igt_fb *fb, int plane) { const struct format_desc_struct *format = lookup_drm_format(fb->drm_format); diff --git a/lib/igt_fb.h b/lib/igt_fb.h index 69132b41..5ed9e35a 100644 --- a/lib/igt_fb.h +++ b/lib/igt_fb.h @@ -170,6 +170,10 @@ void igt_fb_calc_crc(struct igt_fb *fb, igt_crc_t *crc); uint64_t igt_fb_mod_to_tiling(uint64_t modifier); uint64_t igt_fb_tiling_to_mod(uint64_t tiling); +bool igt_fb_is_ccs_plane(const struct igt_fb *fb, int plane); +bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane); +int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int ccs_plane); + /* cairo-based painting */ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb); cairo_surface_t *igt_cairo_image_surface_create_from_png(const char *filename); diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index 9e5bb559..2259a4f1 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -89,6 +89,8 @@ static const uint64_t ccs_modifiers[] = { LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, }; +static bool check_ccs_planes; + /* * Limit maximum used sprite plane width so this test will not mistakenly * fail on hardware limitations which are not interesting to this test. @@ -115,6 +117,52 @@ static void addfb_init(struct igt_fb *fb, struct drm_mode_fb_cmd2 *f) } } +/* + * The CCS planes of compressed framebuffers contain non-zero bytes if the + * engine compressed effectively the framebuffer. The actual encoding of these + * bytes is not specified, but we know that seeing an all-zero CCS plane means + * that the engine left the FB uncompressed, which is not what we expect in + * the test. Look for the first non-zero byte in the given CCS plane to get a + * minimal assurance that compression took place. + */ +static void check_ccs_plane(int drm_fd, igt_fb_t *fb, int plane) +{ + void *map; + void *ccs_p; + size_t ccs_size; + int i; + + ccs_size = fb->strides[plane] * fb->plane_height[plane]; + igt_assert(ccs_size); + + gem_set_domain(drm_fd, fb->gem_handle, I915_GEM_DOMAIN_CPU, 0); + + map = gem_mmap__cpu(drm_fd, fb->gem_handle, 0, fb->size, PROT_READ); + + ccs_size = fb->strides[plane] * fb->plane_height[plane]; + ccs_p = map + fb->offsets[plane]; + for (i = 0; i < ccs_size; i += sizeof(uint32_t)) + if (*(uint32_t *)(ccs_p + i)) + break; + + munmap(map, fb->size); + + igt_assert_f(i < ccs_size, + "CCS plane %d (for main plane %d) lacks compression meta-data\n", + plane, igt_fb_ccs_to_main_plane(fb, plane)); +} + +static void check_all_ccs_planes(int drm_fd, igt_fb_t *fb) +{ + int i; + + for (i = 0; i < fb->num_planes; i++) { + if (igt_fb_is_ccs_plane(fb, i) && + !igt_fb_is_gen12_ccs_cc_plane(fb, i)) + check_ccs_plane(drm_fd, fb, i); + } +} + static void generate_fb(data_t *data, struct igt_fb *fb, int width, int height, enum test_fb_flags fb_flags) @@ -198,6 +246,9 @@ static void generate_fb(data_t *data, struct igt_fb *fb, } else igt_assert_eq(ret, 0); + if (check_ccs_planes) + check_all_ccs_planes(data->drm_fd, fb); + fb->fb_id = f.fb_id; } @@ -376,7 +427,24 @@ static void test_output(data_t *data) static data_t data; -igt_main +static int opt_handler(int opt, int opt_index, void *opt_data) +{ + switch (opt) { + case 'c': + check_ccs_planes = true; + break; + default: + return IGT_OPT_HANDLER_ERROR; + } + + return IGT_OPT_HANDLER_SUCCESS; +} + +static const char *help_str = +" -c\tCheck the presence of compression meta-data\n" +; + +igt_main_args("c", NULL, help_str, opt_handler, NULL) { enum pipe pipe; -- 2.23.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add support and coverage for MC YUV formats 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (9 preceding siblings ...) 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 10/10] tests/kms_ccs: Add option to check the CCS planes Imre Deak @ 2019-12-30 4:12 ` Patchwork 2019-12-30 9:00 ` Imre Deak 2019-12-30 9:18 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork ` (4 subsequent siblings) 15 siblings, 1 reply; 33+ messages in thread From: Patchwork @ 2019-12-30 4:12 UTC (permalink / raw) To: Imre Deak; +Cc: igt-dev == Series Details == Series: lib: Add support and coverage for MC YUV formats URL : https://patchwork.freedesktop.org/series/71483/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7651 -> IGTPW_3889 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_3889 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_3889, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_3889: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@live_client: - fi-skl-6600u: [PASS][1] -> [DMESG-WARN][2] +9 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_selftest@live_client.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i915_selftest@live_client.html * igt@i915_selftest@live_reset: - fi-skl-6600u: [PASS][3] -> [DMESG-FAIL][4] +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_selftest@live_reset.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i915_selftest@live_reset.html Known issues ------------ Here are the changes found in IGTPW_3889 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_pm_rpm@module-reload: - fi-skl-6600u: [PASS][5] -> [DMESG-WARN][6] ([i915#889]) +13 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live_gem_contexts: - fi-byt-j1900: [PASS][7] -> [DMESG-FAIL][8] ([i915#722]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gt_lrc: - fi-skl-6600u: [PASS][9] -> [DMESG-FAIL][10] ([i915#889]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html #### Possible fixes #### * igt@i915_module_load@reload-with-fault-injection: - fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html * igt@kms_busy@basic-flip-pipe-a: - {fi-tgl-guc}: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-tgl-guc/igt@kms_busy@basic-flip-pipe-a.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-tgl-guc/igt@kms_busy@basic-flip-pipe-a.html #### Warnings #### * igt@gem_exec_suspend@basic-s4-devices: - fi-kbl-x1275: [DMESG-WARN][15] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([fdo#107139] / [i915#62] / [i915#92]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html * igt@kms_flip@basic-flip-vs-wf_vblank: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 33) ------------------------------ Additional (4): fi-hsw-4770r fi-skl-6770hq fi-bsw-nick fi-hsw-4770 Missing (15): fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-bwr-2160 fi-snb-2520m fi-ctg-p8600 fi-whl-u fi-bsw-kefka fi-skl-lmem fi-byt-n2820 fi-byt-clapper fi-bdw-samus fi-kbl-r Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5352 -> IGTPW_3889 CI-20190529: 20190529 CI_DRM_7651: dcd9b47d596ff82b9768f1ecba436ef03073c211 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3889: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html IGT_5352: 0586d205f651674e575351c2d5a7d0760716c9f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add support and coverage for MC YUV formats 2019-12-30 4:12 ` [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add support and coverage for MC YUV formats Patchwork @ 2019-12-30 9:00 ` Imre Deak 2019-12-30 9:22 ` Vudum, Lakshminarayana 0 siblings, 1 reply; 33+ messages in thread From: Imre Deak @ 2019-12-30 9:00 UTC (permalink / raw) To: igt-dev, Lakshminarayana Vudum Hi Lakshmi, On Mon, Dec 30, 2019 at 04:12:30AM +0000, Patchwork wrote: > == Series Details == > > Series: lib: Add support and coverage for MC YUV formats > URL : https://patchwork.freedesktop.org/series/71483/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7651 -> IGTPW_3889 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with IGTPW_3889 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in IGTPW_3889, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in IGTPW_3889: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@i915_selftest@live_client: > - fi-skl-6600u: [PASS][1] -> [DMESG-WARN][2] +9 similar issues > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_selftest@live_client.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i915_selftest@live_client.html > > * igt@i915_selftest@live_reset: > - fi-skl-6600u: [PASS][3] -> [DMESG-FAIL][4] +3 similar issues > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_selftest@live_reset.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i915_selftest@live_reset.html These are pre-existing issues, see https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7644/fi-skl-6600u/igt@i915_selftest@live_client.html https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7644/fi-skl-6600u/igt@i915_selftest@live_reset.html --Imre > > > Known issues > ------------ > > Here are the changes found in IGTPW_3889 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@i915_pm_rpm@module-reload: > - fi-skl-6600u: [PASS][5] -> [DMESG-WARN][6] ([i915#889]) +13 similar issues > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html > > * igt@i915_selftest@live_gem_contexts: > - fi-byt-j1900: [PASS][7] -> [DMESG-FAIL][8] ([i915#722]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html > > * igt@i915_selftest@live_gt_lrc: > - fi-skl-6600u: [PASS][9] -> [DMESG-FAIL][10] ([i915#889]) +3 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html > > > #### Possible fixes #### > > * igt@i915_module_load@reload-with-fault-injection: > - fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12] > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html > > * igt@kms_busy@basic-flip-pipe-a: > - {fi-tgl-guc}: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-tgl-guc/igt@kms_busy@basic-flip-pipe-a.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-tgl-guc/igt@kms_busy@basic-flip-pipe-a.html > > > #### Warnings #### > > * igt@gem_exec_suspend@basic-s4-devices: > - fi-kbl-x1275: [DMESG-WARN][15] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([fdo#107139] / [i915#62] / [i915#92]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html > > * igt@kms_flip@basic-flip-vs-modeset: > - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html > > * igt@kms_flip@basic-flip-vs-wf_vblank: > - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +3 similar issues > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 > [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 > [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 > [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889 > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (44 -> 33) > ------------------------------ > > Additional (4): fi-hsw-4770r fi-skl-6770hq fi-bsw-nick fi-hsw-4770 > Missing (15): fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-bwr-2160 fi-snb-2520m fi-ctg-p8600 fi-whl-u fi-bsw-kefka fi-skl-lmem fi-byt-n2820 fi-byt-clapper fi-bdw-samus fi-kbl-r > > > Build changes > ------------- > > * CI: CI-20190529 -> None > * IGT: IGT_5352 -> IGTPW_3889 > > CI-20190529: 20190529 > CI_DRM_7651: dcd9b47d596ff82b9768f1ecba436ef03073c211 @ git://anongit.freedesktop.org/gfx-ci/linux > IGTPW_3889: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html > IGT_5352: 0586d205f651674e575351c2d5a7d0760716c9f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add support and coverage for MC YUV formats 2019-12-30 9:00 ` Imre Deak @ 2019-12-30 9:22 ` Vudum, Lakshminarayana 0 siblings, 0 replies; 33+ messages in thread From: Vudum, Lakshminarayana @ 2019-12-30 9:22 UTC (permalink / raw) To: Deak, Imre, igt-dev@lists.freedesktop.org Imre, Results are re-reported. -----Original Message----- From: Imre Deak <imre.deak@intel.com> Sent: Monday, December 30, 2019 11:00 AM To: igt-dev@lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com> Subject: Re: ✗ Fi.CI.BAT: failure for lib: Add support and coverage for MC YUV formats Hi Lakshmi, On Mon, Dec 30, 2019 at 04:12:30AM +0000, Patchwork wrote: > == Series Details == > > Series: lib: Add support and coverage for MC YUV formats > URL : https://patchwork.freedesktop.org/series/71483/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7651 -> IGTPW_3889 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with IGTPW_3889 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in IGTPW_3889, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in IGTPW_3889: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@i915_selftest@live_client: > - fi-skl-6600u: [PASS][1] -> [DMESG-WARN][2] +9 similar issues > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_selftest@live_client.html > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i > 915_selftest@live_client.html > > * igt@i915_selftest@live_reset: > - fi-skl-6600u: [PASS][3] -> [DMESG-FAIL][4] +3 similar issues > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_selftest@live_reset.html > [4]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i > 915_selftest@live_reset.html These are pre-existing issues, see https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7644/fi-skl-6600u/igt@i915_selftest@live_client.html https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7644/fi-skl-6600u/igt@i915_selftest@live_reset.html --Imre > > > Known issues > ------------ > > Here are the changes found in IGTPW_3889 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@i915_pm_rpm@module-reload: > - fi-skl-6600u: [PASS][5] -> [DMESG-WARN][6] ([i915#889]) +13 similar issues > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html > [6]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i > 915_pm_rpm@module-reload.html > > * igt@i915_selftest@live_gem_contexts: > - fi-byt-j1900: [PASS][7] -> [DMESG-FAIL][8] ([i915#722]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html > [8]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-byt-j1900/igt@i > 915_selftest@live_gem_contexts.html > > * igt@i915_selftest@live_gt_lrc: > - fi-skl-6600u: [PASS][9] -> [DMESG-FAIL][10] ([i915#889]) +3 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html > [10]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i > 915_selftest@live_gt_lrc.html > > > #### Possible fixes #### > > * igt@i915_module_load@reload-with-fault-injection: > - fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12] > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html > [12]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-bxt-dsi/igt@i91 > 5_module_load@reload-with-fault-injection.html > > * igt@kms_busy@basic-flip-pipe-a: > - {fi-tgl-guc}: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-tgl-guc/igt@kms_busy@basic-flip-pipe-a.html > [14]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-tgl-guc/igt@kms > _busy@basic-flip-pipe-a.html > > > #### Warnings #### > > * igt@gem_exec_suspend@basic-s4-devices: > - fi-kbl-x1275: [DMESG-WARN][15] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([fdo#107139] / [i915#62] / [i915#92]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html > [16]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@g > em_exec_suspend@basic-s4-devices.html > > * igt@kms_flip@basic-flip-vs-modeset: > - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html > [18]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@k > ms_flip@basic-flip-vs-modeset.html > > * igt@kms_flip@basic-flip-vs-wf_vblank: > - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +3 similar issues > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank.html > [20]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@k > ms_flip@basic-flip-vs-wf_vblank.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 > [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 > [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 > [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889 > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (44 -> 33) > ------------------------------ > > Additional (4): fi-hsw-4770r fi-skl-6770hq fi-bsw-nick fi-hsw-4770 > Missing (15): fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-bwr-2160 fi-snb-2520m fi-ctg-p8600 fi-whl-u fi-bsw-kefka fi-skl-lmem fi-byt-n2820 fi-byt-clapper fi-bdw-samus fi-kbl-r > > > Build changes > ------------- > > * CI: CI-20190529 -> None > * IGT: IGT_5352 -> IGTPW_3889 > > CI-20190529: 20190529 > CI_DRM_7651: dcd9b47d596ff82b9768f1ecba436ef03073c211 @ git://anongit.freedesktop.org/gfx-ci/linux > IGTPW_3889: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html > IGT_5352: 0586d205f651674e575351c2d5a7d0760716c9f1 @ > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for lib: Add support and coverage for MC YUV formats 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (10 preceding siblings ...) 2019-12-30 4:12 ` [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add support and coverage for MC YUV formats Patchwork @ 2019-12-30 9:18 ` Patchwork 2019-12-30 12:50 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork ` (3 subsequent siblings) 15 siblings, 0 replies; 33+ messages in thread From: Patchwork @ 2019-12-30 9:18 UTC (permalink / raw) To: Imre Deak; +Cc: igt-dev == Series Details == Series: lib: Add support and coverage for MC YUV formats URL : https://patchwork.freedesktop.org/series/71483/ State : success == Summary == CI Bug Log - changes from CI_DRM_7651 -> IGTPW_3889 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html Known issues ------------ Here are the changes found in IGTPW_3889 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_pm_rpm@module-reload: - fi-skl-6600u: [PASS][1] -> [DMESG-WARN][2] ([i915#889]) +23 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live_gem_contexts: - fi-byt-j1900: [PASS][3] -> [DMESG-FAIL][4] ([i915#722]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gt_lrc: - fi-skl-6600u: [PASS][5] -> [DMESG-FAIL][6] ([i915#889]) +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html #### Possible fixes #### * igt@i915_module_load@reload-with-fault-injection: - fi-bxt-dsi: [INCOMPLETE][7] ([fdo#103927]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html * igt@kms_busy@basic-flip-pipe-a: - {fi-tgl-guc}: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-tgl-guc/igt@kms_busy@basic-flip-pipe-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-tgl-guc/igt@kms_busy@basic-flip-pipe-a.html #### Warnings #### * igt@gem_exec_suspend@basic-s4-devices: - fi-kbl-x1275: [DMESG-WARN][11] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([fdo#107139] / [i915#62] / [i915#92]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html * igt@kms_flip@basic-flip-vs-wf_vblank: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 33) ------------------------------ Additional (4): fi-hsw-4770r fi-skl-6770hq fi-bsw-nick fi-hsw-4770 Missing (15): fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-bwr-2160 fi-snb-2520m fi-ctg-p8600 fi-whl-u fi-bsw-kefka fi-skl-lmem fi-byt-n2820 fi-byt-clapper fi-bdw-samus fi-kbl-r Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5352 -> IGTPW_3889 CI-20190529: 20190529 CI_DRM_7651: dcd9b47d596ff82b9768f1ecba436ef03073c211 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3889: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html IGT_5352: 0586d205f651674e575351c2d5a7d0760716c9f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for lib: Add support and coverage for MC YUV formats 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (11 preceding siblings ...) 2019-12-30 9:18 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork @ 2019-12-30 12:50 ` Patchwork 2019-12-30 13:23 ` Imre Deak 2019-12-30 15:53 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork ` (2 subsequent siblings) 15 siblings, 1 reply; 33+ messages in thread From: Patchwork @ 2019-12-30 12:50 UTC (permalink / raw) To: Imre Deak; +Cc: igt-dev == Series Details == Series: lib: Add support and coverage for MC YUV formats URL : https://patchwork.freedesktop.org/series/71483/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7651_full -> IGTPW_3889_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_3889_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_3889_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_3889_full: ### IGT changes ### #### Possible regressions #### * igt@gem_blits@basic: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl3/igt@gem_blits@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl6/igt@gem_blits@basic.html * igt@gem_set_tiling_vs_blt@tiled-to-untiled: - shard-snb: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb1/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb2/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html Known issues ------------ Here are the changes found in IGTPW_3889_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@vcs0-s3: - shard-kbl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103665]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl2/igt@gem_ctx_isolation@vcs0-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl4/igt@gem_ctx_isolation@vcs0-s3.html * igt@gem_ctx_isolation@vcs1-clean: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb4/igt@gem_ctx_isolation@vcs1-clean.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb8/igt@gem_ctx_isolation@vcs1-clean.html * igt@gem_ctx_persistence@bcs0-mixed-process: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#679]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@gem_ctx_persistence@bcs0-mixed-process.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb5/igt@gem_ctx_persistence@bcs0-mixed-process.html * igt@gem_eio@kms: - shard-snb: [PASS][11] -> [INCOMPLETE][12] ([i915#82]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb6/igt@gem_eio@kms.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb1/igt@gem_eio@kms.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +6 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html * igt@i915_pm_rps@waitboost: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#413]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@i915_pm_rps@waitboost.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb6/igt@i915_pm_rps@waitboost.html * igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding: - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html - shard-apl: [PASS][19] -> [FAIL][20] ([i915#54]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@perf_pmu@init-busy-vcs1: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#112080]) +12 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb2/igt@perf_pmu@init-busy-vcs1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@perf_pmu@init-busy-vcs1.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109276]) +18 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html #### Possible fixes #### * igt@gem_ctx_persistence@bcs0-mixed-process: - shard-apl: [FAIL][31] ([i915#679]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl6/igt@gem_ctx_persistence@bcs0-mixed-process.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl4/igt@gem_ctx_persistence@bcs0-mixed-process.html * igt@gem_ctx_persistence@vcs1-mixed: - shard-iclb: [SKIP][33] ([fdo#109276] / [fdo#112080]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed.html * igt@gem_eio@unwedge-stress: - shard-snb: [FAIL][35] ([i915#232]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb7/igt@gem_eio@unwedge-stress.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb4/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][37] ([fdo#110854]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb8/igt@gem_exec_balancer@smoke.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb4/igt@gem_exec_balancer@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [SKIP][39] ([fdo#112080]) -> [PASS][40] +6 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@gem_exec_parallel@vcs1-fds.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html * {igt@gem_exec_schedule@pi-common-bsd}: - shard-iclb: [SKIP][41] ([i915#677]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@gem_exec_schedule@pi-common-bsd.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [SKIP][43] ([fdo#112146]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [FAIL][45] ([i915#644]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html - shard-apl: [FAIL][47] ([i915#644]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl1/igt@gem_ppgtt@flink-and-close-vma-leak.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl8/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@gem_render_copy_redux@interruptible: - shard-hsw: [FAIL][49] ([i915#910]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-hsw5/igt@gem_render_copy_redux@interruptible.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-hsw7/igt@gem_render_copy_redux@interruptible.html * igt@gem_userptr_blits@dmabuf-sync: - shard-snb: [DMESG-WARN][51] ([fdo#111870]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb7/igt@gem_userptr_blits@dmabuf-sync.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb2/igt@gem_userptr_blits@dmabuf-sync.html * igt@i915_pm_rps@reset: - shard-iclb: [FAIL][53] ([i915#413]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb7/igt@i915_pm_rps@reset.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb1/igt@i915_pm_rps@reset.html * igt@i915_selftest@mock_requests: - shard-glk: [INCOMPLETE][55] ([i915#58] / [k.org#198133]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk4/igt@i915_selftest@mock_requests.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk4/igt@i915_selftest@mock_requests.html * igt@kms_big_fb@x-tiled-8bpp-rotate-0: - shard-snb: [SKIP][57] ([fdo#109271]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-kbl: [FAIL][59] ([i915#54]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html - shard-apl: [FAIL][61] ([i915#54]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt@kms_flip@2x-plain-flip-ts-check-interruptible: - shard-glk: [FAIL][63] ([i915#34]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk7/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [DMESG-WARN][65] ([i915#180]) -> [PASS][66] +3 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html - shard-kbl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +5 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt: - shard-glk: [FAIL][69] ([i915#49]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][71] ([fdo#109441]) -> [PASS][72] +2 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_setmode@basic: - shard-apl: [FAIL][73] ([i915#31]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl3/igt@kms_setmode@basic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl2/igt@kms_setmode@basic.html * igt@prime_busy@hang-bsd2: - shard-iclb: [SKIP][75] ([fdo#109276]) -> [PASS][76] +14 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@prime_busy@hang-bsd2.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb4/igt@prime_busy@hang-bsd2.html #### Warnings #### * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-snb: [DMESG-WARN][77] ([fdo#111870]) -> [DMESG-WARN][78] ([fdo#110789] / [fdo#111870]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34 [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644 [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677 [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#910]: https://gitlab.freedesktop.org/drm/intel/issues/910 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 8) ------------------------------ Missing (3): pig-skl-6260u pig-glk-j5005 pig-hsw-4770r Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5352 -> IGTPW_3889 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_7651: dcd9b47d596ff82b9768f1ecba436ef03073c211 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3889: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html IGT_5352: 0586d205f651674e575351c2d5a7d0760716c9f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [igt-dev] ✗ Fi.CI.IGT: failure for lib: Add support and coverage for MC YUV formats 2019-12-30 12:50 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork @ 2019-12-30 13:23 ` Imre Deak 0 siblings, 0 replies; 33+ messages in thread From: Imre Deak @ 2019-12-30 13:23 UTC (permalink / raw) To: igt-dev, Lakshminarayana Vudum On Mon, Dec 30, 2019 at 12:50:01PM +0000, Patchwork wrote: > == Series Details == > > Series: lib: Add support and coverage for MC YUV formats > URL : https://patchwork.freedesktop.org/series/71483/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7651_full -> IGTPW_3889_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with IGTPW_3889_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in IGTPW_3889_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in IGTPW_3889_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@gem_blits@basic: > - shard-kbl: [PASS][1] -> [DMESG-WARN][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl3/igt@gem_blits@basic.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl6/igt@gem_blits@basic.html This looks like https://gitlab.freedesktop.org/drm/intel/issues/836 at least on the locking scenario. > > * igt@gem_set_tiling_vs_blt@tiled-to-untiled: > - shard-snb: [PASS][3] -> [DMESG-WARN][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb1/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb2/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html and this one is like https://gitlab.freedesktop.org/drm/intel/issues/793 again just based on locking scenario. > > > Known issues > ------------ > > Here are the changes found in IGTPW_3889_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_ctx_isolation@vcs0-s3: > - shard-kbl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103665]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl2/igt@gem_ctx_isolation@vcs0-s3.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl4/igt@gem_ctx_isolation@vcs0-s3.html > > * igt@gem_ctx_isolation@vcs1-clean: > - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080]) +1 similar issue > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb4/igt@gem_ctx_isolation@vcs1-clean.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb8/igt@gem_ctx_isolation@vcs1-clean.html > > * igt@gem_ctx_persistence@bcs0-mixed-process: > - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#679]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@gem_ctx_persistence@bcs0-mixed-process.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb5/igt@gem_ctx_persistence@bcs0-mixed-process.html > > * igt@gem_eio@kms: > - shard-snb: [PASS][11] -> [INCOMPLETE][12] ([i915#82]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb6/igt@gem_eio@kms.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb1/igt@gem_eio@kms.html > > * igt@gem_exec_schedule@reorder-wide-bsd: > - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +6 similar issues > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html > > * igt@i915_pm_rps@waitboost: > - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#413]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@i915_pm_rps@waitboost.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb6/igt@i915_pm_rps@waitboost.html > > * igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding: > - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#54]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html > - shard-apl: [PASS][19] -> [FAIL][20] ([i915#54]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html > > * igt@kms_cursor_crc@pipe-c-cursor-suspend: > - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +3 similar issues > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html > > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: > - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +3 similar issues > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > > * igt@kms_psr@psr2_cursor_mmap_cpu: > - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html > > * igt@perf_pmu@init-busy-vcs1: > - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#112080]) +12 similar issues > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb2/igt@perf_pmu@init-busy-vcs1.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@perf_pmu@init-busy-vcs1.html > > * igt@prime_vgem@fence-wait-bsd2: > - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109276]) +18 similar issues > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html > > > #### Possible fixes #### > > * igt@gem_ctx_persistence@bcs0-mixed-process: > - shard-apl: [FAIL][31] ([i915#679]) -> [PASS][32] > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl6/igt@gem_ctx_persistence@bcs0-mixed-process.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl4/igt@gem_ctx_persistence@bcs0-mixed-process.html > > * igt@gem_ctx_persistence@vcs1-mixed: > - shard-iclb: [SKIP][33] ([fdo#109276] / [fdo#112080]) -> [PASS][34] > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed.html > > * igt@gem_eio@unwedge-stress: > - shard-snb: [FAIL][35] ([i915#232]) -> [PASS][36] > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb7/igt@gem_eio@unwedge-stress.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb4/igt@gem_eio@unwedge-stress.html > > * igt@gem_exec_balancer@smoke: > - shard-iclb: [SKIP][37] ([fdo#110854]) -> [PASS][38] > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb8/igt@gem_exec_balancer@smoke.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb4/igt@gem_exec_balancer@smoke.html > > * igt@gem_exec_parallel@vcs1-fds: > - shard-iclb: [SKIP][39] ([fdo#112080]) -> [PASS][40] +6 similar issues > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@gem_exec_parallel@vcs1-fds.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html > > * {igt@gem_exec_schedule@pi-common-bsd}: > - shard-iclb: [SKIP][41] ([i915#677]) -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@gem_exec_schedule@pi-common-bsd.html > > * igt@gem_exec_schedule@wide-bsd: > - shard-iclb: [SKIP][43] ([fdo#112146]) -> [PASS][44] +2 similar issues > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html > > * igt@gem_ppgtt@flink-and-close-vma-leak: > - shard-glk: [FAIL][45] ([i915#644]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html > - shard-apl: [FAIL][47] ([i915#644]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl1/igt@gem_ppgtt@flink-and-close-vma-leak.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl8/igt@gem_ppgtt@flink-and-close-vma-leak.html > > * igt@gem_render_copy_redux@interruptible: > - shard-hsw: [FAIL][49] ([i915#910]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-hsw5/igt@gem_render_copy_redux@interruptible.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-hsw7/igt@gem_render_copy_redux@interruptible.html > > * igt@gem_userptr_blits@dmabuf-sync: > - shard-snb: [DMESG-WARN][51] ([fdo#111870]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb7/igt@gem_userptr_blits@dmabuf-sync.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb2/igt@gem_userptr_blits@dmabuf-sync.html > > * igt@i915_pm_rps@reset: > - shard-iclb: [FAIL][53] ([i915#413]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb7/igt@i915_pm_rps@reset.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb1/igt@i915_pm_rps@reset.html > > * igt@i915_selftest@mock_requests: > - shard-glk: [INCOMPLETE][55] ([i915#58] / [k.org#198133]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk4/igt@i915_selftest@mock_requests.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk4/igt@i915_selftest@mock_requests.html > > * igt@kms_big_fb@x-tiled-8bpp-rotate-0: > - shard-snb: [SKIP][57] ([fdo#109271]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html > > * igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen: > - shard-kbl: [FAIL][59] ([i915#54]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html > - shard-apl: [FAIL][61] ([i915#54]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html > > * igt@kms_flip@2x-plain-flip-ts-check-interruptible: > - shard-glk: [FAIL][63] ([i915#34]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk7/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html > > * igt@kms_flip@flip-vs-suspend-interruptible: > - shard-apl: [DMESG-WARN][65] ([i915#180]) -> [PASS][66] +3 similar issues > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html > - shard-kbl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +5 similar issues > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html > > * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt: > - shard-glk: [FAIL][69] ([i915#49]) -> [PASS][70] > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html > > * igt@kms_psr@psr2_cursor_plane_move: > - shard-iclb: [SKIP][71] ([fdo#109441]) -> [PASS][72] +2 similar issues > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html > > * igt@kms_setmode@basic: > - shard-apl: [FAIL][73] ([i915#31]) -> [PASS][74] > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl3/igt@kms_setmode@basic.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl2/igt@kms_setmode@basic.html > > * igt@prime_busy@hang-bsd2: > - shard-iclb: [SKIP][75] ([fdo#109276]) -> [PASS][76] +14 similar issues > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@prime_busy@hang-bsd2.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb4/igt@prime_busy@hang-bsd2.html > > > #### Warnings #### > > * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: > - shard-snb: [DMESG-WARN][77] ([fdo#111870]) -> [DMESG-WARN][78] ([fdo#110789] / [fdo#111870]) > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789 > [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 > [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 > [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 > [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34 > [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 > [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644 > [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677 > [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#910]: https://gitlab.freedesktop.org/drm/intel/issues/910 > [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > Participating hosts (11 -> 8) > ------------------------------ > > Missing (3): pig-skl-6260u pig-glk-j5005 pig-hsw-4770r > > > Build changes > ------------- > > * CI: CI-20190529 -> None > * IGT: IGT_5352 -> IGTPW_3889 > * Piglit: piglit_4509 -> None > > CI-20190529: 20190529 > CI_DRM_7651: dcd9b47d596ff82b9768f1ecba436ef03073c211 @ git://anongit.freedesktop.org/gfx-ci/linux > IGTPW_3889: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html > IGT_5352: 0586d205f651674e575351c2d5a7d0760716c9f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for lib: Add support and coverage for MC YUV formats 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (12 preceding siblings ...) 2019-12-30 12:50 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork @ 2019-12-30 15:53 ` Patchwork 2019-12-30 19:02 ` [igt-dev] ✓ Fi.CI.BAT: success for lib: Add support and coverage for MC YUV formats (rev3) Patchwork 2019-12-31 8:45 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 15 siblings, 0 replies; 33+ messages in thread From: Patchwork @ 2019-12-30 15:53 UTC (permalink / raw) To: Imre Deak; +Cc: igt-dev == Series Details == Series: lib: Add support and coverage for MC YUV formats URL : https://patchwork.freedesktop.org/series/71483/ State : success == Summary == CI Bug Log - changes from CI_DRM_7651_full -> IGTPW_3889_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html Known issues ------------ Here are the changes found in IGTPW_3889_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_blits@basic: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#836]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl3/igt@gem_blits@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl6/igt@gem_blits@basic.html * igt@gem_ctx_isolation@vcs0-s3: - shard-kbl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103665]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl2/igt@gem_ctx_isolation@vcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl4/igt@gem_ctx_isolation@vcs0-s3.html * igt@gem_ctx_isolation@vcs1-clean: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb4/igt@gem_ctx_isolation@vcs1-clean.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb8/igt@gem_ctx_isolation@vcs1-clean.html * igt@gem_ctx_persistence@bcs0-mixed-process: - shard-iclb: [PASS][7] -> [FAIL][8] ([i915#679]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@gem_ctx_persistence@bcs0-mixed-process.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb5/igt@gem_ctx_persistence@bcs0-mixed-process.html * igt@gem_eio@kms: - shard-snb: [PASS][9] -> [INCOMPLETE][10] ([i915#82]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb6/igt@gem_eio@kms.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb1/igt@gem_eio@kms.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html * igt@gem_set_tiling_vs_blt@tiled-to-untiled: - shard-snb: [PASS][13] -> [DMESG-WARN][14] ([i915#793]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb1/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb2/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html * igt@i915_pm_rps@waitboost: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#413]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@i915_pm_rps@waitboost.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb6/igt@i915_pm_rps@waitboost.html * igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding: - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html - shard-apl: [PASS][19] -> [FAIL][20] ([i915#54]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@perf_pmu@init-busy-vcs1: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#112080]) +12 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb2/igt@perf_pmu@init-busy-vcs1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@perf_pmu@init-busy-vcs1.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109276]) +18 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html #### Possible fixes #### * igt@gem_ctx_persistence@bcs0-mixed-process: - shard-apl: [FAIL][31] ([i915#679]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl6/igt@gem_ctx_persistence@bcs0-mixed-process.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl4/igt@gem_ctx_persistence@bcs0-mixed-process.html * igt@gem_ctx_persistence@vcs1-mixed: - shard-iclb: [SKIP][33] ([fdo#109276] / [fdo#112080]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed.html * igt@gem_eio@unwedge-stress: - shard-snb: [FAIL][35] ([i915#232]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb7/igt@gem_eio@unwedge-stress.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb4/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][37] ([fdo#110854]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb8/igt@gem_exec_balancer@smoke.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb4/igt@gem_exec_balancer@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [SKIP][39] ([fdo#112080]) -> [PASS][40] +6 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@gem_exec_parallel@vcs1-fds.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html * {igt@gem_exec_schedule@pi-common-bsd}: - shard-iclb: [SKIP][41] ([i915#677]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@gem_exec_schedule@pi-common-bsd.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [SKIP][43] ([fdo#112146]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [FAIL][45] ([i915#644]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html - shard-apl: [FAIL][47] ([i915#644]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl1/igt@gem_ppgtt@flink-and-close-vma-leak.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl8/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@gem_render_copy_redux@interruptible: - shard-hsw: [FAIL][49] ([i915#910]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-hsw5/igt@gem_render_copy_redux@interruptible.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-hsw7/igt@gem_render_copy_redux@interruptible.html * igt@gem_userptr_blits@dmabuf-sync: - shard-snb: [DMESG-WARN][51] ([fdo#111870]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb7/igt@gem_userptr_blits@dmabuf-sync.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb2/igt@gem_userptr_blits@dmabuf-sync.html * igt@i915_pm_rps@reset: - shard-iclb: [FAIL][53] ([i915#413]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb7/igt@i915_pm_rps@reset.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb1/igt@i915_pm_rps@reset.html * igt@i915_selftest@mock_requests: - shard-glk: [INCOMPLETE][55] ([i915#58] / [k.org#198133]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk4/igt@i915_selftest@mock_requests.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk4/igt@i915_selftest@mock_requests.html * igt@kms_big_fb@x-tiled-8bpp-rotate-0: - shard-snb: [SKIP][57] ([fdo#109271]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-kbl: [FAIL][59] ([i915#54]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html - shard-apl: [FAIL][61] ([i915#54]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt@kms_flip@2x-plain-flip-ts-check-interruptible: - shard-glk: [FAIL][63] ([i915#34]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk7/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [DMESG-WARN][65] ([i915#180]) -> [PASS][66] +3 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html - shard-kbl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +5 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt: - shard-glk: [FAIL][69] ([i915#49]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-glk2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][71] ([fdo#109441]) -> [PASS][72] +2 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_setmode@basic: - shard-apl: [FAIL][73] ([i915#31]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-apl3/igt@kms_setmode@basic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-apl2/igt@kms_setmode@basic.html * igt@prime_busy@hang-bsd2: - shard-iclb: [SKIP][75] ([fdo#109276]) -> [PASS][76] +14 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-iclb5/igt@prime_busy@hang-bsd2.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-iclb4/igt@prime_busy@hang-bsd2.html #### Warnings #### * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-snb: [DMESG-WARN][77] ([fdo#111870]) -> [DMESG-WARN][78] ([fdo#110789] / [fdo#111870]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7651/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34 [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644 [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677 [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679 [i915#793]: https://gitlab.freedesktop.org/drm/intel/issues/793 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#836]: https://gitlab.freedesktop.org/drm/intel/issues/836 [i915#910]: https://gitlab.freedesktop.org/drm/intel/issues/910 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 8) ------------------------------ Missing (3): pig-skl-6260u pig-glk-j5005 pig-hsw-4770r Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5352 -> IGTPW_3889 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_7651: dcd9b47d596ff82b9768f1ecba436ef03073c211 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3889: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html IGT_5352: 0586d205f651674e575351c2d5a7d0760716c9f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3889/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for lib: Add support and coverage for MC YUV formats (rev3) 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (13 preceding siblings ...) 2019-12-30 15:53 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork @ 2019-12-30 19:02 ` Patchwork 2019-12-31 8:45 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 15 siblings, 0 replies; 33+ messages in thread From: Patchwork @ 2019-12-30 19:02 UTC (permalink / raw) To: Imre Deak; +Cc: igt-dev == Series Details == Series: lib: Add support and coverage for MC YUV formats (rev3) URL : https://patchwork.freedesktop.org/series/71483/ State : success == Summary == CI Bug Log - changes from CI_DRM_7656 -> IGTPW_3892 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/index.html Known issues ------------ Here are the changes found in IGTPW_3892 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] ([i915#671] / [i915#69]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-skl-6600u/igt@i915_module_load@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-skl-6600u/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-ivb-3770: [PASS][3] -> [DMESG-FAIL][4] ([i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-ivb-3770/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-byt-j1900: [PASS][5] -> [DMESG-FAIL][6] ([i915#722]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html #### Possible fixes #### * igt@gem_close_race@basic-threads: - fi-byt-j1900: [TIMEOUT][7] ([i915#816]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-byt-j1900/igt@gem_close_race@basic-threads.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-byt-j1900/igt@gem_close_race@basic-threads.html * igt@i915_module_load@reload-with-fault-injection: - fi-skl-lmem: [INCOMPLETE][9] ([i915#671]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-skl-lmem/igt@i915_module_load@reload-with-fault-injection.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-skl-lmem/igt@i915_module_load@reload-with-fault-injection.html - fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-byt-j1900: [DMESG-FAIL][13] ([i915#725]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-byt-j1900/igt@i915_selftest@live_blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-byt-j1900/igt@i915_selftest@live_blt.html * igt@kms_busy@basic-flip-pipe-a: - {fi-tgl-guc}: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-tgl-guc/igt@kms_busy@basic-flip-pipe-a.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-tgl-guc/igt@kms_busy@basic-flip-pipe-a.html #### Warnings #### * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-kbl-x1275/igt@i915_pm_rpm@basic-pci-d3-state.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-kbl-x1275/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@i915_selftest@live_blt: - fi-hsw-4770: [DMESG-FAIL][19] ([i915#563]) -> [DMESG-FAIL][20] ([i915#553] / [i915#725]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-hsw-4770/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (46 -> 43) ------------------------------ Additional (5): fi-byt-n2820 fi-bwr-2160 fi-bsw-kefka fi-kbl-7560u fi-tgl-y Missing (8): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5355 -> IGTPW_3892 CI-20190529: 20190529 CI_DRM_7656: 635576de746ef28c1635b4cf4fb12f4db1104f8b @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3892: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/index.html IGT_5355: 2ead76177f2546d3eec0abbd0d9e47cd36588199 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for lib: Add support and coverage for MC YUV formats (rev3) 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak ` (14 preceding siblings ...) 2019-12-30 19:02 ` [igt-dev] ✓ Fi.CI.BAT: success for lib: Add support and coverage for MC YUV formats (rev3) Patchwork @ 2019-12-31 8:45 ` Patchwork 2019-12-31 12:49 ` Imre Deak 15 siblings, 1 reply; 33+ messages in thread From: Patchwork @ 2019-12-31 8:45 UTC (permalink / raw) To: Imre Deak; +Cc: igt-dev == Series Details == Series: lib: Add support and coverage for MC YUV formats (rev3) URL : https://patchwork.freedesktop.org/series/71483/ State : success == Summary == CI Bug Log - changes from CI_DRM_7656_full -> IGTPW_3892_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/index.html Known issues ------------ Here are the changes found in IGTPW_3892_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-apl4/igt@gem_ctx_isolation@rcs0-s3.html * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb3/igt@gem_ctx_isolation@vcs1-dirty-create.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb2/igt@gem_exec_balancer@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb5/igt@gem_exec_balancer@smoke.html * igt@gem_exec_create@basic: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111736]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_exec_create@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb5/igt@gem_exec_create@basic.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd2: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +18 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd2.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd2.html * igt@gem_exec_schedule@preempt-queue-chain-bsd2: - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111677]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb9/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb9/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html * igt@gem_exec_schedule@preempt-queue-chain-render: - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111606] / [fdo#111677]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_exec_schedule@preempt-queue-chain-render.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb3/igt@gem_exec_schedule@preempt-queue-chain-render.html * igt@gem_exec_schedule@smoketest-bsd1: - shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([i915#463]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb1/igt@gem_exec_schedule@smoketest-bsd1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb3/igt@gem_exec_schedule@smoketest-bsd1.html * igt@gem_exec_suspend@basic-s0: - shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#472]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb9/igt@gem_exec_suspend@basic-s0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb3/igt@gem_exec_suspend@basic-s0.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-snb: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html * igt@i915_pm_dc@dc5-dpms: - shard-iclb: [PASS][23] -> [FAIL][24] ([i915#447]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb1/igt@i915_pm_dc@dc5-dpms.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html * igt@i915_selftest@mock_requests: - shard-apl: [PASS][25] -> [INCOMPLETE][26] ([fdo#103927]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-apl4/igt@i915_selftest@mock_requests.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-apl3/igt@i915_selftest@mock_requests.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding: - shard-glk: [PASS][27] -> [FAIL][28] ([i915#54]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-glk2/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-glk3/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][29] -> [FAIL][30] ([i915#79]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite: - shard-tglb: [PASS][31] -> [FAIL][32] ([i915#49]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +4 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_psr@psr2_suspend: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb2/igt@kms_psr@psr2_suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb3/igt@kms_psr@psr2_suspend.html * igt@perf@short-reads: - shard-kbl: [PASS][37] -> [TIMEOUT][38] ([i915#51]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-kbl4/igt@perf@short-reads.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-kbl1/igt@perf@short-reads.html * igt@perf_pmu@busy-no-semaphores-vcs1: - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#112080]) +6 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html * igt@perf_pmu@enable-race-vcs0: - shard-tglb: [PASS][41] -> [INCOMPLETE][42] ([i915#480]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@perf_pmu@enable-race-vcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb2/igt@perf_pmu@enable-race-vcs0.html #### Possible fixes #### * igt@gem_ctx_isolation@vcs1-none: - shard-iclb: [SKIP][43] ([fdo#109276] / [fdo#112080]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb3/igt@gem_ctx_isolation@vcs1-none.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb4/igt@gem_ctx_isolation@vcs1-none.html * igt@gem_eio@kms: - shard-tglb: [INCOMPLETE][45] ([i915#476]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb1/igt@gem_eio@kms.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb8/igt@gem_eio@kms.html * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [SKIP][47] ([fdo#112146]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb2/igt@gem_exec_schedule@in-order-bsd.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb6/igt@gem_exec_schedule@in-order-bsd.html * {igt@gem_exec_schedule@pi-userfault-bsd}: - shard-iclb: [SKIP][49] ([i915#677]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb4/igt@gem_exec_schedule@pi-userfault-bsd.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb6/igt@gem_exec_schedule@pi-userfault-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [SKIP][51] ([fdo#109276]) -> [PASS][52] +18 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html * igt@gem_exec_schedule@preempt-queue-chain-vebox: - shard-tglb: [INCOMPLETE][53] ([fdo#111677]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_exec_schedule@preempt-queue-chain-vebox.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb9/igt@gem_exec_schedule@preempt-queue-chain-vebox.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-blt: - shard-tglb: [INCOMPLETE][55] ([fdo#111606] / [fdo#111677]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb1/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html * igt@gem_exec_schedule@smoketest-blt: - shard-tglb: [INCOMPLETE][57] ([i915#470]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb3/igt@gem_exec_schedule@smoketest-blt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb3/igt@gem_exec_schedule@smoketest-blt.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-snb: [FAIL][59] ([i915#520]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-snb2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html - shard-tglb: [FAIL][61] ([i915#520]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb9/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [FAIL][63] ([i915#644]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@gem_sync@basic-all: - shard-tglb: [INCOMPLETE][65] ([i915#470] / [i915#472]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb5/igt@gem_sync@basic-all.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb1/igt@gem_sync@basic-all.html * igt@gem_sync@basic-store-each: - shard-tglb: [INCOMPLETE][67] ([i915#435] / [i915#472]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_sync@basic-store-each.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb2/igt@gem_sync@basic-store-each.html * igt@gem_tiled_wc: - shard-snb: [DMESG-WARN][69] ([i915#915]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb4/igt@gem_tiled_wc.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-snb4/igt@gem_tiled_wc.html * igt@gem_userptr_blits@sync-unmap: - shard-snb: [DMESG-WARN][71] ([fdo#111870]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb5/igt@gem_userptr_blits@sync-unmap.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-snb2/igt@gem_userptr_blits@sync-unmap.html * igt@i915_hangman@error-state-capture-vcs1: - shard-iclb: [SKIP][73] ([fdo#112080]) -> [PASS][74] +8 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb7/igt@i915_hangman@error-state-capture-vcs1.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb2/igt@i915_hangman@error-state-capture-vcs1.html * igt@i915_pm_rps@waitboost: - shard-iclb: [FAIL][75] ([i915#413]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb7/igt@i915_pm_rps@waitboost.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb6/igt@i915_pm_rps@waitboost.html * igt@i915_selftest@live_requests: - shard-tglb: [INCOMPLETE][77] ([i915#472]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb9/igt@i915_selftest@live_requests.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb8/igt@i915_selftest@live_requests.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-kbl: [FAIL][79] ([i915#79]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@basic: - shard-glk: [FAIL][81] ([i915#49]) -> [PASS][82] [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-glk1/igt@kms_frontbuffer_tracking@basic.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-glk6/igt@kms_frontbuffer_tracking@basic.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite: - shard-tglb: [FAIL][83] ([i915#49]) -> [PASS][84] +1 similar issue [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [DMESG-WARN][85] ([i915#180]) -> [PASS][86] +2 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][87] ([fdo#109441]) -> [PASS][88] +3 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_setmode@basic: - shard-apl: [FAIL][89] ([i915#31]) -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-apl6/igt@kms_setmode@basic.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-apl8/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][91] ([i915#180]) -> [PASS][92] +3 similar issues [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html #### Warnings #### * igt@gem_ctx_isolation@vcs1-nonpriv: - shard-iclb: [SKIP][93] ([fdo#109276] / [fdo#112080]) -> [FAIL][94] ([IGT#28]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html * igt@gem_eio@kms: - shard-snb: [INCOMPLETE][95] ([i915#82]) -> [DMESG-WARN][96] ([i915#444] / [i915#503]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb4/igt@gem_eio@kms.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-snb4/igt@gem_eio@kms.html * igt@gem_tiled_blits@interruptible: - shard-hsw: [FAIL][97] ([i915#832]) -> [FAIL][98] ([i915#818]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-hsw6/igt@gem_tiled_blits@interruptible.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-hsw5/igt@gem_tiled_blits@interruptible.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [INCOMPLETE][99] ([fdo#103665]) -> [DMESG-WARN][100] ([i915#180]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-kbl6/igt@i915_suspend@debugfs-reader.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-kbl4/igt@i915_suspend@debugfs-reader.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][101] ([fdo#109349]) -> [DMESG-WARN][102] ([fdo#107724]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html * igt@kms_flip@flip-vs-suspend: - shard-apl: [DMESG-WARN][103] ([i915#180]) -> [FAIL][104] ([fdo#103375]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-apl1/igt@kms_flip@flip-vs-suspend.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-apl4/igt@kms_flip@flip-vs-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606 [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677 [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736 [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413 [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435 [i915#444]: https://gitlab.freedesktop.org/drm/intel/issues/444 [i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447 [i915#463]: https://gitlab.freedesktop.org/drm/intel/issues/463 [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470 [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472 [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476 [i915#480]: https://gitlab.freedesktop.org/drm/intel/issues/480 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#503]: https://gitlab.freedesktop.org/drm/intel/issues/503 [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51 [i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644 [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#832]: https://gitlab.freedesktop.org/drm/intel/issues/832 [i915#915]: https://gitlab.freedesktop.org/drm/intel/issues/915 Participating hosts (10 -> 8) ------------------------------ Missing (2): pig-skl-6260u pig-glk-j5005 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5355 -> IGTPW_3892 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_7656: 635576de746ef28c1635b4cf4fb12f4db1104f8b @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3892: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/index.html IGT_5355: 2ead76177f2546d3eec0abbd0d9e47cd36588199 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [igt-dev] ✓ Fi.CI.IGT: success for lib: Add support and coverage for MC YUV formats (rev3) 2019-12-31 8:45 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork @ 2019-12-31 12:49 ` Imre Deak 0 siblings, 0 replies; 33+ messages in thread From: Imre Deak @ 2019-12-31 12:49 UTC (permalink / raw) To: igt-dev, Mika Kahola, Juha-Pekka Heikkilä On Tue, Dec 31, 2019 at 08:45:26AM +0000, Patchwork wrote: > == Series Details == > > Series: lib: Add support and coverage for MC YUV formats (rev3) > URL : https://patchwork.freedesktop.org/series/71483/ > State : success Patchset pushed, thanks for the reviews. > > == Summary == > > CI Bug Log - changes from CI_DRM_7656_full -> IGTPW_3892_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/index.html > > Known issues > ------------ > > Here are the changes found in IGTPW_3892_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_ctx_isolation@rcs0-s3: > - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +4 similar issues > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-apl4/igt@gem_ctx_isolation@rcs0-s3.html > > * igt@gem_ctx_isolation@vcs1-dirty-create: > - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +3 similar issues > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb3/igt@gem_ctx_isolation@vcs1-dirty-create.html > > * igt@gem_exec_balancer@smoke: > - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb2/igt@gem_exec_balancer@smoke.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb5/igt@gem_exec_balancer@smoke.html > > * igt@gem_exec_create@basic: > - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111736]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_exec_create@basic.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb5/igt@gem_exec_create@basic.html > > * igt@gem_exec_schedule@preempt-other-chain-bsd: > - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +7 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html > > * igt@gem_exec_schedule@preempt-queue-bsd2: > - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +18 similar issues > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd2.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd2.html > > * igt@gem_exec_schedule@preempt-queue-chain-bsd2: > - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111677]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb9/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb9/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html > > * igt@gem_exec_schedule@preempt-queue-chain-render: > - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111606] / [fdo#111677]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_exec_schedule@preempt-queue-chain-render.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb3/igt@gem_exec_schedule@preempt-queue-chain-render.html > > * igt@gem_exec_schedule@smoketest-bsd1: > - shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([i915#463]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb1/igt@gem_exec_schedule@smoketest-bsd1.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb3/igt@gem_exec_schedule@smoketest-bsd1.html > > * igt@gem_exec_suspend@basic-s0: > - shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#472]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb9/igt@gem_exec_suspend@basic-s0.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb3/igt@gem_exec_suspend@basic-s0.html > > * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: > - shard-snb: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870]) +1 similar issue > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html > > * igt@i915_pm_dc@dc5-dpms: > - shard-iclb: [PASS][23] -> [FAIL][24] ([i915#447]) > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb1/igt@i915_pm_dc@dc5-dpms.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html > > * igt@i915_selftest@mock_requests: > - shard-apl: [PASS][25] -> [INCOMPLETE][26] ([fdo#103927]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-apl4/igt@i915_selftest@mock_requests.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-apl3/igt@i915_selftest@mock_requests.html > > * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding: > - shard-glk: [PASS][27] -> [FAIL][28] ([i915#54]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-glk2/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-glk3/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html > > * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: > - shard-glk: [PASS][29] -> [FAIL][30] ([i915#79]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite: > - shard-tglb: [PASS][31] -> [FAIL][32] ([i915#49]) > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html > > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: > - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +4 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html > > * igt@kms_psr@psr2_suspend: > - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb2/igt@kms_psr@psr2_suspend.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb3/igt@kms_psr@psr2_suspend.html > > * igt@perf@short-reads: > - shard-kbl: [PASS][37] -> [TIMEOUT][38] ([i915#51]) > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-kbl4/igt@perf@short-reads.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-kbl1/igt@perf@short-reads.html > > * igt@perf_pmu@busy-no-semaphores-vcs1: > - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#112080]) +6 similar issues > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html > > * igt@perf_pmu@enable-race-vcs0: > - shard-tglb: [PASS][41] -> [INCOMPLETE][42] ([i915#480]) > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@perf_pmu@enable-race-vcs0.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb2/igt@perf_pmu@enable-race-vcs0.html > > > #### Possible fixes #### > > * igt@gem_ctx_isolation@vcs1-none: > - shard-iclb: [SKIP][43] ([fdo#109276] / [fdo#112080]) -> [PASS][44] +1 similar issue > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb3/igt@gem_ctx_isolation@vcs1-none.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb4/igt@gem_ctx_isolation@vcs1-none.html > > * igt@gem_eio@kms: > - shard-tglb: [INCOMPLETE][45] ([i915#476]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb1/igt@gem_eio@kms.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb8/igt@gem_eio@kms.html > > * igt@gem_exec_schedule@in-order-bsd: > - shard-iclb: [SKIP][47] ([fdo#112146]) -> [PASS][48] +1 similar issue > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb2/igt@gem_exec_schedule@in-order-bsd.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb6/igt@gem_exec_schedule@in-order-bsd.html > > * {igt@gem_exec_schedule@pi-userfault-bsd}: > - shard-iclb: [SKIP][49] ([i915#677]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb4/igt@gem_exec_schedule@pi-userfault-bsd.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb6/igt@gem_exec_schedule@pi-userfault-bsd.html > > * igt@gem_exec_schedule@preempt-queue-bsd1: > - shard-iclb: [SKIP][51] ([fdo#109276]) -> [PASS][52] +18 similar issues > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html > > * igt@gem_exec_schedule@preempt-queue-chain-vebox: > - shard-tglb: [INCOMPLETE][53] ([fdo#111677]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_exec_schedule@preempt-queue-chain-vebox.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb9/igt@gem_exec_schedule@preempt-queue-chain-vebox.html > > * igt@gem_exec_schedule@preempt-queue-contexts-chain-blt: > - shard-tglb: [INCOMPLETE][55] ([fdo#111606] / [fdo#111677]) -> [PASS][56] +1 similar issue > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb1/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html > > * igt@gem_exec_schedule@smoketest-blt: > - shard-tglb: [INCOMPLETE][57] ([i915#470]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb3/igt@gem_exec_schedule@smoketest-blt.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb3/igt@gem_exec_schedule@smoketest-blt.html > > * igt@gem_persistent_relocs@forked-interruptible-thrashing: > - shard-snb: [FAIL][59] ([i915#520]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-snb2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html > - shard-tglb: [FAIL][61] ([i915#520]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb9/igt@gem_persistent_relocs@forked-interruptible-thrashing.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html > > * igt@gem_ppgtt@flink-and-close-vma-leak: > - shard-glk: [FAIL][63] ([i915#644]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html > > * igt@gem_sync@basic-all: > - shard-tglb: [INCOMPLETE][65] ([i915#470] / [i915#472]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb5/igt@gem_sync@basic-all.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb1/igt@gem_sync@basic-all.html > > * igt@gem_sync@basic-store-each: > - shard-tglb: [INCOMPLETE][67] ([i915#435] / [i915#472]) -> [PASS][68] > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_sync@basic-store-each.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb2/igt@gem_sync@basic-store-each.html > > * igt@gem_tiled_wc: > - shard-snb: [DMESG-WARN][69] ([i915#915]) -> [PASS][70] > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb4/igt@gem_tiled_wc.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-snb4/igt@gem_tiled_wc.html > > * igt@gem_userptr_blits@sync-unmap: > - shard-snb: [DMESG-WARN][71] ([fdo#111870]) -> [PASS][72] > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb5/igt@gem_userptr_blits@sync-unmap.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-snb2/igt@gem_userptr_blits@sync-unmap.html > > * igt@i915_hangman@error-state-capture-vcs1: > - shard-iclb: [SKIP][73] ([fdo#112080]) -> [PASS][74] +8 similar issues > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb7/igt@i915_hangman@error-state-capture-vcs1.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb2/igt@i915_hangman@error-state-capture-vcs1.html > > * igt@i915_pm_rps@waitboost: > - shard-iclb: [FAIL][75] ([i915#413]) -> [PASS][76] > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb7/igt@i915_pm_rps@waitboost.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb6/igt@i915_pm_rps@waitboost.html > > * igt@i915_selftest@live_requests: > - shard-tglb: [INCOMPLETE][77] ([i915#472]) -> [PASS][78] > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb9/igt@i915_selftest@live_requests.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb8/igt@i915_selftest@live_requests.html > > * igt@kms_flip@flip-vs-expired-vblank-interruptible: > - shard-kbl: [FAIL][79] ([i915#79]) -> [PASS][80] > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html > > * igt@kms_frontbuffer_tracking@basic: > - shard-glk: [FAIL][81] ([i915#49]) -> [PASS][82] > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-glk1/igt@kms_frontbuffer_tracking@basic.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-glk6/igt@kms_frontbuffer_tracking@basic.html > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite: > - shard-tglb: [FAIL][83] ([i915#49]) -> [PASS][84] +1 similar issue > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html > > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: > - shard-apl: [DMESG-WARN][85] ([i915#180]) -> [PASS][86] +2 similar issues > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > > * igt@kms_psr@psr2_sprite_plane_move: > - shard-iclb: [SKIP][87] ([fdo#109441]) -> [PASS][88] +3 similar issues > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html > > * igt@kms_setmode@basic: > - shard-apl: [FAIL][89] ([i915#31]) -> [PASS][90] > [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-apl6/igt@kms_setmode@basic.html > [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-apl8/igt@kms_setmode@basic.html > > * igt@kms_vblank@pipe-a-ts-continuation-suspend: > - shard-kbl: [DMESG-WARN][91] ([i915#180]) -> [PASS][92] +3 similar issues > [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html > [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html > > > #### Warnings #### > > * igt@gem_ctx_isolation@vcs1-nonpriv: > - shard-iclb: [SKIP][93] ([fdo#109276] / [fdo#112080]) -> [FAIL][94] ([IGT#28]) > [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html > [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html > > * igt@gem_eio@kms: > - shard-snb: [INCOMPLETE][95] ([i915#82]) -> [DMESG-WARN][96] ([i915#444] / [i915#503]) > [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb4/igt@gem_eio@kms.html > [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-snb4/igt@gem_eio@kms.html > > * igt@gem_tiled_blits@interruptible: > - shard-hsw: [FAIL][97] ([i915#832]) -> [FAIL][98] ([i915#818]) > [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-hsw6/igt@gem_tiled_blits@interruptible.html > [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-hsw5/igt@gem_tiled_blits@interruptible.html > > * igt@i915_suspend@debugfs-reader: > - shard-kbl: [INCOMPLETE][99] ([fdo#103665]) -> [DMESG-WARN][100] ([i915#180]) > [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-kbl6/igt@i915_suspend@debugfs-reader.html > [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-kbl4/igt@i915_suspend@debugfs-reader.html > > * igt@kms_dp_dsc@basic-dsc-enable-edp: > - shard-iclb: [SKIP][101] ([fdo#109349]) -> [DMESG-WARN][102] ([fdo#107724]) > [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html > [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html > > * igt@kms_flip@flip-vs-suspend: > - shard-apl: [DMESG-WARN][103] ([i915#180]) -> [FAIL][104] ([fdo#103375]) > [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-apl1/igt@kms_flip@flip-vs-suspend.html > [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/shard-apl4/igt@kms_flip@flip-vs-suspend.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28 > [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 > [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 > [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 > [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 > [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 > [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 > [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606 > [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677 > [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736 > [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 > [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 > [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413 > [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435 > [i915#444]: https://gitlab.freedesktop.org/drm/intel/issues/444 > [i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447 > [i915#463]: https://gitlab.freedesktop.org/drm/intel/issues/463 > [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470 > [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472 > [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476 > [i915#480]: https://gitlab.freedesktop.org/drm/intel/issues/480 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#503]: https://gitlab.freedesktop.org/drm/intel/issues/503 > [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51 > [i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644 > [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#832]: https://gitlab.freedesktop.org/drm/intel/issues/832 > [i915#915]: https://gitlab.freedesktop.org/drm/intel/issues/915 > > > Participating hosts (10 -> 8) > ------------------------------ > > Missing (2): pig-skl-6260u pig-glk-j5005 > > > Build changes > ------------- > > * CI: CI-20190529 -> None > * IGT: IGT_5355 -> IGTPW_3892 > * Piglit: piglit_4509 -> None > > CI-20190529: 20190529 > CI_DRM_7656: 635576de746ef28c1635b4cf4fb12f4db1104f8b @ git://anongit.freedesktop.org/gfx-ci/linux > IGTPW_3892: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/index.html > IGT_5355: 2ead76177f2546d3eec0abbd0d9e47cd36588199 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3892/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2019-12-31 12:50 UTC | newest] Thread overview: 33+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-12-30 3:40 [igt-dev] [PATCH i-g-t 00/10] lib: Add support and coverage for MC YUV formats Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 01/10] lib/igt_buf: Use compression type consistently Imre Deak 2019-12-30 12:00 ` Kahola, Mika 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 02/10] lib/igt_buf: Extend igt_buf to include two CCS surfaces Imre Deak 2019-12-30 12:02 ` Kahola, Mika 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 03/10] lib/igt_buf: Extend igt_buf to include two color surfaces Imre Deak 2019-12-30 12:06 ` Kahola, Mika 2019-12-30 12:58 ` Imre Deak 2019-12-30 17:58 ` [igt-dev] [PATCH i-g-t v2 " Imre Deak 2019-12-31 8:40 ` Kahola, Mika 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 04/10] lib: Add engine copy support for YUV formats Imre Deak 2019-12-30 13:23 ` Kahola, Mika 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 05/10] Revert "tests/kms_plane: Disable GEN12 media compression YUV tests" Imre Deak 2019-12-30 13:24 ` Kahola, Mika 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 06/10] tests/kms_ccs: Add support for testing multiple formats Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 07/10] tests/kms_ccs: Add GEN12 CCS media compression format modifier Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 08/10] tests/kms_ccs: Work around CRC mismatch when mixing SDR/HDR planes Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 09/10] tests/kms_ccs: Test YUV formats too Imre Deak 2019-12-30 3:40 ` [igt-dev] [PATCH i-g-t 10/10] tests/kms_ccs: Add option to check the CCS planes Imre Deak 2019-12-30 12:47 ` Juha-Pekka Heikkila 2019-12-30 13:12 ` Imre Deak 2019-12-30 13:34 ` Juha-Pekka Heikkila 2019-12-30 17:58 ` [igt-dev] [PATCH i-g-t v2 " Imre Deak 2019-12-30 4:12 ` [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add support and coverage for MC YUV formats Patchwork 2019-12-30 9:00 ` Imre Deak 2019-12-30 9:22 ` Vudum, Lakshminarayana 2019-12-30 9:18 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork 2019-12-30 12:50 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 2019-12-30 13:23 ` Imre Deak 2019-12-30 15:53 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork 2019-12-30 19:02 ` [igt-dev] ✓ Fi.CI.BAT: success for lib: Add support and coverage for MC YUV formats (rev3) Patchwork 2019-12-31 8:45 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 2019-12-31 12:49 ` Imre Deak
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox