[igt-dev] [PATCH i-g-t 1/5] lib/i915: Create a context wrapping one specific engine

[igt-dev] [PATCH i-g-t 1/5] lib/i915: Create a context wrapping one specific engine

[Chris Wilson]

Quite frequently we want to execute on one precise engine, so add a
convenience routine to create a context that contains only that engine
in the default [0] slot.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/i915/gem_context.c | 64 +++++++++++++++++++++++++++++++-----------
 lib/i915/gem_context.h |  2 ++
 2 files changed, 49 insertions(+), 17 deletions(-)

diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 50dfee3d1..169e43d2e 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -43,6 +43,21 @@
  * software features improving submission model (context priority).
  */
 
+static int create_ext_ioctl(int i915,
+			    struct drm_i915_gem_context_create_ext *arg)
+{
+	int err;
+
+	err = 0;
+	if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
+		err = -errno;
+		igt_assume(err);
+	}
+
+	errno = 0;
+	return err;
+}
+
 /**
  * gem_has_contexts:
  * @fd: open i915 drm file descriptor
@@ -324,17 +339,14 @@ __gem_context_clone(int i915,
 		.flags = flags | I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
 		.extensions = to_user_pointer(&clone),
 	};
-	int err = 0;
+	int err;
 
-	if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &arg)) {
-		err = -errno;
-		igt_assume(err);
-	}
+	err = create_ext_ioctl(i915, &arg);
+	if (err)
+		return err;
 
 	*out = arg.ctx_id;
-
-	errno = 0;
-	return err;
+	return 0;
 }
 
 static bool __gem_context_has(int i915, uint32_t share, unsigned int flags)
@@ -382,16 +394,8 @@ bool gem_has_context_clone(int i915)
 		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
 		.extensions = to_user_pointer(&ext),
 	};
-	int err;
-
-	err = 0;
-	if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create)) {
-		err = -errno;
-		igt_assume(err);
-	}
-	errno = 0;
 
-	return err == -ENOENT;
+	return create_ext_ioctl(i915, &create) == -ENOENT;
 }
 
 /**
@@ -492,3 +496,29 @@ gem_context_copy_engines(int src_fd, uint32_t src, int dst_fd, uint32_t dst)
 	param.ctx_id = dst;
 	gem_context_set_param(dst_fd, &param);
 }
+
+uint32_t gem_context_create_for_engine(int i915, unsigned int class, unsigned int inst)
+{
+	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+		.engines = { { .engine_class = class, .engine_instance = inst } }
+	};
+	struct drm_i915_gem_context_create_ext_setparam p_engines = {
+		.base = {
+			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+			.next_extension = 0, /* end of chain */
+		},
+		.param = {
+			.param = I915_CONTEXT_PARAM_ENGINES,
+			.value = to_user_pointer(&engines),
+			.size = sizeof(engines),
+		},
+	};
+	struct drm_i915_gem_context_create_ext create = {
+		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+		.extensions = to_user_pointer(&p_engines),
+	};
+
+	igt_assert_eq(create_ext_ioctl(i915, &create), 0);
+	igt_assert_neq(create.ctx_id, 0);
+	return create.ctx_id;
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index 15e5db281..b478c47a1 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -34,6 +34,8 @@ int __gem_context_create(int fd, uint32_t *ctx_id);
 void gem_context_destroy(int fd, uint32_t ctx_id);
 int __gem_context_destroy(int fd, uint32_t ctx_id);
 
+uint32_t gem_context_create_for_engine(int fd, unsigned int class, unsigned int inst);
+
 int __gem_context_clone(int i915,
 			uint32_t src, unsigned int share,
 			unsigned int flags,
-- 
2.25.1

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[Intel-gfx] [PATCH i-g-t 2/5] lib/i915: Dynamic subtest constructor for sysfs/engines

[Chris Wilson]

Simplify testing sysfs/engines by providing a convenience routine that
iterates over each engine, calling a igt_dynamic routine.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/i915/gem_engine_topology.c | 48 ++++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  3 +++
 2 files changed, 51 insertions(+)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 6eca28236..53abb29fa 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -22,6 +22,8 @@
  */
 
 #include <fcntl.h>
+#include <sys/stat.h>
+#include <sys/syscall.h>
 #include <unistd.h>
 
 #include "drmtest.h"
@@ -413,3 +415,49 @@ uint32_t gem_engine_mmio_base(int i915, const char *engine)
 
 	return mmio;
 }
+
+void dyn_sysfs_engines(int i915, int engines, const char *file,
+		       void (*test)(int, int))
+{
+	char buf[512];
+	int len;
+
+	lseek(engines, 0, SEEK_SET);
+	while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
+		void *ptr = buf;
+
+		while (len) {
+			struct linux_dirent64 {
+				ino64_t        d_ino;
+				off64_t        d_off;
+				unsigned short d_reclen;
+				unsigned char  d_type;
+				char           d_name[];
+			} *de = ptr;
+			char *name;
+			int engine;
+
+			ptr += de->d_reclen;
+			len -= de->d_reclen;
+
+			engine = openat(engines, de->d_name, O_RDONLY);
+			name = igt_sysfs_get(engine, "name");
+			if (!name) {
+				close(engine);
+				continue;
+			}
+
+			igt_dynamic(name) {
+				if (file) {
+					struct stat st;
+
+					igt_require(fstatat(engine, file, &st, 0) == 0);
+				}
+
+				test(i915, engine);
+			}
+
+			close(engine);
+		}
+	}
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 219c84b72..b624d607e 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -80,4 +80,7 @@ int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
 			      const char *fmt, ...);
 uint32_t gem_engine_mmio_base(int i915, const char *engine);
 
+void dyn_sysfs_engines(int i915, int engines, const char *file,
+		       void (*test)(int i915, int engine));
+
 #endif /* GEM_ENGINE_TOPOLOGY_H */
-- 
2.25.1

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Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 2/5] lib/i915: Dynamic subtest constructor for sysfs/engines

[Andi Shyti]

Hi Chris,

> +	lseek(engines, 0, SEEK_SET);
> +	while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> +		void *ptr = buf;
> +
> +		while (len) {
> +			struct linux_dirent64 {
> +				ino64_t        d_ino;
> +				off64_t        d_off;
> +				unsigned short d_reclen;
> +				unsigned char  d_type;
> +				char           d_name[];
> +			} *de = ptr;

it's unfortunate to be in the situation of doing this, But I
don't see better alternative, it needs to be fixed in the
glibc :(

Reviewed-by: Andi Shyti <andi.shyti@intel.com>

Thanks,
Andi
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[igt-dev] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs

[Chris Wilson]

We [will] expose various per-engine scheduling controls. One of which,
'preempt_timeout_ms', defines how we wait for a preemption request to be
honoured by the currently executing context. If it fails to relieve the
GPU within the required timeout, the engine is reset and the miscreant
forcibly evicted.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/Makefile.sources             |   3 +
 tests/i915/sysfs_preempt_timeout.c | 311 +++++++++++++++++++++++++++++
 tests/intel-ci/blacklist.txt       |   1 +
 tests/meson.build                  |   1 +
 4 files changed, 316 insertions(+)
 create mode 100644 tests/i915/sysfs_preempt_timeout.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 4ac6e35ca..c1711b336 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -104,6 +104,9 @@ TESTS_progs = \
 	vgem_slow \
 	$(NULL)
 
+TESTS_progs += sysfs_preempt_timeout
+sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c
+
 TESTS_progs += gem_bad_reloc
 gem_bad_reloc_SOURCES = i915/gem_bad_reloc.c
 
diff --git a/tests/i915/sysfs_preempt_timeout.c b/tests/i915/sysfs_preempt_timeout.c
new file mode 100644
index 000000000..be1905bcd
--- /dev/null
+++ b/tests/i915/sysfs_preempt_timeout.c
@@ -0,0 +1,311 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <dirent.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <sched.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "drmtest.h" /* gem_quiescent_gpu()! */
+#include "i915/gem_engine_topology.h"
+#include "igt_dummyload.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h" /* igt_require_gem()! */
+#include "sw_sync.h"
+
+#include "igt_debugfs.h"
+
+#define ATTR "preempt_timeout_ms"
+#define RESET_TIMEOUT 20 /* milliseconds, at least one jiffie for kworker */
+
+static bool __enable_hangcheck(int dir, bool state)
+{
+	return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static bool enable_hangcheck(int i915, bool state)
+{
+	bool success;
+	int dir;
+
+	dir = igt_sysfs_open_parameters(i915);
+	if (dir < 0) /* no parameters, must be default! */
+		return false;
+
+	success = __enable_hangcheck(dir, state);
+	close(dir);
+
+	return success;
+}
+
+static void set_preempt_timeout(int engine, unsigned int value)
+{
+	unsigned int delay;
+
+	igt_sysfs_printf(engine, ATTR, "%u", value);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, value);
+}
+
+static void test_idempotent(int i915, int engine)
+{
+	unsigned int delays[] = { 0, 1, 1000, 1234, 654321 };
+	unsigned int saved;
+
+	/* Quick test that store/show reports the same values */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	for (int i = 0; i < ARRAY_SIZE(delays); i++)
+		set_preempt_timeout(engine, delays[i]);
+
+	set_preempt_timeout(engine, saved);
+}
+
+static void test_invalid(int i915, int engine)
+{
+	unsigned int saved, delay;
+
+	/* Quick test that values that are not representable are rejected */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	igt_sysfs_printf(engine, ATTR, PRIu64, -1);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, saved);
+
+	igt_sysfs_printf(engine, ATTR, "%d", -1);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, saved);
+
+	igt_sysfs_printf(engine, ATTR, PRIu64, 40ull << 32);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, saved);
+}
+
+static void set_unbannable(int i915, uint32_t ctx)
+{
+	struct drm_i915_gem_context_param p = {
+		.ctx_id = ctx,
+		.param = I915_CONTEXT_PARAM_BANNABLE,
+	};
+
+	gem_context_set_param(i915, &p);
+}
+
+static uint32_t create_context(int i915, unsigned int class, unsigned int inst, int prio)
+{
+	uint32_t ctx;
+
+	ctx = gem_context_create_for_engine(i915, class, inst);
+	set_unbannable(i915, ctx);
+	gem_context_set_priority(i915, ctx, prio);
+
+	return ctx;
+}
+
+static uint64_t __test_timeout(int i915, int engine, unsigned int timeout)
+{
+	unsigned int class, inst;
+	struct timespec ts = {};
+	igt_spin_t *spin[2];
+	uint64_t elapsed;
+	uint32_t ctx[2];
+
+	igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+	igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+	set_preempt_timeout(engine, timeout);
+
+	ctx[0] = create_context(i915, class, inst, -1023);
+	spin[0] = igt_spin_new(i915, ctx[0],
+			       .flags = (IGT_SPIN_NO_PREEMPTION |
+					 IGT_SPIN_POLL_RUN |
+					 IGT_SPIN_FENCE_OUT));
+	igt_spin_busywait_until_started(spin[0]);
+
+	ctx[1] = create_context(i915, class, inst, 1023);
+	igt_nsec_elapsed(&ts);
+	spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+	igt_spin_busywait_until_started(spin[1]);
+	elapsed = igt_nsec_elapsed(&ts);
+
+	igt_spin_free(i915, spin[1]);
+
+	igt_assert_eq(sync_fence_wait(spin[0]->out_fence, RESET_TIMEOUT), 0);
+	igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+	igt_spin_free(i915, spin[0]);
+
+	gem_context_destroy(i915, ctx[1]);
+	gem_context_destroy(i915, ctx[0]);
+	gem_quiescent_gpu(i915);
+
+	return elapsed;
+}
+
+static void test_timeout(int i915, int engine)
+{
+	int delays[] = { 1, 50, 100, 500 };
+	unsigned int saved;
+
+	/*
+	 * Send down some non-preemptable workloads and then request a
+	 * switch to a higher priority context. The HW will not be able to
+	 * respond, so the kernel will be forced to reset the hog. This
+	 * timeout should match our specification, and so we can measure
+	 * the delay from requesting the preemption to its completion.
+	 */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	gem_quiescent_gpu(i915);
+	igt_require(enable_hangcheck(i915, false));
+
+	for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+		uint64_t elapsed;
+
+		elapsed = __test_timeout(i915, engine, delays[i]);
+		igt_info("%s:%d, elapsed=%.3fms\n",
+			 ATTR, delays[i], elapsed * 1e-6);
+
+		/*
+		 * We need to give a couple of jiffies slack for the scheduler timeouts
+		 * and then a little more slack fr the overhead in submitting and
+		 * measuring. 50ms should cover all of our sins and be useful
+		 * tolerance.
+		 */
+		igt_assert_f(elapsed / 1000 / 1000 < delays[i] + 50,
+			     "Forced preemption timeout exceeded request!\n");
+	}
+
+	igt_assert(enable_hangcheck(i915, true));
+	gem_quiescent_gpu(i915);
+	set_preempt_timeout(engine, saved);
+}
+
+static void test_off(int i915, int engine)
+{
+	unsigned int class, inst;
+	igt_spin_t *spin[2];
+	unsigned int saved;
+	uint32_t ctx[2];
+
+	/*
+	 * We support setting the timeout to 0 to disable the reset on
+	 * preemption failure. Having established that we can do forced
+	 * preemption on demand, we use the same setup (non-preeemptable hog
+	 * followed by a high priority context) and verify that the hog is
+	 * never reset. Never is a long time, so we settle for 150s.
+	 */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	gem_quiescent_gpu(i915);
+	igt_require(enable_hangcheck(i915, false));
+
+	igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+	igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+	set_preempt_timeout(engine, 0);
+
+	ctx[0] = create_context(i915, class, inst, -1023);
+	spin[0] = igt_spin_new(i915, ctx[0],
+			       .flags = (IGT_SPIN_NO_PREEMPTION |
+					 IGT_SPIN_POLL_RUN |
+					 IGT_SPIN_FENCE_OUT));
+	igt_spin_busywait_until_started(spin[0]);
+
+	ctx[1] = create_context(i915, class, inst, 1023);
+	spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+
+	for (int i = 0; i < 150; i++) {
+		igt_assert_eq(sync_fence_status(spin[0]->out_fence), 0);
+		sleep(1);
+	}
+
+	set_preempt_timeout(engine, 1);
+
+	igt_spin_busywait_until_started(spin[1]);
+	igt_spin_free(i915, spin[1]);
+
+	igt_assert_eq(sync_fence_wait(spin[0]->out_fence, RESET_TIMEOUT), 0);
+	igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+	igt_spin_free(i915, spin[0]);
+
+	gem_context_destroy(i915, ctx[1]);
+	gem_context_destroy(i915, ctx[0]);
+
+	igt_assert(enable_hangcheck(i915, true));
+	gem_quiescent_gpu(i915);
+
+	set_preempt_timeout(engine, saved);
+}
+
+igt_main
+{
+	static const struct {
+		const char *name;
+		void (*fn)(int, int);
+	} tests[] = {
+		{ "idempotent", test_idempotent },
+		{ "invalid", test_invalid },
+		{ "timeout", test_timeout },
+		{ "off", test_off },
+		{ }
+	};
+	int i915 = -1, engines = -1;
+
+	igt_fixture {
+		int sys;
+
+		i915 = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(i915);
+		igt_allow_hang(i915, 0, 0);
+
+		sys = igt_sysfs_open(i915);
+		igt_require(sys != -1);
+
+		engines = openat(sys, "engine", O_RDONLY);
+		igt_require(engines != -1);
+
+		close(sys);
+	}
+
+	for (typeof(*tests) *t = tests; t->name; t++)
+		igt_subtest_with_dynamic(t->name)
+			dyn_sysfs_engines(i915, engines, ATTR, t->fn);
+
+	igt_fixture {
+		close(engines);
+		close(i915);
+	}
+}
diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index 8085719f5..1b5442278 100644
--- a/tests/intel-ci/blacklist.txt
+++ b/tests/intel-ci/blacklist.txt
@@ -60,6 +60,7 @@ igt@gem_sync@(?!.*basic).*
 igt@gem_tiled_swapping@(?!non-threaded).*
 igt@gem_userptr_blits@(major|minor|forked|mlocked|swapping).*
 igt@gem_wait@.*hang.*
+igt@sysfs_preemption_timeout@off.*
 ###############################################
 # GEM: Not worth fixing
 ###############################################
diff --git a/tests/meson.build b/tests/meson.build
index 9280eb3d8..bafd00513 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -227,6 +227,7 @@ i915_progs = [
 	'i915_query',
 	'i915_selftest',
 	'i915_suspend',
+	'sysfs_preempt_timeout',
 ]
 
 test_deps = [ igt_deps ]
-- 
2.25.1

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Re: [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs

[Andi Shyti]

Hi Chris,

> We [will] expose various per-engine scheduling controls. One of which,
> 'preempt_timeout_ms', defines how we wait for a preemption request to be
> honoured by the currently executing context. If it fails to relieve the
> GPU within the required timeout, the engine is reset and the miscreant
> forcibly evicted.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

for the next three patches (3, 4 and 5) I'm not going to repeat
myself :P

Reviewed-by: Andi Shyti <andi.shyti@intel.com>

Andi
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[igt-dev] [PATCH i-g-t 4/5] i915: Exercise sysfs heartbeat controls

[Chris Wilson]

We [will] expose various per-engine scheduling controls. One of which,
'heartbeat_duration_ms', defines how often we send a heartbeat down the
engine to check upon the health of the engine. If a heartbeat does not
complete within the interval (or two), the engine is declared hung.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/Makefile.sources                |   3 +
 tests/i915/sysfs_heartbeat_interval.c | 446 ++++++++++++++++++++++++++
 tests/intel-ci/blacklist.txt          |   1 +
 tests/meson.build                     |   1 +
 4 files changed, 451 insertions(+)
 create mode 100644 tests/i915/sysfs_heartbeat_interval.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index c1711b336..7b1f8194d 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -104,6 +104,9 @@ TESTS_progs = \
 	vgem_slow \
 	$(NULL)
 
+TESTS_progs += sysfs_heartbeat_interval
+sysfs_heartbeat_interval_SOURCES = i915/sysfs_heartbeat_interval.c
+
 TESTS_progs += sysfs_preempt_timeout
 sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c
 
diff --git a/tests/i915/sysfs_heartbeat_interval.c b/tests/i915/sysfs_heartbeat_interval.c
new file mode 100644
index 000000000..0ba19b263
--- /dev/null
+++ b/tests/i915/sysfs_heartbeat_interval.c
@@ -0,0 +1,446 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <dirent.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <signal.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+
+#include "drmtest.h" /* gem_quiescent_gpu()! */
+#include "i915/gem_engine_topology.h"
+#include "igt_dummyload.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h" /* igt_require_gem()! */
+#include "sw_sync.h"
+
+#include "igt_debugfs.h"
+
+#define ATTR "heartbeat_interval_ms"
+#define RESET_TIMEOUT 20 /* milliseconds, at least one jiffie for kworker */
+
+static bool __enable_hangcheck(int dir, bool state)
+{
+	return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static void enable_hangcheck(int i915, bool state)
+{
+	int dir;
+
+	dir = igt_sysfs_open_parameters(i915);
+	if (dir < 0) /* no parameters, must be default! */
+		return;
+
+	__enable_hangcheck(dir, state);
+	close(dir);
+}
+
+static void set_heartbeat(int engine, unsigned int value)
+{
+	unsigned int delay = ~value;
+
+	igt_debug("set %s:%d\n", ATTR, value);
+	igt_require(igt_sysfs_printf(engine, ATTR, "%u", value) > 0);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, value);
+}
+
+static void test_idempotent(int i915, int engine)
+{
+	unsigned int delays[] = { 1, 1000, 5000, 50000, 123456789 };
+	unsigned int saved;
+
+	/* Quick test that the property reports the values we set */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	for (int i = 0; i < ARRAY_SIZE(delays); i++)
+		set_heartbeat(engine, delays[i]);
+
+	set_heartbeat(engine, saved);
+}
+
+static void test_invalid(int i915, int engine)
+{
+	unsigned int saved, delay;
+
+	/* Quick test that we reject any unrepresentable intervals */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	igt_sysfs_printf(engine, ATTR, PRIu64, -1);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, saved);
+
+	igt_sysfs_printf(engine, ATTR, PRIu64, 10ull << 32);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, saved);
+}
+
+static void set_unbannable(int i915, uint32_t ctx)
+{
+	struct drm_i915_gem_context_param p = {
+		.ctx_id = ctx,
+		.param = I915_CONTEXT_PARAM_BANNABLE,
+	};
+
+	gem_context_set_param(i915, &p);
+}
+
+static uint32_t create_context(int i915, unsigned int class, unsigned int inst, int prio)
+{
+	uint32_t ctx;
+
+	ctx = gem_context_create_for_engine(i915, class, inst);
+	set_unbannable(i915, ctx);
+	gem_context_set_priority(i915, ctx, prio);
+
+	return ctx;
+}
+
+static uint64_t __test_timeout(int i915, int engine, unsigned int timeout)
+{
+	unsigned int class, inst;
+	struct timespec ts = {};
+	igt_spin_t *spin[2];
+	uint64_t elapsed;
+	uint32_t ctx[2];
+
+	igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+	igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+	set_heartbeat(engine, timeout);
+
+	ctx[0] = create_context(i915, class, inst, 1023);
+	spin[0] = igt_spin_new(i915, ctx[0],
+			       .flags = (IGT_SPIN_NO_PREEMPTION |
+					 IGT_SPIN_POLL_RUN |
+					 IGT_SPIN_FENCE_OUT));
+	igt_spin_busywait_until_started(spin[0]);
+
+	ctx[1] = create_context(i915, class, inst, -1023);
+	igt_nsec_elapsed(&ts);
+	spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+	igt_spin_busywait_until_started(spin[1]);
+	elapsed = igt_nsec_elapsed(&ts);
+
+	igt_spin_free(i915, spin[1]);
+
+	igt_assert_eq(sync_fence_wait(spin[0]->out_fence, RESET_TIMEOUT), 0);
+	igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+	igt_spin_free(i915, spin[0]);
+
+	gem_context_destroy(i915, ctx[1]);
+	gem_context_destroy(i915, ctx[0]);
+	gem_quiescent_gpu(i915);
+
+	return elapsed;
+}
+
+static void test_precise(int i915, int engine)
+{
+	int delays[] = { 1, 50, 100, 500 };
+	unsigned int saved;
+
+	/*
+	 * The heartbeat interval defines how long the kernel waits between
+	 * checking on the status of the engines. It first sends down a
+	 * heartbeat pulse, waits the interval and sees if the system managed
+	 * to complete the pulse. If not, it gives a priority bump to the pulse
+	 * and waits again. This is repeated until the priority cannot be bumped
+	 * any more, and the system is declared hung.
+	 *
+	 * If we combine the preemptive pulse with forced preemption, we instead
+	 * get a much faster hang detection. Thus in combination we can measure
+	 * the system response time to reseting a hog as a measure of the
+	 * heartbeat interval, and so confirm it matches our specification.
+	 */
+
+	igt_require(igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 1) == 1);
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+	gem_quiescent_gpu(i915);
+
+	for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+		uint64_t elapsed;
+
+		elapsed = __test_timeout(i915, engine, delays[i]);
+		igt_info("%s:%d, elapsed=%.3fms[%d]\n", ATTR,
+			 delays[i], elapsed * 1e-6,
+			 (int)(elapsed / 1000 / 1000));
+
+		/*
+		 * It takes a couple of missed heartbeats before we start
+		 * terminating hogs, and a little bit of jiffie slack for
+		 * scheduling at each step. 150ms should cover all of our
+		 * sins and be useful tolerance.
+		 */
+		igt_assert_f(elapsed / 1000 / 1000 < 3 * delays[i] + 150,
+			     "Heartbeat interval (and CPR) exceeded request!\n");
+	}
+
+	gem_quiescent_gpu(i915);
+	set_heartbeat(engine, saved);
+}
+
+static void test_nopreempt(int i915, int engine)
+{
+	int delays[] = { 1, 50, 100, 500 };
+	unsigned int saved;
+
+	/*
+	 * The same principle as test_precise(), except that forced preemption
+	 * is disabled (or simply not supported by the platform). This time,
+	 * it waits until the system misses a few heartbeat before doing a
+	 * per-engine/full-gpu reset. As such it is less precise, but we
+	 * can still estimate an upper bound for our specified heartbeat
+	 * interval and verify the system conforms.
+	 */
+
+	/* Test heartbeats with forced preemption  disabled */
+	igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 0);
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+	gem_quiescent_gpu(i915);
+
+	for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+		uint64_t elapsed;
+
+		elapsed = __test_timeout(i915, engine, delays[i]);
+		igt_info("%s:%d, elapsed=%.3fms[%d]\n", ATTR,
+			 delays[i], elapsed * 1e-6,
+			 (int)(elapsed / 1000 / 1000));
+
+		/*
+		 * It takes a few missed heartbeats before we start
+		 * terminating hogs, and a little bit of jiffie slack for
+		 * scheduling at each step. 250ms should cover all of our
+		 * sins and be useful tolerance.
+		 */
+		igt_assert_f(elapsed / 1000 / 1000 < 5 * delays[i] + 250,
+			     "Heartbeat interval (and CPR) exceeded request!\n");
+	}
+
+	gem_quiescent_gpu(i915);
+	set_heartbeat(engine, saved);
+}
+
+static void client(int i915, int engine, int *ctl, int duration, int expect)
+{
+	unsigned int class, inst;
+	unsigned long count = 0;
+	uint32_t ctx;
+
+	igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+	igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+	ctx = create_context(i915, class, inst, 0);
+
+	while (!READ_ONCE(*ctl)) {
+		igt_spin_t *spin;
+
+		spin = igt_spin_new(i915, ctx,
+				    .flags = (IGT_SPIN_NO_PREEMPTION |
+					      IGT_SPIN_POLL_RUN |
+					      IGT_SPIN_FENCE_OUT));
+		igt_spin_busywait_until_started(spin);
+
+		igt_spin_set_timeout(spin, (uint64_t)duration * 1000 * 1000);
+		sync_fence_wait(spin->out_fence, -1);
+
+		igt_assert_eq(sync_fence_status(spin->out_fence), expect);
+		count++;
+	}
+
+	gem_context_destroy(i915, ctx);
+	igt_info("%s client completed %lu spins\n",
+		 expect < 0 ? "Bad" : "Good", count);
+}
+
+static void __test_mixed(int i915, int engine,
+			 int heartbeat,
+			 int good,
+			 int bad,
+			 int duration)
+{
+	unsigned int saved;
+	int *shared;
+
+	/*
+	 * Given two clients of which one is a hog, be sure we cleanly
+	 * terminate the hog leaving the good client to run.
+	 */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+	gem_quiescent_gpu(i915);
+
+	shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+	igt_assert(shared != MAP_FAILED);
+
+	set_heartbeat(engine, heartbeat);
+
+	igt_fork(child, 1) /* good client */
+		client(i915, engine, shared, good, 1);
+	igt_fork(child, 1) /* bad client */
+		client(i915, engine, shared, bad, -EIO);
+
+	sleep(duration);
+
+	*shared = true;
+	igt_waitchildren();
+	munmap(shared, 4096);
+
+	gem_quiescent_gpu(i915);
+	set_heartbeat(engine, saved);
+}
+
+static void test_mixed(int i915, int engine)
+{
+	/*
+	 * Hogs rarely run alone. Our hang detection must carefully wean
+	 * out the hogs from the innocent clients. Thus we run a mixed workload
+	 * with non-preemptable hogs that exceed the heartbeat, and quicker
+	 * innocents. We inspect the fence status of each to verify that
+	 * only the hogs are reset.
+	 */
+	igt_require(igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 1) == 1);
+	__test_mixed(i915, engine, 10, 10, 100, 5);
+}
+
+static void test_long(int i915, int engine)
+{
+	/*
+	 * Some clients relish being hogs, and demand that the system
+	 * never do hangchecking. Never is hard to test, so instead we
+	 * run over a day and verify that only the super hogs are reset.
+	 */
+	igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 0);
+	__test_mixed(i915, engine,
+		     60 * 1000, /* 60s */
+		     60 * 1000, /* 60s */
+		     300 * 1000, /* 5min */
+		     24 * 3600 /* 24hours */);
+}
+
+static void test_off(int i915, int engine)
+{
+	unsigned int class, inst;
+	unsigned int saved;
+	igt_spin_t *spin;
+	uint32_t ctx;
+
+	/*
+	 * Some other clients request that there is never any interruption
+	 * or jitter in their workload and so demand that the kernel never
+	 * sends a heartbeat to steal precious cycles from their workload.
+	 * Turn off the heartbeat and check that the workload is uninterrupted
+	 * for 150s.
+	 */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+	gem_quiescent_gpu(i915);
+
+	igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+	igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+	set_heartbeat(engine, 0);
+
+	ctx = create_context(i915, class, inst, 0);
+
+	spin = igt_spin_new(i915, ctx,
+			    .flags = (IGT_SPIN_POLL_RUN |
+				      IGT_SPIN_NO_PREEMPTION |
+				      IGT_SPIN_FENCE_OUT));
+	igt_spin_busywait_until_started(spin);
+
+	for (int i = 0; i < 150; i++) {
+		igt_assert_eq(sync_fence_status(spin->out_fence), 0);
+		sleep(1);
+	}
+
+	set_heartbeat(engine, 1);
+
+	igt_assert_eq(sync_fence_wait(spin->out_fence, 250), 0);
+	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
+
+	igt_spin_free(i915, spin);
+
+	gem_quiescent_gpu(i915);
+	set_heartbeat(engine, saved);
+}
+
+igt_main
+{
+	static const struct {
+		const char *name;
+		void (*fn)(int, int);
+	} tests[] = {
+		{ "idempotent", test_idempotent },
+		{ "invalid", test_invalid },
+		{ "precise", test_precise },
+		{ "nopreempt", test_nopreempt },
+		{ "mixed", test_mixed },
+		{ "off", test_off },
+		{ "long", test_long },
+		{ }
+	};
+	int i915 = -1, engines = -1;
+
+	igt_fixture {
+		int sys;
+
+		i915 = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(i915);
+		igt_allow_hang(i915, 0, 0);
+
+		sys = igt_sysfs_open(i915);
+		igt_require(sys != -1);
+
+		engines = openat(sys, "engine", O_RDONLY);
+		igt_require(engines != -1);
+		close(sys);
+
+		enable_hangcheck(i915, true);
+	}
+
+	for (typeof(*tests) *t = tests; t->name; t++)
+		igt_subtest_with_dynamic(t->name)
+			dyn_sysfs_engines(i915, engines, ATTR, t->fn);
+
+	igt_fixture {
+		close(engines);
+		close(i915);
+	}
+}
diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index 1b5442278..a02ef67e6 100644
--- a/tests/intel-ci/blacklist.txt
+++ b/tests/intel-ci/blacklist.txt
@@ -60,6 +60,7 @@ igt@gem_sync@(?!.*basic).*
 igt@gem_tiled_swapping@(?!non-threaded).*
 igt@gem_userptr_blits@(major|minor|forked|mlocked|swapping).*
 igt@gem_wait@.*hang.*
+igt@sysfs_heartbeat_timeout@long.*
 igt@sysfs_preemption_timeout@off.*
 ###############################################
 # GEM: Not worth fixing
diff --git a/tests/meson.build b/tests/meson.build
index bafd00513..3e5952101 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -227,6 +227,7 @@ i915_progs = [
 	'i915_query',
 	'i915_selftest',
 	'i915_suspend',
+	'sysfs_heartbeat_interval',
 	'sysfs_preempt_timeout',
 ]
 
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 5/5] i915: Exercise timeslice sysfs property

[Chris Wilson]

We [will] expose various per-engine scheduling controls. One of which,
'timeslice_duration_ms', defines the scheduling quantum. If a context
exhausts its timeslice, it will be preempted in favour of running one of
its compatriots.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/Makefile.sources                |   3 +
 tests/i915/sysfs_timeslice_duration.c | 531 ++++++++++++++++++++++++++
 tests/intel-ci/blacklist.txt          |   1 +
 tests/meson.build                     |   1 +
 4 files changed, 536 insertions(+)
 create mode 100644 tests/i915/sysfs_timeslice_duration.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 7b1f8194d..1793020ea 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -110,6 +110,9 @@ sysfs_heartbeat_interval_SOURCES = i915/sysfs_heartbeat_interval.c
 TESTS_progs += sysfs_preempt_timeout
 sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c
 
+TESTS_progs += sysfs_timeslice_duration
+sysfs_timeslice_duration_SOURCES = i915/sysfs_timeslice_duration.c
+
 TESTS_progs += gem_bad_reloc
 gem_bad_reloc_SOURCES = i915/gem_bad_reloc.c
 
diff --git a/tests/i915/sysfs_timeslice_duration.c b/tests/i915/sysfs_timeslice_duration.c
new file mode 100644
index 000000000..15174ddec
--- /dev/null
+++ b/tests/i915/sysfs_timeslice_duration.c
@@ -0,0 +1,531 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <dirent.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "drmtest.h" /* gem_quiescent_gpu()! */
+#include "i915/gem_engine_topology.h"
+#include "i915/gem_mman.h"
+#include "igt_dummyload.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h" /* igt_require_gem()! */
+#include "intel_chipset.h"
+#include "intel_reg.h"
+#include "sw_sync.h"
+
+#define ATTR "timeslice_duration_ms"
+#define RESET_TIMEOUT 20 /* milliseconds, at least one jiffie for kworker */
+
+#define MI_SEMAPHORE_WAIT		(0x1c << 23)
+#define   MI_SEMAPHORE_POLL             (1 << 15)
+#define   MI_SEMAPHORE_SAD_GT_SDD       (0 << 12)
+#define   MI_SEMAPHORE_SAD_GTE_SDD      (1 << 12)
+#define   MI_SEMAPHORE_SAD_LT_SDD       (2 << 12)
+#define   MI_SEMAPHORE_SAD_LTE_SDD      (3 << 12)
+#define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
+#define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
+
+static bool __enable_hangcheck(int dir, bool state)
+{
+	return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static bool enable_hangcheck(int i915, bool state)
+{
+	bool success;
+	int dir;
+
+	dir = igt_sysfs_open_parameters(i915);
+	if (dir < 0) /* no parameters, must be default! */
+		return false;
+
+	success = __enable_hangcheck(dir, state);
+	close(dir);
+
+	return success;
+}
+
+static void set_timeslice(int engine, unsigned int value)
+{
+	unsigned int delay;
+
+	igt_sysfs_printf(engine, ATTR, "%u", value);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, value);
+}
+
+static void test_idempotent(int i915, int engine)
+{
+	const unsigned int delays[] = { 0, 1, 1234, 654321 };
+	unsigned int saved;
+
+	/* Quick test to verify the kernel reports the same values as we write */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	for (int i = 0; i < ARRAY_SIZE(delays); i++)
+		set_timeslice(engine, delays[i]);
+
+	set_timeslice(engine, saved);
+}
+
+static void test_invalid(int i915, int engine)
+{
+	unsigned int saved, delay;
+
+	/* Quick test that non-representable delays are rejected */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	igt_sysfs_printf(engine, ATTR, PRIu64, -1);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, saved);
+
+	igt_sysfs_printf(engine, ATTR, "%d", -1);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, saved);
+
+	igt_sysfs_printf(engine, ATTR, PRIu64, 123ull << 32);
+	igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+	igt_assert_eq(delay, saved);
+}
+
+static void set_unbannable(int i915, uint32_t ctx)
+{
+	struct drm_i915_gem_context_param p = {
+		.ctx_id = ctx,
+		.param = I915_CONTEXT_PARAM_BANNABLE,
+	};
+
+	gem_context_set_param(i915, &p);
+}
+
+static uint32_t create_context(int i915, unsigned int class, unsigned int inst, int prio)
+{
+	uint32_t ctx;
+
+	ctx = gem_context_create_for_engine(i915, class, inst);
+	set_unbannable(i915, ctx);
+	gem_context_set_priority(i915, ctx, prio);
+
+	return ctx;
+}
+
+static int cmp_u32(const void *_a, const void *_b)
+{
+	const uint32_t *a = _a, *b = _b;
+
+	return *a - *b;
+}
+
+static double clockrate(int i915)
+{
+	int freq;
+	drm_i915_getparam_t gp = {
+		.value = &freq,
+		.param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+	};
+
+	igt_require(igt_ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp) == 0);
+	return 1e9 / freq;
+}
+
+static uint64_t __test_duration(int i915, int engine, unsigned int timeout)
+{
+	struct drm_i915_gem_exec_object2 obj[3] = {
+		{
+			.handle = gem_create(i915, 4096),
+			.offset = 0,
+			.flags = EXEC_OBJECT_PINNED,
+		},
+		{
+			.handle = gem_create(i915, 4096),
+			.offset = 4096,
+			.flags = EXEC_OBJECT_PINNED,
+		},
+		{ gem_create(i915, 4096) }
+	};
+	struct drm_i915_gem_execbuffer2 eb = {
+		.buffer_count = ARRAY_SIZE(obj),
+		.buffers_ptr = to_user_pointer(obj),
+	};
+	const int gen = intel_gen(intel_get_drm_devid(i915));
+	double duration = clockrate(i915);
+	unsigned int class, inst, mmio;
+	uint32_t *cs, *map;
+	uint32_t ctx[2];
+	int start;
+	int i;
+
+	igt_require(gem_scheduler_has_preemption(i915));
+	igt_require(gen >= 8); /* MI_SEMAPHORE_WAIT */
+
+	igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+	igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+	igt_require(igt_sysfs_scanf(engine, "mmio_base", "%x", &mmio) == 1);
+
+	set_timeslice(engine, timeout);
+
+	ctx[0] = create_context(i915, class, inst, 0);
+	ctx[1] = create_context(i915, class, inst, 0);
+
+	map = gem_mmap__device_coherent(i915, obj[2].handle,
+					0, 4096, PROT_WRITE);
+	gem_set_domain(i915, obj[2].handle,
+		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+	cs = map;
+	for (i = 0; i < 10; i++) {
+		*cs++ = MI_SEMAPHORE_WAIT |
+			MI_SEMAPHORE_POLL |
+			MI_SEMAPHORE_SAD_NEQ_SDD |
+			(4 - 2 + (gen >= 12));
+		*cs++ = 0;
+		*cs++ = obj[0].offset + sizeof(uint32_t) * i;
+		*cs++ = 0;
+		if (gen >= 12)
+			*cs++ = 0;
+
+		*cs++ = 0x24 << 23 | 2; /* SRM */
+		*cs++ = mmio + 0x358;
+		*cs++ = obj[1].offset + sizeof(uint32_t) * i;
+		*cs++ = 0;
+
+		*cs++ = MI_STORE_DWORD_IMM;
+		*cs++ = obj[0].offset +
+			4096 - sizeof(uint32_t) * i - sizeof(uint32_t);
+		*cs++ = 0;
+		*cs++ = 1;
+	}
+	*cs++ = MI_BATCH_BUFFER_END;
+
+	cs += 16 - ((cs - map) & 15);
+	start = (cs - map) * sizeof(*cs);
+	for (i = 0; i < 10; i++) {
+		*cs++ = MI_STORE_DWORD_IMM;
+		*cs++ = obj[0].offset + sizeof(uint32_t) * i;
+		*cs++ = 0;
+		*cs++ = 1;
+
+		*cs++ = MI_SEMAPHORE_WAIT |
+			MI_SEMAPHORE_POLL |
+			MI_SEMAPHORE_SAD_NEQ_SDD |
+			(4 - 2 + (gen >= 12));
+		*cs++ = 0;
+		*cs++ = obj[0].offset +
+			4096 - sizeof(uint32_t) * i - sizeof(uint32_t);
+		*cs++ = 0;
+		if (gen >= 12)
+			*cs++ = 0;
+	}
+	*cs++ = MI_BATCH_BUFFER_END;
+	igt_assert(cs - map < 4096 / sizeof(*cs));
+	munmap(map, 4096);
+
+	eb.rsvd1 = ctx[0];
+	gem_execbuf(i915, &eb);
+
+	eb.rsvd1 = ctx[1];
+	eb.batch_start_offset = start;
+	gem_execbuf(i915, &eb);
+
+	gem_sync(i915, obj[2].handle);
+
+	gem_set_domain(i915, obj[1].handle,
+		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+	map = gem_mmap__device_coherent(i915, obj[1].handle,
+					0, 4096, PROT_WRITE);
+	for (i = 0; i < 9; i++)
+		map[i] = map[i + 1] - map[i];
+	qsort(map, 9, sizeof(*map), cmp_u32);
+	duration *= map[4] / 2; /* 2 sema-waits between timestamp updates */
+	munmap(map, 4096);
+
+	for (i = 0; i < ARRAY_SIZE(ctx); i++)
+		gem_context_destroy(i915, ctx[i]);
+
+	for (i = 0; i < ARRAY_SIZE(obj); i++)
+		gem_close(i915, obj[i].handle);
+
+	return duration;
+}
+
+static unsigned int set_heartbeat(int engine, unsigned int value)
+{
+	const char *attr= "heartbeat_interval_ms";
+	unsigned int old = ~value, new;
+
+	igt_debug("set %s:%d\n", attr, value);
+	igt_sysfs_scanf(engine, attr, "%u", &old);
+	igt_require(igt_sysfs_printf(engine, attr, "%u", value) > 0);
+	igt_sysfs_scanf(engine, attr, "%u", &new);
+	igt_assert_eq(new, value);
+
+	return old;
+}
+
+static void disable_heartbeat(int engine, unsigned int *saved)
+{
+	*saved = set_heartbeat(engine, 0);
+}
+
+static void enable_heartbeat(int engine, unsigned int saved)
+{
+	set_heartbeat(engine, saved);
+}
+
+static void test_duration(int i915, int engine)
+{
+	int delays[] = { 1, 50, 100, 500 };
+	unsigned int saved, heartbeat;
+
+	/*
+	 * Timeslicing at its very basic level is sharing the GPU by
+	 * running one context for interval before running another. After
+	 * each interval the running context is swapped for another runnable
+	 * context.
+	 *
+	 * We can measure this directly by watching the xCS_TIMESTAMP and
+	 * recording its value every time we switch into the context, using
+	 * a couple of semaphores to busyspin for the timeslice.
+	 */
+
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	gem_quiescent_gpu(i915);
+
+	disable_heartbeat(engine, &heartbeat);
+	for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+		uint64_t elapsed;
+
+		elapsed = __test_duration(i915, engine, delays[i]);
+		igt_info("%s:%d, elapsed=%.3fms\n",
+			 ATTR, delays[i], elapsed * 1e-6);
+
+		/*
+		 * We need to give a couple of jiffies slack for the scheduler timeouts
+		 * and then a little more slack fr the overhead in submitting and
+		 * measuring. 50ms should cover all of our sins and be useful
+		 * tolerance.
+		 */
+		igt_assert_f(elapsed / 1000 / 1000 < delays[i] + 50,
+			     "Timeslice exceeded request!\n");
+	}
+	enable_heartbeat(engine, heartbeat);
+
+	gem_quiescent_gpu(i915);
+	set_timeslice(engine, saved);
+}
+
+static uint64_t __test_timeout(int i915, int engine, unsigned int timeout)
+{
+	unsigned int class, inst;
+	struct timespec ts = {};
+	igt_spin_t *spin[2];
+	uint64_t elapsed;
+	uint32_t ctx[2];
+
+	igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+	igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+	set_timeslice(engine, timeout);
+
+	ctx[0] = create_context(i915, class, inst, 0);
+	spin[0] = igt_spin_new(i915, ctx[0],
+			       .flags = (IGT_SPIN_NO_PREEMPTION |
+					 IGT_SPIN_POLL_RUN |
+					 IGT_SPIN_FENCE_OUT));
+	igt_spin_busywait_until_started(spin[0]);
+
+	ctx[1] = create_context(i915, class, inst, 0);
+	igt_nsec_elapsed(&ts);
+	spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+	igt_spin_busywait_until_started(spin[1]);
+	elapsed = igt_nsec_elapsed(&ts);
+
+	igt_spin_free(i915, spin[1]);
+
+	igt_assert_eq(sync_fence_wait(spin[0]->out_fence, RESET_TIMEOUT), 0);
+	igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+	igt_spin_free(i915, spin[0]);
+
+	gem_context_destroy(i915, ctx[1]);
+	gem_context_destroy(i915, ctx[0]);
+	gem_quiescent_gpu(i915);
+
+	return elapsed;
+}
+
+static void test_timeout(int i915, int engine)
+{
+	int delays[] = { 1, 50, 100, 500 };
+	unsigned int saved;
+
+	/*
+	 * Timeslicing requires us to preempt the running context in order to
+	 * switch into its contemporary. If we couple a unpreemptable hog
+	 * with a fast forced reset, we can measure the timeslice by how long
+	 * it takes for the hog to be reset and the high priority context
+	 * to complete.
+	 */
+
+	igt_require(igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 1) == 1);
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	gem_quiescent_gpu(i915);
+	igt_require(enable_hangcheck(i915, false));
+
+	for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+		uint64_t elapsed;
+
+		elapsed = __test_timeout(i915, engine, delays[i]);
+		igt_info("%s:%d, elapsed=%.3fms\n",
+			 ATTR, delays[i], elapsed * 1e-6);
+
+		/*
+		 * We need to give a couple of jiffies slack for the scheduler timeouts
+		 * and then a little more slack fr the overhead in submitting and
+		 * measuring. 50ms should cover all of our sins and be useful
+		 * tolerance.
+		 */
+		igt_assert_f(elapsed / 1000 / 1000 < delays[i] + 50,
+			     "Timeslice exceeded request!\n");
+	}
+
+	igt_assert(enable_hangcheck(i915, true));
+	gem_quiescent_gpu(i915);
+	set_timeslice(engine, saved);
+}
+
+static void test_off(int i915, int engine)
+{
+	unsigned int class, inst;
+	unsigned int saved;
+	igt_spin_t *spin[2];
+	uint32_t ctx[2];
+
+	/*
+	 * As always, there are some who must run uninterrupted and simply do
+	 * not want to share the GPU even for a microsecond. Those greedy
+	 * clients can disable timeslicing entirely, and so set the timeslice
+	 * to 0. We test that a hog is not preempted within the 150s of
+	 * our boredom threshold.
+	 */
+
+	igt_require(igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 1) == 1);
+	igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+	igt_debug("Initial %s:%u\n", ATTR, saved);
+
+	gem_quiescent_gpu(i915);
+	igt_require(enable_hangcheck(i915, false));
+
+	igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+	igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+	set_timeslice(engine, 0);
+
+	ctx[0] = create_context(i915, class, inst, 0);
+	spin[0] = igt_spin_new(i915, ctx[0],
+			       .flags = (IGT_SPIN_NO_PREEMPTION |
+					 IGT_SPIN_POLL_RUN |
+					 IGT_SPIN_FENCE_OUT));
+	igt_spin_busywait_until_started(spin[0]);
+
+	ctx[1] = create_context(i915, class, inst, 0);
+	spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+
+	for (int i = 0; i < 150; i++) {
+		igt_assert_eq(sync_fence_status(spin[0]->out_fence), 0);
+		sleep(1);
+	}
+
+	set_timeslice(engine, 1);
+
+	igt_spin_busywait_until_started(spin[1]);
+	igt_spin_free(i915, spin[1]);
+
+	igt_assert_eq(sync_fence_wait(spin[0]->out_fence, RESET_TIMEOUT), 0);
+	igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+	igt_spin_free(i915, spin[0]);
+
+	gem_context_destroy(i915, ctx[1]);
+	gem_context_destroy(i915, ctx[0]);
+
+	igt_assert(enable_hangcheck(i915, true));
+	gem_quiescent_gpu(i915);
+
+	set_timeslice(engine, saved);
+}
+
+igt_main
+{
+	static const struct {
+		const char *name;
+		void (*fn)(int, int);
+	} tests[] = {
+		{ "idempotent", test_idempotent },
+		{ "invalid", test_invalid },
+		{ "duration", test_duration },
+		{ "timeout", test_timeout },
+		{ "off", test_off },
+		{ }
+	};
+	int i915 = -1, engines = -1;
+
+	igt_fixture {
+		int sys;
+
+		i915 = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(i915);
+		igt_allow_hang(i915, 0, 0);
+
+		sys = igt_sysfs_open(i915);
+		igt_require(sys != -1);
+
+		engines = openat(sys, "engine", O_RDONLY);
+		igt_require(engines != -1);
+
+		close(sys);
+	}
+
+	for (typeof(*tests) *t = tests; t->name; t++)
+		igt_subtest_with_dynamic(t->name)
+			dyn_sysfs_engines(i915, engines, ATTR, t->fn);
+
+	igt_fixture {
+		close(engines);
+		close(i915);
+	}
+}
diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index a02ef67e6..d0e1ee909 100644
--- a/tests/intel-ci/blacklist.txt
+++ b/tests/intel-ci/blacklist.txt
@@ -62,6 +62,7 @@ igt@gem_userptr_blits@(major|minor|forked|mlocked|swapping).*
 igt@gem_wait@.*hang.*
 igt@sysfs_heartbeat_timeout@long.*
 igt@sysfs_preemption_timeout@off.*
+igt@sysfs_timeslice_duration@off.*
 ###############################################
 # GEM: Not worth fixing
 ###############################################
diff --git a/tests/meson.build b/tests/meson.build
index 3e5952101..7629afde9 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -229,6 +229,7 @@ i915_progs = [
 	'i915_suspend',
 	'sysfs_heartbeat_interval',
 	'sysfs_preempt_timeout',
+	'sysfs_timeslice_duration',
 ]
 
 test_deps = [ igt_deps ]
-- 
2.25.1

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[igt-dev] ✗ GitLab.Pipeline: failure for series starting with [i-g-t,1/5] lib/i915: Create a context wrapping one specific engine

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/5] lib/i915: Create a context wrapping one specific engine
URL   : https://patchwork.freedesktop.org/series/74575/
State : failure

== Summary ==

ERROR! This series introduces new undocumented tests:

sysfs_heartbeat_interval
sysfs_heartbeat_interval@idempotent
sysfs_heartbeat_interval@invalid
sysfs_heartbeat_interval@long
sysfs_heartbeat_interval@mixed
sysfs_heartbeat_interval@nopreempt
sysfs_heartbeat_interval@off
sysfs_heartbeat_interval@precise
sysfs_preempt_timeout
sysfs_preempt_timeout@idempotent
sysfs_preempt_timeout@invalid
sysfs_preempt_timeout@off
sysfs_preempt_timeout@timeout
sysfs_timeslice_duration
sysfs_timeslice_duration@duration
sysfs_timeslice_duration@idempotent
sysfs_timeslice_duration@invalid
sysfs_timeslice_duration@off
sysfs_timeslice_duration@timeout

Can you document them as per the requirement in the [CONTRIBUTING.md]?

[Documentation] has more details on how to do this.

Here are few examples:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/0316695d03aa46108296b27f3982ec93200c7a6e
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/443cc658e1e6b492ee17bf4f4d891029eb7a205d

Thanks in advance!

[CONTRIBUTING.md]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md#L19
[Documentation]: https://drm.pages.freedesktop.org/igt-gpu-tools/igt-gpu-tools-Core.html#igt-describe

Other than that, pipeline status: SUCCESS.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/118604 for the overview.

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/118604
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[igt-dev] ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/5] lib/i915: Create a context wrapping one specific engine

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/5] lib/i915: Create a context wrapping one specific engine
URL   : https://patchwork.freedesktop.org/series/74575/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8120 -> IGTPW_4291
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_4291 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_4291, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4291/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_4291:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@execlists:
    - fi-cfl-8700k:       [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8120/fi-cfl-8700k/igt@i915_selftest@live@execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4291/fi-cfl-8700k/igt@i915_selftest@live@execlists.html

  
Known issues
------------

  Here are the changes found in IGTPW_4291 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_parallel@contexts:
    - fi-tgl-y:           [PASS][3] -> [INCOMPLETE][4] ([CI#94] / [i915#470] / [i915#529])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8120/fi-tgl-y/igt@gem_exec_parallel@contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4291/fi-tgl-y/igt@gem_exec_parallel@contexts.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gem_contexts:
    - fi-skl-lmem:        [INCOMPLETE][5] ([i915#424]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8120/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4291/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-soraka:      [DMESG-FAIL][7] ([i915#541]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8120/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4291/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  
  [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
  [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
  [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
  [i915#529]: https://gitlab.freedesktop.org/drm/intel/issues/529
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Participating hosts (49 -> 43)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5505 -> IGTPW_4291

  CI-20190529: 20190529
  CI_DRM_8120: ce66c439df71f01b018803664c4a50fc61255788 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4291: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4291/index.html
  IGT_5505: 8973d811f3fdfb4ace4aabab2095ce0309881648 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@sysfs_heartbeat_interval@idempotent
+igt@sysfs_heartbeat_interval@invalid
+igt@sysfs_heartbeat_interval@long
+igt@sysfs_heartbeat_interval@mixed
+igt@sysfs_heartbeat_interval@nopreempt
+igt@sysfs_heartbeat_interval@off
+igt@sysfs_heartbeat_interval@precise
+igt@sysfs_preempt_timeout@idempotent
+igt@sysfs_preempt_timeout@invalid
+igt@sysfs_preempt_timeout@off
+igt@sysfs_preempt_timeout@timeout
+igt@sysfs_timeslice_duration@duration
+igt@sysfs_timeslice_duration@idempotent
+igt@sysfs_timeslice_duration@invalid
+igt@sysfs_timeslice_duration@off
+igt@sysfs_timeslice_duration@timeout

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4291/index.html
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Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 1/5] lib/i915: Create a context wrapping one specific engine

[Andi Shyti]

Hi Chris,

On Wed, Mar 11, 2020 at 09:34:44AM +0000, Chris Wilson wrote:
> Quite frequently we want to execute on one precise engine, so add a
> convenience routine to create a context that contains only that engine
> in the default [0] slot.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Andi Shyti <andi.shyti@intel.com>

Thanks,
Andi
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