[igt-dev] [PATCH i-g-t 0/4] Remove libdrm from media_spin

[igt-dev] [PATCH i-g-t 0/4] Remove libdrm from media_spin

[Zbigniew Kempczyński]

All localized functions gathered in media_spin were removed.

Zbigniew Kempczyński (4):
  lib/intel_bufops: add fields for keeping offset and context
  lib/intel_batchbuffer: add bb reset
  tests/i915_pm_sseu: remove libdrm dependency
  HAX: run gpgpu|media_fill and i915_pm_sseu in BAT only

 lib/gpu_cmds.c                        |   6 +-
 lib/intel_batchbuffer.c               |  84 ++++-
 lib/intel_batchbuffer.h               |  12 +-
 lib/intel_bufops.h                    |   4 +
 lib/media_spin.c                      | 469 ++++----------------------
 lib/media_spin.h                      |   8 +-
 tests/i915/i915_pm_sseu.c             |  69 ++--
 tests/intel-ci/fast-feedback.testlist | 162 +--------
 8 files changed, 185 insertions(+), 629 deletions(-)

-- 
2.26.0

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[igt-dev] [PATCH i-g-t 1/4] lib/intel_bufops: add fields for keeping offset and context

[Zbigniew Kempczyński]

To avoid relocations when intel_buf is used we need to keep previous
offset and context. Add addr structure with offset and ctx fields.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/gpu_cmds.c     | 6 +++---
 lib/intel_bufops.h | 4 ++++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 8c284eb1..417253a7 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -109,7 +109,7 @@ gen7_fill_surface_state(struct intel_bb *ibb,
 
 	address = intel_bb_offset_reloc(ibb, buf->handle,
 					read_domain, write_domain,
-					offset + 4, 0x0);
+					offset + 4, buf->addr.offset);
 	igt_assert(address >> 32 == 0);
 
 	ss->ss1.base_addr = address;
@@ -161,7 +161,7 @@ gen8_fill_surface_state(struct intel_bb *ibb,
 
 	address = intel_bb_offset_reloc(ibb, buf->handle,
 					read_domain, write_domain,
-					offset + 4 * 8, 0x0);
+					offset + 4 * 8, buf->addr.offset);
 
 	ss->ss8.base_addr = (uint32_t) address;
 	ss->ss9.base_addr_hi = address >> 32;
@@ -218,7 +218,7 @@ gen11_fill_surface_state(struct intel_bb *ibb,
 
 	address = intel_bb_offset_reloc(ibb, buf->handle,
 					read_domain, write_domain,
-					offset + 4 * 8, 0x0);
+					offset + 4 * 8, buf->addr.offset);
 
 	ss->ss8.base_addr = (uint32_t) address;
 	ss->ss9.base_addr_hi = address >> 32;
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 3a4fae4e..95217cfe 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -18,6 +18,10 @@ struct intel_buf {
 		uint32_t offset;
 		uint32_t stride;
 	} aux;
+	struct {
+		uint64_t offset;
+		uint32_t ctx;
+	} addr;
 };
 
 static inline unsigned int intel_buf_width(const struct intel_buf *buf)
-- 
2.26.0

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[igt-dev] [PATCH i-g-t 2/4] lib/intel_batchbuffer: add bb reset

[Zbigniew Kempczyński]

For some scenarios we want to keep previous objects and their offsets
and recreate only batchbuffer object. To allow user do that add
bb reset function which can or not purge collected objects from
previous run.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 84 +++++++++++++++++++++++++++++++++++------
 lib/intel_batchbuffer.h | 12 ++++--
 2 files changed, 81 insertions(+), 15 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 49f2d0fe..2a882627 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1203,7 +1203,7 @@ static void __reallocate_objects(struct intel_bb *ibb)
 }
 
 /**
- * __intel_bb_create:
+ * intel_bb_create:
  * @i915: drm fd
  * @size: size of the batchbuffer
  *
@@ -1250,6 +1250,26 @@ static void __do_nothing(void *node)
 	(void) node;
 }
 
+static void __intel_bb_destroy_objects(struct intel_bb *ibb)
+{
+	uint32_t i;
+
+	/* Free relocations */
+	for (i = 0; i < ibb->num_objects; i++)
+		free(from_user_pointer(ibb->objects[i].relocs_ptr));
+
+	free(ibb->objects);
+	tdestroy(ibb->root, __do_nothing);
+
+	ibb->objects = NULL;
+	ibb->root = NULL;
+	ibb->num_objects = 0;
+	ibb->num_relocs = 0;
+	ibb->allocated_objects = 0;
+	ibb->allocated_relocs = 0;
+	ibb->ptr = ibb->batch;
+}
+
 /**
  * intel_bb_destroy:
  * @ibb: pointer to intel_bb
@@ -1258,21 +1278,33 @@ static void __do_nothing(void *node)
  */
 void intel_bb_destroy(struct intel_bb *ibb)
 {
-	uint32_t i;
-
 	igt_assert(ibb);
 
-	/* Free relocations */
-	for (i = 0; i < ibb->num_objects; i++)
-		free(from_user_pointer(ibb->objects[i].relocs_ptr));
+	__intel_bb_destroy_objects(ibb);
+	gem_close(ibb->i915, ibb->handle);
 
-	free(ibb->objects);
-	tdestroy(ibb->root, __do_nothing);
+	free(ibb);
+}
+
+/*
+ * intel_bb_reset:
+ * @ibb: pointer to intel_bb
+ * @purge_objects_cache: if true destroy internal execobj and relocs + cache
+ *
+ * Recreate batch bo.
+*/
+void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
+{
+	if (purge_objects_cache) {
+		__intel_bb_destroy_objects(ibb);
+		__reallocate_objects(ibb);
+	}
 
-	munmap(ibb->batch, ibb->size);
 	gem_close(ibb->i915, ibb->handle);
+	ibb->handle = gem_create(ibb->i915, ibb->size);
 
-	free(ibb);
+	intel_bb_add_object(ibb, ibb->handle, 0, false);
+	ibb->ptr = ibb->batch;
 }
 
 /**
@@ -1573,7 +1605,7 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 	execbuf.buffers_ptr = (uintptr_t) ibb->objects;
 	execbuf.buffer_count = ibb->num_objects;
 	execbuf.batch_len = end_offset;
-	execbuf.rsvd1 = ctx;
+	execbuf.rsvd1 = ibb->ctx = ctx;
 	execbuf.flags = flags | I915_EXEC_BATCH_FIRST;
 
 	ret = __gem_execbuf(ibb->i915, &execbuf);
@@ -1649,3 +1681,33 @@ uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle)
 
 	return (*found)->offset;
 }
+
+/**
+ * intel_bb_object_offset_to_buf:
+ * @ibb: pointer to intel_bb
+ * @buf: buffer we want to store last exec offset and context id
+ *
+ * Copy object offset used in the batch to intel_buf to allow caller prepare
+ * other batch likely without relocations.
+ */
+bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf)
+{
+	struct drm_i915_gem_exec_object2 object = { .handle = buf->handle };
+	struct drm_i915_gem_exec_object2 **found;
+
+	igt_assert(ibb);
+	igt_assert(buf);
+
+	found = tfind((void *) &object, &ibb->root, __compare_objects);
+	if (!found) {
+		buf->addr.offset = 0;
+		buf->addr.ctx = 0;
+
+		return false;
+	}
+
+	buf->addr.offset = (*found)->offset;
+	buf->addr.ctx = ibb->ctx;
+
+	return true;
+}
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index ae052c17..0649fc22 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -405,8 +405,8 @@ igt_vme_func_t igt_get_media_vme_func(int devid);
 
 /**
  * igt_media_spinfunc_t:
- * @batch: batchbuffer object
- * @dst: destination i-g-t buffer object
+ * @i915: drm fd
+ * @buf: destination buffer object
  * @spins: number of loops to execute
  *
  * This is the type of the per-platform media spin functions. The
@@ -420,8 +420,8 @@ igt_vme_func_t igt_get_media_vme_func(int devid);
  * destination buffer on completion. This utility provides a simple way
  * to keep the render engine busy for a set time for various tests.
  */
-typedef void (*igt_media_spinfunc_t)(struct intel_batchbuffer *batch,
-				     const struct igt_buf *dst, uint32_t spins);
+typedef void (*igt_media_spinfunc_t)(int i915,
+				     struct intel_buf *buf, uint32_t spins);
 
 igt_media_spinfunc_t igt_get_media_spinfunc(int devid);
 
@@ -443,6 +443,8 @@ struct intel_bb {
 	uint64_t gtt_size;
 	bool supports_48b_address;
 
+	uint32_t ctx;
+
 	void *root;
 	struct drm_i915_gem_exec_object2 *objects;
 	uint32_t num_objects;
@@ -457,6 +459,7 @@ struct intel_bb {
 struct intel_bb *intel_bb_create(int i915, uint32_t size);
 
 void intel_bb_destroy(struct intel_bb *ibb);
+void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache);
 void intel_bb_set_debug(struct intel_bb *ibb, bool debug);
 
 static inline uint32_t intel_bb_offset(struct intel_bb *ibb)
@@ -524,5 +527,6 @@ void intel_bb_exec_with_context(struct intel_bb *ibb, uint32_t end_offset,
 				uint32_t ctx, uint64_t flags, bool sync);
 
 uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle);
+bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf);
 
 #endif
-- 
2.26.0

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[igt-dev] [PATCH i-g-t 3/4] tests/i915_pm_sseu: remove libdrm dependency

[Zbigniew Kempczyński]

Remove all "localized" functions in media spin and libdrm usage
in the test.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/media_spin.c          | 469 +++++---------------------------------
 lib/media_spin.h          |   8 +-
 tests/i915/i915_pm_sseu.c |  69 +++---
 3 files changed, 94 insertions(+), 452 deletions(-)

diff --git a/lib/media_spin.c b/lib/media_spin.c
index d3d0c278..6e81a13d 100644
--- a/lib/media_spin.c
+++ b/lib/media_spin.c
@@ -24,15 +24,13 @@
  * 	Jeff McGee <jeff.mcgee@intel.com>
  */
 
-#include <intel_bufmgr.h>
 #include <i915_drm.h>
 #include "intel_reg.h"
 #include "drmtest.h"
 #include "intel_batchbuffer.h"
 #include "intel_chipset.h"
-#include "gen7_media.h"
-#include "gen8_media.h"
 #include "media_spin.h"
+#include "gpu_cmds.h"
 
 static const uint32_t spin_kernel[][4] = {
 	{ 0x00600001, 0x20800208, 0x008d0000, 0x00000000 }, /* mov (8)r4.0<1>:ud r0.0<8;8;1>:ud */
@@ -67,6 +65,7 @@ static const uint32_t spin_kernel[][4] = {
  *
  */
 
+#define PAGE_SIZE 4096
 #define BATCH_STATE_SPLIT 2048
 /* VFE STATE params */
 #define THREADS 0
@@ -80,455 +79,113 @@ static const uint32_t spin_kernel[][4] = {
 #define xoffset 0
 #define yoffset 0
 
-static void
-gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
-{
-	int ret;
-
-	ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
-	if (ret == 0)
-		ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
-					    NULL, 0, 0, 0);
-	igt_assert(ret == 0);
-}
-
 static uint32_t
-gen7_fill_kernel(struct intel_batchbuffer *batch,
-		 const uint32_t kernel[][4], size_t size)
-{
-	uint32_t offset;
-
-	offset = intel_batchbuffer_copy_data(batch, kernel, size, 64);
-
-	return offset;
-}
-
-static uint32_t
-gen7_fill_surface_state(struct intel_batchbuffer *batch,
-			const struct igt_buf *buf,
-			uint32_t format,
-			int is_dst)
-{
-	struct gen7_surface_state *ss;
-	uint32_t write_domain, read_domain, offset;
-	int ret;
-
-	if (is_dst) {
-		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
-	} else {
-		write_domain = 0;
-		read_domain = I915_GEM_DOMAIN_SAMPLER;
-	}
-
-	ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
-	offset = intel_batchbuffer_subdata_offset(batch, ss);
-
-	ss->ss0.surface_type = SURFACE_2D;
-	ss->ss0.surface_format = format;
-	ss->ss0.render_cache_read_write = 1;
-
-	if (buf->tiling == I915_TILING_X)
-		ss->ss0.tiled_mode = 2;
-	else if (buf->tiling == I915_TILING_Y)
-		ss->ss0.tiled_mode = 3;
-
-	ss->ss1.base_addr = buf->bo->offset;
-	ret = drm_intel_bo_emit_reloc(batch->bo,
-				intel_batchbuffer_subdata_offset(batch, ss) + 4,
-				buf->bo, 0,
-				read_domain, write_domain);
-	igt_assert(ret == 0);
-
-	ss->ss2.height = igt_buf_height(buf) - 1;
-	ss->ss2.width  = igt_buf_width(buf) - 1;
-
-	ss->ss3.pitch  = buf->surface[0].stride - 1;
-
-	ss->ss7.shader_chanel_select_r = 4;
-	ss->ss7.shader_chanel_select_g = 5;
-	ss->ss7.shader_chanel_select_b = 6;
-	ss->ss7.shader_chanel_select_a = 7;
-
-	return offset;
-}
-
-static uint32_t
-gen8_fill_surface_state(struct intel_batchbuffer *batch,
-			const struct igt_buf *buf,
-			uint32_t format,
-			int is_dst)
-{
-	struct gen8_surface_state *ss;
-	uint32_t write_domain, read_domain, offset;
-	int ret;
-
-	if (is_dst) {
-		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
-	} else {
-		write_domain = 0;
-		read_domain = I915_GEM_DOMAIN_SAMPLER;
-	}
-
-	ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
-	offset = intel_batchbuffer_subdata_offset(batch, ss);
-
-	ss->ss0.surface_type = SURFACE_2D;
-	ss->ss0.surface_format = format;
-	ss->ss0.render_cache_read_write = 1;
-	ss->ss0.vertical_alignment = 1; /* align 4 */
-	ss->ss0.horizontal_alignment = 1; /* align 4 */
-
-	if (buf->tiling == I915_TILING_X)
-		ss->ss0.tiled_mode = 2;
-	else if (buf->tiling == I915_TILING_Y)
-		ss->ss0.tiled_mode = 3;
-
-	ss->ss8.base_addr = buf->bo->offset;
-
-	ret = drm_intel_bo_emit_reloc(batch->bo,
-				intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4,
-				buf->bo, 0, read_domain, write_domain);
-	igt_assert(ret == 0);
-
-	ss->ss2.height = igt_buf_height(buf) - 1;
-	ss->ss2.width  = igt_buf_width(buf) - 1;
-	ss->ss3.pitch  = buf->surface[0].stride - 1;
-
-	ss->ss7.shader_chanel_select_r = 4;
-	ss->ss7.shader_chanel_select_g = 5;
-	ss->ss7.shader_chanel_select_b = 6;
-	ss->ss7.shader_chanel_select_a = 7;
-
-	return offset;
-}
-
-static uint32_t
-gen8_spin_curbe_buffer_data(struct intel_batchbuffer *batch,
-			    uint32_t iters)
+gen8_spin_curbe_buffer_data(struct intel_bb *ibb, uint32_t iters)
 {
 	uint32_t *curbe_buffer;
 	uint32_t offset;
 
-	curbe_buffer = intel_batchbuffer_subdata_alloc(batch, 64, 64);
-	offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
-	*curbe_buffer = iters;
-
-	return offset;
-}
-
-static uint32_t
-gen7_fill_binding_table(struct intel_batchbuffer *batch,
-			const struct igt_buf *dst)
-{
-	uint32_t *binding_table, offset;
-
-	binding_table = intel_batchbuffer_subdata_alloc(batch, 32, 64);
-	offset = intel_batchbuffer_subdata_offset(batch, binding_table);
-	if (IS_GEN7(batch->devid))
-		binding_table[0] = gen7_fill_surface_state(batch, dst,
-						SURFACEFORMAT_R8_UNORM, 1);
-	else
-		binding_table[0] = gen8_fill_surface_state(batch, dst,
-						SURFACEFORMAT_R8_UNORM, 1);
-
-	return offset;
-}
-
-static uint32_t
-gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
-			       const struct igt_buf *dst,
-			       const uint32_t kernel[][4],
-			       size_t size)
-{
-	struct gen8_interface_descriptor_data *idd;
-	uint32_t offset;
-	uint32_t binding_table_offset, kernel_offset;
-
-	binding_table_offset = gen7_fill_binding_table(batch, dst);
-	kernel_offset = gen7_fill_kernel(batch, kernel, size);
-
-	idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
-	offset = intel_batchbuffer_subdata_offset(batch, idd);
+	intel_bb_ptr_align(ibb, 64);
+	curbe_buffer = intel_bb_ptr(ibb);
+	offset = intel_bb_offset(ibb);
 
-	idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
-
-	idd->desc2.single_program_flow = 1;
-	idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
-
-	idd->desc3.sampler_count = 0;      /* 0 samplers used */
-	idd->desc3.sampler_state_pointer = 0;
-
-	idd->desc4.binding_table_entry_count = 0;
-	idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
-
-	idd->desc5.constant_urb_entry_read_offset = 0;
-	idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
-
-	idd->desc6.num_threads_in_tg = 1;
+	*curbe_buffer = iters;
+	intel_bb_ptr_add(ibb, 64);
 
 	return offset;
 }
 
-static void
-gen8_emit_state_base_address(struct intel_batchbuffer *batch)
-{
-	OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2));
-
-	/* general */
-	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
-	OUT_BATCH(0);
-
-	/* stateless data port */
-	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
-
-	/* surface */
-	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
-
-	/* dynamic */
-	OUT_RELOC(batch->bo,
-		  I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
-		  0, BASE_ADDRESS_MODIFY);
-
-	/* indirect */
-	OUT_BATCH(0);
-	OUT_BATCH(0);
-
-	/* instruction */
-	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
-		  BASE_ADDRESS_MODIFY);
-
-	/* general state buffer size */
-	OUT_BATCH(0xfffff000 | 1);
-	/* dynamic state buffer size */
-	OUT_BATCH(1 << 12 | 1);
-	/* indirect object buffer size */
-	OUT_BATCH(0xfffff000 | 1);
-	/* instruction buffer size, must set modify enable bit, otherwise it may
-	 * result in GPU hang
-	 */
-	OUT_BATCH(1 << 12 | 1);
-}
-
-static void
-gen8_emit_vfe_state(struct intel_batchbuffer *batch, uint32_t threads,
-		    uint32_t urb_entries, uint32_t urb_size,
-		    uint32_t curbe_size)
-{
-	OUT_BATCH(GEN7_MEDIA_VFE_STATE | (9 - 2));
-
-	/* scratch buffer */
-	OUT_BATCH(0);
-	OUT_BATCH(0);
-
-	/* number of threads & urb entries */
-	OUT_BATCH(threads << 16 |
-		urb_entries << 8);
-
-	OUT_BATCH(0);
-
-	/* urb entry size & curbe size */
-	OUT_BATCH(urb_size << 16 |
-		curbe_size);
-
-	/* scoreboard */
-	OUT_BATCH(0);
-	OUT_BATCH(0);
-	OUT_BATCH(0);
-}
-
-static void
-gen7_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer)
-{
-	OUT_BATCH(GEN7_MEDIA_CURBE_LOAD | (4 - 2));
-	OUT_BATCH(0);
-	/* curbe total data length */
-	OUT_BATCH(64);
-	/* curbe data start address, is relative to the dynamics base address */
-	OUT_BATCH(curbe_buffer);
-}
-
-static void
-gen7_emit_interface_descriptor_load(struct intel_batchbuffer *batch,
-				    uint32_t interface_descriptor)
-{
-	OUT_BATCH(GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
-	OUT_BATCH(0);
-	/* interface descriptor data length */
-	if (IS_GEN7(batch->devid))
-		OUT_BATCH(sizeof(struct gen7_interface_descriptor_data));
-	else
-		OUT_BATCH(sizeof(struct gen8_interface_descriptor_data));
-	/* interface descriptor address, is relative to the dynamics base
-	 * address
-	 */
-	OUT_BATCH(interface_descriptor);
-}
-
-static void
-gen8_emit_media_state_flush(struct intel_batchbuffer *batch)
-{
-	OUT_BATCH(GEN8_MEDIA_STATE_FLUSH | (2 - 2));
-	OUT_BATCH(0);
-}
-
-static void
-gen_emit_media_object(struct intel_batchbuffer *batch,
-		      unsigned int xoff, unsigned int yoff)
-{
-	OUT_BATCH(GEN7_MEDIA_OBJECT | (8 - 2));
-
-	/* interface descriptor offset */
-	OUT_BATCH(0);
-
-	/* without indirect data */
-	OUT_BATCH(0);
-	OUT_BATCH(0);
-
-	/* scoreboard */
-	OUT_BATCH(0);
-	OUT_BATCH(0);
-
-	/* inline data (xoffset, yoffset) */
-	OUT_BATCH(xoff);
-	OUT_BATCH(yoff);
-	if (AT_LEAST_GEN(batch->devid, 8) && !IS_CHERRYVIEW(batch->devid))
-		gen8_emit_media_state_flush(batch);
-}
-
-static void
-gen9_emit_state_base_address(struct intel_batchbuffer *batch)
-{
-	OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (19 - 2));
-
-	/* general */
-	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
-	OUT_BATCH(0);
-
-	/* stateless data port */
-	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
-
-	/* surface */
-	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
-
-	/* dynamic */
-	OUT_RELOC(batch->bo,
-		  I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
-		  0, BASE_ADDRESS_MODIFY);
-
-	/* indirect */
-	OUT_BATCH(0);
-	OUT_BATCH(0);
-
-	/* instruction */
-	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
-		  BASE_ADDRESS_MODIFY);
-
-	/* general state buffer size */
-	OUT_BATCH(0xfffff000 | 1);
-	/* dynamic state buffer size */
-	OUT_BATCH(1 << 12 | 1);
-	/* indirect object buffer size */
-	OUT_BATCH(0xfffff000 | 1);
-	/* intruction buffer size, must set modify enable bit, otherwise it may
-	 * result in GPU hang
-	 */
-	OUT_BATCH(1 << 12 | 1);
-
-	/* Bindless surface state base address */
-	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
-	OUT_BATCH(0);
-	OUT_BATCH(0xfffff000);
-}
-
 void
-gen8_media_spinfunc(struct intel_batchbuffer *batch,
-		    const struct igt_buf *dst, uint32_t spins)
+gen8_media_spinfunc(int i915, struct intel_buf *buf, uint32_t spins)
 {
+	struct intel_bb *ibb;
 	uint32_t curbe_buffer, interface_descriptor;
-	uint32_t batch_end;
 
-	intel_batchbuffer_flush_with_context(batch, NULL);
+	ibb = intel_bb_create(i915, PAGE_SIZE);
+	intel_bb_add_object(ibb, buf->handle, 0, true);
 
 	/* setup states */
-	batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
 
-	curbe_buffer = gen8_spin_curbe_buffer_data(batch, spins);
-	interface_descriptor = gen8_fill_interface_descriptor(batch, dst,
+	curbe_buffer = gen8_spin_curbe_buffer_data(ibb, spins);
+	interface_descriptor = gen8_fill_interface_descriptor(ibb, buf,
 					      spin_kernel, sizeof(spin_kernel));
-	igt_assert(batch->ptr < &batch->buffer[4095]);
+
+	intel_bb_ptr_set(ibb, 0);
 
 	/* media pipeline */
-	batch->ptr = batch->buffer;
-	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
-	gen8_emit_state_base_address(batch);
+	intel_bb_out(ibb, GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
+	gen8_emit_state_base_address(ibb);
 
-	gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES,
+	gen8_emit_vfe_state(ibb, THREADS, MEDIA_URB_ENTRIES,
 			    MEDIA_URB_SIZE, MEDIA_CURBE_SIZE);
 
-	gen7_emit_curbe_load(batch, curbe_buffer);
+	gen7_emit_curbe_load(ibb, curbe_buffer);
 
-	gen7_emit_interface_descriptor_load(batch, interface_descriptor);
+	gen7_emit_interface_descriptor_load(ibb, interface_descriptor);
 
-	gen_emit_media_object(batch, xoffset, yoffset);
+	gen_emit_media_object(ibb, xoffset, yoffset);
 
-	OUT_BATCH(MI_BATCH_BUFFER_END);
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 32);
 
-	batch_end = intel_batchbuffer_align(batch, 8);
-	igt_assert(batch_end < BATCH_STATE_SPLIT);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
 
-	gen7_render_flush(batch, batch_end);
-	intel_batchbuffer_reset(batch);
+	intel_bb_object_offset_to_buf(ibb, buf);
+	intel_bb_destroy(ibb);
 }
 
-
 void
-gen9_media_spinfunc(struct intel_batchbuffer *batch,
-		    const struct igt_buf *dst, uint32_t spins)
+gen9_media_spinfunc(int i915, struct intel_buf *buf, uint32_t spins)
 {
+	struct intel_bb *ibb;
 	uint32_t curbe_buffer, interface_descriptor;
-	uint32_t batch_end;
 
-	intel_batchbuffer_flush_with_context(batch, NULL);
+	ibb = intel_bb_create(i915, PAGE_SIZE);
+	intel_bb_add_object(ibb, buf->handle, 0, true);
 
 	/* setup states */
-	batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
 
-	curbe_buffer = gen8_spin_curbe_buffer_data(batch, spins);
-	interface_descriptor = gen8_fill_interface_descriptor(batch, dst,
+	curbe_buffer = gen8_spin_curbe_buffer_data(ibb, spins);
+	interface_descriptor = gen8_fill_interface_descriptor(ibb, buf,
 					      spin_kernel, sizeof(spin_kernel));
-	igt_assert(batch->ptr < &batch->buffer[4095]);
+
+	intel_bb_ptr_set(ibb, 0);
 
 	/* media pipeline */
-	batch->ptr = batch->buffer;
-	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
-		  GEN9_FORCE_MEDIA_AWAKE_ENABLE |
-		  GEN9_SAMPLER_DOP_GATE_DISABLE |
-		  GEN9_PIPELINE_SELECTION_MASK |
-		  GEN9_SAMPLER_DOP_GATE_MASK |
-		  GEN9_FORCE_MEDIA_AWAKE_MASK);
-	gen9_emit_state_base_address(batch);
-
-	gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES,
+	intel_bb_out(ibb, GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+		     GEN9_FORCE_MEDIA_AWAKE_ENABLE |
+		     GEN9_SAMPLER_DOP_GATE_DISABLE |
+		     GEN9_PIPELINE_SELECTION_MASK |
+		     GEN9_SAMPLER_DOP_GATE_MASK |
+		     GEN9_FORCE_MEDIA_AWAKE_MASK);
+	gen9_emit_state_base_address(ibb);
+
+	gen8_emit_vfe_state(ibb, THREADS, MEDIA_URB_ENTRIES,
 			    MEDIA_URB_SIZE, MEDIA_CURBE_SIZE);
 
-	gen7_emit_curbe_load(batch, curbe_buffer);
+	gen7_emit_curbe_load(ibb, curbe_buffer);
+
+	gen7_emit_interface_descriptor_load(ibb, interface_descriptor);
 
-	gen7_emit_interface_descriptor_load(batch, interface_descriptor);
+	gen_emit_media_object(ibb, xoffset, yoffset);
 
-	gen_emit_media_object(batch, xoffset, yoffset);
+	intel_bb_out(ibb, GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+		     GEN9_FORCE_MEDIA_AWAKE_DISABLE |
+		     GEN9_SAMPLER_DOP_GATE_ENABLE |
+		     GEN9_PIPELINE_SELECTION_MASK |
+		     GEN9_SAMPLER_DOP_GATE_MASK |
+		     GEN9_FORCE_MEDIA_AWAKE_MASK);
 
-	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
-		  GEN9_FORCE_MEDIA_AWAKE_DISABLE |
-		  GEN9_SAMPLER_DOP_GATE_ENABLE |
-		  GEN9_PIPELINE_SELECTION_MASK |
-		  GEN9_SAMPLER_DOP_GATE_MASK |
-		  GEN9_FORCE_MEDIA_AWAKE_MASK);
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
 
-	OUT_BATCH(MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 32);
 
-	batch_end = intel_batchbuffer_align(batch, 8);
-	igt_assert(batch_end < BATCH_STATE_SPLIT);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
 
-	gen7_render_flush(batch, batch_end);
-	intel_batchbuffer_reset(batch);
+	intel_bb_object_offset_to_buf(ibb, buf);
+	intel_bb_destroy(ibb);
 }
diff --git a/lib/media_spin.h b/lib/media_spin.h
index 768eccc0..5e15e021 100644
--- a/lib/media_spin.h
+++ b/lib/media_spin.h
@@ -27,10 +27,10 @@
 #ifndef MEDIA_SPIN_H
 #define MEDIA_SPIN_H
 
-void gen8_media_spinfunc(struct intel_batchbuffer *batch,
-			 const struct igt_buf *dst, uint32_t spins);
+struct intel_buf;
 
-void gen9_media_spinfunc(struct intel_batchbuffer *batch,
-			 const struct igt_buf *dst, uint32_t spins);
+void gen8_media_spinfunc(int i915, struct intel_buf *buf, uint32_t spins);
+
+void gen9_media_spinfunc(int i915, struct intel_buf *buf, uint32_t spins);
 
 #endif /* MEDIA_SPIN_H */
diff --git a/tests/i915/i915_pm_sseu.c b/tests/i915/i915_pm_sseu.c
index 461c70cc..2f28bd56 100644
--- a/tests/i915/i915_pm_sseu.c
+++ b/tests/i915/i915_pm_sseu.c
@@ -34,7 +34,7 @@
 
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
+#include "intel_bufops.h"
 
 IGT_TEST_DESCRIPTION("Tests slice/subslice/EU power gating functionality.\n");
 
@@ -43,10 +43,10 @@ static struct {
 	int drm_fd;
 	int devid;
 	int gen;
-	drm_intel_bufmgr *bufmgr;
-	struct intel_batchbuffer *batch;
+
+	struct buf_ops *bops;
+	struct intel_buf buf;
 	igt_media_spinfunc_t spinfunc;
-	struct igt_buf buf;
 	uint32_t spins_per_msec;
 } gem;
 
@@ -233,11 +233,8 @@ dbg_deinit(void)
 }
 
 static void
-gem_check_spin(uint32_t spins)
+gem_check_spin(uint32_t *data, uint32_t spins)
 {
-	uint32_t *data;
-
-	data = (uint32_t*)gem.buf.bo->virtual;
 	igt_assert_eq_u32(*data, spins);
 }
 
@@ -246,8 +243,8 @@ gem_get_target_spins(double dt)
 {
 	struct timespec tstart, tdone;
 	double prev_dt, cur_dt;
-	uint32_t spins;
-	int i, ret;
+	uint32_t spins, *ptr;
+	int i;
 
 	/* Double increments until we bound the target time */
 	prev_dt = 0.0;
@@ -255,13 +252,17 @@ gem_get_target_spins(double dt)
 		spins = 1 << i;
 		clock_gettime(CLOCK_MONOTONIC, &tstart);
 
-		gem.spinfunc(gem.batch, &gem.buf, spins);
-		ret = drm_intel_bo_map(gem.buf.bo, 0);
-		igt_assert_eq(ret, 0);
+		gem.spinfunc(gem.drm_fd, &gem.buf, spins);
+		gem_sync(gem.drm_fd, gem.buf.handle);
+
+		ptr = gem_mmap__device_coherent(gem.drm_fd, gem.buf.handle,
+						0, gem.buf.size, PROT_READ);
+
 		clock_gettime(CLOCK_MONOTONIC, &tdone);
 
-		gem_check_spin(spins);
-		drm_intel_bo_unmap(gem.buf.bo);
+		gem_check_spin(ptr, spins);
+
+		munmap(ptr, gem.buf.size);
 
 		cur_dt = to_dt(&tstart, &tdone);
 		if (cur_dt > dt)
@@ -292,25 +293,12 @@ gem_init(void)
 	gem.spinfunc = igt_get_media_spinfunc(gem.devid);
 	igt_require(gem.spinfunc);
 
-	gem.bufmgr = drm_intel_bufmgr_gem_init(gem.drm_fd, 4096);
-	igt_assert(gem.bufmgr);
+	gem.bops = buf_ops_create(gem.drm_fd);
 	gem.init = 2;
 
-	drm_intel_bufmgr_gem_enable_reuse(gem.bufmgr);
-
-	gem.batch = intel_batchbuffer_alloc(gem.bufmgr, gem.devid);
-	igt_assert(gem.batch);
+	intel_buf_init(gem.bops, &gem.buf, 1, 1, 32, 0, I915_TILING_NONE, 0);
 	gem.init = 3;
 
-	gem.buf.surface[0].stride = sizeof(uint32_t);
-	gem.buf.tiling = I915_TILING_NONE;
-	gem.buf.surface[0].size = gem.buf.surface[0].stride;
-	gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "",
-					gem.buf.surface[0].size, 4096);
-	gem.buf.bpp = 32;
-	igt_assert(gem.buf.bo);
-	gem.init = 4;
-
 	gem.spins_per_msec = gem_get_target_spins(100) / 100;
 }
 
@@ -319,13 +307,10 @@ gem_deinit(void)
 {
 	switch (gem.init)
 	{
-	case 4:
-		drm_intel_bo_unmap(gem.buf.bo);
-		drm_intel_bo_unreference(gem.buf.bo);
 	case 3:
-		intel_batchbuffer_free(gem.batch);
+		intel_buf_close(gem.bops, &gem.buf);
 	case 2:
-		drm_intel_bufmgr_destroy(gem.bufmgr);
+		buf_ops_destroy(gem.bops);
 	case 1:
 		close(gem.drm_fd);
 	}
@@ -354,7 +339,8 @@ full_enable(void)
 {
 	struct status stat;
 	const int spin_msec = 10;
-	int ret, spins;
+	uint32_t *ptr;
+	int spins;
 
 	/*
 	 * Gen9 SKL is the first case in which render power gating can leave
@@ -365,16 +351,15 @@ full_enable(void)
 
 	spins = spin_msec * gem.spins_per_msec;
 
-	gem.spinfunc(gem.batch, &gem.buf, spins);
+	gem.spinfunc(gem.drm_fd, &gem.buf, spins);
 
 	usleep(2000); /* 2ms wait to make sure batch is running */
 	dbg_get_status(&stat);
 
-	ret = drm_intel_bo_map(gem.buf.bo, 0);
-	igt_assert_eq(ret, 0);
-
-	gem_check_spin(spins);
-	drm_intel_bo_unmap(gem.buf.bo);
+	ptr = gem_mmap__device_coherent(gem.drm_fd, gem.buf.handle,
+					0, gem.buf.size, PROT_READ);
+	gem_check_spin(ptr, spins);
+	munmap(ptr, gem.buf.size);
 
 	check_full_enable(&stat);
 }
-- 
2.26.0

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[igt-dev] [PATCH i-g-t 4/4] HAX: run gpgpu|media_fill and i915_pm_sseu in BAT only

[Zbigniew Kempczyński]

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel-ci/fast-feedback.testlist | 162 +-------------------------
 1 file changed, 3 insertions(+), 159 deletions(-)

diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index 04f6affc..694c00c6 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -1,162 +1,6 @@
 # Keep alphabetically sorted by default
 
-igt@core_auth@basic-auth
-igt@debugfs_test@read_all_entries
-igt@fbdev@mmap
-igt@gem_basic@bad-close
-igt@gem_basic@create-close
-igt@gem_basic@create-fd-close
-igt@gem_busy@busy@all
-igt@gem_close_race@basic-process
-igt@gem_close_race@basic-threads
-igt@gem_ctx_create@basic
-igt@gem_ctx_create@basic-files
-igt@gem_ctx_exec@basic
-igt@gem_exec_basic@basic
-igt@gem_exec_create@basic
-igt@gem_exec_fence@basic-busy
-igt@gem_exec_fence@basic-wait
-igt@gem_exec_fence@basic-await
-igt@gem_exec_fence@nb-await
-igt@gem_exec_gttfill@basic
-igt@gem_exec_parallel@engines
-igt@gem_exec_store@basic
-igt@gem_exec_suspend@basic-s0
-igt@gem_exec_suspend@basic-s3
-igt@gem_flink_basic@bad-flink
-igt@gem_flink_basic@bad-open
-igt@gem_flink_basic@basic
-igt@gem_flink_basic@double-flink
-igt@gem_flink_basic@flink-lifetime
-igt@gem_linear_blits@basic
-igt@gem_mmap@basic
-igt@gem_mmap_gtt@basic
-igt@gem_render_linear_blits@basic
-igt@gem_render_tiled_blits@basic
-igt@gem_ringfill@basic-all
-igt@gem_sync@basic-all
-igt@gem_sync@basic-each
-igt@gem_tiled_blits@basic
-igt@gem_tiled_fence_blits@basic
-igt@gem_tiled_pread_basic
-igt@gem_wait@busy@all
-igt@gem_wait@wait@all
-igt@i915_getparams_basic@basic-eu-total
-igt@i915_getparams_basic@basic-subslice-total
-igt@i915_hangman@error-state-basic
-igt@kms_addfb_basic@addfb25-bad-modifier
-igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling
-igt@kms_addfb_basic@addfb25-modifier-no-flag
-igt@kms_addfb_basic@addfb25-x-tiled
-igt@kms_addfb_basic@addfb25-x-tiled-mismatch
-igt@kms_addfb_basic@addfb25-yf-tiled
-igt@kms_addfb_basic@addfb25-y-tiled
-igt@kms_addfb_basic@addfb25-y-tiled-small
-igt@kms_addfb_basic@bad-pitch-0
-igt@kms_addfb_basic@bad-pitch-1024
-igt@kms_addfb_basic@bad-pitch-128
-igt@kms_addfb_basic@bad-pitch-256
-igt@kms_addfb_basic@bad-pitch-32
-igt@kms_addfb_basic@bad-pitch-63
-igt@kms_addfb_basic@bad-pitch-65536
-igt@kms_addfb_basic@bad-pitch-999
-igt@kms_addfb_basic@basic
-igt@kms_addfb_basic@basic-x-tiled
-igt@kms_addfb_basic@basic-y-tiled
-igt@kms_addfb_basic@bo-too-small
-igt@kms_addfb_basic@bo-too-small-due-to-tiling
-igt@kms_addfb_basic@clobberred-modifier
-igt@kms_addfb_basic@framebuffer-vs-set-tiling
-igt@kms_addfb_basic@invalid-get-prop
-igt@kms_addfb_basic@invalid-get-prop-any
-igt@kms_addfb_basic@invalid-set-prop
-igt@kms_addfb_basic@invalid-set-prop-any
-igt@kms_addfb_basic@no-handle
-igt@kms_addfb_basic@size-max
-igt@kms_addfb_basic@small-bo
-igt@kms_addfb_basic@tile-pitch-mismatch
-igt@kms_addfb_basic@too-high
-igt@kms_addfb_basic@too-wide
-igt@kms_addfb_basic@unused-handle
-igt@kms_addfb_basic@unused-modifier
-igt@kms_addfb_basic@unused-offsets
-igt@kms_addfb_basic@unused-pitches
-igt@kms_busy@basic
-igt@kms_chamelium@dp-hpd-fast
-igt@kms_chamelium@dp-edid-read
-igt@kms_chamelium@dp-crc-fast
-igt@kms_chamelium@hdmi-hpd-fast
-igt@kms_chamelium@hdmi-edid-read
-igt@kms_chamelium@hdmi-crc-fast
-igt@kms_chamelium@vga-hpd-fast
-igt@kms_chamelium@vga-edid-read
-igt@kms_chamelium@common-hpd-after-suspend
-igt@kms_prop_blob@basic
-igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic
-igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy
-igt@kms_cursor_legacy@basic-flip-after-cursor-atomic
-igt@kms_cursor_legacy@basic-flip-after-cursor-legacy
-igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size
-igt@kms_cursor_legacy@basic-flip-before-cursor-atomic
-igt@kms_cursor_legacy@basic-flip-before-cursor-legacy
-igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size
-igt@kms_flip@basic-flip-vs-dpms
-igt@kms_flip@basic-flip-vs-modeset
-igt@kms_flip@basic-flip-vs-wf_vblank
-igt@kms_flip@basic-plain-flip
-igt@kms_force_connector_basic@force-connector-state
-igt@kms_force_connector_basic@force-edid
-igt@kms_force_connector_basic@force-load-detect
-igt@kms_force_connector_basic@prune-stale-modes
-igt@kms_frontbuffer_tracking@basic
-igt@kms_pipe_crc_basic@hang-read-crc-pipe-a
-igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a
-igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence
-igt@kms_pipe_crc_basic@read-crc-pipe-a
-igt@kms_pipe_crc_basic@read-crc-pipe-b
-igt@kms_pipe_crc_basic@read-crc-pipe-c
-igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence
-igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a
-igt@kms_psr@primary_page_flip
-igt@kms_psr@cursor_plane_move
-igt@kms_psr@sprite_plane_onoff
-igt@kms_psr@primary_mmap_gtt
-igt@kms_setmode@basic-clone-single-crtc
-igt@i915_pm_backlight@basic-brightness
-igt@i915_pm_rpm@basic-pci-d3-state
-igt@i915_pm_rpm@basic-rte
-igt@i915_pm_rps@basic-api
-igt@prime_self_import@basic-llseek-bad
-igt@prime_self_import@basic-llseek-size
-igt@prime_self_import@basic-with_fd_dup
-igt@prime_self_import@basic-with_one_bo
-igt@prime_self_import@basic-with_one_bo_two_files
-igt@prime_self_import@basic-with_two_bos
-igt@prime_vgem@basic-fence-flip
-igt@prime_vgem@basic-fence-mmap
-igt@prime_vgem@basic-fence-read
-igt@prime_vgem@basic-gtt
-igt@prime_vgem@basic-read
-igt@prime_vgem@basic-write
-igt@vgem_basic@setversion
-igt@vgem_basic@create
-igt@vgem_basic@debugfs
-igt@vgem_basic@dmabuf-export
-igt@vgem_basic@dmabuf-fence
-igt@vgem_basic@dmabuf-fence-before
-igt@vgem_basic@dmabuf-mmap
-igt@vgem_basic@mmap
-igt@vgem_basic@second-client
-igt@vgem_basic@sysfs
+igt@gem_gpgpu_fill
+igt@gem_media_fill
+igt@i915_pm_sseu
 
-# All tests that do module unloading and reloading are executed last.
-# They will sometimes reveal issues of earlier tests leaving the
-# driver in a broken state that is not otherwise noticed in that test.
-
-igt@vgem_basic@unload
-igt@i915_module_load@reload
-igt@i915_pm_rpm@module-reload
-
-# Kernel selftests
-igt@i915_selftest@live
-igt@dmabuf@all
-- 
2.26.0

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[igt-dev] ✗ Fi.CI.BAT: failure for Remove libdrm from media_spin

[Patchwork]

== Series Details ==

Series: Remove libdrm from media_spin
URL   : https://patchwork.freedesktop.org/series/77951/
State : failure

== Summary ==

CI Bug Log - changes from IGT_5694 -> IGTPW_4644
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_4644 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_4644, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_4644:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_sseu@full-enable:
    - fi-kbl-soraka:      NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-kbl-soraka/igt@i915_pm_sseu@full-enable.html
    - fi-skl-6600u:       NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-skl-6600u/igt@i915_pm_sseu@full-enable.html
    - fi-whl-u:           NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-whl-u/igt@i915_pm_sseu@full-enable.html
    - fi-cfl-guc:         NOTRUN -> [FAIL][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-cfl-guc/igt@i915_pm_sseu@full-enable.html
    - fi-cml-s:           NOTRUN -> [FAIL][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-cml-s/igt@i915_pm_sseu@full-enable.html
    - fi-apl-guc:         NOTRUN -> [FAIL][6]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-apl-guc/igt@i915_pm_sseu@full-enable.html
    - fi-bxt-dsi:         NOTRUN -> [FAIL][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-bxt-dsi/igt@i915_pm_sseu@full-enable.html
    - fi-cfl-8700k:       NOTRUN -> [FAIL][8]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-cfl-8700k/igt@i915_pm_sseu@full-enable.html
    - fi-cml-u2:          NOTRUN -> [FAIL][9]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-cml-u2/igt@i915_pm_sseu@full-enable.html
    - fi-kbl-r:           NOTRUN -> [FAIL][10]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-kbl-r/igt@i915_pm_sseu@full-enable.html
    - fi-kbl-8809g:       NOTRUN -> [FAIL][11]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-kbl-8809g/igt@i915_pm_sseu@full-enable.html
    - fi-kbl-guc:         NOTRUN -> [FAIL][12]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-kbl-guc/igt@i915_pm_sseu@full-enable.html
    - fi-kbl-7500u:       NOTRUN -> [FAIL][13]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-kbl-7500u/igt@i915_pm_sseu@full-enable.html
    - fi-cfl-8109u:       NOTRUN -> [FAIL][14]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-cfl-8109u/igt@i915_pm_sseu@full-enable.html
    - fi-skl-guc:         NOTRUN -> [FAIL][15]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-skl-guc/igt@i915_pm_sseu@full-enable.html
    - fi-kbl-x1275:       NOTRUN -> [FAIL][16]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-kbl-x1275/igt@i915_pm_sseu@full-enable.html
    - fi-glk-dsi:         NOTRUN -> [FAIL][17]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-glk-dsi/igt@i915_pm_sseu@full-enable.html
    - fi-skl-6700k2:      NOTRUN -> [FAIL][18]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-skl-6700k2/igt@i915_pm_sseu@full-enable.html
    - fi-skl-lmem:        NOTRUN -> [FAIL][19]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/fi-skl-lmem/igt@i915_pm_sseu@full-enable.html

  
New tests
---------

  New tests have been introduced between IGT_5694 and IGTPW_4644:

### New IGT tests (1) ###

  * igt@i915_pm_sseu:
    - Statuses :
    - Exec time: [None] s

  



Participating hosts (50 -> 44)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5694 -> IGTPW_4644

  CI-20190529: 20190529
  CI_DRM_8575: b261605291bae8f267174f92df7513a3a7184573 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4644: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/index.html
  IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4644/index.html
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