[igt-dev] [PATCH i-g-t,v2 0/3] Add testing for CCS

[igt-dev] [PATCH i-g-t,v2 0/3] Add testing for CCS

[apoorva1.singh]

From: Apoorva Singh <apoorva1.singh@intel.com>

- Add new libraries i915_blt and intel_mocs for various blt
  commands and mocs settings.

- Add a new platform flag, has_flat_ccs, for platforms
  supporting Flat CCS.

- Add gem_ccs test for CCS testing.
  Commands are constructed with XY_BLOCK_COPY_BLT
  and XY_CTRL_SURF_COPY_BLT instructions.

Apoorva Singh (2):
  lib/i915: Introduce libraries i915_blt and intel_mocs
  lib/intel_chipset.h: Add has_flat_ccs flag

CQ Tang (1):
  i915/gem_ccs: Add testing for CCS

 lib/i915/gem_engine_topology.c |  38 ++
 lib/i915/gem_engine_topology.h |   5 +
 lib/i915/i915_blt.c            | 419 +++++++++++++++++++++
 lib/i915/i915_blt.h            |  93 +++++
 lib/i915/intel_mocs.c          |  75 ++++
 lib/i915/intel_mocs.h          |  43 +++
 lib/intel_chipset.h            |   3 +
 lib/meson.build                |   2 +
 tests/i915/gem_ccs.c           | 640 +++++++++++++++++++++++++++++++++
 tests/meson.build              |   1 +
 10 files changed, 1319 insertions(+)
 create mode 100644 lib/i915/i915_blt.c
 create mode 100644 lib/i915/i915_blt.h
 create mode 100644 lib/i915/intel_mocs.c
 create mode 100644 lib/i915/intel_mocs.h
 create mode 100644 tests/i915/gem_ccs.c

-- 
2.25.1

[igt-dev] [PATCH i-g-t, v2 1/3] lib/i915: Introduce libraries i915_blt and intel_mocs

[apoorva1.singh]

From: Apoorva Singh <apoorva1.singh@intel.com>

Add new libraries i915_blt and intel_mocs for various blt
commands and mocs settings.

Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
---
 lib/i915/i915_blt.c   | 419 ++++++++++++++++++++++++++++++++++++++++++
 lib/i915/i915_blt.h   |  93 ++++++++++
 lib/i915/intel_mocs.c |  75 ++++++++
 lib/i915/intel_mocs.h |  43 +++++
 lib/meson.build       |   2 +
 5 files changed, 632 insertions(+)
 create mode 100644 lib/i915/i915_blt.c
 create mode 100644 lib/i915/i915_blt.h
 create mode 100644 lib/i915/intel_mocs.c
 create mode 100644 lib/i915/intel_mocs.h

diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
new file mode 100644
index 00000000..a3771f40
--- /dev/null
+++ b/lib/i915/i915_blt.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *	Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
+ *
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+#include "i915_blt.h"
+#include "i915/intel_mocs.h"
+
+/*
+ * make_block_copy_batch:
+ * @fd: open i915 drm file descriptor
+ * @batch_buf: the batch buffer to populate with the command
+ * @src: fd of the source BO
+ * @dst: fd of the destination BO
+ * @length: size of the src and dest BOs
+ * @reloc: pointer to the relocation entyr for this command
+ * @src_mem_type: source memory type (denotes direct or indirect
+ *			addressing)
+ * @dst_mem_type: destination memory type (denotes direct or indirect
+ *			addressing)
+ * @src_compression: flag to enable uncompressed read of compressed data
+ *			at the source
+ * @dst_compression: flag to enable compressed write at the destination
+ * @resolve: flag to enable resolve of compressed data
+ */
+static int make_block_copy_batch(int fd, uint32_t *batch_buf,
+				 uint32_t src, uint32_t dst, uint32_t length,
+				 struct drm_i915_gem_relocation_entry *reloc,
+				 int src_mem_type, int dst_mem_type,
+				 int src_compression, int dst_compression,
+				 int resolve)
+{
+	uint32_t *b = batch_buf;
+	uint8_t src_mocs = intel_get_uc_mocs(fd);
+	uint8_t dst_mocs = src_mocs;
+
+	/* BG 0 */
+	b[0] = BLOCK_COPY_BLT_CMD | resolve;
+
+	/* BG 1
+	 *
+	 * Using Tile 4 dimensions.  Height = 32 rows
+	 * Width = 128 bytes
+	 */
+	b[1] = dst_compression | TILE_4_FORMAT | TILE_4_WIDTH_DWORD |
+		dst_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
+
+	/* BG 3
+	 *
+	 * X2 = TILE_4_WIDTH
+	 * Y2 = (length / TILE_4_WIDTH) << 16:
+	 */
+	b[3] = TILE_4_WIDTH | (length >> 7) << DEST_Y2_COORDINATE_SHIFT;
+
+	/* relocate address in b[4] and b[5] */
+	reloc->offset = 4 * (sizeof(uint32_t));
+	reloc->delta = 0;
+	reloc->target_handle = dst;
+	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc->write_domain = I915_GEM_DOMAIN_RENDER;
+	reloc->presumed_offset = 0;
+	reloc++;
+
+	/* BG 6 */
+	b[6] = dst_mem_type << DEST_MEM_TYPE_SHIFT;
+
+	/* BG 8 */
+	b[8] = src_compression | TILE_4_WIDTH_DWORD | TILE_4_FORMAT |
+		src_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
+
+	/* relocate address in b[9] and b[10] */
+	reloc->offset = 9 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle = src;
+	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+
+	/* BG 11 */
+	b[11] = src_mem_type << SRC_MEM_TYPE_SHIFT;
+
+	/* BG 16  */
+	b[16] = SURFACE_TYPE_2D |
+		((TILE_4_WIDTH - 1) << DEST_SURF_WIDTH_SHIFT) |
+		(TILE_4_HEIGHT - 1);
+
+	/* BG 19 */
+	b[19] = SURFACE_TYPE_2D |
+		((TILE_4_WIDTH - 1) << SRC_SURF_WIDTH_SHIFT) |
+		(TILE_4_HEIGHT - 1);
+
+	b += XY_BLOCK_COPY_BLT_LEN_DWORD;
+
+	b[0] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
+	reloc->offset = 23 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle = dst_compression > 0 ? dst : src;
+	reloc->read_domains = 0;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+	b[3] = 0;
+
+	b[4] = MI_FLUSH_DW | MI_FLUSH_CCS;
+	reloc->offset = 27 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle = dst_compression > 0 ? dst : src;
+	reloc->read_domains = 0;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+	b[7] = 0;
+
+	b[8] = MI_BATCH_BUFFER_END;
+	b[9] = 0;
+
+	b += 10;
+
+	return (b - batch_buf) * sizeof(uint32_t);
+}
+
+static int __xy_block_copy_blt(int fd, uint32_t cmd,
+			       uint32_t *batch_buf,
+			       uint32_t src, uint32_t dst,
+			       uint32_t length, int mode, uint32_t ctx,
+			       struct intel_execution_engine2 *e)
+{
+	struct drm_i915_gem_relocation_entry reloc[4];
+	struct drm_i915_gem_exec_object2 exec[3];
+	struct drm_i915_gem_execbuffer2 execbuf;
+	int len;
+	int src_mem_type, dst_mem_type;
+	int dst_compression, src_compression;
+	int resolve;
+	uint64_t ahnd = get_reloc_ahnd(fd, 0);
+
+	if (mode == 2) { /* in-place decompress */
+		src_mem_type = MEM_TYPE_LOCAL;
+		dst_mem_type = MEM_TYPE_LOCAL;
+		src_compression = COMPRESSION_ENABLE | AUX_CCS_E;
+		dst_compression = COMPRESSION_ENABLE | AUX_CCS_E;
+		resolve = FULL_RESOLVE;
+	} else if (mode == 1) { /* copy from smem to lmem */
+		src_mem_type = MEM_TYPE_SYS;
+		dst_mem_type = MEM_TYPE_LOCAL;
+		src_compression = 0;
+		dst_compression = COMPRESSION_ENABLE | AUX_CCS_E;
+		resolve = 0;
+	} else { /* copy from lmem to smem */
+		src_mem_type = MEM_TYPE_LOCAL;
+		dst_mem_type = MEM_TYPE_SYS;
+		src_compression = COMPRESSION_ENABLE | AUX_CCS_E;
+		dst_compression = 0;
+		resolve = 0;
+	}
+
+	/* construct the batch buffer */
+	memset(reloc, 0, sizeof(reloc));
+	memset(batch_buf, 0, BATCH_SIZE);
+	len = make_block_copy_batch(fd, batch_buf,
+				    src, dst, length, reloc,
+				    src_mem_type, dst_mem_type,
+				    src_compression, dst_compression,
+				    resolve);
+	igt_assert(len > 0);
+
+	/* write batch buffer to 'cmd' BO */
+	gem_write(fd, cmd, 0, batch_buf, len);
+
+	/* Execute the batch buffer */
+	memset(exec, 0, sizeof(exec));
+	if (mode == 2) {
+		exec[0].handle = dst;
+		exec[1].handle = cmd;
+		exec[1].relocation_count = !ahnd ? 4 : 0;
+		exec[1].relocs_ptr = to_user_pointer(reloc);
+		if (ahnd) {
+			exec[0].offset = get_offset(ahnd, exec[0].handle, length * CCS_RATIO, 0);
+			exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+			exec[1].offset = get_offset(ahnd, exec[1].handle, BATCH_SIZE, 0);
+			exec[1].flags |= EXEC_OBJECT_PINNED;
+		}
+	} else {
+		exec[0].handle = src;
+		exec[1].handle = dst;
+		exec[2].handle = cmd;
+		exec[2].relocation_count = !ahnd ? 4 : 0;
+		exec[2].relocs_ptr = to_user_pointer(reloc);
+		if (ahnd) {
+			exec[0].offset = get_offset(ahnd, exec[0].handle, length * CCS_RATIO, 0);
+			exec[0].flags |= EXEC_OBJECT_PINNED;
+			exec[1].offset = get_offset(ahnd, exec[1].handle, length * CCS_RATIO, 0);
+			exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+			exec[2].offset = get_offset(ahnd, exec[2].handle, BATCH_SIZE, 0);
+			exec[2].flags |= EXEC_OBJECT_PINNED;
+		}
+	}
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(exec);
+	if (mode == 2)
+		execbuf.buffer_count = 2;
+	else
+		execbuf.buffer_count = 3;
+	execbuf.batch_len = len;
+
+	if (ctx)
+		execbuf.rsvd1 = ctx;
+
+	execbuf.flags = I915_EXEC_BLT;
+	if (e)
+		execbuf.flags = e->flags;
+
+	gem_execbuf(fd, &execbuf);
+	gem_sync(fd, cmd);
+
+	return 0;
+}
+
+int xy_block_copy_blt(int fd, uint32_t cmd,
+		      uint32_t *batch_buf,
+		      uint32_t src, uint32_t dst,
+		      uint32_t length, int mode,
+		      struct intel_execution_engine2 *e)
+{
+	return __xy_block_copy_blt(fd, cmd, batch_buf, src,
+			dst, length, mode, 0, e);
+}
+
+int xy_block_copy_blt_ctx(int fd, uint32_t cmd,
+			  uint32_t *batch_buf,
+			  uint32_t src, uint32_t dst,
+			  uint32_t length, int mode, uint32_t ctx)
+{
+	return __xy_block_copy_blt(fd, cmd, batch_buf, src,
+			dst, length, mode, ctx, 0);
+}
+
+/*
+ * make_ctrl_surf_batch:
+ * @fd: open i915 drm file descriptor
+ * @batch_buf: the batch buffer to populate with the command
+ * @src: fd of the source BO
+ * @dst: fd of the destination BO
+ * @length: size of the ctrl surf in bytes
+ * @reloc: pointer to the relocation entyr for this command
+ * @src_mem_access: source memory type (denotes direct or indirect
+ *			addressing)
+ * @dst_mem_acdcess: destination memory type (denotes direct or indirect
+ *			addressing)
+ */
+static int make_ctrl_surf_batch(int fd, uint32_t *batch_buf,
+				uint32_t src, uint32_t dst, uint32_t length,
+				struct drm_i915_gem_relocation_entry *reloc,
+				int src_mem_access, int dst_mem_access)
+{
+	int num_ccs_blocks;
+	uint32_t *b = batch_buf;
+	uint8_t src_mocs = intel_get_uc_mocs(fd);
+	uint8_t dst_mocs = src_mocs;
+
+	num_ccs_blocks = length / CCS_RATIO;
+	if (num_ccs_blocks < 1)
+		num_ccs_blocks = 1;
+	if (num_ccs_blocks > NUM_CCS_BLKS_PER_XFER)
+		return 0;
+
+	/*
+	 * We use logical AND with 1023 since the size field
+	 * takes values which is in the range of 0 - 1023
+	 */
+	b[0] = ((XY_CTRL_SURF_COPY_BLT) |
+		(src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
+		(dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
+		(((num_ccs_blocks - 1) & 1023) << CCS_SIZE_SHIFT));
+
+	b[2] = src_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
+
+	/* relocate address in b[1] and b[2] */
+	reloc->offset = 1 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle = src;
+	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+
+	b[4] = dst_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
+
+	/* relocate address in b[3] and b[4] */
+	reloc->offset = 3 * (sizeof(uint32_t));
+	reloc->delta = 0;
+	reloc->target_handle = dst;
+	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc->write_domain = I915_GEM_DOMAIN_RENDER;
+	reloc->presumed_offset = 0;
+	reloc++;
+
+	b[5] = 0;
+
+	b[6] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
+	reloc->offset = 7 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle =
+	dst_mem_access == INDIRECT_ACCESS ? dst : src;
+	reloc->read_domains = 0;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+	b[9] = 0;
+
+	b[10] = MI_FLUSH_DW | MI_FLUSH_CCS;
+	reloc->offset = 11 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle =
+	dst_mem_access == INDIRECT_ACCESS ? dst : src;
+	reloc->read_domains = 0;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+	b[13] = 0;
+
+	b[14] = MI_BATCH_BUFFER_END;
+	b[15] = 0;
+
+	b += 16;
+
+	return (b - batch_buf) * sizeof(uint32_t);
+}
+
+int xy_ctrl_surf_copy_blt(int fd, uint32_t cmd,
+			  uint32_t *batch_buf,
+			  uint32_t src, uint32_t dst,
+			  uint32_t length, bool writetodev,
+			  struct intel_execution_engine2 *e)
+{
+	struct drm_i915_gem_relocation_entry reloc[4];
+	struct drm_i915_gem_exec_object2 exec[3];
+	struct drm_i915_gem_execbuffer2 execbuf;
+	int len, src_mem_access, dst_mem_access;
+	uint64_t ahnd = get_reloc_ahnd(fd, 0);
+
+	if (writetodev) {
+		src_mem_access = DIRECT_ACCESS;
+		dst_mem_access = INDIRECT_ACCESS;
+	} else {
+		src_mem_access = INDIRECT_ACCESS;
+		dst_mem_access = DIRECT_ACCESS;
+	}
+
+	/* construct batch command buffer */
+	memset(reloc, 0, sizeof(reloc));
+	memset(batch_buf, 0, BATCH_SIZE);
+	len = make_ctrl_surf_batch(fd, batch_buf,
+				   src, dst, length, reloc,
+				   src_mem_access, dst_mem_access);
+	igt_assert(len > 0);
+
+	/* Copy the batch buff to BO cmd */
+	gem_write(fd, cmd, 0, batch_buf, len);
+
+	/* Execute the batch buffer */
+	memset(exec, 0, sizeof(exec));
+	exec[0].handle = src;
+	exec[1].handle = dst;
+	exec[2].handle = cmd;
+	exec[2].relocation_count = !ahnd ? 4 : 0;
+	exec[2].relocs_ptr = to_user_pointer(reloc);
+	if (ahnd) {
+		exec[0].offset = get_offset(ahnd, exec[0].handle, length * CCS_RATIO, 0);
+		exec[0].flags |= EXEC_OBJECT_PINNED;
+		exec[1].offset = get_offset(ahnd, exec[1].handle, length * CCS_RATIO, 0);
+		exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+		exec[2].offset = get_offset(ahnd, exec[2].handle, BATCH_SIZE, 0);
+		exec[2].flags |= EXEC_OBJECT_PINNED;
+	}
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(exec);
+	execbuf.buffer_count = 3;
+	execbuf.batch_len = len;
+	execbuf.flags = I915_EXEC_BLT;
+	if (e)
+		execbuf.flags = e->flags;
+
+	gem_execbuf(fd, &execbuf);
+	gem_sync(fd, cmd);
+
+	return 0;
+}
diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
new file mode 100644
index 00000000..f091c46a
--- /dev/null
+++ b/lib/i915/i915_blt.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *	Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
+ *
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+
+#define MI_FLUSH_DW_LEN_DWORD	4
+#define MI_FLUSH_DW		(0x26 << 23 | 1)
+#define MI_FLUSH_CCS		(1 << 16)
+#define MI_FLUSH_LLC		(1 << 9)
+#define MI_INVALIDATE_TLB	(1 << 18)
+
+/* XY_BLOCK_COPY_BLT instruction has 22 bit groups 1 DWORD each */
+#define XY_BLOCK_COPY_BLT_LEN_DWORD	22
+#define BLOCK_COPY_BLT_CMD		(2 << 29 | 0x41 << 22 | 0x14)
+#define COMPRESSION_ENABLE		(1 << 29)
+#define AUX_CCS_E			(5 << 18)
+#define FULL_RESOLVE			(1 << 12)
+#define PARTIAL_RESOLVE			(2 << 12)
+#define TILE_4_FORMAT			(2 << 30)
+#define TILE_4_WIDTH			(128)
+#define TILE_4_WIDTH_DWORD		((128 >> 2) - 1)
+#define TILE_4_HEIGHT			(32)
+#define SURFACE_TYPE_2D			(1 << 29)
+
+#define DEST_Y2_COORDINATE_SHIFT	(16)
+#define DEST_MEM_TYPE_SHIFT		(31)
+#define SRC_MEM_TYPE_SHIFT		(31)
+#define DEST_SURF_WIDTH_SHIFT		(14)
+#define SRC_SURF_WIDTH_SHIFT		(14)
+
+#define XY_CTRL_SURF_COPY_BLT		(2 << 29 | 0x48 << 22 | 3)
+#define SRC_ACCESS_TYPE_SHIFT		21
+#define DST_ACCESS_TYPE_SHIFT		20
+#define CCS_SIZE_SHIFT			8
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+#define MI_ARB_CHECK			MI_INSTR(0x05, 0)
+#define NUM_CCS_BLKS_PER_XFER		1024
+#define INDIRECT_ACCESS                 0
+#define DIRECT_ACCESS                   1
+
+#define BATCH_SIZE			4096
+#define BOSIZE_MIN			(4 * 1024)
+#define BOSIZE_MAX			(4 * 1024 * 1024)
+#define CCS_RATIO			256
+
+#define MEM_TYPE_SYS			1
+#define MEM_TYPE_LOCAL			0
+
+int xy_block_copy_blt(int fd, uint32_t cmd,
+		      uint32_t *batch_buf,
+		      uint32_t src, uint32_t dst,
+		      uint32_t length, int mode,
+		      struct intel_execution_engine2 *e);
+
+int xy_ctrl_surf_copy_blt(int fd, uint32_t cmd,
+			  uint32_t *batch_buf,
+			  uint32_t src, uint32_t dst,
+			  uint32_t length, bool writetodev,
+			  struct intel_execution_engine2 *e);
+
+int xy_block_copy_blt_ctx(int fd, uint32_t cmd,
+			  uint32_t *batch_buf,
+			  uint32_t src, uint32_t dst,
+			  uint32_t length, int mode, uint32_t ctx);
diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
new file mode 100644
index 00000000..cbb1cc69
--- /dev/null
+++ b/lib/i915/intel_mocs.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright © 2021 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Apoorva Singh <apoorva1.singh@intel.com>
+ *
+ */
+#include "igt.h"
+#include "i915/gem.h"
+#include "intel_mocs.h"
+
+static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
+{
+	uint16_t devid = intel_get_drm_devid(fd);
+
+	/*
+	 * Gen >= 12 onwards don't have a setting for PTE,
+	 * so using I915_MOCS_PTE as mocs index may leads to
+	 * some undefined MOCS behavior.
+	 * Correct MOCS index should be referred from BSPCES
+	 * and programmed accordingly.
+	 * This helper function is providing current UC as well
+	 * as WB MOCS index based on platform.
+
+	 */
+	if (IS_DG1(devid)) {
+		mocs->uc_index = 1;
+		mocs->wb_index = 5;
+	} else if (IS_GEN12(devid)) {
+		mocs->uc_index = 3;
+		mocs->wb_index = 2;
+	} else {
+		mocs->uc_index = I915_MOCS_PTE;
+		mocs->wb_index = I915_MOCS_CACHED;
+	}
+}
+
+/* BitField [6:1] represents index to MOCS Tables
+ * BitField [0] represents Encryption/Decryption
+ */
+
+uint8_t intel_get_wb_mocs(int fd)
+{
+	struct drm_i915_mocs_index mocs;
+
+	get_mocs_index(fd, &mocs);
+	return mocs.wb_index << 1;
+}
+
+uint8_t intel_get_uc_mocs(int fd)
+{
+	struct drm_i915_mocs_index mocs;
+
+	get_mocs_index(fd, &mocs);
+	return mocs.uc_index << 1;
+}
diff --git a/lib/i915/intel_mocs.h b/lib/i915/intel_mocs.h
new file mode 100644
index 00000000..8289ab1f
--- /dev/null
+++ b/lib/i915/intel_mocs.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright © 2021 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Apoorva Singh <apoorva1.singh@intel.com>
+ *
+ */
+#ifndef _INTEL_MOCS_H
+#define _INTEL_MOCS_H
+
+#define XY_FAST_COLOR_BLT_MOCS_SHIFT		21
+#define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
+#define XY_FAST_COPY_BLT_MOCS_SHIFT		17
+#define XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT	25
+#define MEM_COPY_MOCS_SHIFT			25
+
+struct drm_i915_mocs_index {
+	uint8_t uc_index;
+	uint8_t wb_index;
+};
+
+uint8_t intel_get_wb_mocs(int fd);
+uint8_t intel_get_uc_mocs(int fd);
+#endif /* _INTEL_MOCS_H */
diff --git a/lib/meson.build b/lib/meson.build
index 297b0ad2..525d62f9 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -11,6 +11,8 @@ lib_sources = [
 	'i915/gem_mman.c',
 	'i915/gem_vm.c',
 	'i915/intel_memory_region.c',
+	'i915/intel_mocs.c',
+	'i915/i915_blt.c',
 	'igt_collection.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t, v2 1/3] lib/i915: Introduce libraries i915_blt and intel_mocs

[Zbigniew Kempczyński]

On Mon, Nov 22, 2021 at 12:18:47PM +0530, apoorva1.singh@intel.com wrote:
> From: Apoorva Singh <apoorva1.singh@intel.com>
> 
> Add new libraries i915_blt and intel_mocs for various blt
> commands and mocs settings.
> 
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
> ---
>  lib/i915/i915_blt.c   | 419 ++++++++++++++++++++++++++++++++++++++++++
>  lib/i915/i915_blt.h   |  93 ++++++++++
>  lib/i915/intel_mocs.c |  75 ++++++++
>  lib/i915/intel_mocs.h |  43 +++++
>  lib/meson.build       |   2 +
>  5 files changed, 632 insertions(+)
>  create mode 100644 lib/i915/i915_blt.c
>  create mode 100644 lib/i915/i915_blt.h
>  create mode 100644 lib/i915/intel_mocs.c
>  create mode 100644 lib/i915/intel_mocs.h
> 
> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
> new file mode 100644
> index 00000000..a3771f40
> --- /dev/null
> +++ b/lib/i915/i915_blt.c
> @@ -0,0 +1,419 @@
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *	Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> + *
> + */

Use SPDX instead, be aware of difference in comments between header and c file.

> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +#include "i915_blt.h"
> +#include "i915/intel_mocs.h"
> +
> +/*
> + * make_block_copy_batch:
> + * @fd: open i915 drm file descriptor
> + * @batch_buf: the batch buffer to populate with the command
> + * @src: fd of the source BO
> + * @dst: fd of the destination BO
> + * @length: size of the src and dest BOs
> + * @reloc: pointer to the relocation entyr for this command
> + * @src_mem_type: source memory type (denotes direct or indirect
> + *			addressing)
> + * @dst_mem_type: destination memory type (denotes direct or indirect
> + *			addressing)
> + * @src_compression: flag to enable uncompressed read of compressed data
> + *			at the source
> + * @dst_compression: flag to enable compressed write at the destination
> + * @resolve: flag to enable resolve of compressed data

Return value not described.

> + */
> +static int make_block_copy_batch(int fd, uint32_t *batch_buf,
> +				 uint32_t src, uint32_t dst, uint32_t length,
> +				 struct drm_i915_gem_relocation_entry *reloc,
> +				 int src_mem_type, int dst_mem_type,
> +				 int src_compression, int dst_compression,
> +				 int resolve)
> +{
> +	uint32_t *b = batch_buf;
> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
> +	uint8_t dst_mocs = src_mocs;
> +
> +	/* BG 0 */
> +	b[0] = BLOCK_COPY_BLT_CMD | resolve;
> +
> +	/* BG 1
> +	 *
> +	 * Using Tile 4 dimensions.  Height = 32 rows
> +	 * Width = 128 bytes
> +	 */
> +	b[1] = dst_compression | TILE_4_FORMAT | TILE_4_WIDTH_DWORD |
> +		dst_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
> +
> +	/* BG 3
> +	 *
> +	 * X2 = TILE_4_WIDTH
> +	 * Y2 = (length / TILE_4_WIDTH) << 16:
> +	 */
> +	b[3] = TILE_4_WIDTH | (length >> 7) << DEST_Y2_COORDINATE_SHIFT;
> +
> +	/* relocate address in b[4] and b[5] */
> +	reloc->offset = 4 * (sizeof(uint32_t));
> +	reloc->delta = 0;
> +	reloc->target_handle = dst;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = I915_GEM_DOMAIN_RENDER;
> +	reloc->presumed_offset = 0;
> +	reloc++;

This is I don't like, we're filling batch here but offsets for no-reloc
stays zeroed. How the caller can influence on these fields?

> +
> +	/* BG 6 */
> +	b[6] = dst_mem_type << DEST_MEM_TYPE_SHIFT;
> +
> +	/* BG 8 */
> +	b[8] = src_compression | TILE_4_WIDTH_DWORD | TILE_4_FORMAT |
> +		src_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
> +
> +	/* relocate address in b[9] and b[10] */

Same comment as above.

> +	reloc->offset = 9 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = src;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +
> +	/* BG 11 */
> +	b[11] = src_mem_type << SRC_MEM_TYPE_SHIFT;
> +
> +	/* BG 16  */
> +	b[16] = SURFACE_TYPE_2D |
> +		((TILE_4_WIDTH - 1) << DEST_SURF_WIDTH_SHIFT) |
> +		(TILE_4_HEIGHT - 1);
> +
> +	/* BG 19 */
> +	b[19] = SURFACE_TYPE_2D |
> +		((TILE_4_WIDTH - 1) << SRC_SURF_WIDTH_SHIFT) |
> +		(TILE_4_HEIGHT - 1);
> +
> +	b += XY_BLOCK_COPY_BLT_LEN_DWORD;
> +
> +	b[0] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
> +	reloc->offset = 23 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = dst_compression > 0 ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +	b[3] = 0;
> +
> +	b[4] = MI_FLUSH_DW | MI_FLUSH_CCS;
> +	reloc->offset = 27 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = dst_compression > 0 ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +	b[7] = 0;
> +
> +	b[8] = MI_BATCH_BUFFER_END;
> +	b[9] = 0;
> +
> +	b += 10;
> +
> +	return (b - batch_buf) * sizeof(uint32_t);
> +}
> +
> +static int __xy_block_copy_blt(int fd, uint32_t cmd,
> +			       uint32_t *batch_buf,
> +			       uint32_t src, uint32_t dst,
> +			       uint32_t length, int mode, uint32_t ctx,
> +			       struct intel_execution_engine2 *e)
> +{
> +	struct drm_i915_gem_relocation_entry reloc[4];
> +	struct drm_i915_gem_exec_object2 exec[3];
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	int len;
> +	int src_mem_type, dst_mem_type;
> +	int dst_compression, src_compression;
> +	int resolve;
> +	uint64_t ahnd = get_reloc_ahnd(fd, 0);

Allocator should be taken from context ctx, not 0. I think ahnd also
could be argument for this function and we could achieve pipelineing
(couple of consecutive ccs blits without stalls - gem_sync()).

> +
> +	if (mode == 2) { /* in-place decompress */
> +		src_mem_type = MEM_TYPE_LOCAL;
> +		dst_mem_type = MEM_TYPE_LOCAL;
> +		src_compression = COMPRESSION_ENABLE | AUX_CCS_E;
> +		dst_compression = COMPRESSION_ENABLE | AUX_CCS_E;
> +		resolve = FULL_RESOLVE;
> +	} else if (mode == 1) { /* copy from smem to lmem */
> +		src_mem_type = MEM_TYPE_SYS;
> +		dst_mem_type = MEM_TYPE_LOCAL;
> +		src_compression = 0;
> +		dst_compression = COMPRESSION_ENABLE | AUX_CCS_E;
> +		resolve = 0;
> +	} else { /* copy from lmem to smem */
> +		src_mem_type = MEM_TYPE_LOCAL;
> +		dst_mem_type = MEM_TYPE_SYS;
> +		src_compression = COMPRESSION_ENABLE | AUX_CCS_E;
> +		dst_compression = 0;
> +		resolve = 0;
> +	}
> +
> +	/* construct the batch buffer */
> +	memset(reloc, 0, sizeof(reloc));
> +	memset(batch_buf, 0, BATCH_SIZE);
> +	len = make_block_copy_batch(fd, batch_buf,
> +				    src, dst, length, reloc,
> +				    src_mem_type, dst_mem_type,
> +				    src_compression, dst_compression,
> +				    resolve);
> +	igt_assert(len > 0);
> +
> +	/* write batch buffer to 'cmd' BO */
> +	gem_write(fd, cmd, 0, batch_buf, len);
> +
> +	/* Execute the batch buffer */
> +	memset(exec, 0, sizeof(exec));
> +	if (mode == 2) {
> +		exec[0].handle = dst;
> +		exec[1].handle = cmd;
> +		exec[1].relocation_count = !ahnd ? 4 : 0;
> +		exec[1].relocs_ptr = to_user_pointer(reloc);
> +		if (ahnd) {
> +			exec[0].offset = get_offset(ahnd, exec[0].handle, length * CCS_RATIO, 0);
> +			exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> +			exec[1].offset = get_offset(ahnd, exec[1].handle, BATCH_SIZE, 0);
> +			exec[1].flags |= EXEC_OBJECT_PINNED;
> +		}
> +	} else {
> +		exec[0].handle = src;
> +		exec[1].handle = dst;
> +		exec[2].handle = cmd;
> +		exec[2].relocation_count = !ahnd ? 4 : 0;
> +		exec[2].relocs_ptr = to_user_pointer(reloc);
> +		if (ahnd) {
> +			exec[0].offset = get_offset(ahnd, exec[0].handle, length * CCS_RATIO, 0);
> +			exec[0].flags |= EXEC_OBJECT_PINNED;
> +			exec[1].offset = get_offset(ahnd, exec[1].handle, length * CCS_RATIO, 0);
> +			exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> +			exec[2].offset = get_offset(ahnd, exec[2].handle, BATCH_SIZE, 0);
> +			exec[2].flags |= EXEC_OBJECT_PINNED;

Ok, you're preparing and setting offsets but batch still contains 0.
 
> +		}
> +	}
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(exec);
> +	if (mode == 2)
> +		execbuf.buffer_count = 2;
> +	else
> +		execbuf.buffer_count = 3;
> +	execbuf.batch_len = len;
> +
> +	if (ctx)
> +		execbuf.rsvd1 = ctx;
> +
> +	execbuf.flags = I915_EXEC_BLT;
> +	if (e)
> +		execbuf.flags = e->flags;
> +
> +	gem_execbuf(fd, &execbuf);
> +	gem_sync(fd, cmd);

You've opened allocator handle but it was not closed. Also gem_sync()
brokes pipelining here.

> +
> +	return 0;

What for we return any value if it is always is 0?

> +}
> +
> +int xy_block_copy_blt(int fd, uint32_t cmd,
> +		      uint32_t *batch_buf,
> +		      uint32_t src, uint32_t dst,
> +		      uint32_t length, int mode,
> +		      struct intel_execution_engine2 *e)
> +{
> +	return __xy_block_copy_blt(fd, cmd, batch_buf, src,
> +			dst, length, mode, 0, e);
> +}
> +
> +int xy_block_copy_blt_ctx(int fd, uint32_t cmd,
> +			  uint32_t *batch_buf,
> +			  uint32_t src, uint32_t dst,
> +			  uint32_t length, int mode, uint32_t ctx)
> +{
> +	return __xy_block_copy_blt(fd, cmd, batch_buf, src,
> +			dst, length, mode, ctx, 0);
> +}
> +
> +/*
> + * make_ctrl_surf_batch:
> + * @fd: open i915 drm file descriptor
> + * @batch_buf: the batch buffer to populate with the command
> + * @src: fd of the source BO
> + * @dst: fd of the destination BO
> + * @length: size of the ctrl surf in bytes
> + * @reloc: pointer to the relocation entyr for this command
> + * @src_mem_access: source memory type (denotes direct or indirect
> + *			addressing)
> + * @dst_mem_acdcess: destination memory type (denotes direct or indirect
> + *			addressing)
> + */
> +static int make_ctrl_surf_batch(int fd, uint32_t *batch_buf,
> +				uint32_t src, uint32_t dst, uint32_t length,
> +				struct drm_i915_gem_relocation_entry *reloc,
> +				int src_mem_access, int dst_mem_access)
> +{
> +	int num_ccs_blocks;
> +	uint32_t *b = batch_buf;
> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
> +	uint8_t dst_mocs = src_mocs;
> +
> +	num_ccs_blocks = length / CCS_RATIO;
> +	if (num_ccs_blocks < 1)
> +		num_ccs_blocks = 1;
> +	if (num_ccs_blocks > NUM_CCS_BLKS_PER_XFER)
> +		return 0;
> +
> +	/*
> +	 * We use logical AND with 1023 since the size field
> +	 * takes values which is in the range of 0 - 1023
> +	 */
> +	b[0] = ((XY_CTRL_SURF_COPY_BLT) |
> +		(src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
> +		(dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
> +		(((num_ccs_blocks - 1) & 1023) << CCS_SIZE_SHIFT));
> +
> +	b[2] = src_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
> +
> +	/* relocate address in b[1] and b[2] */

All regarding addresses from above functions apply here.

> +	reloc->offset = 1 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = src;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +
> +	b[4] = dst_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
> +
> +	/* relocate address in b[3] and b[4] */
> +	reloc->offset = 3 * (sizeof(uint32_t));
> +	reloc->delta = 0;
> +	reloc->target_handle = dst;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = I915_GEM_DOMAIN_RENDER;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +
> +	b[5] = 0;
> +
> +	b[6] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
> +	reloc->offset = 7 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle =
> +	dst_mem_access == INDIRECT_ACCESS ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +	b[9] = 0;
> +
> +	b[10] = MI_FLUSH_DW | MI_FLUSH_CCS;
> +	reloc->offset = 11 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle =
> +	dst_mem_access == INDIRECT_ACCESS ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +	b[13] = 0;
> +
> +	b[14] = MI_BATCH_BUFFER_END;
> +	b[15] = 0;
> +
> +	b += 16;
> +
> +	return (b - batch_buf) * sizeof(uint32_t);
> +}
> +
> +int xy_ctrl_surf_copy_blt(int fd, uint32_t cmd,
> +			  uint32_t *batch_buf,
> +			  uint32_t src, uint32_t dst,
> +			  uint32_t length, bool writetodev,
> +			  struct intel_execution_engine2 *e)

Why we don't support ctx here?

> +{
> +	struct drm_i915_gem_relocation_entry reloc[4];
> +	struct drm_i915_gem_exec_object2 exec[3];
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	int len, src_mem_access, dst_mem_access;
> +	uint64_t ahnd = get_reloc_ahnd(fd, 0);
> +
> +	if (writetodev) {
> +		src_mem_access = DIRECT_ACCESS;
> +		dst_mem_access = INDIRECT_ACCESS;
> +	} else {
> +		src_mem_access = INDIRECT_ACCESS;
> +		dst_mem_access = DIRECT_ACCESS;
> +	}
> +
> +	/* construct batch command buffer */
> +	memset(reloc, 0, sizeof(reloc));
> +	memset(batch_buf, 0, BATCH_SIZE);
> +	len = make_ctrl_surf_batch(fd, batch_buf,
> +				   src, dst, length, reloc,
> +				   src_mem_access, dst_mem_access);
> +	igt_assert(len > 0);
> +
> +	/* Copy the batch buff to BO cmd */
> +	gem_write(fd, cmd, 0, batch_buf, len);
> +
> +	/* Execute the batch buffer */
> +	memset(exec, 0, sizeof(exec));
> +	exec[0].handle = src;
> +	exec[1].handle = dst;
> +	exec[2].handle = cmd;
> +	exec[2].relocation_count = !ahnd ? 4 : 0;
> +	exec[2].relocs_ptr = to_user_pointer(reloc);
> +	if (ahnd) {
> +		exec[0].offset = get_offset(ahnd, exec[0].handle, length * CCS_RATIO, 0);
> +		exec[0].flags |= EXEC_OBJECT_PINNED;
> +		exec[1].offset = get_offset(ahnd, exec[1].handle, length * CCS_RATIO, 0);
> +		exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> +		exec[2].offset = get_offset(ahnd, exec[2].handle, BATCH_SIZE, 0);
> +		exec[2].flags |= EXEC_OBJECT_PINNED;
> +	}
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(exec);
> +	execbuf.buffer_count = 3;
> +	execbuf.batch_len = len;
> +	execbuf.flags = I915_EXEC_BLT;
> +	if (e)
> +		execbuf.flags = e->flags;
> +
> +	gem_execbuf(fd, &execbuf);
> +	gem_sync(fd, cmd);
> +
> +	return 0;

All commands regarding offset within batch and return value applies here.

> +}
> diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
> new file mode 100644
> index 00000000..f091c46a
> --- /dev/null
> +++ b/lib/i915/i915_blt.h
> @@ -0,0 +1,93 @@
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *	Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> + *
> + */

Use SPDX.

> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +
> +#define MI_FLUSH_DW_LEN_DWORD	4
> +#define MI_FLUSH_DW		(0x26 << 23 | 1)
> +#define MI_FLUSH_CCS		(1 << 16)
> +#define MI_FLUSH_LLC		(1 << 9)
> +#define MI_INVALIDATE_TLB	(1 << 18)
> +
> +/* XY_BLOCK_COPY_BLT instruction has 22 bit groups 1 DWORD each */
> +#define XY_BLOCK_COPY_BLT_LEN_DWORD	22
> +#define BLOCK_COPY_BLT_CMD		(2 << 29 | 0x41 << 22 | 0x14)
> +#define COMPRESSION_ENABLE		(1 << 29)
> +#define AUX_CCS_E			(5 << 18)
> +#define FULL_RESOLVE			(1 << 12)
> +#define PARTIAL_RESOLVE			(2 << 12)
> +#define TILE_4_FORMAT			(2 << 30)
> +#define TILE_4_WIDTH			(128)
> +#define TILE_4_WIDTH_DWORD		((128 >> 2) - 1)
> +#define TILE_4_HEIGHT			(32)
> +#define SURFACE_TYPE_2D			(1 << 29)
> +
> +#define DEST_Y2_COORDINATE_SHIFT	(16)
> +#define DEST_MEM_TYPE_SHIFT		(31)
> +#define SRC_MEM_TYPE_SHIFT		(31)
> +#define DEST_SURF_WIDTH_SHIFT		(14)
> +#define SRC_SURF_WIDTH_SHIFT		(14)
> +
> +#define XY_CTRL_SURF_COPY_BLT		(2 << 29 | 0x48 << 22 | 3)
> +#define SRC_ACCESS_TYPE_SHIFT		21
> +#define DST_ACCESS_TYPE_SHIFT		20
> +#define CCS_SIZE_SHIFT			8
> +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> +#define MI_ARB_CHECK			MI_INSTR(0x05, 0)
> +#define NUM_CCS_BLKS_PER_XFER		1024
> +#define INDIRECT_ACCESS                 0
> +#define DIRECT_ACCESS                   1
> +
> +#define BATCH_SIZE			4096
> +#define BOSIZE_MIN			(4 * 1024)
> +#define BOSIZE_MAX			(4 * 1024 * 1024)
> +#define CCS_RATIO			256
> +
> +#define MEM_TYPE_SYS			1
> +#define MEM_TYPE_LOCAL			0
> +
> +int xy_block_copy_blt(int fd, uint32_t cmd,
> +		      uint32_t *batch_buf,
> +		      uint32_t src, uint32_t dst,
> +		      uint32_t length, int mode,
> +		      struct intel_execution_engine2 *e);
> +
> +int xy_ctrl_surf_copy_blt(int fd, uint32_t cmd,
> +			  uint32_t *batch_buf,
> +			  uint32_t src, uint32_t dst,
> +			  uint32_t length, bool writetodev,
> +			  struct intel_execution_engine2 *e);

xy_block_copy_blt has corresponding _ctx version, maybe xy_ctrl_surf_copy_blt
should also have?

> +
> +int xy_block_copy_blt_ctx(int fd, uint32_t cmd,
> +			  uint32_t *batch_buf,
> +			  uint32_t src, uint32_t dst,
> +			  uint32_t length, int mode, uint32_t ctx);
> diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
> new file mode 100644
> index 00000000..cbb1cc69
> --- /dev/null
> +++ b/lib/i915/intel_mocs.c
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright © 2021 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *      Apoorva Singh <apoorva1.singh@intel.com>
> + *
> + */

Use SPDX.


> +#include "igt.h"
> +#include "i915/gem.h"
> +#include "intel_mocs.h"
> +
> +static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
> +{
> +	uint16_t devid = intel_get_drm_devid(fd);
> +
> +	/*
> +	 * Gen >= 12 onwards don't have a setting for PTE,
> +	 * so using I915_MOCS_PTE as mocs index may leads to
> +	 * some undefined MOCS behavior.
> +	 * Correct MOCS index should be referred from BSPCES
> +	 * and programmed accordingly.
> +	 * This helper function is providing current UC as well
> +	 * as WB MOCS index based on platform.
> +
> +	 */
> +	if (IS_DG1(devid)) {
> +		mocs->uc_index = 1;
> +		mocs->wb_index = 5;
> +	} else if (IS_GEN12(devid)) {
> +		mocs->uc_index = 3;
> +		mocs->wb_index = 2;
> +	} else {
> +		mocs->uc_index = I915_MOCS_PTE;
> +		mocs->wb_index = I915_MOCS_CACHED;
> +	}
> +}
> +
> +/* BitField [6:1] represents index to MOCS Tables
> + * BitField [0] represents Encryption/Decryption
> + */
> +
> +uint8_t intel_get_wb_mocs(int fd)
> +{
> +	struct drm_i915_mocs_index mocs;
> +
> +	get_mocs_index(fd, &mocs);
> +	return mocs.wb_index << 1;
> +}
> +
> +uint8_t intel_get_uc_mocs(int fd)
> +{
> +	struct drm_i915_mocs_index mocs;
> +
> +	get_mocs_index(fd, &mocs);
> +	return mocs.uc_index << 1;
> +}
> diff --git a/lib/i915/intel_mocs.h b/lib/i915/intel_mocs.h
> new file mode 100644
> index 00000000..8289ab1f
> --- /dev/null
> +++ b/lib/i915/intel_mocs.h
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright © 2021 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *      Apoorva Singh <apoorva1.singh@intel.com>
> + *
> + */

Use SPDX.

--
Zbigniew

> +#ifndef _INTEL_MOCS_H
> +#define _INTEL_MOCS_H
> +
> +#define XY_FAST_COLOR_BLT_MOCS_SHIFT		21
> +#define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
> +#define XY_FAST_COPY_BLT_MOCS_SHIFT		17
> +#define XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT	25
> +#define MEM_COPY_MOCS_SHIFT			25
> +
> +struct drm_i915_mocs_index {
> +	uint8_t uc_index;
> +	uint8_t wb_index;
> +};
> +
> +uint8_t intel_get_wb_mocs(int fd);
> +uint8_t intel_get_uc_mocs(int fd);
> +#endif /* _INTEL_MOCS_H */
> diff --git a/lib/meson.build b/lib/meson.build
> index 297b0ad2..525d62f9 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -11,6 +11,8 @@ lib_sources = [
>  	'i915/gem_mman.c',
>  	'i915/gem_vm.c',
>  	'i915/intel_memory_region.c',
> +	'i915/intel_mocs.c',
> +	'i915/i915_blt.c',
>  	'igt_collection.c',
>  	'igt_color_encoding.c',
>  	'igt_debugfs.c',
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH i-g-t, v2 1/3] lib/i915: Introduce libraries i915_blt and intel_mocs

[Zbigniew Kempczyński]

On Mon, Nov 22, 2021 at 12:18:47PM +0530, apoorva1.singh@intel.com wrote:

<cut>

I've also wondered - should be the code below part of separate patch?

--
Zbigniew

> diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
> new file mode 100644
> index 00000000..cbb1cc69
> --- /dev/null
> +++ b/lib/i915/intel_mocs.c
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright © 2021 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *      Apoorva Singh <apoorva1.singh@intel.com>
> + *
> + */
> +#include "igt.h"
> +#include "i915/gem.h"
> +#include "intel_mocs.h"
> +
> +static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
> +{
> +	uint16_t devid = intel_get_drm_devid(fd);
> +
> +	/*
> +	 * Gen >= 12 onwards don't have a setting for PTE,
> +	 * so using I915_MOCS_PTE as mocs index may leads to
> +	 * some undefined MOCS behavior.
> +	 * Correct MOCS index should be referred from BSPCES
> +	 * and programmed accordingly.
> +	 * This helper function is providing current UC as well
> +	 * as WB MOCS index based on platform.
> +
> +	 */
> +	if (IS_DG1(devid)) {
> +		mocs->uc_index = 1;
> +		mocs->wb_index = 5;
> +	} else if (IS_GEN12(devid)) {
> +		mocs->uc_index = 3;
> +		mocs->wb_index = 2;
> +	} else {
> +		mocs->uc_index = I915_MOCS_PTE;
> +		mocs->wb_index = I915_MOCS_CACHED;
> +	}
> +}
> +
> +/* BitField [6:1] represents index to MOCS Tables
> + * BitField [0] represents Encryption/Decryption
> + */
> +
> +uint8_t intel_get_wb_mocs(int fd)
> +{
> +	struct drm_i915_mocs_index mocs;
> +
> +	get_mocs_index(fd, &mocs);
> +	return mocs.wb_index << 1;
> +}
> +
> +uint8_t intel_get_uc_mocs(int fd)
> +{
> +	struct drm_i915_mocs_index mocs;
> +
> +	get_mocs_index(fd, &mocs);
> +	return mocs.uc_index << 1;
> +}
> diff --git a/lib/i915/intel_mocs.h b/lib/i915/intel_mocs.h
> new file mode 100644
> index 00000000..8289ab1f
> --- /dev/null
> +++ b/lib/i915/intel_mocs.h
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright © 2021 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *      Apoorva Singh <apoorva1.singh@intel.com>
> + *
> + */
> +#ifndef _INTEL_MOCS_H
> +#define _INTEL_MOCS_H
> +
> +#define XY_FAST_COLOR_BLT_MOCS_SHIFT		21
> +#define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
> +#define XY_FAST_COPY_BLT_MOCS_SHIFT		17
> +#define XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT	25
> +#define MEM_COPY_MOCS_SHIFT			25
> +
> +struct drm_i915_mocs_index {
> +	uint8_t uc_index;
> +	uint8_t wb_index;
> +};
> +
> +uint8_t intel_get_wb_mocs(int fd);
> +uint8_t intel_get_uc_mocs(int fd);
> +#endif /* _INTEL_MOCS_H */
> diff --git a/lib/meson.build b/lib/meson.build
> index 297b0ad2..525d62f9 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -11,6 +11,8 @@ lib_sources = [
>  	'i915/gem_mman.c',
>  	'i915/gem_vm.c',
>  	'i915/intel_memory_region.c',
> +	'i915/intel_mocs.c',
> +	'i915/i915_blt.c',
>  	'igt_collection.c',
>  	'igt_color_encoding.c',
>  	'igt_debugfs.c',
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH i-g-t, v2 1/3] lib/i915: Introduce libraries i915_blt and intel_mocs

[Zbigniew Kempczyński]

On Mon, Nov 22, 2021 at 12:18:47PM +0530, apoorva1.singh@intel.com wrote:

<cut>

> +/*
> + * make_ctrl_surf_batch:
> + * @fd: open i915 drm file descriptor
> + * @batch_buf: the batch buffer to populate with the command
> + * @src: fd of the source BO
> + * @dst: fd of the destination BO
> + * @length: size of the ctrl surf in bytes
> + * @reloc: pointer to the relocation entyr for this command
> + * @src_mem_access: source memory type (denotes direct or indirect
> + *			addressing)
> + * @dst_mem_acdcess: destination memory type (denotes direct or indirect
> + *			addressing)
> + */
> +static int make_ctrl_surf_batch(int fd, uint32_t *batch_buf,
> +				uint32_t src, uint32_t dst, uint32_t length,
> +				struct drm_i915_gem_relocation_entry *reloc,
> +				int src_mem_access, int dst_mem_access)
> +{
> +	int num_ccs_blocks;
> +	uint32_t *b = batch_buf;
> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
> +	uint8_t dst_mocs = src_mocs;
> +
> +	num_ccs_blocks = length / CCS_RATIO;
> +	if (num_ccs_blocks < 1)
> +		num_ccs_blocks = 1;
> +	if (num_ccs_blocks > NUM_CCS_BLKS_PER_XFER)
> +		return 0;
> +
> +	/*
> +	 * We use logical AND with 1023 since the size field
> +	 * takes values which is in the range of 0 - 1023
> +	 */
> +	b[0] = ((XY_CTRL_SURF_COPY_BLT) |

I've just realized myself this command is not available for gens where
relocations are enabled so all reloc stuff below can be removed.

--
Zbigniew

> +		(src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
> +		(dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
> +		(((num_ccs_blocks - 1) & 1023) << CCS_SIZE_SHIFT));
> +
 

Re: [igt-dev] [PATCH i-g-t, v2 1/3] lib/i915: Introduce libraries i915_blt and intel_mocs

[Zbigniew Kempczyński]

On Mon, Nov 22, 2021 at 12:18:47PM +0530, apoorva1.singh@intel.com wrote:

<cut>

> +int xy_ctrl_surf_copy_blt(int fd, uint32_t cmd,
> +			  uint32_t *batch_buf,
> +			  uint32_t src, uint32_t dst,
> +			  uint32_t length, bool writetodev,
> +			  struct intel_execution_engine2 *e)

If we pass engine likely it won't be in default context, so it necessary
to pass ctx here.

What I don't like here is to pass cmd and batch_buf here. If you want to
reuse cmd in the caller you need to synchronize on this handle so you
won't achieve pipelining.

> +{
> +	struct drm_i915_gem_relocation_entry reloc[4];
> +	struct drm_i915_gem_exec_object2 exec[3];
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	int len, src_mem_access, dst_mem_access;
> +	uint64_t ahnd = get_reloc_ahnd(fd, 0);

This is a little bit tricky, if caller will create different allocator on 
same context we would get assert. Better way is to pass ahnd from the caller
and do get_offset/put_offset using strategy it choose.

> +
> +	if (writetodev) {
> +		src_mem_access = DIRECT_ACCESS;
> +		dst_mem_access = INDIRECT_ACCESS;
> +	} else {
> +		src_mem_access = INDIRECT_ACCESS;
> +		dst_mem_access = DIRECT_ACCESS;
> +	}
> +
> +	/* construct batch command buffer */
> +	memset(reloc, 0, sizeof(reloc));
> +	memset(batch_buf, 0, BATCH_SIZE);

So we assume batch_buf at least is BATCH_SIZE length, it will be bigger
we will survive, if smaller heap corruption will occur. I can only guess
cmd is created outside to allow creating it in any memory region.

> +	len = make_ctrl_surf_batch(fd, batch_buf,
> +				   src, dst, length, reloc,
> +				   src_mem_access, dst_mem_access);
> +	igt_assert(len > 0);
> +
> +	/* Copy the batch buff to BO cmd */
> +	gem_write(fd, cmd, 0, batch_buf, len);
> +
> +	/* Execute the batch buffer */
> +	memset(exec, 0, sizeof(exec));
> +	exec[0].handle = src;
> +	exec[1].handle = dst;
> +	exec[2].handle = cmd;
> +	exec[2].relocation_count = !ahnd ? 4 : 0;
> +	exec[2].relocs_ptr = to_user_pointer(reloc);
> +	if (ahnd) {
> +		exec[0].offset = get_offset(ahnd, exec[0].handle, length * CCS_RATIO, 0);
> +		exec[0].flags |= EXEC_OBJECT_PINNED;
> +		exec[1].offset = get_offset(ahnd, exec[1].handle, length * CCS_RATIO, 0);
> +		exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> +		exec[2].offset = get_offset(ahnd, exec[2].handle, BATCH_SIZE, 0);
> +		exec[2].flags |= EXEC_OBJECT_PINNED;
> +	}
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(exec);
> +	execbuf.buffer_count = 3;
> +	execbuf.batch_len = len;
> +	execbuf.flags = I915_EXEC_BLT;
> +	if (e)
> +		execbuf.flags = e->flags;
> +
> +	gem_execbuf(fd, &execbuf);
> +	gem_sync(fd, cmd);
> +
> +	return 0;
> +}

I'm sorry for couple of email regarding same code, but I catched wider
context in third patch (gem_ccs test).

--
Zbigniew 

[igt-dev] [PATCH i-g-t, v2 2/3] lib/intel_chipset.h: Add has_flat_ccs flag

[apoorva1.singh]

From: Apoorva Singh <apoorva1.singh@intel.com>

Add a new platform flag, has_flat_ccs, for platforms
supporting Flat CCS.

Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
---
 lib/intel_chipset.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 2b795527..d2719932 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -40,6 +40,7 @@ struct intel_device_info {
 	unsigned graphics_ver;
 	unsigned display_ver;
 	unsigned gt; /* 0 if unknown */
+	bool has_flat_ccs : 1;
 	bool is_mobile : 1;
 	bool is_whitney : 1;
 	bool is_almador : 1;
@@ -209,4 +210,6 @@ void intel_check_pch(void);
 				   IS_CHERRYVIEW(devid) || \
 				   IS_BROXTON(devid)))
 
+#define HAS_FLAT_CCS(devid)	(intel_get_device_info(devid)->has_flat_ccs)
+
 #endif /* _INTEL_CHIPSET_H */
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t, v2 2/3] lib/intel_chipset.h: Add has_flat_ccs flag

[Zbigniew Kempczyński]

On Mon, Nov 22, 2021 at 12:18:48PM +0530, apoorva1.singh@intel.com wrote:
> From: Apoorva Singh <apoorva1.singh@intel.com>
> 
> Add a new platform flag, has_flat_ccs, for platforms
> supporting Flat CCS.
> 
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
> ---
>  lib/intel_chipset.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> index 2b795527..d2719932 100644
> --- a/lib/intel_chipset.h
> +++ b/lib/intel_chipset.h
> @@ -40,6 +40,7 @@ struct intel_device_info {
>  	unsigned graphics_ver;
>  	unsigned display_ver;
>  	unsigned gt; /* 0 if unknown */
> +	bool has_flat_ccs : 1;
>  	bool is_mobile : 1;
>  	bool is_whitney : 1;
>  	bool is_almador : 1;
> @@ -209,4 +210,6 @@ void intel_check_pch(void);
>  				   IS_CHERRYVIEW(devid) || \
>  				   IS_BROXTON(devid)))
>  
> +#define HAS_FLAT_CCS(devid)	(intel_get_device_info(devid)->has_flat_ccs)
> +

This will require explicit define line for newer gens - I got nothing
against it (I see no better solution right now). I've not found dg2
definition so above series is a little bit dead code now and we got
no possibility to test it on CI. Anyway:

Acked-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew 

>  #endif /* _INTEL_CHIPSET_H */
> -- 
> 2.25.1
> 

[igt-dev] [PATCH i-g-t,v2 3/3] i915/gem_ccs: Add testing for CCS

[apoorva1.singh]

From: CQ Tang <cq.tang@intel.com>

Add gem_ccs test for CCS testing.
Commands are constructed with XY_BLOCK_COPY_BLT
and XY_CTRL_SURF_COPY_BLT instructions.

Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
---
 lib/i915/gem_engine_topology.c |  38 ++
 lib/i915/gem_engine_topology.h |   5 +
 tests/i915/gem_ccs.c           | 640 +++++++++++++++++++++++++++++++++
 tests/meson.build              |   1 +
 4 files changed, 684 insertions(+)
 create mode 100644 tests/i915/gem_ccs.c

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 729f42b0..37b5875e 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -488,6 +488,44 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
 	return ret;
 }
 
+static bool
+__gem_engine_has_capability(int i915, const char *engine,
+			    const char *attr, const char *cap)
+{
+	char buf[4096] = {};
+	FILE *file;
+
+	file = __open_attr(igt_sysfs_open(i915), "r",
+			   "engine", engine, attr, NULL);
+	if (file) {
+		fread(buf, 1, sizeof(buf) - 1, file);
+		fclose(file);
+	}
+
+	return strstr(buf, cap);
+}
+
+bool gem_engine_has_capability(int i915, const char *engine, const char *cap)
+{
+	return __gem_engine_has_capability(i915, engine, "capabilities", cap);
+}
+
+bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap)
+{
+	return __gem_engine_has_capability(i915, engine, "known_capabilities", cap);
+}
+
+bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine)
+{
+	if (engine->class != I915_ENGINE_CLASS_COPY)
+		return false;
+
+	if (!gem_engine_has_known_capability(i915, engine->name, "block_copy"))
+		return intel_gen(intel_get_drm_devid(i915)) >= 12;
+
+	return gem_engine_has_capability(i915, engine->name, "block_copy");
+}
+
 uint32_t gem_engine_mmio_base(int i915, const char *engine)
 {
 	unsigned int mmio = 0;
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 4cfab560..d24bc9e8 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -124,6 +124,11 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
 
 uint32_t gem_engine_mmio_base(int i915, const char *engine);
 
+bool gem_engine_has_capability(int i915, const char *engine, const char *cap);
+bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap);
+
+bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine);
+
 void dyn_sysfs_engines(int i915, int engines, const char *file,
 		       void (*test)(int i915, int engine));
 
diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
new file mode 100644
index 00000000..e4dc9139
--- /dev/null
+++ b/tests/i915/gem_ccs.c
@@ -0,0 +1,640 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *	CQ Tang <cq.tang@intel.com>
+ *	Neel Desai <neel.desai@intel.com>
+ *
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+#include "i915/gem.h"
+#include "i915/gem_create.h"
+#include "lib/intel_chipset.h"
+#include "i915/i915_blt.h"
+
+IGT_TEST_DESCRIPTION("Exercise the memory bandwidth compression and "
+		     "decompression when copying data between "
+		     "system and local memory");
+
+static void igt_wr_xy_ctrl_surf_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
+					 uint32_t src, uint32_t dst, uint32_t out,
+					 int ccssize, uint8_t *pattern_buf,
+					 uint8_t *read_buf, int bosize,
+					 struct intel_execution_engine2 *e)
+{
+	int ret, i;
+
+	/* set 'src' to random pattern */
+	gem_write(fd, src, 0, pattern_buf, bosize);
+
+	/*
+	 * 'dst' is lmem BO with ccs, directly
+	 * copy content in 'src' BO to 'dst' BO's ccs
+	 */
+	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+				    src, dst, ccssize, true, e);
+
+	igt_assert(!ret);
+
+	/* clear out BO */
+	memset(read_buf, 0, ccssize);
+	gem_write(fd, out, 0, read_buf, ccssize);
+
+	/* copy 'dst' BO's ccs into 'out' BO */
+	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+				    dst, out, ccssize, false, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	gem_read(fd, out, 0, read_buf, ccssize);
+	/*
+	 * check 'read_buf',
+	 * it should have original pattern
+	 */
+	for (i = 0; i < ccssize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(!ret);
+}
+
+static void igt_overwritten_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
+					      uint32_t src, uint32_t dst, uint32_t out,
+					      int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
+					      int bosize, struct intel_execution_engine2 *e)
+{
+	int ret, i;
+
+	/************************************************/
+	/* #2 CCS is overwritten by XY_BLOCK_COPY_BLT   */
+	/************************************************/
+	igt_info("copy random pattern to lmem BO with compression\n");
+
+	/* set 'src' to random pattern */
+	gem_write(fd, src, 0, pattern_buf, bosize);
+	/* set 'dst' to random pattern */
+	gem_write(fd, dst, 0, pattern_buf, bosize);
+
+	/*
+	 * 'dst' is lmem BO with ccs,
+	 * copy content in 'src' BO to 'dst' BO
+	 */
+	ret = xy_block_copy_blt(fd, cmd, batch_buf,
+				src, dst, bosize, 1, e);
+	igt_assert(!ret);
+
+	/* clear out BO */
+	memset(read_buf, 0, ccssize);
+	gem_write(fd, out, 0, read_buf, ccssize);
+
+	/* copy 'dst' BO's ccs into 'out' BO */
+	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+				    dst, out, ccssize, false, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	gem_read(fd, out, 0, read_buf, ccssize);
+
+	/*
+	 * check 'read_buf',
+	 * it should NOT have original pattern
+	 * (overwrite by XY_BLOCK_COPY_BLT)
+	 */
+	for (i = 0; i < ccssize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(ret);
+
+	/* read 'dst' BO into read_buf */
+	memset(read_buf, 0, bosize);
+	gem_read(fd, dst, 0, read_buf, bosize);
+
+	/*
+	 * check 'read_buf',
+	 * it should not have original pattern
+	 */
+	for (i = 0; i < bosize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(ret);
+
+	/* clear out BO */
+	memset(read_buf, 0, bosize);
+	gem_write(fd, out, 0, read_buf, bosize);
+
+	/* copy 'dst' BO into 'out' BO */
+	ret = xy_block_copy_blt(fd, cmd, batch_buf,
+				dst, out, bosize, 0, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	gem_read(fd, out, 0, read_buf, bosize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have original pattern
+	 */
+	for (i = 0; i < bosize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(!ret);
+
+	/* decompress 'dst' in place */
+	ret = xy_block_copy_blt(fd, cmd, batch_buf,
+				dst, dst, bosize, 2, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	memset(read_buf, 0, bosize);
+	gem_read(fd, dst, 0, read_buf, bosize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have original pattern
+	 */
+	for (i = 0; i < bosize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(!ret);
+
+	/* clear out BO */
+	memset(read_buf, 0, bosize);
+	gem_write(fd, out, 0, read_buf, bosize);
+
+	/* copy decompressed 'dst' to 'out' */
+	ret = xy_block_copy_blt(fd, cmd, batch_buf,
+				dst, out, bosize, 0, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	gem_read(fd, out, 0, read_buf, bosize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have original pattern
+	 */
+	for (i = 0; i < bosize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+
+	igt_assert(!ret);
+}
+
+static void igt_corrupted_xy_ctrl_surf_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
+						uint32_t src, uint32_t dst, uint32_t out,
+						int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
+						int bosize, struct intel_execution_engine2 *e)
+{
+	int ret, i;
+
+	/* set 'src' to random pattern */
+	gem_write(fd, src, 0, pattern_buf, bosize);
+
+	/************************************************/
+	/* #3 CCS is corrupted by XY_CTRL_SURF_COPY_BLT */
+	/************************************************/
+	igt_info("corrupt CCS via XY_CTRL_SURF_COPY_BLT\n");
+
+	/*
+	 * corrupt 'dst' BO's ccs by writing directly
+	 */
+	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+				    src, dst, ccssize, true, e);
+	igt_assert(!ret);
+
+	/* clear out BO */
+	memset(read_buf, 0, bosize);
+	gem_write(fd, out, 0, read_buf, bosize);
+
+	/* copy 'dst' BO into 'out' BO */
+	ret = xy_block_copy_blt(fd, cmd, batch_buf,
+				dst, out, bosize, 0, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	gem_read(fd, out, 0, read_buf, bosize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have corrupted pattern
+	 */
+	for (i = 0; i < bosize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(ret);
+
+	/* clear out BO */
+	memset(read_buf, 0, ccssize);
+	gem_write(fd, out, 0, read_buf, ccssize);
+
+	/* copy 'dst' BO's ccs into 'out' BO */
+	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+				    dst, out, ccssize, false, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	gem_read(fd, out, 0, read_buf, ccssize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have original pattern
+	 */
+	for (i = 0; i < ccssize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(!ret);
+}
+
+static void igt_copy_zero_pattern_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
+						    uint32_t src, uint32_t dst, uint32_t out,
+						    int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
+						    uint8_t *input_buf, int bosize,
+						    struct intel_execution_engine2 *e)
+{
+	int ret, i;
+
+	/************************************************/
+	/* #4 Copy zeros pattern with XY_BLOCK_COPY_BLT */
+	/************************************************/
+	igt_info("copy zeros pattern to lmem BO with compression\n");
+
+	/* set src BO to random pattern */
+	gem_write(fd, src, 0, pattern_buf, bosize);
+	/* set dst BO to random pattern */
+	gem_write(fd, dst, 0, pattern_buf, bosize);
+	/* set ccs to random pattern */
+	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+				    src, dst, ccssize, true, e);
+	igt_assert(!ret);
+
+	/* clear 'src' BO */
+	memset(input_buf, 0, bosize);
+	gem_write(fd, src, 0, input_buf, bosize);
+
+	/* copy 'src' to 'dst' with compression */
+	ret = xy_block_copy_blt(fd, cmd, batch_buf,
+				src, dst, bosize, 1, e);
+	igt_assert(!ret);
+
+	/* set out BO to random pattern */
+	gem_write(fd, out, 0, pattern_buf, bosize);
+
+	/* copy 'dst' BO back into 'out' BO */
+	ret = xy_block_copy_blt(fd, cmd, batch_buf,
+				dst, out, bosize, 0, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	gem_read(fd, out, 0, read_buf, bosize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have same zero pattern
+	 */
+	for (i = 0; i < bosize; i++) {
+		if (read_buf[i] != input_buf[i])
+			ret++;
+	}
+	igt_assert(!ret);
+
+	/* clear read_buf */
+	memset(read_buf, 0, bosize);
+	/* read 'dst' BO into read_buf */
+	gem_read(fd, dst, 0, read_buf, bosize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have the same pattern
+	 * as zero pattern compression won't change
+	 * target pages, only change ccs.
+	 */
+	for (i = 0; i < bosize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(!ret);
+
+	/* clear out BO */
+	memset(read_buf, 0, ccssize);
+	gem_write(fd, out, 0, read_buf, ccssize);
+
+	/* copy 'dst' BO's ccs into 'out' BO */
+	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+				    dst, out, ccssize, false, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	gem_read(fd, out, 0, read_buf, ccssize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have different pattern
+	 */
+	for (i = 0; i < ccssize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(ret);
+}
+
+static void igt_copy_repeat_pattern_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
+						      uint32_t src, uint32_t dst, uint32_t out,
+						      int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
+						      uint8_t *input_buf, int bosize,
+						      struct intel_execution_engine2 *e)
+{
+	int ret, i;
+
+	/************************************************/
+	/* #5 Copy repeat pattern with XY_BLOCK_COPY_BLT*/
+	/************************************************/
+	igt_info("copy repeat pattern to lmem BO with compression\n");
+
+	/* Set 'src' to random pattern */
+	gem_write(fd, src, 0, pattern_buf, bosize);
+	/* Set 'dst' and 'ccs' to random pattern */
+	gem_write(fd, src, 0, pattern_buf, ccssize);
+	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+				    src, dst, ccssize, true, e);
+	igt_assert(!ret);
+	gem_write(fd, dst, 0, pattern_buf, bosize);
+
+	/* generate repeating pattern */
+	input_buf[0] = (uint8_t)rand();
+	input_buf[1] = (uint8_t)rand();
+	input_buf[2] = (uint8_t)rand();
+	input_buf[3] = (uint8_t)rand();
+	for (i = 4; i < bosize; i++)
+		input_buf[i] = input_buf[i - 4];
+	gem_write(fd, src, 0, input_buf, bosize);
+	ret = xy_block_copy_blt(fd, cmd, batch_buf,
+				src, dst, bosize, 1, e);
+	igt_assert(!ret);
+
+	/* clear out BO */
+	memset(read_buf, 0, bosize);
+	gem_write(fd, out, 0, read_buf, bosize);
+
+	/* copy 'dst' BO back into 'out' BO */
+	ret = xy_block_copy_blt(fd, cmd, batch_buf,
+				dst, out, bosize, 0, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	gem_read(fd, out, 0, read_buf, bosize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have same pattern
+	 */
+	for (i = 0; i < bosize; i++) {
+		if (read_buf[i] != input_buf[i])
+			ret++;
+	}
+	igt_assert(!ret);
+
+	/* clear read_buf */
+	memset(read_buf, 0, bosize);
+	/* read 'dst' BO into read_buf */
+	gem_read(fd, dst, 0, read_buf, bosize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have different pattern
+	 */
+	for (i = 0; i < bosize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(ret);
+
+	/* clear out BO */
+	memset(read_buf, 0, ccssize);
+	gem_write(fd, out, 0, read_buf, ccssize);
+
+	/* copy 'dst' BO's ccs into 'out' BO */
+	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+				    dst, out, ccssize, false, e);
+	igt_assert(!ret);
+
+	/* read 'out' BO into read_buf */
+	gem_read(fd, out, 0, read_buf, ccssize);
+
+	/*
+	 * check 'read_buf',
+	 * it should have different pattern
+	 */
+	for (i = 0; i < ccssize; i++) {
+		if (read_buf[i] != pattern_buf[i])
+			ret++;
+	}
+	igt_assert(ret);
+}
+
+/*
+ * Allocate a BO in SMEM.
+ * Fill a pattern
+ * Use XY_BLOCK_COPY_BLT to copy it to LMEM with compression enabled
+ * Clear the BO in SMEM, and the pattern_buf in which the pattern was
+ * stored
+ * Use XY_BLOCK_COPY_BLT to copy it back to the BO in SMEM with
+ * resolve
+ * Compare the value in the BO in SMEM matches the pattern
+ */
+static void test_ccs(int fd, int size, uint32_t region, char *sub_name,
+		     struct intel_execution_engine2 *e)
+{
+	int bosize, ccssize, ret, i;
+	int start, end;
+	uint32_t cmd, src, dst, out;
+	uint32_t batch_buf[BATCH_SIZE / sizeof(uint32_t)];
+	uint8_t *pattern_buf, *input_buf, *read_buf;
+	struct timeval tv;
+
+	if (size > 0) {
+		start = size;
+		end = start + 1;
+	} else {
+		start = BOSIZE_MIN;
+		end = BOSIZE_MAX;
+	}
+
+	/*
+	 * create batch BO in smem for execution.
+	 */
+	cmd = gem_create(fd, BATCH_SIZE);
+
+	for (bosize = start; bosize < end; bosize *= 2) {
+		/* allocate working buffers */
+		pattern_buf = malloc(bosize);
+		igt_assert(pattern_buf);
+		input_buf = malloc(bosize);
+		igt_assert(input_buf);
+		read_buf = malloc(bosize);
+		igt_assert(read_buf);
+
+		ccssize = bosize / CCS_RATIO;
+
+		/* allocate working BOs in the right location */
+		src = gem_create_in_memory_regions(fd, bosize,
+						   INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
+		dst = gem_create_in_memory_regions(fd, bosize, region);
+		out = gem_create_in_memory_regions(fd, bosize,
+						   INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
+
+		/* fill in random pattern */
+		ret = gettimeofday(&tv, NULL);
+		igt_assert(!ret);
+		srandom((int)tv.tv_usec);
+
+		for (i = 0; i < bosize; i++)
+			pattern_buf[i] = (uint8_t)rand();
+
+		igt_info("progress: bosize %d, ccssize %d\n", bosize, ccssize);
+
+		igt_dynamic_f("write_read_in_ccs_surface-%s-%s", sub_name, e->name)
+			igt_wr_xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+						     src, dst, out, ccssize,
+						     pattern_buf, read_buf, bosize, e);
+		igt_dynamic_f("verify_compression_of_random_data-%s-%s", sub_name, e->name)
+			igt_overwritten_xy_block_copy_blt(fd, cmd, batch_buf,
+							  src, dst, out, ccssize,
+							  pattern_buf, read_buf, bosize, e);
+		igt_dynamic_f("verify_corrupted_pattern_in_ccs_surface-%s-%s", sub_name, e->name)
+			igt_corrupted_xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+							    src, dst, out, ccssize,
+							    pattern_buf, read_buf, bosize, e);
+		igt_dynamic_f("copy_zero_pattern_with_compression-%s-%s", sub_name, e->name)
+			igt_copy_zero_pattern_xy_block_copy_blt(fd, cmd, batch_buf,
+								src, dst, out, ccssize, pattern_buf,
+								read_buf, input_buf, bosize, e);
+		igt_dynamic_f("copy_repeat_pattern_with_compression-%s-%s", sub_name, e->name)
+			igt_copy_repeat_pattern_xy_block_copy_blt(fd, cmd, batch_buf,
+								  src, dst, out, ccssize, pattern_buf,
+								  read_buf, input_buf, bosize, e);
+
+		/* cleanup... */
+		gem_close(fd, out);
+		gem_close(fd, dst);
+		gem_close(fd, src);
+		free(read_buf);
+		free(input_buf);
+		free(pattern_buf);
+	}
+
+	gem_close(fd, cmd);
+}
+
+igt_main
+{
+	struct drm_i915_query_memory_regions *query_info;
+	struct intel_execution_engine2 *e;
+	struct igt_collection *regions, *set;
+	char *sub_name;
+	uint32_t region;
+	int drm_fd;
+
+	igt_fixture {
+		drm_fd = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(drm_fd);
+		igt_require(AT_LEAST_GEN(intel_get_drm_devid(drm_fd), 12) > 0);
+		igt_require(HAS_FLAT_CCS(intel_get_drm_devid(drm_fd)));
+
+		query_info = gem_get_query_memory_regions(drm_fd);
+		igt_require(query_info);
+
+		set = get_memory_region_set(query_info, I915_DEVICE_MEMORY);
+	}
+
+	igt_subtest_with_dynamic("basic-gem-ccs-4K") {
+		for_each_physical_engine(drm_fd, e) {
+			if (!gem_engine_can_block_copy(drm_fd, e))
+				continue;
+
+			for_each_combination(regions, 1, set) {
+				sub_name = memregion_dynamic_subtest_name(regions);
+				region = igt_collection_get_value(regions, 0);
+				test_ccs(drm_fd, 4 * 1024, region, sub_name, e);
+				free(sub_name);
+			}
+		}
+	}
+
+	igt_subtest_with_dynamic("basic-gem-ccs-64K") {
+		for_each_physical_engine(drm_fd, e) {
+			if (!gem_engine_can_block_copy(drm_fd, e))
+				continue;
+
+			for_each_combination(regions, 1, set) {
+				sub_name = memregion_dynamic_subtest_name(regions);
+				region = igt_collection_get_value(regions, 0);
+				test_ccs(drm_fd, 64 * 1024, region, sub_name, e);
+				free(sub_name);
+			}
+		}
+	}
+
+	igt_subtest_with_dynamic("basic-gem-ccs-1M") {
+		for_each_physical_engine(drm_fd, e) {
+			if (!gem_engine_can_block_copy(drm_fd, e))
+				continue;
+
+			for_each_combination(regions, 1, set) {
+				sub_name = memregion_dynamic_subtest_name(regions);
+				region = igt_collection_get_value(regions, 0);
+				test_ccs(drm_fd, 1024 * 1024, region, sub_name, e);
+				free(sub_name);
+			}
+		}
+	}
+
+	igt_subtest_with_dynamic("basic-gem-ccs-all") {
+		for_each_physical_engine(drm_fd, e) {
+			if (!gem_engine_can_block_copy(drm_fd, e))
+				continue;
+
+			for_each_combination(regions, 1, set) {
+				sub_name = memregion_dynamic_subtest_name(regions);
+				region = igt_collection_get_value(regions, 0);
+				test_ccs(drm_fd, 0, region, sub_name, e);
+				free(sub_name);
+			}
+		}
+	}
+
+	igt_fixture {
+		close(drm_fd);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 0af3e03a..d3e76122 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -105,6 +105,7 @@ i915_progs = [
 	'gem_blits',
 	'gem_busy',
 	'gem_caching',
+	'gem_ccs',
 	'gem_close',
 	'gem_close_race',
 	'gem_concurrent_blit',
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t, v2 3/3] i915/gem_ccs: Add testing for CCS

[Zbigniew Kempczyński]

On Mon, Nov 22, 2021 at 12:18:49PM +0530, apoorva1.singh@intel.com wrote:
> From: CQ Tang <cq.tang@intel.com>
> 
> Add gem_ccs test for CCS testing.
> Commands are constructed with XY_BLOCK_COPY_BLT
> and XY_CTRL_SURF_COPY_BLT instructions.
> 
> Signed-off-by: CQ Tang <cq.tang@intel.com>
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
> ---
>  lib/i915/gem_engine_topology.c |  38 ++
>  lib/i915/gem_engine_topology.h |   5 +
>  tests/i915/gem_ccs.c           | 640 +++++++++++++++++++++++++++++++++
>  tests/meson.build              |   1 +
>  4 files changed, 684 insertions(+)
>  create mode 100644 tests/i915/gem_ccs.c
> 
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> index 729f42b0..37b5875e 100644
> --- a/lib/i915/gem_engine_topology.c
> +++ b/lib/i915/gem_engine_topology.c
> @@ -488,6 +488,44 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
>  	return ret;
>  }
>  
> +static bool
> +__gem_engine_has_capability(int i915, const char *engine,
> +			    const char *attr, const char *cap)
> +{
> +	char buf[4096] = {};
> +	FILE *file;
> +
> +	file = __open_attr(igt_sysfs_open(i915), "r",
> +			   "engine", engine, attr, NULL);
> +	if (file) {
> +		fread(buf, 1, sizeof(buf) - 1, file);
> +		fclose(file);
> +	}
> +
> +	return strstr(buf, cap);
> +}
> +
> +bool gem_engine_has_capability(int i915, const char *engine, const char *cap)
> +{
> +	return __gem_engine_has_capability(i915, engine, "capabilities", cap);
> +}
> +
> +bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap)
> +{
> +	return __gem_engine_has_capability(i915, engine, "known_capabilities", cap);
> +}
> +
> +bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine)
> +{
> +	if (engine->class != I915_ENGINE_CLASS_COPY)
> +		return false;
> +
> +	if (!gem_engine_has_known_capability(i915, engine->name, "block_copy"))
> +		return intel_gen(intel_get_drm_devid(i915)) >= 12;
> +
> +	return gem_engine_has_capability(i915, engine->name, "block_copy");
> +}
> +
>  uint32_t gem_engine_mmio_base(int i915, const char *engine)
>  {
>  	unsigned int mmio = 0;
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> index 4cfab560..d24bc9e8 100644
> --- a/lib/i915/gem_engine_topology.h
> +++ b/lib/i915/gem_engine_topology.h
> @@ -124,6 +124,11 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
>  
>  uint32_t gem_engine_mmio_base(int i915, const char *engine);
>  
> +bool gem_engine_has_capability(int i915, const char *engine, const char *cap);
> +bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap);
> +
> +bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine);
> +
>  void dyn_sysfs_engines(int i915, int engines, const char *file,
>  		       void (*test)(int i915, int engine));
>  
> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
> new file mode 100644
> index 00000000..e4dc9139
> --- /dev/null
> +++ b/tests/i915/gem_ccs.c
> @@ -0,0 +1,640 @@
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *	CQ Tang <cq.tang@intel.com>
> + *	Neel Desai <neel.desai@intel.com>
> + *
> + */

Use SPDX instead.

> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +#include "i915/gem.h"
> +#include "i915/gem_create.h"
> +#include "lib/intel_chipset.h"
> +#include "i915/i915_blt.h"
> +
> +IGT_TEST_DESCRIPTION("Exercise the memory bandwidth compression and "
> +		     "decompression when copying data between "
> +		     "system and local memory");
> +
> +static void igt_wr_xy_ctrl_surf_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
> +					 uint32_t src, uint32_t dst, uint32_t out,
> +					 int ccssize, uint8_t *pattern_buf,
> +					 uint8_t *read_buf, int bosize,
> +					 struct intel_execution_engine2 *e)
> +{
> +	int ret, i;
> +
> +	/* set 'src' to random pattern */
> +	gem_write(fd, src, 0, pattern_buf, bosize);
> +
> +	/*
> +	 * 'dst' is lmem BO with ccs, directly
> +	 * copy content in 'src' BO to 'dst' BO's ccs
> +	 */
> +	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +				    src, dst, ccssize, true, e);
> +
> +	igt_assert(!ret);
> +
> +	/* clear out BO */
> +	memset(read_buf, 0, ccssize);
> +	gem_write(fd, out, 0, read_buf, ccssize);
> +
> +	/* copy 'dst' BO's ccs into 'out' BO */
> +	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +				    dst, out, ccssize, false, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	gem_read(fd, out, 0, read_buf, ccssize);
> +	/*
> +	 * check 'read_buf',
> +	 * it should have original pattern
> +	 */
> +	for (i = 0; i < ccssize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(!ret);
> +}

Apart of unlucky batch_buf, wouldn't be more clear like this:

static void igt_wr_xy_ctrl_surf_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
					 uint32_t src, uint32_t dst, uint32_t out,
					 int ccssize, uint8_t *pattern_buf,
					 uint8_t *read_buf, int bosize,
					 struct intel_execution_engine2 *e)
{
	gem_write(fd, src, 0, pattern_buf, bosize);
	xy_ctrl_surf_copy_blt(fd, cmd, batch_buf, src, dst, ccssize, true, e);

	memset(read_buf, 0, ccssize);
	gem_write(fd, out, 0, read_buf, ccssize);
	xy_ctrl_surf_copy_blt(fd, cmd, batch_buf, dst, out, ccssize, false, e);

	gem_read(fd, out, 0, read_buf, ccssize);

	igt_assert_f(memcmp(read_buf, pattern_buf, ccssize), 0);
}

I also wonder do we need memset() and gem_write() in the middle, imo two subsequent
blits then memcmp() should be enough. Especially if we would remove gem_sync() within
xy_ctrl_surf_copy_blt().

> +
> +static void igt_overwritten_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
> +					      uint32_t src, uint32_t dst, uint32_t out,
> +					      int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
> +					      int bosize, struct intel_execution_engine2 *e)
> +{
> +	int ret, i;
> +
> +	/************************************************/
> +	/* #2 CCS is overwritten by XY_BLOCK_COPY_BLT   */
> +	/************************************************/

This comment style looks odd, use /* */ instead of multiple stars.

> +	igt_info("copy random pattern to lmem BO with compression\n");
> +
> +	/* set 'src' to random pattern */
> +	gem_write(fd, src, 0, pattern_buf, bosize);
> +	/* set 'dst' to random pattern */
> +	gem_write(fd, dst, 0, pattern_buf, bosize);

Same, all above comments are useless, code is self explanatory here.
> +
> +	/*
> +	 * 'dst' is lmem BO with ccs,
> +	 * copy content in 'src' BO to 'dst' BO
> +	 */
> +	ret = xy_block_copy_blt(fd, cmd, batch_buf,
> +				src, dst, bosize, 1, e);
> +	igt_assert(!ret);

Same issue with ret value as in above comments, it is always 0 right now.
> +
> +	/* clear out BO */
> +	memset(read_buf, 0, ccssize);
> +	gem_write(fd, out, 0, read_buf, ccssize);
> +
> +	/* copy 'dst' BO's ccs into 'out' BO */
> +	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +				    dst, out, ccssize, false, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	gem_read(fd, out, 0, read_buf, ccssize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should NOT have original pattern
> +	 * (overwrite by XY_BLOCK_COPY_BLT)
> +	 */
> +	for (i = 0; i < ccssize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(ret);
> +
> +	/* read 'dst' BO into read_buf */
> +	memset(read_buf, 0, bosize);
> +	gem_read(fd, dst, 0, read_buf, bosize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should not have original pattern
> +	 */
> +	for (i = 0; i < bosize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(ret);
> +
> +	/* clear out BO */
> +	memset(read_buf, 0, bosize);
> +	gem_write(fd, out, 0, read_buf, bosize);
> +
> +	/* copy 'dst' BO into 'out' BO */
> +	ret = xy_block_copy_blt(fd, cmd, batch_buf,
> +				dst, out, bosize, 0, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	gem_read(fd, out, 0, read_buf, bosize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have original pattern
> +	 */
> +	for (i = 0; i < bosize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(!ret);
> +
> +	/* decompress 'dst' in place */
> +	ret = xy_block_copy_blt(fd, cmd, batch_buf,
> +				dst, dst, bosize, 2, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	memset(read_buf, 0, bosize);
> +	gem_read(fd, dst, 0, read_buf, bosize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have original pattern
> +	 */
> +	for (i = 0; i < bosize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(!ret);
> +
> +	/* clear out BO */
> +	memset(read_buf, 0, bosize);
> +	gem_write(fd, out, 0, read_buf, bosize);
> +
> +	/* copy decompressed 'dst' to 'out' */
> +	ret = xy_block_copy_blt(fd, cmd, batch_buf,
> +				dst, out, bosize, 0, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	gem_read(fd, out, 0, read_buf, bosize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have original pattern
> +	 */
> +	for (i = 0; i < bosize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +
> +	igt_assert(!ret);
> +}

Please - leave here only important comments, which describe something not obvious
instead commenting each command. Applies to functions below too. Then resubmit.

--
Zbigniew

> +
> +static void igt_corrupted_xy_ctrl_surf_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
> +						uint32_t src, uint32_t dst, uint32_t out,
> +						int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
> +						int bosize, struct intel_execution_engine2 *e)
> +{
> +	int ret, i;
> +
> +	/* set 'src' to random pattern */
> +	gem_write(fd, src, 0, pattern_buf, bosize);
> +
> +	/************************************************/
> +	/* #3 CCS is corrupted by XY_CTRL_SURF_COPY_BLT */
> +	/************************************************/
> +	igt_info("corrupt CCS via XY_CTRL_SURF_COPY_BLT\n");
> +
> +	/*
> +	 * corrupt 'dst' BO's ccs by writing directly
> +	 */
> +	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +				    src, dst, ccssize, true, e);
> +	igt_assert(!ret);
> +
> +	/* clear out BO */
> +	memset(read_buf, 0, bosize);
> +	gem_write(fd, out, 0, read_buf, bosize);
> +
> +	/* copy 'dst' BO into 'out' BO */
> +	ret = xy_block_copy_blt(fd, cmd, batch_buf,
> +				dst, out, bosize, 0, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	gem_read(fd, out, 0, read_buf, bosize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have corrupted pattern
> +	 */
> +	for (i = 0; i < bosize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(ret);
> +
> +	/* clear out BO */
> +	memset(read_buf, 0, ccssize);
> +	gem_write(fd, out, 0, read_buf, ccssize);
> +
> +	/* copy 'dst' BO's ccs into 'out' BO */
> +	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +				    dst, out, ccssize, false, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	gem_read(fd, out, 0, read_buf, ccssize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have original pattern
> +	 */
> +	for (i = 0; i < ccssize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(!ret);
> +}
> +
> +static void igt_copy_zero_pattern_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
> +						    uint32_t src, uint32_t dst, uint32_t out,
> +						    int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
> +						    uint8_t *input_buf, int bosize,
> +						    struct intel_execution_engine2 *e)
> +{
> +	int ret, i;
> +
> +	/************************************************/
> +	/* #4 Copy zeros pattern with XY_BLOCK_COPY_BLT */
> +	/************************************************/
> +	igt_info("copy zeros pattern to lmem BO with compression\n");
> +
> +	/* set src BO to random pattern */
> +	gem_write(fd, src, 0, pattern_buf, bosize);
> +	/* set dst BO to random pattern */
> +	gem_write(fd, dst, 0, pattern_buf, bosize);
> +	/* set ccs to random pattern */
> +	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +				    src, dst, ccssize, true, e);
> +	igt_assert(!ret);
> +
> +	/* clear 'src' BO */
> +	memset(input_buf, 0, bosize);
> +	gem_write(fd, src, 0, input_buf, bosize);
> +
> +	/* copy 'src' to 'dst' with compression */
> +	ret = xy_block_copy_blt(fd, cmd, batch_buf,
> +				src, dst, bosize, 1, e);
> +	igt_assert(!ret);
> +
> +	/* set out BO to random pattern */
> +	gem_write(fd, out, 0, pattern_buf, bosize);
> +
> +	/* copy 'dst' BO back into 'out' BO */
> +	ret = xy_block_copy_blt(fd, cmd, batch_buf,
> +				dst, out, bosize, 0, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	gem_read(fd, out, 0, read_buf, bosize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have same zero pattern
> +	 */
> +	for (i = 0; i < bosize; i++) {
> +		if (read_buf[i] != input_buf[i])
> +			ret++;
> +	}
> +	igt_assert(!ret);
> +
> +	/* clear read_buf */
> +	memset(read_buf, 0, bosize);
> +	/* read 'dst' BO into read_buf */
> +	gem_read(fd, dst, 0, read_buf, bosize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have the same pattern
> +	 * as zero pattern compression won't change
> +	 * target pages, only change ccs.
> +	 */
> +	for (i = 0; i < bosize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(!ret);
> +
> +	/* clear out BO */
> +	memset(read_buf, 0, ccssize);
> +	gem_write(fd, out, 0, read_buf, ccssize);
> +
> +	/* copy 'dst' BO's ccs into 'out' BO */
> +	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +				    dst, out, ccssize, false, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	gem_read(fd, out, 0, read_buf, ccssize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have different pattern
> +	 */
> +	for (i = 0; i < ccssize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(ret);
> +}
> +
> +static void igt_copy_repeat_pattern_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
> +						      uint32_t src, uint32_t dst, uint32_t out,
> +						      int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
> +						      uint8_t *input_buf, int bosize,
> +						      struct intel_execution_engine2 *e)
> +{
> +	int ret, i;
> +
> +	/************************************************/
> +	/* #5 Copy repeat pattern with XY_BLOCK_COPY_BLT*/
> +	/************************************************/
> +	igt_info("copy repeat pattern to lmem BO with compression\n");
> +
> +	/* Set 'src' to random pattern */
> +	gem_write(fd, src, 0, pattern_buf, bosize);
> +	/* Set 'dst' and 'ccs' to random pattern */
> +	gem_write(fd, src, 0, pattern_buf, ccssize);
> +	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +				    src, dst, ccssize, true, e);
> +	igt_assert(!ret);
> +	gem_write(fd, dst, 0, pattern_buf, bosize);
> +
> +	/* generate repeating pattern */
> +	input_buf[0] = (uint8_t)rand();
> +	input_buf[1] = (uint8_t)rand();
> +	input_buf[2] = (uint8_t)rand();
> +	input_buf[3] = (uint8_t)rand();
> +	for (i = 4; i < bosize; i++)
> +		input_buf[i] = input_buf[i - 4];
> +	gem_write(fd, src, 0, input_buf, bosize);
> +	ret = xy_block_copy_blt(fd, cmd, batch_buf,
> +				src, dst, bosize, 1, e);
> +	igt_assert(!ret);
> +
> +	/* clear out BO */
> +	memset(read_buf, 0, bosize);
> +	gem_write(fd, out, 0, read_buf, bosize);
> +
> +	/* copy 'dst' BO back into 'out' BO */
> +	ret = xy_block_copy_blt(fd, cmd, batch_buf,
> +				dst, out, bosize, 0, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	gem_read(fd, out, 0, read_buf, bosize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have same pattern
> +	 */
> +	for (i = 0; i < bosize; i++) {
> +		if (read_buf[i] != input_buf[i])
> +			ret++;
> +	}
> +	igt_assert(!ret);
> +
> +	/* clear read_buf */
> +	memset(read_buf, 0, bosize);
> +	/* read 'dst' BO into read_buf */
> +	gem_read(fd, dst, 0, read_buf, bosize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have different pattern
> +	 */
> +	for (i = 0; i < bosize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(ret);
> +
> +	/* clear out BO */
> +	memset(read_buf, 0, ccssize);
> +	gem_write(fd, out, 0, read_buf, ccssize);
> +
> +	/* copy 'dst' BO's ccs into 'out' BO */
> +	ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +				    dst, out, ccssize, false, e);
> +	igt_assert(!ret);
> +
> +	/* read 'out' BO into read_buf */
> +	gem_read(fd, out, 0, read_buf, ccssize);
> +
> +	/*
> +	 * check 'read_buf',
> +	 * it should have different pattern
> +	 */
> +	for (i = 0; i < ccssize; i++) {
> +		if (read_buf[i] != pattern_buf[i])
> +			ret++;
> +	}
> +	igt_assert(ret);
> +}
> +
> +/*
> + * Allocate a BO in SMEM.
> + * Fill a pattern
> + * Use XY_BLOCK_COPY_BLT to copy it to LMEM with compression enabled
> + * Clear the BO in SMEM, and the pattern_buf in which the pattern was
> + * stored
> + * Use XY_BLOCK_COPY_BLT to copy it back to the BO in SMEM with
> + * resolve
> + * Compare the value in the BO in SMEM matches the pattern
> + */
> +static void test_ccs(int fd, int size, uint32_t region, char *sub_name,
> +		     struct intel_execution_engine2 *e)
> +{
> +	int bosize, ccssize, ret, i;
> +	int start, end;
> +	uint32_t cmd, src, dst, out;
> +	uint32_t batch_buf[BATCH_SIZE / sizeof(uint32_t)];
> +	uint8_t *pattern_buf, *input_buf, *read_buf;
> +	struct timeval tv;
> +
> +	if (size > 0) {
> +		start = size;
> +		end = start + 1;
> +	} else {
> +		start = BOSIZE_MIN;
> +		end = BOSIZE_MAX;
> +	}
> +
> +	/*
> +	 * create batch BO in smem for execution.
> +	 */
> +	cmd = gem_create(fd, BATCH_SIZE);
> +
> +	for (bosize = start; bosize < end; bosize *= 2) {
> +		/* allocate working buffers */
> +		pattern_buf = malloc(bosize);
> +		igt_assert(pattern_buf);
> +		input_buf = malloc(bosize);
> +		igt_assert(input_buf);
> +		read_buf = malloc(bosize);
> +		igt_assert(read_buf);
> +
> +		ccssize = bosize / CCS_RATIO;
> +
> +		/* allocate working BOs in the right location */
> +		src = gem_create_in_memory_regions(fd, bosize,
> +						   INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
> +		dst = gem_create_in_memory_regions(fd, bosize, region);
> +		out = gem_create_in_memory_regions(fd, bosize,
> +						   INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
> +
> +		/* fill in random pattern */
> +		ret = gettimeofday(&tv, NULL);
> +		igt_assert(!ret);
> +		srandom((int)tv.tv_usec);
> +
> +		for (i = 0; i < bosize; i++)
> +			pattern_buf[i] = (uint8_t)rand();
> +
> +		igt_info("progress: bosize %d, ccssize %d\n", bosize, ccssize);
> +
> +		igt_dynamic_f("write_read_in_ccs_surface-%s-%s", sub_name, e->name)
> +			igt_wr_xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +						     src, dst, out, ccssize,
> +						     pattern_buf, read_buf, bosize, e);
> +		igt_dynamic_f("verify_compression_of_random_data-%s-%s", sub_name, e->name)
> +			igt_overwritten_xy_block_copy_blt(fd, cmd, batch_buf,
> +							  src, dst, out, ccssize,
> +							  pattern_buf, read_buf, bosize, e);
> +		igt_dynamic_f("verify_corrupted_pattern_in_ccs_surface-%s-%s", sub_name, e->name)
> +			igt_corrupted_xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> +							    src, dst, out, ccssize,
> +							    pattern_buf, read_buf, bosize, e);
> +		igt_dynamic_f("copy_zero_pattern_with_compression-%s-%s", sub_name, e->name)
> +			igt_copy_zero_pattern_xy_block_copy_blt(fd, cmd, batch_buf,
> +								src, dst, out, ccssize, pattern_buf,
> +								read_buf, input_buf, bosize, e);
> +		igt_dynamic_f("copy_repeat_pattern_with_compression-%s-%s", sub_name, e->name)
> +			igt_copy_repeat_pattern_xy_block_copy_blt(fd, cmd, batch_buf,
> +								  src, dst, out, ccssize, pattern_buf,
> +								  read_buf, input_buf, bosize, e);
> +
> +		/* cleanup... */
> +		gem_close(fd, out);
> +		gem_close(fd, dst);
> +		gem_close(fd, src);
> +		free(read_buf);
> +		free(input_buf);
> +		free(pattern_buf);
> +	}
> +
> +	gem_close(fd, cmd);
> +}
> +
> +igt_main
> +{
> +	struct drm_i915_query_memory_regions *query_info;
> +	struct intel_execution_engine2 *e;
> +	struct igt_collection *regions, *set;
> +	char *sub_name;
> +	uint32_t region;
> +	int drm_fd;
> +
> +	igt_fixture {
> +		drm_fd = drm_open_driver(DRIVER_INTEL);
> +		igt_require_gem(drm_fd);
> +		igt_require(AT_LEAST_GEN(intel_get_drm_devid(drm_fd), 12) > 0);
> +		igt_require(HAS_FLAT_CCS(intel_get_drm_devid(drm_fd)));
> +
> +		query_info = gem_get_query_memory_regions(drm_fd);
> +		igt_require(query_info);
> +
> +		set = get_memory_region_set(query_info, I915_DEVICE_MEMORY);
> +	}
> +
> +	igt_subtest_with_dynamic("basic-gem-ccs-4K") {
> +		for_each_physical_engine(drm_fd, e) {
> +			if (!gem_engine_can_block_copy(drm_fd, e))
> +				continue;
> +
> +			for_each_combination(regions, 1, set) {
> +				sub_name = memregion_dynamic_subtest_name(regions);
> +				region = igt_collection_get_value(regions, 0);
> +				test_ccs(drm_fd, 4 * 1024, region, sub_name, e);
> +				free(sub_name);
> +			}
> +		}
> +	}
> +
> +	igt_subtest_with_dynamic("basic-gem-ccs-64K") {
> +		for_each_physical_engine(drm_fd, e) {
> +			if (!gem_engine_can_block_copy(drm_fd, e))
> +				continue;
> +
> +			for_each_combination(regions, 1, set) {
> +				sub_name = memregion_dynamic_subtest_name(regions);
> +				region = igt_collection_get_value(regions, 0);
> +				test_ccs(drm_fd, 64 * 1024, region, sub_name, e);
> +				free(sub_name);
> +			}
> +		}
> +	}
> +
> +	igt_subtest_with_dynamic("basic-gem-ccs-1M") {
> +		for_each_physical_engine(drm_fd, e) {
> +			if (!gem_engine_can_block_copy(drm_fd, e))
> +				continue;
> +
> +			for_each_combination(regions, 1, set) {
> +				sub_name = memregion_dynamic_subtest_name(regions);
> +				region = igt_collection_get_value(regions, 0);
> +				test_ccs(drm_fd, 1024 * 1024, region, sub_name, e);
> +				free(sub_name);
> +			}
> +		}
> +	}
> +
> +	igt_subtest_with_dynamic("basic-gem-ccs-all") {
> +		for_each_physical_engine(drm_fd, e) {
> +			if (!gem_engine_can_block_copy(drm_fd, e))
> +				continue;
> +
> +			for_each_combination(regions, 1, set) {
> +				sub_name = memregion_dynamic_subtest_name(regions);
> +				region = igt_collection_get_value(regions, 0);
> +				test_ccs(drm_fd, 0, region, sub_name, e);
> +				free(sub_name);
> +			}
> +		}
> +	}
> +
> +	igt_fixture {
> +		close(drm_fd);
> +	}
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index 0af3e03a..d3e76122 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -105,6 +105,7 @@ i915_progs = [
>  	'gem_blits',
>  	'gem_busy',
>  	'gem_caching',
> +	'gem_ccs',
>  	'gem_close',
>  	'gem_close_race',
>  	'gem_concurrent_blit',
> -- 
> 2.25.1
> 

[igt-dev] ✓ Fi.CI.BAT: success for Add testing for CCS (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8190 bytes --]

== Series Details ==

Series: Add testing for CCS (rev2)
URL   : https://patchwork.freedesktop.org/series/96648/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10910 -> IGTPW_6420
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/index.html

Participating hosts (38 -> 34)
------------------------------

  Additional (2): fi-kbl-soraka fi-tgl-u2 
  Missing    (6): bat-dg1-6 bat-dg1-5 bat-adlp-6 bat-adlp-4 bat-jsl-2 bat-jsl-1 

Known issues
------------

  Here are the changes found in IGTPW_6420 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-snb-2600:        NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][2] ([fdo#109271]) +12 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_flink_basic@bad-flink:
    - fi-skl-6600u:       [PASS][3] -> [FAIL][4] ([i915#4547])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html

  * igt@gem_huc_copy@huc-copy:
    - fi-tgl-u2:          NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
    - fi-kbl-soraka:      NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-tgl-u2:          NOTRUN -> [SKIP][7] ([i915#4555])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-tgl-u2/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-tgl-u2:          NOTRUN -> [SKIP][8] ([i915#4555] / [i915#4565]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-hpd-fast:
    - fi-tgl-u2:          NOTRUN -> [SKIP][11] ([fdo#109284] / [fdo#111827]) +8 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-bdw-samus:       NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-bdw-samus/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-tgl-u2:          NOTRUN -> [SKIP][13] ([i915#4103]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-tgl-u2:          NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-bdw-samus:       NOTRUN -> [SKIP][15] ([fdo#109271]) +33 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-bdw-samus/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
    - fi-kbl-soraka:      NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
    - fi-tgl-u2:          NOTRUN -> [SKIP][17] ([i915#3301])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-tgl-u2/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-skl-6600u:       NOTRUN -> [FAIL][18] ([i915#3363] / [i915#4312])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-skl-6600u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-tgl-1115g4:      [FAIL][19] ([i915#1888]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
    - fi-bdw-samus:       [INCOMPLETE][21] ([i915#146] / [i915#2539]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/fi-bdw-samus/igt@gem_exec_suspend@basic-s0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-bdw-samus/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [INCOMPLETE][23] ([i915#3921]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@perf:
    - {fi-tgl-dsi}:       [DMESG-WARN][25] ([i915#2867]) -> [PASS][26] +15 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/fi-tgl-dsi/igt@i915_selftest@live@perf.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/fi-tgl-dsi/igt@i915_selftest@live@perf.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4555]: https://gitlab.freedesktop.org/drm/intel/issues/4555
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6285 -> IGTPW_6420

  CI-20190529: 20190529
  CI_DRM_10910: c1f57b3bc20a7ca6ffe6acc64d2a4d0ec4c327f6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6420: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/index.html
  IGT_6285: 2e0355faad5c2e81cd6705b76e529ce526c7c9bf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@gem_ccs@basic-gem-ccs-1m
+igt@gem_ccs@basic-gem-ccs-4k
+igt@gem_ccs@basic-gem-ccs-64k
+igt@gem_ccs@basic-gem-ccs-all

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/index.html

[-- Attachment #2: Type: text/html, Size: 9989 bytes --]

[igt-dev] ✗ Fi.CI.IGT: failure for Add testing for CCS (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30244 bytes --]

== Series Details ==

Series: Add testing for CCS (rev2)
URL   : https://patchwork.freedesktop.org/series/96648/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10910_full -> IGTPW_6420_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_6420_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_6420_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/index.html

Participating hosts (10 -> 7)
------------------------------

  Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6420_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@gem_ccs@basic-gem-ccs-4k} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][1] +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb6/igt@gem_ccs@basic-gem-ccs-4k.html

  * {igt@gem_ccs@basic-gem-ccs-all} (NEW):
    - shard-tglb:         NOTRUN -> [SKIP][2] +3 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb7/igt@gem_ccs@basic-gem-ccs-all.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-glk:          [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-glk5/igt@gem_workarounds@suspend-resume-fd.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-glk1/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen9_exec_parse@bb-large:
    - shard-apl:          [PASS][5] -> [TIMEOUT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-apl8/igt@gen9_exec_parse@bb-large.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl7/igt@gen9_exec_parse@bb-large.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
    - shard-kbl:          NOTRUN -> [INCOMPLETE][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl7/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled:
    - shard-glk:          [PASS][8] -> [FAIL][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-glk3/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-glk8/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html

  * igt@sysfs_heartbeat_interval@mixed@vecs0:
    - shard-kbl:          [PASS][10] -> [INCOMPLETE][11] +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-kbl2/igt@sysfs_heartbeat_interval@mixed@vecs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl7/igt@sysfs_heartbeat_interval@mixed@vecs0.html

  
New tests
---------

  New tests have been introduced between CI_DRM_10910_full and IGTPW_6420_full:

### New IGT tests (4) ###

  * igt@gem_ccs@basic-gem-ccs-1m:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ccs@basic-gem-ccs-4k:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ccs@basic-gem-ccs-64k:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ccs@basic-gem-ccs-all:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_6420_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-tglb:         NOTRUN -> [SKIP][12] ([fdo#109314])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb6/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_persistence@hostile:
    - shard-snb:          NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-snb7/igt@gem_ctx_persistence@hostile.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-tglb:         NOTRUN -> [SKIP][14] ([i915#280])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb1/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [PASS][19] -> [SKIP][20] ([fdo#109271])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_params@no-bsd:
    - shard-iclb:         NOTRUN -> [SKIP][21] ([fdo#109283])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb3/igt@gem_exec_params@no-bsd.html

  * igt@gem_exec_params@secure-non-root:
    - shard-tglb:         NOTRUN -> [SKIP][22] ([fdo#112283])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb6/igt@gem_exec_params@secure-non-root.html
    - shard-iclb:         NOTRUN -> [SKIP][23] ([fdo#112283])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb6/igt@gem_exec_params@secure-non-root.html

  * igt@gem_exec_whisper@basic-contexts-priority:
    - shard-iclb:         [PASS][24] -> [INCOMPLETE][25] ([i915#1895])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-iclb5/igt@gem_exec_whisper@basic-contexts-priority.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb7/igt@gem_exec_whisper@basic-contexts-priority.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-iclb:         NOTRUN -> [SKIP][26] ([i915#4555])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb5/igt@gem_lmem_swapping@parallel-random.html
    - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#4555] / [i915#4565])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb6/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_media_vme:
    - shard-tglb:         NOTRUN -> [SKIP][28] ([i915#284])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb3/igt@gem_media_vme.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          NOTRUN -> [WARN][29] ([i915#2658])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl7/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-iclb:         NOTRUN -> [WARN][30] ([i915#2658])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb7/igt@gem_pwrite@basic-exhaustion.html
    - shard-kbl:          NOTRUN -> [WARN][31] ([i915#2658])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl2/igt@gem_pwrite@basic-exhaustion.html
    - shard-tglb:         NOTRUN -> [WARN][32] ([i915#2658])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb2/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
    - shard-tglb:         NOTRUN -> [SKIP][33] ([i915#4270]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb2/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([i915#4270]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb4/igt@gem_pxp@reject-modify-context-protection-off-1.html

  * igt@gem_render_copy@yf-tiled-to-vebox-linear:
    - shard-iclb:         NOTRUN -> [SKIP][35] ([i915#768]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb4/igt@gem_render_copy@yf-tiled-to-vebox-linear.html

  * igt@gem_userptr_blits@input-checking:
    - shard-tglb:         NOTRUN -> [DMESG-WARN][36] ([i915#3002])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb3/igt@gem_userptr_blits@input-checking.html

  * igt@gen3_render_tiledy_blits:
    - shard-tglb:         NOTRUN -> [SKIP][37] ([fdo#109289]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb5/igt@gen3_render_tiledy_blits.html

  * igt@gen9_exec_parse@batch-zero-length:
    - shard-iclb:         NOTRUN -> [SKIP][38] ([i915#2856]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb4/igt@gen9_exec_parse@batch-zero-length.html

  * igt@gen9_exec_parse@bb-secure:
    - shard-tglb:         NOTRUN -> [SKIP][39] ([i915#2856]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb5/igt@gen9_exec_parse@bb-secure.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [PASS][40] -> [INCOMPLETE][41] ([i915#3921])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-snb6/igt@i915_selftest@live@hangcheck.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-snb4/igt@i915_selftest@live@hangcheck.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([fdo#111614]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb6/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([fdo#110725] / [fdo#111614])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb1/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglb:         NOTRUN -> [SKIP][44] ([fdo#111615]) +3 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +3 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl7/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][46] ([i915#3689] / [i915#3886]) +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb5/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][47] ([fdo#109278] / [i915#3886]) +3 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb3/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
    - shard-apl:          NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3886]) +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
    - shard-glk:          NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-glk5/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-random-ccs-data-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([fdo#111615] / [i915#3689]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb3/igt@kms_ccs@pipe-c-random-ccs-data-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][51] ([i915#3689]) +3 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb7/igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_ccs.html

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:
    - shard-apl:          NOTRUN -> [SKIP][52] ([fdo#109271]) +57 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl3/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html

  * igt@kms_chamelium@dp-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl6/igt@kms_chamelium@dp-edid-change-during-suspend.html

  * igt@kms_color@pipe-d-ctm-green-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][54] ([fdo#109278] / [i915#1149])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb8/igt@kms_color@pipe-d-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
    - shard-iclb:         NOTRUN -> [SKIP][55] ([fdo#109284] / [fdo#111827]) +3 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb6/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
    - shard-snb:          NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-snb4/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html

  * igt@kms_color_chamelium@pipe-c-gamma:
    - shard-kbl:          NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl2/igt@kms_color_chamelium@pipe-c-gamma.html
    - shard-glk:          NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-glk7/igt@kms_color_chamelium@pipe-c-gamma.html

  * igt@kms_color_chamelium@pipe-d-ctm-max:
    - shard-iclb:         NOTRUN -> [SKIP][59] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-max.html

  * igt@kms_color_chamelium@pipe-d-degamma:
    - shard-tglb:         NOTRUN -> [SKIP][60] ([fdo#109284] / [fdo#111827]) +5 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb7/igt@kms_color_chamelium@pipe-d-degamma.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-iclb:         NOTRUN -> [SKIP][61] ([i915#3116])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb5/igt@kms_content_protection@dp-mst-lic-type-1.html
    - shard-tglb:         NOTRUN -> [SKIP][62] ([i915#3116])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb2/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_cursor_crc@pipe-a-cursor-max-size-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][63] ([i915#3359]) +4 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-max-size-rapid-movement.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][64] -> [DMESG-WARN][65] ([i915#180]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
    - shard-tglb:         [PASS][66] -> [INCOMPLETE][67] ([i915#2411] / [i915#2828] / [i915#456])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-b-cursor-max-size-onscreen:
    - shard-glk:          NOTRUN -> [SKIP][68] ([fdo#109271]) +16 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-glk3/igt@kms_cursor_crc@pipe-b-cursor-max-size-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][69] ([i915#3319]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][70] ([fdo#109279] / [i915#3359]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-tglb:         [PASS][71] -> [INCOMPLETE][72] ([i915#2411] / [i915#4211])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][73] ([fdo#109274] / [fdo#109278])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-iclb:         [PASS][74] -> [FAIL][75] ([i915#2346])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-iclb4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@pipe-c-single-bo:
    - shard-kbl:          [PASS][76] -> [INCOMPLETE][77] ([i915#794])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-kbl7/igt@kms_cursor_legacy@pipe-c-single-bo.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl7/igt@kms_cursor_legacy@pipe-c-single-bo.html

  * igt@kms_flip@2x-flip-vs-panning:
    - shard-iclb:         NOTRUN -> [SKIP][78] ([fdo#109274]) +2 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb8/igt@kms_flip@2x-flip-vs-panning.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
    - shard-glk:          [PASS][79] -> [FAIL][80] ([i915#79])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-apl:          [PASS][81] -> [DMESG-WARN][82] ([i915#180]) +4 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-apl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
    - shard-iclb:         NOTRUN -> [SKIP][83] ([i915#3701])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
    - shard-apl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2672])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
    - shard-kbl:          NOTRUN -> [SKIP][85] ([fdo#109271]) +107 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
    - shard-tglb:         NOTRUN -> [SKIP][86] ([fdo#111825]) +23 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
    - shard-iclb:         NOTRUN -> [SKIP][87] ([fdo#109280]) +14 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-tglb:         NOTRUN -> [SKIP][88] ([i915#433])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb7/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@static-swap:
    - shard-tglb:         NOTRUN -> [SKIP][89] ([i915#1187])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb2/igt@kms_hdr@static-swap.html
    - shard-iclb:         NOTRUN -> [SKIP][90] ([i915#1187])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb6/igt@kms_hdr@static-swap.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][91] ([fdo#108145] / [i915#265]) +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-kbl:          NOTRUN -> [FAIL][92] ([i915#265])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_cursor@pipe-d-viewport-size-128:
    - shard-iclb:         NOTRUN -> [SKIP][93] ([fdo#109278]) +12 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb6/igt@kms_plane_cursor@pipe-d-viewport-size-128.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-tglb:         NOTRUN -> [SKIP][94] ([i915#3536])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb7/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_plane_lowres@pipe-a-tiling-yf:
    - shard-iclb:         NOTRUN -> [SKIP][95] ([i915#3536]) +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-yf.html
    - shard-tglb:         NOTRUN -> [SKIP][96] ([fdo#111615] / [fdo#112054])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb3/igt@kms_plane_lowres@pipe-a-tiling-yf.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-tglb:         NOTRUN -> [SKIP][97] ([i915#2920]) +3 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb3/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
    - shard-iclb:         NOTRUN -> [SKIP][98] ([i915#658]) +2 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-apl:          NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#658])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
    - shard-snb:          NOTRUN -> [SKIP][100] ([fdo#109271]) +30 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-snb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
    - shard-glk:          NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#658])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-glk2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
    - shard-kbl:          NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#658])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-tglb:         NOTRUN -> [SKIP][103] ([i915#1911])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb6/igt@kms_psr2_su@frontbuffer.html
    - shard-iclb:         NOTRUN -> [SKIP][104] ([fdo#109642] / [fdo#111068] / [i915#658])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb1/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][105] -> [SKIP][106] ([fdo#109441]) +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb8/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_psr@psr2_sprite_plane_onoff:
    - shard-tglb:         NOTRUN -> [FAIL][107] ([i915#132] / [i915#3467])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb8/igt@kms_psr@psr2_sprite_plane_onoff.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-apl:          NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#2437])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl3/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@nouveau_crc@pipe-c-source-outp-complete:
    - shard-tglb:         NOTRUN -> [SKIP][109] ([i915#2530]) +1 similar issue
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb8/igt@nouveau_crc@pipe-c-source-outp-complete.html
    - shard-iclb:         NOTRUN -> [SKIP][110] ([i915#2530]) +1 similar issue
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb2/igt@nouveau_crc@pipe-c-source-outp-complete.html

  * igt@prime_nv_api@i915_nv_double_import:
    - shard-iclb:         NOTRUN -> [SKIP][111] ([fdo#109291])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb4/igt@prime_nv_api@i915_nv_double_import.html

  * igt@prime_nv_pcopy@test2:
    - shard-tglb:         NOTRUN -> [SKIP][112] ([fdo#109291])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb5/igt@prime_nv_pcopy@test2.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-tglb:         NOTRUN -> [SKIP][113] ([fdo#109307])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb5/igt@tools_test@sysfs_l3_parity.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [FAIL][114] ([i915#2842]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-tglb:         [FAIL][116] ([i915#2842]) -> [PASS][117] +1 similar issue
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-tglb2/igt@gem_exec_fair@basic-pace@vecs0.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb5/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-sync@rcs0:
    - shard-kbl:          [SKIP][118] ([fdo#109271]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-kbl6/igt@gem_exec_fair@basic-sync@rcs0.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl1/igt@gem_exec_fair@basic-sync@rcs0.html

  * igt@gem_exec_whisper@basic-queues-forked-all:
    - shard-glk:          [DMESG-WARN][120] ([i915#118]) -> [PASS][121] +1 similar issue
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-glk8/igt@gem_exec_whisper@basic-queues-forked-all.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-glk5/igt@gem_exec_whisper@basic-queues-forked-all.html

  * igt@gem_partial_pwrite_pread@writes-after-reads:
    - shard-kbl:          [INCOMPLETE][122] -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-kbl7/igt@gem_partial_pwrite_pread@writes-after-reads.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl6/igt@gem_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_softpin@noreloc-s3:
    - shard-tglb:         [INCOMPLETE][124] ([i915#1373] / [i915#456]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-tglb7/igt@gem_softpin@noreloc-s3.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb5/igt@gem_softpin@noreloc-s3.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-kbl:          [INCOMPLETE][126] ([i915#151]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-kbl4/igt@i915_pm_rpm@system-suspend.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-kbl6/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_suspend@debugfs-reader:
    - shard-apl:          [DMESG-WARN][128] ([i915#180]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-apl3/igt@i915_suspend@debugfs-reader.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-apl6/igt@i915_suspend@debugfs-reader.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
    - shard-tglb:         [INCOMPLETE][130] ([i915#2411] / [i915#456]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-tglb7/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-tglb6/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][132] ([fdo#109441]) -> [PASS][133] +1 similar issue
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_setmode@basic:
    - shard-glk:          [FAIL][134] ([i915#31]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10910/shard-glk8/igt@kms_setmode@basic.html
   [135]: https://intel-gfx-ci.01.org/tree/d

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6420/index.html

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