[igt-dev] [PATCH i-g-t v2 0/4] enable 4-tiled ccs modifiers on dg2

[igt-dev] [PATCH i-g-t v2 0/4] enable 4-tiled ccs modifiers on dg2

[Jeevan B]

LOCAL_I915_FORMAT_MOD_4_TILED_DG2_RC_CCS work for creating framebuffers, they
will pass crc checks. Copying from compressed to non-compressed for some
reason will copy compressed main surface instead of decompressing.

LOCAL_I915_FORMAT_MOD_4_TILED_DG2_MC_CCS produce good image if image is
framebuffer is all solid color. Areas with color edges sometimes cause random
compression block size content, these blocks show at same locations but yet
unknown where they're coming from. xrgb, xyuv and 16bpp yuv work equally.
Planar framebuffers cause fifo underrun hence no idea if content is good or no.

v2: pull headers from kernel

Jeevan B (1):
  drm/fourcc: Import drm_fourcc header from 9035039e1ed69

Juha-Pekka Heikkilä (3):
  lib/DG2: create flat ccs framebuffers with 4-tile
  tests/kms_ccs: Add dg2 tiled-4 ccs modifiers
  tests/kms_getfb: Add flat ccs modifier support

 include/drm-uapi/drm_fourcc.h |  36 ++++++++++
 lib/gen9_render.h             |  40 ++++++++---
 lib/igt_fb.c                  |  49 ++++++++++---
 lib/intel_aux_pgtable.c       |   6 +-
 lib/intel_batchbuffer.c       |   2 +-
 lib/intel_bufops.c            | 119 +++++++++++++++++++++++++++----
 lib/intel_chipset.h           |   3 +-
 lib/rendercopy_gen9.c         | 127 +++++++++++++++++++++++-----------
 lib/veboxcopy_gen12.c         | 109 +++++++++++++++++++++--------
 tests/i915/kms_ccs.c          |  62 ++++++++++-------
 tests/kms_getfb.c             |  20 +++++-
 11 files changed, 439 insertions(+), 134 deletions(-)

-- 
2.35.1

[igt-dev] [PATCH i-g-t v2 1/4] drm/fourcc: Import drm_fourcc header from 9035039e1ed69

[Jeevan B]

commit 9035039e1ed691cd893777a42e048003a2f349d6
Author: Mika Kahola <mika.kahola@intel.com>
Date:   Mon Apr 11 17:34:04 2022 +0300

    drm/fourcc: Introduce format modifier for DG2 clear color

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 include/drm-uapi/drm_fourcc.h | 36 +++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index d8f7cad9..78bebdea 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -583,6 +583,42 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
 
+/*
+ * Intel color control surfaces (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
+
+/*
+ * Intel color control surfaces (CCS) for DG2 media compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. For semi-planar formats
+ * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
+ * 0 and 1, respectively. The CCS for all planes are stored outside of the
+ * GEM object in a reserved memory area dedicated for the storage of the
+ * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
+ * pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
+
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths. The
+ * clear color is stored at plane index 1 and the pitch should be ignored. The
+ * format of the 256 bits of clear color data matches the one used for the
+ * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
+ * for details.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.35.1

[igt-dev] [PATCH i-g-t v2 2/4] lib/DG2: create flat ccs framebuffers with 4-tile

[Jeevan B]

From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>

Add support for DG2 flat ccs framebuffers with tile-4.

Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 lib/gen9_render.h       |  40 ++++++++++---
 lib/igt_fb.c            |  49 ++++++++++++----
 lib/intel_aux_pgtable.c |   6 +-
 lib/intel_batchbuffer.c |   2 +-
 lib/intel_bufops.c      | 119 +++++++++++++++++++++++++++++++++----
 lib/intel_chipset.h     |   3 +-
 lib/rendercopy_gen9.c   | 127 +++++++++++++++++++++++++++-------------
 lib/veboxcopy_gen12.c   | 109 +++++++++++++++++++++++++---------
 8 files changed, 348 insertions(+), 107 deletions(-)

diff --git a/lib/gen9_render.h b/lib/gen9_render.h
index 06d9718c..82a9f99c 100644
--- a/lib/gen9_render.h
+++ b/lib/gen9_render.h
@@ -59,9 +59,15 @@ struct gen9_surface_state {
 		uint32_t depth:11;
 	} ss3;
 
-	struct {
-		uint32_t minimum_array_element:27;
-		uint32_t pad0:5;
+	union {
+		struct {
+			uint32_t minimum_array_element:27;
+			uint32_t pad0:5;
+		} skl;
+		struct {
+			uint32_t decompress_in_l3:1;
+			uint32_t pad0:31;
+		} dg2;
 	} ss4;
 
 	struct {
@@ -116,6 +122,15 @@ struct gen9_surface_state {
 			uint32_t media_compression:1;
 			uint32_t pad2:1;
 		} tgl;
+
+		struct {
+			uint32_t pad0:14;
+			uint32_t disable_support_for_multi_gpu_partial_writes:1;
+			uint32_t disable_support_for_multi_gpu_atomics:1;
+			uint32_t pad1:14;
+			uint32_t memory_compression_enable:1;
+			uint32_t memory_compression_type:1;
+		} dg2;
 	} ss7;
 
 	struct {
@@ -138,15 +153,22 @@ struct gen9_surface_state {
 		uint32_t aux_base_addr_hi;
 	} ss11;
 
-	/* register can be used for either
-	 * clear value or depth clear value
-	 */
 	struct {
-		uint32_t clear_address;
-	} ss12;
+		/*
+		 * compression_format is used only dg2 onward.
+		 * prior to dg2 full ss12 is used for the address
+		 * but due to alignments bits 0..6 will be zero
+		 * and asserted in code to be so
+		 */
+		uint32_t compression_format:5;
+		uint32_t pad0:1;
+		uint32_t clear_address:26;
+        } ss12;
 
 	struct {
-		uint32_t clear_address_hi;
+		uint32_t clear_address_hi:16;
+		uint32_t pad0:16;
+
 	} ss13;
 
 	struct {
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index eafbe7fd..93e98733 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -457,6 +457,9 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 	case I915_FORMAT_MOD_4_TILED:
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 		igt_require_intel(fd);
 		if (intel_display_ver(intel_get_drm_devid(fd)) == 2) {
 			*width_ret = 128;
@@ -565,14 +568,17 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 
 static bool is_gen12_mc_ccs_modifier(uint64_t modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+		modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
 }
 
 static bool is_gen12_ccs_modifier(uint64_t modifier)
 {
 	return is_gen12_mc_ccs_modifier(modifier) ||
 		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
-		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
+		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
+		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS ||
+		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
 }
 
 static bool is_ccs_modifier(uint64_t modifier)
@@ -584,7 +590,7 @@ static bool is_ccs_modifier(uint64_t modifier)
 
 static bool is_ccs_plane(const struct igt_fb *fb, int plane)
 {
-	if (!is_ccs_modifier(fb->modifier))
+	if (!is_ccs_modifier(fb->modifier) || HAS_FLATCCS(intel_get_drm_devid(fb->fd)))
 		return false;
 
 	return plane >= fb->num_planes / 2;
@@ -602,8 +608,15 @@ static bool is_gen12_ccs_plane(const struct igt_fb *fb, int plane)
 
 static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)
 {
-	return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
-	       plane == 2;
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
+	    plane == 2)
+		return true;
+
+	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC &&
+            plane == 1)
+		return true;
+
+	return false;
 }
 
 bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)
@@ -689,7 +702,8 @@ static int fb_num_planes(const struct igt_fb *fb)
 	if (is_ccs_modifier(fb->modifier))
 		num_planes *= 2;
 
-	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
+	    fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
 		num_planes++;
 
 	return num_planes;
@@ -763,7 +777,7 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
 		return ALIGN(min_stride, tile_width);
 	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
 		/* clear color always fixed to 64 bytes */
-		return 64;
+		return HAS_FLATCCS(intel_get_drm_devid(fb->fd)) ? 512 : 64;
 	} else if (is_gen12_ccs_plane(fb, plane)) {
 		/*
 		 * The CCS surface stride is
@@ -966,6 +980,9 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
 	case I915_FORMAT_MOD_4_TILED:
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 		return I915_TILING_4;
 	case I915_FORMAT_MOD_Yf_TILED:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2504,9 +2521,10 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
 	if (is_ccs_modifier(fb->modifier)) {
 		igt_assert_eq(fb->strides[0] & 127, 0);
 
-		if (is_gen12_ccs_modifier(fb->modifier))
-			igt_assert_eq(fb->strides[1] & 63, 0);
-		else
+		if (is_gen12_ccs_modifier(fb->modifier)) {
+			if (!HAS_FLATCCS(intel_get_drm_devid(fb->fd)))
+				igt_assert_eq(fb->strides[1] & 63, 0);
+		} else
 			igt_assert_eq(fb->strides[1] & 127, 0);
 
 		if (is_gen12_mc_ccs_modifier(fb->modifier))
@@ -2539,7 +2557,7 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
 		buf->yuv_semiplanar_bpp = yuv_semiplanar_bpp(fb->drm_format);
 
 	if (is_ccs_modifier(fb->modifier)) {
-		num_surfaces = fb->num_planes / 2;
+		num_surfaces = fb->num_planes / (HAS_FLATCCS(intel_get_drm_devid(fb->fd)) ? 1 : 2);
 		for (i = 0; i < num_surfaces; i++)
 			init_buf_ccs(buf, i,
 				     fb->offsets[num_surfaces + i],
@@ -2560,6 +2578,9 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
 	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
 		buf->cc.offset = fb->offsets[2];
 
+	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
+		buf->cc.offset = fb->offsets[1];
+
 	return buf;
 }
 
@@ -4570,6 +4591,12 @@ const char *igt_fb_modifier_name(uint64_t modifier)
 		return "Y-MC_CCS";
 	case I915_FORMAT_MOD_4_TILED:
 		return "4";
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+		return "4-RC_CCS";
+	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+		return "4-MC_CCS";
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+		return "4-RC_CCS-CC";
 	default:
 		return "?";
 	}
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index f5796fdf..e31a6c34 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -263,7 +263,8 @@ static uint64_t pgt_get_l1_flags(const struct intel_buf *buf, int surface_idx)
 	} entry = {
 		.e = {
 			.valid = 1,
-			.tile_mode = buf->tiling == I915_TILING_Y ? 1 : 0,
+			.tile_mode = buf->tiling == I915_TILING_Y ? 1 :
+				(buf->tiling == I915_TILING_4 ? 2 : 0),
 		}
 	};
 
@@ -274,7 +275,8 @@ static uint64_t pgt_get_l1_flags(const struct intel_buf *buf, int surface_idx)
 	 */
 	igt_assert(buf->tiling == I915_TILING_Y ||
 		   buf->tiling == I915_TILING_Yf ||
-		   buf->tiling == I915_TILING_Ys);
+		   buf->tiling == I915_TILING_Ys ||
+		   buf->tiling == I915_TILING_4);
 
 	entry.e.ycr = surface_idx > 0;
 
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index ebf3c598..81d2e140 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1146,7 +1146,7 @@ igt_render_copyfunc_t igt_get_render_copyfunc(int devid)
 		copy = gen9_render_copyfunc;
 	else if (IS_GEN11(devid))
 		copy = gen11_render_copyfunc;
-	else if (IS_DG2(devid))
+	else if (HAS_4TILE(devid))
 		copy = gen12p71_render_copyfunc;
 	else if (IS_GEN12(devid))
 		copy = gen12_render_copyfunc;
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index f13063fa..72b1bafa 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -89,6 +89,7 @@
 #define TILE_Y      TILE_DEF(I915_TILING_Y)
 #define TILE_Yf     TILE_DEF(I915_TILING_Yf)
 #define TILE_Ys     TILE_DEF(I915_TILING_Ys)
+#define TILE_4      TILE_DEF(I915_TILING_4)
 
 #define CCS_OFFSET(buf) (buf->ccs[0].offset)
 #define CCS_SIZE(gen, buf) \
@@ -105,16 +106,19 @@ struct buf_ops {
 	uint32_t supported_hw_tiles;
 	uint32_t swizzle_x;
 	uint32_t swizzle_y;
+	uint32_t swizzle_tile4;
 	bo_copy linear_to;
 	bo_copy linear_to_x;
 	bo_copy linear_to_y;
 	bo_copy linear_to_yf;
 	bo_copy linear_to_ys;
+	bo_copy linear_to_tile4;
 	bo_copy to_linear;
 	bo_copy x_to_linear;
 	bo_copy y_to_linear;
 	bo_copy yf_to_linear;
 	bo_copy ys_to_linear;
+	bo_copy tile4_to_linear;
 };
 
 static const char *tiling_str(uint32_t tiling)
@@ -125,6 +129,7 @@ static const char *tiling_str(uint32_t tiling)
 	case I915_TILING_Y:    return "Y";
 	case I915_TILING_Yf:   return "Yf";
 	case I915_TILING_Ys:   return "Ys";
+	case I915_TILING_4:    return "4";
 	default:               return "UNKNOWN";
 	}
 }
@@ -222,7 +227,8 @@ static void set_hw_tiled(struct buf_ops *bops, struct intel_buf *buf)
 {
 	uint32_t ret_tiling, ret_swizzle;
 
-	if (buf->tiling != I915_TILING_X && buf->tiling != I915_TILING_Y)
+	if (buf->tiling != I915_TILING_X && buf->tiling != I915_TILING_Y &&
+	    buf->tiling != I915_TILING_4)
 		return;
 
 	if (!buf_ops_has_hw_fence(bops, buf->tiling)) {
@@ -320,6 +326,50 @@ static void *y_ptr(void *ptr,
 	return ptr + pos;
 }
 
+/*
+ * (x,y) to memory location in tiled-4 surface
+ *
+ * coverted those divisions and multiplications to shifts and masks
+ * in hope this wouldn't be so slow.
+ */
+static void *tile4_ptr(void *ptr,
+			unsigned int x, unsigned int y,
+			unsigned int stride, unsigned int cpp)
+{
+	const int tile_width = 128;
+	const int tile_height = 32;
+	const int subtile_size = 64;
+	const int owords = 16;
+	int base, _x, _y, subtile, tile_x, tile_y;
+	int x_loc = x << __builtin_ctz(cpp);
+	int pos;
+
+	/* Pixel in tile via masks */
+	tile_x = x_loc & (tile_width - 1);
+	tile_y = y & (tile_height - 1);
+
+	/* subtile in 4k tile */
+	_x = tile_x >> __builtin_ctz(owords);
+	_y = tile_y >> 2;
+
+	/* tile-4 swizzle */
+	subtile = ((_y >> 1) << 4) + ((_y & 1) << 2) + (_x & 3) + ((_x & 4) << 1);
+
+	/* memory location */
+	base = (y >> __builtin_ctz(tile_height)) *
+		(stride << __builtin_ctz(tile_height)) +
+		(((x_loc >> __builtin_ctz(tile_width)) << __builtin_ctz(4096)));
+
+	pos = base + (subtile << __builtin_ctz(subtile_size)) +
+		((tile_y & 3) << __builtin_ctz(owords)) +
+		(tile_x & (owords - 1));
+	igt_assert((pos & (cpp - 1)) == 0);
+	pos = pos >> __builtin_ctz(cpp);
+
+	return ptr + pos;
+}
+
+
 static void *yf_ptr(void *ptr,
 		    unsigned int x, unsigned int y,
 		    unsigned int stride, unsigned int cpp)
@@ -365,6 +415,8 @@ static tile_fn __get_tile_fn_ptr(int tiling)
 	case I915_TILING_Yf:
 		fn = yf_ptr;
 		break;
+	case I915_TILING_4:
+		fn = tile4_ptr;
 	case I915_TILING_Ys:
 		/* To be implemented */
 		break;
@@ -391,7 +443,7 @@ static void __copy_ccs(struct buf_ops *bops, struct intel_buf *buf,
 	void *map;
 	int gen;
 
-	if (!buf->compression)
+	if (!buf->compression || HAS_FLATCCS(intel_get_drm_devid(bops->fd)))
 		return;
 
 	gen = bops->intel_gen;
@@ -551,6 +603,13 @@ static void copy_linear_to_ys(struct buf_ops *bops, struct intel_buf *buf,
 	__copy_linear_to(bops->fd, buf, linear, I915_TILING_Ys, 0);
 }
 
+static void copy_linear_to_tile4(struct buf_ops *bops, struct intel_buf *buf,
+				 uint32_t *linear)
+{
+	DEBUGFN();
+	__copy_linear_to(bops->fd, buf, linear, I915_TILING_4, bops->swizzle_tile4);
+}
+
 static void __copy_to_linear(int fd, struct intel_buf *buf,
 			     uint32_t *linear, int tiling, uint32_t swizzle)
 {
@@ -601,6 +660,13 @@ static void copy_ys_to_linear(struct buf_ops *bops, struct intel_buf *buf,
 	__copy_to_linear(bops->fd, buf, linear, I915_TILING_Ys, 0);
 }
 
+static void copy_tile4_to_linear(struct buf_ops *bops, struct intel_buf *buf,
+				 uint32_t *linear)
+{
+	DEBUGFN();
+	__copy_to_linear(bops->fd, buf, linear, I915_TILING_4, 0);
+}
+
 static void copy_linear_to_gtt(struct buf_ops *bops, struct intel_buf *buf,
 			       uint32_t *linear)
 {
@@ -752,11 +818,10 @@ static void __intel_buf_init(struct buf_ops *bops,
 	IGT_INIT_LIST_HEAD(&buf->link);
 
 	if (compression) {
-		int aux_width, aux_height;
-
 		igt_require(bops->intel_gen >= 9);
 		igt_assert(req_tiling == I915_TILING_Y ||
-			   req_tiling == I915_TILING_Yf);
+			   req_tiling == I915_TILING_Yf ||
+			   req_tiling == I915_TILING_4);
 		/*
 		 * On GEN12+ we align the main surface to 4 * 4 main surface
 		 * tiles, which is 64kB. These 16 tiles are mapped by 4 AUX
@@ -778,13 +843,19 @@ static void __intel_buf_init(struct buf_ops *bops,
 		buf->bpp = bpp;
 		buf->compression = compression;
 
-		aux_width = intel_buf_ccs_width(bops->intel_gen, buf);
-		aux_height = intel_buf_ccs_height(bops->intel_gen, buf);
+		if (!HAS_FLATCCS(intel_get_drm_devid(bops->fd))) {
+			int aux_width, aux_height;
 
-		buf->ccs[0].offset = buf->surface[0].stride * ALIGN(height, 32);
-		buf->ccs[0].stride = aux_width;
+			aux_width = intel_buf_ccs_width(bops->intel_gen, buf);
+			aux_height = intel_buf_ccs_height(bops->intel_gen, buf);
 
-		size = buf->ccs[0].offset + aux_width * aux_height;
+			buf->ccs[0].offset = buf->surface[0].stride * ALIGN(height, 32);
+			buf->ccs[0].stride = aux_width;
+			size = buf->ccs[0].offset + aux_width * aux_height;
+		}
+		else {
+			size = buf->ccs[0].offset;
+		}
 	} else {
 		if (tiling) {
 			devid =  intel_get_drm_devid(bops->fd);
@@ -1176,17 +1247,19 @@ void intel_buf_write_aux_to_png(struct intel_buf *buf, const char *filename)
 #define DEFAULT_BUFOPS(__gen_start, __gen_end) \
 	.gen_start          = __gen_start, \
 	.gen_end            = __gen_end, \
-	.supported_hw_tiles = TILE_X | TILE_Y, \
+	.supported_hw_tiles = TILE_X | TILE_Y | TILE_4, \
 	.linear_to          = copy_linear_to_wc, \
 	.linear_to_x        = copy_linear_to_gtt, \
 	.linear_to_y        = copy_linear_to_gtt, \
 	.linear_to_yf       = copy_linear_to_yf, \
 	.linear_to_ys       = copy_linear_to_ys, \
+	.linear_to_tile4    = copy_linear_to_tile4, \
 	.to_linear          = copy_wc_to_linear, \
 	.x_to_linear        = copy_gtt_to_linear, \
 	.y_to_linear        = copy_gtt_to_linear, \
 	.yf_to_linear       = copy_yf_to_linear, \
-	.ys_to_linear       = copy_ys_to_linear
+	.ys_to_linear       = copy_ys_to_linear, \
+	.tile4_to_linear    = copy_tile4_to_linear
 
 struct buf_ops buf_ops_arr[] = {
 	{
@@ -1201,7 +1274,7 @@ struct buf_ops buf_ops_arr[] = {
 
 	{
 		DEFAULT_BUFOPS(12, 12),
-		.supported_tiles   = TILE_NONE | TILE_X | TILE_Y | TILE_Yf | TILE_Ys,
+		.supported_tiles   = TILE_NONE | TILE_X | TILE_Y | TILE_Yf | TILE_Ys | TILE_4,
 	},
 };
 
@@ -1230,6 +1303,8 @@ static bool probe_hw_tiling(struct buf_ops *bops, uint32_t tiling,
 			bops->swizzle_x = buf_swizzle;
 		else if (tiling == I915_TILING_Y)
 			bops->swizzle_y = buf_swizzle;
+		else if (tiling == I915_TILING_4)
+			bops->swizzle_tile4 = buf_swizzle;
 
 		*swizzling_supported = buf_swizzle == phys_swizzle;
 	}
@@ -1390,6 +1465,24 @@ static struct buf_ops *__buf_ops_create(int fd, bool check_idempotency)
 		}
 	}
 
+	if (is_hw_tiling_supported(bops, I915_TILING_4)) {
+		bool swizzling_supported;
+		bool supported = probe_hw_tiling(bops, I915_TILING_4,
+						 &swizzling_supported);
+
+		if (!swizzling_supported) {
+			igt_debug("Swizzling for 4 is not supported\n");
+			bops->supported_tiles &= ~TILE_4;
+		}
+
+		igt_debug("4 fence support: %s\n", bool_str(supported));
+		if (!supported) {
+			bops->supported_hw_tiles &= ~TILE_4;
+			bops->linear_to_tile4 = copy_linear_to_tile4;
+			bops->tile4_to_linear = copy_tile4_to_linear;
+		}
+	}
+
 	/* Disable other tiling format functions if not supported */
 	if (!is_tiling_supported(bops, I915_TILING_Yf)) {
 		igt_debug("Yf format not supported\n");
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index db75a829..4d9f4623 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -219,6 +219,7 @@ void intel_check_pch(void);
 
 #define HAS_4TILE(devid)	(intel_get_device_info(devid)->has_4tile)
 
-#define HAS_FLATCCS(devid)	(intel_get_device_info(devid)->has_flatccs)
+/* use HAS_4TILE here as all devices with 4-tile have flat ccs. */
+#define HAS_FLATCCS(devid)	HAS_4TILE(devid)
 
 #endif /* _INTEL_CHIPSET_H */
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 6c45efb4..9d7e5b71 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -165,7 +165,8 @@ intel_get_uc_mocs(int fd) {
 
 /* Mostly copy+paste from gen6, except height, width, pitch moved */
 static uint32_t
-gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) {
+gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
+	      bool fast_clear) {
 	struct gen9_surface_state *ss;
 	uint32_t write_domain, read_domain;
 	uint64_t address;
@@ -192,15 +193,26 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) {
 		case 64: ss->ss0.surface_format = SURFACEFORMAT_R16G16B16A16_FLOAT; break;
 		default: igt_assert(0);
 	}
-	ss->ss0.render_cache_read_write = 1;
 	ss->ss0.vertical_alignment = 1; /* align 4 */
-	ss->ss0.horizontal_alignment = 1; /* align 4 */
+	ss->ss0.horizontal_alignment = 1; /* align 4 or HALIGN_32 on display ver >= 13*/
+
+	if (HAS_4TILE(ibb->devid)) {
+		/*
+		 * mocs table version 1 index 3 groub wb use l3
+		 */
+		ss->ss1.memory_object_control = 3 << 1;
+		ss->ss5.mip_tail_start_lod = 0;
+	} else {
+		ss->ss0.render_cache_read_write = 1;
+		ss->ss1.memory_object_control = intel_get_uc_mocs(i915);
+		ss->ss5.mip_tail_start_lod = 1; /* needed with trmode */
+	}
+
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
 	else if (buf->tiling != I915_TILING_NONE)
 		ss->ss0.tiled_mode = 3;
 
-	ss->ss1.memory_object_control = intel_get_uc_mocs(i915);
 	if (intel_buf_pxp(buf))
 		ss->ss1.memory_object_control |= 1;
 
@@ -208,7 +220,6 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) {
 		ss->ss5.trmode = 1;
 	else if (buf->tiling == I915_TILING_Ys)
 		ss->ss5.trmode = 2;
-	ss->ss5.mip_tail_start_lod = 1; /* needed with trmode */
 
 	address = intel_bb_offset_reloc(ibb, buf->handle,
 					read_domain, write_domain,
@@ -229,20 +240,22 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) {
 	if (buf->compression == I915_COMPRESSION_MEDIA)
 		ss->ss7.tgl.media_compression = 1;
 	else if (buf->compression == I915_COMPRESSION_RENDER) {
-		igt_assert(buf->ccs[0].stride);
-
 		ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */
-		ss->ss6.aux_pitch = (buf->ccs[0].stride / 128) - 1;
 
-		address = intel_bb_offset_reloc_with_delta(ibb, buf->handle,
-							   read_domain, write_domain,
-							   (buf->cc.offset ? (1 << 10) : 0) | buf->ccs[0].offset,
-							   intel_bb_offset(ibb) + 4 * 10,
-							   buf->addr.offset);
-		ss->ss10.aux_base_addr = (address + buf->ccs[0].offset) >> 12;
-		ss->ss11.aux_base_addr_hi = (address + buf->ccs[0].offset) >> 32;
+		if (buf->ccs[0].stride) {
+
+			ss->ss6.aux_pitch = (buf->ccs[0].stride / 128) - 1;
+
+			address = intel_bb_offset_reloc_with_delta(ibb, buf->handle,
+								   read_domain, write_domain,
+								   (buf->cc.offset ? (1 << 10) : 0) | buf->ccs[0].offset,
+								   intel_bb_offset(ibb) + 4 * 10,
+								   buf->addr.offset);
+			ss->ss10.aux_base_addr = (address + buf->ccs[0].offset) >> 12;
+			ss->ss11.aux_base_addr_hi = (address + buf->ccs[0].offset) >> 32;
+		}
 
-		if (buf->cc.offset) {
+		if (fast_clear || (buf->cc.offset && !HAS_FLATCCS(ibb->devid))) {
 			igt_assert(buf->compression == I915_COMPRESSION_RENDER);
 
 			ss->ss10.clearvalue_addr_enable = 1;
@@ -252,9 +265,30 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) {
 								   buf->cc.offset,
 								   intel_bb_offset(ibb) + 4 * 12,
 								   buf->addr.offset);
-			ss->ss12.clear_address = address + buf->cc.offset;
-			ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32;
-		}
+
+			/*
+                         * If this assert doesn't hold below clear address will be
+                         * written wrong.
+                         */
+                        igt_assert(__builtin_ctzl(address + buf->cc.offset) >= 6 &&
+                                   (__builtin_clzl(address + buf->cc.offset) >= 16));
+
+                        ss->ss12.clear_address = (address + buf->cc.offset) >> 6;
+                        ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32;
+                } else if (HAS_FLATCCS(ibb->devid)) {
+                        ss->ss7.dg2.memory_compression_type = 0;
+                        ss->ss7.dg2.memory_compression_enable = 0;
+                        ss->ss7.dg2.disable_support_for_multi_gpu_partial_writes = 1;
+                        ss->ss7.dg2.disable_support_for_multi_gpu_atomics = 1;
+
+                        /*
+                         * For now here is coming only 32bpp rgb format
+                         * which is marked below as B8G8R8X8_UNORM = '8'
+                         * If here ever arrive other formats below need to be
+                         * fixed to take that into account.
+                         */
+                        ss->ss12.compression_format = 8;
+                }
 	}
 
 	return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*ss));
@@ -266,14 +300,15 @@ gen8_bind_surfaces(struct intel_bb *ibb,
 		   const struct intel_buf *dst)
 {
 	uint32_t *binding_table, binding_table_offset;
+	bool fast_clear = !src;
 
 	binding_table = intel_bb_ptr_align(ibb, 32);
 	binding_table_offset = intel_bb_ptr_add_return_prev_offset(ibb, 32);
 
-	binding_table[0] = gen8_bind_buf(ibb, dst, 1);
+	binding_table[0] = gen8_bind_buf(ibb, dst, 1, fast_clear);
 
 	if (src != NULL)
-		binding_table[1] = gen8_bind_buf(ibb, src, 0);
+		binding_table[1] = gen8_bind_buf(ibb, src, 0, false);
 
 	return binding_table_offset;
 }
@@ -856,12 +891,14 @@ gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel, bool fast_clear) {
 static void
 gen9_emit_depth(struct intel_bb *ibb)
 {
+	bool need_10dw = HAS_4TILE(ibb->devid);
+
 	intel_bb_out(ibb, GEN8_3DSTATE_WM_DEPTH_STENCIL | (4 - 2));
 	intel_bb_out(ibb, 0);
 	intel_bb_out(ibb, 0);
 	intel_bb_out(ibb, 0);
 
-	intel_bb_out(ibb, GEN7_3DSTATE_DEPTH_BUFFER | (8-2));
+	intel_bb_out(ibb, GEN7_3DSTATE_DEPTH_BUFFER | (need_10dw ? (10-2) : (8-2)));
 	intel_bb_out(ibb, 0);
 	intel_bb_out(ibb, 0);
 	intel_bb_out(ibb, 0);
@@ -869,6 +906,10 @@ gen9_emit_depth(struct intel_bb *ibb)
 	intel_bb_out(ibb, 0);
 	intel_bb_out(ibb, 0);
 	intel_bb_out(ibb, 0);
+	if (need_10dw) {
+		intel_bb_out(ibb, 0);
+		intel_bb_out(ibb, 0);
+	}
 
 	intel_bb_out(ibb, GEN8_3DSTATE_HIER_DEPTH_BUFFER | (5-2));
 	intel_bb_out(ibb, 0);
@@ -1080,7 +1121,7 @@ void _gen9_render_op(struct intel_bb *ibb,
 
 	gen9_emit_state_base_address(ibb);
 
-	if (IS_DG2(ibb->devid) || intel_gen(ibb->devid) > 12) {
+	if (HAS_4TILE(ibb->devid) || intel_gen(ibb->devid) > 12) {
 		intel_bb_out(ibb, GEN4_3DSTATE_BINDING_TABLE_POOL_ALLOC | 2);
 		intel_bb_emit_reloc(ibb, ibb->handle,
 				    I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
@@ -1197,18 +1238,12 @@ void gen12p71_render_copyfunc(struct intel_bb *ibb,
 			      struct intel_buf *dst,
 			      unsigned int dst_x, unsigned int dst_y)
 {
-	struct aux_pgtable_info pgtable_info = { };
-
-	gen12_aux_pgtable_init(&pgtable_info, ibb, src, dst);
-
 	_gen9_render_op(ibb, src, src_x, src_y,
 			width, height, dst, dst_x, dst_y,
-			pgtable_info.pgtable_buf,
+			NULL,
 			NULL,
 			gen12p71_render_copy,
 			sizeof(gen12p71_render_copy));
-
-	gen12_aux_pgtable_cleanup(ibb, &pgtable_info);
 }
 
 void gen12_render_clearfunc(struct intel_bb *ibb,
@@ -1217,16 +1252,24 @@ void gen12_render_clearfunc(struct intel_bb *ibb,
 			    unsigned int width, unsigned int height,
 			    const float clear_color[4])
 {
-	struct aux_pgtable_info pgtable_info = { };
-
-	gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst);
-
-	_gen9_render_op(ibb, NULL, 0, 0,
-		        width, height, dst, dst_x, dst_y,
-		        pgtable_info.pgtable_buf,
-		        clear_color,
-		        gen12_render_copy,
-		        sizeof(gen12_render_copy));
-
-	gen12_aux_pgtable_cleanup(ibb, &pgtable_info);
+	if (!HAS_4TILE(ibb->devid)) {
+		struct aux_pgtable_info pgtable_info = { };
+		gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst);
+
+		_gen9_render_op(ibb, NULL, 0, 0,
+			        width, height, dst, dst_x, dst_y,
+			        pgtable_info.pgtable_buf,
+			        clear_color,
+			        gen12_render_copy,
+			        sizeof(gen12_render_copy));
+
+		gen12_aux_pgtable_cleanup(ibb, &pgtable_info);
+	} else {
+			_gen9_render_op(ibb, NULL, 0, 0,
+					width, height, dst, dst_x, dst_y,
+					NULL,
+					clear_color,
+					gen12p71_render_copy,
+					sizeof(gen12p71_render_copy));
+	}
 }
diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c
index 17564493..7c3ca245 100644
--- a/lib/veboxcopy_gen12.c
+++ b/lib/veboxcopy_gen12.c
@@ -53,19 +53,25 @@ struct vebox_surface_state {
 		uint32_t width:14;
 		uint32_t height:14;
 	} ss2;
-	struct {
+	union {
+		struct {
 #define VEBOX_TILE_WALK_XMAJOR 0
 #define VEBOX_TILE_WALK_YMAJOR 1
-		uint32_t tile_walk:1;
-		uint32_t tiled_surface:1;
-		uint32_t chroma_half_pitch:1;
-		uint32_t surface_pitch:17;
-		uint32_t chroma_interleave:1;
-		uint32_t lsb_packed_enable:1;
-		uint32_t bayer_input_alignment:2;
-		uint32_t bayer_pattern_format:1;
-		uint32_t bayer_pattern_offset:2;
-		uint32_t surface_format:5;
+			uint32_t tile_walk:1;
+			uint32_t tiled_surface:1;
+			uint32_t chroma_half_pitch:1;
+			uint32_t surface_pitch:17;
+			uint32_t chroma_interleave:1;
+			uint32_t lsb_packed_enable:1;
+			uint32_t bayer_input_alignment:2;
+			uint32_t bayer_pattern_format:1;
+			uint32_t bayer_pattern_offset:2;
+			uint32_t surface_format:5;
+		} tgl;
+		struct {
+			uint32_t tile_mode:2;
+			uint32_t pad0:30;
+		} dg2;
 	} ss3;
 	struct {
 		uint32_t u_y_offset:15;
@@ -82,9 +88,15 @@ struct vebox_surface_state {
 		uint32_t frame_x_offset:15;
 		uint32_t pad:2;
 	} ss6;
-	struct {
-		uint32_t derived_surface_pitch:17;
-		uint32_t pad:15;
+	union {
+		struct {
+			uint32_t derived_surface_pitch:17;
+			uint32_t pad:15;
+		} skl;
+		struct {
+			uint32_t pad:27;
+			uint32_t compression_format:5;
+		} dg2;
 	} ss7;
 	struct {
 		uint32_t skin_score_output_surface_pitch:17;
@@ -166,17 +178,46 @@ static void emit_surface_state_cmd(struct intel_bb *ibb,
 	ss->ss2.height = height - 1;
 	ss->ss2.width = width - 1;
 
-	ss->ss3.surface_format = format;
+	ss->ss3.tgl.surface_format = format;
 	if (format_is_interleaved_yuv(format))
-		ss->ss3.chroma_interleave = 1;
-	ss->ss3.surface_pitch = pitch - 1;
-	ss->ss3.tile_walk = (tiling == I915_TILING_Y) ||
-			    (tiling == I915_TILING_Yf);
-	ss->ss3.tiled_surface = tiling != I915_TILING_NONE;
+		ss->ss3.tgl.chroma_interleave = 1;
+	ss->ss3.tgl.surface_pitch = pitch - 1;
 
 	ss->ss4.u_y_offset = uv_offset / pitch;
 
-	ss->ss7.derived_surface_pitch = pitch - 1;
+	if (HAS_FLATCCS(ibb->devid)) {
+                /*
+                 * f-tile = 3 (Tile F)
+                 */
+                ss->ss3.dg2.tile_mode = (tiling != I915_TILING_NONE) ? 3 : 0;
+
+                switch (format) {
+                case R8G8B8A8_UNORM:
+                        ss->ss7.dg2.compression_format = 0xa;
+                        break;
+                case PLANAR_420_8:
+                        ss->ss7.dg2.compression_format = 0xf;
+                        break;
+                case PLANAR_420_16:
+                        ss->ss7.dg2.compression_format = 8;
+                        break;
+                case YCRCB_NORMAL:
+                        ss->ss7.dg2.compression_format = 3;
+                        break;
+                case PACKED_444A_8:
+                        ss->ss7.dg2.compression_format = 0x9;
+                        break;
+                default:
+                        igt_assert(0);
+                }
+        } else {
+                ss->ss3.tgl.tile_walk = (tiling == I915_TILING_Y) ||
+                        (tiling == I915_TILING_Yf) ||
+                        (tiling == I915_TILING_4);
+                ss->ss3.tgl.tiled_surface = tiling != I915_TILING_NONE;
+        }
+
+	ss->ss7.skl.derived_surface_pitch = pitch - 1;
 
 	intel_bb_ptr_add(ibb, sizeof(*ss));
 }
@@ -203,7 +244,11 @@ static void emit_tiling_convert_cmd(struct intel_bb *ibb,
 		tc->tc1_2.input_compression_type =
 			src->compression == I915_COMPRESSION_RENDER;
 	}
-	tc->tc1_2.input_tiled_resource_mode = src->tiling == I915_TILING_Yf;
+
+	if (HAS_4TILE(ibb->devid))
+		tc->tc1_2.input_mocs_idx = 3;
+	else
+		tc->tc1_2.input_tiled_resource_mode = src->tiling == I915_TILING_Yf;
 	reloc_delta = tc->tc1_2_l;
 
 	igt_assert(src->addr.offset == ALIGN(src->addr.offset, 0x1000));
@@ -220,7 +265,12 @@ static void emit_tiling_convert_cmd(struct intel_bb *ibb,
 		tc->tc3_4.output_compression_type =
 			dst->compression == I915_COMPRESSION_RENDER;
 	}
-	tc->tc3_4.output_tiled_resource_mode = dst->tiling == I915_TILING_Yf;
+
+	if (HAS_4TILE(ibb->devid))
+		tc->tc3_4.output_mocs_idx = 3;
+	else
+		tc->tc3_4.output_tiled_resource_mode = dst->tiling == I915_TILING_Yf;
+
 	reloc_delta = tc->tc3_4_l;
 
 	igt_assert(dst->addr.offset == ALIGN(dst->addr.offset, 0x1000));
@@ -255,10 +305,12 @@ void gen12_vebox_copyfunc(struct intel_bb *ibb,
 	intel_bb_add_intel_buf(ibb, dst, true);
 	intel_bb_add_intel_buf(ibb, src, false);
 
-	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
-	gen12_aux_pgtable_init(&aux_pgtable_info, ibb, src, dst);
-	aux_pgtable_state = gen12_create_aux_pgtable_state(ibb,
-							   aux_pgtable_info.pgtable_buf);
+	if (!HAS_FLATCCS(ibb->devid)) {
+		intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
+		gen12_aux_pgtable_init(&aux_pgtable_info, ibb, src, dst);
+		aux_pgtable_state = gen12_create_aux_pgtable_state(ibb,
+								   aux_pgtable_info.pgtable_buf);
+	}
 
 	intel_bb_ptr_set(ibb, 0);
 	gen12_emit_aux_pgtable_state(ibb, aux_pgtable_state, false);
@@ -311,5 +363,6 @@ void gen12_vebox_copyfunc(struct intel_bb *ibb,
 
 	intel_bb_reset(ibb, false);
 
-	gen12_aux_pgtable_cleanup(ibb, &aux_pgtable_info);
+	if (!HAS_FLATCCS(ibb->devid))
+		gen12_aux_pgtable_cleanup(ibb, &aux_pgtable_info);
 }
-- 
2.35.1

Re: [igt-dev] [PATCH i-g-t v2 2/4] lib/DG2: create flat ccs framebuffers with 4-tile

[Kahola, Mika]

> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Jeevan B
> Sent: Wednesday, April 20, 2022 1:39 PM
> To: igt-dev@lists.freedesktop.org
> Cc: Heikkila, Juha-pekka <juha-pekka.heikkila@intel.com>
> Subject: [igt-dev] [PATCH i-g-t v2 2/4] lib/DG2: create flat ccs framebuffers with
> 4-tile
> 
> From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> 
> Add support for DG2 flat ccs framebuffers with tile-4.
> 
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  lib/gen9_render.h       |  40 ++++++++++---
>  lib/igt_fb.c            |  49 ++++++++++++----
>  lib/intel_aux_pgtable.c |   6 +-
>  lib/intel_batchbuffer.c |   2 +-
>  lib/intel_bufops.c      | 119 +++++++++++++++++++++++++++++++++----
>  lib/intel_chipset.h     |   3 +-
>  lib/rendercopy_gen9.c   | 127 +++++++++++++++++++++++++++-------------
>  lib/veboxcopy_gen12.c   | 109 +++++++++++++++++++++++++---------
>  8 files changed, 348 insertions(+), 107 deletions(-)
> 
> diff --git a/lib/gen9_render.h b/lib/gen9_render.h index 06d9718c..82a9f99c
> 100644
> --- a/lib/gen9_render.h
> +++ b/lib/gen9_render.h
> @@ -59,9 +59,15 @@ struct gen9_surface_state {
>  		uint32_t depth:11;
>  	} ss3;
> 
> -	struct {
> -		uint32_t minimum_array_element:27;
> -		uint32_t pad0:5;
> +	union {
> +		struct {
> +			uint32_t minimum_array_element:27;
> +			uint32_t pad0:5;
> +		} skl;
> +		struct {
> +			uint32_t decompress_in_l3:1;
> +			uint32_t pad0:31;
> +		} dg2;
>  	} ss4;
> 
>  	struct {
> @@ -116,6 +122,15 @@ struct gen9_surface_state {
>  			uint32_t media_compression:1;
>  			uint32_t pad2:1;
>  		} tgl;
> +
> +		struct {
> +			uint32_t pad0:14;
> +			uint32_t
> disable_support_for_multi_gpu_partial_writes:1;
> +			uint32_t disable_support_for_multi_gpu_atomics:1;
> +			uint32_t pad1:14;
> +			uint32_t memory_compression_enable:1;
> +			uint32_t memory_compression_type:1;
> +		} dg2;
>  	} ss7;
> 
>  	struct {
> @@ -138,15 +153,22 @@ struct gen9_surface_state {
>  		uint32_t aux_base_addr_hi;
>  	} ss11;
> 
> -	/* register can be used for either
> -	 * clear value or depth clear value
> -	 */
>  	struct {
> -		uint32_t clear_address;
> -	} ss12;
> +		/*
> +		 * compression_format is used only dg2 onward.
> +		 * prior to dg2 full ss12 is used for the address
> +		 * but due to alignments bits 0..6 will be zero
> +		 * and asserted in code to be so
> +		 */
> +		uint32_t compression_format:5;
> +		uint32_t pad0:1;
> +		uint32_t clear_address:26;
> +        } ss12;
> 
>  	struct {
> -		uint32_t clear_address_hi;
> +		uint32_t clear_address_hi:16;
> +		uint32_t pad0:16;
> +
>  	} ss13;
> 
>  	struct {
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c index eafbe7fd..93e98733 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -457,6 +457,9 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int
> fb_bpp,
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  	case I915_FORMAT_MOD_4_TILED:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>  		igt_require_intel(fd);
>  		if (intel_display_ver(intel_get_drm_devid(fd)) == 2) {
>  			*width_ret = 128;
> @@ -565,14 +568,17 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int
> fb_bpp,
> 
>  static bool is_gen12_mc_ccs_modifier(uint64_t modifier)  {
> -	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
>  }
> 
>  static bool is_gen12_ccs_modifier(uint64_t modifier)  {
>  	return is_gen12_mc_ccs_modifier(modifier) ||
>  		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> -		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
> +		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> ||
> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS ||
> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
>  }
> 
>  static bool is_ccs_modifier(uint64_t modifier) @@ -584,7 +590,7 @@ static
> bool is_ccs_modifier(uint64_t modifier)
> 
>  static bool is_ccs_plane(const struct igt_fb *fb, int plane)  {
> -	if (!is_ccs_modifier(fb->modifier))
> +	if (!is_ccs_modifier(fb->modifier) ||
> +HAS_FLATCCS(intel_get_drm_devid(fb->fd)))
>  		return false;
> 
>  	return plane >= fb->num_planes / 2;
> @@ -602,8 +608,15 @@ static bool is_gen12_ccs_plane(const struct igt_fb *fb,
> int plane)
> 
>  static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)  {
> -	return fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
> -	       plane == 2;
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> &&
> +	    plane == 2)
> +		return true;
> +
> +	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC &&
> +            plane == 1)
> +		return true;
> +
> +	return false;
>  }
> 
>  bool igt_fb_is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane) @@ -
> 689,7 +702,8 @@ static int fb_num_planes(const struct igt_fb *fb)
>  	if (is_ccs_modifier(fb->modifier))
>  		num_planes *= 2;
> 
> -	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> ||
> +	    fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
>  		num_planes++;
> 
>  	return num_planes;
> @@ -763,7 +777,7 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int
> plane)
>  		return ALIGN(min_stride, tile_width);
>  	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
>  		/* clear color always fixed to 64 bytes */
> -		return 64;
> +		return HAS_FLATCCS(intel_get_drm_devid(fb->fd)) ? 512 : 64;
>  	} else if (is_gen12_ccs_plane(fb, plane)) {
>  		/*
>  		 * The CCS surface stride is
> @@ -966,6 +980,9 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return I915_TILING_Y;
>  	case I915_FORMAT_MOD_4_TILED:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>  		return I915_TILING_4;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -2504,9 +2521,10 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
>  	if (is_ccs_modifier(fb->modifier)) {
>  		igt_assert_eq(fb->strides[0] & 127, 0);
> 
> -		if (is_gen12_ccs_modifier(fb->modifier))
> -			igt_assert_eq(fb->strides[1] & 63, 0);
> -		else
> +		if (is_gen12_ccs_modifier(fb->modifier)) {
> +			if (!HAS_FLATCCS(intel_get_drm_devid(fb->fd)))
> +				igt_assert_eq(fb->strides[1] & 63, 0);
> +		} else
>  			igt_assert_eq(fb->strides[1] & 127, 0);
> 
>  		if (is_gen12_mc_ccs_modifier(fb->modifier))
> @@ -2539,7 +2557,7 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
>  		buf->yuv_semiplanar_bpp = yuv_semiplanar_bpp(fb-
> >drm_format);
> 
>  	if (is_ccs_modifier(fb->modifier)) {
> -		num_surfaces = fb->num_planes / 2;
> +		num_surfaces = fb->num_planes /
> +(HAS_FLATCCS(intel_get_drm_devid(fb->fd)) ? 1 : 2);
>  		for (i = 0; i < num_surfaces; i++)
>  			init_buf_ccs(buf, i,
>  				     fb->offsets[num_surfaces + i], @@ -2560,6
> +2578,9 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
>  	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
>  		buf->cc.offset = fb->offsets[2];
> 
> +	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
> +		buf->cc.offset = fb->offsets[1];
> +
>  	return buf;
>  }
> 
> @@ -4570,6 +4591,12 @@ const char *igt_fb_modifier_name(uint64_t
> modifier)
>  		return "Y-MC_CCS";
>  	case I915_FORMAT_MOD_4_TILED:
>  		return "4";
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +		return "4-RC_CCS";
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> +		return "4-MC_CCS";
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> +		return "4-RC_CCS-CC";
>  	default:
>  		return "?";
>  	}
> diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index
> f5796fdf..e31a6c34 100644
> --- a/lib/intel_aux_pgtable.c
> +++ b/lib/intel_aux_pgtable.c
> @@ -263,7 +263,8 @@ static uint64_t pgt_get_l1_flags(const struct intel_buf
> *buf, int surface_idx)
>  	} entry = {
>  		.e = {
>  			.valid = 1,
> -			.tile_mode = buf->tiling == I915_TILING_Y ? 1 : 0,
> +			.tile_mode = buf->tiling == I915_TILING_Y ? 1 :
> +				(buf->tiling == I915_TILING_4 ? 2 : 0),
>  		}
>  	};
> 
> @@ -274,7 +275,8 @@ static uint64_t pgt_get_l1_flags(const struct intel_buf
> *buf, int surface_idx)
>  	 */
>  	igt_assert(buf->tiling == I915_TILING_Y ||
>  		   buf->tiling == I915_TILING_Yf ||
> -		   buf->tiling == I915_TILING_Ys);
> +		   buf->tiling == I915_TILING_Ys ||
> +		   buf->tiling == I915_TILING_4);
> 
>  	entry.e.ycr = surface_idx > 0;
> 
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index
> ebf3c598..81d2e140 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -1146,7 +1146,7 @@ igt_render_copyfunc_t igt_get_render_copyfunc(int
> devid)
>  		copy = gen9_render_copyfunc;
>  	else if (IS_GEN11(devid))
>  		copy = gen11_render_copyfunc;
> -	else if (IS_DG2(devid))
> +	else if (HAS_4TILE(devid))
>  		copy = gen12p71_render_copyfunc;
>  	else if (IS_GEN12(devid))
>  		copy = gen12_render_copyfunc;
> diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c index f13063fa..72b1bafa
> 100644
> --- a/lib/intel_bufops.c
> +++ b/lib/intel_bufops.c
> @@ -89,6 +89,7 @@
>  #define TILE_Y      TILE_DEF(I915_TILING_Y)
>  #define TILE_Yf     TILE_DEF(I915_TILING_Yf)
>  #define TILE_Ys     TILE_DEF(I915_TILING_Ys)
> +#define TILE_4      TILE_DEF(I915_TILING_4)
> 
>  #define CCS_OFFSET(buf) (buf->ccs[0].offset)  #define CCS_SIZE(gen, buf) \ @@
> -105,16 +106,19 @@ struct buf_ops {
>  	uint32_t supported_hw_tiles;
>  	uint32_t swizzle_x;
>  	uint32_t swizzle_y;
> +	uint32_t swizzle_tile4;
>  	bo_copy linear_to;
>  	bo_copy linear_to_x;
>  	bo_copy linear_to_y;
>  	bo_copy linear_to_yf;
>  	bo_copy linear_to_ys;
> +	bo_copy linear_to_tile4;
>  	bo_copy to_linear;
>  	bo_copy x_to_linear;
>  	bo_copy y_to_linear;
>  	bo_copy yf_to_linear;
>  	bo_copy ys_to_linear;
> +	bo_copy tile4_to_linear;
>  };
> 
>  static const char *tiling_str(uint32_t tiling) @@ -125,6 +129,7 @@ static const
> char *tiling_str(uint32_t tiling)
>  	case I915_TILING_Y:    return "Y";
>  	case I915_TILING_Yf:   return "Yf";
>  	case I915_TILING_Ys:   return "Ys";
> +	case I915_TILING_4:    return "4";
>  	default:               return "UNKNOWN";
>  	}
>  }
> @@ -222,7 +227,8 @@ static void set_hw_tiled(struct buf_ops *bops, struct
> intel_buf *buf)  {
>  	uint32_t ret_tiling, ret_swizzle;
> 
> -	if (buf->tiling != I915_TILING_X && buf->tiling != I915_TILING_Y)
> +	if (buf->tiling != I915_TILING_X && buf->tiling != I915_TILING_Y &&
> +	    buf->tiling != I915_TILING_4)
>  		return;
> 
>  	if (!buf_ops_has_hw_fence(bops, buf->tiling)) { @@ -320,6 +326,50
> @@ static void *y_ptr(void *ptr,
>  	return ptr + pos;
>  }
> 
> +/*
> + * (x,y) to memory location in tiled-4 surface
> + *
> + * coverted those divisions and multiplications to shifts and masks
> + * in hope this wouldn't be so slow.
> + */
> +static void *tile4_ptr(void *ptr,
> +			unsigned int x, unsigned int y,
> +			unsigned int stride, unsigned int cpp) {
> +	const int tile_width = 128;
> +	const int tile_height = 32;
> +	const int subtile_size = 64;
> +	const int owords = 16;
> +	int base, _x, _y, subtile, tile_x, tile_y;
> +	int x_loc = x << __builtin_ctz(cpp);
> +	int pos;
> +
> +	/* Pixel in tile via masks */
> +	tile_x = x_loc & (tile_width - 1);
> +	tile_y = y & (tile_height - 1);
> +
> +	/* subtile in 4k tile */
> +	_x = tile_x >> __builtin_ctz(owords);
> +	_y = tile_y >> 2;
> +
> +	/* tile-4 swizzle */
> +	subtile = ((_y >> 1) << 4) + ((_y & 1) << 2) + (_x & 3) + ((_x & 4) <<
> +1);
> +
> +	/* memory location */
> +	base = (y >> __builtin_ctz(tile_height)) *
> +		(stride << __builtin_ctz(tile_height)) +
> +		(((x_loc >> __builtin_ctz(tile_width)) << __builtin_ctz(4096)));
> +
> +	pos = base + (subtile << __builtin_ctz(subtile_size)) +
> +		((tile_y & 3) << __builtin_ctz(owords)) +
> +		(tile_x & (owords - 1));
> +	igt_assert((pos & (cpp - 1)) == 0);
> +	pos = pos >> __builtin_ctz(cpp);
> +
> +	return ptr + pos;
> +}
> +
> +
>  static void *yf_ptr(void *ptr,
>  		    unsigned int x, unsigned int y,
>  		    unsigned int stride, unsigned int cpp) @@ -365,6 +415,8 @@
> static tile_fn __get_tile_fn_ptr(int tiling)
>  	case I915_TILING_Yf:
>  		fn = yf_ptr;
>  		break;
> +	case I915_TILING_4:
> +		fn = tile4_ptr;
>  	case I915_TILING_Ys:
>  		/* To be implemented */
>  		break;
> @@ -391,7 +443,7 @@ static void __copy_ccs(struct buf_ops *bops, struct
> intel_buf *buf,
>  	void *map;
>  	int gen;
> 
> -	if (!buf->compression)
> +	if (!buf->compression || HAS_FLATCCS(intel_get_drm_devid(bops->fd)))
>  		return;
> 
>  	gen = bops->intel_gen;
> @@ -551,6 +603,13 @@ static void copy_linear_to_ys(struct buf_ops *bops,
> struct intel_buf *buf,
>  	__copy_linear_to(bops->fd, buf, linear, I915_TILING_Ys, 0);  }
> 
> +static void copy_linear_to_tile4(struct buf_ops *bops, struct intel_buf *buf,
> +				 uint32_t *linear)
> +{
> +	DEBUGFN();
> +	__copy_linear_to(bops->fd, buf, linear, I915_TILING_4,
> +bops->swizzle_tile4); }
> +
>  static void __copy_to_linear(int fd, struct intel_buf *buf,
>  			     uint32_t *linear, int tiling, uint32_t swizzle)  { @@ -
> 601,6 +660,13 @@ static void copy_ys_to_linear(struct buf_ops *bops, struct
> intel_buf *buf,
>  	__copy_to_linear(bops->fd, buf, linear, I915_TILING_Ys, 0);  }
> 
> +static void copy_tile4_to_linear(struct buf_ops *bops, struct intel_buf *buf,
> +				 uint32_t *linear)
> +{
> +	DEBUGFN();
> +	__copy_to_linear(bops->fd, buf, linear, I915_TILING_4, 0); }
> +
>  static void copy_linear_to_gtt(struct buf_ops *bops, struct intel_buf *buf,
>  			       uint32_t *linear)
>  {
> @@ -752,11 +818,10 @@ static void __intel_buf_init(struct buf_ops *bops,
>  	IGT_INIT_LIST_HEAD(&buf->link);
> 
>  	if (compression) {
> -		int aux_width, aux_height;
> -
>  		igt_require(bops->intel_gen >= 9);
>  		igt_assert(req_tiling == I915_TILING_Y ||
> -			   req_tiling == I915_TILING_Yf);
> +			   req_tiling == I915_TILING_Yf ||
> +			   req_tiling == I915_TILING_4);
>  		/*
>  		 * On GEN12+ we align the main surface to 4 * 4 main surface
>  		 * tiles, which is 64kB. These 16 tiles are mapped by 4 AUX @@ -
> 778,13 +843,19 @@ static void __intel_buf_init(struct buf_ops *bops,
>  		buf->bpp = bpp;
>  		buf->compression = compression;
> 
> -		aux_width = intel_buf_ccs_width(bops->intel_gen, buf);
> -		aux_height = intel_buf_ccs_height(bops->intel_gen, buf);
> +		if (!HAS_FLATCCS(intel_get_drm_devid(bops->fd))) {
> +			int aux_width, aux_height;
> 
> -		buf->ccs[0].offset = buf->surface[0].stride * ALIGN(height, 32);
> -		buf->ccs[0].stride = aux_width;
> +			aux_width = intel_buf_ccs_width(bops->intel_gen, buf);
> +			aux_height = intel_buf_ccs_height(bops->intel_gen,
> buf);
> 
> -		size = buf->ccs[0].offset + aux_width * aux_height;
> +			buf->ccs[0].offset = buf->surface[0].stride *
> ALIGN(height, 32);
> +			buf->ccs[0].stride = aux_width;
> +			size = buf->ccs[0].offset + aux_width * aux_height;
> +		}
> +		else {
> +			size = buf->ccs[0].offset;
> +		}
>  	} else {
>  		if (tiling) {
>  			devid =  intel_get_drm_devid(bops->fd); @@ -1176,17
> +1247,19 @@ void intel_buf_write_aux_to_png(struct intel_buf *buf, const
> char *filename)  #define DEFAULT_BUFOPS(__gen_start, __gen_end) \
>  	.gen_start          = __gen_start, \
>  	.gen_end            = __gen_end, \
> -	.supported_hw_tiles = TILE_X | TILE_Y, \
> +	.supported_hw_tiles = TILE_X | TILE_Y | TILE_4, \
>  	.linear_to          = copy_linear_to_wc, \
>  	.linear_to_x        = copy_linear_to_gtt, \
>  	.linear_to_y        = copy_linear_to_gtt, \
>  	.linear_to_yf       = copy_linear_to_yf, \
>  	.linear_to_ys       = copy_linear_to_ys, \
> +	.linear_to_tile4    = copy_linear_to_tile4, \
>  	.to_linear          = copy_wc_to_linear, \
>  	.x_to_linear        = copy_gtt_to_linear, \
>  	.y_to_linear        = copy_gtt_to_linear, \
>  	.yf_to_linear       = copy_yf_to_linear, \
> -	.ys_to_linear       = copy_ys_to_linear
> +	.ys_to_linear       = copy_ys_to_linear, \
> +	.tile4_to_linear    = copy_tile4_to_linear
> 
>  struct buf_ops buf_ops_arr[] = {
>  	{
> @@ -1201,7 +1274,7 @@ struct buf_ops buf_ops_arr[] = {
> 
>  	{
>  		DEFAULT_BUFOPS(12, 12),
> -		.supported_tiles   = TILE_NONE | TILE_X | TILE_Y | TILE_Yf |
> TILE_Ys,
> +		.supported_tiles   = TILE_NONE | TILE_X | TILE_Y | TILE_Yf |
> TILE_Ys | TILE_4,
>  	},
>  };
> 
> @@ -1230,6 +1303,8 @@ static bool probe_hw_tiling(struct buf_ops *bops,
> uint32_t tiling,
>  			bops->swizzle_x = buf_swizzle;
>  		else if (tiling == I915_TILING_Y)
>  			bops->swizzle_y = buf_swizzle;
> +		else if (tiling == I915_TILING_4)
> +			bops->swizzle_tile4 = buf_swizzle;
> 
>  		*swizzling_supported = buf_swizzle == phys_swizzle;
>  	}
> @@ -1390,6 +1465,24 @@ static struct buf_ops *__buf_ops_create(int fd, bool
> check_idempotency)
>  		}
>  	}
> 
> +	if (is_hw_tiling_supported(bops, I915_TILING_4)) {
> +		bool swizzling_supported;
> +		bool supported = probe_hw_tiling(bops, I915_TILING_4,
> +						 &swizzling_supported);
> +
> +		if (!swizzling_supported) {
> +			igt_debug("Swizzling for 4 is not supported\n");
> +			bops->supported_tiles &= ~TILE_4;
> +		}
> +
> +		igt_debug("4 fence support: %s\n", bool_str(supported));
> +		if (!supported) {
> +			bops->supported_hw_tiles &= ~TILE_4;
> +			bops->linear_to_tile4 = copy_linear_to_tile4;
> +			bops->tile4_to_linear = copy_tile4_to_linear;
> +		}
> +	}
> +
>  	/* Disable other tiling format functions if not supported */
>  	if (!is_tiling_supported(bops, I915_TILING_Yf)) {
>  		igt_debug("Yf format not supported\n"); diff --git
> a/lib/intel_chipset.h b/lib/intel_chipset.h index db75a829..4d9f4623 100644
> --- a/lib/intel_chipset.h
> +++ b/lib/intel_chipset.h
> @@ -219,6 +219,7 @@ void intel_check_pch(void);
> 
>  #define HAS_4TILE(devid)	(intel_get_device_info(devid)->has_4tile)
> 
> -#define HAS_FLATCCS(devid)	(intel_get_device_info(devid)->has_flatccs)
> +/* use HAS_4TILE here as all devices with 4-tile have flat ccs. */
> +#define HAS_FLATCCS(devid)	HAS_4TILE(devid)
> 
>  #endif /* _INTEL_CHIPSET_H */
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index
> 6c45efb4..9d7e5b71 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -165,7 +165,8 @@ intel_get_uc_mocs(int fd) {
> 
>  /* Mostly copy+paste from gen6, except height, width, pitch moved */  static
> uint32_t -gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int
> is_dst) {
> +gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
> +	      bool fast_clear) {
>  	struct gen9_surface_state *ss;
>  	uint32_t write_domain, read_domain;
>  	uint64_t address;
> @@ -192,15 +193,26 @@ gen8_bind_buf(struct intel_bb *ibb, const struct
> intel_buf *buf, int is_dst) {
>  		case 64: ss->ss0.surface_format =
> SURFACEFORMAT_R16G16B16A16_FLOAT; break;
>  		default: igt_assert(0);
>  	}
> -	ss->ss0.render_cache_read_write = 1;
>  	ss->ss0.vertical_alignment = 1; /* align 4 */
> -	ss->ss0.horizontal_alignment = 1; /* align 4 */
> +	ss->ss0.horizontal_alignment = 1; /* align 4 or HALIGN_32 on display
> +ver >= 13*/
> +
> +	if (HAS_4TILE(ibb->devid)) {
> +		/*
> +		 * mocs table version 1 index 3 groub wb use l3
> +		 */
> +		ss->ss1.memory_object_control = 3 << 1;
> +		ss->ss5.mip_tail_start_lod = 0;
> +	} else {
> +		ss->ss0.render_cache_read_write = 1;
> +		ss->ss1.memory_object_control = intel_get_uc_mocs(i915);
> +		ss->ss5.mip_tail_start_lod = 1; /* needed with trmode */
> +	}
> +
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
>  	else if (buf->tiling != I915_TILING_NONE)
>  		ss->ss0.tiled_mode = 3;
> 
> -	ss->ss1.memory_object_control = intel_get_uc_mocs(i915);
>  	if (intel_buf_pxp(buf))
>  		ss->ss1.memory_object_control |= 1;
> 
> @@ -208,7 +220,6 @@ gen8_bind_buf(struct intel_bb *ibb, const struct
> intel_buf *buf, int is_dst) {
>  		ss->ss5.trmode = 1;
>  	else if (buf->tiling == I915_TILING_Ys)
>  		ss->ss5.trmode = 2;
> -	ss->ss5.mip_tail_start_lod = 1; /* needed with trmode */
> 
>  	address = intel_bb_offset_reloc(ibb, buf->handle,
>  					read_domain, write_domain,
> @@ -229,20 +240,22 @@ gen8_bind_buf(struct intel_bb *ibb, const struct
> intel_buf *buf, int is_dst) {
>  	if (buf->compression == I915_COMPRESSION_MEDIA)
>  		ss->ss7.tgl.media_compression = 1;
>  	else if (buf->compression == I915_COMPRESSION_RENDER) {
> -		igt_assert(buf->ccs[0].stride);
> -
>  		ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */
> -		ss->ss6.aux_pitch = (buf->ccs[0].stride / 128) - 1;
> 
> -		address = intel_bb_offset_reloc_with_delta(ibb, buf->handle,
> -							   read_domain,
> write_domain,
> -							   (buf->cc.offset ? (1
> << 10) : 0) | buf->ccs[0].offset,
> -							   intel_bb_offset(ibb)
> + 4 * 10,
> -							   buf->addr.offset);
> -		ss->ss10.aux_base_addr = (address + buf->ccs[0].offset) >> 12;
> -		ss->ss11.aux_base_addr_hi = (address + buf->ccs[0].offset) >>
> 32;
> +		if (buf->ccs[0].stride) {
> +
> +			ss->ss6.aux_pitch = (buf->ccs[0].stride / 128) - 1;
> +
> +			address = intel_bb_offset_reloc_with_delta(ibb, buf-
> >handle,
> +
> read_domain, write_domain,
> +								   (buf-
> >cc.offset ? (1 << 10) : 0) | buf->ccs[0].offset,
> +
> intel_bb_offset(ibb) + 4 * 10,
> +								   buf-
> >addr.offset);
> +			ss->ss10.aux_base_addr = (address + buf-
> >ccs[0].offset) >> 12;
> +			ss->ss11.aux_base_addr_hi = (address + buf-
> >ccs[0].offset) >> 32;
> +		}
> 
> -		if (buf->cc.offset) {
> +		if (fast_clear || (buf->cc.offset && !HAS_FLATCCS(ibb->devid)))
> {
>  			igt_assert(buf->compression ==
> I915_COMPRESSION_RENDER);
> 
>  			ss->ss10.clearvalue_addr_enable = 1; @@ -252,9
> +265,30 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int
> is_dst) {
>  								   buf-
> >cc.offset,
> 
> intel_bb_offset(ibb) + 4 * 12,
>  								   buf-
> >addr.offset);
> -			ss->ss12.clear_address = address + buf->cc.offset;
> -			ss->ss13.clear_address_hi = (address + buf->cc.offset)
> >> 32;
> -		}
> +
> +			/*
> +                         * If this assert doesn't hold below clear address will be
> +                         * written wrong.
> +                         */
> +                        igt_assert(__builtin_ctzl(address + buf->cc.offset) >= 6 &&
> +                                   (__builtin_clzl(address +
> +buf->cc.offset) >= 16));
> +
> +                        ss->ss12.clear_address = (address + buf->cc.offset) >> 6;
> +                        ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32;
> +                } else if (HAS_FLATCCS(ibb->devid)) {
> +                        ss->ss7.dg2.memory_compression_type = 0;
> +                        ss->ss7.dg2.memory_compression_enable = 0;
> +                        ss->ss7.dg2.disable_support_for_multi_gpu_partial_writes = 1;
> +
> + ss->ss7.dg2.disable_support_for_multi_gpu_atomics = 1;
> +
> +                        /*
> +                         * For now here is coming only 32bpp rgb format
> +                         * which is marked below as B8G8R8X8_UNORM = '8'
> +                         * If here ever arrive other formats below need to be
> +                         * fixed to take that into account.
> +                         */
> +                        ss->ss12.compression_format = 8;
> +                }
>  	}
> 
>  	return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*ss)); @@ -
> 266,14 +300,15 @@ gen8_bind_surfaces(struct intel_bb *ibb,
>  		   const struct intel_buf *dst)
>  {
>  	uint32_t *binding_table, binding_table_offset;
> +	bool fast_clear = !src;
> 
>  	binding_table = intel_bb_ptr_align(ibb, 32);
>  	binding_table_offset = intel_bb_ptr_add_return_prev_offset(ibb, 32);
> 
> -	binding_table[0] = gen8_bind_buf(ibb, dst, 1);
> +	binding_table[0] = gen8_bind_buf(ibb, dst, 1, fast_clear);
> 
>  	if (src != NULL)
> -		binding_table[1] = gen8_bind_buf(ibb, src, 0);
> +		binding_table[1] = gen8_bind_buf(ibb, src, 0, false);
> 
>  	return binding_table_offset;
>  }
> @@ -856,12 +891,14 @@ gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel,
> bool fast_clear) {  static void  gen9_emit_depth(struct intel_bb *ibb)  {
> +	bool need_10dw = HAS_4TILE(ibb->devid);
> +
>  	intel_bb_out(ibb, GEN8_3DSTATE_WM_DEPTH_STENCIL | (4 - 2));
>  	intel_bb_out(ibb, 0);
>  	intel_bb_out(ibb, 0);
>  	intel_bb_out(ibb, 0);
> 
> -	intel_bb_out(ibb, GEN7_3DSTATE_DEPTH_BUFFER | (8-2));
> +	intel_bb_out(ibb, GEN7_3DSTATE_DEPTH_BUFFER | (need_10dw ? (10-
> 2) :
> +(8-2)));
>  	intel_bb_out(ibb, 0);
>  	intel_bb_out(ibb, 0);
>  	intel_bb_out(ibb, 0);
> @@ -869,6 +906,10 @@ gen9_emit_depth(struct intel_bb *ibb)
>  	intel_bb_out(ibb, 0);
>  	intel_bb_out(ibb, 0);
>  	intel_bb_out(ibb, 0);
> +	if (need_10dw) {
> +		intel_bb_out(ibb, 0);
> +		intel_bb_out(ibb, 0);
> +	}
> 
>  	intel_bb_out(ibb, GEN8_3DSTATE_HIER_DEPTH_BUFFER | (5-2));
>  	intel_bb_out(ibb, 0);
> @@ -1080,7 +1121,7 @@ void _gen9_render_op(struct intel_bb *ibb,
> 
>  	gen9_emit_state_base_address(ibb);
> 
> -	if (IS_DG2(ibb->devid) || intel_gen(ibb->devid) > 12) {
> +	if (HAS_4TILE(ibb->devid) || intel_gen(ibb->devid) > 12) {
>  		intel_bb_out(ibb,
> GEN4_3DSTATE_BINDING_TABLE_POOL_ALLOC | 2);
>  		intel_bb_emit_reloc(ibb, ibb->handle,
>  				    I915_GEM_DOMAIN_RENDER |
> I915_GEM_DOMAIN_INSTRUCTION, 0, @@ -1197,18 +1238,12 @@ void
> gen12p71_render_copyfunc(struct intel_bb *ibb,
>  			      struct intel_buf *dst,
>  			      unsigned int dst_x, unsigned int dst_y)  {
> -	struct aux_pgtable_info pgtable_info = { };
> -
> -	gen12_aux_pgtable_init(&pgtable_info, ibb, src, dst);
> -
>  	_gen9_render_op(ibb, src, src_x, src_y,
>  			width, height, dst, dst_x, dst_y,
> -			pgtable_info.pgtable_buf,
> +			NULL,
>  			NULL,
>  			gen12p71_render_copy,
>  			sizeof(gen12p71_render_copy));
> -
> -	gen12_aux_pgtable_cleanup(ibb, &pgtable_info);
>  }
> 
>  void gen12_render_clearfunc(struct intel_bb *ibb, @@ -1217,16 +1252,24 @@
> void gen12_render_clearfunc(struct intel_bb *ibb,
>  			    unsigned int width, unsigned int height,
>  			    const float clear_color[4])
>  {
> -	struct aux_pgtable_info pgtable_info = { };
> -
> -	gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst);
> -
> -	_gen9_render_op(ibb, NULL, 0, 0,
> -		        width, height, dst, dst_x, dst_y,
> -		        pgtable_info.pgtable_buf,
> -		        clear_color,
> -		        gen12_render_copy,
> -		        sizeof(gen12_render_copy));
> -
> -	gen12_aux_pgtable_cleanup(ibb, &pgtable_info);
> +	if (!HAS_4TILE(ibb->devid)) {
> +		struct aux_pgtable_info pgtable_info = { };
> +		gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst);
> +
> +		_gen9_render_op(ibb, NULL, 0, 0,
> +			        width, height, dst, dst_x, dst_y,
> +			        pgtable_info.pgtable_buf,
> +			        clear_color,
> +			        gen12_render_copy,
> +			        sizeof(gen12_render_copy));
> +
> +		gen12_aux_pgtable_cleanup(ibb, &pgtable_info);
> +	} else {
> +			_gen9_render_op(ibb, NULL, 0, 0,
> +					width, height, dst, dst_x, dst_y,
> +					NULL,
> +					clear_color,
> +					gen12p71_render_copy,
> +					sizeof(gen12p71_render_copy));
> +	}
>  }
> diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c index
> 17564493..7c3ca245 100644
> --- a/lib/veboxcopy_gen12.c
> +++ b/lib/veboxcopy_gen12.c
> @@ -53,19 +53,25 @@ struct vebox_surface_state {
>  		uint32_t width:14;
>  		uint32_t height:14;
>  	} ss2;
> -	struct {
> +	union {
> +		struct {
>  #define VEBOX_TILE_WALK_XMAJOR 0
>  #define VEBOX_TILE_WALK_YMAJOR 1
> -		uint32_t tile_walk:1;
> -		uint32_t tiled_surface:1;
> -		uint32_t chroma_half_pitch:1;
> -		uint32_t surface_pitch:17;
> -		uint32_t chroma_interleave:1;
> -		uint32_t lsb_packed_enable:1;
> -		uint32_t bayer_input_alignment:2;
> -		uint32_t bayer_pattern_format:1;
> -		uint32_t bayer_pattern_offset:2;
> -		uint32_t surface_format:5;
> +			uint32_t tile_walk:1;
> +			uint32_t tiled_surface:1;
> +			uint32_t chroma_half_pitch:1;
> +			uint32_t surface_pitch:17;
> +			uint32_t chroma_interleave:1;
> +			uint32_t lsb_packed_enable:1;
> +			uint32_t bayer_input_alignment:2;
> +			uint32_t bayer_pattern_format:1;
> +			uint32_t bayer_pattern_offset:2;
> +			uint32_t surface_format:5;
> +		} tgl;
> +		struct {
> +			uint32_t tile_mode:2;
> +			uint32_t pad0:30;
> +		} dg2;
>  	} ss3;
>  	struct {
>  		uint32_t u_y_offset:15;
> @@ -82,9 +88,15 @@ struct vebox_surface_state {
>  		uint32_t frame_x_offset:15;
>  		uint32_t pad:2;
>  	} ss6;
> -	struct {
> -		uint32_t derived_surface_pitch:17;
> -		uint32_t pad:15;
> +	union {
> +		struct {
> +			uint32_t derived_surface_pitch:17;
> +			uint32_t pad:15;
> +		} skl;
> +		struct {
> +			uint32_t pad:27;
> +			uint32_t compression_format:5;
> +		} dg2;
>  	} ss7;
>  	struct {
>  		uint32_t skin_score_output_surface_pitch:17;
> @@ -166,17 +178,46 @@ static void emit_surface_state_cmd(struct intel_bb
> *ibb,
>  	ss->ss2.height = height - 1;
>  	ss->ss2.width = width - 1;
> 
> -	ss->ss3.surface_format = format;
> +	ss->ss3.tgl.surface_format = format;
>  	if (format_is_interleaved_yuv(format))
> -		ss->ss3.chroma_interleave = 1;
> -	ss->ss3.surface_pitch = pitch - 1;
> -	ss->ss3.tile_walk = (tiling == I915_TILING_Y) ||
> -			    (tiling == I915_TILING_Yf);
> -	ss->ss3.tiled_surface = tiling != I915_TILING_NONE;
> +		ss->ss3.tgl.chroma_interleave = 1;
> +	ss->ss3.tgl.surface_pitch = pitch - 1;
> 
>  	ss->ss4.u_y_offset = uv_offset / pitch;
> 
> -	ss->ss7.derived_surface_pitch = pitch - 1;
> +	if (HAS_FLATCCS(ibb->devid)) {
> +                /*
> +                 * f-tile = 3 (Tile F)
> +                 */
> +                ss->ss3.dg2.tile_mode = (tiling != I915_TILING_NONE) ?
> +3 : 0;
> +
> +                switch (format) {
> +                case R8G8B8A8_UNORM:
> +                        ss->ss7.dg2.compression_format = 0xa;
> +                        break;
> +                case PLANAR_420_8:
> +                        ss->ss7.dg2.compression_format = 0xf;
> +                        break;
> +                case PLANAR_420_16:
> +                        ss->ss7.dg2.compression_format = 8;
> +                        break;
> +                case YCRCB_NORMAL:
> +                        ss->ss7.dg2.compression_format = 3;
> +                        break;
> +                case PACKED_444A_8:
> +                        ss->ss7.dg2.compression_format = 0x9;
> +                        break;
> +                default:
> +                        igt_assert(0);
> +                }
> +        } else {
> +                ss->ss3.tgl.tile_walk = (tiling == I915_TILING_Y) ||
> +                        (tiling == I915_TILING_Yf) ||
> +                        (tiling == I915_TILING_4);
> +                ss->ss3.tgl.tiled_surface = tiling != I915_TILING_NONE;
> +        }
> +
> +	ss->ss7.skl.derived_surface_pitch = pitch - 1;
> 
>  	intel_bb_ptr_add(ibb, sizeof(*ss));
>  }
> @@ -203,7 +244,11 @@ static void emit_tiling_convert_cmd(struct intel_bb
> *ibb,
>  		tc->tc1_2.input_compression_type =
>  			src->compression == I915_COMPRESSION_RENDER;
>  	}
> -	tc->tc1_2.input_tiled_resource_mode = src->tiling == I915_TILING_Yf;
> +
> +	if (HAS_4TILE(ibb->devid))
> +		tc->tc1_2.input_mocs_idx = 3;
> +	else
> +		tc->tc1_2.input_tiled_resource_mode = src->tiling ==
> I915_TILING_Yf;
>  	reloc_delta = tc->tc1_2_l;
> 
>  	igt_assert(src->addr.offset == ALIGN(src->addr.offset, 0x1000)); @@ -
> 220,7 +265,12 @@ static void emit_tiling_convert_cmd(struct intel_bb *ibb,
>  		tc->tc3_4.output_compression_type =
>  			dst->compression == I915_COMPRESSION_RENDER;
>  	}
> -	tc->tc3_4.output_tiled_resource_mode = dst->tiling == I915_TILING_Yf;
> +
> +	if (HAS_4TILE(ibb->devid))
> +		tc->tc3_4.output_mocs_idx = 3;
> +	else
> +		tc->tc3_4.output_tiled_resource_mode = dst->tiling ==
> I915_TILING_Yf;
> +
>  	reloc_delta = tc->tc3_4_l;
> 
>  	igt_assert(dst->addr.offset == ALIGN(dst->addr.offset, 0x1000)); @@ -
> 255,10 +305,12 @@ void gen12_vebox_copyfunc(struct intel_bb *ibb,
>  	intel_bb_add_intel_buf(ibb, dst, true);
>  	intel_bb_add_intel_buf(ibb, src, false);
> 
> -	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
> -	gen12_aux_pgtable_init(&aux_pgtable_info, ibb, src, dst);
> -	aux_pgtable_state = gen12_create_aux_pgtable_state(ibb,
> -
> aux_pgtable_info.pgtable_buf);
> +	if (!HAS_FLATCCS(ibb->devid)) {
> +		intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
> +		gen12_aux_pgtable_init(&aux_pgtable_info, ibb, src, dst);
> +		aux_pgtable_state = gen12_create_aux_pgtable_state(ibb,
> +
> aux_pgtable_info.pgtable_buf);
> +	}
> 
>  	intel_bb_ptr_set(ibb, 0);
>  	gen12_emit_aux_pgtable_state(ibb, aux_pgtable_state, false); @@ -
> 311,5 +363,6 @@ void gen12_vebox_copyfunc(struct intel_bb *ibb,
> 
>  	intel_bb_reset(ibb, false);
> 
> -	gen12_aux_pgtable_cleanup(ibb, &aux_pgtable_info);
> +	if (!HAS_FLATCCS(ibb->devid))
> +		gen12_aux_pgtable_cleanup(ibb, &aux_pgtable_info);
>  }
> --
> 2.35.1

[igt-dev] [PATCH i-g-t v2 3/4] tests/kms_ccs: Add dg2 tiled-4 ccs modifiers

[Jeevan B]

From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>

LOCAL_I915_FORMAT_MOD_4_TILED_DG2_RC_CCS
LOCAL_I915_FORMAT_MOD_4_TILED_DG2_MC_CCS
LOCAL_I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC

modifier added for testing and prevent impossible ccs test from
flat ccs

Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/kms_ccs.c | 62 +++++++++++++++++++++++++++-----------------
 1 file changed, 38 insertions(+), 24 deletions(-)

diff --git a/tests/i915/kms_ccs.c b/tests/i915/kms_ccs.c
index 716be5b6..39bf6d58 100644
--- a/tests/i915/kms_ccs.c
+++ b/tests/i915/kms_ccs.c
@@ -98,10 +98,29 @@ static const struct {
 	{I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, "y_tiled_gen12_rc_ccs"},
 	{I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, "y_tiled_gen12_rc_ccs_cc"},
 	{I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, "y_tiled_gen12_mc_ccs"},
+	{I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, "4_tiled_dg2_rc_ccs"},
+	{I915_FORMAT_MOD_4_TILED_DG2_MC_CCS, "4_tiled_dg2_mc_ccs"},
+	{I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC, "4_tiled_dg2_rc_ccs_cc"},
 };
 
 static bool check_ccs_planes;
 
+static const struct {
+	const enum test_flags	flags;
+	const char		*testname;
+	const char		*description;
+} tests[] = {
+	{TEST_BAD_PIXEL_FORMAT, "bad-pixel-format", "Test bad pixel format with given CCS modifier"},
+	{TEST_BAD_ROTATION_90, "bad-rotation-90", "Test 90 degree rotation with given CCS modifier"},
+	{TEST_CRC, "crc-primary-basic", "Test primary plane CRC compatibility with given CCS modifier"},
+	{TEST_CRC | TEST_ROTATE_180, "crc-primary-rotation-180", "Test 180 degree rotation with given CCS modifier"},
+	{TEST_RANDOM, "random-ccs-data", "Test random CCS data"},
+	{TEST_NO_AUX_BUFFER, "missing-ccs-buffer", "Test missing CCS buffer with given CCS modifier"},
+	{TEST_BAD_CCS_HANDLE, "ccs-on-another-bo", "Test CCS with different BO with given modifier"},
+	{TEST_BAD_AUX_STRIDE, "bad-aux-stride", "Test with bad AUX stride with given CCS modifier"},
+	{TEST_CRC | TEST_ALL_PLANES, "crc-sprite-planes-basic", "Test sprite plane CRC compatibility with given CCS modifier"},
+};
+
 /*
  * Limit maximum used sprite plane width so this test will not mistakenly
  * fail on hardware limitations which are not interesting to this test.
@@ -141,7 +160,8 @@ create_fb_prepare_add(int drm_fd, int width, int height,
 
 static bool is_ccs_cc_modifier(uint64_t modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
+		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
 }
 
 /*
@@ -256,12 +276,14 @@ static void test_bad_ccs_plane(data_t *data, int width, int height, int ccs_plan
 	 * an incorrect stride with the same delta as on earlier platforms.
 	 */
 	if (fb_flags & FB_MISALIGN_AUX_STRIDE) {
+		igt_skip_on_f(HAS_FLATCCS(intel_get_drm_devid(data->drm_fd)), "No aux plane on flat ccs.\n");
 		igt_skip_on_f(width <= 1024,
 			      "FB already has the smallest possible stride\n");
 		f.pitches[ccs_plane] -= 64;
 	}
 
 	if (fb_flags & FB_SMALL_AUX_STRIDE) {
+		igt_skip_on_f(HAS_FLATCCS(intel_get_drm_devid(data->drm_fd)), "No aux plane on flat ccs.\n");
 		igt_skip_on_f(width <= 1024,
 			      "FB already has the smallest possible stride\n");
 		f.pitches[ccs_plane] = ALIGN(f.pitches[ccs_plane] / 2, 128);
@@ -277,6 +299,7 @@ static void test_bad_ccs_plane(data_t *data, int width, int height, int ccs_plan
 	}
 
 	if (data->flags & TEST_NO_AUX_BUFFER) {
+		igt_skip_on_f(HAS_FLATCCS(intel_get_drm_devid(data->drm_fd)), "No aux plane on flat ccs.\n");
 		f.handles[ccs_plane] = 0;
 		f.modifier[ccs_plane] = 0;
 		f.pitches[ccs_plane] = 0;
@@ -363,7 +386,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
 				   colors[!!data->plane].b,
 				   1.0};
 
-	/* Use either compressed or Y-tiled to test. However, given the lack of
+	/* Use either compressed or linear to test. However, given the lack of
 	 * available bandwidth, we use linear for the primary plane when
 	 * testing sprites, since we cannot fit two CCS planes into the
 	 * available FIFO configurations.
@@ -371,7 +394,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
 	if (fb_flags & FB_COMPRESSED)
 		modifier = data->ccs_modifier;
 	else if (!(fb_flags & FB_HAS_PLANE))
-		modifier = I915_FORMAT_MOD_Y_TILED;
+		modifier = DRM_FORMAT_MOD_LINEAR;
 	else
 		modifier = 0;
 
@@ -563,9 +586,11 @@ static int test_ccs(data_t *data)
 	return valid_tests;
 }
 
-static void test_output(data_t *data, const char* testformatstring)
+static void test_output(data_t *data, const int testnum)
 {
 	igt_fixture {
+		data->flags = tests[testnum].flags;
+
 		data->output = igt_get_single_output_for_pipe(&data->display,
 							      data->pipe);
 		igt_require(data->output);
@@ -573,10 +598,17 @@ static void test_output(data_t *data, const char* testformatstring)
 	}
 
 	for (int i = 0; i < ARRAY_SIZE(ccs_modifiers); i++) {
+		if ((ccs_modifiers[i].modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS ||
+		    ccs_modifiers[i].modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS ||
+		    ccs_modifiers[i].modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC) &&
+		    tests[testnum].flags & TEST_BAD_CCS_PLANE)
+		    continue;
+
 		data->ccs_modifier = ccs_modifiers[i].modifier;
 
+		igt_describe(tests[testnum].description);
 		igt_subtest_f("pipe-%s-%s-%s", kmstest_pipe_name(data->pipe),
-			      testformatstring, ccs_modifiers[i].str ) {
+			      tests[testnum].testname, ccs_modifiers[i].str) {
 			int valid_tests = 0;
 			igt_require(data->output);
 
@@ -643,22 +675,6 @@ igt_main_args("cs:", NULL, help_str, opt_handler, &data)
 {
 	enum pipe pipe;
 
-	const struct {
-		const enum test_flags	flags;
-		const char		*testname;
-		const char		*description;
-	} tests[] = {
-		{TEST_BAD_PIXEL_FORMAT, "bad-pixel-format", "Test bad pixel format with given CCS modifier"},
-		{TEST_BAD_ROTATION_90, "bad-rotation-90", "Test 90 degree rotation with given CCS modifier"},
-		{TEST_CRC, "crc-primary-basic", "Test primary plane CRC compatibility with given CCS modifier"},
-		{TEST_CRC | TEST_ROTATE_180, "crc-primary-rotation-180", "Test 180 degree rotation with given CCS modifier"},
-		{TEST_RANDOM, "random-ccs-data", "Test random CCS data"},
-		{TEST_NO_AUX_BUFFER, "missing-ccs-buffer", "Test missing CCS buffer with given CCS modifier"},
-		{TEST_BAD_CCS_HANDLE, "ccs-on-another-bo", "Test CCS with different BO with given modifier"},
-		{TEST_BAD_AUX_STRIDE, "bad-aux-stride", "Test with bad AUX stride with given CCS modifier"},
-		{TEST_CRC | TEST_ALL_PLANES, "crc-sprite-planes-basic", "Test sprite plane CRC compatibility with given CCS modifier"},
-	};
-
 	igt_fixture {
 		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
 
@@ -678,9 +694,7 @@ igt_main_args("cs:", NULL, help_str, opt_handler, &data)
 
 		igt_subtest_group {
 			for (int c = 0; c < ARRAY_SIZE(tests); c++) {
-				data.flags = tests[c].flags;
-				igt_describe(tests[c].description);
-				test_output(&data, tests[c].testname);
+				test_output(&data, c);
 			}
 		}
 	}
-- 
2.35.1

Re: [igt-dev] [PATCH i-g-t v2 3/4] tests/kms_ccs: Add dg2 tiled-4 ccs modifiers

[Petri Latvala]

On Wed, Apr 20, 2022 at 04:09:08PM +0530, Jeevan B wrote:
> From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> 
> LOCAL_I915_FORMAT_MOD_4_TILED_DG2_RC_CCS
> LOCAL_I915_FORMAT_MOD_4_TILED_DG2_MC_CCS
> LOCAL_I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC
> 
> modifier added for testing and prevent impossible ccs test from
> flat ccs

They're not LOCAL_ here though.

> 
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
>  tests/i915/kms_ccs.c | 62 +++++++++++++++++++++++++++-----------------
>  1 file changed, 38 insertions(+), 24 deletions(-)
> 
> diff --git a/tests/i915/kms_ccs.c b/tests/i915/kms_ccs.c
> index 716be5b6..39bf6d58 100644
> --- a/tests/i915/kms_ccs.c
> +++ b/tests/i915/kms_ccs.c
> @@ -98,10 +98,29 @@ static const struct {
>  	{I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, "y_tiled_gen12_rc_ccs"},
>  	{I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, "y_tiled_gen12_rc_ccs_cc"},
>  	{I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, "y_tiled_gen12_mc_ccs"},
> +	{I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, "4_tiled_dg2_rc_ccs"},
> +	{I915_FORMAT_MOD_4_TILED_DG2_MC_CCS, "4_tiled_dg2_mc_ccs"},
> +	{I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC, "4_tiled_dg2_rc_ccs_cc"},
>  };
>  
>  static bool check_ccs_planes;
>  
> +static const struct {
> +	const enum test_flags	flags;
> +	const char		*testname;
> +	const char		*description;
> +} tests[] = {
> +	{TEST_BAD_PIXEL_FORMAT, "bad-pixel-format", "Test bad pixel format with given CCS modifier"},
> +	{TEST_BAD_ROTATION_90, "bad-rotation-90", "Test 90 degree rotation with given CCS modifier"},
> +	{TEST_CRC, "crc-primary-basic", "Test primary plane CRC compatibility with given CCS modifier"},
> +	{TEST_CRC | TEST_ROTATE_180, "crc-primary-rotation-180", "Test 180 degree rotation with given CCS modifier"},
> +	{TEST_RANDOM, "random-ccs-data", "Test random CCS data"},
> +	{TEST_NO_AUX_BUFFER, "missing-ccs-buffer", "Test missing CCS buffer with given CCS modifier"},
> +	{TEST_BAD_CCS_HANDLE, "ccs-on-another-bo", "Test CCS with different BO with given modifier"},
> +	{TEST_BAD_AUX_STRIDE, "bad-aux-stride", "Test with bad AUX stride with given CCS modifier"},
> +	{TEST_CRC | TEST_ALL_PLANES, "crc-sprite-planes-basic", "Test sprite plane CRC compatibility with given CCS modifier"},
> +};
> +
>  /*
>   * Limit maximum used sprite plane width so this test will not mistakenly
>   * fail on hardware limitations which are not interesting to this test.
> @@ -141,7 +160,8 @@ create_fb_prepare_add(int drm_fd, int width, int height,
>  
>  static bool is_ccs_cc_modifier(uint64_t modifier)
>  {
> -	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
>  }
>  
>  /*
> @@ -256,12 +276,14 @@ static void test_bad_ccs_plane(data_t *data, int width, int height, int ccs_plan
>  	 * an incorrect stride with the same delta as on earlier platforms.
>  	 */
>  	if (fb_flags & FB_MISALIGN_AUX_STRIDE) {
> +		igt_skip_on_f(HAS_FLATCCS(intel_get_drm_devid(data->drm_fd)), "No aux plane on flat ccs.\n");
>  		igt_skip_on_f(width <= 1024,
>  			      "FB already has the smallest possible stride\n");
>  		f.pitches[ccs_plane] -= 64;
>  	}
>  
>  	if (fb_flags & FB_SMALL_AUX_STRIDE) {
> +		igt_skip_on_f(HAS_FLATCCS(intel_get_drm_devid(data->drm_fd)), "No aux plane on flat ccs.\n");
>  		igt_skip_on_f(width <= 1024,
>  			      "FB already has the smallest possible stride\n");
>  		f.pitches[ccs_plane] = ALIGN(f.pitches[ccs_plane] / 2, 128);
> @@ -277,6 +299,7 @@ static void test_bad_ccs_plane(data_t *data, int width, int height, int ccs_plan
>  	}
>  
>  	if (data->flags & TEST_NO_AUX_BUFFER) {
> +		igt_skip_on_f(HAS_FLATCCS(intel_get_drm_devid(data->drm_fd)), "No aux plane on flat ccs.\n");
>  		f.handles[ccs_plane] = 0;
>  		f.modifier[ccs_plane] = 0;
>  		f.pitches[ccs_plane] = 0;
> @@ -363,7 +386,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
>  				   colors[!!data->plane].b,
>  				   1.0};
>  
> -	/* Use either compressed or Y-tiled to test. However, given the lack of
> +	/* Use either compressed or linear to test. However, given the lack of
>  	 * available bandwidth, we use linear for the primary plane when
>  	 * testing sprites, since we cannot fit two CCS planes into the
>  	 * available FIFO configurations.
> @@ -371,7 +394,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
>  	if (fb_flags & FB_COMPRESSED)
>  		modifier = data->ccs_modifier;
>  	else if (!(fb_flags & FB_HAS_PLANE))
> -		modifier = I915_FORMAT_MOD_Y_TILED;
> +		modifier = DRM_FORMAT_MOD_LINEAR;

This change is not explained in the commit message.


-- 
Petri Latvala

[igt-dev] [PATCH i-g-t v2 4/4] tests/kms_getfb: Add flat ccs modifier support

[Jeevan B]

From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>

Add support for testing/skipping flat ccs modifiers

Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_getfb.c | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/tests/kms_getfb.c b/tests/kms_getfb.c
index 75f5f30c..b3a8d265 100644
--- a/tests/kms_getfb.c
+++ b/tests/kms_getfb.c
@@ -88,11 +88,18 @@ static void get_ccs_fb(int fd, struct drm_mode_fb_cmd2 *ret)
 		.flags = DRM_MODE_FB_MODIFIERS,
 	};
 	int size;
+	uint32_t devid;
 
 	igt_require(has_addfb2_iface(fd));
 	igt_require_intel(fd);
+	devid = intel_get_drm_devid(fd);
 
-	if ((intel_display_ver(intel_get_drm_devid(fd))) >= 12) {
+	if (HAS_FLATCCS(devid)) {
+		add.modifier[0] = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
+		add.pitches[0] = ALIGN(add.width * 4, 4 * 512);
+		size = add.pitches[0] * ALIGN(add.height, 8);
+		size = ALIGN(size, 4096);
+	} else if ((intel_display_ver(devid)) >= 12) {
 		add.modifier[0] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
 		add.modifier[1] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
 
@@ -130,7 +137,9 @@ static void get_ccs_fb(int fd, struct drm_mode_fb_cmd2 *ret)
 
 	add.handles[0] = gem_buffer_create_fb_obj(fd, size);
 	igt_require(add.handles[0] != 0);
-	add.handles[1] = add.handles[0];
+
+	if (!HAS_FLATCCS(intel_get_drm_devid(fd)))
+		add.handles[1] = add.handles[0];
 
 	if (drmIoctl(fd, DRM_IOCTL_MODE_ADDFB2, &add) == 0)
 		*ret = add;
@@ -256,6 +265,9 @@ static void test_duplicate_handles(int fd)
 		struct drm_mode_fb_cmd2 add_ccs = { };
 		struct drm_mode_fb_cmd get = { };
 
+		igt_require_f(!HAS_FLATCCS(intel_get_drm_devid(fd)),
+			      "skip because flat ccs has only one buffer.\n");
+
 		get_ccs_fb(fd, &add_ccs);
 		igt_require(add_ccs.handles[0] != 0);
 		get.fb_id = add_ccs.fb_id;
@@ -350,7 +362,9 @@ static void test_getfb2(int fd)
 				igt_assert_eq_u64(get.modifier[i], 0);
 			}
 		}
-		igt_assert_eq_u32(get.handles[0], get.handles[1]);
+
+		if (!HAS_FLATCCS(intel_get_drm_devid(fd)))
+			igt_assert_eq_u32(get.handles[0], get.handles[1]);
 
 		do_ioctl(fd, DRM_IOCTL_MODE_RMFB, &get.fb_id);
 		gem_close(fd, add_ccs.handles[0]);
-- 
2.35.1

[igt-dev] ✗ Fi.CI.BAT: failure for enable 4-tiled ccs modifiers on dg2 (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9058 bytes --]

== Series Details ==

Series: enable 4-tiled ccs modifiers on dg2 (rev2)
URL   : https://patchwork.freedesktop.org/series/102335/
State : failure

== Summary ==

CI Bug Log - changes from IGT_6441 -> IGTPW_6954
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_6954 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_6954, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/index.html

Participating hosts (49 -> 47)
------------------------------

  Additional (1): fi-icl-u2 
  Missing    (3): fi-ctg-p8600 fi-bsw-cyan fi-hsw-4200u 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6954:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@gem_contexts:
    - fi-bdw-5557u:       NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html

  
Known issues
------------

  Here are the changes found in IGTPW_6954 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-icl-u2:          NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-icl-u2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-icl-u2:          NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_selftest@live@gtt:
    - fi-bdw-5557u:       NOTRUN -> [DMESG-FAIL][4] ([i915#3674])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-bdw-5557u/igt@i915_selftest@live@gtt.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-5:          NOTRUN -> [INCOMPLETE][5] ([i915#5757])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
    - fi-hsw-4770:        [PASS][6] -> [INCOMPLETE][7] ([i915#4785])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6441/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
    - fi-tgl-u2:          [PASS][11] -> [DMESG-WARN][12] ([i915#402])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6441/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-icl-u2:          NOTRUN -> [SKIP][13] ([fdo#109285])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-icl-u2:          NOTRUN -> [SKIP][14] ([i915#3555])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
    - fi-bdw-5557u:       NOTRUN -> [SKIP][15] ([fdo#109271]) +14 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-bdw-5557u/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
    - fi-icl-u2:          NOTRUN -> [SKIP][16] ([i915#3301])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-icl-u2/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-hsw-4770:        NOTRUN -> [FAIL][17] ([fdo#109271] / [i915#4312] / [i915#5594])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-hsw-4770/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_engines:
    - bat-dg1-5:          [INCOMPLETE][18] ([i915#4418]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6441/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/bat-dg1-5/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@gt_lrc:
    - {bat-adlp-6}:       [INCOMPLETE][20] ([i915#5513]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6441/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html

  * igt@kms_busy@basic@flip:
    - fi-tgl-u2:          [DMESG-WARN][22] ([i915#402]) -> [PASS][23] +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6441/fi-tgl-u2/igt@kms_busy@basic@flip.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/fi-tgl-u2/igt@kms_busy@basic@flip.html

  * igt@kms_busy@basic@modeset:
    - {bat-adlp-6}:       [DMESG-WARN][24] ([i915#3576]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6441/bat-adlp-6/igt@kms_busy@basic@modeset.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/bat-adlp-6/igt@kms_busy@basic@modeset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3674]: https://gitlab.freedesktop.org/drm/intel/issues/3674
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
  [i915#5329]: https://gitlab.freedesktop.org/drm/intel/issues/5329
  [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
  [i915#5414]: https://gitlab.freedesktop.org/drm/intel/issues/5414
  [i915#5513]: https://gitlab.freedesktop.org/drm/intel/issues/5513
  [i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
  [i915#5552]: https://gitlab.freedesktop.org/drm/intel/issues/5552
  [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
  [i915#5757]: https://gitlab.freedesktop.org/drm/intel/issues/5757


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6441 -> IGTPW_6954

  CI-20190529: 20190529
  CI_DRM_11526: 6094ebd5db15c51e89ce9960d782613f8df57c63 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6954: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/index.html
  IGT_6441: a44d1d4c9e7198a2d59d7dcaae38e340f7cadcf9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+++ 108 lines
--- 0 lines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6954/index.html

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