[igt-dev] [PATCH i-g-t v4 00/11] Remove libdrm remnants in i915 code

[igt-dev] [PATCH i-g-t v4 00/11] Remove libdrm remnants in i915 code

[Zbigniew Kempczyński]

v2: rewrite instead of prime_udl/prime_nv_* removals.
v3: remove all references to libdrm-intel/intel_bufmgr
v4: rebase

I want finally remove all libdrm stuff, to get this I had to:

1. remove missed bufmgr field in i915_pipe_stress

2. rewrite prime_udl test - it is not used in CI due to lack of 
   DisplayLink hardware and I also don't have such hardware so 
   this is blind rewrite

3. rewrite prime_nv_* tests - similar to prime_udl (blind rewrite)

4. remove drm_import_export test, it exercises libdrm prime caps

5. rewrite intel_upload_blit_* benchmarks - I tried to mimic 
   behavior as much as possible but there'e some minor differences
   in execution time. I think it is related to libdrm internals
   (how it caches handles/mappings). I'm not sure but it shouldn't
   much affect what benchmark is exercising.

6. remove all intel_batchbuffer_* code

7. get libdrm decode code and adopt to use in igt

8. use local decode code (taken from libdrm) in intel_dump|error_decode
   tools

9. remove unused functions in ioctl_wrappers

10 remove libdrm definitions in tools/meson.build

11. remove libdrm/stubs definitions in lib/meson.build + libdrm stubs

Cc: Petri Latvala <petri.latvala@intel.com>

Zbigniew Kempczyński (11):
  tests/i915_pipe_stress: Remove unused bufmgr field
  tests/prime_udl: Remove intel-libdrm dependency
  tests/prime_nv: Remove intel-libdrm calls
  tests/drm_import_export: Remove the test
  benchmarks/intel_upload_blit_*: Remove libdrm in upload blits
  lib/intel_batchbuffer: Get rid of libdrm batchbuffer
  lib/intel_decode: Get drm decode code and adopt to use in igt
  tools/intel_dump|error_decode: Use local igt decode code
  lib/ioctl_wrappers: Remove gem_handle_to_libdrm_bo
  tools/meson: Move tools out of libdrm scope
  lib/meson: Remove libdrm configuration and intel_bufmgr stubs

 benchmarks/intel_upload_blit_large.c     |  131 +-
 benchmarks/intel_upload_blit_large_gtt.c |  130 +-
 benchmarks/intel_upload_blit_large_map.c |  132 +-
 benchmarks/intel_upload_blit_small.c     |  139 +-
 benchmarks/meson.build                   |   13 +-
 lib/i915/intel_decode.c                  | 3962 ++++++++++++++++++++++
 lib/i915/intel_decode.h                  |   42 +
 lib/intel_batchbuffer.c                  |  575 +---
 lib/intel_batchbuffer.h                  |  248 --
 lib/ioctl_wrappers.c                     |   31 -
 lib/ioctl_wrappers.h                     |    5 -
 lib/meson.build                          |    8 +-
 lib/stubs/drm/README                     |    4 -
 lib/stubs/drm/intel_bufmgr.c             |  292 --
 lib/stubs/drm/intel_bufmgr.h             |  323 --
 tests/drm_import_export.c                |  304 --
 tests/i915/i915_pipe_stress.c            |    1 -
 tests/meson.build                        |    1 -
 tests/prime_nv_api.c                     |  151 +-
 tests/prime_nv_pcopy.c                   |  107 +-
 tests/prime_nv_test.c                    |  162 +-
 tests/prime_udl.c                        |   64 +-
 tools/intel_dump_decode.c                |   16 +-
 tools/intel_error_decode.c               |   14 +-
 tools/meson.build                        |   15 +-
 25 files changed, 4536 insertions(+), 2334 deletions(-)
 create mode 100644 lib/i915/intel_decode.c
 create mode 100644 lib/i915/intel_decode.h
 delete mode 100644 lib/stubs/drm/README
 delete mode 100644 lib/stubs/drm/intel_bufmgr.c
 delete mode 100644 lib/stubs/drm/intel_bufmgr.h
 delete mode 100644 tests/drm_import_export.c

-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 01/11] tests/i915_pipe_stress: Remove unused bufmgr field

[Zbigniew Kempczyński]

During rewriting this likely left incidentally even if it is not used.
Lets get rid of it.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 tests/i915/i915_pipe_stress.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/tests/i915/i915_pipe_stress.c b/tests/i915/i915_pipe_stress.c
index 6ce2ce1de2..c06bc65d2c 100644
--- a/tests/i915/i915_pipe_stress.c
+++ b/tests/i915/i915_pipe_stress.c
@@ -119,7 +119,6 @@ struct data {
 	uint64_t modifier;
 	uint32_t devid;
 	struct buf_ops *bops;
-	drm_intel_bufmgr *bufmgr;
 	drmModeModeInfo *last_mode[IGT_MAX_PIPES];
 	struct igt_fb fb[IGT_MAX_PIPES * MAX_PLANES];
 	struct igt_fb cursor_fb[IGT_MAX_PIPES];
-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 02/11] tests/prime_udl: Remove intel-libdrm dependency

[Zbigniew Kempczyński]

To remove all intel-libdrm code in intel_batchbuffer we need to rewrite
and drop it in all dependent code. Currently CI doesn't exercise this
test and I don't have DisplayLink hardware so this is blind rewrite
(instead of removing the test). Common xf86drmMode calls are left
intact as igt likely won't remove libdrm totally.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 tests/prime_udl.c | 64 ++++++++++++++++-------------------------------
 1 file changed, 21 insertions(+), 43 deletions(-)

diff --git a/tests/prime_udl.c b/tests/prime_udl.c
index 582e31f5df..884bf69fea 100644
--- a/tests/prime_udl.c
+++ b/tests/prime_udl.c
@@ -11,14 +11,11 @@
 #include "xf86drm.h"
 #include <xf86drmMode.h>
 
-#include "intel_bufmgr.h"
+#include "i915/gem_create.h"
 
 IGT_TEST_DESCRIPTION("Basic set of prime tests between Intel and DisplayLink");
 
 int intel_fd = -1, udl_fd = -1;
-drm_intel_bufmgr *bufmgr;
-uint32_t devid;
-struct intel_batchbuffer *intel_batch;
 
 #define BO_SIZE (640*480*2)
 
@@ -78,57 +75,50 @@ static int dumb_bo_destroy(int fd, uint32_t handle)
 /*
  * simple share and import
  */
-static int test1(void)
+static void test1(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle, udl_handle;
 	int prime_fd;
-	int ret;
-	uint32_t udl_handle;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
+	igt_assert(prime_fd >= 0);
 
-	ret = drmPrimeFDToHandle(udl_fd, prime_fd, &udl_handle);
+	udl_handle = prime_fd_to_handle(udl_fd, prime_fd);
+	igt_assert(udl_handle > 0);
 
 	dumb_bo_destroy(udl_fd, udl_handle);
-	drm_intel_bo_unreference(test_intel_bo);
-	return ret;
+	gem_close(intel_fd, intel_handle);
 }
 
-static int test2(void)
+static void test2(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle, udl_handle;
 	uint32_t fb_id;
 	drmModeClip clip;
 	int prime_fd;
-	uint32_t udl_handle;
 	int ret;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
+	igt_assert(prime_fd >= 0);
 
-	ret = drmPrimeFDToHandle(udl_fd, prime_fd, &udl_handle);
-	if (ret)
-		goto out;
+	udl_handle = prime_fd_to_handle(udl_fd, prime_fd);
 
 	ret = drmModeAddFB(udl_fd, 640, 480, 16, 16, 640, udl_handle, &fb_id);
-	if (ret)
-		goto out;
+	igt_assert(ret == 0);
 
 	clip.x1 = 0;
 	clip.y1 = 0;
 	clip.x2 = 10;
 	clip.y2 = 10;
 	ret = drmModeDirtyFB(udl_fd, fb_id, &clip, 1);
-	if (ret) {
-		return ret;
-	}
-out:
+	igt_assert(ret == 0);
+
 	dumb_bo_destroy(udl_fd, udl_handle);
-	drm_intel_bo_unreference(test_intel_bo);
-	return ret;
+	gem_close(intel_fd, intel_handle);
 }
 
 igt_simple_main
@@ -138,22 +128,10 @@ igt_simple_main
 	igt_skip_on(udl_fd == -1);
 	igt_skip_on(intel_fd == -1);
 
-	/* set up intel bufmgr */
-	bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
-	/* set up an intel batch buffer */
-	devid = intel_get_drm_devid(intel_fd);
-	intel_batch = intel_batchbuffer_alloc(bufmgr, devid);
-
 	/* create an object on the i915 */
-	igt_assert(test1() == 0);
-
-	igt_assert(test2() == 0);
-
-	intel_batchbuffer_free(intel_batch);
+	test1();
 
-	drm_intel_bufmgr_destroy(bufmgr);
+	test2();
 
 	close(intel_fd);
 	close(udl_fd);
-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 03/11] tests/prime_nv: Remove intel-libdrm calls

[Zbigniew Kempczyński]

Replace intel-libdrm calls with already existing IGT wrappers. We need
this to completely remove intel_batchbuffer helpers.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 tests/prime_nv_api.c   | 151 +++++++++++++++-----------------------
 tests/prime_nv_pcopy.c | 107 +++++++++++----------------
 tests/prime_nv_test.c  | 162 ++++++++++++++++++-----------------------
 3 files changed, 173 insertions(+), 247 deletions(-)

diff --git a/tests/prime_nv_api.c b/tests/prime_nv_api.c
index 054a1ec64a..cb3d52e8d6 100644
--- a/tests/prime_nv_api.c
+++ b/tests/prime_nv_api.c
@@ -15,18 +15,14 @@
 #include <fcntl.h>
 #include <sys/stat.h>
 
-#include "intel_bufmgr.h"
+#include "i915/gem_create.h"
 #include "nouveau.h"
 
 #define BO_SIZE (256*1024)
 
 int intel_fd = -1, intel_fd2 = -1, nouveau_fd = -1, nouveau_fd2 = -1;
-drm_intel_bufmgr *bufmgr;
-drm_intel_bufmgr *bufmgr2;
 struct nouveau_device *ndev, *ndev2;
 struct nouveau_client *nclient, *nclient2;
-uint32_t devid;
-struct intel_batchbuffer *intel_batch;
 
 static void find_and_open_devices(void)
 {
@@ -69,13 +65,12 @@ static void find_and_open_devices(void)
 
 static void test_i915_nv_import_twice(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	igt_assert(nouveau_bo_prime_handle_ref(ndev2, prime_fd, &nvbo2) == 0);
@@ -83,19 +78,18 @@ static void test_i915_nv_import_twice(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_close(intel_fd, intel_handle);
 }
 
 static void test_i915_nv_import_twice_check_flink_name(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 	uint32_t flink_name1, flink_name2;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	igt_assert(nouveau_bo_prime_handle_ref(ndev2, prime_fd, &nvbo2) == 0);
@@ -108,25 +102,24 @@ static void test_i915_nv_import_twice_check_flink_name(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_close(intel_fd, intel_handle);
 }
 
 static void test_i915_nv_reimport_twice_check_flink_name(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 	uint32_t flink_name1, flink_name2;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 
 	/* create a new dma-buf */
 	close(prime_fd);
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev2, prime_fd, &nvbo2) == 0);
 	close(prime_fd);
@@ -138,12 +131,12 @@ static void test_i915_nv_reimport_twice_check_flink_name(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_close(intel_fd, intel_handle);
 }
 
 static void test_nv_i915_import_twice_check_flink_name(void)
 {
-	drm_intel_bo *intel_bo = NULL, *intel_bo2 = NULL;
+	uint32_t intel_handle, intel_handle2;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL;
 	uint32_t flink_name1, flink_name2;
@@ -153,26 +146,23 @@ static void test_nv_i915_import_twice_check_flink_name(void)
 
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
-	igt_assert(intel_bo);
-
-	intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr2, prime_fd, BO_SIZE);
-	igt_assert(intel_bo2);
+	intel_handle = prime_fd_to_handle(intel_fd, prime_fd);
+	intel_handle2 = prime_fd_to_handle(intel_fd2, prime_fd);
 	close(prime_fd);
 
-	igt_assert(drm_intel_bo_flink(intel_bo, &flink_name1) == 0);
-	igt_assert(drm_intel_bo_flink(intel_bo2, &flink_name2) == 0);
+	flink_name1 = gem_flink(intel_fd, intel_handle);
+	flink_name2 = gem_flink(intel_fd2, intel_handle2);
 
 	igt_assert_eq_u32(flink_name1, flink_name2);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(intel_bo);
-	drm_intel_bo_unreference(intel_bo2);
+	gem_close(intel_fd, intel_handle);
+	gem_close(intel_fd2, intel_handle2);
 }
 
 static void test_nv_i915_reimport_twice_check_flink_name(void)
 {
-	drm_intel_bo *intel_bo = NULL, *intel_bo2 = NULL;
+	uint32_t intel_handle, intel_handle2;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL;
 	uint32_t flink_name1, flink_name2;
@@ -182,35 +172,32 @@ static void test_nv_i915_reimport_twice_check_flink_name(void)
 
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
-	igt_assert(intel_bo);
+	intel_handle = prime_fd_to_handle(intel_fd, prime_fd);
 	close(prime_fd);
+
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr2, prime_fd, BO_SIZE);
-	igt_assert(intel_bo2);
+	intel_handle2 = prime_fd_to_handle(intel_fd2, prime_fd);
 	close(prime_fd);
 
-	igt_assert(drm_intel_bo_flink(intel_bo, &flink_name1) == 0);
-	igt_assert(drm_intel_bo_flink(intel_bo2, &flink_name2) == 0);
+	flink_name1 = gem_flink(intel_fd, intel_handle);
+	flink_name2 = gem_flink(intel_fd2, intel_handle2);
 
 	igt_assert_eq_u32(flink_name1, flink_name2);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(intel_bo);
-	drm_intel_bo_unreference(intel_bo2);
+	gem_close(intel_fd, intel_handle);
+	gem_close(intel_fd2, intel_handle2);
 }
 
 static void test_i915_nv_import_vs_close(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-	igt_assert(test_intel_bo);
-
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
@@ -218,20 +205,18 @@ static void test_i915_nv_import_vs_close(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_close(intel_fd, intel_handle);
 }
 
 /* import handle twice on one driver */
 static void test_i915_nv_double_import(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-	igt_assert(test_intel_bo);
-
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo2) == 0);
@@ -241,23 +226,20 @@ static void test_i915_nv_double_import(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_close(intel_fd, intel_handle);
 }
 
 /* export handle twice from one driver - import twice
    see if we get same object */
 static void test_i915_nv_double_export(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd, prime_fd2;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-	igt_assert(test_intel_bo);
-
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
-
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd2);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
+	prime_fd2 = prime_handle_to_fd(intel_fd2, intel_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
@@ -268,27 +250,26 @@ static void test_i915_nv_double_export(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+
+	gem_close(intel_fd, intel_handle);
 }
 
 /* export handle from intel driver - reimport to intel driver
    see if you get same object */
 static void test_i915_self_import(void)
 {
-	drm_intel_bo *test_intel_bo, *test_intel_bo2;
+	uint32_t intel_handle, intel_handle2;
 	int prime_fd;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
-
-	test_intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
+	intel_handle2 = prime_fd_to_handle(intel_fd, prime_fd);
 	close(prime_fd);
-	igt_assert(test_intel_bo2);
 
-	igt_assert(test_intel_bo->handle == test_intel_bo2->handle);
+	igt_assert(intel_handle == intel_handle2);
 
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_close(intel_fd, intel_handle);
 }
 
 /* nouveau export reimport test */
@@ -313,19 +294,17 @@ static void test_nv_self_import(void)
    see if you get same object */
 static void test_i915_self_import_to_different_fd(void)
 {
-	drm_intel_bo *test_intel_bo, *test_intel_bo2;
+	uint32_t intel_handle, intel_handle2;
 	int prime_fd;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
-	test_intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr2, prime_fd, BO_SIZE);
+	intel_handle2 = prime_fd_to_handle(intel_fd2, prime_fd);
 	close(prime_fd);
-	igt_assert(test_intel_bo2);
 
-	drm_intel_bo_unreference(test_intel_bo2);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_close(intel_fd, intel_handle);
+	gem_close(intel_fd2, intel_handle2);
 }
 
 /* nouveau export reimport to other driver test */
@@ -356,16 +335,6 @@ igt_main
 		igt_require(intel_fd != -1);
 		igt_require(intel_fd2 != -1);
 
-		/* set up intel bufmgr */
-		bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
-		igt_assert(bufmgr);
-		/* Do not enable reuse, we share (almost) all buffers. */
-		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
-		bufmgr2 = drm_intel_bufmgr_gem_init(intel_fd2, 4096);
-		igt_assert(bufmgr2);
-		drm_intel_bufmgr_gem_enable_reuse(bufmgr2);
-
 		/* set up nouveau bufmgr */
 		igt_assert(nouveau_device_wrap(nouveau_fd, 0, &ndev) >= 0);
 		igt_assert(nouveau_client_new(ndev, &nclient) >= 0);
@@ -374,11 +343,6 @@ igt_main
 		igt_assert(nouveau_device_wrap(nouveau_fd2, 0, &ndev2) >= 0);
 
 		igt_assert(nouveau_client_new(ndev2, &nclient2) >= 0);;
-
-		/* set up an intel batch buffer */
-		devid = intel_get_drm_devid(intel_fd);
-		intel_batch = intel_batchbuffer_alloc(bufmgr, devid);
-		igt_assert(intel_batch);
 	}
 
 #define xtest(name) \
@@ -399,12 +363,11 @@ igt_main
 	xtest(nv_self_import_to_different_fd);
 	
 	igt_fixture {
-		intel_batchbuffer_free(intel_batch);
-
 		nouveau_device_del(&ndev);
-		drm_intel_bufmgr_destroy(bufmgr);
 
 		close(intel_fd);
+		close(intel_fd2);
 		close(nouveau_fd);
+		close(nouveau_fd2);
 	}
 }
diff --git a/tests/prime_nv_pcopy.c b/tests/prime_nv_pcopy.c
index e465e5fc03..5b2a89d809 100644
--- a/tests/prime_nv_pcopy.c
+++ b/tests/prime_nv_pcopy.c
@@ -25,15 +25,12 @@
 #include <sys/ioctl.h>
 #include <errno.h>
 
-#include "intel_bufmgr.h"
+#include "i915/gem_create.h"
 #include "nouveau.h"
 
 static int intel_fd = -1, nouveau_fd = -1;
-static drm_intel_bufmgr *bufmgr;
 static struct nouveau_device *ndev;
 static struct nouveau_client *nclient;
-static uint32_t devid;
-static struct intel_batchbuffer *batch;
 static struct nouveau_object *nchannel, *pcopy;
 static struct nouveau_bufctx *nbufctx;
 static struct nouveau_pushbuf *npush;
@@ -161,16 +158,17 @@ BEGIN_NVXX(struct nouveau_pushbuf *push, int subc, int mthd, int size)
 }
 
 static void
-noop_intel(drm_intel_bo *bo)
+noop_intel(uint32_t bo_handle)
 {
-	BEGIN_BATCH(3, 1);
-	OUT_BATCH(MI_NOOP);
-	OUT_BATCH(MI_BATCH_BUFFER_END);
-	OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER,
-			I915_GEM_DOMAIN_RENDER, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
+	struct intel_bb *ibb;
+
+	ibb = intel_bb_create(intel_fd, 4096);
+	intel_bb_out(ibb, MI_NOOP);
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_emit_reloc(ibb, bo_handle, I915_GEM_DOMAIN_RENDER,
+			    I915_GEM_DOMAIN_RENDER, 0, 0);
+	intel_bb_flush_blit(ibb);
+	intel_bb_destroy(ibb);
 }
 
 static void find_and_open_devices(void)
@@ -548,25 +546,25 @@ static void test1_micro(void)
 	uint32_t dst_x = 0, dst_y = 0;
 	uint32_t x, y, w = 256, h = 64;
 
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
+	uint8_t *gtt_map;
 	int prime_fd;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", w * h, 4096);
-	igt_assert(test_intel_bo);
-	drm_intel_bo_set_tiling(test_intel_bo, &tiling, w);
-	igt_assert(tiling == I915_TILING_Y);
-	igt_assert(drm_intel_gem_bo_map_gtt(test_intel_bo) == 0);
+	intel_handle = gem_create(intel_fd, w * h);
+	gem_set_tiling(intel_fd, intel_handle, tiling, w);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
-	igt_assert_lte(0, prime_fd);
-	noop_intel(test_intel_bo);
+	gtt_map = gem_mmap__gtt(intel_fd, intel_handle, w * h, PROT_READ | PROT_WRITE);
+
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
+
+	noop_intel(intel_handle);
 
 	nv_bo_alloc(&bo_intel, &intel, w, h, tile_intel_y, prime_fd, 0);
 	nv_bo_alloc(&bo_nvidia, &nvidia, w, h, 0x10, -1, NOUVEAU_BO_VRAM);
 	nv_bo_alloc(&bo_linear, &linear, w, h, 0, -1, NOUVEAU_BO_GART);
 
 	for (y = 0; y < linear.h; ++y) {
-		uint8_t *map = bo_linear->map;
+		uint8_t *map = gtt_map;
 		map += y * linear.pitch;
 		for (x = 0; x < linear.pitch; ++x) {
 			uint8_t pos = x & 0x3f;
@@ -584,15 +582,16 @@ static void test1_micro(void)
 	if (pcopy)
 		perform_copy(bo_intel, &intel, dst_x, dst_y, bo_nvidia, &nvidia, src_x, src_y, w, h);
 	else
-		swtile_y(test_intel_bo->virtual, bo_linear->map, w, h);
+		swtile_y(gtt_map, bo_linear->map, w, h);
 
-	noop_intel(test_intel_bo);
-	check1_micro(test_intel_bo->virtual, intel.pitch, intel.h, dst_x, dst_y, w, h);
+	noop_intel(intel_handle);
+	check1_micro(gtt_map, intel.pitch, intel.h, dst_x, dst_y, w, h);
 
 	nouveau_bo_ref(NULL, &bo_linear);
 	nouveau_bo_ref(NULL, &bo_nvidia);
 	nouveau_bo_ref(NULL, &bo_intel);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_munmap(gtt_map, w * h);
+	gem_close(intel_fd, intel_handle);
 }
 
 /* test 2, see if we can copy from linear to intel X format safely
@@ -685,43 +684,40 @@ static void test3_base(int tile_src, int tile_dst)
 	uint32_t dst_x = 2 * cpp, dst_y = 26;
 	uint32_t w = 298 * cpp, h = 298;
 
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", 2048 * cpp * 768, 4096);
-	igt_assert(test_intel_bo);
-
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
-	igt_assert_lte(0, prime_fd);
+	intel_handle = gem_create(intel_fd, 2048 * cpp * 768);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
 	nv_bo_alloc(&bo_intel, &intel, 2048 * cpp, 768, tile_dst, prime_fd, 0);
 	nv_bo_alloc(&bo_nvidia, &nvidia, 300 * cpp, 300, tile_src, -1, NOUVEAU_BO_VRAM);
 	nv_bo_alloc(&bo_linear, &linear, 2048 * cpp, 768, 0, -1, NOUVEAU_BO_GART);
 
-	noop_intel(test_intel_bo);
+	noop_intel(intel_handle);
 	memset(bo_linear->map, 0x80, bo_linear->size);
 	perform_copy(bo_intel, &intel, 0, 0, bo_linear, &linear, 0, 0, linear.pitch, linear.h);
-	noop_intel(test_intel_bo);
+	noop_intel(intel_handle);
 
 	memset(bo_linear->map, 0x04, bo_linear->size);
 	perform_copy(bo_nvidia, &nvidia, 0, 0, bo_linear, &linear, 0, 0, nvidia.pitch, nvidia.h);
 
 	/* Perform the actual sub rectangle copy */
-	noop_intel(test_intel_bo);
+	noop_intel(intel_handle);
 	perform_copy(bo_intel, &intel, dst_x, dst_y, bo_nvidia, &nvidia, src_x, src_y, w, h);
-	noop_intel(test_intel_bo);
+	noop_intel(intel_handle);
 
 	memset(bo_linear->map, 0x3, bo_linear->size);
-	noop_intel(test_intel_bo);
+	noop_intel(intel_handle);
 	perform_copy(bo_linear, &linear, 0, 0, bo_intel, &intel, 0, 0, intel.pitch, intel.h);
-	noop_intel(test_intel_bo);
+	noop_intel(intel_handle);
 
 	check3(bo_linear->map, linear.pitch, linear.h, dst_x, dst_y, w, h);
 
 	nouveau_bo_ref(NULL, &bo_linear);
 	nouveau_bo_ref(NULL, &bo_nvidia);
 	nouveau_bo_ref(NULL, &bo_intel);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_close(intel_fd, intel_handle);
 }
 
 static void test3_1(void)
@@ -767,25 +763,23 @@ static void test3_5(void)
 /* Test only new style semaphores, old ones are AWFUL */
 static void test_semaphore(void)
 {
-	drm_intel_bo *test_intel_bo = NULL;
+	uint32_t intel_handle;
 	struct nouveau_bo *sema_bo = NULL;
 	int prime_fd;
-	uint32_t *sema;
+	uint32_t *sema, *gtt_map;
 	struct nouveau_pushbuf *push = npush;
 
 	igt_skip_on(ndev->chipset < 0x84);
 
 	/* Should probably be kept in sysmem */
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "semaphore bo", 4096, 4096);
-	igt_assert(test_intel_bo);
+	intel_handle = gem_create(intel_fd, 4096);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
-	igt_assert_lte(0, prime_fd);
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &sema_bo) == 0);
 	close(prime_fd);
 
-	igt_assert(drm_intel_gem_bo_map_gtt(test_intel_bo) == 0);
-	sema = test_intel_bo->virtual;
+	gtt_map = gem_mmap__gtt(intel_fd, intel_handle, 4096, PROT_READ | PROT_WRITE);
+	sema = gtt_map;
 	sema++;
 	*sema = 0;
 
@@ -845,7 +839,8 @@ static void test_semaphore(void)
 	igt_assert(*sema == 9);
 
 	nouveau_bo_ref(NULL, &sema_bo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_munmap(gtt_map, 4096);
+	gem_close(intel_fd, intel_handle);
 }
 
 igt_main
@@ -856,19 +851,8 @@ igt_main
 		igt_require(nouveau_fd != -1);
 		igt_require(intel_fd != -1);
 
-		/* set up intel bufmgr */
-		bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
-		igt_assert(bufmgr);
-		/* Do not enable reuse, we share (almost) all buffers. */
-		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
 		/* set up nouveau bufmgr */
 		init_nouveau();
-
-		/* set up an intel batch buffer */
-		devid = intel_get_drm_devid(intel_fd);
-		batch = intel_batchbuffer_alloc(bufmgr, devid);
-		igt_assert(batch);
 	}
 
 #define xtest(x, args...) \
@@ -893,11 +877,8 @@ igt_main
 		nouveau_pushbuf_del(&npush);
 		nouveau_object_del(&nchannel);
 
-		intel_batchbuffer_free(batch);
-
 		nouveau_client_del(&nclient);
 		nouveau_device_del(&ndev);
-		drm_intel_bufmgr_destroy(bufmgr);
 
 		close(intel_fd);
 		close(nouveau_fd);
diff --git a/tests/prime_nv_test.c b/tests/prime_nv_test.c
index 81d142f42e..bc2579604d 100644
--- a/tests/prime_nv_test.c
+++ b/tests/prime_nv_test.c
@@ -23,15 +23,13 @@
 #include <sys/stat.h>
 #include <sys/ioctl.h>
 
-#include "intel_bufmgr.h"
+#include "i915/gem_create.h"
 #include "nouveau.h"
 
 int intel_fd = -1, nouveau_fd = -1;
-drm_intel_bufmgr *bufmgr;
+struct buf_ops *bops;
 struct nouveau_device *ndev;
 struct nouveau_client *nclient;
-uint32_t devid;
-struct intel_batchbuffer *intel_batch;
 
 #define BO_SIZE (256*1024)
 
@@ -83,20 +81,18 @@ static int find_and_open_devices(void)
  */
 static void test_i915_nv_sharing(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-	igt_assert(test_intel_bo);
-
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_close(intel_fd, intel_handle);
 }
 
 /*
@@ -109,7 +105,7 @@ static void test_i915_nv_sharing(void)
  */
 static void test_nv_i915_sharing(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo;
 
@@ -117,12 +113,11 @@ static void test_nv_i915_sharing(void)
 				  0, BO_SIZE, NULL, &nvbo) == 0);
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
+	intel_handle = prime_fd_to_handle(intel_fd, prime_fd);
 	close(prime_fd);
-	igt_assert(test_intel_bo);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_close(intel_fd, intel_handle);
 }
 
 /*
@@ -131,14 +126,13 @@ static void test_nv_i915_sharing(void)
  */
 static void test_nv_write_i915_cpu_mmap_read(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL;
 	uint32_t *ptr;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
@@ -147,13 +141,12 @@ static void test_nv_write_i915_cpu_mmap_read(void)
 	ptr = nvbo->map;
 	*ptr = 0xdeadbeef;
 
-	drm_intel_bo_map(test_intel_bo, 1);
-	ptr = test_intel_bo->virtual;
-	igt_assert(ptr);
+	ptr = gem_mmap__cpu(intel_fd, intel_handle, 0, BO_SIZE, PROT_READ | PROT_WRITE);
 
 	igt_assert(*ptr == 0xdeadbeef);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_munmap(ptr, BO_SIZE);
+	gem_close(intel_fd, intel_handle);
 }
 
 /*
@@ -162,14 +155,13 @@ static void test_nv_write_i915_cpu_mmap_read(void)
  */
 static void test_nv_write_i915_gtt_mmap_read(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL;
 	uint32_t *ptr;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	intel_handle = gem_create(intel_fd, BO_SIZE);
+	prime_fd = prime_handle_to_fd(intel_fd, intel_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
@@ -177,14 +169,13 @@ static void test_nv_write_i915_gtt_mmap_read(void)
 	ptr = nvbo->map;
 	*ptr = 0xdeadbeef;
 
-	drm_intel_gem_bo_map_gtt(test_intel_bo);
-	ptr = test_intel_bo->virtual;
-	igt_assert(ptr);
+	ptr = gem_mmap__gtt(intel_fd, intel_handle, BO_SIZE, PROT_READ | PROT_WRITE);
 
 	igt_assert(*ptr == 0xdeadbeef);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_munmap(ptr, BO_SIZE);
+	gem_close(intel_fd, intel_handle);
 }
 
 /* test drm_intel_bo_map doesn't work properly,
@@ -192,7 +183,7 @@ static void test_nv_write_i915_gtt_mmap_read(void)
    for these objects */
 __noreturn static void test_i915_import_cpu_mmap(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo;
 	uint32_t *ptr;
@@ -202,22 +193,20 @@ __noreturn static void test_i915_import_cpu_mmap(void)
 	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
 				  0, BO_SIZE, NULL, &nvbo) == 0);
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
-	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
+	intel_handle = prime_fd_to_handle(intel_fd, prime_fd);
 	close(prime_fd);
-	igt_assert(test_intel_bo);
 
 	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
 
 	ptr = nvbo->map;
 	*ptr = 0xdeadbeef;
 
-	igt_assert(drm_intel_bo_map(test_intel_bo, 0) == 0);
-	igt_assert(test_intel_bo->virtual);
-	ptr = test_intel_bo->virtual;
+	ptr = gem_mmap__cpu(intel_fd, intel_handle, 0, BO_SIZE, PROT_READ);
 
 	igt_assert(*ptr == 0xdeadbeef);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_munmap(ptr, BO_SIZE);
+	gem_close(intel_fd, intel_handle);
 }
 
 /* test drm_intel_bo_map_gtt works properly,
@@ -225,7 +214,7 @@ __noreturn static void test_i915_import_cpu_mmap(void)
    for these objects */
 static void test_i915_import_gtt_mmap(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo;
 	uint32_t *ptr;
@@ -234,9 +223,8 @@ static void test_i915_import_gtt_mmap(void)
 				  0, BO_SIZE, NULL, &nvbo) == 0);
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
+	intel_handle = prime_fd_to_handle(intel_fd, prime_fd);
 	close(prime_fd);
-	igt_assert(test_intel_bo);
 
 	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
 
@@ -244,19 +232,18 @@ static void test_i915_import_gtt_mmap(void)
 	*ptr = 0xdeadbeef;
 	*(ptr + 1) = 0xa55a55;
 
-	igt_assert(drm_intel_gem_bo_map_gtt(test_intel_bo) == 0);
-	igt_assert(test_intel_bo->virtual);
-	ptr = test_intel_bo->virtual;
+	ptr = gem_mmap__gtt(intel_fd, intel_handle, BO_SIZE, PROT_READ | PROT_WRITE);
 
 	igt_assert(*ptr == 0xdeadbeef);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_munmap(ptr, BO_SIZE);
+	gem_close(intel_fd, intel_handle);
 }
 
 /* test 7 - import from nouveau into intel, test pread/pwrite fail */
 static void test_i915_import_pread_pwrite(void)
 {
-	drm_intel_bo *test_intel_bo;
+	uint32_t intel_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo;
 	uint32_t *ptr;
@@ -266,85 +253,90 @@ static void test_i915_import_pread_pwrite(void)
 				  0, BO_SIZE, NULL, &nvbo) == 0);
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
+	intel_handle = prime_fd_to_handle(intel_fd, prime_fd);
 	close(prime_fd);
-	igt_assert(test_intel_bo);
 
 	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
 
 	ptr = nvbo->map;
 	*ptr = 0xdeadbeef;
 
-	gem_read(intel_fd, test_intel_bo->handle, 0, buf, 256);
+	gem_read(intel_fd, intel_handle, 0, buf, 256);
 	igt_assert(buf[0] == 0xdeadbeef);
 	buf[0] = 0xabcdef55;
 
-	gem_write(intel_fd, test_intel_bo->handle, 0, buf, 4);
+	gem_write(intel_fd, intel_handle, 0, buf, 4);
 
 	igt_assert(*ptr == 0xabcdef55);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
-}
-
-static void
-set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
-{
-        int size = width * height;
-        uint32_t *vaddr;
-
-        drm_intel_gem_bo_start_gtt_access(bo, true);
-        vaddr = bo->virtual;
-        while (size--)
-                *vaddr++ = val;
+	gem_close(intel_fd, intel_handle);
 }
 
-static drm_intel_bo *
-create_bo(drm_intel_bufmgr *ibufmgr, uint32_t val, int width, int height)
+static uint32_t create_bo(uint32_t val, int width, int height)
 {
-        drm_intel_bo *bo;
+	uint32_t intel_handle;
+	int size = width * height;
+	uint32_t *ptr, *currptr;
 
-        bo = drm_intel_bo_alloc(ibufmgr, "bo", 4*width*height, 0);
-        igt_assert(bo);
+	intel_handle = gem_create(intel_fd, 4*width*height);
+	igt_assert(intel_handle);
 
         /* gtt map doesn't have a write parameter, so just keep the mapping
          * around (to avoid the set_domain with the gtt write domain set) and
          * manually tell the kernel when we start access the gtt. */
-        drm_intel_gem_bo_map_gtt(bo);
+	ptr = gem_mmap__gtt(intel_fd, intel_handle, size, PROT_READ | PROT_WRITE);
+	gem_set_domain(intel_fd, intel_handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+	currptr = ptr;
+	while (size--)
+		*currptr++ = val;
 
-        set_bo(bo, val, width, height);
+	gem_munmap(ptr, size);
 
-        return bo;
+	return intel_handle;
 }
 
 /* use intel hw to fill the BO with a blit from another BO,
    then readback from the nouveau bo, check value is correct */
 static void test_i915_blt_fill_nv_read(void)
 {
-	drm_intel_bo *test_intel_bo, *src_bo;
+	uint32_t dst_handle, src_handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL;
 	uint32_t *ptr;
+	struct intel_bb *ibb;
+	struct intel_buf src, dst;
+	int w = 256;
+	int h = 4; /* for intel_bb_copy size requirement % 4096 */
 
-	src_bo = create_bo(bufmgr, 0xaa55aa55, 256, 1);
+	ibb = intel_bb_create(intel_fd, 4096);
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	src_handle = create_bo(0xaa55aa55, w, h);
+	dst_handle = gem_create(intel_fd, BO_SIZE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, dst_handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
 
-	intel_copy_bo(intel_batch, test_intel_bo, src_bo, BO_SIZE);
+	intel_buf_init_using_handle(bops, src_handle, &src, w, h, 32, 0,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_buf_init_using_handle(bops, dst_handle, &dst, w, 256, 32, 0,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(ibb, &dst, &src, w * h * 4);
 
 	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
 
-	drm_intel_bo_map(test_intel_bo, 0);
-
 	ptr = nvbo->map;
 	igt_assert(*ptr == 0xaa55aa55);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+
+	intel_buf_destroy(&src);
+	intel_buf_destroy(&dst);
+	intel_bb_destroy(ibb);
+	gem_close(intel_fd, dst_handle);
+	gem_close(intel_fd, src_handle);
 }
 
 /* test 8 use nouveau to do blit */
@@ -358,20 +350,12 @@ igt_main
 
 		igt_require(nouveau_fd != -1);
 		igt_require(intel_fd != -1);
-
-		/* set up intel bufmgr */
-		bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
-		igt_assert(bufmgr);
-		/* Do not enable reuse, we share (almost) all buffers. */
-		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+		bops = buf_ops_create(intel_fd);
 
 		/* set up nouveau bufmgr */
 		igt_assert(nouveau_device_wrap(nouveau_fd, 0, &ndev) == 0);
 		igt_assert(nouveau_client_new(ndev, &nclient) == 0);
 
-		/* set up an intel batch buffer */
-		devid = intel_get_drm_devid(intel_fd);
-		intel_batch = intel_batchbuffer_alloc(bufmgr, devid);
 	}
 
 #define xtest(name) \
@@ -388,11 +372,9 @@ igt_main
 	xtest(i915_blt_fill_nv_read);
 
 	igt_fixture {
-		intel_batchbuffer_free(intel_batch);
-
 		nouveau_device_del(&ndev);
-		drm_intel_bufmgr_destroy(bufmgr);
 
+		buf_ops_destroy(bops);
 		close(intel_fd);
 		close(nouveau_fd);
 	}
-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 04/11] tests/drm_import_export: Remove the test

[Zbigniew Kempczyński]

Test exercises libdrm prime operations what is about to remove from IGT.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 tests/drm_import_export.c | 304 --------------------------------------
 tests/meson.build         |   1 -
 2 files changed, 305 deletions(-)
 delete mode 100644 tests/drm_import_export.c

diff --git a/tests/drm_import_export.c b/tests/drm_import_export.c
deleted file mode 100644
index 2dd2f3cb9f..0000000000
--- a/tests/drm_import_export.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * Copyright © 2014 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Daniel Vetter <daniel.vetter@ffwll.ch>
- */
-
-#include "igt.h"
-#include <stdio.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <stdlib.h>
-#include <string.h>
-#include <drm.h>
-#include <i915_drm.h>
-#include <xf86drm.h>
-#include <intel_bufmgr.h>
-#include <errno.h>
-#include <pthread.h>
-#include <unistd.h>
-#include <sys/syscall.h>
-
-#include "i915/gem.h"
-
-#define DURATION 10
-IGT_TEST_DESCRIPTION("Basic check to verify the behaviour of libdrm bo for prime/flink");
-
-int fd;
-drm_intel_bufmgr *bufmgr;
-int fd1;
-drm_intel_bufmgr *bufmgr1;
-
-bool use_flink;
-
-static void new_buffers(void)
-{
-	unsigned int *buf1;
-	drm_intel_bo *bo1, *bo2;
-
-
-	bo1 = drm_intel_bo_alloc(bufmgr, "buf1",16384, 4096);
-	igt_assert(bo1);
-	drm_intel_bo_map(bo1, 1);
-	bo2 = drm_intel_bo_alloc(bufmgr, "buf2", 16384, 4096);
-	igt_assert(bo2);
-	drm_intel_bo_map(bo2, 1);
-
-	buf1 = (unsigned int *)bo1->virtual;
-	igt_assert(buf1);
-	memset(buf1, 0, 16384);
-	buf1[4000]=0x05000000;
-
-	drm_intel_bo_exec(bo1, 16384, NULL, 0,0);
-	drm_intel_bo_wait_rendering(bo1);
-
-	drm_intel_bo_unmap( bo1 );
-	drm_intel_bo_unreference(bo1);
-
-	drm_intel_bo_unmap( bo2 );
-	drm_intel_bo_unreference(bo2);
-}
-
-static void test_surfaces(drm_intel_bo *bo_shared)
-{
-	drm_intel_bo * bo;
-	int loop=2;
-
-	while(loop--) {
-		if (use_flink) {
-			uint32_t name;
-			drm_intel_bo_flink(bo_shared, &name);
-			bo = drm_intel_bo_gem_create_from_name(bufmgr,
-							       "shared resource",
-							       name);
-		} else {
-			int prime_fd;
-
-			drm_intel_bo_gem_export_to_prime(bo_shared, &prime_fd);
-			bo = drm_intel_bo_gem_create_from_prime(bufmgr,
-								prime_fd, 4096);
-			close(prime_fd);
-		}
-
-		igt_assert(bo);
-		new_buffers();
-		drm_intel_bo_unreference(bo);
-	}
-}
-
-static void start_test(void)
-{
-	igt_until_timeout(DURATION) {
-		drm_intel_bo * bo_shared;
-
-		bo_shared = drm_intel_bo_alloc(bufmgr1, "buf-shared",16384, 4096);
-		test_surfaces(bo_shared);
-		drm_intel_bo_unreference(bo_shared);
-	}
-}
-
-static void * test_thread(void * par)
-{
-#ifdef __linux__
-	igt_debug("start %ld\n", (long) gettid());
-#else
-	igt_debug("start %ld\n", (long) pthread_self());
-#endif
-	start_test();
-
-	return NULL;
-}
-
-struct import_race_thread_data {
-	int prime_fd;
-	uint32_t flink_name;
-	unsigned int stop;
-	pthread_mutex_t mutex;
-};
-
-/*
- * Attempt to import the bo. It is possible that GEM_CLOSE was already called
- * in different thread and from i915 point of view the handle is no longer
- * valid (thus create_from_prime/name should fail).
- */
-static void *import_close_thread(void *data)
-{
-	struct import_race_thread_data *t = (struct import_race_thread_data *)data;
-	drm_intel_bo *bo;
-	pthread_mutex_lock(&t->mutex);
-	while (!t->stop) {
-		pthread_mutex_unlock(&t->mutex);
-		bo = NULL;
-		if (use_flink)
-			bo = drm_intel_bo_gem_create_from_name(bufmgr, "buf-shared", t->flink_name);
-		else {
-			pthread_mutex_lock(&t->mutex);
-			if (t->prime_fd != -1) {
-				bo = drm_intel_bo_gem_create_from_prime(bufmgr, t->prime_fd, 4096);
-				pthread_mutex_unlock(&t->mutex);
-			}
-			else
-				/* Lock should be held on entering the loop */
-				continue;
-		}
-
-		if (bo == NULL) {
-			/*
-			 * If the bo is NULL it means that we've unreferenced in other
-			 * thread - therefore we should expect ENOENT
-			 */
-			igt_assert_eq(errno, ENOENT);
-		} else {
-			drm_intel_bo_unreference(bo);
-		}
-
-		pthread_mutex_lock(&t->mutex);
-	}
-	pthread_mutex_unlock(&t->mutex);
-
-	return NULL;
-}
-
-/*
- * It is possible to race between unreference of the underlying BO and importing
- * it from prime_fd/name. Verify that the behaviour of libdrm is consistent for
- * prime/flink.
- */
-static void test_import_close_race(void)
-{
-	pthread_t t;
-	drm_intel_bo *bo;
-	struct import_race_thread_data t_data;
-
-	memset(&t_data, 0, sizeof(t_data));
-	pthread_mutex_init(&t_data.mutex, NULL);
-	t_data.prime_fd = -1;
-
-	igt_assert_eq(pthread_create(&t, NULL, import_close_thread , &t_data), 0);
-
-	igt_until_timeout(DURATION) {
-		bo = drm_intel_bo_alloc(bufmgr, "buf-shared", 4096, 4096);
-		igt_assert(bo != NULL);
-		/*
-		 * We setup the test in such way, that create_from_* can race between
-		 * unreference. If we're using prime, prime_fd is always a valid fd.
-		 */
-		if (use_flink)
-			igt_assert_eq(drm_intel_bo_flink(bo, &(t_data.flink_name)), 0);
-		else {
-			pthread_mutex_lock(&t_data.mutex);
-			igt_assert_eq(drm_intel_bo_gem_export_to_prime(bo, &(t_data.prime_fd)), 0);
-			igt_assert_neq(t_data.prime_fd, -1);
-			pthread_mutex_unlock(&t_data.mutex);
-		}
-
-		drm_intel_bo_unreference(bo);
-
-		pthread_mutex_lock(&t_data.mutex);
-		close(t_data.prime_fd);
-		t_data.prime_fd = -1;
-		pthread_mutex_unlock(&t_data.mutex);
-	}
-
-	pthread_mutex_lock(&t_data.mutex);
-	t_data.stop = 1;
-	pthread_mutex_unlock(&t_data.mutex);
-
-	pthread_join(t, NULL);
-	pthread_mutex_destroy(&t_data.mutex);
-}
-
-pthread_t test_thread_id1;
-pthread_t test_thread_id2;
-pthread_t test_thread_id3;
-pthread_t test_thread_id4;
-
-igt_main {
-	igt_fixture {
-		fd1 = drm_open_driver(DRIVER_INTEL);
-		igt_require_gem(fd1);
-
-		bufmgr1 = drm_intel_bufmgr_gem_init(fd1, 8 *1024);
-		igt_require(bufmgr1);
-
-		drm_intel_bufmgr_gem_enable_reuse(bufmgr1);
-
-		fd = gem_reopen_driver(fd1);
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 8 *1024);
-		igt_assert(bufmgr);
-
-		drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-	}
-
-	igt_describe("Verify whether the behaviour of libdrm"
-		     " is consistent for flink or not.");
-	igt_subtest("import-close-race-flink") {
-		use_flink = true;
-		test_import_close_race();
-	}
-
-	igt_describe("Verify whether the behaviour of libdrm"
-		     " is consistent for prime or not.");
-	igt_subtest("import-close-race-prime") {
-		use_flink = false;
-		test_import_close_race();
-	}
-
-	igt_describe("Multithreaded test to validate the (lack of) locking in"
-		     " the flink code in libdrm.");
-	igt_subtest("flink") {
-		use_flink = true;
-
-		pthread_create(&test_thread_id1, NULL, test_thread, NULL);
-		pthread_create(&test_thread_id2, NULL, test_thread, NULL);
-		pthread_create(&test_thread_id3, NULL, test_thread, NULL);
-		pthread_create(&test_thread_id4, NULL, test_thread, NULL);
-
-		pthread_join(test_thread_id1, NULL);
-		pthread_join(test_thread_id2, NULL);
-		pthread_join(test_thread_id3, NULL);
-		pthread_join(test_thread_id4, NULL);
-	}
-
-	igt_describe("Multithreaded test to validate the (lack of) locking in"
-		     " the prime code in libdrm.");
-	igt_subtest("prime") {
-		use_flink = false;
-
-		pthread_create(&test_thread_id1, NULL, test_thread, NULL);
-		pthread_create(&test_thread_id2, NULL, test_thread, NULL);
-		pthread_create(&test_thread_id3, NULL, test_thread, NULL);
-		pthread_create(&test_thread_id4, NULL, test_thread, NULL);
-
-		pthread_join(test_thread_id1, NULL);
-		pthread_join(test_thread_id2, NULL);
-		pthread_join(test_thread_id3, NULL);
-		pthread_join(test_thread_id4, NULL);
-	}
-
-	igt_fixture {
-		close(fd);
-		close(fd1);
-	}
-}
diff --git a/tests/meson.build b/tests/meson.build
index 619c18b251..c6fe6a3ce6 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -10,7 +10,6 @@ test_progs = [
 	'dmabuf_sync_file',
 	'device_reset',
 	'drm_buddy',
-	'drm_import_export',
 	'drm_mm',
 	'drm_read',
 	'fbdev',
-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 05/11] benchmarks/intel_upload_blit_*: Remove libdrm in upload blits

[Zbigniew Kempczyński]

Few benchmarks still used libdrm so let's rewrite them to be libdrm
free. I tried to mimic the libdrm behavior as much as possible but
according how libdrm caches handles/mappings there may be some
differences in performance execution.

v2: Move benchmarks to scope without libdrm in meson.build

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 benchmarks/intel_upload_blit_large.c     | 131 ++++++++++++---------
 benchmarks/intel_upload_blit_large_gtt.c | 130 ++++++++++++---------
 benchmarks/intel_upload_blit_large_map.c | 132 ++++++++++++---------
 benchmarks/intel_upload_blit_small.c     | 139 ++++++++++++++---------
 benchmarks/meson.build                   |  13 +--
 5 files changed, 315 insertions(+), 230 deletions(-)

diff --git a/benchmarks/intel_upload_blit_large.c b/benchmarks/intel_upload_blit_large.c
index 12bbae3d06..af52d7a4e5 100644
--- a/benchmarks/intel_upload_blit_large.c
+++ b/benchmarks/intel_upload_blit_large.c
@@ -45,6 +45,7 @@
  */
 
 #include "igt.h"
+#include "i915/gem_create.h"
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -72,74 +73,99 @@ get_time_in_secs(void)
 }
 
 static void
-do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
-	  drm_intel_bo *dst_bo, int width, int height)
+do_render(int i915, uint32_t dst_handle)
 {
-	uint32_t data[width * height];
-	drm_intel_bo *src_bo;
-	int i;
+	struct drm_i915_gem_execbuffer2 exec = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	struct drm_i915_gem_relocation_entry reloc[2];
 	static uint32_t seed = 1;
+	uint32_t data[OBJECT_WIDTH * OBJECT_HEIGHT];
+	uint64_t size = OBJECT_WIDTH * OBJECT_HEIGHT * 4, bb_size = 4096;
+	uint32_t src_handle, bb_handle, *bb;
+	uint32_t gen = intel_gen(intel_get_drm_devid(i915));
+	const bool has_64b_reloc = gen >= 8;
+	int i;
+
+	bb_handle = gem_create_from_pool(i915, &bb_size, REGION_SMEM);
+	src_handle = gem_create_from_pool(i915, &size, REGION_SMEM);
 
-	/* Generate some junk.  Real workloads would be doing a lot more
-	 * work to generate the junk.
-	 */
-	for (i = 0; i < width * height; i++) {
+	for (i = 0; i < OBJECT_WIDTH * OBJECT_HEIGHT; i++)
 		data[i] = seed++;
-	}
 
-	/* Upload the junk. */
-	src_bo = drm_intel_bo_alloc(bufmgr, "src", sizeof(data), 4096);
-	drm_intel_bo_subdata(src_bo, 0, sizeof(data), data);
+	gem_write(i915, src_handle, 0, data, sizeof(data));
 
 	/* Render the junk to the dst. */
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	bb = gem_mmap__device_coherent(i915, bb_handle, 0, bb_size, PROT_WRITE);
+	i = 0;
+	bb[i++] = XY_SRC_COPY_BLT_CMD |
+		  XY_SRC_COPY_BLT_WRITE_ALPHA |
+		  XY_SRC_COPY_BLT_WRITE_RGB |
+		  (6 + 2*(gen >= 8));
+	bb[i++] = (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
-		  (width * 4) /* dst pitch */);
-	OUT_BATCH(0); /* dst x1,y1 */
-	OUT_BATCH((height << 16) | width); /* dst x2,y2 */
-	OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0); /* src x1,y1 */
-	OUT_BATCH(width * 4); /* src pitch */
-	OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
-
-	drm_intel_bo_unreference(src_bo);
+		  (OBJECT_WIDTH * 4) /* dst pitch */;
+	bb[i++] = 0; /* dst x1,y1 */
+	bb[i++] = (OBJECT_HEIGHT << 16) | OBJECT_WIDTH; /* dst x2,y2 */
+
+	obj[0].handle = dst_handle;
+	obj[0].offset = dst_handle * size;
+	reloc[0].target_handle = dst_handle;
+	reloc[0].presumed_offset = obj[0].offset;
+	reloc[0].offset = sizeof(uint32_t) * i;
+	reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
+	bb[i++] = obj[0].offset;
+	if (has_64b_reloc)
+		bb[i++] = obj[0].offset >> 32;
+
+	bb[i++] = 0; /* src x1,y1 */
+	bb[i++] = OBJECT_WIDTH * 4; /* src pitch */
+
+	obj[1].handle = src_handle;
+	obj[1].offset = src_handle * size;
+	reloc[1].target_handle = src_handle;
+	reloc[1].presumed_offset = obj[1].offset;
+	reloc[1].offset = sizeof(uint32_t) * i;
+	reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc[1].write_domain = 0;
+	bb[i++] = obj[1].offset;
+	if (has_64b_reloc)
+		bb[i++] = obj[1].offset >> 32;
+
+	obj[2].handle = bb_handle;
+	obj[2].relocs_ptr = to_user_pointer(reloc);
+	obj[2].relocation_count = 2;
+
+	bb[i++] = MI_BATCH_BUFFER_END;
+	gem_munmap(bb, bb_size);
+
+	exec.buffers_ptr = to_user_pointer(obj);
+	exec.buffer_count = 3;
+	exec.flags = gen >= 6 ? I915_EXEC_BLT : 0 | I915_EXEC_NO_RELOC;
+
+	gem_execbuf(i915, &exec);
 }
 
 int main(int argc, char **argv)
 {
-	int fd;
-	int object_size = OBJECT_WIDTH * OBJECT_HEIGHT * 4;
 	double start_time, end_time;
-	drm_intel_bo *dst_bo;
-	drm_intel_bufmgr *bufmgr;
-	struct intel_batchbuffer *batch;
-	int i;
-
-	fd = drm_open_driver(DRIVER_INTEL);
+	uint32_t dst_handle;
+	int i915, i;
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
-
-	dst_bo = drm_intel_bo_alloc(bufmgr, "dst", object_size, 4096);
+	i915 = drm_open_driver(DRIVER_INTEL);
+	dst_handle = gem_create(i915, OBJECT_WIDTH * OBJECT_HEIGHT * 4);
 
 	/* Prep loop to get us warmed up. */
-	for (i = 0; i < 60; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
-	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	for (i = 0; i < 60; i++)
+		do_render(i915, dst_handle);
+	gem_sync(i915, dst_handle);
 
 	/* Do the actual timing. */
 	start_time = get_time_in_secs();
-	for (i = 0; i < 200; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
-	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	for (i = 0; i < 200; i++)
+		do_render(i915, dst_handle);
+	gem_sync(i915, dst_handle);
+
 	end_time = get_time_in_secs();
 
 	printf("%d iterations in %.03f secs: %.01f MB/sec\n", i,
@@ -147,10 +173,5 @@ int main(int argc, char **argv)
 	       (double)i * OBJECT_WIDTH * OBJECT_HEIGHT * 4 / 1024.0 / 1024.0 /
 	       (end_time - start_time));
 
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
-
-	close(fd);
-
-	return 0;
+	close(i915);
 }
diff --git a/benchmarks/intel_upload_blit_large_gtt.c b/benchmarks/intel_upload_blit_large_gtt.c
index 0b704b57d4..1e991a6b24 100644
--- a/benchmarks/intel_upload_blit_large_gtt.c
+++ b/benchmarks/intel_upload_blit_large_gtt.c
@@ -45,6 +45,7 @@
  */
 
 #include "igt.h"
+#include "i915/gem_create.h"
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -69,74 +70,98 @@ get_time_in_secs(void)
 }
 
 static void
-do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
-	  drm_intel_bo *dst_bo, int width, int height)
+do_render(int i915, uint32_t dst_handle)
 {
-	uint32_t *data;
-	drm_intel_bo *src_bo;
-	int i;
+	struct drm_i915_gem_execbuffer2 exec = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	struct drm_i915_gem_relocation_entry reloc[2];
 	static uint32_t seed = 1;
+	uint64_t size = OBJECT_WIDTH * OBJECT_HEIGHT * 4, bb_size = 4096;
+	uint32_t *data, src_handle, bb_handle, *bb;
+	uint32_t gen = intel_gen(intel_get_drm_devid(i915));
+	const bool has_64b_reloc = gen >= 8;
+	int i;
 
-	src_bo = drm_intel_bo_alloc(bufmgr, "src", width * height * 4, 4096);
-
-	drm_intel_gem_bo_map_gtt(src_bo);
+	bb_handle = gem_create_from_pool(i915, &bb_size, REGION_SMEM);
+	src_handle = gem_create_from_pool(i915, &size, REGION_SMEM);
 
-	data = src_bo->virtual;
-	for (i = 0; i < width * height; i++) {
+	data = gem_mmap__gtt(i915, src_handle, size, PROT_WRITE);
+	for (i = 0; i < OBJECT_WIDTH * OBJECT_HEIGHT; i++)
 		data[i] = seed++;
-	}
-
-	drm_intel_gem_bo_unmap_gtt(src_bo);
+	gem_munmap(data, size);
 
 	/* Render the junk to the dst. */
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	bb = gem_mmap__device_coherent(i915, bb_handle, 0, bb_size, PROT_WRITE);
+	i = 0;
+	bb[i++] = XY_SRC_COPY_BLT_CMD |
+		  XY_SRC_COPY_BLT_WRITE_ALPHA |
+		  XY_SRC_COPY_BLT_WRITE_RGB |
+		  (6 + 2*(gen >= 8));
+	bb[i++] = (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
-		  (width * 4) /* dst pitch */);
-	OUT_BATCH(0); /* dst x1,y1 */
-	OUT_BATCH((height << 16) | width); /* dst x2,y2 */
-	OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0); /* src x1,y1 */
-	OUT_BATCH(width * 4); /* src pitch */
-	OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
-
-	drm_intel_bo_unreference(src_bo);
+		  (OBJECT_WIDTH * 4) /* dst pitch */;
+	bb[i++] = 0; /* dst x1,y1 */
+	bb[i++] = (OBJECT_HEIGHT << 16) | OBJECT_WIDTH; /* dst x2,y2 */
+
+	obj[0].handle = dst_handle;
+	obj[0].offset = dst_handle * size;
+	reloc[0].target_handle = dst_handle;
+	reloc[0].presumed_offset = obj[0].offset;
+	reloc[0].offset = sizeof(uint32_t) * i;
+	reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
+	bb[i++] = obj[0].offset;
+	if (has_64b_reloc)
+		bb[i++] = obj[0].offset >> 32;
+
+	bb[i++] = 0; /* src x1,y1 */
+	bb[i++] = OBJECT_WIDTH * 4; /* src pitch */
+
+	obj[1].handle = src_handle;
+	obj[1].offset = src_handle * size;
+	reloc[1].target_handle = src_handle;
+	reloc[1].presumed_offset = obj[1].offset;
+	reloc[1].offset = sizeof(uint32_t) * i;
+	reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc[1].write_domain = 0;
+	bb[i++] = obj[1].offset;
+	if (has_64b_reloc)
+		bb[i++] = obj[1].offset >> 32;
+
+	obj[2].handle = bb_handle;
+	obj[2].relocs_ptr = to_user_pointer(reloc);
+	obj[2].relocation_count = 2;
+
+	bb[i++] = MI_BATCH_BUFFER_END;
+	gem_munmap(bb, bb_size);
+
+	exec.buffers_ptr = to_user_pointer(obj);
+	exec.buffer_count = 3;
+	exec.flags = gen >= 6 ? I915_EXEC_BLT : 0 | I915_EXEC_NO_RELOC;
+
+	gem_execbuf(i915, &exec);
 }
 
 int main(int argc, char **argv)
 {
-	int fd;
-	int object_size = OBJECT_WIDTH * OBJECT_HEIGHT * 4;
 	double start_time, end_time;
-	drm_intel_bo *dst_bo;
-	drm_intel_bufmgr *bufmgr;
-	struct intel_batchbuffer *batch;
-	int i;
-
-	fd = drm_open_driver(DRIVER_INTEL);
+	uint32_t dst_handle;
+	int i915, i;
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
-
-	dst_bo = drm_intel_bo_alloc(bufmgr, "dst", object_size, 4096);
+	i915 = drm_open_driver(DRIVER_INTEL);
+	dst_handle = gem_create(i915, OBJECT_WIDTH * OBJECT_HEIGHT * 4);
 
 	/* Prep loop to get us warmed up. */
-	for (i = 0; i < 60; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
-	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	for (i = 0; i < 60; i++)
+		do_render(i915, dst_handle);
+	gem_sync(i915, dst_handle);
 
 	/* Do the actual timing. */
 	start_time = get_time_in_secs();
-	for (i = 0; i < 200; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
-	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	for (i = 0; i < 200; i++)
+		do_render(i915, dst_handle);
+	gem_sync(i915, dst_handle);
+
 	end_time = get_time_in_secs();
 
 	printf("%d iterations in %.03f secs: %.01f MB/sec\n", i,
@@ -144,10 +169,5 @@ int main(int argc, char **argv)
 	       (double)i * OBJECT_WIDTH * OBJECT_HEIGHT * 4 / 1024.0 / 1024.0 /
 	       (end_time - start_time));
 
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
-
-	close(fd);
-
-	return 0;
+	close(i915);
 }
diff --git a/benchmarks/intel_upload_blit_large_map.c b/benchmarks/intel_upload_blit_large_map.c
index ae05434f26..6d3cd748cf 100644
--- a/benchmarks/intel_upload_blit_large_map.c
+++ b/benchmarks/intel_upload_blit_large_map.c
@@ -48,6 +48,7 @@
  */
 
 #include "igt.h"
+#include "i915/gem_create.h"
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -72,74 +73,99 @@ get_time_in_secs(void)
 }
 
 static void
-do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
-	  drm_intel_bo *dst_bo, int width, int height)
+do_render(int i915, uint32_t dst_handle)
 {
-	uint32_t *data;
-	drm_intel_bo *src_bo;
-	int i;
+	struct drm_i915_gem_execbuffer2 exec = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	struct drm_i915_gem_relocation_entry reloc[2];
 	static uint32_t seed = 1;
+	uint64_t size = OBJECT_WIDTH * OBJECT_HEIGHT * 4, bb_size = 4096;
+	uint32_t *data, src_handle, bb_handle, *bb;
+	uint32_t gen = intel_gen(intel_get_drm_devid(i915));
+	const bool has_64b_reloc = gen >= 8;
+	int i;
 
-	src_bo = drm_intel_bo_alloc(bufmgr, "src", width * height * 4, 4096);
-
-	drm_intel_bo_map(src_bo, 1);
+	bb_handle = gem_create_from_pool(i915, &bb_size, REGION_SMEM);
+	src_handle = gem_create_from_pool(i915, &size, REGION_SMEM);
 
-	data = src_bo->virtual;
-	for (i = 0; i < width * height; i++) {
+	data = gem_mmap__cpu(i915, src_handle, 0, size, PROT_WRITE);
+	for (i = 0; i < OBJECT_WIDTH * OBJECT_HEIGHT; i++)
 		data[i] = seed++;
-	}
-
-	drm_intel_bo_unmap(src_bo);
+	gem_set_domain(i915, src_handle, I915_GEM_DOMAIN_CPU, 0);
+	gem_munmap(data, size);
 
 	/* Render the junk to the dst. */
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	bb = gem_mmap__device_coherent(i915, bb_handle, 0, bb_size, PROT_WRITE);
+	i = 0;
+	bb[i++] = XY_SRC_COPY_BLT_CMD |
+		  XY_SRC_COPY_BLT_WRITE_ALPHA |
+		  XY_SRC_COPY_BLT_WRITE_RGB |
+		  (6 + 2*(gen >= 8));
+	bb[i++] = (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
-		  (width * 4) /* dst pitch */);
-	OUT_BATCH(0); /* dst x1,y1 */
-	OUT_BATCH((height << 16) | width); /* dst x2,y2 */
-	OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0); /* src x1,y1 */
-	OUT_BATCH(width * 4); /* src pitch */
-	OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
-
-	drm_intel_bo_unreference(src_bo);
+		  (OBJECT_WIDTH * 4) /* dst pitch */;
+	bb[i++] = 0; /* dst x1,y1 */
+	bb[i++] = (OBJECT_HEIGHT << 16) | OBJECT_WIDTH; /* dst x2,y2 */
+
+	obj[0].handle = dst_handle;
+	obj[0].offset = dst_handle * size;
+	reloc[0].target_handle = dst_handle;
+	reloc[0].presumed_offset = obj[0].offset;
+	reloc[0].offset = sizeof(uint32_t) * i;
+	reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
+	bb[i++] = obj[0].offset;
+	if (has_64b_reloc)
+		bb[i++] = obj[0].offset >> 32;
+
+	bb[i++] = 0; /* src x1,y1 */
+	bb[i++] = OBJECT_WIDTH * 4; /* src pitch */
+
+	obj[1].handle = src_handle;
+	obj[1].offset = src_handle * size;
+	reloc[1].target_handle = src_handle;
+	reloc[1].presumed_offset = obj[1].offset;
+	reloc[1].offset = sizeof(uint32_t) * i;
+	reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc[1].write_domain = 0;
+	bb[i++] = obj[1].offset;
+	if (has_64b_reloc)
+		bb[i++] = obj[1].offset >> 32;
+
+	obj[2].handle = bb_handle;
+	obj[2].relocs_ptr = to_user_pointer(reloc);
+	obj[2].relocation_count = 2;
+
+	bb[i++] = MI_BATCH_BUFFER_END;
+	gem_munmap(bb, bb_size);
+
+	exec.buffers_ptr = to_user_pointer(obj);
+	exec.buffer_count = 3;
+	exec.flags = gen >= 6 ? I915_EXEC_BLT : 0 | I915_EXEC_NO_RELOC;
+
+	gem_execbuf(i915, &exec);
 }
 
 int main(int argc, char **argv)
 {
-	int fd;
-	int object_size = OBJECT_WIDTH * OBJECT_HEIGHT * 4;
 	double start_time, end_time;
-	drm_intel_bo *dst_bo;
-	drm_intel_bufmgr *bufmgr;
-	struct intel_batchbuffer *batch;
-	int i;
-
-	fd = drm_open_driver(DRIVER_INTEL);
+	uint32_t dst_handle;
+	int i915, i;
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
-
-	dst_bo = drm_intel_bo_alloc(bufmgr, "dst", object_size, 4096);
+	i915 = drm_open_driver(DRIVER_INTEL);
+	dst_handle = gem_create(i915, OBJECT_WIDTH * OBJECT_HEIGHT * 4);
 
 	/* Prep loop to get us warmed up. */
-	for (i = 0; i < 60; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
-	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	for (i = 0; i < 60; i++)
+		do_render(i915, dst_handle);
+	gem_sync(i915, dst_handle);
 
 	/* Do the actual timing. */
 	start_time = get_time_in_secs();
-	for (i = 0; i < 200; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
-	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	for (i = 0; i < 200; i++)
+		do_render(i915, dst_handle);
+	gem_sync(i915, dst_handle);
+
 	end_time = get_time_in_secs();
 
 	printf("%d iterations in %.03f secs: %.01f MB/sec\n", i,
@@ -147,10 +173,6 @@ int main(int argc, char **argv)
 	       (double)i * OBJECT_WIDTH * OBJECT_HEIGHT * 4 / 1024.0 / 1024.0 /
 	       (end_time - start_time));
 
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
-
-	close(fd);
-
-	return 0;
+	close(i915);
 }
+
diff --git a/benchmarks/intel_upload_blit_small.c b/benchmarks/intel_upload_blit_small.c
index 7e3346eb74..525d68e36a 100644
--- a/benchmarks/intel_upload_blit_small.c
+++ b/benchmarks/intel_upload_blit_small.c
@@ -41,6 +41,7 @@
  */
 
 #include "igt.h"
+#include "i915/gem_create.h"
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -66,21 +67,27 @@ get_time_in_secs(void)
 }
 
 static void
-do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
-	  drm_intel_bo *dst_bo, int width, int height)
+do_render(int i915, uint32_t dst_handle)
 {
-	uint32_t data[64];
-	drm_intel_bo *src_bo;
-	int i;
+	struct drm_i915_gem_execbuffer2 exec = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	struct drm_i915_gem_relocation_entry reloc[2];
 	static uint32_t seed = 1;
+	uint32_t data[OBJECT_WIDTH * OBJECT_HEIGHT];
+	uint64_t size = OBJECT_WIDTH * OBJECT_HEIGHT * 4, bb_size = 4096;
+	uint32_t src_handle, bb_handle, *bb;
+	uint32_t gen = intel_gen(intel_get_drm_devid(i915));
+	const bool has_64b_reloc = gen >= 8;
+	int i;
 
-	src_bo = drm_intel_bo_alloc(bufmgr, "src", width * height * 4, 4096);
+	bb_handle = gem_create_from_pool(i915, &bb_size, REGION_SMEM);
+	src_handle = gem_create_from_pool(i915, &size, REGION_SMEM);
 
 	/* Upload some junk.  Real workloads would be doing a lot more
 	 * work to generate the junk.
 	 */
-	for (i = 0; i < width * height;) {
-		int size, j;
+	for (i = 0; i < OBJECT_WIDTH * OBJECT_HEIGHT; i++) {
+		int subsize, j;
 
 		/* Choose a size from 1 to 64 dwords to upload.
 		 * Normal workloads have a distribution of sizes with a
@@ -88,68 +95,92 @@ do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
 		 * pile of vertices, most likely), but I'm trying to get at
 		 * the cost of the small uploads here.
 		 */
-		size = random() % 64 + 1;
-		if (i + size > width * height)
-			size = width * height - i;
+		subsize = random() % 64 + 1;
+		if (i + subsize > OBJECT_WIDTH * OBJECT_HEIGHT)
+			subsize = OBJECT_WIDTH * OBJECT_HEIGHT - i;
 
-		for (j = 0; j < size; j++)
+		for (j = 0; j < subsize; j++)
 			data[j] = seed++;
 
 		/* Upload the junk. */
-		drm_intel_bo_subdata(src_bo, i * 4, size * 4, data);
+		//drm_intel_bo_subdata(src_bo, i * 4, size * 4, data);
+		gem_write(i915, src_handle, i * 4, data, subsize * 4);
 
-		i += size;
+		i += subsize;
 	}
 
 	/* Render the junk to the dst. */
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	bb = gem_mmap__device_coherent(i915, bb_handle, 0, bb_size, PROT_WRITE);
+	i = 0;
+	bb[i++] = XY_SRC_COPY_BLT_CMD |
+		  XY_SRC_COPY_BLT_WRITE_ALPHA |
+		  XY_SRC_COPY_BLT_WRITE_RGB |
+		  (6 + 2*(gen >= 8));
+	bb[i++] = (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
-		  (width * 4) /* dst pitch */);
-	OUT_BATCH(0); /* dst x1,y1 */
-	OUT_BATCH((height << 16) | width); /* dst x2,y2 */
-	OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0); /* src x1,y1 */
-	OUT_BATCH(width * 4); /* src pitch */
-	OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
-
-	drm_intel_bo_unreference(src_bo);
+		  (OBJECT_WIDTH * 4) /* dst pitch */;
+	bb[i++] = 0; /* dst x1,y1 */
+	bb[i++] = (OBJECT_HEIGHT << 16) | OBJECT_WIDTH; /* dst x2,y2 */
+
+	obj[0].handle = dst_handle;
+	obj[0].offset = dst_handle * size;
+	reloc[0].target_handle = dst_handle;
+	reloc[0].presumed_offset = obj[0].offset;
+	reloc[0].offset = sizeof(uint32_t) * i;
+	reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
+	bb[i++] = obj[0].offset;
+	if (has_64b_reloc)
+		bb[i++] = obj[0].offset >> 32;
+
+	bb[i++] = 0; /* src x1,y1 */
+	bb[i++] = OBJECT_WIDTH * 4; /* src pitch */
+
+	obj[1].handle = src_handle;
+	obj[1].offset = src_handle * size;
+	reloc[1].target_handle = src_handle;
+	reloc[1].presumed_offset = obj[1].offset;
+	reloc[1].offset = sizeof(uint32_t) * i;
+	reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc[1].write_domain = 0;
+	bb[i++] = obj[1].offset;
+	if (has_64b_reloc)
+		bb[i++] = obj[1].offset >> 32;
+
+	obj[2].handle = bb_handle;
+	obj[2].relocs_ptr = to_user_pointer(reloc);
+	obj[2].relocation_count = 2;
+
+	bb[i++] = MI_BATCH_BUFFER_END;
+	gem_munmap(bb, bb_size);
+
+	exec.buffers_ptr = to_user_pointer(obj);
+	exec.buffer_count = 3;
+	exec.flags = gen >= 6 ? I915_EXEC_BLT : 0 | I915_EXEC_NO_RELOC;
+
+	gem_execbuf(i915, &exec);
 }
 
 int main(int argc, char **argv)
 {
-	int fd;
-	int object_size = OBJECT_WIDTH * OBJECT_HEIGHT * 4;
 	double start_time, end_time;
-	drm_intel_bo *dst_bo;
-	drm_intel_bufmgr *bufmgr;
-	struct intel_batchbuffer *batch;
-	int i;
-
-	fd = drm_open_driver(DRIVER_INTEL);
-
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+	uint32_t dst_handle;
+	int i915, i;
 
-	dst_bo = drm_intel_bo_alloc(bufmgr, "dst", object_size, 4096);
+	i915 = drm_open_driver(DRIVER_INTEL);
+	dst_handle = gem_create(i915, OBJECT_WIDTH * OBJECT_HEIGHT * 4);
 
 	/* Prep loop to get us warmed up. */
-	for (i = 0; i < 20; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
-	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	for (i = 0; i < 60; i++)
+		do_render(i915, dst_handle);
+	gem_sync(i915, dst_handle);
 
 	/* Do the actual timing. */
 	start_time = get_time_in_secs();
-	for (i = 0; i < 1000; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
-	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	for (i = 0; i < 1000; i++)
+		do_render(i915, dst_handle);
+	gem_sync(i915, dst_handle);
+
 	end_time = get_time_in_secs();
 
 	printf("%d iterations in %.03f secs: %.01f MB/sec\n", i,
@@ -157,10 +188,6 @@ int main(int argc, char **argv)
 	       (double)i * OBJECT_WIDTH * OBJECT_HEIGHT * 4 / 1024.0 / 1024.0 /
 	       (end_time - start_time));
 
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
-
-	close(fd);
-
-	return 0;
+	close(i915);
 }
+
diff --git a/benchmarks/meson.build b/benchmarks/meson.build
index 98a08e25cd..c451268bc4 100644
--- a/benchmarks/meson.build
+++ b/benchmarks/meson.build
@@ -13,20 +13,15 @@ benchmark_progs = [
 	'gem_syslatency',
 	'gem_userptr_benchmark',
 	'gem_wsim',
+	'intel_upload_blit_large',
+	'intel_upload_blit_large_gtt',
+	'intel_upload_blit_large_map',
+	'intel_upload_blit_small',
 	'kms_vblank',
 	'prime_lookup',
 	'vgem_mmap',
 ]
 
-if libdrm_intel.found()
-	benchmark_progs += [
-		'intel_upload_blit_large',
-		'intel_upload_blit_large_gtt',
-		'intel_upload_blit_large_map',
-		'intel_upload_blit_small',
-	]
-endif
-
 benchmarksdir = join_paths(libexecdir, 'benchmarks')
 
 foreach prog : benchmark_progs
-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 06/11] lib/intel_batchbuffer: Get rid of libdrm batchbuffer

[Zbigniew Kempczyński]

As few remnants were rewritten (prime_udl, prime_nv_*, benchmarks)
we can finally remove libdrm code in intel_batchbuffer.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 lib/intel_batchbuffer.c | 575 +---------------------------------------
 lib/intel_batchbuffer.h | 248 -----------------
 2 files changed, 2 insertions(+), 821 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 5c76fdb1b0..b8f11730e6 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -37,7 +37,6 @@
 #include "drmtest.h"
 #include "i915/gem_create.h"
 #include "intel_batchbuffer.h"
-#include "intel_bufmgr.h"
 #include "intel_bufops.h"
 #include "intel_chipset.h"
 #include "intel_reg.h"
@@ -66,16 +65,6 @@
  * @title: Batch Buffer
  * @include: igt.h
  *
- * This library provides some basic support for batchbuffers and using the
- * blitter engine based upon libdrm. A new batchbuffer is allocated with
- * intel_batchbuffer_alloc() and for simple blitter commands submitted with
- * intel_batchbuffer_flush().
- *
- * It also provides some convenient macros to easily emit commands into
- * batchbuffers. All those macros presume that a pointer to a #intel_batchbuffer
- * structure called batch is in scope. The basic macros are #BEGIN_BATCH,
- * #OUT_BATCH, #OUT_RELOC and #ADVANCE_BATCH.
- *
  * Note that this library's header pulls in the [i-g-t core](igt-gpu-tools-i-g-t-core.html)
  * library as a dependency.
  */
@@ -84,515 +73,13 @@ static bool intel_bb_do_tracking;
 static IGT_LIST_HEAD(intel_bb_list);
 static pthread_mutex_t intel_bb_list_lock = PTHREAD_MUTEX_INITIALIZER;
 
-/**
- * intel_batchbuffer_align:
- * @batch: batchbuffer object
- * @align: value in bytes to which we want to align
- *
- * Aligns the current in-batch offset to the given value.
- *
- * Returns: Batchbuffer offset aligned to the given value.
- */
-uint32_t
-intel_batchbuffer_align(struct intel_batchbuffer *batch, uint32_t align)
-{
-	uint32_t offset = batch->ptr - batch->buffer;
-
-	offset = ALIGN(offset, align);
-	batch->ptr = batch->buffer + offset;
-	return offset;
-}
-
-/**
- * intel_batchbuffer_subdata_alloc:
- * @batch: batchbuffer object
- * @size: amount of bytes need to allocate
- * @align: value in bytes to which we want to align
- *
- * Verify if sufficient @size within @batch is available to deny overflow.
- * Then allocate @size bytes within @batch.
- *
- * Returns: Offset within @batch between allocated subdata and base of @batch.
- */
-void *
-intel_batchbuffer_subdata_alloc(struct intel_batchbuffer *batch, uint32_t size,
-				uint32_t align)
-{
-	uint32_t offset = intel_batchbuffer_align(batch, align);
-
-	igt_assert(size <= intel_batchbuffer_space(batch));
-
-	batch->ptr += size;
-	return memset(batch->buffer + offset, 0, size);
-}
-
-/**
- * intel_batchbuffer_subdata_offset:
- * @batch: batchbuffer object
- * @ptr: pointer to given data
- *
- * Returns: Offset within @batch between @ptr and base of @batch.
- */
-uint32_t
-intel_batchbuffer_subdata_offset(struct intel_batchbuffer *batch, void *ptr)
-{
-	return (uint8_t *)ptr - batch->buffer;
-}
-
-/**
- * intel_batchbuffer_reset:
- * @batch: batchbuffer object
- *
- * Resets @batch by allocating a new gem buffer object as backing storage.
- */
-void
-intel_batchbuffer_reset(struct intel_batchbuffer *batch)
-{
-	if (batch->bo != NULL) {
-		drm_intel_bo_unreference(batch->bo);
-		batch->bo = NULL;
-	}
-
-	batch->bo = drm_intel_bo_alloc(batch->bufmgr, "batchbuffer",
-				       BATCH_SZ, 4096);
-
-	memset(batch->buffer, 0, sizeof(batch->buffer));
-	batch->ctx = NULL;
-
-	batch->ptr = batch->buffer;
-	batch->end = NULL;
-}
-
-/**
- * intel_batchbuffer_alloc:
- * @bufmgr: libdrm buffer manager
- * @devid: pci device id of the drm device
- *
- * Allocates a new batchbuffer object. @devid must be supplied since libdrm
- * doesn't expose it directly.
- *
- * Returns: The allocated and initialized batchbuffer object.
- */
-struct intel_batchbuffer *
-intel_batchbuffer_alloc(drm_intel_bufmgr *bufmgr, uint32_t devid)
-{
-	struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
-
-	batch->bufmgr = bufmgr;
-	batch->devid = devid;
-	batch->gen = intel_gen(devid);
-	intel_batchbuffer_reset(batch);
-
-	return batch;
-}
-
-/**
- * intel_batchbuffer_free:
- * @batch: batchbuffer object
- *
- * Releases all resource of the batchbuffer object @batch.
- */
-void
-intel_batchbuffer_free(struct intel_batchbuffer *batch)
-{
-	drm_intel_bo_unreference(batch->bo);
-	batch->bo = NULL;
-	free(batch);
-}
-
 #define CMD_POLY_STIPPLE_OFFSET       0x7906
 
-static unsigned int
-flush_on_ring_common(struct intel_batchbuffer *batch, int ring)
-{
-	unsigned int used = batch->ptr - batch->buffer;
-
-	if (used == 0)
-		return 0;
-
-	if (IS_GEN5(batch->devid)) {
-		/* emit gen5 w/a without batch space checks - we reserve that
-		 * already. */
-		*(uint32_t *) (batch->ptr) = CMD_POLY_STIPPLE_OFFSET << 16;
-		batch->ptr += 4;
-		*(uint32_t *) (batch->ptr) = 0;
-		batch->ptr += 4;
-	}
-
-	/* Round batchbuffer usage to 2 DWORDs. */
-	if ((used & 4) == 0) {
-		*(uint32_t *) (batch->ptr) = 0; /* noop */
-		batch->ptr += 4;
-	}
-
-	/* Mark the end of the buffer. */
-	*(uint32_t *)(batch->ptr) = MI_BATCH_BUFFER_END; /* noop */
-	batch->ptr += 4;
-	return batch->ptr - batch->buffer;
-}
-
-/**
- * intel_batchbuffer_flush_on_ring:
- * @batch: batchbuffer object
- * @ring: execbuf ring flag
- *
- * Submits the batch for execution on @ring.
- */
-void
-intel_batchbuffer_flush_on_ring(struct intel_batchbuffer *batch, int ring)
-{
-	unsigned int used = flush_on_ring_common(batch, ring);
-	drm_intel_context *ctx;
-
-	if (used == 0)
-		return;
-
-	do_or_die(drm_intel_bo_subdata(batch->bo, 0, used, batch->buffer));
-
-	batch->ptr = NULL;
-
-	/* XXX bad kernel API */
-	ctx = batch->ctx;
-	if (ring != I915_EXEC_RENDER)
-		ctx = NULL;
-	do_or_die(drm_intel_gem_bo_context_exec(batch->bo, ctx, used, ring));
-
-	intel_batchbuffer_reset(batch);
-}
-
-void
-intel_batchbuffer_set_context(struct intel_batchbuffer *batch,
-				     drm_intel_context *context)
-{
-	batch->ctx = context;
-}
-
-/**
- * intel_batchbuffer_flush_with_context:
- * @batch: batchbuffer object
- * @context: libdrm hardware context object
- *
- * Submits the batch for execution on the render engine with the supplied
- * hardware context.
- */
-void
-intel_batchbuffer_flush_with_context(struct intel_batchbuffer *batch,
-				     drm_intel_context *context)
-{
-	int ret;
-	unsigned int used = flush_on_ring_common(batch, I915_EXEC_RENDER);
-
-	if (used == 0)
-		return;
-
-	ret = drm_intel_bo_subdata(batch->bo, 0, used, batch->buffer);
-	igt_assert(ret == 0);
-
-	batch->ptr = NULL;
-
-	ret = drm_intel_gem_bo_context_exec(batch->bo, context, used,
-					    I915_EXEC_RENDER);
-	igt_assert(ret == 0);
-
-	intel_batchbuffer_reset(batch);
-}
-
-/**
- * intel_batchbuffer_flush:
- * @batch: batchbuffer object
- *
- * Submits the batch for execution on the blitter engine, selecting the right
- * ring depending upon the hardware platform.
- */
-void
-intel_batchbuffer_flush(struct intel_batchbuffer *batch)
-{
-	int ring = 0;
-	if (HAS_BLT_RING(batch->devid))
-		ring = I915_EXEC_BLT;
-	intel_batchbuffer_flush_on_ring(batch, ring);
-}
-
-
-/**
- * intel_batchbuffer_emit_reloc:
- * @batch: batchbuffer object
- * @buffer: relocation target libdrm buffer object
- * @delta: delta value to add to @buffer's gpu address
- * @read_domains: gem domain bits for the relocation
- * @write_domain: gem domain bit for the relocation
- * @fenced: whether this gpu access requires fences
- *
- * Emits both a libdrm relocation entry pointing at @buffer and the pre-computed
- * DWORD of @batch's presumed gpu address plus the supplied @delta into @batch.
- *
- * Note that @fenced is only relevant if @buffer is actually tiled.
- *
- * This is the only way buffers get added to the validate list.
- */
-void
-intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
-                             drm_intel_bo *buffer, uint64_t delta,
-			     uint32_t read_domains, uint32_t write_domain,
-			     int fenced)
-{
-	uint64_t offset;
-	int ret;
-
-	if (batch->ptr - batch->buffer > BATCH_SZ)
-		igt_info("bad relocation ptr %p map %p offset %d size %d\n",
-			 batch->ptr, batch->buffer,
-			 (int)(batch->ptr - batch->buffer), BATCH_SZ);
-
-	if (fenced)
-		ret = drm_intel_bo_emit_reloc_fence(batch->bo, batch->ptr - batch->buffer,
-						    buffer, delta,
-						    read_domains, write_domain);
-	else
-		ret = drm_intel_bo_emit_reloc(batch->bo, batch->ptr - batch->buffer,
-					      buffer, delta,
-					      read_domains, write_domain);
-
-	offset = buffer->offset64;
-	offset += delta;
-	intel_batchbuffer_emit_dword(batch, offset);
-	if (batch->gen >= 8)
-		intel_batchbuffer_emit_dword(batch, offset >> 32);
-	igt_assert(ret == 0);
-}
-
-/**
- * intel_batchbuffer_copy_data:
- * @batch: batchbuffer object
- * @data: pointer to the data to write into the batchbuffer
- * @bytes: number of bytes to write into the batchbuffer
- * @align: value in bytes to which we want to align
- *
- * This transfers the given @data into the batchbuffer. Note that the length
- * must be DWORD aligned, i.e. multiples of 32bits. The caller must
- * confirm that there is enough space in the batch for the data to be
- * copied.
- *
- * Returns: Offset of copied data.
- */
-uint32_t
-intel_batchbuffer_copy_data(struct intel_batchbuffer *batch,
-			    const void *data, unsigned int bytes,
-			    uint32_t align)
-{
-	uint32_t *subdata;
-
-	igt_assert((bytes & 3) == 0);
-	subdata = intel_batchbuffer_subdata_alloc(batch, bytes, align);
-	memcpy(subdata, data, bytes);
-
-	return intel_batchbuffer_subdata_offset(batch, subdata);
-}
-
-#define CHECK_RANGE(x)	do { \
+#define CHECK_RANGE(x) do { \
 	igt_assert_lte(0, (x)); \
 	igt_assert_lt((x), (1 << 15)); \
 } while (0)
 
-/**
- * intel_blt_copy:
- * @batch: batchbuffer object
- * @src_bo: source libdrm buffer object
- * @src_x1: source pixel x-coordination
- * @src_y1: source pixel y-coordination
- * @src_pitch: @src_bo's pitch in bytes
- * @dst_bo: destination libdrm buffer object
- * @dst_x1: destination pixel x-coordination
- * @dst_y1: destination pixel y-coordination
- * @dst_pitch: @dst_bo's pitch in bytes
- * @width: width of the copied rectangle
- * @height: height of the copied rectangle
- * @bpp: bits per pixel
- *
- * This emits a 2D copy operation using blitter commands into the supplied batch
- * buffer object.
- */
-void
-intel_blt_copy(struct intel_batchbuffer *batch,
-	       drm_intel_bo *src_bo, int src_x1, int src_y1, int src_pitch,
-	       drm_intel_bo *dst_bo, int dst_x1, int dst_y1, int dst_pitch,
-	       int width, int height, int bpp)
-{
-	const unsigned int gen = batch->gen;
-	uint32_t src_tiling, dst_tiling, swizzle;
-	uint32_t cmd_bits = 0;
-	uint32_t br13_bits;
-
-	igt_assert(bpp*(src_x1 + width) <= 8*src_pitch);
-	igt_assert(bpp*(dst_x1 + width) <= 8*dst_pitch);
-	igt_assert(src_pitch * (src_y1 + height) <= src_bo->size);
-	igt_assert(dst_pitch * (dst_y1 + height) <= dst_bo->size);
-
-	drm_intel_bo_get_tiling(src_bo, &src_tiling, &swizzle);
-	drm_intel_bo_get_tiling(dst_bo, &dst_tiling, &swizzle);
-
-	if (gen >= 4 && src_tiling != I915_TILING_NONE) {
-		src_pitch /= 4;
-		cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
-	}
-
-	if (gen >= 4 && dst_tiling != I915_TILING_NONE) {
-		dst_pitch /= 4;
-		cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
-	}
-
-	CHECK_RANGE(src_x1); CHECK_RANGE(src_y1);
-	CHECK_RANGE(dst_x1); CHECK_RANGE(dst_y1);
-	CHECK_RANGE(width); CHECK_RANGE(height);
-	CHECK_RANGE(src_x1 + width); CHECK_RANGE(src_y1 + height);
-	CHECK_RANGE(dst_x1 + width); CHECK_RANGE(dst_y1 + height);
-	CHECK_RANGE(src_pitch); CHECK_RANGE(dst_pitch);
-
-	br13_bits = 0;
-	switch (bpp) {
-	case 8:
-		break;
-	case 16:		/* supporting only RGB565, not ARGB1555 */
-		br13_bits |= 1 << 24;
-		break;
-	case 32:
-		br13_bits |= 3 << 24;
-		cmd_bits |= XY_SRC_COPY_BLT_WRITE_ALPHA |
-			    XY_SRC_COPY_BLT_WRITE_RGB;
-		break;
-	default:
-		igt_fail(IGT_EXIT_FAILURE);
-	}
-
-	BLIT_COPY_BATCH_START(cmd_bits);
-	OUT_BATCH((br13_bits) |
-		  (0xcc << 16) | /* copy ROP */
-		  dst_pitch);
-	OUT_BATCH((dst_y1 << 16) | dst_x1); /* dst x1,y1 */
-	OUT_BATCH(((dst_y1 + height) << 16) | (dst_x1 + width)); /* dst x2,y2 */
-	OUT_RELOC_FENCED(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH((src_y1 << 16) | src_x1); /* src x1,y1 */
-	OUT_BATCH(src_pitch);
-	OUT_RELOC_FENCED(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-#define CMD_POLY_STIPPLE_OFFSET       0x7906
-	if (gen == 5) {
-		BEGIN_BATCH(2, 0);
-		OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16);
-		OUT_BATCH(0);
-		ADVANCE_BATCH();
-	}
-
-	if (gen >= 6 && src_bo == dst_bo) {
-		BEGIN_BATCH(3, 0);
-		OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
-		OUT_BATCH(0);
-		OUT_BATCH(0);
-		ADVANCE_BATCH();
-	}
-
-	intel_batchbuffer_flush(batch);
-}
-
-/**
- * intel_copy_bo:
- * @batch: batchbuffer object
- * @src_bo: source libdrm buffer object
- * @dst_bo: destination libdrm buffer object
- * @size: size of the copy range in bytes
- *
- * This emits a copy operation using blitter commands into the supplied batch
- * buffer object. A total of @size bytes from the start of @src_bo is copied
- * over to @dst_bo. Note that @size must be page-aligned.
- */
-void
-intel_copy_bo(struct intel_batchbuffer *batch,
-	      drm_intel_bo *dst_bo, drm_intel_bo *src_bo,
-	      long int size)
-{
-	igt_assert(size % 4096 == 0);
-
-	intel_blt_copy(batch,
-		       src_bo, 0, 0, 4096,
-		       dst_bo, 0, 0, 4096,
-		       4096/4, size/4096, 32);
-}
-
-/**
- * igt_buf_width:
- * @buf: the i-g-t buffer object
- *
- * Computes the width in 32-bit pixels of the given buffer.
- *
- * Returns:
- * The width of the buffer.
- */
-unsigned igt_buf_width(const struct igt_buf *buf)
-{
-	return buf->surface[0].stride/(buf->bpp / 8);
-}
-
-/**
- * igt_buf_height:
- * @buf: the i-g-t buffer object
- *
- * Computes the height in 32-bit pixels of the given buffer.
- *
- * Returns:
- * The height of the buffer.
- */
-unsigned igt_buf_height(const struct igt_buf *buf)
-{
-	return buf->surface[0].size/buf->surface[0].stride;
-}
-
-/**
- * igt_buf_intel_ccs_width:
- * @buf: the Intel i-g-t buffer object
- * @gen: device generation
- *
- * Computes the width of ccs buffer when considered as Intel surface data.
- *
- * Returns:
- * The width of the ccs buffer data.
- */
-unsigned int igt_buf_intel_ccs_width(unsigned int gen, const struct igt_buf *buf)
-{
-	/*
-	 * GEN12+: The CCS unit size is 64 bytes mapping 4 main surface
-	 * tiles. Thus the width of the CCS unit is 4*32=128 pixels on the
-	 * main surface.
-	 */
-	if (gen >= 12)
-		return DIV_ROUND_UP(igt_buf_width(buf), 128) * 64;
-
-	return DIV_ROUND_UP(igt_buf_width(buf), 1024) * 128;
-}
-
-/**
- * igt_buf_intel_ccs_height:
- * @buf: the i-g-t buffer object
- * @gen: device generation
- *
- * Computes the height of ccs buffer when considered as Intel surface data.
- *
- * Returns:
- * The height of the ccs buffer data.
- */
-unsigned int igt_buf_intel_ccs_height(unsigned int gen, const struct igt_buf *buf)
-{
-	/*
-	 * GEN12+: The CCS unit size is 64 bytes mapping 4 main surface
-	 * tiles. Thus the height of the CCS unit is 32 pixel rows on the main
-	 * surface.
-	 */
-	if (gen >= 12)
-		return DIV_ROUND_UP(igt_buf_height(buf), 32);
-
-	return DIV_ROUND_UP(igt_buf_height(buf), 512) * 32;
-}
-
 /*
  * pitches are in bytes if the surfaces are linear, number of dwords
  * otherwise
@@ -1084,65 +571,6 @@ void igt_blitter_fast_copy__raw(int fd,
 	gem_close(fd, batch_handle);
 }
 
-/**
- * igt_blitter_fast_copy:
- * @batch: batchbuffer object
- * @src: source i-g-t buffer object
- * @src_delta: offset into the source i-g-t bo
- * @src_x: source pixel x-coordination
- * @src_y: source pixel y-coordination
- * @width: width of the copied rectangle
- * @height: height of the copied rectangle
- * @dst: destination i-g-t buffer object
- * @dst_delta: offset into the destination i-g-t bo
- * @dst_x: destination pixel x-coordination
- * @dst_y: destination pixel y-coordination
- *
- * Copy @src into @dst using the gen9 fast copy blitter command.
- *
- * The source and destination surfaces cannot overlap.
- */
-void igt_blitter_fast_copy(struct intel_batchbuffer *batch,
-			   const struct igt_buf *src, unsigned src_delta,
-			   unsigned src_x, unsigned src_y,
-			   unsigned width, unsigned height,
-			   int bpp,
-			   const struct igt_buf *dst, unsigned dst_delta,
-			   unsigned dst_x, unsigned dst_y)
-{
-	uint32_t src_pitch, dst_pitch;
-	uint32_t dword0, dword1;
-
-	igt_assert(src->bpp == dst->bpp);
-
-	src_pitch = fast_copy_pitch(src->surface[0].stride, src->tiling);
-	dst_pitch = fast_copy_pitch(dst->surface[0].stride, src->tiling);
-	dword0 = fast_copy_dword0(src->tiling, dst->tiling);
-	dword1 = fast_copy_dword1(src->tiling, dst->tiling, dst->bpp);
-
-	CHECK_RANGE(src_x); CHECK_RANGE(src_y);
-	CHECK_RANGE(dst_x); CHECK_RANGE(dst_y);
-	CHECK_RANGE(width); CHECK_RANGE(height);
-	CHECK_RANGE(src_x + width); CHECK_RANGE(src_y + height);
-	CHECK_RANGE(dst_x + width); CHECK_RANGE(dst_y + height);
-	CHECK_RANGE(src_pitch); CHECK_RANGE(dst_pitch);
-
-	BEGIN_BATCH(10, 2);
-	OUT_BATCH(dword0);
-	OUT_BATCH(dword1 | dst_pitch);
-	OUT_BATCH((dst_y << 16) | dst_x); /* dst x1,y1 */
-	OUT_BATCH(((dst_y + height) << 16) | (dst_x + width)); /* dst x2,y2 */
-	OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, dst_delta);
-	OUT_BATCH(0);	/* dst address upper bits */
-	OUT_BATCH((src_y << 16) | src_x); /* src x1,y1 */
-	OUT_BATCH(src_pitch);
-	OUT_RELOC(src->bo, I915_GEM_DOMAIN_RENDER, 0, src_delta);
-	OUT_BATCH(0);	/* src address upper bits */
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
-}
-
 /**
  * igt_get_render_copyfunc:
  * @devid: pci device id
@@ -2140,6 +1568,7 @@ __intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf,
 		}
 	}
 
+	igt_info("Adding offset handle: %u, %lx\n", buf->handle, buf->addr.offset);
 	obj = intel_bb_add_object(ibb, buf->handle, intel_buf_bo_size(buf),
 				  buf->addr.offset, alignment, write);
 	buf->addr.offset = obj->offset;
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 2418cb5662..37db0ffa7f 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -2,7 +2,6 @@
 #define INTEL_BATCHBUFFER_H
 
 #include <stdint.h>
-#include <intel_bufmgr.h>
 #include <i915_drm.h>
 
 #include "igt_core.h"
@@ -12,194 +11,6 @@
 #include "intel_allocator.h"
 
 #define BATCH_SZ 4096
-#define BATCH_RESERVED 16
-
-struct intel_batchbuffer {
-	drm_intel_bufmgr *bufmgr;
-	uint32_t devid;
-	unsigned int gen;
-
-	drm_intel_context *ctx;
-	drm_intel_bo *bo;
-
-	uint8_t buffer[BATCH_SZ];
-	uint8_t *ptr, *end;
-};
-
-struct intel_batchbuffer *intel_batchbuffer_alloc(drm_intel_bufmgr *bufmgr,
-						  uint32_t devid);
-
-void intel_batchbuffer_set_context(struct intel_batchbuffer *batch,
-				   drm_intel_context *ctx);
-
-
-void intel_batchbuffer_free(struct intel_batchbuffer *batch);
-
-
-void intel_batchbuffer_flush(struct intel_batchbuffer *batch);
-void intel_batchbuffer_flush_on_ring(struct intel_batchbuffer *batch, int ring);
-void intel_batchbuffer_flush_with_context(struct intel_batchbuffer *batch,
-					  drm_intel_context *context);
-
-void intel_batchbuffer_reset(struct intel_batchbuffer *batch);
-
-uint32_t intel_batchbuffer_copy_data(struct intel_batchbuffer *batch,
-				const void *data, unsigned int bytes,
-				uint32_t align);
-
-void intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
-				  drm_intel_bo *buffer,
-				  uint64_t delta,
-				  uint32_t read_domains,
-				  uint32_t write_domain,
-				  int fenced);
-
-uint32_t
-intel_batchbuffer_align(struct intel_batchbuffer *batch, uint32_t align);
-
-void *
-intel_batchbuffer_subdata_alloc(struct intel_batchbuffer *batch,
-				uint32_t size, uint32_t align);
-
-uint32_t
-intel_batchbuffer_subdata_offset(struct intel_batchbuffer *batch, void *ptr);
-
-/* Inline functions - might actually be better off with these
- * non-inlined.  Certainly better off switching all command packets to
- * be passed as structs rather than dwords, but that's a little bit of
- * work...
- */
-#pragma GCC diagnostic ignored "-Winline"
-static inline unsigned int
-intel_batchbuffer_space(struct intel_batchbuffer *batch)
-{
-	return (BATCH_SZ - BATCH_RESERVED) - (batch->ptr - batch->buffer);
-}
-
-
-static inline void
-intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, uint32_t dword)
-{
-	igt_assert(intel_batchbuffer_space(batch) >= 4);
-	*(uint32_t *) (batch->ptr) = dword;
-	batch->ptr += 4;
-}
-
-static inline void
-intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
-                                unsigned int sz)
-{
-	igt_assert(sz < BATCH_SZ - BATCH_RESERVED);
-	if (intel_batchbuffer_space(batch) < sz)
-		intel_batchbuffer_flush(batch);
-}
-
-/**
- * BEGIN_BATCH:
- * @n: number of DWORDS to emit
- * @r: number of RELOCS to emit
- *
- * Prepares a batch to emit @n DWORDS, flushing it if there's not enough space
- * available.
- *
- * This macro needs a pointer to an #intel_batchbuffer structure called batch in
- * scope.
- */
-#define BEGIN_BATCH(n, r) do {						\
-	int __n = (n); \
-	igt_assert(batch->end == NULL); \
-	if (batch->gen >= 8) __n += r;	\
-	__n *= 4; \
-	intel_batchbuffer_require_space(batch, __n);			\
-	batch->end = batch->ptr + __n; \
-} while (0)
-
-/**
- * OUT_BATCH:
- * @d: DWORD to emit
- *
- * Emits @d into a batch.
- *
- * This macro needs a pointer to an #intel_batchbuffer structure called batch in
- * scope.
- */
-#define OUT_BATCH(d) intel_batchbuffer_emit_dword(batch, d)
-
-/**
- * OUT_RELOC_FENCED:
- * @buf: relocation target libdrm buffer object
- * @read_domains: gem domain bits for the relocation
- * @write_domain: gem domain bit for the relocation
- * @delta: delta value to add to @buffer's gpu address
- *
- * Emits a fenced relocation into a batch.
- *
- * This macro needs a pointer to an #intel_batchbuffer structure called batch in
- * scope.
- */
-#define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do {		\
-	igt_assert((delta) >= 0);						\
-	intel_batchbuffer_emit_reloc(batch, buf, delta,			\
-				     read_domains, write_domain, 1);	\
-} while (0)
-
-/**
- * OUT_RELOC:
- * @buf: relocation target libdrm buffer object
- * @read_domains: gem domain bits for the relocation
- * @write_domain: gem domain bit for the relocation
- * @delta: delta value to add to @buffer's gpu address
- *
- * Emits a normal, unfenced relocation into a batch.
- *
- * This macro needs a pointer to an #intel_batchbuffer structure called batch in
- * scope.
- */
-#define OUT_RELOC(buf, read_domains, write_domain, delta) do {		\
-	igt_assert((delta) >= 0);						\
-	intel_batchbuffer_emit_reloc(batch, buf, delta,			\
-				     read_domains, write_domain, 0);	\
-} while (0)
-
-/**
- * ADVANCE_BATCH:
- *
- * Completes the batch command emission sequence started with #BEGIN_BATCH.
- *
- * This macro needs a pointer to an #intel_batchbuffer structure called batch in
- * scope.
- */
-#define ADVANCE_BATCH() do {						\
-	igt_assert(batch->ptr == batch->end); \
-	batch->end = NULL; \
-} while(0)
-
-#define BLIT_COPY_BATCH_START(flags) do { \
-	BEGIN_BATCH(8, 2); \
-	OUT_BATCH(XY_SRC_COPY_BLT_CMD | \
-		  XY_SRC_COPY_BLT_WRITE_ALPHA | \
-		  XY_SRC_COPY_BLT_WRITE_RGB | \
-		  (flags) | \
-		  (6 + 2*(batch->gen >= 8))); \
-} while(0)
-
-#define COLOR_BLIT_COPY_BATCH_START(flags) do { \
-	BEGIN_BATCH(6, 1); \
-	OUT_BATCH(XY_COLOR_BLT_CMD_NOLEN | \
-		  COLOR_BLT_WRITE_ALPHA | \
-		  XY_COLOR_BLT_WRITE_RGB | \
-		  (flags) | \
-		  (4 + (batch->gen >= 8))); \
-} while(0)
-
-void
-intel_blt_copy(struct intel_batchbuffer *batch,
-	      drm_intel_bo *src_bo, int src_x1, int src_y1, int src_pitch,
-	      drm_intel_bo *dst_bo, int dst_x1, int dst_y1, int dst_pitch,
-	      int width, int height, int bpp);
-void intel_copy_bo(struct intel_batchbuffer *batch,
-		   drm_intel_bo *dst_bo, drm_intel_bo *src_bo,
-		   long int size);
 
 /*
  * Yf/Ys/4 tiling
@@ -220,57 +31,6 @@ enum i915_compression {
 	I915_COMPRESSION_MEDIA,
 };
 
-/**
- * igt_buf:
- * @bo: underlying libdrm buffer object
- * @stride: stride of the buffer
- * @tiling: tiling mode bits
- * @compression: memory compression mode
- * @bpp: bits per pixel, 8, 16 or 32.
- * @data: pointer to the memory mapping of the buffer
- * @size: size of the buffer object
- *
- * This is a i-g-t buffer object wrapper structure which augments the baseline
- * libdrm buffer object with suitable data needed by the render/vebox copy and
- * the fill functions.
- */
-struct igt_buf {
-	drm_intel_bo *bo;
-	uint32_t tiling;
-	enum i915_compression compression;
-	uint32_t bpp;
-	uint32_t yuv_semiplanar_bpp;
-	uint32_t *data;
-	bool format_is_yuv:1;
-	bool format_is_yuv_semiplanar:1;
-	struct {
-		uint32_t offset;
-		uint32_t stride;
-		uint32_t size;
-	} surface[2];
-	struct {
-		uint32_t offset;
-		uint32_t stride;
-	} ccs[2];
-	struct {
-		uint32_t offset;
-	} cc;
-	/*< private >*/
-	unsigned num_tiles;
-};
-
-static inline bool igt_buf_compressed(const struct igt_buf *buf)
-{
-	return buf->compression != I915_COMPRESSION_NONE;
-}
-
-unsigned igt_buf_width(const struct igt_buf *buf);
-unsigned igt_buf_height(const struct igt_buf *buf);
-unsigned int igt_buf_intel_ccs_width(unsigned int gen,
-				     const struct igt_buf *buf);
-unsigned int igt_buf_intel_ccs_height(unsigned int gen,
-				      const struct igt_buf *buf);
-
 void igt_blitter_src_copy(int fd,
 			  uint64_t ahnd,
 			  uint32_t ctx,
@@ -297,14 +57,6 @@ void igt_blitter_src_copy(int fd,
 			  uint32_t dst_x, uint32_t dst_y,
 			  uint64_t dst_size);
 
-void igt_blitter_fast_copy(struct intel_batchbuffer *batch,
-			   const struct igt_buf *src, unsigned src_delta,
-			   unsigned src_x, unsigned src_y,
-			   unsigned width, unsigned height,
-			   int bpp,
-			   const struct igt_buf *dst, unsigned dst_delta,
-			   unsigned dst_x, unsigned dst_y);
-
 void igt_blitter_fast_copy__raw(int fd,
 				uint64_t ahnd,
 				uint32_t ctx,
-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 07/11] lib/intel_decode: Get drm decode code and adopt to use in igt

[Zbigniew Kempczyński]

Decoding part is in use in intel_dump_decode and intel_error_decode
tools. To detach from libdrm just take copy - it is almost verbatim
(apart of rename and some minor intel_gen() adoptions).

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 lib/i915/intel_decode.c | 3962 +++++++++++++++++++++++++++++++++++++++
 lib/i915/intel_decode.h |   42 +
 lib/meson.build         |    1 +
 3 files changed, 4005 insertions(+)
 create mode 100644 lib/i915/intel_decode.c
 create mode 100644 lib/i915/intel_decode.h

diff --git a/lib/i915/intel_decode.c b/lib/i915/intel_decode.c
new file mode 100644
index 0000000000..80b92d90c6
--- /dev/null
+++ b/lib/i915/intel_decode.c
@@ -0,0 +1,3962 @@
+/*
+ * Copyright © 2009-2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdarg.h>
+#include <string.h>
+
+#include "igt.h"
+#include "intel_decode.h"
+
+/* Struct for tracking intel_decode state. */
+struct intel_decode {
+	/** stdio file where the output should land.  Defaults to stdout. */
+	FILE *out;
+
+	/** PCI device ID. */
+	uint32_t devid;
+
+	/**
+	 * Shorthand device identifier: 3 is 915, 4 is 965, 5 is
+	 * Ironlake, etc.
+	 */
+	int gen;
+
+	/** GPU address of the start of the current packet. */
+	uint32_t hw_offset;
+	/** CPU virtual address of the start of the current packet. */
+	uint32_t *data;
+	/** DWORDs of remaining batchbuffer data starting from the packet. */
+	uint32_t count;
+
+	/** GPU address of the start of the batchbuffer data. */
+	uint32_t base_hw_offset;
+	/** CPU Virtual address of the start of the batchbuffer data. */
+	uint32_t *base_data;
+	/** Number of DWORDs of batchbuffer data. */
+	uint32_t base_count;
+
+	/** @{
+	 * GPU head and tail pointers, which will be noted in the dump, or ~0.
+	 */
+	uint32_t head, tail;
+	/** @} */
+
+	/**
+	 * Whether to dump the dwords after MI_BATCHBUFFER_END.
+	 *
+	 * This sometimes provides clues in corrupted batchbuffers,
+	 * and is used by the intel-gpu-tools.
+	 */
+	bool dump_past_end;
+
+	bool overflowed;
+};
+
+static FILE *out;
+static uint32_t saved_s2 = 0, saved_s4 = 0;
+static char saved_s2_set = 0, saved_s4_set = 0;
+static uint32_t head_offset = 0xffffffff;	/* undefined */
+static uint32_t tail_offset = 0xffffffff;	/* undefined */
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(A) (sizeof(A)/sizeof(A[0]))
+#endif
+
+#define BUFFER_FAIL(_count, _len, _name) do {			\
+    fprintf(out, "Buffer size too small in %s (%d < %d)\n",	\
+	    (_name), (_count), (_len));				\
+    return _count;						\
+} while (0)
+
+static float int_as_float(uint32_t intval)
+{
+	union intfloat {
+		uint32_t i;
+		float f;
+	} uval;
+
+	uval.i = intval;
+	return uval.f;
+}
+
+static void DRM_PRINTFLIKE(3, 4)
+instr_out(struct intel_decode *ctx, unsigned int index,
+	  const char *fmt, ...)
+{
+	va_list va;
+	const char *parseinfo;
+	uint32_t offset = ctx->hw_offset + index * 4;
+
+	if (index > ctx->count) {
+		if (!ctx->overflowed) {
+			fprintf(out, "ERROR: Decode attempted to continue beyond end of batchbuffer\n");
+			ctx->overflowed = true;
+		}
+		return;
+	}
+
+	if (offset == head_offset)
+		parseinfo = "HEAD";
+	else if (offset == tail_offset)
+		parseinfo = "TAIL";
+	else
+		parseinfo = "    ";
+
+	fprintf(out, "0x%08x: %s 0x%08x: %s", offset, parseinfo,
+		ctx->data[index], index == 0 ? "" : "   ");
+	va_start(va, fmt);
+	vfprintf(out, fmt, va);
+	va_end(va);
+}
+
+static int
+decode_MI_SET_CONTEXT(struct intel_decode *ctx)
+{
+	uint32_t data = ctx->data[1];
+	if (ctx->gen > 7)
+		return 1;
+
+	instr_out(ctx, 0, "MI_SET_CONTEXT\n");
+	instr_out(ctx, 1, "gtt offset = 0x%x%s%s\n",
+		  data & ~0xfff,
+		  data & (1<<1)? ", Force Restore": "",
+		  data & (1<<0)? ", Restore Inhibit": "");
+
+	return 2;
+}
+
+static int
+decode_MI_WAIT_FOR_EVENT(struct intel_decode *ctx)
+{
+	const char *cc_wait;
+	int cc_shift = 0;
+	uint32_t data = ctx->data[0];
+
+	if (ctx->gen <= 5)
+		cc_shift = 9;
+	else
+		cc_shift = 16;
+
+	switch ((data >> cc_shift) & 0x1f) {
+	case 1:
+		cc_wait = ", cc wait 1";
+		break;
+	case 2:
+		cc_wait = ", cc wait 2";
+		break;
+	case 3:
+		cc_wait = ", cc wait 3";
+		break;
+	case 4:
+		cc_wait = ", cc wait 4";
+		break;
+	case 5:
+		cc_wait = ", cc wait 4";
+		break;
+	default:
+		cc_wait = "";
+		break;
+	}
+
+	if (ctx->gen <= 5) {
+		instr_out(ctx, 0, "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+			  data & (1<<18)? ", pipe B start vblank wait": "",
+			  data & (1<<17)? ", pipe A start vblank wait": "",
+			  data & (1<<16)? ", overlay flip pending wait": "",
+			  data & (1<<14)? ", pipe B hblank wait": "",
+			  data & (1<<13)? ", pipe A hblank wait": "",
+			  cc_wait,
+			  data & (1<<8)? ", plane C pending flip wait": "",
+			  data & (1<<7)? ", pipe B vblank wait": "",
+			  data & (1<<6)? ", plane B pending flip wait": "",
+			  data & (1<<5)? ", pipe B scan line wait": "",
+			  data & (1<<4)? ", fbc idle wait": "",
+			  data & (1<<3)? ", pipe A vblank wait": "",
+			  data & (1<<2)? ", plane A pending flip wait": "",
+			  data & (1<<1)? ", plane A scan line wait": "");
+	} else {
+		instr_out(ctx, 0, "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s\n",
+			  data & (1<<20)? ", sprite C pending flip wait": "", /* ivb */
+			  cc_wait,
+			  data & (1<<13)? ", pipe B hblank wait": "",
+			  data & (1<<11)? ", pipe B vblank wait": "",
+			  data & (1<<10)? ", sprite B pending flip wait": "",
+			  data & (1<<9)? ", plane B pending flip wait": "",
+			  data & (1<<8)? ", plane B scan line wait": "",
+			  data & (1<<5)? ", pipe A hblank wait": "",
+			  data & (1<<3)? ", pipe A vblank wait": "",
+			  data & (1<<2)? ", sprite A pending flip wait": "",
+			  data & (1<<1)? ", plane A pending flip wait": "",
+			  data & (1<<0)? ", plane A scan line wait": "");
+	}
+
+	return 1;
+}
+
+static int
+decode_mi(struct intel_decode *ctx)
+{
+	unsigned int opcode, len = -1;
+	const char *post_sync_op = "";
+	uint32_t *data = ctx->data;
+
+	struct {
+		uint32_t opcode;
+		int len_mask;
+		unsigned int min_len;
+		unsigned int max_len;
+		const char *name;
+		int (*func)(struct intel_decode *ctx);
+	} opcodes_mi[] = {
+		{ 0x08, 0, 1, 1, "MI_ARB_ON_OFF" },
+		{ 0x0a, 0, 1, 1, "MI_BATCH_BUFFER_END" },
+		{ 0x30, 0x3f, 3, 3, "MI_BATCH_BUFFER" },
+		{ 0x31, 0x3f, 2, 2, "MI_BATCH_BUFFER_START" },
+		{ 0x14, 0x3f, 3, 3, "MI_DISPLAY_BUFFER_INFO" },
+		{ 0x04, 0, 1, 1, "MI_FLUSH" },
+		{ 0x22, 0x1f, 3, 3, "MI_LOAD_REGISTER_IMM" },
+		{ 0x13, 0x3f, 2, 2, "MI_LOAD_SCAN_LINES_EXCL" },
+		{ 0x12, 0x3f, 2, 2, "MI_LOAD_SCAN_LINES_INCL" },
+		{ 0x00, 0, 1, 1, "MI_NOOP" },
+		{ 0x11, 0x3f, 2, 2, "MI_OVERLAY_FLIP" },
+		{ 0x07, 0, 1, 1, "MI_REPORT_HEAD" },
+		{ 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT", decode_MI_SET_CONTEXT },
+		{ 0x20, 0x3f, 3, 4, "MI_STORE_DATA_IMM" },
+		{ 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" },
+		{ 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" },
+		{ 0x02, 0, 1, 1, "MI_USER_INTERRUPT" },
+		{ 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT", decode_MI_WAIT_FOR_EVENT },
+		{ 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" },
+		{ 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" },
+		{ 0x28, 0x3f, 3, 3, "MI_REPORT_PERF_COUNT" },
+		{ 0x29, 0xff, 3, 3, "MI_LOAD_REGISTER_MEM" },
+		{ 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH"},
+	}, *opcode_mi = NULL;
+
+	/* check instruction length */
+	for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]);
+	     opcode++) {
+		if ((data[0] & 0x1f800000) >> 23 == opcodes_mi[opcode].opcode) {
+			len = 1;
+			if (opcodes_mi[opcode].max_len > 1) {
+				len =
+				    (data[0] & opcodes_mi[opcode].len_mask) + 2;
+				if (len < opcodes_mi[opcode].min_len
+				    || len > opcodes_mi[opcode].max_len) {
+					fprintf(out,
+						"Bad length (%d) in %s, [%d, %d]\n",
+						len, opcodes_mi[opcode].name,
+						opcodes_mi[opcode].min_len,
+						opcodes_mi[opcode].max_len);
+				}
+			}
+			opcode_mi = &opcodes_mi[opcode];
+			break;
+		}
+	}
+
+	if (opcode_mi && opcode_mi->func)
+		return opcode_mi->func(ctx);
+
+	switch ((data[0] & 0x1f800000) >> 23) {
+	case 0x0a:
+		instr_out(ctx, 0, "MI_BATCH_BUFFER_END\n");
+		return -1;
+	case 0x16:
+		instr_out(ctx, 0, "MI_SEMAPHORE_MBOX%s%s%s%s %u\n",
+			  data[0] & (1 << 22) ? " global gtt," : "",
+			  data[0] & (1 << 21) ? " update semaphore," : "",
+			  data[0] & (1 << 20) ? " compare semaphore," : "",
+			  data[0] & (1 << 18) ? " use compare reg" : "",
+			  (data[0] & (0x3 << 16)) >> 16);
+		instr_out(ctx, 1, "value\n");
+		instr_out(ctx, 2, "address\n");
+		return len;
+	case 0x21:
+		instr_out(ctx, 0, "MI_STORE_DATA_INDEX%s\n",
+			  data[0] & (1 << 21) ? " use per-process HWS," : "");
+		instr_out(ctx, 1, "index\n");
+		instr_out(ctx, 2, "dword\n");
+		if (len == 4)
+			instr_out(ctx, 3, "upper dword\n");
+		return len;
+	case 0x00:
+		if (data[0] & (1 << 22))
+			instr_out(ctx, 0,
+				  "MI_NOOP write NOPID reg, val=0x%x\n",
+				  data[0] & ((1 << 22) - 1));
+		else
+			instr_out(ctx, 0, "MI_NOOP\n");
+		return len;
+	case 0x26:
+		switch (data[0] & (0x3 << 14)) {
+		case (0 << 14):
+			post_sync_op = "no write";
+			break;
+		case (1 << 14):
+			post_sync_op = "write data";
+			break;
+		case (2 << 14):
+			post_sync_op = "reserved";
+			break;
+		case (3 << 14):
+			post_sync_op = "write TIMESTAMP";
+			break;
+		}
+		instr_out(ctx, 0,
+			  "MI_FLUSH_DW%s%s%s%s post_sync_op='%s' %s%s\n",
+			  data[0] & (1 << 22) ?
+			  " enable protected mem (BCS-only)," : "",
+			  data[0] & (1 << 21) ? " store in hws," : "",
+			  data[0] & (1 << 18) ? " invalidate tlb," : "",
+			  data[0] & (1 << 17) ? " flush gfdt," : "",
+			  post_sync_op,
+			  data[0] & (1 << 8) ? " enable notify interrupt," : "",
+			  data[0] & (1 << 7) ?
+			  " invalidate video state (BCS-only)," : "");
+		if (data[0] & (1 << 21))
+			instr_out(ctx, 1, "hws index\n");
+		else
+			instr_out(ctx, 1, "address\n");
+		instr_out(ctx, 2, "dword\n");
+		if (len == 4)
+			instr_out(ctx, 3, "upper dword\n");
+		return len;
+	}
+
+	for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]);
+	     opcode++) {
+		if ((data[0] & 0x1f800000) >> 23 == opcodes_mi[opcode].opcode) {
+			unsigned int i;
+
+			instr_out(ctx, 0, "%s\n",
+				  opcodes_mi[opcode].name);
+			for (i = 1; i < len; i++) {
+				instr_out(ctx, i, "dword %d\n", i);
+			}
+
+			return len;
+		}
+	}
+
+	instr_out(ctx, 0, "MI UNKNOWN\n");
+	return 1;
+}
+
+static void
+decode_2d_br00(struct intel_decode *ctx, const char *cmd)
+{
+	instr_out(ctx, 0,
+		  "%s (rgb %sabled, alpha %sabled, src tile %d, dst tile %d)\n",
+		  cmd,
+		  (ctx->data[0] & (1 << 20)) ? "en" : "dis",
+		  (ctx->data[0] & (1 << 21)) ? "en" : "dis",
+		  (ctx->data[0] >> 15) & 1,
+		  (ctx->data[0] >> 11) & 1);
+}
+
+static void
+decode_2d_br01(struct intel_decode *ctx)
+{
+	const char *format;
+	switch ((ctx->data[1] >> 24) & 0x3) {
+	case 0:
+		format = "8";
+		break;
+	case 1:
+		format = "565";
+		break;
+	case 2:
+		format = "1555";
+		break;
+	case 3:
+		format = "8888";
+		break;
+	}
+
+	instr_out(ctx, 1,
+		  "format %s, pitch %d, rop 0x%02x, "
+		  "clipping %sabled, %s%s \n",
+		  format,
+		  (short)(ctx->data[1] & 0xffff),
+		  (ctx->data[1] >> 16) & 0xff,
+		  ctx->data[1] & (1 << 30) ? "en" : "dis",
+		  ctx->data[1] & (1 << 31) ? "solid pattern enabled, " : "",
+		  ctx->data[1] & (1 << 31) ?
+		  "mono pattern transparency enabled, " : "");
+
+}
+
+static int
+decode_2d(struct intel_decode *ctx)
+{
+	unsigned int opcode, len;
+	uint32_t *data = ctx->data;
+
+	struct {
+		uint32_t opcode;
+		unsigned int min_len;
+		unsigned int max_len;
+		const char *name;
+	} opcodes_2d[] = {
+		{ 0x40, 5, 5, "COLOR_BLT" },
+		{ 0x43, 6, 6, "SRC_COPY_BLT" },
+		{ 0x01, 8, 8, "XY_SETUP_BLT" },
+		{ 0x11, 9, 9, "XY_SETUP_MONO_PATTERN_SL_BLT" },
+		{ 0x03, 3, 3, "XY_SETUP_CLIP_BLT" },
+		{ 0x24, 2, 2, "XY_PIXEL_BLT" },
+		{ 0x25, 3, 3, "XY_SCANLINES_BLT" },
+		{ 0x26, 4, 4, "Y_TEXT_BLT" },
+		{ 0x31, 5, 134, "XY_TEXT_IMMEDIATE_BLT" },
+		{ 0x50, 6, 6, "XY_COLOR_BLT" },
+		{ 0x51, 6, 6, "XY_PAT_BLT" },
+		{ 0x76, 8, 8, "XY_PAT_CHROMA_BLT" },
+		{ 0x72, 7, 135, "XY_PAT_BLT_IMMEDIATE" },
+		{ 0x77, 9, 137, "XY_PAT_CHROMA_BLT_IMMEDIATE" },
+		{ 0x52, 9, 9, "XY_MONO_PAT_BLT" },
+		{ 0x59, 7, 7, "XY_MONO_PAT_FIXED_BLT" },
+		{ 0x53, 8, 8, "XY_SRC_COPY_BLT" },
+		{ 0x54, 8, 8, "XY_MONO_SRC_COPY_BLT" },
+		{ 0x71, 9, 137, "XY_MONO_SRC_COPY_IMMEDIATE_BLT" },
+		{ 0x55, 9, 9, "XY_FULL_BLT" },
+		{ 0x55, 9, 137, "XY_FULL_IMMEDIATE_PATTERN_BLT" },
+		{ 0x56, 9, 9, "XY_FULL_MONO_SRC_BLT" },
+		{ 0x75, 10, 138, "XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT" },
+		{ 0x57, 12, 12, "XY_FULL_MONO_PATTERN_BLT" },
+		{ 0x58, 12, 12, "XY_FULL_MONO_PATTERN_MONO_SRC_BLT"},
+	};
+
+	switch ((data[0] & 0x1fc00000) >> 22) {
+	case 0x25:
+		instr_out(ctx, 0,
+			  "XY_SCANLINES_BLT (pattern seed (%d, %d), dst tile %d)\n",
+			  (data[0] >> 12) & 0x8,
+			  (data[0] >> 8) & 0x8, (data[0] >> 11) & 1);
+
+		len = (data[0] & 0x000000ff) + 2;
+		if (len != 3)
+			fprintf(out, "Bad count in XY_SCANLINES_BLT\n");
+
+		instr_out(ctx, 1, "dest (%d,%d)\n",
+			  data[1] & 0xffff, data[1] >> 16);
+		instr_out(ctx, 2, "dest (%d,%d)\n",
+			  data[2] & 0xffff, data[2] >> 16);
+		return len;
+	case 0x01:
+		decode_2d_br00(ctx, "XY_SETUP_BLT");
+
+		len = (data[0] & 0x000000ff) + 2;
+		if (len != 8)
+			fprintf(out, "Bad count in XY_SETUP_BLT\n");
+
+		decode_2d_br01(ctx);
+		instr_out(ctx, 2, "cliprect (%d,%d)\n",
+			  data[2] & 0xffff, data[2] >> 16);
+		instr_out(ctx, 3, "cliprect (%d,%d)\n",
+			  data[3] & 0xffff, data[3] >> 16);
+		instr_out(ctx, 4, "setup dst offset 0x%08x\n",
+			  data[4]);
+		instr_out(ctx, 5, "setup background color\n");
+		instr_out(ctx, 6, "setup foreground color\n");
+		instr_out(ctx, 7, "color pattern offset\n");
+		return len;
+	case 0x03:
+		decode_2d_br00(ctx, "XY_SETUP_CLIP_BLT");
+
+		len = (data[0] & 0x000000ff) + 2;
+		if (len != 3)
+			fprintf(out, "Bad count in XY_SETUP_CLIP_BLT\n");
+
+		instr_out(ctx, 1, "cliprect (%d,%d)\n",
+			  data[1] & 0xffff, data[2] >> 16);
+		instr_out(ctx, 2, "cliprect (%d,%d)\n",
+			  data[2] & 0xffff, data[3] >> 16);
+		return len;
+	case 0x11:
+		decode_2d_br00(ctx, "XY_SETUP_MONO_PATTERN_SL_BLT");
+
+		len = (data[0] & 0x000000ff) + 2;
+		if (len != 9)
+			fprintf(out,
+				"Bad count in XY_SETUP_MONO_PATTERN_SL_BLT\n");
+
+		decode_2d_br01(ctx);
+		instr_out(ctx, 2, "cliprect (%d,%d)\n",
+			  data[2] & 0xffff, data[2] >> 16);
+		instr_out(ctx, 3, "cliprect (%d,%d)\n",
+			  data[3] & 0xffff, data[3] >> 16);
+		instr_out(ctx, 4, "setup dst offset 0x%08x\n",
+			  data[4]);
+		instr_out(ctx, 5, "setup background color\n");
+		instr_out(ctx, 6, "setup foreground color\n");
+		instr_out(ctx, 7, "mono pattern dw0\n");
+		instr_out(ctx, 8, "mono pattern dw1\n");
+		return len;
+	case 0x50:
+		decode_2d_br00(ctx, "XY_COLOR_BLT");
+
+		len = (data[0] & 0x000000ff) + 2;
+		if (len != 6)
+			fprintf(out, "Bad count in XY_COLOR_BLT\n");
+
+		decode_2d_br01(ctx);
+		instr_out(ctx, 2, "(%d,%d)\n",
+			  data[2] & 0xffff, data[2] >> 16);
+		instr_out(ctx, 3, "(%d,%d)\n",
+			  data[3] & 0xffff, data[3] >> 16);
+		instr_out(ctx, 4, "offset 0x%08x\n", data[4]);
+		instr_out(ctx, 5, "color\n");
+		return len;
+	case 0x53:
+		decode_2d_br00(ctx, "XY_SRC_COPY_BLT");
+
+		len = (data[0] & 0x000000ff) + 2;
+		if (len != 8)
+			fprintf(out, "Bad count in XY_SRC_COPY_BLT\n");
+
+		decode_2d_br01(ctx);
+		instr_out(ctx, 2, "dst (%d,%d)\n",
+			  data[2] & 0xffff, data[2] >> 16);
+		instr_out(ctx, 3, "dst (%d,%d)\n",
+			  data[3] & 0xffff, data[3] >> 16);
+		instr_out(ctx, 4, "dst offset 0x%08x\n", data[4]);
+		instr_out(ctx, 5, "src (%d,%d)\n",
+			  data[5] & 0xffff, data[5] >> 16);
+		instr_out(ctx, 6, "src pitch %d\n",
+			  (short)(data[6] & 0xffff));
+		instr_out(ctx, 7, "src offset 0x%08x\n", data[7]);
+		return len;
+	}
+
+	for (opcode = 0; opcode < sizeof(opcodes_2d) / sizeof(opcodes_2d[0]);
+	     opcode++) {
+		if ((data[0] & 0x1fc00000) >> 22 == opcodes_2d[opcode].opcode) {
+			unsigned int i;
+
+			len = 1;
+			instr_out(ctx, 0, "%s\n",
+				  opcodes_2d[opcode].name);
+			if (opcodes_2d[opcode].max_len > 1) {
+				len = (data[0] & 0x000000ff) + 2;
+				if (len < opcodes_2d[opcode].min_len ||
+				    len > opcodes_2d[opcode].max_len) {
+					fprintf(out, "Bad count in %s\n",
+						opcodes_2d[opcode].name);
+				}
+			}
+
+			for (i = 1; i < len; i++) {
+				instr_out(ctx, i, "dword %d\n", i);
+			}
+
+			return len;
+		}
+	}
+
+	instr_out(ctx, 0, "2D UNKNOWN\n");
+	return 1;
+}
+
+static int
+decode_3d_1c(struct intel_decode *ctx)
+{
+	uint32_t *data = ctx->data;
+	uint32_t opcode;
+
+	opcode = (data[0] & 0x00f80000) >> 19;
+
+	switch (opcode) {
+	case 0x11:
+		instr_out(ctx, 0,
+			  "3DSTATE_DEPTH_SUBRECTANGLE_DISABLE\n");
+		return 1;
+	case 0x10:
+		instr_out(ctx, 0, "3DSTATE_SCISSOR_ENABLE %s\n",
+			  data[0] & 1 ? "enabled" : "disabled");
+		return 1;
+	case 0x01:
+		instr_out(ctx, 0, "3DSTATE_MAP_COORD_SET_I830\n");
+		return 1;
+	case 0x0a:
+		instr_out(ctx, 0, "3DSTATE_MAP_CUBE_I830\n");
+		return 1;
+	case 0x05:
+		instr_out(ctx, 0, "3DSTATE_MAP_TEX_STREAM_I830\n");
+		return 1;
+	}
+
+	instr_out(ctx, 0, "3D UNKNOWN: 3d_1c opcode = 0x%x\n",
+		  opcode);
+	return 1;
+}
+
+/** Sets the string dstname to describe the destination of the PS instruction */
+static void
+i915_get_instruction_dst(uint32_t *data, int i, char *dstname, int do_mask)
+{
+	uint32_t a0 = data[i];
+	int dst_nr = (a0 >> 14) & 0xf;
+	char dstmask[8];
+	const char *sat;
+
+	if (do_mask) {
+		if (((a0 >> 10) & 0xf) == 0xf) {
+			dstmask[0] = 0;
+		} else {
+			int dstmask_index = 0;
+
+			dstmask[dstmask_index++] = '.';
+			if (a0 & (1 << 10))
+				dstmask[dstmask_index++] = 'x';
+			if (a0 & (1 << 11))
+				dstmask[dstmask_index++] = 'y';
+			if (a0 & (1 << 12))
+				dstmask[dstmask_index++] = 'z';
+			if (a0 & (1 << 13))
+				dstmask[dstmask_index++] = 'w';
+			dstmask[dstmask_index++] = 0;
+		}
+
+		if (a0 & (1 << 22))
+			sat = ".sat";
+		else
+			sat = "";
+	} else {
+		dstmask[0] = 0;
+		sat = "";
+	}
+
+	switch ((a0 >> 19) & 0x7) {
+	case 0:
+		if (dst_nr > 15)
+			fprintf(out, "bad destination reg R%d\n", dst_nr);
+		sprintf(dstname, "R%d%s%s", dst_nr, dstmask, sat);
+		break;
+	case 4:
+		if (dst_nr > 0)
+			fprintf(out, "bad destination reg oC%d\n", dst_nr);
+		sprintf(dstname, "oC%s%s", dstmask, sat);
+		break;
+	case 5:
+		if (dst_nr > 0)
+			fprintf(out, "bad destination reg oD%d\n", dst_nr);
+		sprintf(dstname, "oD%s%s", dstmask, sat);
+		break;
+	case 6:
+		if (dst_nr > 3)
+			fprintf(out, "bad destination reg U%d\n", dst_nr);
+		sprintf(dstname, "U%d%s%s", dst_nr, dstmask, sat);
+		break;
+	default:
+		sprintf(dstname, "RESERVED");
+		break;
+	}
+}
+
+static const char *
+i915_get_channel_swizzle(uint32_t select)
+{
+	switch (select & 0x7) {
+	case 0:
+		return (select & 8) ? "-x" : "x";
+	case 1:
+		return (select & 8) ? "-y" : "y";
+	case 2:
+		return (select & 8) ? "-z" : "z";
+	case 3:
+		return (select & 8) ? "-w" : "w";
+	case 4:
+		return (select & 8) ? "-0" : "0";
+	case 5:
+		return (select & 8) ? "-1" : "1";
+	default:
+		return (select & 8) ? "-bad" : "bad";
+	}
+}
+
+static void
+i915_get_instruction_src_name(uint32_t src_type, uint32_t src_nr, char *name)
+{
+	switch (src_type) {
+	case 0:
+		sprintf(name, "R%d", src_nr);
+		if (src_nr > 15)
+			fprintf(out, "bad src reg %s\n", name);
+		break;
+	case 1:
+		if (src_nr < 8)
+			sprintf(name, "T%d", src_nr);
+		else if (src_nr == 8)
+			sprintf(name, "DIFFUSE");
+		else if (src_nr == 9)
+			sprintf(name, "SPECULAR");
+		else if (src_nr == 10)
+			sprintf(name, "FOG");
+		else {
+			fprintf(out, "bad src reg T%d\n", src_nr);
+			sprintf(name, "RESERVED");
+		}
+		break;
+	case 2:
+		sprintf(name, "C%d", src_nr);
+		if (src_nr > 31)
+			fprintf(out, "bad src reg %s\n", name);
+		break;
+	case 4:
+		sprintf(name, "oC");
+		if (src_nr > 0)
+			fprintf(out, "bad src reg oC%d\n", src_nr);
+		break;
+	case 5:
+		sprintf(name, "oD");
+		if (src_nr > 0)
+			fprintf(out, "bad src reg oD%d\n", src_nr);
+		break;
+	case 6:
+		sprintf(name, "U%d", src_nr);
+		if (src_nr > 3)
+			fprintf(out, "bad src reg %s\n", name);
+		break;
+	default:
+		fprintf(out, "bad src reg type %d\n", src_type);
+		sprintf(name, "RESERVED");
+		break;
+	}
+}
+
+static void i915_get_instruction_src0(uint32_t *data, int i, char *srcname)
+{
+	uint32_t a0 = data[i];
+	uint32_t a1 = data[i + 1];
+	int src_nr = (a0 >> 2) & 0x1f;
+	const char *swizzle_x = i915_get_channel_swizzle((a1 >> 28) & 0xf);
+	const char *swizzle_y = i915_get_channel_swizzle((a1 >> 24) & 0xf);
+	const char *swizzle_z = i915_get_channel_swizzle((a1 >> 20) & 0xf);
+	const char *swizzle_w = i915_get_channel_swizzle((a1 >> 16) & 0xf);
+	char swizzle[100];
+
+	i915_get_instruction_src_name((a0 >> 7) & 0x7, src_nr, srcname);
+	sprintf(swizzle, ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z,
+		swizzle_w);
+	if (strcmp(swizzle, ".xyzw") != 0)
+		strcat(srcname, swizzle);
+}
+
+static void i915_get_instruction_src1(uint32_t *data, int i, char *srcname)
+{
+	uint32_t a1 = data[i + 1];
+	uint32_t a2 = data[i + 2];
+	int src_nr = (a1 >> 8) & 0x1f;
+	const char *swizzle_x = i915_get_channel_swizzle((a1 >> 4) & 0xf);
+	const char *swizzle_y = i915_get_channel_swizzle((a1 >> 0) & 0xf);
+	const char *swizzle_z = i915_get_channel_swizzle((a2 >> 28) & 0xf);
+	const char *swizzle_w = i915_get_channel_swizzle((a2 >> 24) & 0xf);
+	char swizzle[100];
+
+	i915_get_instruction_src_name((a1 >> 13) & 0x7, src_nr, srcname);
+	sprintf(swizzle, ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z,
+		swizzle_w);
+	if (strcmp(swizzle, ".xyzw") != 0)
+		strcat(srcname, swizzle);
+}
+
+static void i915_get_instruction_src2(uint32_t *data, int i, char *srcname)
+{
+	uint32_t a2 = data[i + 2];
+	int src_nr = (a2 >> 16) & 0x1f;
+	const char *swizzle_x = i915_get_channel_swizzle((a2 >> 12) & 0xf);
+	const char *swizzle_y = i915_get_channel_swizzle((a2 >> 8) & 0xf);
+	const char *swizzle_z = i915_get_channel_swizzle((a2 >> 4) & 0xf);
+	const char *swizzle_w = i915_get_channel_swizzle((a2 >> 0) & 0xf);
+	char swizzle[100];
+
+	i915_get_instruction_src_name((a2 >> 21) & 0x7, src_nr, srcname);
+	sprintf(swizzle, ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z,
+		swizzle_w);
+	if (strcmp(swizzle, ".xyzw") != 0)
+		strcat(srcname, swizzle);
+}
+
+static void
+i915_get_instruction_addr(uint32_t src_type, uint32_t src_nr, char *name)
+{
+	switch (src_type) {
+	case 0:
+		sprintf(name, "R%d", src_nr);
+		if (src_nr > 15)
+			fprintf(out, "bad src reg %s\n", name);
+		break;
+	case 1:
+		if (src_nr < 8)
+			sprintf(name, "T%d", src_nr);
+		else if (src_nr == 8)
+			sprintf(name, "DIFFUSE");
+		else if (src_nr == 9)
+			sprintf(name, "SPECULAR");
+		else if (src_nr == 10)
+			sprintf(name, "FOG");
+		else {
+			fprintf(out, "bad src reg T%d\n", src_nr);
+			sprintf(name, "RESERVED");
+		}
+		break;
+	case 4:
+		sprintf(name, "oC");
+		if (src_nr > 0)
+			fprintf(out, "bad src reg oC%d\n", src_nr);
+		break;
+	case 5:
+		sprintf(name, "oD");
+		if (src_nr > 0)
+			fprintf(out, "bad src reg oD%d\n", src_nr);
+		break;
+	default:
+		fprintf(out, "bad src reg type %d\n", src_type);
+		sprintf(name, "RESERVED");
+		break;
+	}
+}
+
+static void
+i915_decode_alu1(struct intel_decode *ctx,
+		 int i, char *instr_prefix, const char *op_name)
+{
+	char dst[100], src0[100];
+
+	i915_get_instruction_dst(ctx->data, i, dst, 1);
+	i915_get_instruction_src0(ctx->data, i, src0);
+
+	instr_out(ctx, i++, "%s: %s %s, %s\n", instr_prefix,
+		  op_name, dst, src0);
+	instr_out(ctx, i++, "%s\n", instr_prefix);
+	instr_out(ctx, i++, "%s\n", instr_prefix);
+}
+
+static void
+i915_decode_alu2(struct intel_decode *ctx,
+		 int i, char *instr_prefix, const char *op_name)
+{
+	char dst[100], src0[100], src1[100];
+
+	i915_get_instruction_dst(ctx->data, i, dst, 1);
+	i915_get_instruction_src0(ctx->data, i, src0);
+	i915_get_instruction_src1(ctx->data, i, src1);
+
+	instr_out(ctx, i++, "%s: %s %s, %s, %s\n", instr_prefix,
+		  op_name, dst, src0, src1);
+	instr_out(ctx, i++, "%s\n", instr_prefix);
+	instr_out(ctx, i++, "%s\n", instr_prefix);
+}
+
+static void
+i915_decode_alu3(struct intel_decode *ctx,
+		 int i, char *instr_prefix, const char *op_name)
+{
+	char dst[100], src0[100], src1[100], src2[100];
+
+	i915_get_instruction_dst(ctx->data, i, dst, 1);
+	i915_get_instruction_src0(ctx->data, i, src0);
+	i915_get_instruction_src1(ctx->data, i, src1);
+	i915_get_instruction_src2(ctx->data, i, src2);
+
+	instr_out(ctx, i++, "%s: %s %s, %s, %s, %s\n", instr_prefix,
+		  op_name, dst, src0, src1, src2);
+	instr_out(ctx, i++, "%s\n", instr_prefix);
+	instr_out(ctx, i++, "%s\n", instr_prefix);
+}
+
+static void
+i915_decode_tex(struct intel_decode *ctx, int i,
+		const char *instr_prefix, const char *tex_name)
+{
+	uint32_t t0 = ctx->data[i];
+	uint32_t t1 = ctx->data[i + 1];
+	char dst_name[100];
+	char addr_name[100];
+	int sampler_nr;
+
+	i915_get_instruction_dst(ctx->data, i, dst_name, 0);
+	i915_get_instruction_addr((t1 >> 24) & 0x7,
+				  (t1 >> 17) & 0xf, addr_name);
+	sampler_nr = t0 & 0xf;
+
+	instr_out(ctx, i++, "%s: %s %s, S%d, %s\n", instr_prefix,
+		  tex_name, dst_name, sampler_nr, addr_name);
+	instr_out(ctx, i++, "%s\n", instr_prefix);
+	instr_out(ctx, i++, "%s\n", instr_prefix);
+}
+
+static void
+i915_decode_dcl(struct intel_decode *ctx, int i, char *instr_prefix)
+{
+	uint32_t d0 = ctx->data[i];
+	const char *sampletype;
+	int dcl_nr = (d0 >> 14) & 0xf;
+	const char *dcl_x = d0 & (1 << 10) ? "x" : "";
+	const char *dcl_y = d0 & (1 << 11) ? "y" : "";
+	const char *dcl_z = d0 & (1 << 12) ? "z" : "";
+	const char *dcl_w = d0 & (1 << 13) ? "w" : "";
+	char dcl_mask[10];
+
+	switch ((d0 >> 19) & 0x3) {
+	case 1:
+		sprintf(dcl_mask, ".%s%s%s%s", dcl_x, dcl_y, dcl_z, dcl_w);
+		if (strcmp(dcl_mask, ".") == 0)
+			fprintf(out, "bad (empty) dcl mask\n");
+
+		if (dcl_nr > 10)
+			fprintf(out, "bad T%d dcl register number\n", dcl_nr);
+		if (dcl_nr < 8) {
+			if (strcmp(dcl_mask, ".x") != 0 &&
+			    strcmp(dcl_mask, ".xy") != 0 &&
+			    strcmp(dcl_mask, ".xz") != 0 &&
+			    strcmp(dcl_mask, ".w") != 0 &&
+			    strcmp(dcl_mask, ".xyzw") != 0) {
+				fprintf(out, "bad T%d.%s dcl mask\n", dcl_nr,
+					dcl_mask);
+			}
+			instr_out(ctx, i++, "%s: DCL T%d%s\n",
+				  instr_prefix, dcl_nr, dcl_mask);
+		} else {
+			if (strcmp(dcl_mask, ".xz") == 0)
+				fprintf(out, "errataed bad dcl mask %s\n",
+					dcl_mask);
+			else if (strcmp(dcl_mask, ".xw") == 0)
+				fprintf(out, "errataed bad dcl mask %s\n",
+					dcl_mask);
+			else if (strcmp(dcl_mask, ".xzw") == 0)
+				fprintf(out, "errataed bad dcl mask %s\n",
+					dcl_mask);
+
+			if (dcl_nr == 8) {
+				instr_out(ctx, i++,
+					  "%s: DCL DIFFUSE%s\n", instr_prefix,
+					  dcl_mask);
+			} else if (dcl_nr == 9) {
+				instr_out(ctx, i++,
+					  "%s: DCL SPECULAR%s\n", instr_prefix,
+					  dcl_mask);
+			} else if (dcl_nr == 10) {
+				instr_out(ctx, i++,
+					  "%s: DCL FOG%s\n", instr_prefix,
+					  dcl_mask);
+			}
+		}
+		instr_out(ctx, i++, "%s\n", instr_prefix);
+		instr_out(ctx, i++, "%s\n", instr_prefix);
+		break;
+	case 3:
+		switch ((d0 >> 22) & 0x3) {
+		case 0:
+			sampletype = "2D";
+			break;
+		case 1:
+			sampletype = "CUBE";
+			break;
+		case 2:
+			sampletype = "3D";
+			break;
+		default:
+			sampletype = "RESERVED";
+			break;
+		}
+		if (dcl_nr > 15)
+			fprintf(out, "bad S%d dcl register number\n", dcl_nr);
+		instr_out(ctx, i++, "%s: DCL S%d %s\n",
+			  instr_prefix, dcl_nr, sampletype);
+		instr_out(ctx, i++, "%s\n", instr_prefix);
+		instr_out(ctx, i++, "%s\n", instr_prefix);
+		break;
+	default:
+		instr_out(ctx, i++, "%s: DCL RESERVED%d\n",
+			  instr_prefix, dcl_nr);
+		instr_out(ctx, i++, "%s\n", instr_prefix);
+		instr_out(ctx, i++, "%s\n", instr_prefix);
+	}
+}
+
+static void
+i915_decode_instruction(struct intel_decode *ctx,
+			int i, char *instr_prefix)
+{
+	switch ((ctx->data[i] >> 24) & 0x1f) {
+	case 0x0:
+		instr_out(ctx, i++, "%s: NOP\n", instr_prefix);
+		instr_out(ctx, i++, "%s\n", instr_prefix);
+		instr_out(ctx, i++, "%s\n", instr_prefix);
+		break;
+	case 0x01:
+		i915_decode_alu2(ctx, i, instr_prefix, "ADD");
+		break;
+	case 0x02:
+		i915_decode_alu1(ctx, i, instr_prefix, "MOV");
+		break;
+	case 0x03:
+		i915_decode_alu2(ctx, i, instr_prefix, "MUL");
+		break;
+	case 0x04:
+		i915_decode_alu3(ctx, i, instr_prefix, "MAD");
+		break;
+	case 0x05:
+		i915_decode_alu3(ctx, i, instr_prefix, "DP2ADD");
+		break;
+	case 0x06:
+		i915_decode_alu2(ctx, i, instr_prefix, "DP3");
+		break;
+	case 0x07:
+		i915_decode_alu2(ctx, i, instr_prefix, "DP4");
+		break;
+	case 0x08:
+		i915_decode_alu1(ctx, i, instr_prefix, "FRC");
+		break;
+	case 0x09:
+		i915_decode_alu1(ctx, i, instr_prefix, "RCP");
+		break;
+	case 0x0a:
+		i915_decode_alu1(ctx, i, instr_prefix, "RSQ");
+		break;
+	case 0x0b:
+		i915_decode_alu1(ctx, i, instr_prefix, "EXP");
+		break;
+	case 0x0c:
+		i915_decode_alu1(ctx, i, instr_prefix, "LOG");
+		break;
+	case 0x0d:
+		i915_decode_alu2(ctx, i, instr_prefix, "CMP");
+		break;
+	case 0x0e:
+		i915_decode_alu2(ctx, i, instr_prefix, "MIN");
+		break;
+	case 0x0f:
+		i915_decode_alu2(ctx, i, instr_prefix, "MAX");
+		break;
+	case 0x10:
+		i915_decode_alu1(ctx, i, instr_prefix, "FLR");
+		break;
+	case 0x11:
+		i915_decode_alu1(ctx, i, instr_prefix, "MOD");
+		break;
+	case 0x12:
+		i915_decode_alu1(ctx, i, instr_prefix, "TRC");
+		break;
+	case 0x13:
+		i915_decode_alu2(ctx, i, instr_prefix, "SGE");
+		break;
+	case 0x14:
+		i915_decode_alu2(ctx, i, instr_prefix, "SLT");
+		break;
+	case 0x15:
+		i915_decode_tex(ctx, i, instr_prefix, "TEXLD");
+		break;
+	case 0x16:
+		i915_decode_tex(ctx, i, instr_prefix, "TEXLDP");
+		break;
+	case 0x17:
+		i915_decode_tex(ctx, i, instr_prefix, "TEXLDB");
+		break;
+	case 0x19:
+		i915_decode_dcl(ctx, i, instr_prefix);
+		break;
+	default:
+		instr_out(ctx, i++, "%s: unknown\n", instr_prefix);
+		instr_out(ctx, i++, "%s\n", instr_prefix);
+		instr_out(ctx, i++, "%s\n", instr_prefix);
+		break;
+	}
+}
+
+static const char *
+decode_compare_func(uint32_t op)
+{
+	switch (op & 0x7) {
+	case 0:
+		return "always";
+	case 1:
+		return "never";
+	case 2:
+		return "less";
+	case 3:
+		return "equal";
+	case 4:
+		return "lequal";
+	case 5:
+		return "greater";
+	case 6:
+		return "notequal";
+	case 7:
+		return "gequal";
+	}
+	return "";
+}
+
+static const char *
+decode_stencil_op(uint32_t op)
+{
+	switch (op & 0x7) {
+	case 0:
+		return "keep";
+	case 1:
+		return "zero";
+	case 2:
+		return "replace";
+	case 3:
+		return "incr_sat";
+	case 4:
+		return "decr_sat";
+	case 5:
+		return "greater";
+	case 6:
+		return "incr";
+	case 7:
+		return "decr";
+	}
+	return "";
+}
+
+#if 0
+static const char *
+decode_logic_op(uint32_t op)
+{
+	switch (op & 0xf) {
+	case 0:
+		return "clear";
+	case 1:
+		return "nor";
+	case 2:
+		return "and_inv";
+	case 3:
+		return "copy_inv";
+	case 4:
+		return "and_rvrse";
+	case 5:
+		return "inv";
+	case 6:
+		return "xor";
+	case 7:
+		return "nand";
+	case 8:
+		return "and";
+	case 9:
+		return "equiv";
+	case 10:
+		return "noop";
+	case 11:
+		return "or_inv";
+	case 12:
+		return "copy";
+	case 13:
+		return "or_rvrse";
+	case 14:
+		return "or";
+	case 15:
+		return "set";
+	}
+	return "";
+}
+#endif
+
+static const char *
+decode_blend_fact(uint32_t op)
+{
+	switch (op & 0xf) {
+	case 1:
+		return "zero";
+	case 2:
+		return "one";
+	case 3:
+		return "src_colr";
+	case 4:
+		return "inv_src_colr";
+	case 5:
+		return "src_alpha";
+	case 6:
+		return "inv_src_alpha";
+	case 7:
+		return "dst_alpha";
+	case 8:
+		return "inv_dst_alpha";
+	case 9:
+		return "dst_colr";
+	case 10:
+		return "inv_dst_colr";
+	case 11:
+		return "src_alpha_sat";
+	case 12:
+		return "cnst_colr";
+	case 13:
+		return "inv_cnst_colr";
+	case 14:
+		return "cnst_alpha";
+	case 15:
+		return "inv_const_alpha";
+	}
+	return "";
+}
+
+static const char *
+decode_tex_coord_mode(uint32_t mode)
+{
+	switch (mode & 0x7) {
+	case 0:
+		return "wrap";
+	case 1:
+		return "mirror";
+	case 2:
+		return "clamp_edge";
+	case 3:
+		return "cube";
+	case 4:
+		return "clamp_border";
+	case 5:
+		return "mirror_once";
+	}
+	return "";
+}
+
+static const char *
+decode_sample_filter(uint32_t mode)
+{
+	switch (mode & 0x7) {
+	case 0:
+		return "nearest";
+	case 1:
+		return "linear";
+	case 2:
+		return "anisotropic";
+	case 3:
+		return "4x4_1";
+	case 4:
+		return "4x4_2";
+	case 5:
+		return "4x4_flat";
+	case 6:
+		return "6x5_mono";
+	}
+	return "";
+}
+
+static int
+decode_3d_1d(struct intel_decode *ctx)
+{
+	unsigned int len, i, c, idx, word, map, sampler, instr;
+	const char *format, *zformat, *type;
+	uint32_t opcode;
+	uint32_t *data = ctx->data;
+	uint32_t devid = ctx->devid;
+
+	struct {
+		uint32_t opcode;
+		int i830_only;
+		unsigned int min_len;
+		unsigned int max_len;
+		const char *name;
+	} opcodes_3d_1d[] = {
+		{ 0x86, 0, 4, 4, "3DSTATE_CHROMA_KEY" },
+		{ 0x88, 0, 2, 2, "3DSTATE_CONSTANT_BLEND_COLOR" },
+		{ 0x99, 0, 2, 2, "3DSTATE_DEFAULT_DIFFUSE" },
+		{ 0x9a, 0, 2, 2, "3DSTATE_DEFAULT_SPECULAR" },
+		{ 0x98, 0, 2, 2, "3DSTATE_DEFAULT_Z" },
+		{ 0x97, 0, 2, 2, "3DSTATE_DEPTH_OFFSET_SCALE" },
+		{ 0x9d, 0, 65, 65, "3DSTATE_FILTER_COEFFICIENTS_4X4" },
+		{ 0x9e, 0, 4, 4, "3DSTATE_MONO_FILTER" },
+		{ 0x89, 0, 4, 4, "3DSTATE_FOG_MODE" },
+		{ 0x8f, 0, 2, 16, "3DSTATE_MAP_PALLETE_LOAD_32" },
+		{ 0x83, 0, 2, 2, "3DSTATE_SPAN_STIPPLE" },
+		{ 0x8c, 1, 2, 2, "3DSTATE_MAP_COORD_TRANSFORM_I830" },
+		{ 0x8b, 1, 2, 2, "3DSTATE_MAP_VERTEX_TRANSFORM_I830" },
+		{ 0x8d, 1, 3, 3, "3DSTATE_W_STATE_I830" },
+		{ 0x01, 1, 2, 2, "3DSTATE_COLOR_FACTOR_I830" },
+		{ 0x02, 1, 2, 2, "3DSTATE_MAP_COORD_SETBIND_I830"},
+	}, *opcode_3d_1d;
+
+	opcode = (data[0] & 0x00ff0000) >> 16;
+
+	switch (opcode) {
+	case 0x07:
+		/* This instruction is unusual.  A 0 length means just
+		 * 1 DWORD instead of 2.  The 0 length is specified in
+		 * one place to be unsupported, but stated to be
+		 * required in another, and 0 length LOAD_INDIRECTs
+		 * appear to cause no harm at least.
+		 */
+		instr_out(ctx, 0, "3DSTATE_LOAD_INDIRECT\n");
+		len = (data[0] & 0x000000ff) + 1;
+		i = 1;
+		if (data[0] & (0x01 << 8)) {
+			instr_out(ctx, i++, "SIS.0\n");
+			instr_out(ctx, i++, "SIS.1\n");
+		}
+		if (data[0] & (0x02 << 8)) {
+			instr_out(ctx, i++, "DIS.0\n");
+		}
+		if (data[0] & (0x04 << 8)) {
+			instr_out(ctx, i++, "SSB.0\n");
+			instr_out(ctx, i++, "SSB.1\n");
+		}
+		if (data[0] & (0x08 << 8)) {
+			instr_out(ctx, i++, "MSB.0\n");
+			instr_out(ctx, i++, "MSB.1\n");
+		}
+		if (data[0] & (0x10 << 8)) {
+			instr_out(ctx, i++, "PSP.0\n");
+			instr_out(ctx, i++, "PSP.1\n");
+		}
+		if (data[0] & (0x20 << 8)) {
+			instr_out(ctx, i++, "PSC.0\n");
+			instr_out(ctx, i++, "PSC.1\n");
+		}
+		if (len != i) {
+			fprintf(out, "Bad count in 3DSTATE_LOAD_INDIRECT\n");
+			return len;
+		}
+		return len;
+	case 0x04:
+		instr_out(ctx, 0,
+			  "3DSTATE_LOAD_STATE_IMMEDIATE_1\n");
+		len = (data[0] & 0x0000000f) + 2;
+		i = 1;
+		for (word = 0; word <= 8; word++) {
+			if (data[0] & (1 << (4 + word))) {
+				/* save vertex state for decode */
+				if (!IS_GEN2(devid)) {
+					int tex_num;
+
+					if (word == 2) {
+						saved_s2_set = 1;
+						saved_s2 = data[i];
+					}
+					if (word == 4) {
+						saved_s4_set = 1;
+						saved_s4 = data[i];
+					}
+
+					switch (word) {
+					case 0:
+						instr_out(ctx, i,
+							  "S0: vbo offset: 0x%08x%s\n",
+							  data[i] & (~1),
+							  data[i] & 1 ?
+							  ", auto cache invalidate disabled"
+							  : "");
+						break;
+					case 1:
+						instr_out(ctx, i,
+							  "S1: vertex width: %i, vertex pitch: %i\n",
+							  (data[i] >> 24) &
+							  0x3f,
+							  (data[i] >> 16) &
+							  0x3f);
+						break;
+					case 2:
+						instr_out(ctx, i,
+							  "S2: texcoord formats: ");
+						for (tex_num = 0;
+						     tex_num < 8; tex_num++) {
+							switch ((data[i] >>
+								 tex_num *
+								 4) & 0xf) {
+							case 0:
+								fprintf(out,
+									"%i=2D ",
+									tex_num);
+								break;
+							case 1:
+								fprintf(out,
+									"%i=3D ",
+									tex_num);
+								break;
+							case 2:
+								fprintf(out,
+									"%i=4D ",
+									tex_num);
+								break;
+							case 3:
+								fprintf(out,
+									"%i=1D ",
+									tex_num);
+								break;
+							case 4:
+								fprintf(out,
+									"%i=2D_16 ",
+									tex_num);
+								break;
+							case 5:
+								fprintf(out,
+									"%i=4D_16 ",
+									tex_num);
+								break;
+							case 0xf:
+								fprintf(out,
+									"%i=NP ",
+									tex_num);
+								break;
+							}
+						}
+						fprintf(out, "\n");
+
+						break;
+					case 3:
+						instr_out(ctx, i,
+							  "S3: not documented\n");
+						break;
+					case 4:
+						{
+							const char *cullmode = "";
+							const char *vfmt_xyzw = "";
+							switch ((data[i] >> 13)
+								& 0x3) {
+							case 0:
+								cullmode =
+								    "both";
+								break;
+							case 1:
+								cullmode =
+								    "none";
+								break;
+							case 2:
+								cullmode = "cw";
+								break;
+							case 3:
+								cullmode =
+								    "ccw";
+								break;
+							}
+							switch (data[i] &
+								(7 << 6 | 1 <<
+								 2)) {
+							case 1 << 6:
+								vfmt_xyzw =
+								    "XYZ,";
+								break;
+							case 2 << 6:
+								vfmt_xyzw =
+								    "XYZW,";
+								break;
+							case 3 << 6:
+								vfmt_xyzw =
+								    "XY,";
+								break;
+							case 4 << 6:
+								vfmt_xyzw =
+								    "XYW,";
+								break;
+							case 1 << 6 | 1 << 2:
+								vfmt_xyzw =
+								    "XYZF,";
+								break;
+							case 2 << 6 | 1 << 2:
+								vfmt_xyzw =
+								    "XYZWF,";
+								break;
+							case 3 << 6 | 1 << 2:
+								vfmt_xyzw =
+								    "XYF,";
+								break;
+							case 4 << 6 | 1 << 2:
+								vfmt_xyzw =
+								    "XYWF,";
+								break;
+							}
+							instr_out(ctx, i,
+								  "S4: point_width=%i, line_width=%.1f,"
+								  "%s%s%s%s%s cullmode=%s, vfmt=%s%s%s%s%s%s "
+								  "%s%s%s%s%s\n",
+								  (data[i] >>
+								   23) & 0x1ff,
+								  ((data[i] >>
+								    19) & 0xf) /
+								  2.0,
+								  data[i] & (0xf
+									     <<
+									     15)
+								  ?
+								  " flatshade="
+								  : "",
+								  data[i] & (1
+									     <<
+									     18)
+								  ? "Alpha," :
+								  "",
+								  data[i] & (1
+									     <<
+									     17)
+								  ? "Fog," : "",
+								  data[i] & (1
+									     <<
+									     16)
+								  ? "Specular,"
+								  : "",
+								  data[i] & (1
+									     <<
+									     15)
+								  ? "Color," :
+								  "", cullmode,
+								  data[i] & (1
+									     <<
+									     12)
+								  ?
+								  "PointWidth,"
+								  : "",
+								  data[i] & (1
+									     <<
+									     11)
+								  ? "SpecFog," :
+								  "",
+								  data[i] & (1
+									     <<
+									     10)
+								  ? "Color," :
+								  "",
+								  data[i] & (1
+									     <<
+									     9)
+								  ? "DepthOfs,"
+								  : "",
+								  vfmt_xyzw,
+								  data[i] & (1
+									     <<
+									     9)
+								  ? "FogParam,"
+								  : "",
+								  data[i] & (1
+									     <<
+									     5)
+								  ?
+								  "force default diffuse, "
+								  : "",
+								  data[i] & (1
+									     <<
+									     4)
+								  ?
+								  "force default specular, "
+								  : "",
+								  data[i] & (1
+									     <<
+									     3)
+								  ?
+								  "local depth ofs enable, "
+								  : "",
+								  data[i] & (1
+									     <<
+									     1)
+								  ?
+								  "point sprite enable, "
+								  : "",
+								  data[i] & (1
+									     <<
+									     0)
+								  ?
+								  "line AA enable, "
+								  : "");
+							break;
+						}
+					case 5:
+						{
+							instr_out(ctx, i,
+								  "S5:%s%s%s%s%s"
+								  "%s%s%s%s stencil_ref=0x%x, stencil_test=%s, "
+								  "stencil_fail=%s, stencil_pass_z_fail=%s, "
+								  "stencil_pass_z_pass=%s, %s%s%s%s\n",
+								  data[i] & (0xf
+									     <<
+									     28)
+								  ?
+								  " write_disable="
+								  : "",
+								  data[i] & (1
+									     <<
+									     31)
+								  ? "Alpha," :
+								  "",
+								  data[i] & (1
+									     <<
+									     30)
+								  ? "Red," : "",
+								  data[i] & (1
+									     <<
+									     29)
+								  ? "Green," :
+								  "",
+								  data[i] & (1
+									     <<
+									     28)
+								  ? "Blue," :
+								  "",
+								  data[i] & (1
+									     <<
+									     27)
+								  ?
+								  " force default point size,"
+								  : "",
+								  data[i] & (1
+									     <<
+									     26)
+								  ?
+								  " last pixel enable,"
+								  : "",
+								  data[i] & (1
+									     <<
+									     25)
+								  ?
+								  " global depth ofs enable,"
+								  : "",
+								  data[i] & (1
+									     <<
+									     24)
+								  ?
+								  " fog enable,"
+								  : "",
+								  (data[i] >>
+								   16) & 0xff,
+								  decode_compare_func
+								  (data[i] >>
+								   13),
+								  decode_stencil_op
+								  (data[i] >>
+								   10),
+								  decode_stencil_op
+								  (data[i] >>
+								   7),
+								  decode_stencil_op
+								  (data[i] >>
+								   4),
+								  data[i] & (1
+									     <<
+									     3)
+								  ?
+								  "stencil write enable, "
+								  : "",
+								  data[i] & (1
+									     <<
+									     2)
+								  ?
+								  "stencil test enable, "
+								  : "",
+								  data[i] & (1
+									     <<
+									     1)
+								  ?
+								  "color dither enable, "
+								  : "",
+								  data[i] & (1
+									     <<
+									     0)
+								  ?
+								  "logicop enable, "
+								  : "");
+						}
+						break;
+					case 6:
+						instr_out(ctx, i,
+							  "S6: %salpha_test=%s, alpha_ref=0x%x, "
+							  "depth_test=%s, %ssrc_blnd_fct=%s, dst_blnd_fct=%s, "
+							  "%s%stristrip_provoking_vertex=%i\n",
+							  data[i] & (1 << 31) ?
+							  "alpha test enable, "
+							  : "",
+							  decode_compare_func
+							  (data[i] >> 28),
+							  data[i] & (0xff <<
+								     20),
+							  decode_compare_func
+							  (data[i] >> 16),
+							  data[i] & (1 << 15) ?
+							  "cbuf blend enable, "
+							  : "",
+							  decode_blend_fact(data
+									    [i]
+									    >>
+									    8),
+							  decode_blend_fact(data
+									    [i]
+									    >>
+									    4),
+							  data[i] & (1 << 3) ?
+							  "depth write enable, "
+							  : "",
+							  data[i] & (1 << 2) ?
+							  "cbuf write enable, "
+							  : "",
+							  data[i] & (0x3));
+						break;
+					case 7:
+						instr_out(ctx, i,
+							  "S7: depth offset constant: 0x%08x\n",
+							  data[i]);
+						break;
+					}
+				} else {
+					instr_out(ctx, i,
+						  "S%d: 0x%08x\n", word, data[i]);
+				}
+				i++;
+			}
+		}
+		if (len != i) {
+			fprintf(out,
+				"Bad count in 3DSTATE_LOAD_STATE_IMMEDIATE_1\n");
+		}
+		return len;
+	case 0x03:
+		instr_out(ctx, 0,
+			  "3DSTATE_LOAD_STATE_IMMEDIATE_2\n");
+		len = (data[0] & 0x0000000f) + 2;
+		i = 1;
+		for (word = 6; word <= 14; word++) {
+			if (data[0] & (1 << word)) {
+				if (word == 6)
+					instr_out(ctx, i++,
+						  "TBCF\n");
+				else if (word >= 7 && word <= 10) {
+					instr_out(ctx, i++,
+						  "TB%dC\n", word - 7);
+					instr_out(ctx, i++,
+						  "TB%dA\n", word - 7);
+				} else if (word >= 11 && word <= 14) {
+					instr_out(ctx, i,
+						  "TM%dS0: offset=0x%08x, %s\n",
+						  word - 11,
+						  data[i] & 0xfffffffe,
+						  data[i] & 1 ? "use fence" :
+						  "");
+					i++;
+					instr_out(ctx, i,
+						  "TM%dS1: height=%i, width=%i, %s\n",
+						  word - 11, data[i] >> 21,
+						  (data[i] >> 10) & 0x3ff,
+						  data[i] & 2 ? (data[i] & 1 ?
+								 "y-tiled" :
+								 "x-tiled") :
+						  "");
+					i++;
+					instr_out(ctx, i,
+						  "TM%dS2: pitch=%i, \n",
+						  word - 11,
+						  ((data[i] >> 21) + 1) * 4);
+					i++;
+					instr_out(ctx, i++,
+						  "TM%dS3\n", word - 11);
+					instr_out(ctx, i++,
+						  "TM%dS4: dflt color\n",
+						  word - 11);
+				}
+			}
+		}
+		if (len != i) {
+			fprintf(out,
+				"Bad count in 3DSTATE_LOAD_STATE_IMMEDIATE_2\n");
+		}
+		return len;
+	case 0x00:
+		instr_out(ctx, 0, "3DSTATE_MAP_STATE\n");
+		len = (data[0] & 0x0000003f) + 2;
+		instr_out(ctx, 1, "mask\n");
+
+		i = 2;
+		for (map = 0; map <= 15; map++) {
+			if (data[1] & (1 << map)) {
+				int width, height, pitch, dword;
+				const char *tiling;
+
+				dword = data[i];
+				instr_out(ctx, i++,
+					  "map %d MS2 %s%s%s\n", map,
+					  dword & (1 << 31) ?
+					  "untrusted surface, " : "",
+					  dword & (1 << 1) ?
+					  "vertical line stride enable, " : "",
+					  dword & (1 << 0) ?
+					  "vertical ofs enable, " : "");
+
+				dword = data[i];
+				width = ((dword >> 10) & ((1 << 11) - 1)) + 1;
+				height = ((dword >> 21) & ((1 << 11) - 1)) + 1;
+
+				tiling = "none";
+				if (dword & (1 << 2))
+					tiling = "fenced";
+				else if (dword & (1 << 1))
+					tiling = dword & (1 << 0) ? "Y" : "X";
+				type = " BAD";
+				format = "BAD";
+				switch ((dword >> 7) & 0x7) {
+				case 1:
+					type = "8b";
+					switch ((dword >> 3) & 0xf) {
+					case 0:
+						format = "I";
+						break;
+					case 1:
+						format = "L";
+						break;
+					case 4:
+						format = "A";
+						break;
+					case 5:
+						format = " mono";
+						break;
+					}
+					break;
+				case 2:
+					type = "16b";
+					switch ((dword >> 3) & 0xf) {
+					case 0:
+						format = " rgb565";
+						break;
+					case 1:
+						format = " argb1555";
+						break;
+					case 2:
+						format = " argb4444";
+						break;
+					case 5:
+						format = " ay88";
+						break;
+					case 6:
+						format = " bump655";
+						break;
+					case 7:
+						format = "I";
+						break;
+					case 8:
+						format = "L";
+						break;
+					case 9:
+						format = "A";
+						break;
+					}
+					break;
+				case 3:
+					type = "32b";
+					switch ((dword >> 3) & 0xf) {
+					case 0:
+						format = " argb8888";
+						break;
+					case 1:
+						format = " abgr8888";
+						break;
+					case 2:
+						format = " xrgb8888";
+						break;
+					case 3:
+						format = " xbgr8888";
+						break;
+					case 4:
+						format = " qwvu8888";
+						break;
+					case 5:
+						format = " axvu8888";
+						break;
+					case 6:
+						format = " lxvu8888";
+						break;
+					case 7:
+						format = " xlvu8888";
+						break;
+					case 8:
+						format = " argb2101010";
+						break;
+					case 9:
+						format = " abgr2101010";
+						break;
+					case 10:
+						format = " awvu2101010";
+						break;
+					case 11:
+						format = " gr1616";
+						break;
+					case 12:
+						format = " vu1616";
+						break;
+					case 13:
+						format = " xI824";
+						break;
+					case 14:
+						format = " xA824";
+						break;
+					case 15:
+						format = " xL824";
+						break;
+					}
+					break;
+				case 5:
+					type = "422";
+					switch ((dword >> 3) & 0xf) {
+					case 0:
+						format = " yuv_swapy";
+						break;
+					case 1:
+						format = " yuv";
+						break;
+					case 2:
+						format = " yuv_swapuv";
+						break;
+					case 3:
+						format = " yuv_swapuvy";
+						break;
+					}
+					break;
+				case 6:
+					type = "compressed";
+					switch ((dword >> 3) & 0x7) {
+					case 0:
+						format = " dxt1";
+						break;
+					case 1:
+						format = " dxt2_3";
+						break;
+					case 2:
+						format = " dxt4_5";
+						break;
+					case 3:
+						format = " fxt1";
+						break;
+					case 4:
+						format = " dxt1_rb";
+						break;
+					}
+					break;
+				case 7:
+					type = "4b indexed";
+					switch ((dword >> 3) & 0xf) {
+					case 7:
+						format = " argb8888";
+						break;
+					}
+					break;
+				}
+				dword = data[i];
+				instr_out(ctx, i++,
+					  "map %d MS3 [width=%d, height=%d, format=%s%s, tiling=%s%s]\n",
+					  map, width, height, type, format,
+					  tiling,
+					  dword & (1 << 9) ? " palette select" :
+					  "");
+
+				dword = data[i];
+				pitch =
+				    4 * (((dword >> 21) & ((1 << 11) - 1)) + 1);
+				instr_out(ctx, i++,
+					  "map %d MS4 [pitch=%d, max_lod=%i, vol_depth=%i, cube_face_ena=%x, %s]\n",
+					  map, pitch, (dword >> 9) & 0x3f,
+					  dword & 0xff, (dword >> 15) & 0x3f,
+					  dword & (1 << 8) ? "miplayout legacy"
+					  : "miplayout right");
+			}
+		}
+		if (len != i) {
+			fprintf(out, "Bad count in 3DSTATE_MAP_STATE\n");
+			return len;
+		}
+		return len;
+	case 0x06:
+		instr_out(ctx, 0,
+			  "3DSTATE_PIXEL_SHADER_CONSTANTS\n");
+		len = (data[0] & 0x000000ff) + 2;
+
+		i = 2;
+		for (c = 0; c <= 31; c++) {
+			if (data[1] & (1 << c)) {
+				instr_out(ctx, i, "C%d.X = %f\n", c,
+					  int_as_float(data[i]));
+				i++;
+				instr_out(ctx, i, "C%d.Y = %f\n",
+					  c, int_as_float(data[i]));
+				i++;
+				instr_out(ctx, i, "C%d.Z = %f\n",
+					  c, int_as_float(data[i]));
+				i++;
+				instr_out(ctx, i, "C%d.W = %f\n",
+					  c, int_as_float(data[i]));
+				i++;
+			}
+		}
+		if (len != i) {
+			fprintf(out,
+				"Bad count in 3DSTATE_PIXEL_SHADER_CONSTANTS\n");
+		}
+		return len;
+	case 0x05:
+		instr_out(ctx, 0, "3DSTATE_PIXEL_SHADER_PROGRAM\n");
+		len = (data[0] & 0x000000ff) + 2;
+		if ((len - 1) % 3 != 0 || len > 370) {
+			fprintf(out,
+				"Bad count in 3DSTATE_PIXEL_SHADER_PROGRAM\n");
+		}
+		i = 1;
+		for (instr = 0; instr < (len - 1) / 3; instr++) {
+			char instr_prefix[10];
+
+			sprintf(instr_prefix, "PS%03d", instr);
+			i915_decode_instruction(ctx, i,
+						instr_prefix);
+			i += 3;
+		}
+		return len;
+	case 0x01:
+		if (IS_GEN2(devid))
+			break;
+		instr_out(ctx, 0, "3DSTATE_SAMPLER_STATE\n");
+		instr_out(ctx, 1, "mask\n");
+		len = (data[0] & 0x0000003f) + 2;
+		i = 2;
+		for (sampler = 0; sampler <= 15; sampler++) {
+			if (data[1] & (1 << sampler)) {
+				uint32_t dword;
+				const char *mip_filter = "";
+
+				dword = data[i];
+				switch ((dword >> 20) & 0x3) {
+				case 0:
+					mip_filter = "none";
+					break;
+				case 1:
+					mip_filter = "nearest";
+					break;
+				case 3:
+					mip_filter = "linear";
+					break;
+				}
+				instr_out(ctx, i++,
+					  "sampler %d SS2:%s%s%s "
+					  "base_mip_level=%i, mip_filter=%s, mag_filter=%s, min_filter=%s "
+					  "lod_bias=%.2f,%s max_aniso=%i, shadow_func=%s\n",
+					  sampler,
+					  dword & (1 << 31) ? " reverse gamma,"
+					  : "",
+					  dword & (1 << 30) ? " packed2planar,"
+					  : "",
+					  dword & (1 << 29) ?
+					  " colorspace conversion," : "",
+					  (dword >> 22) & 0x1f, mip_filter,
+					  decode_sample_filter(dword >> 17),
+					  decode_sample_filter(dword >> 14),
+					  ((dword >> 5) & 0x1ff) / (0x10 * 1.0),
+					  dword & (1 << 4) ? " shadow," : "",
+					  dword & (1 << 3) ? 4 : 2,
+					  decode_compare_func(dword));
+				dword = data[i];
+				instr_out(ctx, i++,
+					  "sampler %d SS3: min_lod=%.2f,%s "
+					  "tcmode_x=%s, tcmode_y=%s, tcmode_z=%s,%s texmap_idx=%i,%s\n",
+					  sampler,
+					  ((dword >> 24) & 0xff) / (0x10 * 1.0),
+					  dword & (1 << 17) ?
+					  " kill pixel enable," : "",
+					  decode_tex_coord_mode(dword >> 12),
+					  decode_tex_coord_mode(dword >> 9),
+					  decode_tex_coord_mode(dword >> 6),
+					  dword & (1 << 5) ?
+					  " normalized coords," : "",
+					  (dword >> 1) & 0xf,
+					  dword & (1 << 0) ? " deinterlacer," :
+					  "");
+				dword = data[i];
+				instr_out(ctx, i++,
+					  "sampler %d SS4: border color\n",
+					  sampler);
+			}
+		}
+		if (len != i) {
+			fprintf(out, "Bad count in 3DSTATE_SAMPLER_STATE\n");
+		}
+		return len;
+	case 0x85:
+		len = (data[0] & 0x0000000f) + 2;
+
+		if (len != 2)
+			fprintf(out,
+				"Bad count in 3DSTATE_DEST_BUFFER_VARIABLES\n");
+
+		instr_out(ctx, 0,
+			  "3DSTATE_DEST_BUFFER_VARIABLES\n");
+
+		switch ((data[1] >> 8) & 0xf) {
+		case 0x0:
+			format = "g8";
+			break;
+		case 0x1:
+			format = "x1r5g5b5";
+			break;
+		case 0x2:
+			format = "r5g6b5";
+			break;
+		case 0x3:
+			format = "a8r8g8b8";
+			break;
+		case 0x4:
+			format = "ycrcb_swapy";
+			break;
+		case 0x5:
+			format = "ycrcb_normal";
+			break;
+		case 0x6:
+			format = "ycrcb_swapuv";
+			break;
+		case 0x7:
+			format = "ycrcb_swapuvy";
+			break;
+		case 0x8:
+			format = "a4r4g4b4";
+			break;
+		case 0x9:
+			format = "a1r5g5b5";
+			break;
+		case 0xa:
+			format = "a2r10g10b10";
+			break;
+		default:
+			format = "BAD";
+			break;
+		}
+		switch ((data[1] >> 2) & 0x3) {
+		case 0x0:
+			zformat = "u16";
+			break;
+		case 0x1:
+			zformat = "f16";
+			break;
+		case 0x2:
+			zformat = "u24x8";
+			break;
+		default:
+			zformat = "BAD";
+			break;
+		}
+		instr_out(ctx, 1,
+			  "%s format, %s depth format, early Z %sabled\n",
+			  format, zformat,
+			  (data[1] & (1 << 31)) ? "en" : "dis");
+		return len;
+
+	case 0x8e:
+		{
+			const char *name, *tiling;
+
+			len = (data[0] & 0x0000000f) + 2;
+			if (len != 3)
+				fprintf(out,
+					"Bad count in 3DSTATE_BUFFER_INFO\n");
+
+			switch ((data[1] >> 24) & 0x7) {
+			case 0x3:
+				name = "color";
+				break;
+			case 0x7:
+				name = "depth";
+				break;
+			default:
+				name = "unknown";
+				break;
+			}
+
+			tiling = "none";
+			if (data[1] & (1 << 23))
+				tiling = "fenced";
+			else if (data[1] & (1 << 22))
+				tiling = data[1] & (1 << 21) ? "Y" : "X";
+
+			instr_out(ctx, 0, "3DSTATE_BUFFER_INFO\n");
+			instr_out(ctx, 1,
+				  "%s, tiling = %s, pitch=%d\n", name, tiling,
+				  data[1] & 0xffff);
+
+			instr_out(ctx, 2, "address\n");
+			return len;
+		}
+	case 0x81:
+		len = (data[0] & 0x0000000f) + 2;
+
+		if (len != 3)
+			fprintf(out,
+				"Bad count in 3DSTATE_SCISSOR_RECTANGLE\n");
+
+		instr_out(ctx, 0, "3DSTATE_SCISSOR_RECTANGLE\n");
+		instr_out(ctx, 1, "(%d,%d)\n",
+			  data[1] & 0xffff, data[1] >> 16);
+		instr_out(ctx, 2, "(%d,%d)\n",
+			  data[2] & 0xffff, data[2] >> 16);
+
+		return len;
+	case 0x80:
+		len = (data[0] & 0x0000000f) + 2;
+
+		if (len != 5)
+			fprintf(out,
+				"Bad count in 3DSTATE_DRAWING_RECTANGLE\n");
+
+		instr_out(ctx, 0, "3DSTATE_DRAWING_RECTANGLE\n");
+		instr_out(ctx, 1, "%s\n",
+			  data[1] & (1 << 30) ? "depth ofs disabled " : "");
+		instr_out(ctx, 2, "(%d,%d)\n",
+			  data[2] & 0xffff, data[2] >> 16);
+		instr_out(ctx, 3, "(%d,%d)\n",
+			  data[3] & 0xffff, data[3] >> 16);
+		instr_out(ctx, 4, "(%d,%d)\n",
+			  data[4] & 0xffff, data[4] >> 16);
+
+		return len;
+	case 0x9c:
+		len = (data[0] & 0x0000000f) + 2;
+
+		if (len != 7)
+			fprintf(out, "Bad count in 3DSTATE_CLEAR_PARAMETERS\n");
+
+		instr_out(ctx, 0, "3DSTATE_CLEAR_PARAMETERS\n");
+		instr_out(ctx, 1, "prim_type=%s, clear=%s%s%s\n",
+			  data[1] & (1 << 16) ? "CLEAR_RECT" : "ZONE_INIT",
+			  data[1] & (1 << 2) ? "color," : "",
+			  data[1] & (1 << 1) ? "depth," : "",
+			  data[1] & (1 << 0) ? "stencil," : "");
+		instr_out(ctx, 2, "clear color\n");
+		instr_out(ctx, 3, "clear depth/stencil\n");
+		instr_out(ctx, 4, "color value (rgba8888)\n");
+		instr_out(ctx, 5, "depth value %f\n",
+			  int_as_float(data[5]));
+		instr_out(ctx, 6, "clear stencil\n");
+		return len;
+	}
+
+	for (idx = 0; idx < ARRAY_SIZE(opcodes_3d_1d); idx++) {
+		opcode_3d_1d = &opcodes_3d_1d[idx];
+		if (opcode_3d_1d->i830_only && !IS_GEN2(devid))
+			continue;
+
+		if (((data[0] & 0x00ff0000) >> 16) == opcode_3d_1d->opcode) {
+			len = 1;
+
+			instr_out(ctx, 0, "%s\n",
+				  opcode_3d_1d->name);
+			if (opcode_3d_1d->max_len > 1) {
+				len = (data[0] & 0x0000ffff) + 2;
+				if (len < opcode_3d_1d->min_len ||
+				    len > opcode_3d_1d->max_len) {
+					fprintf(out, "Bad count in %s\n",
+						opcode_3d_1d->name);
+				}
+			}
+
+			for (i = 1; i < len; i++) {
+				instr_out(ctx, i, "dword %d\n", i);
+			}
+
+			return len;
+		}
+	}
+
+	instr_out(ctx, 0, "3D UNKNOWN: 3d_1d opcode = 0x%x\n",
+		  opcode);
+	return 1;
+}
+
+static int
+decode_3d_primitive(struct intel_decode *ctx)
+{
+	uint32_t *data = ctx->data;
+	uint32_t count = ctx->count;
+	char immediate = (data[0] & (1 << 23)) == 0;
+	unsigned int len, i, j, ret;
+	const char *primtype;
+	int original_s2 = saved_s2;
+	int original_s4 = saved_s4;
+
+	switch ((data[0] >> 18) & 0xf) {
+	case 0x0:
+		primtype = "TRILIST";
+		break;
+	case 0x1:
+		primtype = "TRISTRIP";
+		break;
+	case 0x2:
+		primtype = "TRISTRIP_REVERSE";
+		break;
+	case 0x3:
+		primtype = "TRIFAN";
+		break;
+	case 0x4:
+		primtype = "POLYGON";
+		break;
+	case 0x5:
+		primtype = "LINELIST";
+		break;
+	case 0x6:
+		primtype = "LINESTRIP";
+		break;
+	case 0x7:
+		primtype = "RECTLIST";
+		break;
+	case 0x8:
+		primtype = "POINTLIST";
+		break;
+	case 0x9:
+		primtype = "DIB";
+		break;
+	case 0xa:
+		primtype = "CLEAR_RECT";
+		saved_s4 = 3 << 6;
+		saved_s2 = ~0;
+		break;
+	default:
+		primtype = "unknown";
+		break;
+	}
+
+	/* XXX: 3DPRIM_DIB not supported */
+	if (immediate) {
+		len = (data[0] & 0x0003ffff) + 2;
+		instr_out(ctx, 0, "3DPRIMITIVE inline %s\n",
+			  primtype);
+		if (count < len)
+			BUFFER_FAIL(count, len, "3DPRIMITIVE inline");
+		if (!saved_s2_set || !saved_s4_set) {
+			fprintf(out, "unknown vertex format\n");
+			for (i = 1; i < len; i++) {
+				instr_out(ctx, i,
+					  "           vertex data (%f float)\n",
+					  int_as_float(data[i]));
+			}
+		} else {
+			unsigned int vertex = 0;
+			for (i = 1; i < len;) {
+				unsigned int tc;
+
+#define VERTEX_OUT(fmt, ...) do {					\
+    if (i < len)							\
+	instr_out(ctx, i, " V%d."fmt"\n", vertex, __VA_ARGS__); \
+    else								\
+	fprintf(out, " missing data in V%d\n", vertex);			\
+    i++;								\
+} while (0)
+
+				VERTEX_OUT("X = %f", int_as_float(data[i]));
+				VERTEX_OUT("Y = %f", int_as_float(data[i]));
+				switch (saved_s4 >> 6 & 0x7) {
+				case 0x1:
+					VERTEX_OUT("Z = %f",
+						   int_as_float(data[i]));
+					break;
+				case 0x2:
+					VERTEX_OUT("Z = %f",
+						   int_as_float(data[i]));
+					VERTEX_OUT("W = %f",
+						   int_as_float(data[i]));
+					break;
+				case 0x3:
+					break;
+				case 0x4:
+					VERTEX_OUT("W = %f",
+						   int_as_float(data[i]));
+					break;
+				default:
+					fprintf(out, "bad S4 position mask\n");
+				}
+
+				if (saved_s4 & (1 << 10)) {
+					VERTEX_OUT
+					    ("color = (A=0x%02x, R=0x%02x, G=0x%02x, "
+					     "B=0x%02x)", data[i] >> 24,
+					     (data[i] >> 16) & 0xff,
+					     (data[i] >> 8) & 0xff,
+					     data[i] & 0xff);
+				}
+				if (saved_s4 & (1 << 11)) {
+					VERTEX_OUT
+					    ("spec = (A=0x%02x, R=0x%02x, G=0x%02x, "
+					     "B=0x%02x)", data[i] >> 24,
+					     (data[i] >> 16) & 0xff,
+					     (data[i] >> 8) & 0xff,
+					     data[i] & 0xff);
+				}
+				if (saved_s4 & (1 << 12))
+					VERTEX_OUT("width = 0x%08x)", data[i]);
+
+				for (tc = 0; tc <= 7; tc++) {
+					switch ((saved_s2 >> (tc * 4)) & 0xf) {
+					case 0x0:
+						VERTEX_OUT("T%d.X = %f", tc,
+							   int_as_float(data
+									[i]));
+						VERTEX_OUT("T%d.Y = %f", tc,
+							   int_as_float(data
+									[i]));
+						break;
+					case 0x1:
+						VERTEX_OUT("T%d.X = %f", tc,
+							   int_as_float(data
+									[i]));
+						VERTEX_OUT("T%d.Y = %f", tc,
+							   int_as_float(data
+									[i]));
+						VERTEX_OUT("T%d.Z = %f", tc,
+							   int_as_float(data
+									[i]));
+						break;
+					case 0x2:
+						VERTEX_OUT("T%d.X = %f", tc,
+							   int_as_float(data
+									[i]));
+						VERTEX_OUT("T%d.Y = %f", tc,
+							   int_as_float(data
+									[i]));
+						VERTEX_OUT("T%d.Z = %f", tc,
+							   int_as_float(data
+									[i]));
+						VERTEX_OUT("T%d.W = %f", tc,
+							   int_as_float(data
+									[i]));
+						break;
+					case 0x3:
+						VERTEX_OUT("T%d.X = %f", tc,
+							   int_as_float(data
+									[i]));
+						break;
+					case 0x4:
+						VERTEX_OUT
+						    ("T%d.XY = 0x%08x half-float",
+						     tc, data[i]);
+						break;
+					case 0x5:
+						VERTEX_OUT
+						    ("T%d.XY = 0x%08x half-float",
+						     tc, data[i]);
+						VERTEX_OUT
+						    ("T%d.ZW = 0x%08x half-float",
+						     tc, data[i]);
+						break;
+					case 0xf:
+						break;
+					default:
+						fprintf(out,
+							"bad S2.T%d format\n",
+							tc);
+					}
+				}
+				vertex++;
+			}
+		}
+
+		ret = len;
+	} else {
+		/* indirect vertices */
+		len = data[0] & 0x0000ffff;	/* index count */
+		if (data[0] & (1 << 17)) {
+			/* random vertex access */
+			if (count < (len + 1) / 2 + 1) {
+				BUFFER_FAIL(count, (len + 1) / 2 + 1,
+					    "3DPRIMITIVE random indirect");
+			}
+			instr_out(ctx, 0,
+				  "3DPRIMITIVE random indirect %s (%d)\n",
+				  primtype, len);
+			if (len == 0) {
+				/* vertex indices continue until 0xffff is
+				 * found
+				 */
+				for (i = 1; i < count; i++) {
+					if ((data[i] & 0xffff) == 0xffff) {
+						instr_out(ctx, i,
+							  "    indices: (terminator)\n");
+						ret = i;
+						goto out;
+					} else if ((data[i] >> 16) == 0xffff) {
+						instr_out(ctx, i,
+							  "    indices: 0x%04x, (terminator)\n",
+							  data[i] & 0xffff);
+						ret = i;
+						goto out;
+					} else {
+						instr_out(ctx, i,
+							  "    indices: 0x%04x, 0x%04x\n",
+							  data[i] & 0xffff,
+							  data[i] >> 16);
+					}
+				}
+				fprintf(out,
+					"3DPRIMITIVE: no terminator found in index buffer\n");
+				ret = count;
+				goto out;
+			} else {
+				/* fixed size vertex index buffer */
+				for (j = 1, i = 0; i < len; i += 2, j++) {
+					if (i * 2 == len - 1) {
+						instr_out(ctx, j,
+							  "    indices: 0x%04x\n",
+							  data[j] & 0xffff);
+					} else {
+						instr_out(ctx, j,
+							  "    indices: 0x%04x, 0x%04x\n",
+							  data[j] & 0xffff,
+							  data[j] >> 16);
+					}
+				}
+			}
+			ret = (len + 1) / 2 + 1;
+			goto out;
+		} else {
+			/* sequential vertex access */
+			instr_out(ctx, 0,
+				  "3DPRIMITIVE sequential indirect %s, %d starting from "
+				  "%d\n", primtype, len, data[1] & 0xffff);
+			instr_out(ctx, 1, "           start\n");
+			ret = 2;
+			goto out;
+		}
+	}
+
+out:
+	saved_s2 = original_s2;
+	saved_s4 = original_s4;
+	return ret;
+}
+
+static int
+decode_3d(struct intel_decode *ctx)
+{
+	uint32_t opcode;
+	unsigned int idx;
+	uint32_t *data = ctx->data;
+
+	struct {
+		uint32_t opcode;
+		unsigned int min_len;
+		unsigned int max_len;
+		const char *name;
+	} opcodes_3d[] = {
+		{ 0x06, 1, 1, "3DSTATE_ANTI_ALIASING" },
+		{ 0x08, 1, 1, "3DSTATE_BACKFACE_STENCIL_OPS" },
+		{ 0x09, 1, 1, "3DSTATE_BACKFACE_STENCIL_MASKS" },
+		{ 0x16, 1, 1, "3DSTATE_COORD_SET_BINDINGS" },
+		{ 0x15, 1, 1, "3DSTATE_FOG_COLOR" },
+		{ 0x0b, 1, 1, "3DSTATE_INDEPENDENT_ALPHA_BLEND" },
+		{ 0x0d, 1, 1, "3DSTATE_MODES_4" },
+		{ 0x0c, 1, 1, "3DSTATE_MODES_5" },
+		{ 0x07, 1, 1, "3DSTATE_RASTERIZATION_RULES"},
+	}, *opcode_3d;
+
+	opcode = (data[0] & 0x1f000000) >> 24;
+
+	switch (opcode) {
+	case 0x1f:
+		return decode_3d_primitive(ctx);
+	case 0x1d:
+		return decode_3d_1d(ctx);
+	case 0x1c:
+		return decode_3d_1c(ctx);
+	}
+
+	for (idx = 0; idx < ARRAY_SIZE(opcodes_3d); idx++) {
+		opcode_3d = &opcodes_3d[idx];
+		if (opcode == opcode_3d->opcode) {
+			unsigned int len = 1, i;
+
+			instr_out(ctx, 0, "%s\n", opcode_3d->name);
+			if (opcode_3d->max_len > 1) {
+				len = (data[0] & 0xff) + 2;
+				if (len < opcode_3d->min_len ||
+				    len > opcode_3d->max_len) {
+					fprintf(out, "Bad count in %s\n",
+						opcode_3d->name);
+				}
+			}
+
+			for (i = 1; i < len; i++) {
+				instr_out(ctx, i, "dword %d\n", i);
+			}
+			return len;
+		}
+	}
+
+	instr_out(ctx, 0, "3D UNKNOWN: 3d opcode = 0x%x\n", opcode);
+	return 1;
+}
+
+static const char *get_965_surfacetype(unsigned int surfacetype)
+{
+	switch (surfacetype) {
+	case 0:
+		return "1D";
+	case 1:
+		return "2D";
+	case 2:
+		return "3D";
+	case 3:
+		return "CUBE";
+	case 4:
+		return "BUFFER";
+	case 7:
+		return "NULL";
+	default:
+		return "unknown";
+	}
+}
+
+static const char *get_965_depthformat(unsigned int depthformat)
+{
+	switch (depthformat) {
+	case 0:
+		return "s8_z24float";
+	case 1:
+		return "z32float";
+	case 2:
+		return "z24s8";
+	case 5:
+		return "z16";
+	default:
+		return "unknown";
+	}
+}
+
+static const char *get_965_element_component(uint32_t data, int component)
+{
+	uint32_t component_control = (data >> (16 + (3 - component) * 4)) & 0x7;
+
+	switch (component_control) {
+	case 0:
+		return "nostore";
+	case 1:
+		switch (component) {
+		case 0:
+			return "X";
+		case 1:
+			return "Y";
+		case 2:
+			return "Z";
+		case 3:
+			return "W";
+		default:
+			return "fail";
+		}
+	case 2:
+		return "0.0";
+	case 3:
+		return "1.0";
+	case 4:
+		return "0x1";
+	case 5:
+		return "VID";
+	default:
+		return "fail";
+	}
+}
+
+static const char *get_965_prim_type(uint32_t primtype)
+{
+	switch (primtype) {
+	case 0x01:
+		return "point list";
+	case 0x02:
+		return "line list";
+	case 0x03:
+		return "line strip";
+	case 0x04:
+		return "tri list";
+	case 0x05:
+		return "tri strip";
+	case 0x06:
+		return "tri fan";
+	case 0x07:
+		return "quad list";
+	case 0x08:
+		return "quad strip";
+	case 0x09:
+		return "line list adj";
+	case 0x0a:
+		return "line strip adj";
+	case 0x0b:
+		return "tri list adj";
+	case 0x0c:
+		return "tri strip adj";
+	case 0x0d:
+		return "tri strip reverse";
+	case 0x0e:
+		return "polygon";
+	case 0x0f:
+		return "rect list";
+	case 0x10:
+		return "line loop";
+	case 0x11:
+		return "point list bf";
+	case 0x12:
+		return "line strip cont";
+	case 0x13:
+		return "line strip bf";
+	case 0x14:
+		return "line strip cont bf";
+	case 0x15:
+		return "tri fan no stipple";
+	default:
+		return "fail";
+	}
+}
+
+static int
+i965_decode_urb_fence(struct intel_decode *ctx, int len)
+{
+	uint32_t vs_fence, clip_fence, gs_fence, sf_fence, vfe_fence, cs_fence;
+	uint32_t *data = ctx->data;
+
+	if (len != 3)
+		fprintf(out, "Bad count in URB_FENCE\n");
+
+	vs_fence = data[1] & 0x3ff;
+	gs_fence = (data[1] >> 10) & 0x3ff;
+	clip_fence = (data[1] >> 20) & 0x3ff;
+	sf_fence = data[2] & 0x3ff;
+	vfe_fence = (data[2] >> 10) & 0x3ff;
+	cs_fence = (data[2] >> 20) & 0x7ff;
+
+	instr_out(ctx, 0, "URB_FENCE: %s%s%s%s%s%s\n",
+		  (data[0] >> 13) & 1 ? "cs " : "",
+		  (data[0] >> 12) & 1 ? "vfe " : "",
+		  (data[0] >> 11) & 1 ? "sf " : "",
+		  (data[0] >> 10) & 1 ? "clip " : "",
+		  (data[0] >> 9) & 1 ? "gs " : "",
+		  (data[0] >> 8) & 1 ? "vs " : "");
+	instr_out(ctx, 1,
+		  "vs fence: %d, clip_fence: %d, gs_fence: %d\n",
+		  vs_fence, clip_fence, gs_fence);
+	instr_out(ctx, 2,
+		  "sf fence: %d, vfe_fence: %d, cs_fence: %d\n",
+		  sf_fence, vfe_fence, cs_fence);
+	if (gs_fence < vs_fence)
+		fprintf(out, "gs fence < vs fence!\n");
+	if (clip_fence < gs_fence)
+		fprintf(out, "clip fence < gs fence!\n");
+	if (sf_fence < clip_fence)
+		fprintf(out, "sf fence < clip fence!\n");
+	if (cs_fence < sf_fence)
+		fprintf(out, "cs fence < sf fence!\n");
+
+	return len;
+}
+
+static void
+state_base_out(struct intel_decode *ctx, unsigned int index,
+	       const char *name)
+{
+	if (ctx->data[index] & 1) {
+		instr_out(ctx, index,
+			  "%s state base address 0x%08x\n", name,
+			  ctx->data[index] & ~1);
+	} else {
+		instr_out(ctx, index, "%s state base not updated\n",
+			  name);
+	}
+}
+
+static void
+state_max_out(struct intel_decode *ctx, unsigned int index,
+	      const char *name)
+{
+	if (ctx->data[index] & 1) {
+		if (ctx->data[index] == 1) {
+			instr_out(ctx, index,
+				  "%s state upper bound disabled\n", name);
+		} else {
+			instr_out(ctx, index,
+				  "%s state upper bound 0x%08x\n", name,
+				  ctx->data[index] & ~1);
+		}
+	} else {
+		instr_out(ctx, index,
+			  "%s state upper bound not updated\n", name);
+	}
+}
+
+static int
+gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(struct intel_decode *ctx)
+{
+	instr_out(ctx, 0, "3DSTATE_VIEWPORT_STATE_POINTERS_CC\n");
+	instr_out(ctx, 1, "pointer to CC viewport\n");
+
+	return 2;
+}
+
+static int
+gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(struct intel_decode *ctx)
+{
+	instr_out(ctx, 0, "3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP\n");
+	instr_out(ctx, 1, "pointer to SF_CLIP viewport\n");
+
+	return 2;
+}
+
+static int
+gen7_3DSTATE_BLEND_STATE_POINTERS(struct intel_decode *ctx)
+{
+	instr_out(ctx, 0, "3DSTATE_BLEND_STATE_POINTERS\n");
+	instr_out(ctx, 1, "pointer to BLEND_STATE at 0x%08x (%s)\n",
+		  ctx->data[1] & ~1,
+		  (ctx->data[1] & 1) ? "changed" : "unchanged");
+
+	return 2;
+}
+
+static int
+gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(struct intel_decode *ctx)
+{
+	instr_out(ctx, 0, "3DSTATE_DEPTH_STENCIL_STATE_POINTERS\n");
+	instr_out(ctx, 1,
+		  "pointer to DEPTH_STENCIL_STATE at 0x%08x (%s)\n",
+		  ctx->data[1] & ~1,
+		  (ctx->data[1] & 1) ? "changed" : "unchanged");
+
+	return 2;
+}
+
+static int
+gen7_3DSTATE_HIER_DEPTH_BUFFER(struct intel_decode *ctx)
+{
+	instr_out(ctx, 0, "3DSTATE_HIER_DEPTH_BUFFER\n");
+	instr_out(ctx, 1, "pitch %db\n",
+		  (ctx->data[1] & 0x1ffff) + 1);
+	instr_out(ctx, 2, "pointer to HiZ buffer\n");
+
+	return 3;
+}
+
+static int
+gen6_3DSTATE_CC_STATE_POINTERS(struct intel_decode *ctx)
+{
+	instr_out(ctx, 0, "3DSTATE_CC_STATE_POINTERS\n");
+	instr_out(ctx, 1, "blend change %d\n", ctx->data[1] & 1);
+	instr_out(ctx, 2, "depth stencil change %d\n",
+		  ctx->data[2] & 1);
+	instr_out(ctx, 3, "cc change %d\n", ctx->data[3] & 1);
+
+	return 4;
+}
+
+static int
+gen7_3DSTATE_CC_STATE_POINTERS(struct intel_decode *ctx)
+{
+	instr_out(ctx, 0, "3DSTATE_CC_STATE_POINTERS\n");
+	instr_out(ctx, 1, "pointer to COLOR_CALC_STATE at 0x%08x "
+		  "(%s)\n",
+		  ctx->data[1] & ~1,
+		  (ctx->data[1] & 1) ? "changed" : "unchanged");
+
+	return 2;
+}
+
+static int
+gen7_3DSTATE_URB_unit(struct intel_decode *ctx, const char *unit)
+{
+    int start_kb = ((ctx->data[1] >> 25) & 0x3f) * 8;
+    /* the field is # of 512-bit rows - 1, we print bytes */
+    int entry_size = (((ctx->data[1] >> 16) & 0x1ff) + 1);
+    int nr_entries = ctx->data[1] & 0xffff;
+
+    instr_out(ctx, 0, "3DSTATE_URB_%s\n", unit);
+    instr_out(ctx, 1,
+	      "%dKB start, size=%d 64B rows, nr_entries=%d, total size %dB\n",
+	      start_kb, entry_size, nr_entries, nr_entries * 64 * entry_size);
+
+    return 2;
+}
+
+static int
+gen7_3DSTATE_URB_VS(struct intel_decode *ctx)
+{
+	return gen7_3DSTATE_URB_unit(ctx, "VS");
+}
+
+static int
+gen7_3DSTATE_URB_HS(struct intel_decode *ctx)
+{
+	return gen7_3DSTATE_URB_unit(ctx, "HS");
+}
+
+static int
+gen7_3DSTATE_URB_DS(struct intel_decode *ctx)
+{
+	return gen7_3DSTATE_URB_unit(ctx, "DS");
+}
+
+static int
+gen7_3DSTATE_URB_GS(struct intel_decode *ctx)
+{
+	return gen7_3DSTATE_URB_unit(ctx, "GS");
+}
+
+static int
+gen7_3DSTATE_CONSTANT(struct intel_decode *ctx, const char *unit)
+{
+	int rlen[4];
+
+	rlen[0] = (ctx->data[1] >> 0) & 0xffff;
+	rlen[1] = (ctx->data[1] >> 16) & 0xffff;
+	rlen[2] = (ctx->data[2] >> 0) & 0xffff;
+	rlen[3] = (ctx->data[2] >> 16) & 0xffff;
+
+	instr_out(ctx, 0, "3DSTATE_CONSTANT_%s\n", unit);
+	instr_out(ctx, 1, "len 0 = %d, len 1 = %d\n", rlen[0], rlen[1]);
+	instr_out(ctx, 2, "len 2 = %d, len 3 = %d\n", rlen[2], rlen[3]);
+	instr_out(ctx, 3, "pointer to constbuf 0\n");
+	instr_out(ctx, 4, "pointer to constbuf 1\n");
+	instr_out(ctx, 5, "pointer to constbuf 2\n");
+	instr_out(ctx, 6, "pointer to constbuf 3\n");
+
+	return 7;
+}
+
+static int
+gen7_3DSTATE_CONSTANT_VS(struct intel_decode *ctx)
+{
+	return gen7_3DSTATE_CONSTANT(ctx, "VS");
+}
+
+static int
+gen7_3DSTATE_CONSTANT_GS(struct intel_decode *ctx)
+{
+	return gen7_3DSTATE_CONSTANT(ctx, "GS");
+}
+
+static int
+gen7_3DSTATE_CONSTANT_PS(struct intel_decode *ctx)
+{
+	return gen7_3DSTATE_CONSTANT(ctx, "PS");
+}
+
+static int
+gen7_3DSTATE_CONSTANT_DS(struct intel_decode *ctx)
+{
+	return gen7_3DSTATE_CONSTANT(ctx, "DS");
+}
+
+static int
+gen7_3DSTATE_CONSTANT_HS(struct intel_decode *ctx)
+{
+	return gen7_3DSTATE_CONSTANT(ctx, "HS");
+}
+
+
+static int
+gen6_3DSTATE_WM(struct intel_decode *ctx)
+{
+	instr_out(ctx, 0, "3DSTATE_WM\n");
+	instr_out(ctx, 1, "kernel start pointer 0\n");
+	instr_out(ctx, 2,
+		  "SPF=%d, VME=%d, Sampler Count %d, "
+		  "Binding table count %d\n",
+		  (ctx->data[2] >> 31) & 1,
+		  (ctx->data[2] >> 30) & 1,
+		  (ctx->data[2] >> 27) & 7,
+		  (ctx->data[2] >> 18) & 0xff);
+	instr_out(ctx, 3, "scratch offset\n");
+	instr_out(ctx, 4,
+		  "Depth Clear %d, Depth Resolve %d, HiZ Resolve %d, "
+		  "Dispatch GRF start[0] %d, start[1] %d, start[2] %d\n",
+		  (ctx->data[4] & (1 << 30)) != 0,
+		  (ctx->data[4] & (1 << 28)) != 0,
+		  (ctx->data[4] & (1 << 27)) != 0,
+		  (ctx->data[4] >> 16) & 0x7f,
+		  (ctx->data[4] >> 8) & 0x7f,
+		  (ctx->data[4] & 0x7f));
+	instr_out(ctx, 5,
+		  "MaxThreads %d, PS KillPixel %d, PS computed Z %d, "
+		  "PS use sourceZ %d, Thread Dispatch %d, PS use sourceW %d, "
+		  "Dispatch32 %d, Dispatch16 %d, Dispatch8 %d\n",
+		  ((ctx->data[5] >> 25) & 0x7f) + 1,
+		  (ctx->data[5] & (1 << 22)) != 0,
+		  (ctx->data[5] & (1 << 21)) != 0,
+		  (ctx->data[5] & (1 << 20)) != 0,
+		  (ctx->data[5] & (1 << 19)) != 0,
+		  (ctx->data[5] & (1 << 8)) != 0,
+		  (ctx->data[5] & (1 << 2)) != 0,
+		  (ctx->data[5] & (1 << 1)) != 0,
+		  (ctx->data[5] & (1 << 0)) != 0);
+	instr_out(ctx, 6,
+		  "Num SF output %d, Pos XY offset %d, ZW interp mode %d , "
+		  "Barycentric interp mode 0x%x, Point raster rule %d, "
+		  "Multisample mode %d, "
+		  "Multisample Dispatch mode %d\n",
+		  (ctx->data[6] >> 20) & 0x3f,
+		  (ctx->data[6] >> 18) & 3,
+		  (ctx->data[6] >> 16) & 3,
+		  (ctx->data[6] >> 10) & 0x3f,
+		  (ctx->data[6] & (1 << 9)) != 0,
+		  (ctx->data[6] >> 1) & 3,
+		  (ctx->data[6] & 1));
+	instr_out(ctx, 7, "kernel start pointer 1\n");
+	instr_out(ctx, 8, "kernel start pointer 2\n");
+
+	return 9;
+}
+
+static int
+gen7_3DSTATE_WM(struct intel_decode *ctx)
+{
+	const char *computed_depth = "";
+	const char *early_depth = "";
+	const char *zw_interp = "";
+
+	switch ((ctx->data[1] >> 23) & 0x3) {
+	case 0:
+		computed_depth = "";
+		break;
+	case 1:
+		computed_depth = "computed depth";
+		break;
+	case 2:
+		computed_depth = "computed depth >=";
+		break;
+	case 3:
+		computed_depth = "computed depth <=";
+		break;
+	}
+
+	switch ((ctx->data[1] >> 21) & 0x3) {
+	case 0:
+		early_depth = "";
+		break;
+	case 1:
+		early_depth = ", EDSC_PSEXEC";
+		break;
+	case 2:
+		early_depth = ", EDSC_PREPS";
+		break;
+	case 3:
+		early_depth = ", BAD EDSC";
+		break;
+	}
+
+	switch ((ctx->data[1] >> 17) & 0x3) {
+	case 0:
+		early_depth = "";
+		break;
+	case 1:
+		early_depth = ", BAD ZW interp";
+		break;
+	case 2:
+		early_depth = ", ZW centroid";
+		break;
+	case 3:
+		early_depth = ", ZW sample";
+		break;
+	}
+
+	instr_out(ctx, 0, "3DSTATE_WM\n");
+	instr_out(ctx, 1, "(%s%s%s%s%s%s)%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+		  (ctx->data[1] & (1 << 11)) ? "PP " : "",
+		  (ctx->data[1] & (1 << 12)) ? "PC " : "",
+		  (ctx->data[1] & (1 << 13)) ? "PS " : "",
+		  (ctx->data[1] & (1 << 14)) ? "NPP " : "",
+		  (ctx->data[1] & (1 << 15)) ? "NPC " : "",
+		  (ctx->data[1] & (1 << 16)) ? "NPS " : "",
+		  (ctx->data[1] & (1 << 30)) ? ", depth clear" : "",
+		  (ctx->data[1] & (1 << 29)) ? "" : ", disabled",
+		  (ctx->data[1] & (1 << 28)) ? ", depth resolve" : "",
+		  (ctx->data[1] & (1 << 27)) ? ", hiz resolve" : "",
+		  (ctx->data[1] & (1 << 25)) ? ", kill" : "",
+		  computed_depth,
+		  early_depth,
+		  zw_interp,
+		  (ctx->data[1] & (1 << 20)) ? ", source depth" : "",
+		  (ctx->data[1] & (1 << 19)) ? ", source W" : "",
+		  (ctx->data[1] & (1 << 10)) ? ", coverage" : "",
+		  (ctx->data[1] & (1 << 4)) ? ", poly stipple" : "",
+		  (ctx->data[1] & (1 << 3)) ? ", line stipple" : "",
+		  (ctx->data[1] & (1 << 2)) ? ", point UL" : ", point UR"
+		  );
+	instr_out(ctx, 2, "MS\n");
+
+	return 3;
+}
+
+static int
+gen4_3DPRIMITIVE(struct intel_decode *ctx)
+{
+	instr_out(ctx, 0,
+		  "3DPRIMITIVE: %s %s\n",
+		  get_965_prim_type((ctx->data[0] >> 10) & 0x1f),
+		  (ctx->data[0] & (1 << 15)) ? "random" : "sequential");
+	instr_out(ctx, 1, "vertex count\n");
+	instr_out(ctx, 2, "start vertex\n");
+	instr_out(ctx, 3, "instance count\n");
+	instr_out(ctx, 4, "start instance\n");
+	instr_out(ctx, 5, "index bias\n");
+
+	return 6;
+}
+
+static int
+gen7_3DPRIMITIVE(struct intel_decode *ctx)
+{
+	bool indirect = !!(ctx->data[0] & (1 << 10));
+
+	instr_out(ctx, 0,
+		  "3DPRIMITIVE: %s%s\n",
+		  indirect ? " indirect" : "",
+		  (ctx->data[0] & (1 << 8)) ? " predicated" : "");
+	instr_out(ctx, 1, "%s %s\n",
+		  get_965_prim_type(ctx->data[1] & 0x3f),
+		  (ctx->data[1] & (1 << 8)) ? "random" : "sequential");
+	instr_out(ctx, 2, indirect ? "ignored" : "vertex count\n");
+	instr_out(ctx, 3, indirect ? "ignored" : "start vertex\n");
+	instr_out(ctx, 4, indirect ? "ignored" : "instance count\n");
+	instr_out(ctx, 5, indirect ? "ignored" : "start instance\n");
+	instr_out(ctx, 6, indirect ? "ignored" : "index bias\n");
+
+	return 7;
+}
+
+static int
+decode_3d_965(struct intel_decode *ctx)
+{
+	uint32_t opcode;
+	unsigned int len;
+	unsigned int i, j, sba_len;
+	const char *desc1 = NULL;
+	uint32_t *data = ctx->data;
+	uint32_t devid = ctx->devid;
+
+	struct {
+		uint32_t opcode;
+		uint32_t len_mask;
+		int unsigned min_len;
+		int unsigned max_len;
+		const char *name;
+		int gen;
+		int (*func)(struct intel_decode *ctx);
+	} opcodes_3d[] = {
+		{ 0x6000, 0x00ff, 3, 3, "URB_FENCE" },
+		{ 0x6001, 0xffff, 2, 2, "CS_URB_STATE" },
+		{ 0x6002, 0x00ff, 2, 2, "CONSTANT_BUFFER" },
+		{ 0x6101, 0xffff, 6, 10, "STATE_BASE_ADDRESS" },
+		{ 0x6102, 0xffff, 2, 2, "STATE_SIP" },
+		{ 0x6104, 0xffff, 1, 1, "3DSTATE_PIPELINE_SELECT" },
+		{ 0x680b, 0xffff, 1, 1, "3DSTATE_VF_STATISTICS" },
+		{ 0x6904, 0xffff, 1, 1, "3DSTATE_PIPELINE_SELECT" },
+		{ 0x7800, 0xffff, 7, 7, "3DSTATE_PIPELINED_POINTERS" },
+		{ 0x7801, 0x00ff, 4, 6, "3DSTATE_BINDING_TABLE_POINTERS" },
+		{ 0x7802, 0x00ff, 4, 4, "3DSTATE_SAMPLER_STATE_POINTERS" },
+		{ 0x7805, 0x00ff, 7, 7, "3DSTATE_DEPTH_BUFFER", 7 },
+		{ 0x7805, 0x00ff, 3, 3, "3DSTATE_URB" },
+		{ 0x7804, 0x00ff, 3, 3, "3DSTATE_CLEAR_PARAMS" },
+		{ 0x7806, 0x00ff, 3, 3, "3DSTATE_STENCIL_BUFFER" },
+		{ 0x790f, 0x00ff, 3, 3, "3DSTATE_HIER_DEPTH_BUFFER", 6 },
+		{ 0x7807, 0x00ff, 3, 3, "3DSTATE_HIER_DEPTH_BUFFER", 7, gen7_3DSTATE_HIER_DEPTH_BUFFER },
+		{ 0x7808, 0x00ff, 5, 257, "3DSTATE_VERTEX_BUFFERS" },
+		{ 0x7809, 0x00ff, 3, 256, "3DSTATE_VERTEX_ELEMENTS" },
+		{ 0x780a, 0x00ff, 3, 3, "3DSTATE_INDEX_BUFFER" },
+		{ 0x780b, 0xffff, 1, 1, "3DSTATE_VF_STATISTICS" },
+		{ 0x780d, 0x00ff, 4, 4, "3DSTATE_VIEWPORT_STATE_POINTERS" },
+		{ 0x780e, 0xffff, 4, 4, NULL, 6, gen6_3DSTATE_CC_STATE_POINTERS },
+		{ 0x780e, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_CC_STATE_POINTERS },
+		{ 0x780f, 0x00ff, 2, 2, "3DSTATE_SCISSOR_POINTERS" },
+		{ 0x7810, 0x00ff, 6, 6, "3DSTATE_VS" },
+		{ 0x7811, 0x00ff, 7, 7, "3DSTATE_GS" },
+		{ 0x7812, 0x00ff, 4, 4, "3DSTATE_CLIP" },
+		{ 0x7813, 0x00ff, 20, 20, "3DSTATE_SF", 6 },
+		{ 0x7813, 0x00ff, 7, 7, "3DSTATE_SF", 7 },
+		{ 0x7814, 0x00ff, 3, 3, "3DSTATE_WM", 7, gen7_3DSTATE_WM },
+		{ 0x7814, 0x00ff, 9, 9, "3DSTATE_WM", 6, gen6_3DSTATE_WM },
+		{ 0x7815, 0x00ff, 5, 5, "3DSTATE_CONSTANT_VS_STATE", 6 },
+		{ 0x7815, 0x00ff, 7, 7, "3DSTATE_CONSTANT_VS", 7, gen7_3DSTATE_CONSTANT_VS },
+		{ 0x7816, 0x00ff, 5, 5, "3DSTATE_CONSTANT_GS_STATE", 6 },
+		{ 0x7816, 0x00ff, 7, 7, "3DSTATE_CONSTANT_GS", 7, gen7_3DSTATE_CONSTANT_GS },
+		{ 0x7817, 0x00ff, 5, 5, "3DSTATE_CONSTANT_PS_STATE", 6 },
+		{ 0x7817, 0x00ff, 7, 7, "3DSTATE_CONSTANT_PS", 7, gen7_3DSTATE_CONSTANT_PS },
+		{ 0x7818, 0xffff, 2, 2, "3DSTATE_SAMPLE_MASK" },
+		{ 0x7819, 0x00ff, 7, 7, "3DSTATE_CONSTANT_HS", 7, gen7_3DSTATE_CONSTANT_HS },
+		{ 0x781a, 0x00ff, 7, 7, "3DSTATE_CONSTANT_DS", 7, gen7_3DSTATE_CONSTANT_DS },
+		{ 0x781b, 0x00ff, 7, 7, "3DSTATE_HS" },
+		{ 0x781c, 0x00ff, 4, 4, "3DSTATE_TE" },
+		{ 0x781d, 0x00ff, 6, 6, "3DSTATE_DS" },
+		{ 0x781e, 0x00ff, 3, 3, "3DSTATE_STREAMOUT" },
+		{ 0x781f, 0x00ff, 14, 14, "3DSTATE_SBE" },
+		{ 0x7820, 0x00ff, 8, 8, "3DSTATE_PS" },
+		{ 0x7821, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP },
+		{ 0x7823, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC },
+		{ 0x7824, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_BLEND_STATE_POINTERS },
+		{ 0x7825, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS },
+		{ 0x7826, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_VS" },
+		{ 0x7827, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_HS" },
+		{ 0x7828, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_DS" },
+		{ 0x7829, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_GS" },
+		{ 0x782a, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_PS" },
+		{ 0x782b, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_VS" },
+		{ 0x782c, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_HS" },
+		{ 0x782d, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_DS" },
+		{ 0x782e, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_GS" },
+		{ 0x782f, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_PS" },
+		{ 0x7830, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_VS },
+		{ 0x7831, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_HS },
+		{ 0x7832, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_DS },
+		{ 0x7833, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_GS },
+		{ 0x7900, 0xffff, 4, 4, "3DSTATE_DRAWING_RECTANGLE" },
+		{ 0x7901, 0xffff, 5, 5, "3DSTATE_CONSTANT_COLOR" },
+		{ 0x7905, 0xffff, 5, 7, "3DSTATE_DEPTH_BUFFER" },
+		{ 0x7906, 0xffff, 2, 2, "3DSTATE_POLY_STIPPLE_OFFSET" },
+		{ 0x7907, 0xffff, 33, 33, "3DSTATE_POLY_STIPPLE_PATTERN" },
+		{ 0x7908, 0xffff, 3, 3, "3DSTATE_LINE_STIPPLE" },
+		{ 0x7909, 0xffff, 2, 2, "3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP" },
+		{ 0x7909, 0xffff, 2, 2, "3DSTATE_CLEAR_PARAMS" },
+		{ 0x790a, 0xffff, 3, 3, "3DSTATE_AA_LINE_PARAMETERS" },
+		{ 0x790b, 0xffff, 4, 4, "3DSTATE_GS_SVB_INDEX" },
+		{ 0x790d, 0xffff, 3, 3, "3DSTATE_MULTISAMPLE", 6 },
+		{ 0x790d, 0xffff, 4, 4, "3DSTATE_MULTISAMPLE", 7 },
+		{ 0x7910, 0x00ff, 2, 2, "3DSTATE_CLEAR_PARAMS" },
+		{ 0x7912, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_VS" },
+		{ 0x7913, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_HS" },
+		{ 0x7914, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_DS" },
+		{ 0x7915, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_GS" },
+		{ 0x7916, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_PS" },
+		{ 0x7917, 0x00ff, 2, 2+128*2, "3DSTATE_SO_DECL_LIST" },
+		{ 0x7918, 0x00ff, 4, 4, "3DSTATE_SO_BUFFER" },
+		{ 0x7a00, 0x00ff, 4, 6, "PIPE_CONTROL" },
+		{ 0x7b00, 0x00ff, 7, 7, NULL, 7, gen7_3DPRIMITIVE },
+		{ 0x7b00, 0x00ff, 6, 6, NULL, 0, gen4_3DPRIMITIVE },
+	}, *opcode_3d = NULL;
+
+	opcode = (data[0] & 0xffff0000) >> 16;
+
+	for (i = 0; i < ARRAY_SIZE(opcodes_3d); i++) {
+		if (opcode != opcodes_3d[i].opcode)
+			continue;
+
+		/* If it's marked as not our gen, skip. */
+		if (opcodes_3d[i].gen && opcodes_3d[i].gen != ctx->gen)
+			continue;
+
+		opcode_3d = &opcodes_3d[i];
+		break;
+	}
+
+	if (opcode_3d) {
+		if (opcode_3d->max_len == 1)
+			len = 1;
+		else
+			len = (data[0] & opcode_3d->len_mask) + 2;
+
+		if (len < opcode_3d->min_len ||
+		    len > opcode_3d->max_len) {
+			fprintf(out, "Bad length %d in %s, expected %d-%d\n",
+				len, opcode_3d->name,
+				opcode_3d->min_len, opcode_3d->max_len);
+		}
+	} else {
+		len = (data[0] & 0x0000ffff) + 2;
+	}
+
+	switch (opcode) {
+	case 0x6000:
+		return i965_decode_urb_fence(ctx, len);
+	case 0x6001:
+		instr_out(ctx, 0, "CS_URB_STATE\n");
+		instr_out(ctx, 1,
+			  "entry_size: %d [%d bytes], n_entries: %d\n",
+			  (data[1] >> 4) & 0x1f,
+			  (((data[1] >> 4) & 0x1f) + 1) * 64, data[1] & 0x7);
+		return len;
+	case 0x6002:
+		instr_out(ctx, 0, "CONSTANT_BUFFER: %s\n",
+			  (data[0] >> 8) & 1 ? "valid" : "invalid");
+		instr_out(ctx, 1,
+			  "offset: 0x%08x, length: %d bytes\n", data[1] & ~0x3f,
+			  ((data[1] & 0x3f) + 1) * 64);
+		return len;
+	case 0x6101:
+		i = 0;
+		instr_out(ctx, 0, "STATE_BASE_ADDRESS\n");
+		i++;
+
+		if (IS_GEN6(devid) || IS_GEN7(devid))
+			sba_len = 10;
+		else if (IS_GEN5(devid))
+			sba_len = 8;
+		else
+			sba_len = 6;
+		if (len != sba_len)
+			fprintf(out, "Bad count in STATE_BASE_ADDRESS\n");
+
+		state_base_out(ctx, i++, "general");
+		state_base_out(ctx, i++, "surface");
+		if (IS_GEN6(devid) || IS_GEN7(devid))
+			state_base_out(ctx, i++, "dynamic");
+		state_base_out(ctx, i++, "indirect");
+		if (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid))
+			state_base_out(ctx, i++, "instruction");
+
+		state_max_out(ctx, i++, "general");
+		if (IS_GEN6(devid) || IS_GEN7(devid))
+			state_max_out(ctx, i++, "dynamic");
+		state_max_out(ctx, i++, "indirect");
+		if (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid))
+			state_max_out(ctx, i++, "instruction");
+
+		return len;
+	case 0x7800:
+		instr_out(ctx, 0, "3DSTATE_PIPELINED_POINTERS\n");
+		instr_out(ctx, 1, "VS state\n");
+		instr_out(ctx, 2, "GS state\n");
+		instr_out(ctx, 3, "Clip state\n");
+		instr_out(ctx, 4, "SF state\n");
+		instr_out(ctx, 5, "WM state\n");
+		instr_out(ctx, 6, "CC state\n");
+		return len;
+	case 0x7801:
+		if (len != 6 && len != 4)
+			fprintf(out,
+				"Bad count in 3DSTATE_BINDING_TABLE_POINTERS\n");
+		if (len == 6) {
+			instr_out(ctx, 0,
+				  "3DSTATE_BINDING_TABLE_POINTERS\n");
+			instr_out(ctx, 1, "VS binding table\n");
+			instr_out(ctx, 2, "GS binding table\n");
+			instr_out(ctx, 3, "Clip binding table\n");
+			instr_out(ctx, 4, "SF binding table\n");
+			instr_out(ctx, 5, "WM binding table\n");
+		} else {
+			instr_out(ctx, 0,
+				  "3DSTATE_BINDING_TABLE_POINTERS: VS mod %d, "
+				  "GS mod %d, PS mod %d\n",
+				  (data[0] & (1 << 8)) != 0,
+				  (data[0] & (1 << 9)) != 0,
+				  (data[0] & (1 << 12)) != 0);
+			instr_out(ctx, 1, "VS binding table\n");
+			instr_out(ctx, 2, "GS binding table\n");
+			instr_out(ctx, 3, "WM binding table\n");
+		}
+
+		return len;
+	case 0x7802:
+		instr_out(ctx, 0,
+			  "3DSTATE_SAMPLER_STATE_POINTERS: VS mod %d, "
+			  "GS mod %d, PS mod %d\n", (data[0] & (1 << 8)) != 0,
+			  (data[0] & (1 << 9)) != 0,
+			  (data[0] & (1 << 12)) != 0);
+		instr_out(ctx, 1, "VS sampler state\n");
+		instr_out(ctx, 2, "GS sampler state\n");
+		instr_out(ctx, 3, "WM sampler state\n");
+		return len;
+	case 0x7805:
+		/* Actually 3DSTATE_DEPTH_BUFFER on gen7. */
+		if (ctx->gen == 7)
+			break;
+
+		instr_out(ctx, 0, "3DSTATE_URB\n");
+		instr_out(ctx, 1,
+			  "VS entries %d, alloc size %d (1024bit row)\n",
+			  data[1] & 0xffff, ((data[1] >> 16) & 0x07f) + 1);
+		instr_out(ctx, 2,
+			  "GS entries %d, alloc size %d (1024bit row)\n",
+			  (data[2] >> 8) & 0x3ff, (data[2] & 7) + 1);
+		return len;
+
+	case 0x7808:
+		if ((len - 1) % 4 != 0)
+			fprintf(out, "Bad count in 3DSTATE_VERTEX_BUFFERS\n");
+		instr_out(ctx, 0, "3DSTATE_VERTEX_BUFFERS\n");
+
+		for (i = 1; i < len;) {
+			int idx, access;
+			if (IS_GEN6(devid)) {
+				idx = 26;
+				access = 20;
+			} else {
+				idx = 27;
+				access = 26;
+			}
+			instr_out(ctx, i,
+				  "buffer %d: %s, pitch %db\n", data[i] >> idx,
+				  data[i] & (1 << access) ? "random" :
+				  "sequential", data[i] & 0x07ff);
+			i++;
+			instr_out(ctx, i++, "buffer address\n");
+			instr_out(ctx, i++, "max index\n");
+			instr_out(ctx, i++, "mbz\n");
+		}
+		return len;
+
+	case 0x7809:
+		if ((len + 1) % 2 != 0)
+			fprintf(out, "Bad count in 3DSTATE_VERTEX_ELEMENTS\n");
+		instr_out(ctx, 0, "3DSTATE_VERTEX_ELEMENTS\n");
+
+		for (i = 1; i < len;) {
+			instr_out(ctx, i,
+				  "buffer %d: %svalid, type 0x%04x, "
+				  "src offset 0x%04x bytes\n",
+				  data[i] >> ((IS_GEN6(devid) || IS_GEN7(devid)) ? 26 : 27),
+				  data[i] & (1 << ((IS_GEN6(devid) || IS_GEN7(devid)) ? 25 : 26)) ?
+				  "" : "in", (data[i] >> 16) & 0x1ff,
+				  data[i] & 0x07ff);
+			i++;
+			instr_out(ctx, i, "(%s, %s, %s, %s), "
+				  "dst offset 0x%02x bytes\n",
+				  get_965_element_component(data[i], 0),
+				  get_965_element_component(data[i], 1),
+				  get_965_element_component(data[i], 2),
+				  get_965_element_component(data[i], 3),
+				  (data[i] & 0xff) * 4);
+			i++;
+		}
+		return len;
+
+	case 0x780d:
+		instr_out(ctx, 0,
+			  "3DSTATE_VIEWPORT_STATE_POINTERS\n");
+		instr_out(ctx, 1, "clip\n");
+		instr_out(ctx, 2, "sf\n");
+		instr_out(ctx, 3, "cc\n");
+		return len;
+
+	case 0x780a:
+		instr_out(ctx, 0, "3DSTATE_INDEX_BUFFER\n");
+		instr_out(ctx, 1, "beginning buffer address\n");
+		instr_out(ctx, 2, "ending buffer address\n");
+		return len;
+
+	case 0x780f:
+		instr_out(ctx, 0, "3DSTATE_SCISSOR_POINTERS\n");
+		instr_out(ctx, 1, "scissor rect offset\n");
+		return len;
+
+	case 0x7810:
+		instr_out(ctx, 0, "3DSTATE_VS\n");
+		instr_out(ctx, 1, "kernel pointer\n");
+		instr_out(ctx, 2,
+			  "SPF=%d, VME=%d, Sampler Count %d, "
+			  "Binding table count %d\n", (data[2] >> 31) & 1,
+			  (data[2] >> 30) & 1, (data[2] >> 27) & 7,
+			  (data[2] >> 18) & 0xff);
+		instr_out(ctx, 3, "scratch offset\n");
+		instr_out(ctx, 4,
+			  "Dispatch GRF start %d, VUE read length %d, "
+			  "VUE read offset %d\n", (data[4] >> 20) & 0x1f,
+			  (data[4] >> 11) & 0x3f, (data[4] >> 4) & 0x3f);
+		instr_out(ctx, 5,
+			  "Max Threads %d, Vertex Cache %sable, "
+			  "VS func %sable\n", ((data[5] >> 25) & 0x7f) + 1,
+			  (data[5] & (1 << 1)) != 0 ? "dis" : "en",
+			  (data[5] & 1) != 0 ? "en" : "dis");
+		return len;
+
+	case 0x7811:
+		instr_out(ctx, 0, "3DSTATE_GS\n");
+		instr_out(ctx, 1, "kernel pointer\n");
+		instr_out(ctx, 2,
+			  "SPF=%d, VME=%d, Sampler Count %d, "
+			  "Binding table count %d\n", (data[2] >> 31) & 1,
+			  (data[2] >> 30) & 1, (data[2] >> 27) & 7,
+			  (data[2] >> 18) & 0xff);
+		instr_out(ctx, 3, "scratch offset\n");
+		instr_out(ctx, 4,
+			  "Dispatch GRF start %d, VUE read length %d, "
+			  "VUE read offset %d\n", (data[4] & 0xf),
+			  (data[4] >> 11) & 0x3f, (data[4] >> 4) & 0x3f);
+		instr_out(ctx, 5,
+			  "Max Threads %d, Rendering %sable\n",
+			  ((data[5] >> 25) & 0x7f) + 1,
+			  (data[5] & (1 << 8)) != 0 ? "en" : "dis");
+		instr_out(ctx, 6,
+			  "Reorder %sable, Discard Adjaceny %sable, "
+			  "GS %sable\n",
+			  (data[6] & (1 << 30)) != 0 ? "en" : "dis",
+			  (data[6] & (1 << 29)) != 0 ? "en" : "dis",
+			  (data[6] & (1 << 15)) != 0 ? "en" : "dis");
+		return len;
+
+	case 0x7812:
+		instr_out(ctx, 0, "3DSTATE_CLIP\n");
+		instr_out(ctx, 1,
+			  "UserClip distance cull test mask 0x%x\n",
+			  data[1] & 0xff);
+		instr_out(ctx, 2,
+			  "Clip %sable, API mode %s, Viewport XY test %sable, "
+			  "Viewport Z test %sable, Guardband test %sable, Clip mode %d, "
+			  "Perspective Divide %sable, Non-Perspective Barycentric %sable, "
+			  "Tri Provoking %d, Line Provoking %d, Trifan Provoking %d\n",
+			  (data[2] & (1 << 31)) != 0 ? "en" : "dis",
+			  (data[2] & (1 << 30)) != 0 ? "D3D" : "OGL",
+			  (data[2] & (1 << 28)) != 0 ? "en" : "dis",
+			  (data[2] & (1 << 27)) != 0 ? "en" : "dis",
+			  (data[2] & (1 << 26)) != 0 ? "en" : "dis",
+			  (data[2] >> 13) & 7,
+			  (data[2] & (1 << 9)) != 0 ? "dis" : "en",
+			  (data[2] & (1 << 8)) != 0 ? "en" : "dis",
+			  (data[2] >> 4) & 3, (data[2] >> 2) & 3,
+			  (data[2] & 3));
+		instr_out(ctx, 3,
+			  "Min PointWidth %d, Max PointWidth %d, "
+			  "Force Zero RTAIndex %sable, Max VPIndex %d\n",
+			  (data[3] >> 17) & 0x7ff, (data[3] >> 6) & 0x7ff,
+			  (data[3] & (1 << 5)) != 0 ? "en" : "dis",
+			  (data[3] & 0xf));
+		return len;
+
+	case 0x7813:
+		if (ctx->gen == 7)
+			break;
+
+		instr_out(ctx, 0, "3DSTATE_SF\n");
+		instr_out(ctx, 1,
+			  "Attrib Out %d, Attrib Swizzle %sable, VUE read length %d, "
+			  "VUE read offset %d\n", (data[1] >> 22) & 0x3f,
+			  (data[1] & (1 << 21)) != 0 ? "en" : "dis",
+			  (data[1] >> 11) & 0x1f, (data[1] >> 4) & 0x3f);
+		instr_out(ctx, 2,
+			  "Legacy Global DepthBias %sable, FrontFace fill %d, BF fill %d, "
+			  "VP transform %sable, FrontWinding_%s\n",
+			  (data[2] & (1 << 11)) != 0 ? "en" : "dis",
+			  (data[2] >> 5) & 3, (data[2] >> 3) & 3,
+			  (data[2] & (1 << 1)) != 0 ? "en" : "dis",
+			  (data[2] & 1) != 0 ? "CCW" : "CW");
+		instr_out(ctx, 3,
+			  "AA %sable, CullMode %d, Scissor %sable, Multisample m ode %d\n",
+			  (data[3] & (1 << 31)) != 0 ? "en" : "dis",
+			  (data[3] >> 29) & 3,
+			  (data[3] & (1 << 11)) != 0 ? "en" : "dis",
+			  (data[3] >> 8) & 3);
+		instr_out(ctx, 4,
+			  "Last Pixel %sable, SubPixel Precision %d, Use PixelWidth %d\n",
+			  (data[4] & (1 << 31)) != 0 ? "en" : "dis",
+			  (data[4] & (1 << 12)) != 0 ? 4 : 8,
+			  (data[4] & (1 << 11)) != 0);
+		instr_out(ctx, 5,
+			  "Global Depth Offset Constant %f\n",
+			  *(float *)(&data[5]));
+		instr_out(ctx, 6, "Global Depth Offset Scale %f\n",
+			  *(float *)(&data[6]));
+		instr_out(ctx, 7, "Global Depth Offset Clamp %f\n",
+			  *(float *)(&data[7]));
+
+		for (i = 0, j = 0; i < 8; i++, j += 2)
+			instr_out(ctx, i + 8,
+				  "Attrib %d (Override %s%s%s%s, Const Source %d, Swizzle Select %d, "
+				  "Source %d); Attrib %d (Override %s%s%s%s, Const Source %d, Swizzle Select %d, Source %d)\n",
+				  j + 1,
+				  (data[8 + i] & (1 << 31)) != 0 ? "W" : "",
+				  (data[8 + i] & (1 << 30)) != 0 ? "Z" : "",
+				  (data[8 + i] & (1 << 29)) != 0 ? "Y" : "",
+				  (data[8 + i] & (1 << 28)) != 0 ? "X" : "",
+				  (data[8 + i] >> 25) & 3,
+				  (data[8 + i] >> 22) & 3,
+				  (data[8 + i] >> 16) & 0x1f, j,
+				  (data[8 + i] & (1 << 15)) != 0 ? "W" : "",
+				  (data[8 + i] & (1 << 14)) != 0 ? "Z" : "",
+				  (data[8 + i] & (1 << 13)) != 0 ? "Y" : "",
+				  (data[8 + i] & (1 << 12)) != 0 ? "X" : "",
+				  (data[8 + i] >> 9) & 3,
+				  (data[8 + i] >> 6) & 3, (data[8 + i] & 0x1f));
+		instr_out(ctx, 16,
+			  "Point Sprite TexCoord Enable\n");
+		instr_out(ctx, 17, "Const Interp Enable\n");
+		instr_out(ctx, 18,
+			  "Attrib 7-0 WrapShortest Enable\n");
+		instr_out(ctx, 19,
+			  "Attrib 15-8 WrapShortest Enable\n");
+
+		return len;
+
+	case 0x7900:
+		instr_out(ctx, 0, "3DSTATE_DRAWING_RECTANGLE\n");
+		instr_out(ctx, 1, "top left: %d,%d\n",
+			  data[1] & 0xffff, (data[1] >> 16) & 0xffff);
+		instr_out(ctx, 2, "bottom right: %d,%d\n",
+			  data[2] & 0xffff, (data[2] >> 16) & 0xffff);
+		instr_out(ctx, 3, "origin: %d,%d\n",
+			  (int)data[3] & 0xffff, ((int)data[3] >> 16) & 0xffff);
+
+		return len;
+
+	case 0x7905:
+		instr_out(ctx, 0, "3DSTATE_DEPTH_BUFFER\n");
+		if (IS_GEN5(devid) || IS_GEN6(devid))
+			instr_out(ctx, 1,
+				  "%s, %s, pitch = %d bytes, %stiled, HiZ %d, Separate Stencil %d\n",
+				  get_965_surfacetype(data[1] >> 29),
+				  get_965_depthformat((data[1] >> 18) & 0x7),
+				  (data[1] & 0x0001ffff) + 1,
+				  data[1] & (1 << 27) ? "" : "not ",
+				  (data[1] & (1 << 22)) != 0,
+				  (data[1] & (1 << 21)) != 0);
+		else
+			instr_out(ctx, 1,
+				  "%s, %s, pitch = %d bytes, %stiled\n",
+				  get_965_surfacetype(data[1] >> 29),
+				  get_965_depthformat((data[1] >> 18) & 0x7),
+				  (data[1] & 0x0001ffff) + 1,
+				  data[1] & (1 << 27) ? "" : "not ");
+		instr_out(ctx, 2, "depth offset\n");
+		instr_out(ctx, 3, "%dx%d\n",
+			  ((data[3] & 0x0007ffc0) >> 6) + 1,
+			  ((data[3] & 0xfff80000) >> 19) + 1);
+		instr_out(ctx, 4, "volume depth\n");
+		if (len >= 6)
+			instr_out(ctx, 5, "\n");
+		if (len >= 7) {
+			if (IS_GEN6(devid))
+				instr_out(ctx, 6, "\n");
+			else
+				instr_out(ctx, 6,
+					  "render target view extent\n");
+		}
+
+		return len;
+
+	case 0x7a00:
+		if (IS_GEN6(devid) || IS_GEN7(devid)) {
+			if (len != 4 && len != 5)
+				fprintf(out, "Bad count in PIPE_CONTROL\n");
+
+			switch ((data[1] >> 14) & 0x3) {
+			case 0:
+				desc1 = "no write";
+				break;
+			case 1:
+				desc1 = "qword write";
+				break;
+			case 2:
+				desc1 = "PS_DEPTH_COUNT write";
+				break;
+			case 3:
+				desc1 = "TIMESTAMP write";
+				break;
+			}
+			instr_out(ctx, 0, "PIPE_CONTROL\n");
+			instr_out(ctx, 1,
+				  "%s, %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+				  desc1,
+				  data[1] & (1 << 20) ? "cs stall, " : "",
+				  data[1] & (1 << 19) ?
+				  "global snapshot count reset, " : "",
+				  data[1] & (1 << 18) ? "tlb invalidate, " : "",
+				  data[1] & (1 << 17) ? "gfdt flush, " : "",
+				  data[1] & (1 << 17) ? "media state clear, " :
+				  "",
+				  data[1] & (1 << 13) ? "depth stall, " : "",
+				  data[1] & (1 << 12) ?
+				  "render target cache flush, " : "",
+				  data[1] & (1 << 11) ?
+				  "instruction cache invalidate, " : "",
+				  data[1] & (1 << 10) ?
+				  "texture cache invalidate, " : "",
+				  data[1] & (1 << 9) ?
+				  "indirect state invalidate, " : "",
+				  data[1] & (1 << 8) ? "notify irq, " : "",
+				  data[1] & (1 << 7) ? "PIPE_CONTROL flush, " :
+				  "",
+				  data[1] & (1 << 6) ? "protect mem app_id, " :
+				  "", data[1] & (1 << 5) ? "DC flush, " : "",
+				  data[1] & (1 << 4) ? "vf fetch invalidate, " :
+				  "",
+				  data[1] & (1 << 3) ?
+				  "constant cache invalidate, " : "",
+				  data[1] & (1 << 2) ?
+				  "state cache invalidate, " : "",
+				  data[1] & (1 << 1) ? "stall at scoreboard, " :
+				  "",
+				  data[1] & (1 << 0) ? "depth cache flush, " :
+				  "");
+			if (len == 5) {
+				instr_out(ctx, 2,
+					  "destination address\n");
+				instr_out(ctx, 3,
+					  "immediate dword low\n");
+				instr_out(ctx, 4,
+					  "immediate dword high\n");
+			} else {
+				for (i = 2; i < len; i++) {
+					instr_out(ctx, i, "\n");
+				}
+			}
+			return len;
+		} else {
+			if (len != 4)
+				fprintf(out, "Bad count in PIPE_CONTROL\n");
+
+			switch ((data[0] >> 14) & 0x3) {
+			case 0:
+				desc1 = "no write";
+				break;
+			case 1:
+				desc1 = "qword write";
+				break;
+			case 2:
+				desc1 = "PS_DEPTH_COUNT write";
+				break;
+			case 3:
+				desc1 = "TIMESTAMP write";
+				break;
+			}
+			instr_out(ctx, 0,
+				  "PIPE_CONTROL: %s, %sdepth stall, %sRC write flush, "
+				  "%sinst flush\n",
+				  desc1,
+				  data[0] & (1 << 13) ? "" : "no ",
+				  data[0] & (1 << 12) ? "" : "no ",
+				  data[0] & (1 << 11) ? "" : "no ");
+			instr_out(ctx, 1, "destination address\n");
+			instr_out(ctx, 2, "immediate dword low\n");
+			instr_out(ctx, 3, "immediate dword high\n");
+			return len;
+		}
+	}
+
+	if (opcode_3d) {
+		if (opcode_3d->func) {
+			return opcode_3d->func(ctx);
+		} else {
+			instr_out(ctx, 0, "%s\n", opcode_3d->name);
+
+			for (i = 1; i < len; i++) {
+				instr_out(ctx, i, "dword %d\n", i);
+			}
+			return len;
+		}
+	}
+
+	instr_out(ctx, 0, "3D UNKNOWN: 3d_965 opcode = 0x%x\n",
+		  opcode);
+	return 1;
+}
+
+static int
+decode_3d_i830(struct intel_decode *ctx)
+{
+	unsigned int idx;
+	uint32_t opcode;
+	uint32_t *data = ctx->data;
+
+	struct {
+		uint32_t opcode;
+		unsigned int min_len;
+		unsigned int max_len;
+		const char *name;
+	} opcodes_3d[] = {
+		{ 0x02, 1, 1, "3DSTATE_MODES_3" },
+		{ 0x03, 1, 1, "3DSTATE_ENABLES_1" },
+		{ 0x04, 1, 1, "3DSTATE_ENABLES_2" },
+		{ 0x05, 1, 1, "3DSTATE_VFT0" },
+		{ 0x06, 1, 1, "3DSTATE_AA" },
+		{ 0x07, 1, 1, "3DSTATE_RASTERIZATION_RULES" },
+		{ 0x08, 1, 1, "3DSTATE_MODES_1" },
+		{ 0x09, 1, 1, "3DSTATE_STENCIL_TEST" },
+		{ 0x0a, 1, 1, "3DSTATE_VFT1" },
+		{ 0x0b, 1, 1, "3DSTATE_INDPT_ALPHA_BLEND" },
+		{ 0x0c, 1, 1, "3DSTATE_MODES_5" },
+		{ 0x0d, 1, 1, "3DSTATE_MAP_BLEND_OP" },
+		{ 0x0e, 1, 1, "3DSTATE_MAP_BLEND_ARG" },
+		{ 0x0f, 1, 1, "3DSTATE_MODES_2" },
+		{ 0x15, 1, 1, "3DSTATE_FOG_COLOR" },
+		{ 0x16, 1, 1, "3DSTATE_MODES_4"},
+	}, *opcode_3d;
+
+	opcode = (data[0] & 0x1f000000) >> 24;
+
+	switch (opcode) {
+	case 0x1f:
+		return decode_3d_primitive(ctx);
+	case 0x1d:
+		return decode_3d_1d(ctx);
+	case 0x1c:
+		return decode_3d_1c(ctx);
+	}
+
+	for (idx = 0; idx < ARRAY_SIZE(opcodes_3d); idx++) {
+		opcode_3d = &opcodes_3d[idx];
+		if ((data[0] & 0x1f000000) >> 24 == opcode_3d->opcode) {
+			unsigned int len = 1, i;
+
+			instr_out(ctx, 0, "%s\n", opcode_3d->name);
+			if (opcode_3d->max_len > 1) {
+				len = (data[0] & 0xff) + 2;
+				if (len < opcode_3d->min_len ||
+				    len > opcode_3d->max_len) {
+					fprintf(out, "Bad count in %s\n",
+						opcode_3d->name);
+				}
+			}
+
+			for (i = 1; i < len; i++) {
+				instr_out(ctx, i, "dword %d\n", i);
+			}
+			return len;
+		}
+	}
+
+	instr_out(ctx, 0, "3D UNKNOWN: 3d_i830 opcode = 0x%x\n",
+		  opcode);
+	return 1;
+}
+
+struct intel_decode *
+intel_decode_context_alloc(uint32_t devid)
+{
+	struct intel_decode *ctx;
+	int gen = 0;
+
+	gen = intel_gen(devid);
+
+	ctx = calloc(1, sizeof(struct intel_decode));
+	if (!ctx)
+		return NULL;
+
+	ctx->devid = devid;
+	ctx->gen = gen;
+	ctx->out = stdout;
+
+	return ctx;
+}
+
+void
+intel_decode_context_free(struct intel_decode *ctx)
+{
+	free(ctx);
+}
+
+void
+intel_decode_set_dump_past_end(struct intel_decode *ctx,
+				   int dump_past_end)
+{
+	ctx->dump_past_end = !!dump_past_end;
+}
+
+void
+intel_decode_set_batch_pointer(struct intel_decode *ctx,
+				   void *data, uint32_t hw_offset, int count)
+{
+	ctx->base_data = data;
+	ctx->base_hw_offset = hw_offset;
+	ctx->base_count = count;
+}
+
+void
+intel_decode_set_head_tail(struct intel_decode *ctx,
+			       uint32_t head, uint32_t tail)
+{
+	ctx->head = head;
+	ctx->tail = tail;
+}
+
+void
+intel_decode_set_output_file(struct intel_decode *ctx,
+				 FILE *output)
+{
+	ctx->out = output;
+}
+
+/**
+ * Decodes an i830-i915 batch buffer, writing the output to stdout.
+ *
+ * \param data batch buffer contents
+ * \param count number of DWORDs to decode in the batch buffer
+ * \param hw_offset hardware address for the buffer
+ */
+void
+intel_decode(struct intel_decode *ctx)
+{
+	int ret;
+	unsigned int index = 0;
+	uint32_t devid;
+	int size;
+	void *temp;
+
+	if (!ctx)
+		return;
+
+	/* Put a scratch page full of obviously undefined data after
+	 * the batchbuffer.  This lets us avoid a bunch of length
+	 * checking in statically sized packets.
+	 */
+	size = ctx->base_count * 4;
+	temp = malloc(size + 4096);
+	memcpy(temp, ctx->base_data, size);
+	memset((char *)temp + size, 0xd0, 4096);
+	ctx->data = temp;
+
+	ctx->hw_offset = ctx->base_hw_offset;
+	ctx->count = ctx->base_count;
+
+	devid = ctx->devid;
+	head_offset = ctx->head;
+	tail_offset = ctx->tail;
+	out = ctx->out;
+
+	saved_s2_set = 0;
+	saved_s4_set = 1;
+
+	while (ctx->count > 0) {
+		index = 0;
+
+		switch ((ctx->data[index] & 0xe0000000) >> 29) {
+		case 0x0:
+			ret = decode_mi(ctx);
+
+			/* If MI_BATCHBUFFER_END happened, then dump
+			 * the rest of the output in case we some day
+			 * want it in debugging, but don't decode it
+			 * since it'll just confuse in the common
+			 * case.
+			 */
+			if (ret == -1) {
+				if (ctx->dump_past_end) {
+					index++;
+				} else {
+					for (index = index + 1; index < ctx->count;
+					     index++) {
+						instr_out(ctx, index, "\n");
+					}
+				}
+			} else
+				index += ret;
+			break;
+		case 0x2:
+			index += decode_2d(ctx);
+			break;
+		case 0x3:
+			if (AT_LEAST_GEN(devid, 4)) {
+				index +=
+				    decode_3d_965(ctx);
+			} else if (IS_GEN3(devid)) {
+				index += decode_3d(ctx);
+			} else {
+				index +=
+				    decode_3d_i830(ctx);
+			}
+			break;
+		default:
+			instr_out(ctx, index, "UNKNOWN\n");
+			index++;
+			break;
+		}
+		fflush(out);
+
+		if (ctx->count < index)
+			break;
+
+		ctx->count -= index;
+		ctx->data += index;
+		ctx->hw_offset += 4 * index;
+	}
+
+	free(temp);
+}
diff --git a/lib/i915/intel_decode.h b/lib/i915/intel_decode.h
new file mode 100644
index 0000000000..35ba757e39
--- /dev/null
+++ b/lib/i915/intel_decode.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright © 2009-2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef INTEL_DECODE_H
+#define INTEL_DECODE_H
+
+#include <stdio.h>
+#include <stdint.h>
+
+struct intel_decode;
+
+struct intel_decode *intel_decode_context_alloc(uint32_t devid);
+void intel_decode_context_free(struct intel_decode *ctx);
+void intel_decode_set_dump_past_end(struct intel_decode *ctx, int dump_past_end);
+void intel_decode_set_batch_pointer(struct intel_decode *ctx,
+				    void *data, uint32_t hw_offset, int count);
+void intel_decode_set_head_tail(struct intel_decode *ctx,
+				uint32_t head, uint32_t tail);
+void intel_decode_set_output_file(struct intel_decode *ctx, FILE *output);
+void intel_decode(struct intel_decode *ctx);
+
+#endif /* INTEL_DECODE_H */
diff --git a/lib/meson.build b/lib/meson.build
index 8ae9fe13d1..80315009be 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -10,6 +10,7 @@ lib_sources = [
 	'i915/gem_ring.c',
 	'i915/gem_mman.c',
 	'i915/gem_vm.c',
+	'i915/intel_decode.c',
 	'i915/intel_memory_region.c',
 	'i915/intel_mocs.c',
 	'i915/i915_blt.c',
-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 08/11] tools/intel_dump|error_decode: Use local igt decode code

[Zbigniew Kempczyński]

Instead of using libdrm decode code, switch to ported to IGT counterpart.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 tools/intel_dump_decode.c  | 16 ++++++++--------
 tools/intel_error_decode.c | 14 +++++++-------
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/tools/intel_dump_decode.c b/tools/intel_dump_decode.c
index 4bb774406f..95e06fbe7f 100644
--- a/tools/intel_dump_decode.c
+++ b/tools/intel_dump_decode.c
@@ -34,9 +34,9 @@
 #include <fcntl.h>
 #include <getopt.h>
 
-#include <intel_bufmgr.h>
+#include "i915/intel_decode.h"
 
-struct drm_intel_decode *ctx;
+struct intel_decode *ctx;
 
 static void
 read_bin_file(const char * filename)
@@ -54,12 +54,12 @@ read_bin_file(const char * filename)
 		exit (1);
 	}
 
-	drm_intel_decode_set_dump_past_end(ctx, 1);
+	intel_decode_set_dump_past_end(ctx, 1);
 
 	offset = 0;
 	while ((ret = read (fd, buf, sizeof(buf))) > 0) {
-		drm_intel_decode_set_batch_pointer(ctx, buf, offset, ret/4);
-		drm_intel_decode(ctx);
+		intel_decode_set_batch_pointer(ctx, buf, offset, ret/4);
+		intel_decode(ctx);
 		offset += ret;
 	}
 	close (fd);
@@ -112,8 +112,8 @@ read_data_file(const char * filename)
     }
 
     if (count) {
-	drm_intel_decode_set_batch_pointer(ctx, data, gtt_offset, count);
-	drm_intel_decode(ctx);
+	intel_decode_set_batch_pointer(ctx, data, gtt_offset, count);
+	intel_decode(ctx);
     }
 
     free (data);
@@ -192,7 +192,7 @@ main (int argc, char *argv[])
 	if (devid_str)
 		devid = strtoul(devid_str, NULL, 0);
 
-	ctx = drm_intel_decode_context_alloc(devid);
+	ctx = intel_decode_context_alloc(devid);
 
 	if (optind == argc) {
 		fprintf(stderr, "no input file given\n");
diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index 90a18a07ba..99680bedc7 100644
--- a/tools/intel_error_decode.c
+++ b/tools/intel_error_decode.c
@@ -49,7 +49,6 @@
 #include <sys/stat.h>
 #include <err.h>
 #include <assert.h>
-#include <intel_bufmgr.h>
 #include <zlib.h>
 #include <ctype.h>
 
@@ -58,6 +57,7 @@
 #include "instdone.h"
 #include "intel_reg.h"
 #include "drmtest.h"
+#include "i915/intel_decode.h"
 
 static uint32_t
 print_head(unsigned int reg)
@@ -445,7 +445,7 @@ static bool maybe_ascii(const void *data, int check)
 	return true;
 }
 
-static void decode(struct drm_intel_decode *ctx,
+static void decode(struct intel_decode *ctx,
 		   const char *buffer_name,
 		   const char *ring_name,
 		   uint64_t gtt_offset,
@@ -466,9 +466,9 @@ static void decode(struct drm_intel_decode *ctx,
 	printf("\n");
 
 	if (decode && ctx) {
-		drm_intel_decode_set_batch_pointer(ctx, data, gtt_offset,
+		intel_decode_set_batch_pointer(ctx, data, gtt_offset,
 						   *count);
-		drm_intel_decode(ctx);
+		intel_decode(ctx);
 	} else if (maybe_ascii(data, 16)) {
 		printf("%*s\n", 4 * *count, (char *)data);
 	} else {
@@ -566,7 +566,7 @@ static int ascii85_decode(const char *in, uint32_t **out, bool inflate)
 static void
 read_data_file(FILE *file)
 {
-	struct drm_intel_decode *decode_ctx = NULL;
+	struct intel_decode *decode_ctx = NULL;
 	uint32_t devid = PCI_CHIP_I855_GM;
 	uint32_t *data = NULL;
 	uint32_t head[MAX_RINGS];
@@ -692,7 +692,7 @@ read_data_file(FILE *file)
 				printf("Detected GEN%i chipset\n",
 						intel_gen(devid));
 
-				decode_ctx = drm_intel_decode_context_alloc(devid);
+				decode_ctx = intel_decode_context_alloc(devid);
 			}
 
 			matched = sscanf(line, "  CTL: 0x%08x\n", &reg);
@@ -708,7 +708,7 @@ read_data_file(FILE *file)
 			if (matched == 1) {
 				print_acthd(reg, ring_length);
 				if (decode_ctx)
-					drm_intel_decode_set_head_tail(decode_ctx,
+					intel_decode_set_head_tail(decode_ctx,
 								       reg,
 								       0xffffffff);
 			}
-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 09/11] lib/ioctl_wrappers: Remove gem_handle_to_libdrm_bo

[Zbigniew Kempczyński]

Function is not used anymore in IGT so lets remove it, especially it
keeps libdrm dependency.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 lib/ioctl_wrappers.c | 31 -------------------------------
 lib/ioctl_wrappers.h |  5 -----
 2 files changed, 36 deletions(-)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 09eb3ce7b5..1ab41ab6d6 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -92,37 +92,6 @@
 int (*igt_ioctl)(int fd, unsigned long request, void *arg) = drmIoctl;
 
 
-/**
- * gem_handle_to_libdrm_bo:
- * @bufmgr: libdrm buffer manager instance
- * @fd: open i915 drm file descriptor
- * @name: buffer name in libdrm
- * @handle: gem buffer object handle
- *
- * This helper function imports a raw gem buffer handle into the libdrm buffer
- * manager.
- *
- * Returns: The imported libdrm buffer manager object.
- */
-drm_intel_bo *
-gem_handle_to_libdrm_bo(drm_intel_bufmgr *bufmgr, int fd, const char *name, uint32_t handle)
-{
-	struct drm_gem_flink flink;
-	int ret;
-	drm_intel_bo *bo;
-
-	memset(&flink, 0, sizeof(handle));
-	flink.handle = handle;
-	ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink);
-	igt_assert(ret == 0);
-	errno = 0;
-
-	bo = drm_intel_bo_gem_create_from_name(bufmgr, name, flink.name);
-	igt_assert(bo);
-
-	return bo;
-}
-
 static int
 __gem_get_tiling(int fd, struct drm_i915_gem_get_tiling *arg)
 {
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 9a897fec23..cf228c2651 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -33,7 +33,6 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include <sys/mman.h>
-#include <intel_bufmgr.h>
 #include <i915_drm.h>
 
 #include "i915/gem_context.h"
@@ -51,10 +50,6 @@
  */
 extern int (*igt_ioctl)(int fd, unsigned long request, void *arg);
 
-/* libdrm interfacing */
-drm_intel_bo * gem_handle_to_libdrm_bo(drm_intel_bufmgr *bufmgr, int fd,
-				       const char *name, uint32_t handle);
-
 /* ioctl_wrappers.c:
  *
  * ioctl wrappers and similar stuff for bare metal testing */
-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 10/11] tools/meson: Move tools out of libdrm scope

[Zbigniew Kempczyński]

Libdrm was removed from intel tools so lets remove libdrm configuration
and migrate tools to normal tools list.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 tools/meson.build | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/tools/meson.build b/tools/meson.build
index 24d0ea7140..d2defec870 100644
--- a/tools/meson.build
+++ b/tools/meson.build
@@ -18,9 +18,12 @@ tools_progs = [
 	'intel_bios_dumper',
 	'intel_display_crc',
 	'intel_display_poller',
+	'intel_dump_decode',
+	'intel_error_decode',
 	'intel_forcewaked',
 	'intel_gpu_frequency',
 	'intel_firmware_decode',
+	'intel_framebuffer_dump',
 	'intel_gpu_time',
 	'intel_gtt',
 	'intel_guc_logger',
@@ -28,6 +31,7 @@ tools_progs = [
 	'intel_lid',
 	'intel_opregion_decode',
 	'intel_panel_fitter',
+	'intel_perf_counters',
 	'intel_pm_rpm',
 	'intel_reg_checker',
 	'intel_residency',
@@ -40,16 +44,7 @@ tools_progs = [
 	'lsgpu',
 ]
 tool_deps = igt_deps
-
-if libdrm_intel.found()
-	tools_progs += [
-		'intel_dump_decode',
-		'intel_error_decode',
-		'intel_framebuffer_dump',
-		'intel_perf_counters',
-	]
-	tool_deps += zlib
-endif
+tool_deps += zlib
 
 foreach prog : tools_progs
 	executable(prog, prog + '.c',
-- 
2.34.1

[igt-dev] [PATCH i-g-t v4 11/11] lib/meson: Remove libdrm configuration and intel_bufmgr stubs

[Zbigniew Kempczyński]

We don't need to link with intel libdrm so get rid of libdrm configuration
as well as bufmgr stub.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 lib/meson.build              |   7 -
 lib/stubs/drm/README         |   4 -
 lib/stubs/drm/intel_bufmgr.c | 292 -------------------------------
 lib/stubs/drm/intel_bufmgr.h | 323 -----------------------------------
 4 files changed, 626 deletions(-)
 delete mode 100644 lib/stubs/drm/README
 delete mode 100644 lib/stubs/drm/intel_bufmgr.c
 delete mode 100644 lib/stubs/drm/intel_bufmgr.h

diff --git a/lib/meson.build b/lib/meson.build
index 80315009be..f2bf11226c 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -114,13 +114,6 @@ lib_deps = [
 	zlib
 ]
 
-if libdrm_intel.found()
-	lib_deps += libdrm_intel
-else
-	lib_sources += 'stubs/drm/intel_bufmgr.c'
-	inc = [ inc, include_directories('stubs/drm') ]
-endif
-
 if libdrm_nouveau.found()
 	lib_deps += libdrm_nouveau
 	lib_sources += [
diff --git a/lib/stubs/drm/README b/lib/stubs/drm/README
deleted file mode 100644
index 79f2b5f676..0000000000
--- a/lib/stubs/drm/README
+++ /dev/null
@@ -1,4 +0,0 @@
-intel_bufmgr.h is a local copy of the file provided by libdrm (intel/intel_bufmgr.h).
-
-Before releasing i-g-t a current copy of intel_bufmgr.h should be copied into
-this directory of i-g-t.
diff --git a/lib/stubs/drm/intel_bufmgr.c b/lib/stubs/drm/intel_bufmgr.c
deleted file mode 100644
index cbab2484bd..0000000000
--- a/lib/stubs/drm/intel_bufmgr.c
+++ /dev/null
@@ -1,292 +0,0 @@
-#include <stdbool.h>
-#include <errno.h>
-
-#include "igt_core.h"
-#include "intel_bufmgr.h"
-
-#ifdef __GNUC__
-#pragma GCC push_options
-#pragma GCC diagnostic ignored "-Wsuggest-attribute=noreturn"
-#endif
-
-static const char missing_support_str[] = "Not compiled with libdrm_intel support\n";
-
-drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size)
-{
-	igt_require_f(false, missing_support_str);
-	return NULL;
-}
-
-void drm_intel_bo_unreference(drm_intel_bo *bo)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
-				 unsigned long size, unsigned int alignment)
-{
-	igt_require_f(false, missing_support_str);
-	return NULL;
-}
-
-int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
-			 unsigned long size, const void *data)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
-				  int used, unsigned int flags)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
-				drm_intel_bo *target_bo, uint32_t target_offset,
-				uint32_t read_domains, uint32_t write_domain)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
-				  drm_intel_bo *target_bo,
-				  uint32_t target_offset,
-				  uint32_t read_domains, uint32_t write_domain)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
-			    uint32_t * swizzle_mode)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
-			  struct drm_clip_rect *cliprects, int num_cliprects,
-			  int DR4, unsigned int flags)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-void drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
-					      drm_intel_aub_annotation *annotations,
-					      unsigned count)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-int drm_intel_bo_exec(drm_intel_bo *bo, int used,
-		      struct drm_clip_rect *cliprects, int num_cliprects, int DR4)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
-			     unsigned long size, void *data)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_bo_map(drm_intel_bo *bo, int write_enable)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-int drm_intel_bo_unmap(drm_intel_bo *bo)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
-						const char *name,
-						unsigned int handle)
-{
-	igt_require_f(false, missing_support_str);
-	return NULL;
-}
-
-int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
-						 int prime_fd, int size)
-{
-	igt_require_f(false, missing_support_str);
-	return NULL;
-}
-
-void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
-					     int limit)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
-{
-	igt_require_f(false, missing_support_str);
-	return NULL;
-}
-
-int drm_intel_gem_context_get_id(drm_intel_context *ctx,
-                                 uint32_t *ctx_id)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-void drm_intel_gem_context_destroy(drm_intel_context *ctx)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
-				       const char *name,
-				       int x, int y, int cpp,
-				       uint32_t *tiling_mode,
-				       unsigned long *pitch,
-				       unsigned long flags)
-{
-	igt_require_f(false, missing_support_str);
-	return NULL;
-}
-
-void drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
-					  const char *filename)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
-				   int x1, int y1, int width, int height,
-				   enum aub_dump_bmp_format format,
-				   int pitch, int offset)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
-				uint32_t stride)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-void drm_intel_bo_reference(drm_intel_bo *bo)
-{
-	igt_require_f(false, missing_support_str);
-}
-
-int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
-					    const char *name,
-					    unsigned long size,
-					    unsigned int alignment)
-{
-	igt_require_f(false, missing_support_str);
-	return NULL;
-}
-
-int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
-{
-	igt_require_f(false, missing_support_str);
-	return -ENODEV;
-}
-
-drm_intel_bo *drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
-					 const char *name,
-					 void *addr, uint32_t tiling_mode,
-					 uint32_t stride, unsigned long size,
-					 unsigned long flags)
-{
-	igt_require_f(false, missing_support_str);
-	return NULL;
-}
-
-#ifdef __GNUC__
-#pragma GCC pop_options
-#endif
diff --git a/lib/stubs/drm/intel_bufmgr.h b/lib/stubs/drm/intel_bufmgr.h
deleted file mode 100644
index f6bb4f5213..0000000000
--- a/lib/stubs/drm/intel_bufmgr.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * Copyright © 2008-2012 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <eric@anholt.net>
- *
- */
-
-/**
- * @file intel_bufmgr.h
- *
- * Public definitions of Intel-specific bufmgr functions.
- */
-
-#ifndef INTEL_BUFMGR_H
-#define INTEL_BUFMGR_H
-
-#include <stdio.h>
-#include <stdint.h>
-#include <stdio.h>
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-struct drm_clip_rect;
-
-typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
-typedef struct _drm_intel_context drm_intel_context;
-typedef struct _drm_intel_bo drm_intel_bo;
-
-struct _drm_intel_bo {
-	/**
-	 * Size in bytes of the buffer object.
-	 *
-	 * The size may be larger than the size originally requested for the
-	 * allocation, such as being aligned to page size.
-	 */
-	unsigned long size;
-
-	/**
-	 * Alignment requirement for object
-	 *
-	 * Used for GTT mapping & pinning the object.
-	 */
-	unsigned long align;
-
-	/**
-	 * Deprecated field containing (possibly the low 32-bits of) the last
-	 * seen virtual card address.  Use offset64 instead.
-	 */
-	unsigned long offset;
-
-	/**
-	 * Virtual address for accessing the buffer data.  Only valid while
-	 * mapped.
-	 */
-#ifdef __cplusplus
-	void *virt;
-#else
-	void *virtual;
-#endif
-
-	/** Buffer manager context associated with this buffer object */
-	drm_intel_bufmgr *bufmgr;
-
-	/**
-	 * MM-specific handle for accessing object
-	 */
-	int handle;
-
-	/**
-	 * Last seen card virtual address (offset from the beginning of the
-	 * aperture) for the object.  This should be used to fill relocation
-	 * entries when calling drm_intel_bo_emit_reloc()
-	 */
-	uint64_t offset64;
-};
-
-enum aub_dump_bmp_format {
-	AUB_DUMP_BMP_FORMAT_8BIT = 1,
-	AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
-	AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
-	AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
-};
-
-typedef struct _drm_intel_aub_annotation {
-	uint32_t type;
-	uint32_t subtype;
-	uint32_t ending_offset;
-} drm_intel_aub_annotation;
-
-#define BO_ALLOC_FOR_RENDER (1<<0)
-
-drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
-				 unsigned long size, unsigned int alignment);
-drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
-					    const char *name,
-					    unsigned long size,
-					    unsigned int alignment);
-drm_intel_bo *drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
-					const char *name,
-					void *addr, uint32_t tiling_mode,
-					uint32_t stride, unsigned long size,
-					unsigned long flags);
-drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
-				       const char *name,
-				       int x, int y, int cpp,
-				       uint32_t *tiling_mode,
-				       unsigned long *pitch,
-				       unsigned long flags);
-void drm_intel_bo_reference(drm_intel_bo *bo);
-void drm_intel_bo_unreference(drm_intel_bo *bo);
-int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
-int drm_intel_bo_unmap(drm_intel_bo *bo);
-
-int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
-			 unsigned long size, const void *data);
-int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
-			     unsigned long size, void *data);
-void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
-
-void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
-void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
-int drm_intel_bo_exec(drm_intel_bo *bo, int used,
-		      struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
-int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
-			struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
-			unsigned int flags);
-int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
-
-int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
-			    drm_intel_bo *target_bo, uint32_t target_offset,
-			    uint32_t read_domains, uint32_t write_domain);
-int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
-				  drm_intel_bo *target_bo,
-				  uint32_t target_offset,
-				  uint32_t read_domains, uint32_t write_domain);
-int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
-int drm_intel_bo_unpin(drm_intel_bo *bo);
-int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
-			    uint32_t stride);
-int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
-			    uint32_t * swizzle_mode);
-int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
-int drm_intel_bo_busy(drm_intel_bo *bo);
-int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
-int drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable);
-int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset);
-
-int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
-int drm_intel_bo_is_reusable(drm_intel_bo *bo);
-int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
-
-/* drm_intel_bufmgr_gem.c */
-drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
-drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
-						const char *name,
-						unsigned int handle);
-void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
-void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
-void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
-					     int limit);
-int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
-int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
-int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
-
-int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
-void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
-void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
-
-void
-drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
-				      const char *filename);
-void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
-void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
-				   int x1, int y1, int width, int height,
-				   enum aub_dump_bmp_format format,
-				   int pitch, int offset);
-void
-drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
-					 drm_intel_aub_annotation *annotations,
-					 unsigned count);
-
-int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
-
-int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
-int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
-int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
-
-drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
-int drm_intel_gem_context_get_id(drm_intel_context *ctx,
-                                 uint32_t *ctx_id);
-void drm_intel_gem_context_destroy(drm_intel_context *ctx);
-int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
-				  int used, unsigned int flags);
-
-int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
-drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
-						int prime_fd, int size);
-
-/* drm_intel_bufmgr_fake.c */
-drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
-					     unsigned long low_offset,
-					     void *low_virtual,
-					     unsigned long size,
-					     volatile unsigned int
-					     *last_dispatch);
-void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
-					     volatile unsigned int
-					     *last_dispatch);
-void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
-					     int (*exec) (drm_intel_bo *bo,
-							  unsigned int used,
-							  void *priv),
-					     void *priv);
-void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
-					      unsigned int (*emit) (void *priv),
-					      void (*wait) (unsigned int fence,
-							    void *priv),
-					      void *priv);
-drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
-					     const char *name,
-					     unsigned long offset,
-					     unsigned long size, void *virt);
-void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
-					     void (*invalidate_cb) (drm_intel_bo
-								    * bo,
-								    void *ptr),
-					     void *ptr);
-
-void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
-void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
-
-struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid);
-void drm_intel_decode_context_free(struct drm_intel_decode *ctx);
-void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
-					void *data, uint32_t hw_offset,
-					int count);
-void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
-					int dump_past_end);
-void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
-				    uint32_t head, uint32_t tail);
-void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
-void drm_intel_decode(struct drm_intel_decode *ctx);
-
-int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
-		       uint32_t offset,
-		       uint64_t *result);
-
-int drm_intel_get_reset_stats(drm_intel_context *ctx,
-			      uint32_t *reset_count,
-			      uint32_t *active,
-			      uint32_t *pending);
-
-int drm_intel_get_subslice_total(int fd, unsigned int *subslice_total);
-int drm_intel_get_eu_total(int fd, unsigned int *eu_total);
-
-/** @{ Compatibility defines to keep old code building despite the symbol rename
- * from dri_* to drm_intel_*
- */
-#define dri_bo drm_intel_bo
-#define dri_bufmgr drm_intel_bufmgr
-#define dri_bo_alloc drm_intel_bo_alloc
-#define dri_bo_reference drm_intel_bo_reference
-#define dri_bo_unreference drm_intel_bo_unreference
-#define dri_bo_map drm_intel_bo_map
-#define dri_bo_unmap drm_intel_bo_unmap
-#define dri_bo_subdata drm_intel_bo_subdata
-#define dri_bo_get_subdata drm_intel_bo_get_subdata
-#define dri_bo_wait_rendering drm_intel_bo_wait_rendering
-#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
-#define dri_bufmgr_destroy drm_intel_bufmgr_destroy
-#define dri_bo_exec drm_intel_bo_exec
-#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
-#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset,		\
-			  reloc_offset, target_bo)			\
-	drm_intel_bo_emit_reloc(reloc_bo, reloc_offset,			\
-				target_bo, target_offset,		\
-				read, write);
-#define dri_bo_pin drm_intel_bo_pin
-#define dri_bo_unpin drm_intel_bo_unpin
-#define dri_bo_get_tiling drm_intel_bo_get_tiling
-#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
-#define dri_bo_flink drm_intel_bo_flink
-#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
-#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
-#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
-#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
-#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
-#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
-#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
-#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
-#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
-#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
-#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
-
-/** @{ */
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* INTEL_BUFMGR_H */
-- 
2.34.1

[igt-dev] ✓ Fi.CI.BAT: success for Remove libdrm remnants in i915 code (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6145 bytes --]

== Series Details ==

Series: Remove libdrm remnants in i915 code (rev4)
URL   : https://patchwork.freedesktop.org/series/111200/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12471 -> IGTPW_8200
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html

Participating hosts (44 -> 44)
------------------------------

  Additional (1): fi-hsw-4770 
  Missing    (1): fi-tgl-dsi 

Known issues
------------

  Here are the changes found in IGTPW_8200 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [PASS][1] -> [FAIL][2] ([i915#7229])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@gem_softpin@allocator-basic-reserve:
    - fi-hsw-4770:        NOTRUN -> [SKIP][3] ([fdo#109271]) +11 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/fi-hsw-4770/igt@gem_softpin@allocator-basic-reserve.html

  * igt@i915_selftest@live@gt_timelines:
    - fi-apl-guc:         [PASS][4] -> [INCOMPLETE][5] ([i915#7511])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-4770:        NOTRUN -> [INCOMPLETE][6] ([i915#4785])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@slpc:
    - bat-adlp-4:         [PASS][7] -> [DMESG-FAIL][8] ([i915#6367])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/bat-adlp-4/igt@i915_selftest@live@slpc.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/bat-adlp-4/igt@i915_selftest@live@slpc.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-hsw-4770:        NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +7 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/fi-hsw-4770/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_psr@sprite_plane_onoff:
    - fi-hsw-4770:        NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1072]) +3 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
    - fi-hsw-4770:        NOTRUN -> [FAIL][11] ([i915#5594])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/fi-hsw-4770/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - {bat-rplp-1}:       [DMESG-WARN][12] ([i915#2867]) -> [PASS][13] +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-soraka:      [DMESG-FAIL][14] ([i915#5334]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@late_gt_pm:
    - fi-kbl-soraka:      [INCOMPLETE][16] -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/fi-kbl-soraka/igt@i915_selftest@live@late_gt_pm.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/fi-kbl-soraka/igt@i915_selftest@live@late_gt_pm.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
  [i915#7346]: https://gitlab.freedesktop.org/drm/intel/issues/7346
  [i915#7511]: https://gitlab.freedesktop.org/drm/intel/issues/7511


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7083 -> IGTPW_8200

  CI-20190529: 20190529
  CI_DRM_12471: 7f8dc69dce0e934751fe31c01a6b6baa0c65bf23 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8200: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html
  IGT_7083: c001793d5f22deb01918b6ba52af829794582df1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

-igt@drm_import_export@flink
-igt@drm_import_export@import-close-race-flink
-igt@drm_import_export@import-close-race-prime
-igt@drm_import_export@prime

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html

[-- Attachment #2: Type: text/html, Size: 6358 bytes --]

[igt-dev] ✗ Fi.CI.IGT: failure for Remove libdrm remnants in i915 code (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 35500 bytes --]

== Series Details ==

Series: Remove libdrm remnants in i915 code (rev4)
URL   : https://patchwork.freedesktop.org/series/111200/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12471_full -> IGTPW_8200_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_8200_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_8200_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html

Participating hosts (9 -> 8)
------------------------------

  Additional (2): shard-rkl shard-dg1 
  Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_8200_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_caching@read-writes:
    - shard-apl:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@gem_caching@read-writes.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-apl:          [PASS][2] -> [INCOMPLETE][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  
Known issues
------------

  Here are the changes found in IGTPW_8200_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         NOTRUN -> [FAIL][4] ([i915#2410])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-iclb:         NOTRUN -> [FAIL][9] ([i915#2842]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
    - shard-tglb:         NOTRUN -> [FAIL][10] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-apl:          NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - shard-iclb:         NOTRUN -> [SKIP][12] ([i915#4613]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_lmem_swapping@parallel-random-engines.html
    - shard-tglb:         NOTRUN -> [SKIP][13] ([i915#4613]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][14] ([i915#768])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_softpin@evict-single-offset:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([i915#4171])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@gem_softpin@evict-single-offset.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gem_softpin@evict-single-offset.html

  * igt@gem_vm_create@invalid-create:
    - shard-snb:          NOTRUN -> [SKIP][17] ([fdo#109271]) +65 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb7/igt@gem_vm_create@invalid-create.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-tglb:         NOTRUN -> [SKIP][18] ([i915#2527] / [i915#2856])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@gen9_exec_parse@bb-chained.html
    - shard-iclb:         NOTRUN -> [SKIP][19] ([i915#2856])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gen9_exec_parse@bb-chained.html

  * igt@i915_module_load@reload:
    - shard-snb:          [PASS][20] -> [DMESG-WARN][21] ([i915#4528])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-snb4/igt@i915_module_load@reload.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb4/igt@i915_module_load@reload.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][22] ([i915#4281])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-iclb:         NOTRUN -> [SKIP][23] ([i915#5723])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@i915_query@test-query-geometry-subslices.html
    - shard-tglb:         NOTRUN -> [SKIP][24] ([i915#5723])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@i915_query@test-query-geometry-subslices.html

  * igt@kms_atomic@atomic_plane_damage:
    - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#4765])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_atomic@atomic_plane_damage.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-iclb:         NOTRUN -> [SKIP][26] ([i915#404])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
    - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#404])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271]) +44 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@kms_big_fb@linear-32bpp-rotate-270.html
    - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#111614]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb7/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][31] ([fdo#109278]) +6 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][32] ([i915#3689] / [i915#6095]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb2/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#111615] / [i915#3689])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([i915#6095])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3689])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb7/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_chamelium@dp-crc-fast:
    - shard-iclb:         NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827]) +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@dp-frame-dump:
    - shard-apl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_chamelium@dp-frame-dump.html
    - shard-snb:          NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb4/igt@kms_chamelium@dp-frame-dump.html

  * igt@kms_chamelium@hdmi-audio-edid:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +2 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@kms_chamelium@hdmi-audio-edid.html

  * igt@kms_content_protection@lic@pipe-a-dp-1:
    - shard-apl:          NOTRUN -> [TIMEOUT][41] ([i915#7173])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl1/igt@kms_content_protection@lic@pipe-a-dp-1.html

  * igt@kms_content_protection@mei_interface:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([i915#7118])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb2/igt@kms_content_protection@mei_interface.html
    - shard-iclb:         NOTRUN -> [SKIP][43] ([i915#7118])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_content_protection@mei_interface.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#109279] / [i915#3359])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_cursor_crc@cursor-offscreen-512x170.html
    - shard-tglb:         NOTRUN -> [SKIP][45] ([fdo#109279] / [i915#3359])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1:
    - shard-apl:          [PASS][46] -> [DMESG-WARN][47] ([i915#180])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor@toggle:
    - shard-iclb:         [PASS][48] -> [FAIL][49] ([i915#2346]) +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#1769] / [i915#3555])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_flip@plain-flip-ts-check@a-edp1:
    - shard-iclb:         [PASS][51] -> [DMESG-WARN][52] ([i915#7507])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@kms_flip@plain-flip-ts-check@a-edp1.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_flip@plain-flip-ts-check@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-iclb:         NOTRUN -> [SKIP][53] ([i915#2587] / [i915#2672]) +4 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][54] ([i915#2672]) +8 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][55] ([i915#2672] / [i915#3555])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt:
    - shard-iclb:         [PASS][56] -> [FAIL][57] ([i915#2546])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
    - shard-tglb:         NOTRUN -> [SKIP][58] ([i915#6497]) +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render:
    - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#109280] / [fdo#111825]) +7 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109280]) +6 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1:
    - shard-apl:          NOTRUN -> [FAIL][61] ([i915#4573]) +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl6/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
    - shard-iclb:         [PASS][62] -> [SKIP][63] ([i915#5176]) +2 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
    - shard-iclb:         [PASS][64] -> [SKIP][65] ([i915#5235]) +2 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html

  * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
    - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#2920])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
    - shard-iclb:         NOTRUN -> [SKIP][67] ([fdo#111068] / [i915#658])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
    - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#658])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1:
    - shard-iclb:         NOTRUN -> [FAIL][69] ([i915#5939]) +2 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [PASS][70] -> [SKIP][71] ([fdo#109441]) +2 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-iclb:         [PASS][72] -> [SKIP][73] ([i915#5519])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_vblank@pipe-a-wait-busy:
    - shard-iclb:         NOTRUN -> [DMESG-WARN][74] ([i915#7507])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_vblank@pipe-a-wait-busy.html

  * igt@perf@gen12-oa-tlb-invalidate:
    - shard-iclb:         NOTRUN -> [SKIP][75] ([fdo#109289])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@perf@gen12-oa-tlb-invalidate.html

  
#### Possible fixes ####

  * igt@gem_exec_balancer@parallel:
    - shard-iclb:         [SKIP][76] ([i915#4525]) -> [PASS][77] +2 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@gem_exec_balancer@parallel.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@gem_exec_balancer@parallel.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][78] ([i915#3989] / [i915#454]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-apl:          [DMESG-WARN][80] ([i915#180]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_psr@psr2_sprite_plane_onoff:
    - shard-iclb:         [SKIP][82] ([fdo#109441]) -> [PASS][83] +2 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb3/igt@kms_psr@psr2_sprite_plane_onoff.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html

  * igt@kms_vblank@pipe-b-wait-idle-hang:
    - shard-apl:          [SKIP][84] ([fdo#109271]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl8/igt@kms_vblank@pipe-b-wait-idle-hang.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@kms_vblank@pipe-b-wait-idle-hang.html

  
#### Warnings ####

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-iclb:         [SKIP][86] ([i915#4525]) -> [FAIL][87] ([i915#6117])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][88] ([i915#658]) -> [SKIP][89] ([i915#588])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-iclb:         [SKIP][90] ([i915#2920]) -> [SKIP][91] ([i915#658])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area:
    - shard-iclb:         [SKIP][92] ([i915#2920]) -> [SKIP][93] ([fdo#111068] / [i915#658])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][94], [FAIL][95], [FAIL][96]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][97], [FAIL][98], [FAIL][99]) ([i915#3002] / [i915#4312])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@runner@aborted.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl8/igt@runner@aborted.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl7/igt@runner@aborted.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@runner@aborted.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl1/igt@runner@aborted.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
  [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
  [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4765]: https://gitlab.freedesktop.org/drm/intel/issues/4765
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
  [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
  [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
  [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
  [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
  [i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7507]: https://gitlab.freedesktop.org/drm/intel/issues/7507
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7083 -> IGTPW_8200
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_12471: 7f8dc69dce0e934751fe31c01a6b6baa0c65bf23 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8200: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html
  IGT_7083: c001793d5f22deb01918b6ba52af829794582df1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html

[-- Attachment #2: Type: text/html, Size: 32255 bytes --]

Re: [igt-dev] ✗ Fi.CI.IGT: failure for Remove libdrm remnants in i915 code (rev4)

[Petri Latvala]

On Tue, Dec 06, 2022 at 10:35:34AM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: Remove libdrm remnants in i915 code (rev4)
> URL   : https://patchwork.freedesktop.org/series/111200/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_12471_full -> IGTPW_8200_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with IGTPW_8200_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in IGTPW_8200_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html
> 
> Participating hosts (9 -> 8)
> ------------------------------
> 
>   Additional (2): shard-rkl shard-dg1 
>   Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in IGTPW_8200_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@gem_caching@read-writes:
>     - shard-apl:          NOTRUN -> [INCOMPLETE][1]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@gem_caching@read-writes.html
> 
>   * igt@gem_partial_pwrite_pread@writes-after-reads-display:
>     - shard-apl:          [PASS][2] -> [INCOMPLETE][3]
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

Zbigniew, how confident are you that these are not caused by the
changes?


-- 
Petri Latvala



> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in IGTPW_8200_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_ctx_persistence@many-contexts:
>     - shard-tglb:         NOTRUN -> [FAIL][4] ([i915#2410])
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_ctx_persistence@many-contexts.html
> 
>   * igt@gem_exec_balancer@parallel-keep-in-fence:
>     - shard-iclb:         [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html
> 
>   * igt@gem_exec_fair@basic-pace-share@rcs0:
>     - shard-tglb:         [PASS][7] -> [FAIL][8] ([i915#2842])
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
> 
>   * igt@gem_exec_fair@basic-pace-solo@rcs0:
>     - shard-iclb:         NOTRUN -> [FAIL][9] ([i915#2842]) +1 similar issue
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
>     - shard-tglb:         NOTRUN -> [FAIL][10] ([i915#2842])
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> 
>   * igt@gem_lmem_swapping@heavy-verify-random:
>     - shard-apl:          NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +2 similar issues
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@gem_lmem_swapping@heavy-verify-random.html
> 
>   * igt@gem_lmem_swapping@parallel-random-engines:
>     - shard-iclb:         NOTRUN -> [SKIP][12] ([i915#4613]) +1 similar issue
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_lmem_swapping@parallel-random-engines.html
>     - shard-tglb:         NOTRUN -> [SKIP][13] ([i915#4613]) +1 similar issue
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_lmem_swapping@parallel-random-engines.html
> 
>   * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
>     - shard-iclb:         NOTRUN -> [SKIP][14] ([i915#768])
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html
> 
>   * igt@gem_softpin@evict-single-offset:
>     - shard-iclb:         [PASS][15] -> [FAIL][16] ([i915#4171])
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@gem_softpin@evict-single-offset.html
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gem_softpin@evict-single-offset.html
> 
>   * igt@gem_vm_create@invalid-create:
>     - shard-snb:          NOTRUN -> [SKIP][17] ([fdo#109271]) +65 similar issues
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb7/igt@gem_vm_create@invalid-create.html
> 
>   * igt@gen9_exec_parse@bb-chained:
>     - shard-tglb:         NOTRUN -> [SKIP][18] ([i915#2527] / [i915#2856])
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@gen9_exec_parse@bb-chained.html
>     - shard-iclb:         NOTRUN -> [SKIP][19] ([i915#2856])
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gen9_exec_parse@bb-chained.html
> 
>   * igt@i915_module_load@reload:
>     - shard-snb:          [PASS][20] -> [DMESG-WARN][21] ([i915#4528])
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-snb4/igt@i915_module_load@reload.html
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb4/igt@i915_module_load@reload.html
> 
>   * igt@i915_pm_dc@dc9-dpms:
>     - shard-tglb:         NOTRUN -> [SKIP][22] ([i915#4281])
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@i915_pm_dc@dc9-dpms.html
> 
>   * igt@i915_query@test-query-geometry-subslices:
>     - shard-iclb:         NOTRUN -> [SKIP][23] ([i915#5723])
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@i915_query@test-query-geometry-subslices.html
>     - shard-tglb:         NOTRUN -> [SKIP][24] ([i915#5723])
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@i915_query@test-query-geometry-subslices.html
> 
>   * igt@kms_atomic@atomic_plane_damage:
>     - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#4765])
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_atomic@atomic_plane_damage.html
> 
>   * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
>     - shard-iclb:         NOTRUN -> [SKIP][26] ([i915#404])
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
>     - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#404])
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
> 
>   * igt@kms_big_fb@linear-32bpp-rotate-270:
>     - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271]) +44 similar issues
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@kms_big_fb@linear-32bpp-rotate-270.html
>     - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#111614]) +1 similar issue
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb7/igt@kms_big_fb@linear-32bpp-rotate-270.html
> 
>   * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
>     - shard-iclb:         NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614]) +1 similar issue
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
> 
>   * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs:
>     - shard-iclb:         NOTRUN -> [SKIP][31] ([fdo#109278]) +6 similar issues
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs.html
> 
>   * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs:
>     - shard-tglb:         NOTRUN -> [SKIP][32] ([i915#3689] / [i915#6095]) +1 similar issue
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb2/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs.html
> 
>   * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
>     - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886])
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
> 
>   * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
>     - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#111615] / [i915#3689])
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html
> 
>   * igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
>     - shard-tglb:         NOTRUN -> [SKIP][35] ([i915#6095])
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html
> 
>   * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
>     - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3689])
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb7/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
> 
>   * igt@kms_chamelium@dp-crc-fast:
>     - shard-iclb:         NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827]) +2 similar issues
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_chamelium@dp-crc-fast.html
> 
>   * igt@kms_chamelium@dp-frame-dump:
>     - shard-apl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +4 similar issues
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_chamelium@dp-frame-dump.html
>     - shard-snb:          NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +2 similar issues
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb4/igt@kms_chamelium@dp-frame-dump.html
> 
>   * igt@kms_chamelium@hdmi-audio-edid:
>     - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +2 similar issues
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@kms_chamelium@hdmi-audio-edid.html
> 
>   * igt@kms_content_protection@lic@pipe-a-dp-1:
>     - shard-apl:          NOTRUN -> [TIMEOUT][41] ([i915#7173])
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl1/igt@kms_content_protection@lic@pipe-a-dp-1.html
> 
>   * igt@kms_content_protection@mei_interface:
>     - shard-tglb:         NOTRUN -> [SKIP][42] ([i915#7118])
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb2/igt@kms_content_protection@mei_interface.html
>     - shard-iclb:         NOTRUN -> [SKIP][43] ([i915#7118])
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_content_protection@mei_interface.html
> 
>   * igt@kms_cursor_crc@cursor-offscreen-512x170:
>     - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#109279] / [i915#3359])
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_cursor_crc@cursor-offscreen-512x170.html
>     - shard-tglb:         NOTRUN -> [SKIP][45] ([fdo#109279] / [i915#3359])
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_cursor_crc@cursor-offscreen-512x170.html
> 
>   * igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1:
>     - shard-apl:          [PASS][46] -> [DMESG-WARN][47] ([i915#180])
>    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
> 
>   * igt@kms_cursor_legacy@flip-vs-cursor@toggle:
>     - shard-iclb:         [PASS][48] -> [FAIL][49] ([i915#2346]) +2 similar issues
>    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
> 
>   * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
>     - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#1769] / [i915#3555])
>    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
> 
>   * igt@kms_flip@plain-flip-ts-check@a-edp1:
>     - shard-iclb:         [PASS][51] -> [DMESG-WARN][52] ([i915#7507])
>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@kms_flip@plain-flip-ts-check@a-edp1.html
>    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_flip@plain-flip-ts-check@a-edp1.html
> 
>   * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
>     - shard-iclb:         NOTRUN -> [SKIP][53] ([i915#2587] / [i915#2672]) +4 similar issues
>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
> 
>   * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
>     - shard-iclb:         NOTRUN -> [SKIP][54] ([i915#2672]) +8 similar issues
>    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
> 
>   * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
>     - shard-iclb:         NOTRUN -> [SKIP][55] ([i915#2672] / [i915#3555])
>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt:
>     - shard-iclb:         [PASS][56] -> [FAIL][57] ([i915#2546])
>    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
>    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
>     - shard-tglb:         NOTRUN -> [SKIP][58] ([i915#6497]) +2 similar issues
>    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
> 
>   * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render:
>     - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#109280] / [fdo#111825]) +7 similar issues
>    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render.html
> 
>   * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
>     - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109280]) +6 similar issues
>    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
> 
>   * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1:
>     - shard-apl:          NOTRUN -> [FAIL][61] ([i915#4573]) +2 similar issues
>    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl6/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1.html
> 
>   * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
>     - shard-iclb:         [PASS][62] -> [SKIP][63] ([i915#5176]) +2 similar issues
>    [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
>    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
> 
>   * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
>     - shard-iclb:         [PASS][64] -> [SKIP][65] ([i915#5235]) +2 similar issues
>    [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
>    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
> 
>   * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
>     - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#2920])
>    [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
>     - shard-iclb:         NOTRUN -> [SKIP][67] ([fdo#111068] / [i915#658])
>    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
>     - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#658])
>    [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> 
>   * igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1:
>     - shard-iclb:         NOTRUN -> [FAIL][69] ([i915#5939]) +2 similar issues
>    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1.html
> 
>   * igt@kms_psr@psr2_sprite_mmap_gtt:
>     - shard-iclb:         [PASS][70] -> [SKIP][71] ([fdo#109441]) +2 similar issues
>    [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
>    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
> 
>   * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
>     - shard-iclb:         [PASS][72] -> [SKIP][73] ([i915#5519])
>    [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
>    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> 
>   * igt@kms_vblank@pipe-a-wait-busy:
>     - shard-iclb:         NOTRUN -> [DMESG-WARN][74] ([i915#7507])
>    [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_vblank@pipe-a-wait-busy.html
> 
>   * igt@perf@gen12-oa-tlb-invalidate:
>     - shard-iclb:         NOTRUN -> [SKIP][75] ([fdo#109289])
>    [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@perf@gen12-oa-tlb-invalidate.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_exec_balancer@parallel:
>     - shard-iclb:         [SKIP][76] ([i915#4525]) -> [PASS][77] +2 similar issues
>    [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@gem_exec_balancer@parallel.html
>    [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@gem_exec_balancer@parallel.html
> 
>   * igt@i915_pm_dc@dc6-psr:
>     - shard-iclb:         [FAIL][78] ([i915#3989] / [i915#454]) -> [PASS][79]
>    [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
>    [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
> 
>   * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
>     - shard-apl:          [DMESG-WARN][80] ([i915#180]) -> [PASS][81]
>    [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
>    [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> 
>   * igt@kms_psr@psr2_sprite_plane_onoff:
>     - shard-iclb:         [SKIP][82] ([fdo#109441]) -> [PASS][83] +2 similar issues
>    [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb3/igt@kms_psr@psr2_sprite_plane_onoff.html
>    [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
> 
>   * igt@kms_vblank@pipe-b-wait-idle-hang:
>     - shard-apl:          [SKIP][84] ([fdo#109271]) -> [PASS][85]
>    [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl8/igt@kms_vblank@pipe-b-wait-idle-hang.html
>    [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@kms_vblank@pipe-b-wait-idle-hang.html
> 
>   
> #### Warnings ####
> 
>   * igt@gem_exec_balancer@parallel-ordering:
>     - shard-iclb:         [SKIP][86] ([i915#4525]) -> [FAIL][87] ([i915#6117])
>    [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
>    [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
> 
>   * igt@i915_pm_dc@dc3co-vpb-simulation:
>     - shard-iclb:         [SKIP][88] ([i915#658]) -> [SKIP][89] ([i915#588])
>    [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
>    [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
> 
>   * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
>     - shard-iclb:         [SKIP][90] ([i915#2920]) -> [SKIP][91] ([i915#658])
>    [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
>    [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
> 
>   * igt@kms_psr2_sf@plane-move-sf-dmg-area:
>     - shard-iclb:         [SKIP][92] ([i915#2920]) -> [SKIP][93] ([fdo#111068] / [i915#658])
>    [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
>    [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
> 
>   * igt@runner@aborted:
>     - shard-apl:          ([FAIL][94], [FAIL][95], [FAIL][96]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][97], [FAIL][98], [FAIL][99]) ([i915#3002] / [i915#4312])
>    [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@runner@aborted.html
>    [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl8/igt@runner@aborted.html
>    [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl7/igt@runner@aborted.html
>    [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@runner@aborted.html
>    [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl1/igt@runner@aborted.html
>    [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@runner@aborted.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
>   [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
>   [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
>   [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
>   [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
>   [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
>   [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
>   [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
>   [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
>   [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
>   [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
>   [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
>   [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
>   [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
>   [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
>   [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
>   [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
>   [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
>   [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
>   [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
>   [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
>   [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
>   [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
>   [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
>   [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
>   [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
>   [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
>   [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
>   [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
>   [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
>   [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
>   [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
>   [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
>   [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
>   [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
>   [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
>   [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
>   [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
>   [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
>   [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
>   [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
>   [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
>   [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
>   [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
>   [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
>   [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
>   [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
>   [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
>   [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
>   [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
>   [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
>   [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
>   [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
>   [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
>   [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
>   [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
>   [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
>   [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
>   [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
>   [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
>   [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
>   [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
>   [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
>   [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
>   [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
>   [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
>   [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
>   [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
>   [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
>   [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
>   [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
>   [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
>   [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
>   [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
>   [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
>   [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
>   [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
>   [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
>   [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
>   [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
>   [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
>   [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
>   [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
>   [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
>   [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
>   [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
>   [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
>   [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
>   [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
>   [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
>   [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
>   [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
>   [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
>   [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
>   [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
>   [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
>   [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
>   [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
>   [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
>   [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
>   [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
>   [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
>   [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
>   [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
>   [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
>   [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
>   [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
>   [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
>   [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
>   [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
>   [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
>   [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
>   [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
>   [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
>   [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
>   [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
>   [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
>   [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
>   [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
>   [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
>   [i915#4765]: https://gitlab.freedesktop.org/drm/intel/issues/4765
>   [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
>   [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
>   [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
>   [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
>   [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
>   [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
>   [i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
>   [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
>   [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
>   [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
>   [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
>   [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
>   [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
>   [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
>   [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
>   [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
>   [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
>   [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
>   [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
>   [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
>   [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
>   [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
>   [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
>   [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
>   [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
>   [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
>   [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
>   [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
>   [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
>   [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
>   [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
>   [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
>   [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
>   [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
>   [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
>   [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
>   [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
>   [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
>   [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
>   [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
>   [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
>   [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
>   [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
>   [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
>   [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
>   [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
>   [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
>   [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
>   [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
>   [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
>   [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
>   [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
>   [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
>   [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
>   [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
>   [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
>   [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
>   [i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
>   [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
>   [i915#7507]: https://gitlab.freedesktop.org/drm/intel/issues/7507
>   [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
>   [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
>   [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * IGT: IGT_7083 -> IGTPW_8200
>   * Piglit: piglit_4509 -> None
> 
>   CI-20190529: 20190529
>   CI_DRM_12471: 7f8dc69dce0e934751fe31c01a6b6baa0c65bf23 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGTPW_8200: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html
>   IGT_7083: c001793d5f22deb01918b6ba52af829794582df1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html

Re: [igt-dev] ✗ Fi.CI.IGT: failure for Remove libdrm remnants in i915 code (rev4)

[Zbigniew Kempczyński]

On Wed, Dec 14, 2022 at 10:21:48AM +0200, Petri Latvala wrote:
> On Tue, Dec 06, 2022 at 10:35:34AM +0000, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: Remove libdrm remnants in i915 code (rev4)
> > URL   : https://patchwork.freedesktop.org/series/111200/
> > State : failure
> > 
> > == Summary ==
> > 
> > CI Bug Log - changes from CI_DRM_12471_full -> IGTPW_8200_full
> > ====================================================
> > 
> > Summary
> > -------
> > 
> >   **FAILURE**
> > 
> >   Serious unknown changes coming with IGTPW_8200_full absolutely need to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the changes
> >   introduced in IGTPW_8200_full, please notify your bug team to allow them
> >   to document this new failure mode, which will reduce false positives in CI.
> > 
> >   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html
> > 
> > Participating hosts (9 -> 8)
> > ------------------------------
> > 
> >   Additional (2): shard-rkl shard-dg1 
> >   Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 
> > 
> > Possible new issues
> > -------------------
> > 
> >   Here are the unknown changes that may have been introduced in IGTPW_8200_full:
> > 
> > ### IGT changes ###
> > 
> > #### Possible regressions ####
> > 
> >   * igt@gem_caching@read-writes:
> >     - shard-apl:          NOTRUN -> [INCOMPLETE][1]
> >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@gem_caching@read-writes.html
> > 
> >   * igt@gem_partial_pwrite_pread@writes-after-reads-display:
> >     - shard-apl:          [PASS][2] -> [INCOMPLETE][3]
> >    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
> >    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
> 
> Zbigniew, how confident are you that these are not caused by the
> changes?

gem_partial_pwrite_pread is using intel-bb, which wasn't touched in the series.
I don't think this series is related to regressions above so I'm quite confident
there's another reason of this.

--
Zbigniew

> 
> 
> -- 
> Petri Latvala
> 
> 
> 
> > 
> >   
> > Known issues
> > ------------
> > 
> >   Here are the changes found in IGTPW_8200_full that come from known issues:
> > 
> > ### IGT changes ###
> > 
> > #### Issues hit ####
> > 
> >   * igt@gem_ctx_persistence@many-contexts:
> >     - shard-tglb:         NOTRUN -> [FAIL][4] ([i915#2410])
> >    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_ctx_persistence@many-contexts.html
> > 
> >   * igt@gem_exec_balancer@parallel-keep-in-fence:
> >     - shard-iclb:         [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue
> >    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
> >    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html
> > 
> >   * igt@gem_exec_fair@basic-pace-share@rcs0:
> >     - shard-tglb:         [PASS][7] -> [FAIL][8] ([i915#2842])
> >    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
> >    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
> > 
> >   * igt@gem_exec_fair@basic-pace-solo@rcs0:
> >     - shard-iclb:         NOTRUN -> [FAIL][9] ([i915#2842]) +1 similar issue
> >    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> >     - shard-tglb:         NOTRUN -> [FAIL][10] ([i915#2842])
> >    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> > 
> >   * igt@gem_lmem_swapping@heavy-verify-random:
> >     - shard-apl:          NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +2 similar issues
> >    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@gem_lmem_swapping@heavy-verify-random.html
> > 
> >   * igt@gem_lmem_swapping@parallel-random-engines:
> >     - shard-iclb:         NOTRUN -> [SKIP][12] ([i915#4613]) +1 similar issue
> >    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_lmem_swapping@parallel-random-engines.html
> >     - shard-tglb:         NOTRUN -> [SKIP][13] ([i915#4613]) +1 similar issue
> >    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_lmem_swapping@parallel-random-engines.html
> > 
> >   * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
> >     - shard-iclb:         NOTRUN -> [SKIP][14] ([i915#768])
> >    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html
> > 
> >   * igt@gem_softpin@evict-single-offset:
> >     - shard-iclb:         [PASS][15] -> [FAIL][16] ([i915#4171])
> >    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@gem_softpin@evict-single-offset.html
> >    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gem_softpin@evict-single-offset.html
> > 
> >   * igt@gem_vm_create@invalid-create:
> >     - shard-snb:          NOTRUN -> [SKIP][17] ([fdo#109271]) +65 similar issues
> >    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb7/igt@gem_vm_create@invalid-create.html
> > 
> >   * igt@gen9_exec_parse@bb-chained:
> >     - shard-tglb:         NOTRUN -> [SKIP][18] ([i915#2527] / [i915#2856])
> >    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@gen9_exec_parse@bb-chained.html
> >     - shard-iclb:         NOTRUN -> [SKIP][19] ([i915#2856])
> >    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gen9_exec_parse@bb-chained.html
> > 
> >   * igt@i915_module_load@reload:
> >     - shard-snb:          [PASS][20] -> [DMESG-WARN][21] ([i915#4528])
> >    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-snb4/igt@i915_module_load@reload.html
> >    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb4/igt@i915_module_load@reload.html
> > 
> >   * igt@i915_pm_dc@dc9-dpms:
> >     - shard-tglb:         NOTRUN -> [SKIP][22] ([i915#4281])
> >    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@i915_pm_dc@dc9-dpms.html
> > 
> >   * igt@i915_query@test-query-geometry-subslices:
> >     - shard-iclb:         NOTRUN -> [SKIP][23] ([i915#5723])
> >    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@i915_query@test-query-geometry-subslices.html
> >     - shard-tglb:         NOTRUN -> [SKIP][24] ([i915#5723])
> >    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@i915_query@test-query-geometry-subslices.html
> > 
> >   * igt@kms_atomic@atomic_plane_damage:
> >     - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#4765])
> >    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_atomic@atomic_plane_damage.html
> > 
> >   * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
> >     - shard-iclb:         NOTRUN -> [SKIP][26] ([i915#404])
> >    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
> >     - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#404])
> >    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
> > 
> >   * igt@kms_big_fb@linear-32bpp-rotate-270:
> >     - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271]) +44 similar issues
> >    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@kms_big_fb@linear-32bpp-rotate-270.html
> >     - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#111614]) +1 similar issue
> >    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb7/igt@kms_big_fb@linear-32bpp-rotate-270.html
> > 
> >   * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
> >     - shard-iclb:         NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614]) +1 similar issue
> >    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
> > 
> >   * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs:
> >     - shard-iclb:         NOTRUN -> [SKIP][31] ([fdo#109278]) +6 similar issues
> >    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs.html
> > 
> >   * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs:
> >     - shard-tglb:         NOTRUN -> [SKIP][32] ([i915#3689] / [i915#6095]) +1 similar issue
> >    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb2/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs.html
> > 
> >   * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
> >     - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886])
> >    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
> > 
> >   * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
> >     - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#111615] / [i915#3689])
> >    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html
> > 
> >   * igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
> >     - shard-tglb:         NOTRUN -> [SKIP][35] ([i915#6095])
> >    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html
> > 
> >   * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
> >     - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3689])
> >    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb7/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
> > 
> >   * igt@kms_chamelium@dp-crc-fast:
> >     - shard-iclb:         NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827]) +2 similar issues
> >    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_chamelium@dp-crc-fast.html
> > 
> >   * igt@kms_chamelium@dp-frame-dump:
> >     - shard-apl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +4 similar issues
> >    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_chamelium@dp-frame-dump.html
> >     - shard-snb:          NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +2 similar issues
> >    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb4/igt@kms_chamelium@dp-frame-dump.html
> > 
> >   * igt@kms_chamelium@hdmi-audio-edid:
> >     - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +2 similar issues
> >    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@kms_chamelium@hdmi-audio-edid.html
> > 
> >   * igt@kms_content_protection@lic@pipe-a-dp-1:
> >     - shard-apl:          NOTRUN -> [TIMEOUT][41] ([i915#7173])
> >    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl1/igt@kms_content_protection@lic@pipe-a-dp-1.html
> > 
> >   * igt@kms_content_protection@mei_interface:
> >     - shard-tglb:         NOTRUN -> [SKIP][42] ([i915#7118])
> >    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb2/igt@kms_content_protection@mei_interface.html
> >     - shard-iclb:         NOTRUN -> [SKIP][43] ([i915#7118])
> >    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_content_protection@mei_interface.html
> > 
> >   * igt@kms_cursor_crc@cursor-offscreen-512x170:
> >     - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#109279] / [i915#3359])
> >    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_cursor_crc@cursor-offscreen-512x170.html
> >     - shard-tglb:         NOTRUN -> [SKIP][45] ([fdo#109279] / [i915#3359])
> >    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_cursor_crc@cursor-offscreen-512x170.html
> > 
> >   * igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1:
> >     - shard-apl:          [PASS][46] -> [DMESG-WARN][47] ([i915#180])
> >    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
> >    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
> > 
> >   * igt@kms_cursor_legacy@flip-vs-cursor@toggle:
> >     - shard-iclb:         [PASS][48] -> [FAIL][49] ([i915#2346]) +2 similar issues
> >    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
> >    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
> > 
> >   * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
> >     - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#1769] / [i915#3555])
> >    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
> > 
> >   * igt@kms_flip@plain-flip-ts-check@a-edp1:
> >     - shard-iclb:         [PASS][51] -> [DMESG-WARN][52] ([i915#7507])
> >    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@kms_flip@plain-flip-ts-check@a-edp1.html
> >    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_flip@plain-flip-ts-check@a-edp1.html
> > 
> >   * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
> >     - shard-iclb:         NOTRUN -> [SKIP][53] ([i915#2587] / [i915#2672]) +4 similar issues
> >    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
> > 
> >   * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
> >     - shard-iclb:         NOTRUN -> [SKIP][54] ([i915#2672]) +8 similar issues
> >    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
> > 
> >   * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
> >     - shard-iclb:         NOTRUN -> [SKIP][55] ([i915#2672] / [i915#3555])
> >    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
> > 
> >   * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt:
> >     - shard-iclb:         [PASS][56] -> [FAIL][57] ([i915#2546])
> >    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
> >    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
> > 
> >   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
> >     - shard-tglb:         NOTRUN -> [SKIP][58] ([i915#6497]) +2 similar issues
> >    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
> > 
> >   * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render:
> >     - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#109280] / [fdo#111825]) +7 similar issues
> >    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render.html
> > 
> >   * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
> >     - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109280]) +6 similar issues
> >    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
> > 
> >   * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1:
> >     - shard-apl:          NOTRUN -> [FAIL][61] ([i915#4573]) +2 similar issues
> >    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl6/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1.html
> > 
> >   * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
> >     - shard-iclb:         [PASS][62] -> [SKIP][63] ([i915#5176]) +2 similar issues
> >    [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
> >    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
> > 
> >   * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
> >     - shard-iclb:         [PASS][64] -> [SKIP][65] ([i915#5235]) +2 similar issues
> >    [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
> >    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
> > 
> >   * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
> >     - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#2920])
> >    [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> >     - shard-iclb:         NOTRUN -> [SKIP][67] ([fdo#111068] / [i915#658])
> >    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> >     - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#658])
> >    [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> > 
> >   * igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1:
> >     - shard-iclb:         NOTRUN -> [FAIL][69] ([i915#5939]) +2 similar issues
> >    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1.html
> > 
> >   * igt@kms_psr@psr2_sprite_mmap_gtt:
> >     - shard-iclb:         [PASS][70] -> [SKIP][71] ([fdo#109441]) +2 similar issues
> >    [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
> >    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
> > 
> >   * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
> >     - shard-iclb:         [PASS][72] -> [SKIP][73] ([i915#5519])
> >    [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> >    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> > 
> >   * igt@kms_vblank@pipe-a-wait-busy:
> >     - shard-iclb:         NOTRUN -> [DMESG-WARN][74] ([i915#7507])
> >    [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_vblank@pipe-a-wait-busy.html
> > 
> >   * igt@perf@gen12-oa-tlb-invalidate:
> >     - shard-iclb:         NOTRUN -> [SKIP][75] ([fdo#109289])
> >    [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@perf@gen12-oa-tlb-invalidate.html
> > 
> >   
> > #### Possible fixes ####
> > 
> >   * igt@gem_exec_balancer@parallel:
> >     - shard-iclb:         [SKIP][76] ([i915#4525]) -> [PASS][77] +2 similar issues
> >    [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@gem_exec_balancer@parallel.html
> >    [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@gem_exec_balancer@parallel.html
> > 
> >   * igt@i915_pm_dc@dc6-psr:
> >     - shard-iclb:         [FAIL][78] ([i915#3989] / [i915#454]) -> [PASS][79]
> >    [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
> >    [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
> > 
> >   * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> >     - shard-apl:          [DMESG-WARN][80] ([i915#180]) -> [PASS][81]
> >    [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> >    [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> > 
> >   * igt@kms_psr@psr2_sprite_plane_onoff:
> >     - shard-iclb:         [SKIP][82] ([fdo#109441]) -> [PASS][83] +2 similar issues
> >    [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb3/igt@kms_psr@psr2_sprite_plane_onoff.html
> >    [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
> > 
> >   * igt@kms_vblank@pipe-b-wait-idle-hang:
> >     - shard-apl:          [SKIP][84] ([fdo#109271]) -> [PASS][85]
> >    [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl8/igt@kms_vblank@pipe-b-wait-idle-hang.html
> >    [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@kms_vblank@pipe-b-wait-idle-hang.html
> > 
> >   
> > #### Warnings ####
> > 
> >   * igt@gem_exec_balancer@parallel-ordering:
> >     - shard-iclb:         [SKIP][86] ([i915#4525]) -> [FAIL][87] ([i915#6117])
> >    [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
> >    [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
> > 
> >   * igt@i915_pm_dc@dc3co-vpb-simulation:
> >     - shard-iclb:         [SKIP][88] ([i915#658]) -> [SKIP][89] ([i915#588])
> >    [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
> >    [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
> > 
> >   * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
> >     - shard-iclb:         [SKIP][90] ([i915#2920]) -> [SKIP][91] ([i915#658])
> >    [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
> >    [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
> > 
> >   * igt@kms_psr2_sf@plane-move-sf-dmg-area:
> >     - shard-iclb:         [SKIP][92] ([i915#2920]) -> [SKIP][93] ([fdo#111068] / [i915#658])
> >    [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
> >    [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
> > 
> >   * igt@runner@aborted:
> >     - shard-apl:          ([FAIL][94], [FAIL][95], [FAIL][96]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][97], [FAIL][98], [FAIL][99]) ([i915#3002] / [i915#4312])
> >    [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@runner@aborted.html
> >    [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl8/igt@runner@aborted.html
> >    [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl7/igt@runner@aborted.html
> >    [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@runner@aborted.html
> >    [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl1/igt@runner@aborted.html
> >    [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@runner@aborted.html
> > 
> >   
> >   {name}: This element is suppressed. This means it is ignored when computing
> >           the status of the difference (SUCCESS, WARNING, or FAILURE).
> > 
> >   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> >   [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
> >   [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
> >   [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
> >   [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
> >   [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
> >   [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> >   [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> >   [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
> >   [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
> >   [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
> >   [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
> >   [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
> >   [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
> >   [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
> >   [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
> >   [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
> >   [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
> >   [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
> >   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> >   [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
> >   [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
> >   [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
> >   [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
> >   [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> >   [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
> >   [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
> >   [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
> >   [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
> >   [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> >   [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
> >   [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
> >   [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
> >   [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
> >   [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
> >   [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
> >   [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
> >   [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
> >   [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> >   [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
> >   [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
> >   [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
> >   [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
> >   [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
> >   [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
> >   [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> >   [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
> >   [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
> >   [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
> >   [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
> >   [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
> >   [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
> >   [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
> >   [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
> >   [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
> >   [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
> >   [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
> >   [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
> >   [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
> >   [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
> >   [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
> >   [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
> >   [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
> >   [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
> >   [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
> >   [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
> >   [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
> >   [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
> >   [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
> >   [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
> >   [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
> >   [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
> >   [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
> >   [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
> >   [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
> >   [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
> >   [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
> >   [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
> >   [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
> >   [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
> >   [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
> >   [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> >   [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
> >   [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
> >   [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
> >   [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
> >   [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
> >   [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
> >   [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
> >   [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
> >   [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
> >   [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> >   [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
> >   [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
> >   [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
> >   [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
> >   [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
> >   [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
> >   [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
> >   [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
> >   [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
> >   [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
> >   [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
> >   [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
> >   [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> >   [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
> >   [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
> >   [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
> >   [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
> >   [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
> >   [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
> >   [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
> >   [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> >   [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
> >   [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
> >   [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
> >   [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> >   [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
> >   [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
> >   [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> >   [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
> >   [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
> >   [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> >   [i915#4765]: https://gitlab.freedesktop.org/drm/intel/issues/4765
> >   [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
> >   [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
> >   [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
> >   [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
> >   [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
> >   [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
> >   [i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
> >   [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
> >   [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
> >   [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
> >   [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
> >   [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
> >   [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
> >   [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
> >   [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
> >   [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> >   [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> >   [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> >   [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> >   [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> >   [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> >   [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> >   [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
> >   [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> >   [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
> >   [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
> >   [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
> >   [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
> >   [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
> >   [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
> >   [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
> >   [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> >   [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
> >   [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
> >   [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
> >   [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
> >   [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
> >   [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
> >   [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
> >   [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
> >   [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
> >   [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
> >   [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
> >   [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
> >   [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
> >   [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
> >   [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
> >   [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> >   [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> >   [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
> >   [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
> >   [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
> >   [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
> >   [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
> >   [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
> >   [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
> >   [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
> >   [i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
> >   [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
> >   [i915#7507]: https://gitlab.freedesktop.org/drm/intel/issues/7507
> >   [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
> >   [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
> >   [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
> > 
> > 
> > Build changes
> > -------------
> > 
> >   * CI: CI-20190529 -> None
> >   * IGT: IGT_7083 -> IGTPW_8200
> >   * Piglit: piglit_4509 -> None
> > 
> >   CI-20190529: 20190529
> >   CI_DRM_12471: 7f8dc69dce0e934751fe31c01a6b6baa0c65bf23 @ git://anongit.freedesktop.org/gfx-ci/linux
> >   IGTPW_8200: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html
> >   IGT_7083: c001793d5f22deb01918b6ba52af829794582df1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> >   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> > 
> > == Logs ==
> > 
> > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html

Re: [igt-dev] ✗ Fi.CI.IGT: failure for Remove libdrm remnants in i915 code (rev4)

[Petri Latvala]

On Wed, Dec 14, 2022 at 01:18:23PM +0100, Zbigniew Kempczyński wrote:
> On Wed, Dec 14, 2022 at 10:21:48AM +0200, Petri Latvala wrote:
> > On Tue, Dec 06, 2022 at 10:35:34AM +0000, Patchwork wrote:
> > > == Series Details ==
> > > 
> > > Series: Remove libdrm remnants in i915 code (rev4)
> > > URL   : https://patchwork.freedesktop.org/series/111200/
> > > State : failure
> > > 
> > > == Summary ==
> > > 
> > > CI Bug Log - changes from CI_DRM_12471_full -> IGTPW_8200_full
> > > ====================================================
> > > 
> > > Summary
> > > -------
> > > 
> > >   **FAILURE**
> > > 
> > >   Serious unknown changes coming with IGTPW_8200_full absolutely need to be
> > >   verified manually.
> > >   
> > >   If you think the reported changes have nothing to do with the changes
> > >   introduced in IGTPW_8200_full, please notify your bug team to allow them
> > >   to document this new failure mode, which will reduce false positives in CI.
> > > 
> > >   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html
> > > 
> > > Participating hosts (9 -> 8)
> > > ------------------------------
> > > 
> > >   Additional (2): shard-rkl shard-dg1 
> > >   Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 
> > > 
> > > Possible new issues
> > > -------------------
> > > 
> > >   Here are the unknown changes that may have been introduced in IGTPW_8200_full:
> > > 
> > > ### IGT changes ###
> > > 
> > > #### Possible regressions ####
> > > 
> > >   * igt@gem_caching@read-writes:
> > >     - shard-apl:          NOTRUN -> [INCOMPLETE][1]
> > >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@gem_caching@read-writes.html
> > > 
> > >   * igt@gem_partial_pwrite_pread@writes-after-reads-display:
> > >     - shard-apl:          [PASS][2] -> [INCOMPLETE][3]
> > >    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
> > >    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
> > 
> > Zbigniew, how confident are you that these are not caused by the
> > changes?
> 
> gem_partial_pwrite_pread is using intel-bb, which wasn't touched in the series.
> I don't think this series is related to regressions above so I'm quite confident
> there's another reason of this.


Alright then.

Series is
Acked-by: Petri Latvala <petri.latvala@intel.com>




> 
> --
> Zbigniew
> 
> > 
> > 
> > -- 
> > Petri Latvala
> > 
> > 
> > 
> > > 
> > >   
> > > Known issues
> > > ------------
> > > 
> > >   Here are the changes found in IGTPW_8200_full that come from known issues:
> > > 
> > > ### IGT changes ###
> > > 
> > > #### Issues hit ####
> > > 
> > >   * igt@gem_ctx_persistence@many-contexts:
> > >     - shard-tglb:         NOTRUN -> [FAIL][4] ([i915#2410])
> > >    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_ctx_persistence@many-contexts.html
> > > 
> > >   * igt@gem_exec_balancer@parallel-keep-in-fence:
> > >     - shard-iclb:         [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue
> > >    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
> > >    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html
> > > 
> > >   * igt@gem_exec_fair@basic-pace-share@rcs0:
> > >     - shard-tglb:         [PASS][7] -> [FAIL][8] ([i915#2842])
> > >    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
> > >    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
> > > 
> > >   * igt@gem_exec_fair@basic-pace-solo@rcs0:
> > >     - shard-iclb:         NOTRUN -> [FAIL][9] ([i915#2842]) +1 similar issue
> > >    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> > >     - shard-tglb:         NOTRUN -> [FAIL][10] ([i915#2842])
> > >    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> > > 
> > >   * igt@gem_lmem_swapping@heavy-verify-random:
> > >     - shard-apl:          NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +2 similar issues
> > >    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@gem_lmem_swapping@heavy-verify-random.html
> > > 
> > >   * igt@gem_lmem_swapping@parallel-random-engines:
> > >     - shard-iclb:         NOTRUN -> [SKIP][12] ([i915#4613]) +1 similar issue
> > >    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_lmem_swapping@parallel-random-engines.html
> > >     - shard-tglb:         NOTRUN -> [SKIP][13] ([i915#4613]) +1 similar issue
> > >    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_lmem_swapping@parallel-random-engines.html
> > > 
> > >   * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
> > >     - shard-iclb:         NOTRUN -> [SKIP][14] ([i915#768])
> > >    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html
> > > 
> > >   * igt@gem_softpin@evict-single-offset:
> > >     - shard-iclb:         [PASS][15] -> [FAIL][16] ([i915#4171])
> > >    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@gem_softpin@evict-single-offset.html
> > >    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gem_softpin@evict-single-offset.html
> > > 
> > >   * igt@gem_vm_create@invalid-create:
> > >     - shard-snb:          NOTRUN -> [SKIP][17] ([fdo#109271]) +65 similar issues
> > >    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb7/igt@gem_vm_create@invalid-create.html
> > > 
> > >   * igt@gen9_exec_parse@bb-chained:
> > >     - shard-tglb:         NOTRUN -> [SKIP][18] ([i915#2527] / [i915#2856])
> > >    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@gen9_exec_parse@bb-chained.html
> > >     - shard-iclb:         NOTRUN -> [SKIP][19] ([i915#2856])
> > >    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gen9_exec_parse@bb-chained.html
> > > 
> > >   * igt@i915_module_load@reload:
> > >     - shard-snb:          [PASS][20] -> [DMESG-WARN][21] ([i915#4528])
> > >    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-snb4/igt@i915_module_load@reload.html
> > >    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb4/igt@i915_module_load@reload.html
> > > 
> > >   * igt@i915_pm_dc@dc9-dpms:
> > >     - shard-tglb:         NOTRUN -> [SKIP][22] ([i915#4281])
> > >    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@i915_pm_dc@dc9-dpms.html
> > > 
> > >   * igt@i915_query@test-query-geometry-subslices:
> > >     - shard-iclb:         NOTRUN -> [SKIP][23] ([i915#5723])
> > >    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@i915_query@test-query-geometry-subslices.html
> > >     - shard-tglb:         NOTRUN -> [SKIP][24] ([i915#5723])
> > >    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@i915_query@test-query-geometry-subslices.html
> > > 
> > >   * igt@kms_atomic@atomic_plane_damage:
> > >     - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#4765])
> > >    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_atomic@atomic_plane_damage.html
> > > 
> > >   * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
> > >     - shard-iclb:         NOTRUN -> [SKIP][26] ([i915#404])
> > >    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
> > >     - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#404])
> > >    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
> > > 
> > >   * igt@kms_big_fb@linear-32bpp-rotate-270:
> > >     - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271]) +44 similar issues
> > >    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@kms_big_fb@linear-32bpp-rotate-270.html
> > >     - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#111614]) +1 similar issue
> > >    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb7/igt@kms_big_fb@linear-32bpp-rotate-270.html
> > > 
> > >   * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
> > >     - shard-iclb:         NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614]) +1 similar issue
> > >    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
> > > 
> > >   * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs:
> > >     - shard-iclb:         NOTRUN -> [SKIP][31] ([fdo#109278]) +6 similar issues
> > >    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs.html
> > > 
> > >   * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs:
> > >     - shard-tglb:         NOTRUN -> [SKIP][32] ([i915#3689] / [i915#6095]) +1 similar issue
> > >    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb2/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs.html
> > > 
> > >   * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
> > >     - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886])
> > >    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
> > > 
> > >   * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
> > >     - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#111615] / [i915#3689])
> > >    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html
> > > 
> > >   * igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
> > >     - shard-tglb:         NOTRUN -> [SKIP][35] ([i915#6095])
> > >    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html
> > > 
> > >   * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
> > >     - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3689])
> > >    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb7/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
> > > 
> > >   * igt@kms_chamelium@dp-crc-fast:
> > >     - shard-iclb:         NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827]) +2 similar issues
> > >    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_chamelium@dp-crc-fast.html
> > > 
> > >   * igt@kms_chamelium@dp-frame-dump:
> > >     - shard-apl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +4 similar issues
> > >    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_chamelium@dp-frame-dump.html
> > >     - shard-snb:          NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +2 similar issues
> > >    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb4/igt@kms_chamelium@dp-frame-dump.html
> > > 
> > >   * igt@kms_chamelium@hdmi-audio-edid:
> > >     - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +2 similar issues
> > >    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@kms_chamelium@hdmi-audio-edid.html
> > > 
> > >   * igt@kms_content_protection@lic@pipe-a-dp-1:
> > >     - shard-apl:          NOTRUN -> [TIMEOUT][41] ([i915#7173])
> > >    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl1/igt@kms_content_protection@lic@pipe-a-dp-1.html
> > > 
> > >   * igt@kms_content_protection@mei_interface:
> > >     - shard-tglb:         NOTRUN -> [SKIP][42] ([i915#7118])
> > >    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb2/igt@kms_content_protection@mei_interface.html
> > >     - shard-iclb:         NOTRUN -> [SKIP][43] ([i915#7118])
> > >    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_content_protection@mei_interface.html
> > > 
> > >   * igt@kms_cursor_crc@cursor-offscreen-512x170:
> > >     - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#109279] / [i915#3359])
> > >    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_cursor_crc@cursor-offscreen-512x170.html
> > >     - shard-tglb:         NOTRUN -> [SKIP][45] ([fdo#109279] / [i915#3359])
> > >    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_cursor_crc@cursor-offscreen-512x170.html
> > > 
> > >   * igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1:
> > >     - shard-apl:          [PASS][46] -> [DMESG-WARN][47] ([i915#180])
> > >    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
> > >    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
> > > 
> > >   * igt@kms_cursor_legacy@flip-vs-cursor@toggle:
> > >     - shard-iclb:         [PASS][48] -> [FAIL][49] ([i915#2346]) +2 similar issues
> > >    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
> > >    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
> > > 
> > >   * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
> > >     - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#1769] / [i915#3555])
> > >    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
> > > 
> > >   * igt@kms_flip@plain-flip-ts-check@a-edp1:
> > >     - shard-iclb:         [PASS][51] -> [DMESG-WARN][52] ([i915#7507])
> > >    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@kms_flip@plain-flip-ts-check@a-edp1.html
> > >    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_flip@plain-flip-ts-check@a-edp1.html
> > > 
> > >   * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
> > >     - shard-iclb:         NOTRUN -> [SKIP][53] ([i915#2587] / [i915#2672]) +4 similar issues
> > >    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
> > > 
> > >   * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
> > >     - shard-iclb:         NOTRUN -> [SKIP][54] ([i915#2672]) +8 similar issues
> > >    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
> > > 
> > >   * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
> > >     - shard-iclb:         NOTRUN -> [SKIP][55] ([i915#2672] / [i915#3555])
> > >    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
> > > 
> > >   * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt:
> > >     - shard-iclb:         [PASS][56] -> [FAIL][57] ([i915#2546])
> > >    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
> > >    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
> > > 
> > >   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
> > >     - shard-tglb:         NOTRUN -> [SKIP][58] ([i915#6497]) +2 similar issues
> > >    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
> > > 
> > >   * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render:
> > >     - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#109280] / [fdo#111825]) +7 similar issues
> > >    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render.html
> > > 
> > >   * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
> > >     - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109280]) +6 similar issues
> > >    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
> > > 
> > >   * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1:
> > >     - shard-apl:          NOTRUN -> [FAIL][61] ([i915#4573]) +2 similar issues
> > >    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl6/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1.html
> > > 
> > >   * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
> > >     - shard-iclb:         [PASS][62] -> [SKIP][63] ([i915#5176]) +2 similar issues
> > >    [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
> > >    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
> > > 
> > >   * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
> > >     - shard-iclb:         [PASS][64] -> [SKIP][65] ([i915#5235]) +2 similar issues
> > >    [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
> > >    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
> > > 
> > >   * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
> > >     - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#2920])
> > >    [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> > >     - shard-iclb:         NOTRUN -> [SKIP][67] ([fdo#111068] / [i915#658])
> > >    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> > >     - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#658])
> > >    [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> > > 
> > >   * igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1:
> > >     - shard-iclb:         NOTRUN -> [FAIL][69] ([i915#5939]) +2 similar issues
> > >    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1.html
> > > 
> > >   * igt@kms_psr@psr2_sprite_mmap_gtt:
> > >     - shard-iclb:         [PASS][70] -> [SKIP][71] ([fdo#109441]) +2 similar issues
> > >    [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
> > >    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
> > > 
> > >   * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
> > >     - shard-iclb:         [PASS][72] -> [SKIP][73] ([i915#5519])
> > >    [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> > >    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> > > 
> > >   * igt@kms_vblank@pipe-a-wait-busy:
> > >     - shard-iclb:         NOTRUN -> [DMESG-WARN][74] ([i915#7507])
> > >    [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_vblank@pipe-a-wait-busy.html
> > > 
> > >   * igt@perf@gen12-oa-tlb-invalidate:
> > >     - shard-iclb:         NOTRUN -> [SKIP][75] ([fdo#109289])
> > >    [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@perf@gen12-oa-tlb-invalidate.html
> > > 
> > >   
> > > #### Possible fixes ####
> > > 
> > >   * igt@gem_exec_balancer@parallel:
> > >     - shard-iclb:         [SKIP][76] ([i915#4525]) -> [PASS][77] +2 similar issues
> > >    [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@gem_exec_balancer@parallel.html
> > >    [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@gem_exec_balancer@parallel.html
> > > 
> > >   * igt@i915_pm_dc@dc6-psr:
> > >     - shard-iclb:         [FAIL][78] ([i915#3989] / [i915#454]) -> [PASS][79]
> > >    [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
> > >    [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
> > > 
> > >   * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> > >     - shard-apl:          [DMESG-WARN][80] ([i915#180]) -> [PASS][81]
> > >    [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> > >    [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> > > 
> > >   * igt@kms_psr@psr2_sprite_plane_onoff:
> > >     - shard-iclb:         [SKIP][82] ([fdo#109441]) -> [PASS][83] +2 similar issues
> > >    [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb3/igt@kms_psr@psr2_sprite_plane_onoff.html
> > >    [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
> > > 
> > >   * igt@kms_vblank@pipe-b-wait-idle-hang:
> > >     - shard-apl:          [SKIP][84] ([fdo#109271]) -> [PASS][85]
> > >    [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl8/igt@kms_vblank@pipe-b-wait-idle-hang.html
> > >    [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@kms_vblank@pipe-b-wait-idle-hang.html
> > > 
> > >   
> > > #### Warnings ####
> > > 
> > >   * igt@gem_exec_balancer@parallel-ordering:
> > >     - shard-iclb:         [SKIP][86] ([i915#4525]) -> [FAIL][87] ([i915#6117])
> > >    [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
> > >    [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
> > > 
> > >   * igt@i915_pm_dc@dc3co-vpb-simulation:
> > >     - shard-iclb:         [SKIP][88] ([i915#658]) -> [SKIP][89] ([i915#588])
> > >    [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
> > >    [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
> > > 
> > >   * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
> > >     - shard-iclb:         [SKIP][90] ([i915#2920]) -> [SKIP][91] ([i915#658])
> > >    [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
> > >    [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
> > > 
> > >   * igt@kms_psr2_sf@plane-move-sf-dmg-area:
> > >     - shard-iclb:         [SKIP][92] ([i915#2920]) -> [SKIP][93] ([fdo#111068] / [i915#658])
> > >    [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
> > >    [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
> > > 
> > >   * igt@runner@aborted:
> > >     - shard-apl:          ([FAIL][94], [FAIL][95], [FAIL][96]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][97], [FAIL][98], [FAIL][99]) ([i915#3002] / [i915#4312])
> > >    [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@runner@aborted.html
> > >    [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl8/igt@runner@aborted.html
> > >    [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl7/igt@runner@aborted.html
> > >    [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@runner@aborted.html
> > >    [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl1/igt@runner@aborted.html
> > >    [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@runner@aborted.html
> > > 
> > >   
> > >   {name}: This element is suppressed. This means it is ignored when computing
> > >           the status of the difference (SUCCESS, WARNING, or FAILURE).
> > > 
> > >   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> > >   [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
> > >   [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
> > >   [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
> > >   [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
> > >   [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
> > >   [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> > >   [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> > >   [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
> > >   [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
> > >   [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
> > >   [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
> > >   [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
> > >   [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
> > >   [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
> > >   [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
> > >   [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
> > >   [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
> > >   [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
> > >   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> > >   [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
> > >   [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
> > >   [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
> > >   [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
> > >   [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> > >   [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
> > >   [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
> > >   [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
> > >   [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
> > >   [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> > >   [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
> > >   [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
> > >   [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
> > >   [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
> > >   [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
> > >   [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
> > >   [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
> > >   [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
> > >   [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> > >   [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
> > >   [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
> > >   [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
> > >   [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
> > >   [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
> > >   [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
> > >   [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> > >   [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
> > >   [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
> > >   [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
> > >   [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
> > >   [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
> > >   [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
> > >   [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
> > >   [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
> > >   [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
> > >   [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
> > >   [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
> > >   [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
> > >   [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
> > >   [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
> > >   [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
> > >   [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
> > >   [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
> > >   [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
> > >   [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
> > >   [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
> > >   [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
> > >   [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
> > >   [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
> > >   [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
> > >   [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
> > >   [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
> > >   [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
> > >   [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
> > >   [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
> > >   [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
> > >   [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
> > >   [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
> > >   [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
> > >   [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
> > >   [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
> > >   [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> > >   [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
> > >   [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
> > >   [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
> > >   [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
> > >   [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
> > >   [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
> > >   [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
> > >   [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
> > >   [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
> > >   [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> > >   [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
> > >   [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
> > >   [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
> > >   [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
> > >   [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
> > >   [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
> > >   [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
> > >   [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
> > >   [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
> > >   [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
> > >   [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
> > >   [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
> > >   [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> > >   [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
> > >   [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
> > >   [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
> > >   [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
> > >   [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
> > >   [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
> > >   [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
> > >   [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> > >   [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
> > >   [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
> > >   [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
> > >   [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> > >   [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
> > >   [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
> > >   [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> > >   [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
> > >   [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
> > >   [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> > >   [i915#4765]: https://gitlab.freedesktop.org/drm/intel/issues/4765
> > >   [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
> > >   [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
> > >   [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
> > >   [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
> > >   [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
> > >   [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
> > >   [i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
> > >   [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
> > >   [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
> > >   [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
> > >   [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
> > >   [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
> > >   [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
> > >   [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
> > >   [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
> > >   [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> > >   [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> > >   [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> > >   [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> > >   [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> > >   [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> > >   [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> > >   [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
> > >   [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> > >   [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
> > >   [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
> > >   [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
> > >   [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
> > >   [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
> > >   [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
> > >   [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
> > >   [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> > >   [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
> > >   [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
> > >   [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
> > >   [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
> > >   [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
> > >   [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
> > >   [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
> > >   [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
> > >   [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
> > >   [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
> > >   [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
> > >   [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
> > >   [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
> > >   [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
> > >   [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
> > >   [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> > >   [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> > >   [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
> > >   [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
> > >   [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
> > >   [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
> > >   [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
> > >   [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
> > >   [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
> > >   [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
> > >   [i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
> > >   [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
> > >   [i915#7507]: https://gitlab.freedesktop.org/drm/intel/issues/7507
> > >   [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
> > >   [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
> > >   [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
> > > 
> > > 
> > > Build changes
> > > -------------
> > > 
> > >   * CI: CI-20190529 -> None
> > >   * IGT: IGT_7083 -> IGTPW_8200
> > >   * Piglit: piglit_4509 -> None
> > > 
> > >   CI-20190529: 20190529
> > >   CI_DRM_12471: 7f8dc69dce0e934751fe31c01a6b6baa0c65bf23 @ git://anongit.freedesktop.org/gfx-ci/linux
> > >   IGTPW_8200: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html
> > >   IGT_7083: c001793d5f22deb01918b6ba52af829794582df1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> > >   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> > > 
> > > == Logs ==
> > > 
> > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html

Re: [igt-dev] ✗ Fi.CI.IGT: failure for Remove libdrm remnants in i915 code (rev4)

[Zbigniew Kempczyński]

On Wed, Dec 14, 2022 at 04:01:49PM +0200, Petri Latvala wrote:
> On Wed, Dec 14, 2022 at 01:18:23PM +0100, Zbigniew Kempczyński wrote:
> > On Wed, Dec 14, 2022 at 10:21:48AM +0200, Petri Latvala wrote:
> > > On Tue, Dec 06, 2022 at 10:35:34AM +0000, Patchwork wrote:
> > > > == Series Details ==
> > > > 
> > > > Series: Remove libdrm remnants in i915 code (rev4)
> > > > URL   : https://patchwork.freedesktop.org/series/111200/
> > > > State : failure
> > > > 
> > > > == Summary ==
> > > > 
> > > > CI Bug Log - changes from CI_DRM_12471_full -> IGTPW_8200_full
> > > > ====================================================
> > > > 
> > > > Summary
> > > > -------
> > > > 
> > > >   **FAILURE**
> > > > 
> > > >   Serious unknown changes coming with IGTPW_8200_full absolutely need to be
> > > >   verified manually.
> > > >   
> > > >   If you think the reported changes have nothing to do with the changes
> > > >   introduced in IGTPW_8200_full, please notify your bug team to allow them
> > > >   to document this new failure mode, which will reduce false positives in CI.
> > > > 
> > > >   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html
> > > > 
> > > > Participating hosts (9 -> 8)
> > > > ------------------------------
> > > > 
> > > >   Additional (2): shard-rkl shard-dg1 
> > > >   Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 
> > > > 
> > > > Possible new issues
> > > > -------------------
> > > > 
> > > >   Here are the unknown changes that may have been introduced in IGTPW_8200_full:
> > > > 
> > > > ### IGT changes ###
> > > > 
> > > > #### Possible regressions ####
> > > > 
> > > >   * igt@gem_caching@read-writes:
> > > >     - shard-apl:          NOTRUN -> [INCOMPLETE][1]
> > > >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@gem_caching@read-writes.html
> > > > 
> > > >   * igt@gem_partial_pwrite_pread@writes-after-reads-display:
> > > >     - shard-apl:          [PASS][2] -> [INCOMPLETE][3]
> > > >    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
> > > >    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
> > > 
> > > Zbigniew, how confident are you that these are not caused by the
> > > changes?
> > 
> > gem_partial_pwrite_pread is using intel-bb, which wasn't touched in the series.
> > I don't think this series is related to regressions above so I'm quite confident
> > there's another reason of this.
> 
> 
> Alright then.
> 
> Series is
> Acked-by: Petri Latvala <petri.latvala@intel.com>

Thanks, I will resend and then merge.

--
Zbigniew

> 
> 
> 
> 
> > 
> > --
> > Zbigniew
> > 
> > > 
> > > 
> > > -- 
> > > Petri Latvala
> > > 
> > > 
> > > 
> > > > 
> > > >   
> > > > Known issues
> > > > ------------
> > > > 
> > > >   Here are the changes found in IGTPW_8200_full that come from known issues:
> > > > 
> > > > ### IGT changes ###
> > > > 
> > > > #### Issues hit ####
> > > > 
> > > >   * igt@gem_ctx_persistence@many-contexts:
> > > >     - shard-tglb:         NOTRUN -> [FAIL][4] ([i915#2410])
> > > >    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_ctx_persistence@many-contexts.html
> > > > 
> > > >   * igt@gem_exec_balancer@parallel-keep-in-fence:
> > > >     - shard-iclb:         [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue
> > > >    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
> > > >    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html
> > > > 
> > > >   * igt@gem_exec_fair@basic-pace-share@rcs0:
> > > >     - shard-tglb:         [PASS][7] -> [FAIL][8] ([i915#2842])
> > > >    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
> > > >    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
> > > > 
> > > >   * igt@gem_exec_fair@basic-pace-solo@rcs0:
> > > >     - shard-iclb:         NOTRUN -> [FAIL][9] ([i915#2842]) +1 similar issue
> > > >    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> > > >     - shard-tglb:         NOTRUN -> [FAIL][10] ([i915#2842])
> > > >    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> > > > 
> > > >   * igt@gem_lmem_swapping@heavy-verify-random:
> > > >     - shard-apl:          NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +2 similar issues
> > > >    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@gem_lmem_swapping@heavy-verify-random.html
> > > > 
> > > >   * igt@gem_lmem_swapping@parallel-random-engines:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][12] ([i915#4613]) +1 similar issue
> > > >    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_lmem_swapping@parallel-random-engines.html
> > > >     - shard-tglb:         NOTRUN -> [SKIP][13] ([i915#4613]) +1 similar issue
> > > >    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@gem_lmem_swapping@parallel-random-engines.html
> > > > 
> > > >   * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][14] ([i915#768])
> > > >    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html
> > > > 
> > > >   * igt@gem_softpin@evict-single-offset:
> > > >     - shard-iclb:         [PASS][15] -> [FAIL][16] ([i915#4171])
> > > >    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@gem_softpin@evict-single-offset.html
> > > >    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gem_softpin@evict-single-offset.html
> > > > 
> > > >   * igt@gem_vm_create@invalid-create:
> > > >     - shard-snb:          NOTRUN -> [SKIP][17] ([fdo#109271]) +65 similar issues
> > > >    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb7/igt@gem_vm_create@invalid-create.html
> > > > 
> > > >   * igt@gen9_exec_parse@bb-chained:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][18] ([i915#2527] / [i915#2856])
> > > >    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@gen9_exec_parse@bb-chained.html
> > > >     - shard-iclb:         NOTRUN -> [SKIP][19] ([i915#2856])
> > > >    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@gen9_exec_parse@bb-chained.html
> > > > 
> > > >   * igt@i915_module_load@reload:
> > > >     - shard-snb:          [PASS][20] -> [DMESG-WARN][21] ([i915#4528])
> > > >    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-snb4/igt@i915_module_load@reload.html
> > > >    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb4/igt@i915_module_load@reload.html
> > > > 
> > > >   * igt@i915_pm_dc@dc9-dpms:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][22] ([i915#4281])
> > > >    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@i915_pm_dc@dc9-dpms.html
> > > > 
> > > >   * igt@i915_query@test-query-geometry-subslices:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][23] ([i915#5723])
> > > >    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb6/igt@i915_query@test-query-geometry-subslices.html
> > > >     - shard-tglb:         NOTRUN -> [SKIP][24] ([i915#5723])
> > > >    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@i915_query@test-query-geometry-subslices.html
> > > > 
> > > >   * igt@kms_atomic@atomic_plane_damage:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#4765])
> > > >    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_atomic@atomic_plane_damage.html
> > > > 
> > > >   * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][26] ([i915#404])
> > > >    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
> > > >     - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#404])
> > > >    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
> > > > 
> > > >   * igt@kms_big_fb@linear-32bpp-rotate-270:
> > > >     - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271]) +44 similar issues
> > > >    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@kms_big_fb@linear-32bpp-rotate-270.html
> > > >     - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#111614]) +1 similar issue
> > > >    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb7/igt@kms_big_fb@linear-32bpp-rotate-270.html
> > > > 
> > > >   * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614]) +1 similar issue
> > > >    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
> > > > 
> > > >   * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][31] ([fdo#109278]) +6 similar issues
> > > >    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs.html
> > > > 
> > > >   * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][32] ([i915#3689] / [i915#6095]) +1 similar issue
> > > >    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb2/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs.html
> > > > 
> > > >   * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
> > > >     - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886])
> > > >    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
> > > > 
> > > >   * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#111615] / [i915#3689])
> > > >    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb1/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html
> > > > 
> > > >   * igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][35] ([i915#6095])
> > > >    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html
> > > > 
> > > >   * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3689])
> > > >    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb7/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
> > > > 
> > > >   * igt@kms_chamelium@dp-crc-fast:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827]) +2 similar issues
> > > >    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_chamelium@dp-crc-fast.html
> > > > 
> > > >   * igt@kms_chamelium@dp-frame-dump:
> > > >     - shard-apl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +4 similar issues
> > > >    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_chamelium@dp-frame-dump.html
> > > >     - shard-snb:          NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +2 similar issues
> > > >    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-snb4/igt@kms_chamelium@dp-frame-dump.html
> > > > 
> > > >   * igt@kms_chamelium@hdmi-audio-edid:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +2 similar issues
> > > >    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb3/igt@kms_chamelium@hdmi-audio-edid.html
> > > > 
> > > >   * igt@kms_content_protection@lic@pipe-a-dp-1:
> > > >     - shard-apl:          NOTRUN -> [TIMEOUT][41] ([i915#7173])
> > > >    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl1/igt@kms_content_protection@lic@pipe-a-dp-1.html
> > > > 
> > > >   * igt@kms_content_protection@mei_interface:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][42] ([i915#7118])
> > > >    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb2/igt@kms_content_protection@mei_interface.html
> > > >     - shard-iclb:         NOTRUN -> [SKIP][43] ([i915#7118])
> > > >    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_content_protection@mei_interface.html
> > > > 
> > > >   * igt@kms_cursor_crc@cursor-offscreen-512x170:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#109279] / [i915#3359])
> > > >    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_cursor_crc@cursor-offscreen-512x170.html
> > > >     - shard-tglb:         NOTRUN -> [SKIP][45] ([fdo#109279] / [i915#3359])
> > > >    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_cursor_crc@cursor-offscreen-512x170.html
> > > > 
> > > >   * igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1:
> > > >     - shard-apl:          [PASS][46] -> [DMESG-WARN][47] ([i915#180])
> > > >    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
> > > >    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
> > > > 
> > > >   * igt@kms_cursor_legacy@flip-vs-cursor@toggle:
> > > >     - shard-iclb:         [PASS][48] -> [FAIL][49] ([i915#2346]) +2 similar issues
> > > >    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
> > > >    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
> > > > 
> > > >   * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#1769] / [i915#3555])
> > > >    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
> > > > 
> > > >   * igt@kms_flip@plain-flip-ts-check@a-edp1:
> > > >     - shard-iclb:         [PASS][51] -> [DMESG-WARN][52] ([i915#7507])
> > > >    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@kms_flip@plain-flip-ts-check@a-edp1.html
> > > >    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_flip@plain-flip-ts-check@a-edp1.html
> > > > 
> > > >   * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][53] ([i915#2587] / [i915#2672]) +4 similar issues
> > > >    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
> > > > 
> > > >   * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][54] ([i915#2672]) +8 similar issues
> > > >    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
> > > > 
> > > >   * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][55] ([i915#2672] / [i915#3555])
> > > >    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
> > > > 
> > > >   * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt:
> > > >     - shard-iclb:         [PASS][56] -> [FAIL][57] ([i915#2546])
> > > >    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
> > > >    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
> > > > 
> > > >   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][58] ([i915#6497]) +2 similar issues
> > > >    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
> > > > 
> > > >   * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#109280] / [fdo#111825]) +7 similar issues
> > > >    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render.html
> > > > 
> > > >   * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109280]) +6 similar issues
> > > >    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
> > > > 
> > > >   * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1:
> > > >     - shard-apl:          NOTRUN -> [FAIL][61] ([i915#4573]) +2 similar issues
> > > >    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl6/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-dp-1.html
> > > > 
> > > >   * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
> > > >     - shard-iclb:         [PASS][62] -> [SKIP][63] ([i915#5176]) +2 similar issues
> > > >    [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
> > > >    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
> > > > 
> > > >   * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
> > > >     - shard-iclb:         [PASS][64] -> [SKIP][65] ([i915#5235]) +2 similar issues
> > > >    [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
> > > >    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
> > > > 
> > > >   * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
> > > >     - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#2920])
> > > >    [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-tglb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> > > >     - shard-iclb:         NOTRUN -> [SKIP][67] ([fdo#111068] / [i915#658])
> > > >    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> > > >     - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#658])
> > > >    [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> > > > 
> > > >   * igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1:
> > > >     - shard-iclb:         NOTRUN -> [FAIL][69] ([i915#5939]) +2 similar issues
> > > >    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1.html
> > > > 
> > > >   * igt@kms_psr@psr2_sprite_mmap_gtt:
> > > >     - shard-iclb:         [PASS][70] -> [SKIP][71] ([fdo#109441]) +2 similar issues
> > > >    [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
> > > >    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
> > > > 
> > > >   * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
> > > >     - shard-iclb:         [PASS][72] -> [SKIP][73] ([i915#5519])
> > > >    [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> > > >    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> > > > 
> > > >   * igt@kms_vblank@pipe-a-wait-busy:
> > > >     - shard-iclb:         NOTRUN -> [DMESG-WARN][74] ([i915#7507])
> > > >    [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_vblank@pipe-a-wait-busy.html
> > > > 
> > > >   * igt@perf@gen12-oa-tlb-invalidate:
> > > >     - shard-iclb:         NOTRUN -> [SKIP][75] ([fdo#109289])
> > > >    [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@perf@gen12-oa-tlb-invalidate.html
> > > > 
> > > >   
> > > > #### Possible fixes ####
> > > > 
> > > >   * igt@gem_exec_balancer@parallel:
> > > >     - shard-iclb:         [SKIP][76] ([i915#4525]) -> [PASS][77] +2 similar issues
> > > >    [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb7/igt@gem_exec_balancer@parallel.html
> > > >    [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@gem_exec_balancer@parallel.html
> > > > 
> > > >   * igt@i915_pm_dc@dc6-psr:
> > > >     - shard-iclb:         [FAIL][78] ([i915#3989] / [i915#454]) -> [PASS][79]
> > > >    [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
> > > >    [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
> > > > 
> > > >   * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> > > >     - shard-apl:          [DMESG-WARN][80] ([i915#180]) -> [PASS][81]
> > > >    [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> > > >    [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> > > > 
> > > >   * igt@kms_psr@psr2_sprite_plane_onoff:
> > > >     - shard-iclb:         [SKIP][82] ([fdo#109441]) -> [PASS][83] +2 similar issues
> > > >    [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb3/igt@kms_psr@psr2_sprite_plane_onoff.html
> > > >    [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
> > > > 
> > > >   * igt@kms_vblank@pipe-b-wait-idle-hang:
> > > >     - shard-apl:          [SKIP][84] ([fdo#109271]) -> [PASS][85]
> > > >    [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl8/igt@kms_vblank@pipe-b-wait-idle-hang.html
> > > >    [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@kms_vblank@pipe-b-wait-idle-hang.html
> > > > 
> > > >   
> > > > #### Warnings ####
> > > > 
> > > >   * igt@gem_exec_balancer@parallel-ordering:
> > > >     - shard-iclb:         [SKIP][86] ([i915#4525]) -> [FAIL][87] ([i915#6117])
> > > >    [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
> > > >    [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
> > > > 
> > > >   * igt@i915_pm_dc@dc3co-vpb-simulation:
> > > >     - shard-iclb:         [SKIP][88] ([i915#658]) -> [SKIP][89] ([i915#588])
> > > >    [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
> > > >    [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
> > > > 
> > > >   * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
> > > >     - shard-iclb:         [SKIP][90] ([i915#2920]) -> [SKIP][91] ([i915#658])
> > > >    [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
> > > >    [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
> > > > 
> > > >   * igt@kms_psr2_sf@plane-move-sf-dmg-area:
> > > >     - shard-iclb:         [SKIP][92] ([i915#2920]) -> [SKIP][93] ([fdo#111068] / [i915#658])
> > > >    [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
> > > >    [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
> > > > 
> > > >   * igt@runner@aborted:
> > > >     - shard-apl:          ([FAIL][94], [FAIL][95], [FAIL][96]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][97], [FAIL][98], [FAIL][99]) ([i915#3002] / [i915#4312])
> > > >    [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl2/igt@runner@aborted.html
> > > >    [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl8/igt@runner@aborted.html
> > > >    [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12471/shard-apl7/igt@runner@aborted.html
> > > >    [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl3/igt@runner@aborted.html
> > > >    [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl1/igt@runner@aborted.html
> > > >    [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/shard-apl7/igt@runner@aborted.html
> > > > 
> > > >   
> > > >   {name}: This element is suppressed. This means it is ignored when computing
> > > >           the status of the difference (SUCCESS, WARNING, or FAILURE).
> > > > 
> > > >   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> > > >   [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
> > > >   [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
> > > >   [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
> > > >   [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
> > > >   [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
> > > >   [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> > > >   [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> > > >   [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
> > > >   [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
> > > >   [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
> > > >   [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
> > > >   [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
> > > >   [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
> > > >   [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
> > > >   [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
> > > >   [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
> > > >   [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
> > > >   [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
> > > >   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> > > >   [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
> > > >   [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
> > > >   [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
> > > >   [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
> > > >   [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> > > >   [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
> > > >   [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
> > > >   [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
> > > >   [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
> > > >   [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> > > >   [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
> > > >   [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
> > > >   [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
> > > >   [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
> > > >   [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
> > > >   [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
> > > >   [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
> > > >   [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
> > > >   [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> > > >   [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
> > > >   [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
> > > >   [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
> > > >   [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
> > > >   [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
> > > >   [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
> > > >   [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> > > >   [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
> > > >   [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
> > > >   [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
> > > >   [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
> > > >   [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
> > > >   [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
> > > >   [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
> > > >   [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
> > > >   [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
> > > >   [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
> > > >   [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
> > > >   [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
> > > >   [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
> > > >   [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
> > > >   [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
> > > >   [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
> > > >   [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
> > > >   [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
> > > >   [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
> > > >   [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
> > > >   [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
> > > >   [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
> > > >   [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
> > > >   [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
> > > >   [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
> > > >   [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
> > > >   [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
> > > >   [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
> > > >   [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
> > > >   [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
> > > >   [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
> > > >   [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
> > > >   [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
> > > >   [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
> > > >   [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
> > > >   [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> > > >   [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
> > > >   [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
> > > >   [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
> > > >   [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
> > > >   [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
> > > >   [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
> > > >   [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
> > > >   [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
> > > >   [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
> > > >   [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> > > >   [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
> > > >   [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
> > > >   [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
> > > >   [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
> > > >   [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
> > > >   [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
> > > >   [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
> > > >   [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
> > > >   [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
> > > >   [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
> > > >   [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
> > > >   [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
> > > >   [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> > > >   [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
> > > >   [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
> > > >   [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
> > > >   [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
> > > >   [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
> > > >   [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
> > > >   [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
> > > >   [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> > > >   [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
> > > >   [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
> > > >   [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
> > > >   [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> > > >   [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
> > > >   [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
> > > >   [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> > > >   [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
> > > >   [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
> > > >   [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> > > >   [i915#4765]: https://gitlab.freedesktop.org/drm/intel/issues/4765
> > > >   [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
> > > >   [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
> > > >   [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
> > > >   [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
> > > >   [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
> > > >   [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
> > > >   [i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
> > > >   [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
> > > >   [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
> > > >   [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
> > > >   [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
> > > >   [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
> > > >   [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
> > > >   [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
> > > >   [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
> > > >   [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> > > >   [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> > > >   [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> > > >   [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> > > >   [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> > > >   [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> > > >   [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> > > >   [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
> > > >   [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> > > >   [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
> > > >   [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
> > > >   [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
> > > >   [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
> > > >   [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
> > > >   [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
> > > >   [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
> > > >   [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> > > >   [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
> > > >   [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
> > > >   [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
> > > >   [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
> > > >   [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
> > > >   [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
> > > >   [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
> > > >   [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
> > > >   [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
> > > >   [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
> > > >   [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
> > > >   [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
> > > >   [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
> > > >   [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
> > > >   [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
> > > >   [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> > > >   [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> > > >   [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
> > > >   [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
> > > >   [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
> > > >   [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
> > > >   [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
> > > >   [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
> > > >   [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
> > > >   [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
> > > >   [i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
> > > >   [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
> > > >   [i915#7507]: https://gitlab.freedesktop.org/drm/intel/issues/7507
> > > >   [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
> > > >   [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
> > > >   [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
> > > > 
> > > > 
> > > > Build changes
> > > > -------------
> > > > 
> > > >   * CI: CI-20190529 -> None
> > > >   * IGT: IGT_7083 -> IGTPW_8200
> > > >   * Piglit: piglit_4509 -> None
> > > > 
> > > >   CI-20190529: 20190529
> > > >   CI_DRM_12471: 7f8dc69dce0e934751fe31c01a6b6baa0c65bf23 @ git://anongit.freedesktop.org/gfx-ci/linux
> > > >   IGTPW_8200: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html
> > > >   IGT_7083: c001793d5f22deb01918b6ba52af829794582df1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> > > >   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> > > > 
> > > > == Logs ==
> > > > 
> > > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8200/index.html