From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: igt-dev@lists.freedesktop.org
Cc: Lionel G Landwerlin <lionel.g.landwerlin@linux.intel.com>
Subject: [igt-dev] [PATCH 08/30] i915/perf: Treat ticks as 64 bit
Date: Tue, 14 Feb 2023 12:59:45 -0800 [thread overview]
Message-ID: <20230214210007.2026033-9-umesh.nerlige.ramappa@intel.com> (raw)
In-Reply-To: <20230214210007.2026033-1-umesh.nerlige.ramappa@intel.com>
To support 64 bit OA report headers, treat all ticks as 64 bits.
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
tests/i915/perf.c | 79 ++++++++++++++++++++++++++++++++---------------
1 file changed, 54 insertions(+), 25 deletions(-)
diff --git a/tests/i915/perf.c b/tests/i915/perf.c
index bd3cdb6a..4c7b4e49 100644
--- a/tests/i915/perf.c
+++ b/tests/i915/perf.c
@@ -125,6 +125,7 @@ struct oa_format {
int c_off;
int n_c;
int oa_type;
+ bool report_hdr_64bit;
};
static struct oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = {
@@ -244,7 +245,7 @@ static bool *undefined_a_counters;
static uint64_t oa_exp_1_millisec;
static igt_render_copyfunc_t render_copy = NULL;
-static uint32_t (*read_report_ticks)(const uint32_t *report,
+static uint64_t (*read_report_ticks)(const uint32_t *report,
enum drm_i915_oa_format format);
static void (*sanity_check_reports)(const uint32_t *oa_report0,
const uint32_t *oa_report1,
@@ -438,7 +439,7 @@ sysfs_read(enum i915_attr_id id)
* C2 corresponds to a clock counter for the Haswell render basic metric set
* but it's not included in all of the formats.
*/
-static uint32_t
+static uint64_t
hsw_read_report_ticks(const uint32_t *report, enum drm_i915_oa_format format)
{
uint32_t *c = (uint32_t *)(((uint8_t *)report) + get_oa_format(format).c_off);
@@ -448,10 +449,41 @@ hsw_read_report_ticks(const uint32_t *report, enum drm_i915_oa_format format)
return c[2];
}
-static uint32_t
+static uint64_t
gen8_read_report_ticks(const uint32_t *report, enum drm_i915_oa_format format)
{
- return report[3];
+
+ struct oa_format fmt = get_oa_format(format);
+
+ return fmt.report_hdr_64bit ? *(uint64_t *)&report[6] : report[3];
+}
+
+/*
+ * t0 is a value sampled before t1. width is number of bits used to represent
+ * t0/t1. Normally t1 is greater than t0. In cases where t1 < t0 use this
+ * helper. Since the size of t1/t0 is already 64 bits, no special handling is
+ * needed for width = 64.
+ */
+static uint64_t
+elapsed_delta(uint64_t t1, uint64_t t0, uint32_t width)
+{
+ uint32_t max_bits = sizeof(t1) * 8;
+
+ igt_assert(width <= max_bits);
+
+ if (t1 < t0 && width != max_bits)
+ return ((1ULL << width) - t0) + t1;
+
+ return t1 - t0;
+}
+
+static uint64_t
+oa_tick_delta(const uint32_t *report1,
+ const uint32_t *report0,
+ enum drm_i915_oa_format format)
+{
+ return elapsed_delta(read_report_ticks(report1, format),
+ read_report_ticks(report0, format), 32);
}
static void
@@ -681,8 +713,8 @@ hsw_sanity_check_render_basic_reports(const uint32_t *oa_report0,
enum drm_i915_oa_format fmt)
{
uint32_t time_delta = timebase_scale(oa_report1[1] - oa_report0[1]);
- uint32_t clock_delta;
- uint32_t max_delta;
+ uint64_t clock_delta;
+ uint64_t max_delta;
struct oa_format format = get_oa_format(fmt);
igt_assert_neq(time_delta, 0);
@@ -697,21 +729,19 @@ hsw_sanity_check_render_basic_reports(const uint32_t *oa_report0,
clock_delta = (gt_max_freq_mhz *
(uint64_t)time_delta) / 1000;
} else {
- uint32_t ticks0 = read_report_ticks(oa_report0, fmt);
- uint32_t ticks1 = read_report_ticks(oa_report1, fmt);
uint64_t freq;
- clock_delta = ticks1 - ticks0;
+ clock_delta = oa_tick_delta(oa_report1, oa_report0, fmt);
- igt_assert_neq(clock_delta, 0);
+ igt_assert_neq_u64(clock_delta, 0);
- freq = ((uint64_t)clock_delta * 1000) / time_delta;
+ freq = (clock_delta * 1000) / time_delta;
igt_debug("freq = %"PRIu64"\n", freq);
igt_assert(freq <= gt_max_freq_mhz);
}
- igt_debug("clock delta = %"PRIu32"\n", clock_delta);
+ igt_debug("clock delta = %"PRIu64"\n", clock_delta);
/* The maximum rate for any HSW counter =
* clock_delta * N EUs
@@ -844,7 +874,8 @@ accumulate_reports(struct accumulator *accumulator,
accumulate_uint32(4, start, end, deltas + idx++);
/* clock cycles */
- accumulate_uint32(12, start, end, deltas + idx++);
+ deltas[idx] += oa_tick_delta(end, start, accumulator->format);
+ idx++;
} else {
/* timestamp */
accumulate_uint32(4, start, end, deltas + idx++);
@@ -917,10 +948,8 @@ gen8_sanity_check_test_oa_reports(const uint32_t *oa_report0,
{
struct oa_format format = get_oa_format(fmt);
uint32_t time_delta = timebase_scale(oa_report1[1] - oa_report0[1]);
- uint32_t ticks0 = read_report_ticks(oa_report0, fmt);
- uint32_t ticks1 = read_report_ticks(oa_report1, fmt);
- uint32_t clock_delta = ticks1 - ticks0;
- uint32_t max_delta;
+ uint64_t clock_delta = oa_tick_delta(oa_report1, oa_report0, fmt);
+ uint64_t max_delta;
uint64_t freq;
uint32_t *rpt0_b = (uint32_t *)(((uint8_t *)oa_report0) +
format.b_off);
@@ -933,10 +962,10 @@ gen8_sanity_check_test_oa_reports(const uint32_t *oa_report0,
gen8_read_report_reason(oa_report0),
gen8_read_report_reason(oa_report1));
- freq = time_delta ? ((uint64_t)clock_delta * 1000) / time_delta : 0;
+ freq = time_delta ? (clock_delta * 1000) / time_delta : 0;
igt_debug("freq = %"PRIu64"\n", freq);
- igt_debug("clock delta = %"PRIu32"\n", clock_delta);
+ igt_debug("clock delta = %"PRIu64"\n", clock_delta);
max_delta = clock_delta * intel_perf->devinfo.n_eus;
@@ -1037,7 +1066,7 @@ gen8_sanity_check_test_oa_reports(const uint32_t *oa_report0,
format.c_off);
uint32_t delta = c1[j] - c0[j];
- igt_debug("C%d: delta = %"PRIu32", max_delta=%"PRIu32"\n",
+ igt_debug("C%d: delta = %"PRIu32", max_delta=%"PRIu64"\n",
j, delta, max_delta);
igt_assert(delta <= max_delta);
}
@@ -1529,10 +1558,10 @@ print_reports(uint32_t *oa_report0, uint32_t *oa_report1, int fmt)
if (IS_HASWELL(devid) && format.n_c == 0) {
igt_debug("CLOCK = N/A\n");
} else {
- uint32_t clock0 = read_report_ticks(oa_report0, fmt);
- uint32_t clock1 = read_report_ticks(oa_report1, fmt);
+ uint64_t clock0 = read_report_ticks(oa_report0, fmt);
+ uint64_t clock1 = read_report_ticks(oa_report1, fmt);
- igt_debug("CLOCK: 1st = %"PRIu32", 2nd = %"PRIu32", delta = %"PRIu32"\n",
+ igt_debug("CLOCK: 1st = %"PRIu64", 2nd = %"PRIu64", delta = %"PRIu64"\n",
clock0, clock1, clock1 - clock0);
}
@@ -1634,9 +1663,9 @@ print_report(uint32_t *report, int fmt)
if (IS_HASWELL(devid) && format.n_c == 0) {
igt_debug("CLOCK = N/A\n");
} else {
- uint32_t clock = read_report_ticks(report, fmt);
+ uint64_t clock = read_report_ticks(report, fmt);
- igt_debug("CLOCK: %"PRIu32"\n", clock);
+ igt_debug("CLOCK: %"PRIu64"\n", clock);
}
if (intel_gen(devid) >= 8) {
--
2.36.1
next prev parent reply other threads:[~2023-02-14 21:00 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-14 20:59 [igt-dev] [PATCH 00/30] Enable OAM support in IGT and GPUvis Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 01/30] i915/perf: Add support for 64-bit OA formats Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 02/30] i915/perf: Define a default engine for OA Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 03/30] i915/perf: Use default engine for sseu tests Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 04/30] i915/perf: Ensure rcs0 is present for gen12-mi-rpc Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 05/30] i915/perf: Use ARRAY_SIZE for buffer-fill test Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 06/30] i915/perf: Add class:instance support to OA tests Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 07/30] i915/perf: Enable tests to run on specific engines Umesh Nerlige Ramappa
2023-02-14 20:59 ` Umesh Nerlige Ramappa [this message]
2023-02-14 20:59 ` [igt-dev] [PATCH 09/30] i915/perf: Treat timestamp as 64 bit value Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 10/30] i915/perf: Add OAM format type Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 11/30] i915/perf: Use a helper for OA format Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 12/30] i915/perf: Add support for oa perf groups Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 13/30] i915/perf: Test concurrent access to OA in different groups Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 14/30] i915/perf: Add OAM support Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 15/30] lib/perf: Make chipsets aware of oa formats Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 16/30] i915/perf: Choose OAM format for media metrics Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 17/30] lib/perf" Set missing metric unit for some counters Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 18/30] lib/perf: Add MTL to supprted HW in oa guid registry Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 19/30] lib/perf: Add support for OAM format in codegen Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 20/30] lib/perf: Update MTL GT2 metrics for OAM Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 21/30] lib/perf: Update MTL GT3 " Umesh Nerlige Ramappa
2023-02-14 20:59 ` [igt-dev] [PATCH 22/30] i915/perf: Add support for engine specific metrics Umesh Nerlige Ramappa
2023-02-14 21:00 ` [igt-dev] [PATCH 23/30] i915/perf: Run non-zero-reason on media engines as well Umesh Nerlige Ramappa
2023-02-14 21:00 ` [igt-dev] [PATCH 24/30] i915/perf: Make sanity check failures descriptive Umesh Nerlige Ramappa
2023-02-14 21:00 ` [igt-dev] [PATCH 25/30] lib/perf: Enable multi-tile support for perf library Umesh Nerlige Ramappa
2023-02-14 21:00 ` [igt-dev] [PATCH 26/30] lib/perf: Update MTL OA timestamp and EU thread config Umesh Nerlige Ramappa
2023-02-14 21:00 ` [igt-dev] [PATCH 27/30] lib/perf: Add support for MPEC format Umesh Nerlige Ramappa
2023-02-14 21:00 ` [igt-dev] [PATCH 28/30] lib/perf: Adjust the GPU timestamp for new OA formats Umesh Nerlige Ramappa
2023-02-14 21:00 ` [igt-dev] [PATCH 29/30] tools/perf: Choose the right card Umesh Nerlige Ramappa
2023-02-14 21:00 ` [igt-dev] [PATCH 30/30] lib/perf: Apply shift to raw timestamp as well Umesh Nerlige Ramappa
2023-02-14 21:18 ` [igt-dev] ✗ GitLab.Pipeline: warning for Enable OAM support in IGT and GPUvis Patchwork
2023-02-14 21:47 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2023-02-15 0:48 ` [igt-dev] [PATCH 00/30] " Umesh Nerlige Ramappa
2023-02-15 7:22 ` [igt-dev] ✗ Fi.CI.IGT: failure for " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230214210007.2026033-9-umesh.nerlige.ramappa@intel.com \
--to=umesh.nerlige.ramappa@intel.com \
--cc=igt-dev@lists.freedesktop.org \
--cc=lionel.g.landwerlin@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox