[igt-dev] [PATCH i-g-t 1/2] lib: Copy intel_gpu_commands.h from the kernel

[igt-dev] [PATCH i-g-t 1/2] lib: Copy intel_gpu_commands.h from the kernel

[Vikas Srivastava]

From: Chris Wilson <chris.p.wilson@linux.intel.com>

Cherry picking this patch to fix conflicts while merging
patch to resolve gem_exec_await timeout issue.

The current version of intel_gpu_commands lacks a few definitions and
has a couple of mistakes. This patch should be pushed to the kernel,
along with any other cleanups, and then copied back here.

Signed-off-by: Chris Wilson <chris.p.wilson@linux.intel.com>
Signed-off-by: Vikas Srivastava <vikas.srivastava@intel.com>
---
 include/intel_gpu_commands.h | 533 +++++++++++++++++++++++++++++++++++
 1 file changed, 533 insertions(+)
 create mode 100644 include/intel_gpu_commands.h

diff --git a/include/intel_gpu_commands.h b/include/intel_gpu_commands.h
new file mode 100644
index 000000000..b5239132f
--- /dev/null
+++ b/include/intel_gpu_commands.h
@@ -0,0 +1,533 @@
+/* SPDX-License-Identifier: MIT*/
+/*
+ * Copyright © 2003-2018 Intel Corporation
+ */
+
+#ifndef _INTEL_GPU_COMMANDS_H_
+#define _INTEL_GPU_COMMANDS_H_
+
+#ifdef __KERNEL
+#include <linux/bitops.h>
+#else
+#include "linux_scaffold.h"
+#endif
+
+/*
+ * Target address alignments required for GPU access e.g.
+ * MI_STORE_DWORD_IMM.
+ */
+#define alignof_dword 4
+#define alignof_qword 8
+
+/*
+ * Instruction field definitions used by the command parser
+ */
+#define INSTR_CLIENT_SHIFT      29
+#define   INSTR_MI_CLIENT       0x0
+#define   INSTR_BC_CLIENT       0x2
+#define   INSTR_GSC_CLIENT      0x2 /* MTL + */
+#define   INSTR_RC_CLIENT       0x3
+#define INSTR_SUBCLIENT_SHIFT   27
+#define INSTR_SUBCLIENT_MASK    0x18000000
+#define   INSTR_MEDIA_SUBCLIENT 0x2
+#define INSTR_26_TO_24_MASK	0x7000000
+#define   INSTR_26_TO_24_SHIFT	24
+
+#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
+
+/*
+ * Memory interface instructions used by the kernel
+ */
+#define MI_INSTR(opcode, flags) \
+	(__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
+/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
+#define  MI_GLOBAL_GTT    (1<<22)
+
+#define MI_NOOP			MI_INSTR(0, 0)
+#define MI_SET_PREDICATE	MI_INSTR(0x01, 0)
+#define   MI_SET_PREDICATE_DISABLE	(0 << 0)
+#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
+#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
+#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
+#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
+#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
+#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
+#define MI_FLUSH		MI_INSTR(0x04, 0)
+#define   MI_READ_FLUSH		(1 << 0)
+#define   MI_EXE_FLUSH		(1 << 1)
+#define   MI_NO_WRITE_FLUSH	(1 << 2)
+#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
+#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
+#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
+#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
+#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
+#define   MI_ARB_ENABLE			(1<<0)
+#define   MI_ARB_DISABLE		(0<<0)
+#define MI_MEM_FENCE		MI_INSTR(0x09, 0)
+#define MI_ACQUIRE_ENABLE	(1 << 0)
+#define MI_WRITE_FENCE		(3 << 0)
+#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
+#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
+#define   MI_SUSPEND_FLUSH_EN	(1<<0)
+#define MI_SET_APPID		MI_INSTR(0x0e, 0)
+#define   MI_SET_APPID_SESSION_ID(x)	((x) << 0)
+#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
+#define   MI_OVERLAY_CONTINUE	(0x0<<21)
+#define   MI_OVERLAY_ON		(0x1<<21)
+#define   MI_OVERLAY_OFF	(0x2<<21)
+#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
+#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
+#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
+#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
+/* IVB has funny definitions for which plane to flip. */
+#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
+#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
+#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
+#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
+#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
+#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
+/* SKL ones */
+#define   MI_DISPLAY_FLIP_SKL_PLANE_1_A	(0 << 8)
+#define   MI_DISPLAY_FLIP_SKL_PLANE_1_B	(1 << 8)
+#define   MI_DISPLAY_FLIP_SKL_PLANE_1_C	(2 << 8)
+#define   MI_DISPLAY_FLIP_SKL_PLANE_2_A	(4 << 8)
+#define   MI_DISPLAY_FLIP_SKL_PLANE_2_B	(5 << 8)
+#define   MI_DISPLAY_FLIP_SKL_PLANE_2_C	(6 << 8)
+#define   MI_DISPLAY_FLIP_SKL_PLANE_3_A	(7 << 8)
+#define   MI_DISPLAY_FLIP_SKL_PLANE_3_B	(8 << 8)
+#define   MI_DISPLAY_FLIP_SKL_PLANE_3_C	(9 << 8)
+#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
+#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
+#define   MI_SEMAPHORE_UPDATE	    (1<<21)
+#define   MI_SEMAPHORE_COMPARE	    (1<<20)
+#define   MI_SEMAPHORE_REGISTER	    (1<<18)
+#define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */
+#define   MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */
+#define   MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */
+#define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */
+#define   MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */
+#define   MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */
+#define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */
+#define   MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */
+#define   MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */
+#define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */
+#define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */
+#define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */
+#define   MI_SEMAPHORE_SYNC_INVALID (3<<16)
+#define   MI_SEMAPHORE_SYNC_MASK    (3<<16)
+#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
+#define   MI_MM_SPACE_GTT		(1<<8)
+#define   MI_MM_SPACE_PHYSICAL		(0<<8)
+#define   MI_SAVE_EXT_STATE_EN		(1<<3)
+#define   MI_RESTORE_EXT_STATE_EN	(1<<2)
+#define   MI_FORCE_RESTORE		(1<<1)
+#define   MI_RESTORE_INHIBIT		(1<<0)
+#define   HSW_MI_RS_SAVE_STATE_EN       (1<<3)
+#define   HSW_MI_RS_RESTORE_STATE_EN    (1<<2)
+#define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */
+#define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
+#define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
+#define MI_SEMAPHORE_WAIT_TOKEN	MI_INSTR(0x1c, 3) /* GEN12+ */
+#define   MI_SEMAPHORE_POLL		(1 << 15)
+#define   MI_SEMAPHORE_SAD_GT_SDD	(0 << 12)
+#define   MI_SEMAPHORE_SAD_GTE_SDD	(1 << 12)
+#define   MI_SEMAPHORE_SAD_LT_SDD	(2 << 12)
+#define   MI_SEMAPHORE_SAD_LTE_SDD	(3 << 12)
+#define   MI_SEMAPHORE_SAD_EQ_SDD	(4 << 12)
+#define   MI_SEMAPHORE_SAD_NEQ_SDD	(5 << 12)
+#define   MI_SEMAPHORE_27_TOKEN_MASK	REG_GENMASK(9, 5)
+#define   MI_SEMAPHORE_256_TOKEN_MASK	REG_GENMASK(9, 2)
+#define   MI_SEMAPHORE_27_TOKEN_SHIFT	5
+#define   MI_SEMAPHORE_256_TOKEN_SHIFT	2
+#define MI_STORE_DATA_IMM	MI_INSTR(0x20, 0)
+#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
+#define MI_STORE_DWORD_IMM_GEN4	MI_INSTR(0x20, 2)
+#define MI_STORE_QWORD_IMM_GEN8_POSTED (MI_INSTR(0x20, 3) | (1 << 21))
+#define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | (1 << 10) | (1 << 21))
+#define   MI_MEM_VIRTUAL	(1 << 22) /* 945,g33,965 */
+#define   MI_USE_GGTT		(1 << 22) /* g4x+ */
+#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
+#define MI_ATOMIC		MI_INSTR(0x2f, 1)
+#define MI_ATOMIC_INLINE	(MI_INSTR(0x2f, 9) | MI_ATOMIC_INLINE_DATA)
+#define   MI_ATOMIC_GLOBAL_GTT		(1 << 22)
+#define   MI_ATOMIC_INLINE_DATA		(1 << 18)
+#define   MI_ATOMIC_CS_STALL		(1 << 17)
+#define	  MI_ATOMIC_MOVE		(0x4 << 8)
+#define	  MI_ATOMIC_INC			(0x5 << 8)
+#define	  MI_ATOMIC_DEC			(0x6 << 8)
+#define	  MI_ATOMIC_ADD			(0x7 << 8)
+#define	  MI_ATOMIC_SUB			(0x8 << 8)
+
+/*
+ * Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
+ * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
+ *   simply ignores the register load under certain conditions.
+ * - One can actually load arbitrary many arbitrary registers: Simply issue x
+ *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
+ */
+#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
+/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
+#define   MI_LRI_DEST_CS_MMIO		REG_BIT(19)
+#define   MI_LRI_LRM_CS_MMIO		REG_BIT(19)
+#define   MI_LRI_FORCE_POSTED		(1<<12)
+#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
+#define __MI_STORE_REGISTER_MEM      MI_INSTR(0x24, 0)
+#define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
+#define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
+#define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)
+#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
+#define   MI_FLUSH_DW_PROTECTED_MEM_EN	(1 << 22)
+#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
+#define   MI_INVALIDATE_TLB		(1<<18)
+#define   MI_FLUSH_CCS			(1<<16)
+#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
+#define   MI_FLUSH_DW_OP_MASK		(3<<14)
+#define   MI_FLUSH_LLC			(1<<9)
+#define   MI_FLUSH_DW_NOTIFY		(1<<8)
+#define   MI_INVALIDATE_BSD		(1<<7)
+#define   MI_FLUSH_DW_USE_GTT		(1<<2)
+#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
+#define __MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 0)
+#define MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 1)
+#define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
+#define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 1)
+#define   MI_LRR_SOURCE_CS_MMIO		REG_BIT(18)
+#define   MI_LRR_DEST_CS_MMIO		REG_BIT(19)
+#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
+#define   MI_BATCH_NON_SECURE		(1)
+/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
+#define   MI_BATCH_NON_SECURE_I965	(1<<8)
+#define   MI_BATCH_PPGTT_HSW		(1<<8)
+#define   MI_BATCH_NON_SECURE_HSW	(1<<13)
+#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
+#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
+#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
+#define   MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
+#define   MI_BATCH_PREDICATE         REG_BIT(15) /* HSW+ on RCS only*/
+#define MI_COND_BATCH_BUFFER_END	MI_INSTR(0x36, 0)
+#define   MI_DO_COMPARE				(1 << 21)
+
+/*
+ * 3D instructions used by the kernel
+ */
+#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
+
+#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
+#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
+#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
+#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define   SC_UPDATE_SCISSOR       (0x1<<1)
+#define   SC_ENABLE_MASK          (0x1<<0)
+#define   SC_ENABLE               (0x1<<0)
+#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
+#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
+#define   SCI_YMIN_MASK      (0xffff<<16)
+#define   SCI_XMIN_MASK      (0xffff<<0)
+#define   SCI_YMAX_MASK      (0xffff<<16)
+#define   SCI_XMAX_MASK      (0xffff<<0)
+#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
+#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
+#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
+#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
+#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
+#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
+#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
+#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
+
+#define XY_CTRL_SURF_COPY_BLT		(2<<29 | 0x48<<22 | 3)
+#define   SRC_ACCESS_TYPE_SHIFT		21
+#define   DST_ACCESS_TYPE_SHIFT		20
+#define   CCS_SIZE_SHIFT		8
+/* Bspec lists field as [31:25], but index alone is at [31:26] */
+#define   XY_CSC_BLT_MOCS_INDEX_MASK_GEN12	GENMASK(31, 26)
+#define   XY_CSC_BLT_MOCS_INDEX_MASK_XE2	GENMASK(31, 28)
+#define   NUM_CCS_BYTES_PER_BLOCK	256
+#define   NUM_CCS_BLKS_PER_XFER	1024
+#define   INDIRECT_ACCESS		0
+#define   DIRECT_ACCESS		1
+
+#define COLOR_BLT_CMD			(2 << 29 | 0x40 << 22 | (5 - 2))
+#define XY_BLOCK_COPY_BLT_CMD		(2 << 29 | 0x41 << 22)
+#define   DEST_MEM_TYPE_SHIFT		(31)
+#define   SRC_MEM_TYPE_SHIFT		(31)
+#define   MEM_TYPE_SYS			1
+#define   MEM_TYPE_LOCAL		0
+#define   COMPRESSION_ENABLE		(1 << 29)
+#define   AUX_CCS_E			(5 << 18)
+#define   FULL_RESOLVE			(1 << 12)
+#define   TILE_4_FORMAT			(2 << 30)
+#define   TILE_4_WIDTH			(128)
+#define   TILE_4_WIDTH_DWORD		((128 >> 2) - 1)
+#define   TILE_4_HEIGHT			(32)
+#define   SURFACE_TYPE_2D		(1 << 29)
+#define   DEST_SURF_WIDTH_SHIFT		(14)
+#define   SRC_SURF_WIDTH_SHIFT		(14)
+/* Bspec lists this field as 27:21, but the index alone is in 27:22 */
+#define   XY_BCB_MOCS_INDEX_MASK_GEN12	GENMASK(27, 22)
+#define   XY_BCB_MOCS_INDEX_MASK_XE2	GENMASK(27, 24)
+#define GEN9_XY_FAST_COPY_BLT_CMD	(2 << 29 | 0x42 << 22)
+#define   XY_FAST_COPY_BLT_D0_SRC_TILING_MASK     REG_GENMASK(21, 20)
+#define   XY_FAST_COPY_BLT_D0_DST_TILING_MASK     REG_GENMASK(14, 13)
+#define   XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode)  \
+	REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
+#define   XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode)  \
+	REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
+#define     LINEAR				0
+#define     TILE_X				0x1
+#define     XMAJOR				0x1
+#define     YMAJOR				0x2
+#define     TILE_64			0x3
+#define   XY_FAST_COPY_BLT_D1_SRC_TILE4	REG_BIT(31)
+#define   XY_FAST_COPY_BLT_D1_DST_TILE4	REG_BIT(30)
+#define   PVC_ENABLE_COMPRESSED_SURFACE	REG_BIT(16)
+#define   XY_FCB_MOCS_INDEX_MASK_XE2	GENMASK(23, 20)
+#define BLIT_CCTL_SRC_MOCS_MASK  REG_GENMASK(6, 0)
+#define BLIT_CCTL_DST_MOCS_MASK  REG_GENMASK(14, 8)
+/* Note:  MOCS value = (index << 1) */
+#define BLIT_CCTL_SRC_MOCS(idx) \
+	REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, idx << 1)
+#define BLIT_CCTL_DST_MOCS(idx) \
+	REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, idx << 1)
+#define SRC_COPY_BLT_CMD		(2 << 29 | 0x43 << 22)
+#define XY_FAST_COLOR_BLT		(2 << 29 | 0x44 << 22)
+#define   BLT_COLOR_DEPTH_32		(2 << 19)
+#define   BLT_COLOR_DEPTH_64		(3 << 19)
+/* Bspec lists field as [27:21], but index resides in [27:22] */
+#define   XY_FCB_MOCS_INDEX_MASK	GENMASK(27, 22)
+#define XY_COLOR_BLT_CMD		(2 << 29 | 0x50 << 22)
+#define XY_SRC_COPY_BLT_CMD		(2 << 29 | 0x53 << 22)
+#define XY_MONO_SRC_COPY_IMM_BLT	(2 << 29 | 0x71 << 22 | 5)
+#define   BLT_SRCMEM_SYS		(1<<29)
+#define   BLT_WRITE_A			(2<<20)
+#define   BLT_WRITE_RGB			(1<<20)
+#define   BLT_WRITE_RGBA		(BLT_WRITE_RGB | BLT_WRITE_A)
+#define   BLT_DEPTH_8			(0<<24)
+#define   BLT_DEPTH_16_565		(1<<24)
+#define   BLT_DEPTH_16_1555		(2<<24)
+#define   BLT_DEPTH_32			(3<<24)
+#define   BLT_ROP_SRC_COPY		(0xcc<<16)
+#define   BLT_ROP_COLOR_COPY		(0xf0<<16)
+#define PVC_MEM_COPY_CMD		(2 << 29 | 0x5a << 22)
+#define   PVC_MEM_COPY_SRC_COMPRESSIBLE	BIT(16)
+#define   PVC_MEM_COPY_DST_COMPRESSIBLE	BIT(15)
+#define   PVC_MEM_COPY_DST_COMPRESS_EN	BIT(13)
+#define   MEM_COPY_COMPRESSION_FMT_XEHPC	GENMASK(12, 8)
+#define   MEM_COPY_COMPRESSION_FMT_XE2	GENMASK(12, 9)
+/*
+ * Bspec lists MOCS fields as [31:25] and [6:0], but the actual indices are
+ * in [31:26] and [6:1].
+ */
+#define   MC_SRC_MOCS_INDEX_MASK_GEN12	GENMASK(31, 26)
+#define   MC_SRC_MOCS_INDEX_MASK_XE2	GENMASK(31, 28)
+#define   MC_DST_MOCS_INDEX_MASK_GEN12	GENMASK(6, 1)
+#define   MC_DST_MOCS_INDEX_MASK_XE2	GENMASK(6, 3)
+#define PVC_MEM_SET_CMD			(2 << 29 | 0x5b << 22)
+#define   PVC_MEM_SET_DST_COMPRESSIBLE	BIT(15)
+#define   PVC_MEM_SET_DST_COMPRESS_EN	BIT(13)
+#define   MEM_SET_COMPRESSION_FMT_XEHPC	GENMASK(12, 8)
+#define   MEM_SET_COMPRESSION_FMT_XE2	GENMASK(12, 9)
+/* Bspec lists field as [6:0], but index alone is from [6:1] */
+#define   MS_MOCS_INDEX_MASK_GEN12	GENMASK(6, 1)
+#define   MS_MOCS_INDEX_MASK_XE2	GENMASK(6, 3)
+#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
+#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
+#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
+#define   ASYNC_FLIP                (1<<22)
+#define   DISPLAY_PLANE_A           (0<<20)
+#define   DISPLAY_PLANE_B           (1<<20)
+#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
+#define   PIPE_CONTROL0_HDC_PIPELINE_FLUSH		BIT(9)  /* dword0, gen12 */
+#define   PIPE_CONTROL0_DATAPORT_FLUSH_XE2		BIT(9)	/* dword0, xe2 */
+#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
+#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
+#define   PIPE_CONTROL_FLUSH_L3				(1<<27)
+#define   PIPE_CONTROL_AMFS_FLUSH			(1<<25) /* gen12+ */
+#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
+#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
+#define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
+#define   PIPE_CONTROL_CS_STALL				(1<<20)
+#define   PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET		(1<<19)
+#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
+#define   PIPE_CONTROL_PSD_SYNC				(1<<17) /* gen11+ */
+#define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
+#define   PIPE_CONTROL_WRITE_TIMESTAMP			(3<<14)
+#define   PIPE_CONTROL_QW_WRITE				(1<<14)
+#define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
+#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
+#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
+#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
+#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on ILK */
+#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
+#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
+#define   PIPE_CONTROL_NOTIFY				(1<<8)
+#define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */
+#define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
+#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
+#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
+#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
+#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
+#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
+#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+
+/*
+ * 3D-related flags that can't be set on _engines_ that lack access to the 3D
+ * pipeline (i.e., CCS engines).
+ */
+#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
+		PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
+		PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
+		PIPE_CONTROL_TILE_CACHE_FLUSH | \
+		PIPE_CONTROL_DEPTH_STALL | \
+		PIPE_CONTROL_STALL_AT_SCOREBOARD | \
+		PIPE_CONTROL_PSD_SYNC | \
+		PIPE_CONTROL_AMFS_FLUSH | \
+		PIPE_CONTROL_VF_CACHE_INVALIDATE | \
+		PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
+
+/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
+#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
+		PIPE_CONTROL_3D_ENGINE_FLAGS | \
+		PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
+		PIPE_CONTROL_FLUSH_ENABLE | \
+		PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
+		PIPE_CONTROL_DC_FLUSH_ENABLE)
+
+#define MI_MATH(x)			MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define   MI_MATH_NOOP			MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define   MI_MATH_LOAD(op1, op2)	MI_MATH_INSTR(0x080, op1, op2)
+#define   MI_MATH_LOADINV(op1, op2)	MI_MATH_INSTR(0x480, op1, op2)
+#define   MI_MATH_LOAD0(op1)		MI_MATH_INSTR(0x081, op1, 0x0)
+#define   MI_MATH_LOAD1(op1)		MI_MATH_INSTR(0x481, op1, 0x0)
+#define   MI_MATH_ADD			MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define   MI_MATH_SUB			MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define   MI_MATH_AND			MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define   MI_MATH_OR			MI_MATH_INSTR(0x103, 0x0, 0x0)
+#define   MI_MATH_XOR			MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define   MI_MATH_STORE(op1, op2)	MI_MATH_INSTR(0x180, op1, op2)
+#define   MI_MATH_STOREINV(op1, op2)	MI_MATH_INSTR(0x580, op1, op2)
+/* DG2+ */
+#define   MI_MATH_SHR			MI_MATH_INSTR(0x106, 0x0, 0x0)
+
+/* Registers used as operands in MI_MATH_INSTR */
+#define   MI_MATH_REG(x)		(x)
+#define   MI_MATH_REG_SRCA		0x20
+#define   MI_MATH_REG_SRCB		0x21
+#define   MI_MATH_REG_ACCU		0x31
+#define   MI_MATH_REG_ZF		0x32
+#define   MI_MATH_REG_CF		0x33
+
+/*
+ * Media instructions used by the kernel
+ */
+#define MEDIA_INSTR(pipe, op, sub_op, flags) \
+	(__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
+	(op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))
+
+#define MFX_WAIT				MEDIA_INSTR(1, 0, 0, 0)
+#define  MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG	REG_BIT(8)
+#define  MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG	REG_BIT(9)
+
+#define CRYPTO_KEY_EXCHANGE			MEDIA_INSTR(2, 6, 9, 0)
+
+/*
+ * Commands used only by the command parser
+ */
+#define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
+#define MI_ARB_CHECK            MI_INSTR(0x05, 0)
+#define MI_RS_CONTROL           MI_INSTR(0x06, 0)
+#define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
+#define MI_PREDICATE            MI_INSTR(0x0C, 0)
+#define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
+#define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
+#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
+#define MI_URB_CLEAR            MI_INSTR(0x19, 0)
+#define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
+#define MI_CLFLUSH              MI_INSTR(0x27, 0)
+#define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
+#define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
+#define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
+#define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
+#define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
+#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
+
+#define STATE_SYSTEM_MEM_FENCE_ADDRESS \
+	((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x9 << 16) | 0x1)
+#define STATE_BASE_ADDRESS \
+	((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x1 << 16))
+#define BASE_ADDRESS_MODIFY		REG_BIT(0)
+#define PIPELINE_SELECT \
+	((0x3 << 29) | (0x1 << 27) | (0x1 << 24) | (0x4 << 16))
+#define PIPELINE_SELECT_MEDIA	       REG_BIT(0)
+#define GFX_OP_3DSTATE_VF_STATISTICS \
+	((0x3 << 29) | (0x1 << 27) | (0x0 << 24) | (0xB << 16))
+#define MEDIA_VFE_STATE \
+	((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x0 << 16))
+#define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
+#define MEDIA_INTERFACE_DESCRIPTOR_LOAD \
+	((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x2 << 16))
+#define MEDIA_OBJECT \
+	((0x3 << 29) | (0x2 << 27) | (0x1 << 24) | (0x0 << 16))
+#define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
+#define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
+#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
+	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
+#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
+	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
+#define GFX_OP_3DSTATE_SO_DECL_LIST \
+	((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
+
+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
+	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
+	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
+	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
+	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
+	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
+
+#define COLOR_BLT     ((0x2<<29)|(0x40<<22))
+#define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))
+
+/* Bspec 63347*/
+#define GSC_INSTR(opcode, data, flags) \
+	(__INSTR(INSTR_GSC_CLIENT) | (opcode) << 22 | (data) << 9 | (flags))
+
+/* bspec 65346 */
+#define GSC_FW_LOAD GSC_INSTR(1, 0, 2)
+#define   HECI1_FW_LIMIT_VALID (1<<31)
+
+#define GSC_HECI_CMD_PKT GSC_INSTR(0, 0, 6)
+
+/*
+ * Used to convert an address to canonical form based on size of
+ * virtual address space.
+ * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
+ * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
+ * addresses to be in a canonical form:
+ * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
+ * canonical form [63:48] == [47]."
+ */
+static inline u64 intel_canonical_addr(u32 ppgtt_msb, u64 address)
+{
+	return sign_extend64(address, ppgtt_msb);
+}
+
+static inline u64 intel_noncanonical_addr(u32 ppgtt_msb, u64 address)
+{
+	return address & GENMASK_ULL(ppgtt_msb, 0);
+}
+
+static inline u32 *__gen6_emit_bb_start(u32 *cs, u32 addr, unsigned int flags)
+{
+	*cs++ = MI_BATCH_BUFFER_START | flags;
+	*cs++ = addr;
+
+	return cs;
+}
+
+#endif /* _INTEL_GPU_COMMANDS_H_ */
-- 
2.25.1

[igt-dev] [PATCH i-g-t 2/2] include/intel_gpu_commands: Copy intel_gpu_commands from the kernel

[Vikas Srivastava]

From: Chris Wilson <chris.p.wilson@linux.intel.com>

Define the GPU commands at one place and consolidate on a
single interface consistent with usage inside the kernel.

Signed-off-by: Chris Wilson <chris.p.wilson@linux.intel.com>
Signed-off-by: Vikas Srivastava <vikas.srivastava@intel.com>
---
 include/linux_scaffold.h | 51 ++++++++++++++++++++++++++++++++++++++++
 lib/ioctl_wrappers.h     |  4 ++--
 meson.build              |  2 +-
 3 files changed, 54 insertions(+), 3 deletions(-)
 create mode 100644 include/linux_scaffold.h

diff --git a/include/linux_scaffold.h b/include/linux_scaffold.h
new file mode 100644
index 000000000..57c456180
--- /dev/null
+++ b/include/linux_scaffold.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: MIT */
+
+#ifndef _INTEL_GPU_COMMANDS_SCAFFOLD_H_
+#define _INTEL_GPU_COMMANDS_SCAFFOLD_H_
+
+#include <linux/const.h>
+
+#include <stdint.h>
+
+typedef uint8_t  u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef uint64_t u64;
+
+typedef int8_t  s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+
+static s64 sign_extend64(u64 value, int index)
+{
+	int shift = 63 - index;
+
+	return (s64)(value << shift) >> shift;
+}
+
+/* Make IGT build with Kernels < 4.17 */
+#ifndef _AC
+#  define _AC(X, Y)	__AC(X, Y)
+#endif
+#ifndef _UL
+#  define  _UL(x)		(_AC(x, UL))
+#endif
+#ifndef _ULL
+#  define _ULL(x)		(_AC(x, ULL))
+#endif
+
+#define GENMASK(h, l) \
+	       (((~_UL(0)) - (_UL(1) << (l)) + 1) & \
+	       (~_UL(0) >> (BITS_PER_LONG - 1 - (h))))
+
+#define GENMASK_ULL(h, l) \
+		   (((~_ULL(0)) - (_ULL(1) << (l)) + 1) & \
+		   (~_ULL(0) >> (BITS_PER_LONG_LONG - 1 - (h))))
+
+#define BITS_PER_BYTE 8
+#define BITS_PER_TYPE(t) (sizeof(t) * BITS_PER_BYTE)
+#define BITS_PER_LONG BITS_PER_TYPE(long)
+#define BITS_PER_LONG_LONG BITS_PER_TYPE(long long)
+
+#endif /* _INTEL_GPU_COMMANDS_SCAFFOLD_H_ */
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index cf228c265..aecad2d7d 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -173,9 +173,9 @@ static inline uint64_t to_user_pointer(const void *ptr)
  *
  * Casts a 64bit value from an ioctl into a pointer.
  */
-static inline void *from_user_pointer(uint64_t u64)
+static inline void *from_user_pointer(uint64_t x64)
 {
-	return (void *)(uintptr_t)u64;
+	return (void *)(uintptr_t)x64;
 }
 
 /**
diff --git a/meson.build b/meson.build
index e7a68503d..4dc720bc2 100644
--- a/meson.build
+++ b/meson.build
@@ -85,7 +85,7 @@ with_libdrm = get_option('libdrm_drivers')
 
 build_info = ['Build type: ' + get_option('buildtype')]
 
-inc = include_directories('include/drm-uapi', 'include/linux-uapi', 'lib', 'lib/stubs/syscalls', '.')
+inc = include_directories('include', 'include/drm-uapi', 'include/linux-uapi', 'lib', 'lib/stubs/syscalls', '.')
 
 inc_for_gtkdoc = include_directories('lib')
 
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t 1/2] lib: Copy intel_gpu_commands.h from the kernel

[Zbigniew Kempczyński]

On Tue, Mar 07, 2023 at 09:51:45PM +0530, Vikas Srivastava wrote:
> From: Chris Wilson <chris.p.wilson@linux.intel.com>
> 
> Cherry picking this patch to fix conflicts while merging
> patch to resolve gem_exec_await timeout issue.
> 
> The current version of intel_gpu_commands lacks a few definitions and
> has a couple of mistakes. This patch should be pushed to the kernel,
> along with any other cleanups, and then copied back here.

Looks we worked on same thing:

https://patchwork.freedesktop.org/series/114619/

--
Zbigniew

> 
> Signed-off-by: Chris Wilson <chris.p.wilson@linux.intel.com>
> Signed-off-by: Vikas Srivastava <vikas.srivastava@intel.com>
> ---
>  include/intel_gpu_commands.h | 533 +++++++++++++++++++++++++++++++++++
>  1 file changed, 533 insertions(+)
>  create mode 100644 include/intel_gpu_commands.h
> 
> diff --git a/include/intel_gpu_commands.h b/include/intel_gpu_commands.h
> new file mode 100644
> index 000000000..b5239132f
> --- /dev/null
> +++ b/include/intel_gpu_commands.h
> @@ -0,0 +1,533 @@
> +/* SPDX-License-Identifier: MIT*/
> +/*
> + * Copyright © 2003-2018 Intel Corporation
> + */
> +
> +#ifndef _INTEL_GPU_COMMANDS_H_
> +#define _INTEL_GPU_COMMANDS_H_
> +
> +#ifdef __KERNEL
> +#include <linux/bitops.h>
> +#else
> +#include "linux_scaffold.h"
> +#endif
> +
> +/*
> + * Target address alignments required for GPU access e.g.
> + * MI_STORE_DWORD_IMM.
> + */
> +#define alignof_dword 4
> +#define alignof_qword 8
> +
> +/*
> + * Instruction field definitions used by the command parser
> + */
> +#define INSTR_CLIENT_SHIFT      29
> +#define   INSTR_MI_CLIENT       0x0
> +#define   INSTR_BC_CLIENT       0x2
> +#define   INSTR_GSC_CLIENT      0x2 /* MTL + */
> +#define   INSTR_RC_CLIENT       0x3
> +#define INSTR_SUBCLIENT_SHIFT   27
> +#define INSTR_SUBCLIENT_MASK    0x18000000
> +#define   INSTR_MEDIA_SUBCLIENT 0x2
> +#define INSTR_26_TO_24_MASK	0x7000000
> +#define   INSTR_26_TO_24_SHIFT	24
> +
> +#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
> +
> +/*
> + * Memory interface instructions used by the kernel
> + */
> +#define MI_INSTR(opcode, flags) \
> +	(__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
> +/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
> +#define  MI_GLOBAL_GTT    (1<<22)
> +
> +#define MI_NOOP			MI_INSTR(0, 0)
> +#define MI_SET_PREDICATE	MI_INSTR(0x01, 0)
> +#define   MI_SET_PREDICATE_DISABLE	(0 << 0)
> +#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
> +#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
> +#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
> +#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
> +#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
> +#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
> +#define MI_FLUSH		MI_INSTR(0x04, 0)
> +#define   MI_READ_FLUSH		(1 << 0)
> +#define   MI_EXE_FLUSH		(1 << 1)
> +#define   MI_NO_WRITE_FLUSH	(1 << 2)
> +#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
> +#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
> +#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
> +#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
> +#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
> +#define   MI_ARB_ENABLE			(1<<0)
> +#define   MI_ARB_DISABLE		(0<<0)
> +#define MI_MEM_FENCE		MI_INSTR(0x09, 0)
> +#define MI_ACQUIRE_ENABLE	(1 << 0)
> +#define MI_WRITE_FENCE		(3 << 0)
> +#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
> +#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
> +#define   MI_SUSPEND_FLUSH_EN	(1<<0)
> +#define MI_SET_APPID		MI_INSTR(0x0e, 0)
> +#define   MI_SET_APPID_SESSION_ID(x)	((x) << 0)
> +#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
> +#define   MI_OVERLAY_CONTINUE	(0x0<<21)
> +#define   MI_OVERLAY_ON		(0x1<<21)
> +#define   MI_OVERLAY_OFF	(0x2<<21)
> +#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
> +#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
> +#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
> +#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
> +/* IVB has funny definitions for which plane to flip. */
> +#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
> +#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
> +#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
> +#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
> +#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
> +#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
> +/* SKL ones */
> +#define   MI_DISPLAY_FLIP_SKL_PLANE_1_A	(0 << 8)
> +#define   MI_DISPLAY_FLIP_SKL_PLANE_1_B	(1 << 8)
> +#define   MI_DISPLAY_FLIP_SKL_PLANE_1_C	(2 << 8)
> +#define   MI_DISPLAY_FLIP_SKL_PLANE_2_A	(4 << 8)
> +#define   MI_DISPLAY_FLIP_SKL_PLANE_2_B	(5 << 8)
> +#define   MI_DISPLAY_FLIP_SKL_PLANE_2_C	(6 << 8)
> +#define   MI_DISPLAY_FLIP_SKL_PLANE_3_A	(7 << 8)
> +#define   MI_DISPLAY_FLIP_SKL_PLANE_3_B	(8 << 8)
> +#define   MI_DISPLAY_FLIP_SKL_PLANE_3_C	(9 << 8)
> +#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
> +#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
> +#define   MI_SEMAPHORE_UPDATE	    (1<<21)
> +#define   MI_SEMAPHORE_COMPARE	    (1<<20)
> +#define   MI_SEMAPHORE_REGISTER	    (1<<18)
> +#define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */
> +#define   MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */
> +#define   MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */
> +#define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */
> +#define   MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */
> +#define   MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */
> +#define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */
> +#define   MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */
> +#define   MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */
> +#define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */
> +#define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */
> +#define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */
> +#define   MI_SEMAPHORE_SYNC_INVALID (3<<16)
> +#define   MI_SEMAPHORE_SYNC_MASK    (3<<16)
> +#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
> +#define   MI_MM_SPACE_GTT		(1<<8)
> +#define   MI_MM_SPACE_PHYSICAL		(0<<8)
> +#define   MI_SAVE_EXT_STATE_EN		(1<<3)
> +#define   MI_RESTORE_EXT_STATE_EN	(1<<2)
> +#define   MI_FORCE_RESTORE		(1<<1)
> +#define   MI_RESTORE_INHIBIT		(1<<0)
> +#define   HSW_MI_RS_SAVE_STATE_EN       (1<<3)
> +#define   HSW_MI_RS_RESTORE_STATE_EN    (1<<2)
> +#define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */
> +#define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
> +#define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
> +#define MI_SEMAPHORE_WAIT_TOKEN	MI_INSTR(0x1c, 3) /* GEN12+ */
> +#define   MI_SEMAPHORE_POLL		(1 << 15)
> +#define   MI_SEMAPHORE_SAD_GT_SDD	(0 << 12)
> +#define   MI_SEMAPHORE_SAD_GTE_SDD	(1 << 12)
> +#define   MI_SEMAPHORE_SAD_LT_SDD	(2 << 12)
> +#define   MI_SEMAPHORE_SAD_LTE_SDD	(3 << 12)
> +#define   MI_SEMAPHORE_SAD_EQ_SDD	(4 << 12)
> +#define   MI_SEMAPHORE_SAD_NEQ_SDD	(5 << 12)
> +#define   MI_SEMAPHORE_27_TOKEN_MASK	REG_GENMASK(9, 5)
> +#define   MI_SEMAPHORE_256_TOKEN_MASK	REG_GENMASK(9, 2)
> +#define   MI_SEMAPHORE_27_TOKEN_SHIFT	5
> +#define   MI_SEMAPHORE_256_TOKEN_SHIFT	2
> +#define MI_STORE_DATA_IMM	MI_INSTR(0x20, 0)
> +#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
> +#define MI_STORE_DWORD_IMM_GEN4	MI_INSTR(0x20, 2)
> +#define MI_STORE_QWORD_IMM_GEN8_POSTED (MI_INSTR(0x20, 3) | (1 << 21))
> +#define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | (1 << 10) | (1 << 21))
> +#define   MI_MEM_VIRTUAL	(1 << 22) /* 945,g33,965 */
> +#define   MI_USE_GGTT		(1 << 22) /* g4x+ */
> +#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
> +#define MI_ATOMIC		MI_INSTR(0x2f, 1)
> +#define MI_ATOMIC_INLINE	(MI_INSTR(0x2f, 9) | MI_ATOMIC_INLINE_DATA)
> +#define   MI_ATOMIC_GLOBAL_GTT		(1 << 22)
> +#define   MI_ATOMIC_INLINE_DATA		(1 << 18)
> +#define   MI_ATOMIC_CS_STALL		(1 << 17)
> +#define	  MI_ATOMIC_MOVE		(0x4 << 8)
> +#define	  MI_ATOMIC_INC			(0x5 << 8)
> +#define	  MI_ATOMIC_DEC			(0x6 << 8)
> +#define	  MI_ATOMIC_ADD			(0x7 << 8)
> +#define	  MI_ATOMIC_SUB			(0x8 << 8)
> +
> +/*
> + * Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
> + * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
> + *   simply ignores the register load under certain conditions.
> + * - One can actually load arbitrary many arbitrary registers: Simply issue x
> + *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
> + */
> +#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
> +/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
> +#define   MI_LRI_DEST_CS_MMIO		REG_BIT(19)
> +#define   MI_LRI_LRM_CS_MMIO		REG_BIT(19)
> +#define   MI_LRI_FORCE_POSTED		(1<<12)
> +#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
> +#define __MI_STORE_REGISTER_MEM      MI_INSTR(0x24, 0)
> +#define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
> +#define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
> +#define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)
> +#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
> +#define   MI_FLUSH_DW_PROTECTED_MEM_EN	(1 << 22)
> +#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
> +#define   MI_INVALIDATE_TLB		(1<<18)
> +#define   MI_FLUSH_CCS			(1<<16)
> +#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
> +#define   MI_FLUSH_DW_OP_MASK		(3<<14)
> +#define   MI_FLUSH_LLC			(1<<9)
> +#define   MI_FLUSH_DW_NOTIFY		(1<<8)
> +#define   MI_INVALIDATE_BSD		(1<<7)
> +#define   MI_FLUSH_DW_USE_GTT		(1<<2)
> +#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
> +#define __MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 0)
> +#define MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 1)
> +#define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
> +#define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 1)
> +#define   MI_LRR_SOURCE_CS_MMIO		REG_BIT(18)
> +#define   MI_LRR_DEST_CS_MMIO		REG_BIT(19)
> +#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
> +#define   MI_BATCH_NON_SECURE		(1)
> +/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
> +#define   MI_BATCH_NON_SECURE_I965	(1<<8)
> +#define   MI_BATCH_PPGTT_HSW		(1<<8)
> +#define   MI_BATCH_NON_SECURE_HSW	(1<<13)
> +#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
> +#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
> +#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
> +#define   MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
> +#define   MI_BATCH_PREDICATE         REG_BIT(15) /* HSW+ on RCS only*/
> +#define MI_COND_BATCH_BUFFER_END	MI_INSTR(0x36, 0)
> +#define   MI_DO_COMPARE				(1 << 21)
> +
> +/*
> + * 3D instructions used by the kernel
> + */
> +#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
> +
> +#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
> +#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
> +#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
> +#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
> +#define   SC_UPDATE_SCISSOR       (0x1<<1)
> +#define   SC_ENABLE_MASK          (0x1<<0)
> +#define   SC_ENABLE               (0x1<<0)
> +#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
> +#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
> +#define   SCI_YMIN_MASK      (0xffff<<16)
> +#define   SCI_XMIN_MASK      (0xffff<<0)
> +#define   SCI_YMAX_MASK      (0xffff<<16)
> +#define   SCI_XMAX_MASK      (0xffff<<0)
> +#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
> +#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
> +#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
> +#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
> +#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
> +#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
> +#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
> +#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
> +#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
> +
> +#define XY_CTRL_SURF_COPY_BLT		(2<<29 | 0x48<<22 | 3)
> +#define   SRC_ACCESS_TYPE_SHIFT		21
> +#define   DST_ACCESS_TYPE_SHIFT		20
> +#define   CCS_SIZE_SHIFT		8
> +/* Bspec lists field as [31:25], but index alone is at [31:26] */
> +#define   XY_CSC_BLT_MOCS_INDEX_MASK_GEN12	GENMASK(31, 26)
> +#define   XY_CSC_BLT_MOCS_INDEX_MASK_XE2	GENMASK(31, 28)
> +#define   NUM_CCS_BYTES_PER_BLOCK	256
> +#define   NUM_CCS_BLKS_PER_XFER	1024
> +#define   INDIRECT_ACCESS		0
> +#define   DIRECT_ACCESS		1
> +
> +#define COLOR_BLT_CMD			(2 << 29 | 0x40 << 22 | (5 - 2))
> +#define XY_BLOCK_COPY_BLT_CMD		(2 << 29 | 0x41 << 22)
> +#define   DEST_MEM_TYPE_SHIFT		(31)
> +#define   SRC_MEM_TYPE_SHIFT		(31)
> +#define   MEM_TYPE_SYS			1
> +#define   MEM_TYPE_LOCAL		0
> +#define   COMPRESSION_ENABLE		(1 << 29)
> +#define   AUX_CCS_E			(5 << 18)
> +#define   FULL_RESOLVE			(1 << 12)
> +#define   TILE_4_FORMAT			(2 << 30)
> +#define   TILE_4_WIDTH			(128)
> +#define   TILE_4_WIDTH_DWORD		((128 >> 2) - 1)
> +#define   TILE_4_HEIGHT			(32)
> +#define   SURFACE_TYPE_2D		(1 << 29)
> +#define   DEST_SURF_WIDTH_SHIFT		(14)
> +#define   SRC_SURF_WIDTH_SHIFT		(14)
> +/* Bspec lists this field as 27:21, but the index alone is in 27:22 */
> +#define   XY_BCB_MOCS_INDEX_MASK_GEN12	GENMASK(27, 22)
> +#define   XY_BCB_MOCS_INDEX_MASK_XE2	GENMASK(27, 24)
> +#define GEN9_XY_FAST_COPY_BLT_CMD	(2 << 29 | 0x42 << 22)
> +#define   XY_FAST_COPY_BLT_D0_SRC_TILING_MASK     REG_GENMASK(21, 20)
> +#define   XY_FAST_COPY_BLT_D0_DST_TILING_MASK     REG_GENMASK(14, 13)
> +#define   XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode)  \
> +	REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
> +#define   XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode)  \
> +	REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
> +#define     LINEAR				0
> +#define     TILE_X				0x1
> +#define     XMAJOR				0x1
> +#define     YMAJOR				0x2
> +#define     TILE_64			0x3
> +#define   XY_FAST_COPY_BLT_D1_SRC_TILE4	REG_BIT(31)
> +#define   XY_FAST_COPY_BLT_D1_DST_TILE4	REG_BIT(30)
> +#define   PVC_ENABLE_COMPRESSED_SURFACE	REG_BIT(16)
> +#define   XY_FCB_MOCS_INDEX_MASK_XE2	GENMASK(23, 20)
> +#define BLIT_CCTL_SRC_MOCS_MASK  REG_GENMASK(6, 0)
> +#define BLIT_CCTL_DST_MOCS_MASK  REG_GENMASK(14, 8)
> +/* Note:  MOCS value = (index << 1) */
> +#define BLIT_CCTL_SRC_MOCS(idx) \
> +	REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, idx << 1)
> +#define BLIT_CCTL_DST_MOCS(idx) \
> +	REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, idx << 1)
> +#define SRC_COPY_BLT_CMD		(2 << 29 | 0x43 << 22)
> +#define XY_FAST_COLOR_BLT		(2 << 29 | 0x44 << 22)
> +#define   BLT_COLOR_DEPTH_32		(2 << 19)
> +#define   BLT_COLOR_DEPTH_64		(3 << 19)
> +/* Bspec lists field as [27:21], but index resides in [27:22] */
> +#define   XY_FCB_MOCS_INDEX_MASK	GENMASK(27, 22)
> +#define XY_COLOR_BLT_CMD		(2 << 29 | 0x50 << 22)
> +#define XY_SRC_COPY_BLT_CMD		(2 << 29 | 0x53 << 22)
> +#define XY_MONO_SRC_COPY_IMM_BLT	(2 << 29 | 0x71 << 22 | 5)
> +#define   BLT_SRCMEM_SYS		(1<<29)
> +#define   BLT_WRITE_A			(2<<20)
> +#define   BLT_WRITE_RGB			(1<<20)
> +#define   BLT_WRITE_RGBA		(BLT_WRITE_RGB | BLT_WRITE_A)
> +#define   BLT_DEPTH_8			(0<<24)
> +#define   BLT_DEPTH_16_565		(1<<24)
> +#define   BLT_DEPTH_16_1555		(2<<24)
> +#define   BLT_DEPTH_32			(3<<24)
> +#define   BLT_ROP_SRC_COPY		(0xcc<<16)
> +#define   BLT_ROP_COLOR_COPY		(0xf0<<16)
> +#define PVC_MEM_COPY_CMD		(2 << 29 | 0x5a << 22)
> +#define   PVC_MEM_COPY_SRC_COMPRESSIBLE	BIT(16)
> +#define   PVC_MEM_COPY_DST_COMPRESSIBLE	BIT(15)
> +#define   PVC_MEM_COPY_DST_COMPRESS_EN	BIT(13)
> +#define   MEM_COPY_COMPRESSION_FMT_XEHPC	GENMASK(12, 8)
> +#define   MEM_COPY_COMPRESSION_FMT_XE2	GENMASK(12, 9)
> +/*
> + * Bspec lists MOCS fields as [31:25] and [6:0], but the actual indices are
> + * in [31:26] and [6:1].
> + */
> +#define   MC_SRC_MOCS_INDEX_MASK_GEN12	GENMASK(31, 26)
> +#define   MC_SRC_MOCS_INDEX_MASK_XE2	GENMASK(31, 28)
> +#define   MC_DST_MOCS_INDEX_MASK_GEN12	GENMASK(6, 1)
> +#define   MC_DST_MOCS_INDEX_MASK_XE2	GENMASK(6, 3)
> +#define PVC_MEM_SET_CMD			(2 << 29 | 0x5b << 22)
> +#define   PVC_MEM_SET_DST_COMPRESSIBLE	BIT(15)
> +#define   PVC_MEM_SET_DST_COMPRESS_EN	BIT(13)
> +#define   MEM_SET_COMPRESSION_FMT_XEHPC	GENMASK(12, 8)
> +#define   MEM_SET_COMPRESSION_FMT_XE2	GENMASK(12, 9)
> +/* Bspec lists field as [6:0], but index alone is from [6:1] */
> +#define   MS_MOCS_INDEX_MASK_GEN12	GENMASK(6, 1)
> +#define   MS_MOCS_INDEX_MASK_XE2	GENMASK(6, 3)
> +#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
> +#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
> +#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
> +#define   ASYNC_FLIP                (1<<22)
> +#define   DISPLAY_PLANE_A           (0<<20)
> +#define   DISPLAY_PLANE_B           (1<<20)
> +#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
> +#define   PIPE_CONTROL0_HDC_PIPELINE_FLUSH		BIT(9)  /* dword0, gen12 */
> +#define   PIPE_CONTROL0_DATAPORT_FLUSH_XE2		BIT(9)	/* dword0, xe2 */
> +#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
> +#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
> +#define   PIPE_CONTROL_FLUSH_L3				(1<<27)
> +#define   PIPE_CONTROL_AMFS_FLUSH			(1<<25) /* gen12+ */
> +#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
> +#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
> +#define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
> +#define   PIPE_CONTROL_CS_STALL				(1<<20)
> +#define   PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET		(1<<19)
> +#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
> +#define   PIPE_CONTROL_PSD_SYNC				(1<<17) /* gen11+ */
> +#define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
> +#define   PIPE_CONTROL_WRITE_TIMESTAMP			(3<<14)
> +#define   PIPE_CONTROL_QW_WRITE				(1<<14)
> +#define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
> +#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
> +#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
> +#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
> +#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on ILK */
> +#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
> +#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
> +#define   PIPE_CONTROL_NOTIFY				(1<<8)
> +#define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */
> +#define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
> +#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
> +#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
> +#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
> +#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
> +#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
> +#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
> +
> +/*
> + * 3D-related flags that can't be set on _engines_ that lack access to the 3D
> + * pipeline (i.e., CCS engines).
> + */
> +#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
> +		PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
> +		PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
> +		PIPE_CONTROL_TILE_CACHE_FLUSH | \
> +		PIPE_CONTROL_DEPTH_STALL | \
> +		PIPE_CONTROL_STALL_AT_SCOREBOARD | \
> +		PIPE_CONTROL_PSD_SYNC | \
> +		PIPE_CONTROL_AMFS_FLUSH | \
> +		PIPE_CONTROL_VF_CACHE_INVALIDATE | \
> +		PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
> +
> +/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
> +#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
> +		PIPE_CONTROL_3D_ENGINE_FLAGS | \
> +		PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
> +		PIPE_CONTROL_FLUSH_ENABLE | \
> +		PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
> +		PIPE_CONTROL_DC_FLUSH_ENABLE)
> +
> +#define MI_MATH(x)			MI_INSTR(0x1a, (x) - 1)
> +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> +/* Opcodes for MI_MATH_INSTR */
> +#define   MI_MATH_NOOP			MI_MATH_INSTR(0x000, 0x0, 0x0)
> +#define   MI_MATH_LOAD(op1, op2)	MI_MATH_INSTR(0x080, op1, op2)
> +#define   MI_MATH_LOADINV(op1, op2)	MI_MATH_INSTR(0x480, op1, op2)
> +#define   MI_MATH_LOAD0(op1)		MI_MATH_INSTR(0x081, op1, 0x0)
> +#define   MI_MATH_LOAD1(op1)		MI_MATH_INSTR(0x481, op1, 0x0)
> +#define   MI_MATH_ADD			MI_MATH_INSTR(0x100, 0x0, 0x0)
> +#define   MI_MATH_SUB			MI_MATH_INSTR(0x101, 0x0, 0x0)
> +#define   MI_MATH_AND			MI_MATH_INSTR(0x102, 0x0, 0x0)
> +#define   MI_MATH_OR			MI_MATH_INSTR(0x103, 0x0, 0x0)
> +#define   MI_MATH_XOR			MI_MATH_INSTR(0x104, 0x0, 0x0)
> +#define   MI_MATH_STORE(op1, op2)	MI_MATH_INSTR(0x180, op1, op2)
> +#define   MI_MATH_STOREINV(op1, op2)	MI_MATH_INSTR(0x580, op1, op2)
> +/* DG2+ */
> +#define   MI_MATH_SHR			MI_MATH_INSTR(0x106, 0x0, 0x0)
> +
> +/* Registers used as operands in MI_MATH_INSTR */
> +#define   MI_MATH_REG(x)		(x)
> +#define   MI_MATH_REG_SRCA		0x20
> +#define   MI_MATH_REG_SRCB		0x21
> +#define   MI_MATH_REG_ACCU		0x31
> +#define   MI_MATH_REG_ZF		0x32
> +#define   MI_MATH_REG_CF		0x33
> +
> +/*
> + * Media instructions used by the kernel
> + */
> +#define MEDIA_INSTR(pipe, op, sub_op, flags) \
> +	(__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
> +	(op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))
> +
> +#define MFX_WAIT				MEDIA_INSTR(1, 0, 0, 0)
> +#define  MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG	REG_BIT(8)
> +#define  MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG	REG_BIT(9)
> +
> +#define CRYPTO_KEY_EXCHANGE			MEDIA_INSTR(2, 6, 9, 0)
> +
> +/*
> + * Commands used only by the command parser
> + */
> +#define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
> +#define MI_ARB_CHECK            MI_INSTR(0x05, 0)
> +#define MI_RS_CONTROL           MI_INSTR(0x06, 0)
> +#define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
> +#define MI_PREDICATE            MI_INSTR(0x0C, 0)
> +#define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
> +#define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
> +#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
> +#define MI_URB_CLEAR            MI_INSTR(0x19, 0)
> +#define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
> +#define MI_CLFLUSH              MI_INSTR(0x27, 0)
> +#define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
> +#define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
> +#define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
> +#define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
> +#define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
> +#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
> +
> +#define STATE_SYSTEM_MEM_FENCE_ADDRESS \
> +	((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x9 << 16) | 0x1)
> +#define STATE_BASE_ADDRESS \
> +	((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x1 << 16))
> +#define BASE_ADDRESS_MODIFY		REG_BIT(0)
> +#define PIPELINE_SELECT \
> +	((0x3 << 29) | (0x1 << 27) | (0x1 << 24) | (0x4 << 16))
> +#define PIPELINE_SELECT_MEDIA	       REG_BIT(0)
> +#define GFX_OP_3DSTATE_VF_STATISTICS \
> +	((0x3 << 29) | (0x1 << 27) | (0x0 << 24) | (0xB << 16))
> +#define MEDIA_VFE_STATE \
> +	((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x0 << 16))
> +#define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
> +#define MEDIA_INTERFACE_DESCRIPTOR_LOAD \
> +	((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x2 << 16))
> +#define MEDIA_OBJECT \
> +	((0x3 << 29) | (0x2 << 27) | (0x1 << 24) | (0x0 << 16))
> +#define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
> +#define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
> +#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
> +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
> +#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
> +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
> +#define GFX_OP_3DSTATE_SO_DECL_LIST \
> +	((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
> +
> +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
> +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
> +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
> +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
> +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
> +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
> +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
> +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
> +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
> +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
> +
> +#define COLOR_BLT     ((0x2<<29)|(0x40<<22))
> +#define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))
> +
> +/* Bspec 63347*/
> +#define GSC_INSTR(opcode, data, flags) \
> +	(__INSTR(INSTR_GSC_CLIENT) | (opcode) << 22 | (data) << 9 | (flags))
> +
> +/* bspec 65346 */
> +#define GSC_FW_LOAD GSC_INSTR(1, 0, 2)
> +#define   HECI1_FW_LIMIT_VALID (1<<31)
> +
> +#define GSC_HECI_CMD_PKT GSC_INSTR(0, 0, 6)
> +
> +/*
> + * Used to convert an address to canonical form based on size of
> + * virtual address space.
> + * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
> + * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
> + * addresses to be in a canonical form:
> + * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
> + * canonical form [63:48] == [47]."
> + */
> +static inline u64 intel_canonical_addr(u32 ppgtt_msb, u64 address)
> +{
> +	return sign_extend64(address, ppgtt_msb);
> +}
> +
> +static inline u64 intel_noncanonical_addr(u32 ppgtt_msb, u64 address)
> +{
> +	return address & GENMASK_ULL(ppgtt_msb, 0);
> +}
> +
> +static inline u32 *__gen6_emit_bb_start(u32 *cs, u32 addr, unsigned int flags)
> +{
> +	*cs++ = MI_BATCH_BUFFER_START | flags;
> +	*cs++ = addr;
> +
> +	return cs;
> +}
> +
> +#endif /* _INTEL_GPU_COMMANDS_H_ */
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH i-g-t 1/2] lib: Copy intel_gpu_commands.h from the kernel

[Srivastava, Vikas]

Hi @Kempczynski, Zbigniew, 

Yeah I missed that , thanks for checking . 

Regards,
Vikas 

> -----Original Message-----
> From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
> Sent: Tuesday, March 7, 2023 10:24 PM
> To: Srivastava, Vikas <vikas.srivastava@intel.com>
> Cc: igt-dev@lists.freedesktop.org
> Subject: Re: [igt-dev] [PATCH i-g-t 1/2] lib: Copy intel_gpu_commands.h from
> the kernel
> 
> On Tue, Mar 07, 2023 at 09:51:45PM +0530, Vikas Srivastava wrote:
> > From: Chris Wilson <chris.p.wilson@linux.intel.com>
> >
> > Cherry picking this patch to fix conflicts while merging patch to
> > resolve gem_exec_await timeout issue.
> >
> > The current version of intel_gpu_commands lacks a few definitions and
> > has a couple of mistakes. This patch should be pushed to the kernel,
> > along with any other cleanups, and then copied back here.
> 
> Looks we worked on same thing:
> 
> https://patchwork.freedesktop.org/series/114619/
> 
> --
> Zbigniew
> 
> >
> > Signed-off-by: Chris Wilson <chris.p.wilson@linux.intel.com>
> > Signed-off-by: Vikas Srivastava <vikas.srivastava@intel.com>
> > ---
> >  include/intel_gpu_commands.h | 533
> > +++++++++++++++++++++++++++++++++++
> >  1 file changed, 533 insertions(+)
> >  create mode 100644 include/intel_gpu_commands.h
> >
> > diff --git a/include/intel_gpu_commands.h
> > b/include/intel_gpu_commands.h new file mode 100644 index
> > 000000000..b5239132f
> > --- /dev/null
> > +++ b/include/intel_gpu_commands.h
> > @@ -0,0 +1,533 @@
> > +/* SPDX-License-Identifier: MIT*/
> > +/*
> > + * Copyright (c) 2003-2018 Intel Corporation  */
> > +
> > +#ifndef _INTEL_GPU_COMMANDS_H_
> > +#define _INTEL_GPU_COMMANDS_H_
> > +
> > +#ifdef __KERNEL
> > +#include <linux/bitops.h>
> > +#else
> > +#include "linux_scaffold.h"
> > +#endif
> > +
> > +/*
> > + * Target address alignments required for GPU access e.g.
> > + * MI_STORE_DWORD_IMM.
> > + */
> > +#define alignof_dword 4
> > +#define alignof_qword 8
> > +
> > +/*
> > + * Instruction field definitions used by the command parser  */
> > +#define INSTR_CLIENT_SHIFT      29
> > +#define   INSTR_MI_CLIENT       0x0
> > +#define   INSTR_BC_CLIENT       0x2
> > +#define   INSTR_GSC_CLIENT      0x2 /* MTL + */
> > +#define   INSTR_RC_CLIENT       0x3
> > +#define INSTR_SUBCLIENT_SHIFT   27
> > +#define INSTR_SUBCLIENT_MASK    0x18000000
> > +#define   INSTR_MEDIA_SUBCLIENT 0x2
> > +#define INSTR_26_TO_24_MASK	0x7000000
> > +#define   INSTR_26_TO_24_SHIFT	24
> > +
> > +#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
> > +
> > +/*
> > + * Memory interface instructions used by the kernel  */ #define
> > +MI_INSTR(opcode, flags) \
> > +	(__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
> > +/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
> > +#define  MI_GLOBAL_GTT    (1<<22)
> > +
> > +#define MI_NOOP			MI_INSTR(0, 0)
> > +#define MI_SET_PREDICATE	MI_INSTR(0x01, 0)
> > +#define   MI_SET_PREDICATE_DISABLE	(0 << 0)
> > +#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
> > +#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
> > +#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
> > +#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
> > +#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
> > +#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
> > +#define MI_FLUSH		MI_INSTR(0x04, 0)
> > +#define   MI_READ_FLUSH		(1 << 0)
> > +#define   MI_EXE_FLUSH		(1 << 1)
> > +#define   MI_NO_WRITE_FLUSH	(1 << 2)
> > +#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
> > +#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene
> count */
> > +#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
> > +#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
> > +#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
> > +#define   MI_ARB_ENABLE			(1<<0)
> > +#define   MI_ARB_DISABLE		(0<<0)
> > +#define MI_MEM_FENCE		MI_INSTR(0x09, 0)
> > +#define MI_ACQUIRE_ENABLE	(1 << 0)
> > +#define MI_WRITE_FENCE		(3 << 0)
> > +#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
> > +#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
> > +#define   MI_SUSPEND_FLUSH_EN	(1<<0)
> > +#define MI_SET_APPID		MI_INSTR(0x0e, 0)
> > +#define   MI_SET_APPID_SESSION_ID(x)	((x) << 0)
> > +#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
> > +#define   MI_OVERLAY_CONTINUE	(0x0<<21)
> > +#define   MI_OVERLAY_ON		(0x1<<21)
> > +#define   MI_OVERLAY_OFF	(0x2<<21)
> > +#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
> > +#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
> > +#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
> > +#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
> > +/* IVB has funny definitions for which plane to flip. */
> > +#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
> > +#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
> > +#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
> > +#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
> > +#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
> > +#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
> > +/* SKL ones */
> > +#define   MI_DISPLAY_FLIP_SKL_PLANE_1_A	(0 << 8)
> > +#define   MI_DISPLAY_FLIP_SKL_PLANE_1_B	(1 << 8)
> > +#define   MI_DISPLAY_FLIP_SKL_PLANE_1_C	(2 << 8)
> > +#define   MI_DISPLAY_FLIP_SKL_PLANE_2_A	(4 << 8)
> > +#define   MI_DISPLAY_FLIP_SKL_PLANE_2_B	(5 << 8)
> > +#define   MI_DISPLAY_FLIP_SKL_PLANE_2_C	(6 << 8)
> > +#define   MI_DISPLAY_FLIP_SKL_PLANE_3_A	(7 << 8)
> > +#define   MI_DISPLAY_FLIP_SKL_PLANE_3_B	(8 << 8)
> > +#define   MI_DISPLAY_FLIP_SKL_PLANE_3_C	(9 << 8)
> > +#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
> > +#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
> > +#define   MI_SEMAPHORE_UPDATE	    (1<<21)
> > +#define   MI_SEMAPHORE_COMPARE	    (1<<20)
> > +#define   MI_SEMAPHORE_REGISTER	    (1<<18)
> > +#define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS
> (RVSYNC) */
> > +#define   MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS
> (RVESYNC) */
> > +#define   MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS
> (RBSYNC) */
> > +#define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS
> (VBSYNC) */
> > +#define   MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS
> (VVESYNC) */
> > +#define   MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS
> (VRSYNC) */
> > +#define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS
> (BRSYNC) */
> > +#define   MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS
> (BVESYNC) */
> > +#define   MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS
> (BVSYNC) */
> > +#define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS
> (VEBSYNC) */
> > +#define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS
> (VEVSYNC) */
> > +#define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS
> (VERSYNC) */
> > +#define   MI_SEMAPHORE_SYNC_INVALID (3<<16)
> > +#define   MI_SEMAPHORE_SYNC_MASK    (3<<16)
> > +#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
> > +#define   MI_MM_SPACE_GTT		(1<<8)
> > +#define   MI_MM_SPACE_PHYSICAL		(0<<8)
> > +#define   MI_SAVE_EXT_STATE_EN		(1<<3)
> > +#define   MI_RESTORE_EXT_STATE_EN	(1<<2)
> > +#define   MI_FORCE_RESTORE		(1<<1)
> > +#define   MI_RESTORE_INHIBIT		(1<<0)
> > +#define   HSW_MI_RS_SAVE_STATE_EN       (1<<3)
> > +#define   HSW_MI_RS_RESTORE_STATE_EN    (1<<2)
> > +#define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */
> > +#define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
> > +#define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
> > +#define MI_SEMAPHORE_WAIT_TOKEN	MI_INSTR(0x1c, 3) /* GEN12+
> */
> > +#define   MI_SEMAPHORE_POLL		(1 << 15)
> > +#define   MI_SEMAPHORE_SAD_GT_SDD	(0 << 12)
> > +#define   MI_SEMAPHORE_SAD_GTE_SDD	(1 << 12)
> > +#define   MI_SEMAPHORE_SAD_LT_SDD	(2 << 12)
> > +#define   MI_SEMAPHORE_SAD_LTE_SDD	(3 << 12)
> > +#define   MI_SEMAPHORE_SAD_EQ_SDD	(4 << 12)
> > +#define   MI_SEMAPHORE_SAD_NEQ_SDD	(5 << 12)
> > +#define   MI_SEMAPHORE_27_TOKEN_MASK	REG_GENMASK(9, 5)
> > +#define   MI_SEMAPHORE_256_TOKEN_MASK	REG_GENMASK(9, 2)
> > +#define   MI_SEMAPHORE_27_TOKEN_SHIFT	5
> > +#define   MI_SEMAPHORE_256_TOKEN_SHIFT	2
> > +#define MI_STORE_DATA_IMM	MI_INSTR(0x20, 0)
> > +#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
> > +#define MI_STORE_DWORD_IMM_GEN4	MI_INSTR(0x20, 2)
> > +#define MI_STORE_QWORD_IMM_GEN8_POSTED (MI_INSTR(0x20, 3) | (1 <<
> > +21)) #define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | (1 << 10)
> | (1 << 21))
> > +#define   MI_MEM_VIRTUAL	(1 << 22) /* 945,g33,965 */
> > +#define   MI_USE_GGTT		(1 << 22) /* g4x+ */
> > +#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
> > +#define MI_ATOMIC		MI_INSTR(0x2f, 1)
> > +#define MI_ATOMIC_INLINE	(MI_INSTR(0x2f, 9) |
> MI_ATOMIC_INLINE_DATA)
> > +#define   MI_ATOMIC_GLOBAL_GTT		(1 << 22)
> > +#define   MI_ATOMIC_INLINE_DATA		(1 << 18)
> > +#define   MI_ATOMIC_CS_STALL		(1 << 17)
> > +#define	  MI_ATOMIC_MOVE		(0x4 << 8)
> > +#define	  MI_ATOMIC_INC			(0x5 << 8)
> > +#define	  MI_ATOMIC_DEC			(0x6 << 8)
> > +#define	  MI_ATOMIC_ADD			(0x7 << 8)
> > +#define	  MI_ATOMIC_SUB			(0x8 << 8)
> > +
> > +/*
> > + * Official intel docs are somewhat sloppy concerning
> MI_LOAD_REGISTER_IMM:
> > + * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM -
> otherwise hw
> > + *   simply ignores the register load under certain conditions.
> > + * - One can actually load arbitrary many arbitrary registers: Simply issue x
> > + *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
> > + */
> > +#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
> > +/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
> > +#define   MI_LRI_DEST_CS_MMIO		REG_BIT(19)
> > +#define   MI_LRI_LRM_CS_MMIO		REG_BIT(19)
> > +#define   MI_LRI_FORCE_POSTED		(1<<12)
> > +#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
> > +#define __MI_STORE_REGISTER_MEM      MI_INSTR(0x24, 0)
> > +#define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
> > +#define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
> > +#define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)
> > +#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
> > +#define   MI_FLUSH_DW_PROTECTED_MEM_EN	(1 << 22)
> > +#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
> > +#define   MI_INVALIDATE_TLB		(1<<18)
> > +#define   MI_FLUSH_CCS			(1<<16)
> > +#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
> > +#define   MI_FLUSH_DW_OP_MASK		(3<<14)
> > +#define   MI_FLUSH_LLC			(1<<9)
> > +#define   MI_FLUSH_DW_NOTIFY		(1<<8)
> > +#define   MI_INVALIDATE_BSD		(1<<7)
> > +#define   MI_FLUSH_DW_USE_GTT		(1<<2)
> > +#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
> > +#define __MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 0)
> > +#define MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 1)
> > +#define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
> > +#define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 1)
> > +#define   MI_LRR_SOURCE_CS_MMIO		REG_BIT(18)
> > +#define   MI_LRR_DEST_CS_MMIO		REG_BIT(19)
> > +#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
> > +#define   MI_BATCH_NON_SECURE		(1)
> > +/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
> > +#define   MI_BATCH_NON_SECURE_I965	(1<<8)
> > +#define   MI_BATCH_PPGTT_HSW		(1<<8)
> > +#define   MI_BATCH_NON_SECURE_HSW	(1<<13)
> > +#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
> > +#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4
> */
> > +#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
> > +#define   MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
> > +#define   MI_BATCH_PREDICATE         REG_BIT(15) /* HSW+ on RCS only*/
> > +#define MI_COND_BATCH_BUFFER_END	MI_INSTR(0x36, 0)
> > +#define   MI_DO_COMPARE				(1 << 21)
> > +
> > +/*
> > + * 3D instructions used by the kernel  */ #define GFX_INSTR(opcode,
> > +flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
> > +
> > +#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16)
> | 4)
> > +#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
> > +#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
> > +#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
> > +#define   SC_UPDATE_SCISSOR       (0x1<<1)
> > +#define   SC_ENABLE_MASK          (0x1<<0)
> > +#define   SC_ENABLE               (0x1<<0)
> > +#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
> > +#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
> > +#define   SCI_YMIN_MASK      (0xffff<<16)
> > +#define   SCI_XMIN_MASK      (0xffff<<0)
> > +#define   SCI_YMAX_MASK      (0xffff<<16)
> > +#define   SCI_XMAX_MASK      (0xffff<<0)
> > +#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
> > +#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
> > +#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
> > +#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
> > +#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
> > +#define GFX_OP_DESTBUFFER_VARS
> ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
> > +#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
> > +#define GFX_OP_DRAWRECT_INFO
> ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
> > +#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
> > +
> > +#define XY_CTRL_SURF_COPY_BLT		(2<<29 | 0x48<<22 | 3)
> > +#define   SRC_ACCESS_TYPE_SHIFT		21
> > +#define   DST_ACCESS_TYPE_SHIFT		20
> > +#define   CCS_SIZE_SHIFT		8
> > +/* Bspec lists field as [31:25], but index alone is at [31:26] */
> > +#define   XY_CSC_BLT_MOCS_INDEX_MASK_GEN12	GENMASK(31, 26)
> > +#define   XY_CSC_BLT_MOCS_INDEX_MASK_XE2	GENMASK(31, 28)
> > +#define   NUM_CCS_BYTES_PER_BLOCK	256
> > +#define   NUM_CCS_BLKS_PER_XFER	1024
> > +#define   INDIRECT_ACCESS		0
> > +#define   DIRECT_ACCESS		1
> > +
> > +#define COLOR_BLT_CMD			(2 << 29 | 0x40 << 22 | (5 - 2))
> > +#define XY_BLOCK_COPY_BLT_CMD		(2 << 29 | 0x41 << 22)
> > +#define   DEST_MEM_TYPE_SHIFT		(31)
> > +#define   SRC_MEM_TYPE_SHIFT		(31)
> > +#define   MEM_TYPE_SYS			1
> > +#define   MEM_TYPE_LOCAL		0
> > +#define   COMPRESSION_ENABLE		(1 << 29)
> > +#define   AUX_CCS_E			(5 << 18)
> > +#define   FULL_RESOLVE			(1 << 12)
> > +#define   TILE_4_FORMAT			(2 << 30)
> > +#define   TILE_4_WIDTH			(128)
> > +#define   TILE_4_WIDTH_DWORD		((128 >> 2) - 1)
> > +#define   TILE_4_HEIGHT			(32)
> > +#define   SURFACE_TYPE_2D		(1 << 29)
> > +#define   DEST_SURF_WIDTH_SHIFT		(14)
> > +#define   SRC_SURF_WIDTH_SHIFT		(14)
> > +/* Bspec lists this field as 27:21, but the index alone is in 27:22 */
> > +#define   XY_BCB_MOCS_INDEX_MASK_GEN12	GENMASK(27, 22)
> > +#define   XY_BCB_MOCS_INDEX_MASK_XE2	GENMASK(27, 24)
> > +#define GEN9_XY_FAST_COPY_BLT_CMD	(2 << 29 | 0x42 << 22)
> > +#define   XY_FAST_COPY_BLT_D0_SRC_TILING_MASK     REG_GENMASK(21,
> 20)
> > +#define   XY_FAST_COPY_BLT_D0_DST_TILING_MASK     REG_GENMASK(14,
> 13)
> > +#define   XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode)  \
> > +	REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
> > +#define   XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode)  \
> > +	REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
> > +#define     LINEAR				0
> > +#define     TILE_X				0x1
> > +#define     XMAJOR				0x1
> > +#define     YMAJOR				0x2
> > +#define     TILE_64			0x3
> > +#define   XY_FAST_COPY_BLT_D1_SRC_TILE4	REG_BIT(31)
> > +#define   XY_FAST_COPY_BLT_D1_DST_TILE4	REG_BIT(30)
> > +#define   PVC_ENABLE_COMPRESSED_SURFACE	REG_BIT(16)
> > +#define   XY_FCB_MOCS_INDEX_MASK_XE2	GENMASK(23, 20)
> > +#define BLIT_CCTL_SRC_MOCS_MASK  REG_GENMASK(6, 0) #define
> > +BLIT_CCTL_DST_MOCS_MASK  REG_GENMASK(14, 8)
> > +/* Note:  MOCS value = (index << 1) */ #define
> > +BLIT_CCTL_SRC_MOCS(idx) \
> > +	REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, idx << 1) #define
> > +BLIT_CCTL_DST_MOCS(idx) \
> > +	REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, idx << 1)
> > +#define SRC_COPY_BLT_CMD		(2 << 29 | 0x43 << 22)
> > +#define XY_FAST_COLOR_BLT		(2 << 29 | 0x44 << 22)
> > +#define   BLT_COLOR_DEPTH_32		(2 << 19)
> > +#define   BLT_COLOR_DEPTH_64		(3 << 19)
> > +/* Bspec lists field as [27:21], but index resides in [27:22] */
> > +#define   XY_FCB_MOCS_INDEX_MASK	GENMASK(27, 22)
> > +#define XY_COLOR_BLT_CMD		(2 << 29 | 0x50 << 22)
> > +#define XY_SRC_COPY_BLT_CMD		(2 << 29 | 0x53 << 22)
> > +#define XY_MONO_SRC_COPY_IMM_BLT	(2 << 29 | 0x71 << 22 | 5)
> > +#define   BLT_SRCMEM_SYS		(1<<29)
> > +#define   BLT_WRITE_A			(2<<20)
> > +#define   BLT_WRITE_RGB			(1<<20)
> > +#define   BLT_WRITE_RGBA		(BLT_WRITE_RGB | BLT_WRITE_A)
> > +#define   BLT_DEPTH_8			(0<<24)
> > +#define   BLT_DEPTH_16_565		(1<<24)
> > +#define   BLT_DEPTH_16_1555		(2<<24)
> > +#define   BLT_DEPTH_32			(3<<24)
> > +#define   BLT_ROP_SRC_COPY		(0xcc<<16)
> > +#define   BLT_ROP_COLOR_COPY		(0xf0<<16)
> > +#define PVC_MEM_COPY_CMD		(2 << 29 | 0x5a << 22)
> > +#define   PVC_MEM_COPY_SRC_COMPRESSIBLE	BIT(16)
> > +#define   PVC_MEM_COPY_DST_COMPRESSIBLE	BIT(15)
> > +#define   PVC_MEM_COPY_DST_COMPRESS_EN	BIT(13)
> > +#define   MEM_COPY_COMPRESSION_FMT_XEHPC	GENMASK(12, 8)
> > +#define   MEM_COPY_COMPRESSION_FMT_XE2	GENMASK(12, 9)
> > +/*
> > + * Bspec lists MOCS fields as [31:25] and [6:0], but the actual
> > +indices are
> > + * in [31:26] and [6:1].
> > + */
> > +#define   MC_SRC_MOCS_INDEX_MASK_GEN12	GENMASK(31, 26)
> > +#define   MC_SRC_MOCS_INDEX_MASK_XE2	GENMASK(31, 28)
> > +#define   MC_DST_MOCS_INDEX_MASK_GEN12	GENMASK(6, 1)
> > +#define   MC_DST_MOCS_INDEX_MASK_XE2	GENMASK(6, 3)
> > +#define PVC_MEM_SET_CMD			(2 << 29 | 0x5b << 22)
> > +#define   PVC_MEM_SET_DST_COMPRESSIBLE	BIT(15)
> > +#define   PVC_MEM_SET_DST_COMPRESS_EN	BIT(13)
> > +#define   MEM_SET_COMPRESSION_FMT_XEHPC	GENMASK(12, 8)
> > +#define   MEM_SET_COMPRESSION_FMT_XE2	GENMASK(12, 9)
> > +/* Bspec lists field as [6:0], but index alone is from [6:1] */
> > +#define   MS_MOCS_INDEX_MASK_GEN12	GENMASK(6, 1)
> > +#define   MS_MOCS_INDEX_MASK_XE2	GENMASK(6, 3)
> > +#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
> > +#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
> > +#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
> > +#define   ASYNC_FLIP                (1<<22)
> > +#define   DISPLAY_PLANE_A           (0<<20)
> > +#define   DISPLAY_PLANE_B           (1<<20)
> > +#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-
> 2))
> > +#define   PIPE_CONTROL0_HDC_PIPELINE_FLUSH		BIT(9)  /*
> dword0, gen12 */
> > +#define   PIPE_CONTROL0_DATAPORT_FLUSH_XE2		BIT(9)	/*
> dword0, xe2 */
> > +#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE
> 	(1<<29) /* gen11+ */
> > +#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /*
> gen11+ */
> > +#define   PIPE_CONTROL_FLUSH_L3				(1<<27)
> > +#define   PIPE_CONTROL_AMFS_FLUSH			(1<<25) /*
> gen12+ */
> > +#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /*
> gen7+ */
> > +#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
> > +#define   PIPE_CONTROL_STORE_DATA_INDEX
> 	(1<<21)
> > +#define   PIPE_CONTROL_CS_STALL				(1<<20)
> > +#define   PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET		(1<<19)
> > +#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
> > +#define   PIPE_CONTROL_PSD_SYNC				(1<<17) /*
> gen11+ */
> > +#define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
> > +#define   PIPE_CONTROL_WRITE_TIMESTAMP
> 	(3<<14)
> > +#define   PIPE_CONTROL_QW_WRITE				(1<<14)
> > +#define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
> > +#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
> > +#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
> > +#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /*
> gen6+ */
> > +#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /*
> MBZ on ILK */
> > +#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
> 	(1<<10) /* GM45+ only */
> > +#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
> > +#define   PIPE_CONTROL_NOTIFY				(1<<8)
> > +#define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /*
> gen7+ */
> > +#define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
> > +#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
> > +#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
> > +#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
> > +#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
> > +#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
> > +#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
> > +
> > +/*
> > + * 3D-related flags that can't be set on _engines_ that lack access
> > +to the 3D
> > + * pipeline (i.e., CCS engines).
> > + */
> > +#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
> > +		PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
> > +		PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
> > +		PIPE_CONTROL_TILE_CACHE_FLUSH | \
> > +		PIPE_CONTROL_DEPTH_STALL | \
> > +		PIPE_CONTROL_STALL_AT_SCOREBOARD | \
> > +		PIPE_CONTROL_PSD_SYNC | \
> > +		PIPE_CONTROL_AMFS_FLUSH | \
> > +		PIPE_CONTROL_VF_CACHE_INVALIDATE | \
> > +		PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
> > +
> > +/* 3D-related flags that can't be set on _platforms_ that lack a 3D
> > +pipeline */ #define PIPE_CONTROL_3D_ARCH_FLAGS ( \
> > +		PIPE_CONTROL_3D_ENGINE_FLAGS | \
> > +		PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
> > +		PIPE_CONTROL_FLUSH_ENABLE | \
> > +		PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
> > +		PIPE_CONTROL_DC_FLUSH_ENABLE)
> > +
> > +#define MI_MATH(x)			MI_INSTR(0x1a, (x) - 1)
> > +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10
> > +| (op2))
> > +/* Opcodes for MI_MATH_INSTR */
> > +#define   MI_MATH_NOOP			MI_MATH_INSTR(0x000, 0x0,
> 0x0)
> > +#define   MI_MATH_LOAD(op1, op2)	MI_MATH_INSTR(0x080, op1, op2)
> > +#define   MI_MATH_LOADINV(op1, op2)	MI_MATH_INSTR(0x480, op1,
> op2)
> > +#define   MI_MATH_LOAD0(op1)		MI_MATH_INSTR(0x081, op1,
> 0x0)
> > +#define   MI_MATH_LOAD1(op1)		MI_MATH_INSTR(0x481, op1,
> 0x0)
> > +#define   MI_MATH_ADD			MI_MATH_INSTR(0x100, 0x0,
> 0x0)
> > +#define   MI_MATH_SUB			MI_MATH_INSTR(0x101, 0x0,
> 0x0)
> > +#define   MI_MATH_AND			MI_MATH_INSTR(0x102, 0x0,
> 0x0)
> > +#define   MI_MATH_OR			MI_MATH_INSTR(0x103, 0x0,
> 0x0)
> > +#define   MI_MATH_XOR			MI_MATH_INSTR(0x104, 0x0,
> 0x0)
> > +#define   MI_MATH_STORE(op1, op2)	MI_MATH_INSTR(0x180, op1, op2)
> > +#define   MI_MATH_STOREINV(op1, op2)	MI_MATH_INSTR(0x580, op1,
> op2)
> > +/* DG2+ */
> > +#define   MI_MATH_SHR			MI_MATH_INSTR(0x106, 0x0,
> 0x0)
> > +
> > +/* Registers used as operands in MI_MATH_INSTR */
> > +#define   MI_MATH_REG(x)		(x)
> > +#define   MI_MATH_REG_SRCA		0x20
> > +#define   MI_MATH_REG_SRCB		0x21
> > +#define   MI_MATH_REG_ACCU		0x31
> > +#define   MI_MATH_REG_ZF		0x32
> > +#define   MI_MATH_REG_CF		0x33
> > +
> > +/*
> > + * Media instructions used by the kernel  */ #define
> > +MEDIA_INSTR(pipe, op, sub_op, flags) \
> > +	(__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
> > +	(op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))
> > +
> > +#define MFX_WAIT				MEDIA_INSTR(1, 0, 0, 0)
> > +#define  MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG	REG_BIT(8)
> > +#define  MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG	REG_BIT(9)
> > +
> > +#define CRYPTO_KEY_EXCHANGE			MEDIA_INSTR(2, 6, 9,
> 0)
> > +
> > +/*
> > + * Commands used only by the command parser  */
> > +#define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
> > +#define MI_ARB_CHECK            MI_INSTR(0x05, 0)
> > +#define MI_RS_CONTROL           MI_INSTR(0x06, 0)
> > +#define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
> > +#define MI_PREDICATE            MI_INSTR(0x0C, 0)
> > +#define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
> > +#define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
> > +#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
> > +#define MI_URB_CLEAR            MI_INSTR(0x19, 0)
> > +#define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
> > +#define MI_CLFLUSH              MI_INSTR(0x27, 0)
> > +#define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
> > +#define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
> > +#define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
> > +#define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
> > +#define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
> > +#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
> > +
> > +#define STATE_SYSTEM_MEM_FENCE_ADDRESS \
> > +	((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x9 << 16) | 0x1)
> > +#define STATE_BASE_ADDRESS \
> > +	((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x1 << 16))
> > +#define BASE_ADDRESS_MODIFY		REG_BIT(0)
> > +#define PIPELINE_SELECT \
> > +	((0x3 << 29) | (0x1 << 27) | (0x1 << 24) | (0x4 << 16))
> > +#define PIPELINE_SELECT_MEDIA	       REG_BIT(0)
> > +#define GFX_OP_3DSTATE_VF_STATISTICS \
> > +	((0x3 << 29) | (0x1 << 27) | (0x0 << 24) | (0xB << 16)) #define
> > +MEDIA_VFE_STATE \
> > +	((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x0 << 16)) #define
> > +MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) #define
> > +MEDIA_INTERFACE_DESCRIPTOR_LOAD \
> > +	((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x2 << 16)) #define
> > +MEDIA_OBJECT \
> > +	((0x3 << 29) | (0x2 << 27) | (0x1 << 24) | (0x0 << 16))
> > +#define GPGPU_OBJECT
> ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
> > +#define GPGPU_WALKER
> ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
> > +#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
> > +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
> > +#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
> > +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
> > +#define GFX_OP_3DSTATE_SO_DECL_LIST \
> > +	((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
> > +
> > +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
> > +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
> > +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
> > +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
> > +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
> > +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
> > +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
> > +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
> > +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
> > +	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
> > +
> > +#define COLOR_BLT     ((0x2<<29)|(0x40<<22))
> > +#define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))
> > +
> > +/* Bspec 63347*/
> > +#define GSC_INSTR(opcode, data, flags) \
> > +	(__INSTR(INSTR_GSC_CLIENT) | (opcode) << 22 | (data) << 9 | (flags))
> > +
> > +/* bspec 65346 */
> > +#define GSC_FW_LOAD GSC_INSTR(1, 0, 2)
> > +#define   HECI1_FW_LIMIT_VALID (1<<31)
> > +
> > +#define GSC_HECI_CMD_PKT GSC_INSTR(0, 0, 6)
> > +
> > +/*
> > + * Used to convert an address to canonical form based on size of
> > + * virtual address space.
> > + * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
> > + * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require
> > +the
> > + * addresses to be in a canonical form:
> > + * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in
> > +correct
> > + * canonical form [63:48] == [47]."
> > + */
> > +static inline u64 intel_canonical_addr(u32 ppgtt_msb, u64 address) {
> > +	return sign_extend64(address, ppgtt_msb); }
> > +
> > +static inline u64 intel_noncanonical_addr(u32 ppgtt_msb, u64 address)
> > +{
> > +	return address & GENMASK_ULL(ppgtt_msb, 0); }
> > +
> > +static inline u32 *__gen6_emit_bb_start(u32 *cs, u32 addr, unsigned
> > +int flags) {
> > +	*cs++ = MI_BATCH_BUFFER_START | flags;
> > +	*cs++ = addr;
> > +
> > +	return cs;
> > +}
> > +
> > +#endif /* _INTEL_GPU_COMMANDS_H_ */
> > --
> > 2.25.1
> >

[igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] lib: Copy intel_gpu_commands.h from the kernel

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4874 bytes --]

== Series Details ==

Series: series starting with [i-g-t,1/2] lib: Copy intel_gpu_commands.h from the kernel
URL   : https://patchwork.freedesktop.org/series/114783/
State : success

== Summary ==

CI Bug Log - changes from IGT_7183 -> IGTPW_8569
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/index.html

Participating hosts (36 -> 34)
------------------------------

  Missing    (2): bat-dg1-6 fi-snb-2520m 

Known issues
------------

  Here are the changes found in IGTPW_8569 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@migrate:
    - bat-dg2-11:         [PASS][1] -> [DMESG-WARN][2] ([i915#7699])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/bat-dg2-11/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@requests:
    - bat-rpls-2:         [PASS][3] -> [ABORT][4] ([i915#4983] / [i915#7694] / [i915#7913] / [i915#7981])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/bat-rpls-2/igt@i915_selftest@live@requests.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/bat-rpls-2/igt@i915_selftest@live@requests.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - fi-bsw-nick:        NOTRUN -> [SKIP][5] ([fdo#109271]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/fi-bsw-nick/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
    - bat-rplp-1:         NOTRUN -> [SKIP][6] ([i915#7828])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/bat-rplp-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
    - bat-rpls-1:         NOTRUN -> [SKIP][7] ([i915#7828])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/bat-rpls-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - bat-rpls-1:         NOTRUN -> [SKIP][8] ([i915#1845])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/bat-rpls-1/igt@kms_pipe_crc_basic@suspend-read-crc.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - bat-rpls-1:         [ABORT][9] ([i915#6687] / [i915#7978]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [INCOMPLETE][11] ([i915#7913]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@requests:
    - bat-rplp-1:         [ABORT][13] ([i915#7913]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/bat-rplp-1/igt@i915_selftest@live@requests.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/bat-rplp-1/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@slpc:
    - bat-rpls-1:         [DMESG-FAIL][15] ([i915#6367] / [i915#7996]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/bat-rpls-1/igt@i915_selftest@live@slpc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/bat-rpls-1/igt@i915_selftest@live@slpc.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7694]: https://gitlab.freedesktop.org/drm/intel/issues/7694
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
  [i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
  [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7183 -> IGTPW_8569

  CI-20190529: 20190529
  CI_DRM_12821: 24f94240c4bca70cadfd00528ffd56c3049e5f58 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8569: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/index.html
  IGT_7183: 3434cef8be4e487644a740039ad15123cd094526 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/index.html

[-- Attachment #2: Type: text/html, Size: 5885 bytes --]

[igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/2] lib: Copy intel_gpu_commands.h from the kernel

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 43529 bytes --]

== Series Details ==

Series: series starting with [i-g-t,1/2] lib: Copy intel_gpu_commands.h from the kernel
URL   : https://patchwork.freedesktop.org/series/114783/
State : success

== Summary ==

CI Bug Log - changes from IGT_7183_full -> IGTPW_8569_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/index.html

Participating hosts (8 -> 10)
------------------------------

  Additional (2): shard-tglu-9 shard-tglu0 

Known issues
------------

  Here are the changes found in IGTPW_8569_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - shard-tglu-10:      NOTRUN -> [SKIP][1] ([i915#7456])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@debugfs_test@basic-hwmon.html

  * igt@drm_buddy@all-tests:
    - shard-tglu-10:      NOTRUN -> [SKIP][2] ([i915#6433])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@drm_buddy@all-tests.html

  * igt@fbdev@pan:
    - shard-tglu-9:       NOTRUN -> [SKIP][3] ([i915#2582])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@fbdev@pan.html

  * igt@feature_discovery@display-2x:
    - shard-tglu-9:       NOTRUN -> [SKIP][4] ([i915#1839])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@feature_discovery@display-2x.html

  * igt@feature_discovery@display-3x:
    - shard-tglu-10:      NOTRUN -> [SKIP][5] ([i915#1839])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@feature_discovery@display-3x.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-tglu-9:       NOTRUN -> [SKIP][6] ([i915#3555] / [i915#5325])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-tglu-9:       NOTRUN -> [SKIP][7] ([i915#6335])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-glk6/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-glk:          [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-glk4/igt@gem_exec_fair@basic-none-share@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-glk4/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-tglu-9:       NOTRUN -> [FAIL][11] ([i915#2842]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglu-10:      NOTRUN -> [FAIL][12] ([i915#2842]) +4 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_params@secure-non-root:
    - shard-tglu-9:       NOTRUN -> [SKIP][13] ([fdo#112283]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gem_exec_params@secure-non-root.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglu-9:       NOTRUN -> [SKIP][14] ([i915#2190])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-tglu-10:      NOTRUN -> [SKIP][15] ([i915#4613])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-tglu-9:       NOTRUN -> [SKIP][16] ([i915#4613]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-apl:          NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-apl4/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-tglu-9:       NOTRUN -> [WARN][18] ([i915#2658])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@reject-modify-context-protection-on:
    - shard-tglu-9:       NOTRUN -> [SKIP][19] ([i915#4270]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gem_pxp@reject-modify-context-protection-on.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
    - shard-tglu-10:      NOTRUN -> [SKIP][20] ([i915#4270]) +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@gem_pxp@verify-pxp-stale-ctx-execution.html

  * igt@gem_softpin@evict-snoop:
    - shard-tglu-10:      NOTRUN -> [SKIP][21] ([fdo#109312])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@gem_softpin@evict-snoop.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-tglu-9:       NOTRUN -> [SKIP][22] ([i915#3297])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen3_render_tiledy_blits:
    - shard-tglu-9:       NOTRUN -> [SKIP][23] ([fdo#109289]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gen3_render_tiledy_blits.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-apl:          [PASS][24] -> [ABORT][25] ([i915#5566])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-apl4/igt@gen9_exec_parse@allowed-single.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-apl2/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-tglu-9:       NOTRUN -> [SKIP][26] ([i915#2527] / [i915#2856]) +3 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-tglu-10:      NOTRUN -> [SKIP][27] ([i915#2527] / [i915#2856]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@gen9_exec_parse@unaligned-jump.html

  * igt@i915_module_load@resize-bar:
    - shard-tglu-10:      NOTRUN -> [SKIP][28] ([i915#6412])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_backlight@bad-brightness:
    - shard-tglu-10:      NOTRUN -> [SKIP][29] ([i915#7561]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@i915_pm_backlight@bad-brightness.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-tglu-9:       NOTRUN -> [SKIP][30] ([i915#658])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-tglu-9:       NOTRUN -> [SKIP][31] ([i915#6590])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - shard-tglu-9:       NOTRUN -> [SKIP][32] ([i915#1397])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@i915_pm_rpm@pm-tiling:
    - shard-tglu-9:       NOTRUN -> [SKIP][33] ([i915#3547]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@i915_pm_rpm@pm-tiling.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-tglu-10:      NOTRUN -> [SKIP][34] ([i915#5286]) +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-tglu-10:      NOTRUN -> [SKIP][35] ([fdo#111614]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-tglu-10:      NOTRUN -> [SKIP][36] ([fdo#111615]) +2 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs:
    - shard-tglu-10:      NOTRUN -> [SKIP][37] ([fdo#111615] / [i915#3689]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
    - shard-tglu-10:      NOTRUN -> [SKIP][38] ([i915#3689] / [i915#6095]) +5 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs:
    - shard-tglu-9:       NOTRUN -> [SKIP][39] ([fdo#111615] / [i915#1845] / [i915#7651]) +7 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#3886]) +2 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-apl6/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-glk5/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-tglu-9:       NOTRUN -> [SKIP][42] ([i915#1845] / [i915#7651]) +72 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-tglu-10:      NOTRUN -> [SKIP][43] ([i915#3689] / [i915#3886]) +3 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_mc_ccs:
    - shard-tglu-10:      NOTRUN -> [SKIP][44] ([i915#3689]) +5 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
    - shard-tglu-10:      NOTRUN -> [SKIP][45] ([i915#6095]) +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-tglu-10:      NOTRUN -> [SKIP][46] ([i915#3742])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-tglu-9:       NOTRUN -> [SKIP][47] ([fdo#111827])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-tglu-10:      NOTRUN -> [SKIP][48] ([i915#7828]) +5 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-tglu-9:       NOTRUN -> [SKIP][49] ([i915#7828]) +5 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_color@degamma:
    - shard-tglu-9:       NOTRUN -> [SKIP][50] ([i915#3546])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_color@degamma.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-tglu-10:      NOTRUN -> [SKIP][51] ([i915#3359]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-tglu-10:      NOTRUN -> [SKIP][52] ([fdo#109274]) +1 similar issue
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-tglu-10:      NOTRUN -> [SKIP][53] ([i915#4103])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [PASS][54] -> [FAIL][55] ([i915#2346])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size:
    - shard-tglu-9:       NOTRUN -> [SKIP][56] ([i915#1845]) +21 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-tglu-10:      NOTRUN -> [SKIP][57] ([i915#3840])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-tglu-10:      NOTRUN -> [SKIP][58] ([fdo#109274] / [i915#3637]) +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-nonexisting-fb-interruptible:
    - shard-tglu-9:       NOTRUN -> [SKIP][59] ([fdo#109274] / [i915#3637]) +5 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_flip@2x-nonexisting-fb-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-apl:          [PASS][60] -> [ABORT][61] ([i915#180])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@nonexisting-fb:
    - shard-tglu-9:       NOTRUN -> [SKIP][62] ([i915#3637]) +6 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_flip@nonexisting-fb.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
    - shard-tglu-10:      NOTRUN -> [SKIP][63] ([i915#2587] / [i915#2672]) +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-tglu-9:       NOTRUN -> [SKIP][64] ([i915#3555]) +13 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-apl:          NOTRUN -> [SKIP][65] ([fdo#109271]) +94 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-apl7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-tglu-10:      NOTRUN -> [SKIP][66] ([fdo#110189]) +17 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-tglu-10:      NOTRUN -> [SKIP][67] ([fdo#109280]) +21 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-slowdraw:
    - shard-glk:          NOTRUN -> [SKIP][68] ([fdo#109271]) +17 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-glk5/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-tglu-10:      NOTRUN -> [SKIP][69] ([i915#5439])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
    - shard-tglu-9:       NOTRUN -> [SKIP][70] ([i915#1849]) +50 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_hdr@bpc-switch:
    - shard-tglu-10:      NOTRUN -> [SKIP][71] ([i915#3555]) +7 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_hdr@bpc-switch.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-tglu-9:       NOTRUN -> [SKIP][72] ([i915#1849] / [i915#3558]) +1 similar issue
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@alpha-basic:
    - shard-tglu-9:       NOTRUN -> [SKIP][73] ([i915#7128] / [i915#7294])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_plane_alpha_blend@alpha-basic.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-tglu-10:      NOTRUN -> [SKIP][74] ([fdo#112054] / [i915#5288])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_prime@d3hot:
    - shard-tglu-10:      NOTRUN -> [SKIP][75] ([i915#6524])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-tglu-9:       NOTRUN -> [SKIP][76] ([fdo#111068] / [i915#658])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
    - shard-tglu-10:      NOTRUN -> [SKIP][77] ([fdo#111068] / [i915#658])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-tglu-10:      NOTRUN -> [SKIP][78] ([fdo#109642] / [fdo#111068] / [i915#658])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-glk:          NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-glk7/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@primary_page_flip:
    - shard-tglu-9:       NOTRUN -> [SKIP][80] ([fdo#110189]) +5 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_psr@primary_page_flip.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-tglu-10:      NOTRUN -> [SKIP][81] ([i915#5289])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-tglu-9:       NOTRUN -> [SKIP][82] ([fdo#109309])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-b:
    - shard-tglu-9:       NOTRUN -> [SKIP][83] ([fdo#109274]) +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@kms_universal_plane@disable-primary-vs-flip-pipe-b.html

  * igt@perf_pmu@event-wait@rcs0:
    - shard-tglu-10:      NOTRUN -> [SKIP][84] ([fdo#112283])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@perf_pmu@event-wait@rcs0.html

  * igt@prime_vgem@fence-write-hang:
    - shard-tglu-9:       NOTRUN -> [SKIP][85] ([fdo#109295])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@prime_vgem@fence-write-hang.html

  * igt@v3d/v3d_create_bo@create-bo-zeroed:
    - shard-tglu-10:      NOTRUN -> [SKIP][86] ([fdo#109315] / [i915#2575]) +1 similar issue
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@v3d/v3d_create_bo@create-bo-zeroed.html

  * igt@v3d/v3d_perfmon@destroy-valid-perfmon:
    - shard-tglu-9:       NOTRUN -> [SKIP][87] ([fdo#109315] / [i915#2575]) +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@v3d/v3d_perfmon@destroy-valid-perfmon.html

  * igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done:
    - shard-tglu-9:       NOTRUN -> [SKIP][88] ([i915#2575]) +6 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-9/igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done.html

  * igt@vc4/vc4_mmap@mmap-bad-handle:
    - shard-tglu-10:      NOTRUN -> [SKIP][89] ([i915#2575]) +4 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-tglu-10/igt@vc4/vc4_mmap@mmap-bad-handle.html

  
#### Possible fixes ####

  * {igt@gem_barrier_race@remote-request@rcs0}:
    - shard-apl:          [ABORT][90] ([i915#8211] / [i915#8234]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-apl1/igt@gem_barrier_race@remote-request@rcs0.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-apl1/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_ctx_persistence@hang:
    - {shard-rkl}:        [SKIP][92] ([i915#6252]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-5/igt@gem_ctx_persistence@hang.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-6/igt@gem_ctx_persistence@hang.html

  * igt@gem_eio@suspend:
    - {shard-rkl}:        [FAIL][94] ([i915#5115] / [i915#7052]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-4/igt@gem_eio@suspend.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-6/igt@gem_eio@suspend.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - {shard-rkl}:        [FAIL][96] ([i915#2842]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-5/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-4/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-glk:          [FAIL][98] ([i915#2842]) -> [PASS][99] +1 similar issue
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-glk5/igt@gem_exec_fair@basic-pace@vcs0.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-glk6/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - {shard-rkl}:        [SKIP][100] ([i915#3281]) -> [PASS][101] +10 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-1/igt@gem_exec_reloc@basic-write-read-noreloc.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_mmap_gtt@coherency:
    - {shard-rkl}:        [SKIP][102] ([fdo#111656]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-2/igt@gem_mmap_gtt@coherency.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-5/igt@gem_mmap_gtt@coherency.html

  * igt@gem_pread@bench:
    - {shard-rkl}:        [SKIP][104] ([i915#3282]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-1/igt@gem_pread@bench.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-5/igt@gem_pread@bench.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [ABORT][106] ([i915#5566]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-apl7/igt@gen9_exec_parse@allowed-all.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-apl1/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@bb-chained:
    - {shard-rkl}:        [SKIP][108] ([i915#2527]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-4/igt@gen9_exec_parse@bb-chained.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-5/igt@gen9_exec_parse@bb-chained.html

  * igt@i915_hangman@engine-engine-error@bcs0:
    - {shard-rkl}:        [SKIP][110] ([i915#6258]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-5/igt@i915_hangman@engine-engine-error@bcs0.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-2/igt@i915_hangman@engine-engine-error@bcs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - {shard-rkl}:        [WARN][112] ([i915#2681]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
    - {shard-dg1}:        [FAIL][114] ([i915#3591]) -> [PASS][115] +1 similar issue
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - {shard-dg1}:        [SKIP][116] ([i915#1397]) -> [PASS][117] +1 similar issue
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-dg1-14/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-dg1-17/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@i915_selftest@live@gem_contexts:
    - {shard-rkl}:        [ABORT][118] ([i915#7913]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-3/igt@i915_selftest@live@gem_contexts.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-4/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - {shard-rkl}:        [FAIL][120] ([fdo#103375]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-4/igt@i915_suspend@fence-restore-tiled2untiled.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-5/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1:
    - shard-apl:          [ABORT][122] ([i915#180]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-apl2/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-apl2/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [FAIL][124] ([i915#2346]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - {shard-rkl}:        [SKIP][126] ([i915#1849] / [i915#4098]) -> [PASS][127] +15 similar issues
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_properties@crtc-properties-atomic:
    - {shard-rkl}:        [SKIP][128] ([i915#1849]) -> [PASS][129] +1 similar issue
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-2/igt@kms_properties@crtc-properties-atomic.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-6/igt@kms_properties@crtc-properties-atomic.html

  * igt@kms_psr@primary_mmap_cpu:
    - {shard-rkl}:        [SKIP][130] ([i915#1072]) -> [PASS][131] +1 similar issue
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-2/igt@kms_psr@primary_mmap_cpu.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-6/igt@kms_psr@primary_mmap_cpu.html

  * igt@kms_vblank@pipe-a-query-busy-hang:
    - shard-apl:          [SKIP][132] ([fdo#109271]) -> [PASS][133] +2 similar issues
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-apl1/igt@kms_vblank@pipe-a-query-busy-hang.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-apl1/igt@kms_vblank@pipe-a-query-busy-hang.html

  * igt@kms_vblank@pipe-b-query-forked-hang:
    - shard-glk:          [SKIP][134] ([fdo#109271]) -> [PASS][135] +1 similar issue
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-glk6/igt@kms_vblank@pipe-b-query-forked-hang.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-glk8/igt@kms_vblank@pipe-b-query-forked-hang.html

  * igt@kms_vblank@pipe-b-query-idle:
    - {shard-rkl}:        [SKIP][136] ([i915#1845] / [i915#4098]) -> [PASS][137] +17 similar issues
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-4/igt@kms_vblank@pipe-b-query-idle.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-6/igt@kms_vblank@pipe-b-query-idle.html

  * igt@perf@gen12-mi-rpc:
    - {shard-rkl}:        [SKIP][138] ([fdo#109289]) -> [PASS][139]
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-5/igt@perf@gen12-mi-rpc.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-1/igt@perf@gen12-mi-rpc.html

  * igt@perf@polling-small-buf:
    - {shard-rkl}:        [FAIL][140] ([i915#1722]) -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-4/igt@perf@polling-small-buf.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-6/igt@perf@polling-small-buf.html

  * igt@perf_pmu@idle@rcs0:
    - {shard-rkl}:        [FAIL][142] ([i915#4349]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7183/shard-rkl-4/igt@perf_pmu@idle@rcs0.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/shard-rkl-4/igt@perf_pmu@idle@rcs0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4778]: https://gitlab.freedesktop.org/drm/intel/issues/4778
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5775]: https://gitlab.freedesktop.org/drm/intel/issues/5775
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
  [i915#6403]: https://gitlab.freedesktop.org/drm/intel/issues/6403
  [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
  [i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
  [i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
  [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
  [i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
  [i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7183 -> IGTPW_8569

  CI-20190529: 20190529
  CI_DRM_12821: 24f94240c4bca70cadfd00528ffd56c3049e5f58 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8569: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/index.html
  IGT_7183: 3434cef8be4e487644a740039ad15123cd094526 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8569/index.html

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