* [igt-dev] [PATCH i-g-t] lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
@ 2023-03-27 15:43 Zbigniew Kempczyński
2023-03-27 18:27 ` [igt-dev] ✗ Fi.CI.BAT: failure for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Zbigniew Kempczyński @ 2023-03-27 15:43 UTC (permalink / raw)
To: igt-dev
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Adding xeph_gpgpu_fillfunc to have gpgpu_fill running on XEPH (DG2).
On XEPH there's no GPGPU_WALK command, it has COMPUTE_WALK what requires
pipeline creation change.
Shader used in the test was taken from previous generation with
adding SWSB dependency tracking. SWSB was added using iga64 automatic
dependency generating:
iga64 -p=12p5 -Xauto-deps shader.asm
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
lib/gen8_media.h | 2 +
lib/gpgpu_fill.c | 65 +++++
lib/gpgpu_fill.h | 6 +
lib/gpu_cmds.c | 251 +++++++++++++++++++
lib/gpu_cmds.h | 35 +++
lib/i915/shaders/gpgpu/xeph_gpgpu_kernel.asm | 12 +
lib/intel_batchbuffer.c | 18 +-
lib/xeph_media.h | 207 +++++++++++++++
8 files changed, 588 insertions(+), 8 deletions(-)
create mode 100644 lib/i915/shaders/gpgpu/xeph_gpgpu_kernel.asm
create mode 100644 lib/xeph_media.h
diff --git a/lib/gen8_media.h b/lib/gen8_media.h
index d2a049a1ec..b5c19e503c 100644
--- a/lib/gen8_media.h
+++ b/lib/gen8_media.h
@@ -23,6 +23,8 @@
#define GEN8_MEDIA_STATE_FLUSH GFXPIPE(2, 0, 4)
#define GEN8_MEDIA_OBJECT GFXPIPE(2, 1, 0)
+#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC GFXPIPE(3, 1, 25)
+
struct gen8_interface_descriptor_data
{
struct {
diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
index 0f031a5248..5655ec9477 100644
--- a/lib/gpgpu_fill.c
+++ b/lib/gpgpu_fill.c
@@ -99,6 +99,19 @@ static const uint32_t gen12_gpgpu_kernel[][4] = {
{ 0x00040131, 0x00000004, 0x7020700c, 0x10000000 },
};
+static const uint32_t xeph_gpgpu_kernel[][4] = {
+ { 0x00020061, 0x01050000, 0x00000104, 0x00000000 },
+ { 0x00000069, 0x02058220, 0x02000024, 0x00000004 },
+ { 0x00000061, 0x02250220, 0x000000c4, 0x00000000 },
+ { 0x00030061, 0x04050220, 0x00460005, 0x00000000 },
+ { 0x00011a61, 0x04050220, 0x00220205, 0x00000000 },
+ { 0x00000061, 0x04454220, 0x00000000, 0x0000000f },
+ { 0x00041e61, 0x05050220, 0x00000104, 0x00000000 },
+ { 0x80001901, 0x00010000, 0x00000000, 0x00000000 },
+ { 0x00044031, 0x00000000, 0xc0000414, 0x02a00000 },
+ { 0x00030031, 0x00000004, 0x3000500c, 0x00000000 },
+};
+
/*
* This sets up the gpgpu pipeline,
*
@@ -280,6 +293,47 @@ __gen9_gpgpu_fillfunc(int i915,
intel_bb_destroy(ibb);
}
+static void
+__xeph_gpgpu_fillfunc(int i915,
+ struct intel_buf *buf,
+ unsigned int x, unsigned int y,
+ unsigned int width, unsigned int height,
+ uint8_t color, const uint32_t kernel[][4],
+ size_t kernel_size)
+{
+ struct intel_bb *ibb;
+ struct xeph_interface_descriptor_data idd;
+ (void) x;
+ (void) y;
+
+ ibb = intel_bb_create(i915, PAGE_SIZE);
+ intel_bb_add_intel_buf(ibb, buf, true);
+
+ intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
+
+ xeph_fill_interface_descriptor(ibb, buf,
+ kernel, kernel_size, &idd);
+
+ intel_bb_ptr_set(ibb, 0);
+
+ /* GPGPU pipeline */
+ intel_bb_out(ibb, GEN7_PIPELINE_SELECT | GEN9_PIPELINE_SELECTION_MASK |
+ PIPELINE_SELECT_GPGPU);
+ xeph_emit_state_base_address(ibb);
+ xeph_emit_state_compute_mode(ibb);
+ xeph_emit_state_binding_table_pool_alloc(ibb);
+ xeph_emit_cfe_state(ibb, THREADS);
+ xeph_emit_compute_walk(ibb, width, height, &idd, color);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 32);
+
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
+
+ intel_bb_destroy(ibb);
+}
+
void gen9_gpgpu_fillfunc(int i915,
struct intel_buf *buf,
unsigned x, unsigned y,
@@ -312,3 +366,14 @@ void gen12_gpgpu_fillfunc(int i915,
gen12_gpgpu_kernel,
sizeof(gen12_gpgpu_kernel));
}
+
+void xeph_gpgpu_fillfunc(int i915,
+ struct intel_buf *buf,
+ unsigned int x, unsigned int y,
+ unsigned int width, unsigned int height,
+ uint8_t color)
+{
+ __xeph_gpgpu_fillfunc(i915, buf, x, y, width, height, color,
+ xeph_gpgpu_kernel,
+ sizeof(xeph_gpgpu_kernel));
+}
diff --git a/lib/gpgpu_fill.h b/lib/gpgpu_fill.h
index 25abe1fa19..15ef147ce0 100644
--- a/lib/gpgpu_fill.h
+++ b/lib/gpgpu_fill.h
@@ -61,4 +61,10 @@ void gen12_gpgpu_fillfunc(int i915,
unsigned width, unsigned height,
uint8_t color);
+void
+xeph_gpgpu_fillfunc(int i915,
+ struct intel_buf *dst,
+ unsigned int x, unsigned int y,
+ unsigned int width, unsigned int height,
+ uint8_t color);
#endif /* GPGPU_FILL_H */
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index c31b51f7b4..0abca0a007 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -262,6 +262,10 @@ gen7_fill_binding_table(struct intel_bb *ibb,
binding_table[0] = gen7_fill_surface_state(ibb, buf,
SURFACEFORMAT_R8_UNORM, 1);
+ else if (intel_graphics_ver(devid) >= IP_VER(12, 50))
+ binding_table[0] = xeph_fill_surface_state(ibb, buf,
+ SURFACEFORMAT_R8_UNORM, 1);
+
else
binding_table[0] = gen8_fill_surface_state(ibb, buf,
SURFACEFORMAT_R8_UNORM, 1);
@@ -773,3 +777,250 @@ gen7_emit_media_objects(struct intel_bb *ibb,
for (j = 0; j < height / 16; j++)
gen_emit_media_object(ibb, x + i * 16, y + j * 16);
}
+
+/*
+ * XEPH
+ */
+void
+xeph_fill_interface_descriptor(struct intel_bb *ibb,
+ struct intel_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size,
+ struct xeph_interface_descriptor_data *idd)
+{
+ uint32_t binding_table_offset, kernel_offset;
+
+ binding_table_offset = gen7_fill_binding_table(ibb, dst);
+ kernel_offset = gen7_fill_kernel(ibb, kernel, size);
+
+ memset(idd, 0, sizeof(*idd));
+ idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+ idd->desc2.single_program_flow = 1;
+ idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
+
+ idd->desc3.sampler_count = 0; /* 0 samplers used */
+ idd->desc3.sampler_state_pointer = 0;
+
+ idd->desc4.binding_table_entry_count = 0;
+ idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
+
+ idd->desc5.num_threads_in_tg = 1;
+}
+
+uint32_t
+xeph_fill_surface_state(struct intel_bb *ibb,
+ struct intel_buf *buf,
+ uint32_t format,
+ int is_dst)
+{
+ struct xeph_surface_state *ss;
+ uint32_t write_domain, read_domain, offset;
+ uint64_t address;
+
+ if (is_dst) {
+ write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+ } else {
+ write_domain = 0;
+ read_domain = I915_GEM_DOMAIN_SAMPLER;
+ }
+
+ intel_bb_ptr_align(ibb, 64);
+ offset = intel_bb_offset(ibb);
+ ss = intel_bb_ptr(ibb);
+ intel_bb_ptr_add(ibb, 64);
+
+ ss->ss0.surface_type = SURFACE_2D;
+ ss->ss0.surface_format = format;
+ ss->ss0.render_cache_read_write = 1;
+ ss->ss0.vertical_alignment = 1; /* align 4 */
+ ss->ss0.horizontal_alignment = 1; /* align 4 */
+
+ if (buf->tiling == I915_TILING_X)
+ ss->ss0.tiled_mode = 2;
+ else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
+ ss->ss0.tiled_mode = 3;
+
+ address = intel_bb_offset_reloc(ibb, buf->handle,
+ read_domain, write_domain,
+ offset + 4 * 8, 0x0);
+
+ ss->ss8.base_addr_lo = (uint32_t) address;
+ ss->ss9.base_addr_hi = address >> 32;
+
+ ss->ss2.height = intel_buf_height(buf) - 1;
+ ss->ss2.width = intel_buf_width(buf) - 1;
+ ss->ss3.pitch = buf->surface[0].stride - 1;
+
+ ss->ss7.shader_channel_select_r = 4;
+ ss->ss7.shader_channel_select_g = 5;
+ ss->ss7.shader_channel_select_b = 6;
+ ss->ss7.shader_channel_select_a = 7;
+
+ return offset;
+}
+
+void
+xeph_emit_cfe_state(struct intel_bb *ibb, uint32_t threads)
+{
+ bool dfeud = CFE_CAN_DISABLE_FUSED_EU_DISPATCH(ibb->devid);
+
+ intel_bb_out(ibb, XEPH_CFE_STATE | (6 - 2));
+
+ /* scratch buffer */
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, 0);
+
+#define _LEGACY_MODE (1 << 6)
+ /* number of threads & urb entries */
+ intel_bb_out(ibb, (max_t(threads, threads, 64) - 1) << 16 | (dfeud ? _LEGACY_MODE : 0));
+
+ intel_bb_out(ibb, 0);
+ intel_bb_out(ibb, 0);
+}
+
+void
+xeph_emit_state_compute_mode(struct intel_bb *ibb)
+{
+ intel_bb_out(ibb, XEPH_STATE_COMPUTE_MODE);
+ intel_bb_out(ibb, 0);
+}
+
+void
+xeph_emit_state_binding_table_pool_alloc(struct intel_bb *ibb)
+{
+ intel_bb_out(ibb, GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC | 2);
+ intel_bb_emit_reloc(ibb, ibb->handle,
+ I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
+ 0, 0, 0x0);
+ intel_bb_out(ibb, 1 << 12);
+}
+
+void
+xeph_emit_state_base_address(struct intel_bb *ibb)
+{
+ intel_bb_out(ibb, GEN8_STATE_BASE_ADDRESS | 0x14); //dw0
+
+ /* general */
+ intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); //dw1-dw2
+ intel_bb_out(ibb, 0);
+
+ /* stateless data port */
+ intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); //dw3
+
+ /* surface */
+ intel_bb_emit_reloc(ibb, ibb->handle, I915_GEM_DOMAIN_SAMPLER, //dw4-dw5
+ 0, BASE_ADDRESS_MODIFY, 0x0);
+
+ /* dynamic */
+ intel_bb_emit_reloc(ibb, ibb->handle, //dw6-dw7
+ I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
+ 0, BASE_ADDRESS_MODIFY, 0x0);
+
+ /* indirect */
+ intel_bb_out(ibb, 0); //dw8-dw9
+ intel_bb_out(ibb, 0);
+
+ /* instruction */
+ intel_bb_emit_reloc(ibb, ibb->handle,
+ I915_GEM_DOMAIN_INSTRUCTION, //dw10-dw11
+ 0, BASE_ADDRESS_MODIFY, 0x0);
+
+ /* general state buffer size */
+ intel_bb_out(ibb, 0xfffff000 | 1); //dw12
+ /* dynamic state buffer size */
+ intel_bb_out(ibb, 1 << 12 | 1); //dw13
+ /* indirect object buffer size */
+ intel_bb_out(ibb, 0xfffff000 | 1); //dw14
+ /* intruction buffer size */
+ intel_bb_out(ibb, 1 << 12 | 1); //dw15
+
+ /* Bindless surface state base address */
+ intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); //dw16
+ intel_bb_out(ibb, 0); //dw17
+ intel_bb_out(ibb, 0xfffff000); //dw18
+
+ /* Bindless sampler state base address */
+ intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); //dw19
+ intel_bb_out(ibb, 0); //dw20
+ intel_bb_out(ibb, 0); //dw21
+}
+
+void
+xeph_emit_compute_walk(struct intel_bb *ibb,
+ unsigned int width, unsigned int height,
+ struct xeph_interface_descriptor_data *pidd,
+ uint8_t color)
+{
+ uint32_t x_dim, y_dim;
+
+ /*
+ * Simply do SIMD16 based dispatch, so every thread uses
+ * SIMD16 channels.
+ *
+ * Define our own thread group size, e.g 16x1 for every group, then
+ * will have 1 thread each group in SIMD16 dispatch. So thread
+ * width/height/depth are all 1.
+ *
+ * Then thread group X = width / 16 (aligned to 16)
+ * thread group Y = height;
+ */
+ x_dim = (width + 15) / 16;
+ y_dim = height;
+
+ intel_bb_out(ibb, XEPH_COMPUTE_WALKER | 0x25);
+
+ intel_bb_out(ibb, 0); /* debug object */ //dw1
+ intel_bb_out(ibb, 0); /* indirect data length */ //dw2
+ intel_bb_out(ibb, 0); /* indirect data offset */ //dw3
+
+ /* SIMD size */
+ intel_bb_out(ibb, 1 << 30 | 1 << 25); /* SIMD16 | enable inline */ //dw4
+
+ /* Execution mask */
+ intel_bb_out(ibb, 0xffffffff); //dw5
+
+ /* x/y/z max */
+ intel_bb_out(ibb, (x_dim << 20) | (y_dim << 10) | 1); //dw6
+
+ /* x dim */
+ intel_bb_out(ibb, x_dim); //dw7
+
+ /* y dim */
+ intel_bb_out(ibb, y_dim); //dw8
+
+ /* z dim */
+ intel_bb_out(ibb, 1); //dw9
+
+ /* group id x/y/z */
+ intel_bb_out(ibb, 0); //dw10
+ intel_bb_out(ibb, 0); //dw11
+ intel_bb_out(ibb, 0); //dw12
+
+ /* partition id / partition size */
+ intel_bb_out(ibb, 0); //dw13
+ intel_bb_out(ibb, 0); //dw14
+
+ /* preempt x/y/z */
+ intel_bb_out(ibb, 0); //dw15
+ intel_bb_out(ibb, 0); //dw16
+ intel_bb_out(ibb, 0); //dw17
+
+ /* Interface descriptor data */
+ for (int i = 0; i < 8; i++) { //dw18-25
+ intel_bb_out(ibb, ((uint32_t *) pidd)[i]);
+ }
+
+ /* Postsync data */
+ intel_bb_out(ibb, 0); //dw26
+ intel_bb_out(ibb, 0); //dw27
+ intel_bb_out(ibb, 0); //dw28
+ intel_bb_out(ibb, 0); //dw29
+ intel_bb_out(ibb, 0); //dw30
+
+ /* Inline data */
+ intel_bb_out(ibb, (uint32_t) color); //dw31
+ for (int i = 0; i < 7; i++) { //dw32-38
+ intel_bb_out(ibb, 0x0);
+ }
+}
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 56f09b6e1e..ac9d4c07c8 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -30,6 +30,7 @@
#include "media_fill.h"
#include "gen7_media.h"
#include "gen8_media.h"
+#include "xeph_media.h"
#include "intel_reg.h"
#include "drmtest.h"
#include "intel_batchbuffer.h"
@@ -107,4 +108,38 @@ void
gen7_emit_media_objects(struct intel_bb *ibb,
unsigned int x, unsigned int y,
unsigned int width, unsigned int height);
+
+void
+xeph_fill_interface_descriptor(struct intel_bb *ibb,
+ struct intel_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size,
+ struct xeph_interface_descriptor_data *idd);
+
+uint32_t
+xeph_fill_surface_state(struct intel_bb *ibb,
+ struct intel_buf *buf,
+ uint32_t format,
+ int is_dst);
+
+void
+xeph_emit_state_compute_mode(struct intel_bb *ibb);
+
+void
+xeph_emit_state_binding_table_pool_alloc(struct intel_bb *ibb);
+
+void
+xeph_emit_cfe_state(struct intel_bb *ibb, uint32_t threads);
+
+#define CFE_CAN_DISABLE_FUSED_EU_DISPATCH(devid) (IS_DG2(devid))
+
+void
+xeph_emit_state_base_address(struct intel_bb *ibb);
+
+void
+xeph_emit_compute_walk(struct intel_bb *ibb,
+ unsigned int width, unsigned int height,
+ struct xeph_interface_descriptor_data *pidd,
+ uint8_t color);
+
#endif /* GPU_CMDS_H */
diff --git a/lib/i915/shaders/gpgpu/xeph_gpgpu_kernel.asm b/lib/i915/shaders/gpgpu/xeph_gpgpu_kernel.asm
new file mode 100644
index 0000000000..7adfbd0f04
--- /dev/null
+++ b/lib/i915/shaders/gpgpu/xeph_gpgpu_kernel.asm
@@ -0,0 +1,12 @@
+L0:
+ mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub
+ shl (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud 0x4:ud
+ mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud
+ mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud
+ mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud {I@2}
+ mov (1|M0) r4.2<1>:ud 0xF:ud
+ mov (16|M0) r5.0<1>:ud r1.0<0;1,0>:ud {I@6}
+(W) sync.nop null {I@1}
+ send.dc1 (16|M0) null r4 null 0x0 0x40A8000 {$0} // wr:2h+0, rd:0, Media Block Write msc:0, to #0
+ send.gtwy (8|M0) null r80 null 0x0 0x02000000 {EOT}
+L176:
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index da4c238cae..6850f3a864 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -747,16 +747,18 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid)
{
igt_fillfunc_t fill = NULL;
- if (IS_GEN7(devid))
- fill = gen7_gpgpu_fillfunc;
- else if (IS_GEN8(devid))
- fill = gen8_gpgpu_fillfunc;
- else if (IS_GEN9(devid) || IS_GEN10(devid))
- fill = gen9_gpgpu_fillfunc;
- else if (IS_GEN11(devid))
- fill = gen11_gpgpu_fillfunc;
+ if (intel_graphics_ver(devid) >= IP_VER(12, 50))
+ fill = xeph_gpgpu_fillfunc;
else if (IS_GEN12(devid))
fill = gen12_gpgpu_fillfunc;
+ else if (IS_GEN11(devid))
+ fill = gen11_gpgpu_fillfunc;
+ else if (IS_GEN9(devid) || IS_GEN10(devid))
+ fill = gen9_gpgpu_fillfunc;
+ else if (IS_GEN8(devid))
+ fill = gen8_gpgpu_fillfunc;
+ else if (IS_GEN7(devid))
+ fill = gen7_gpgpu_fillfunc;
return fill;
}
diff --git a/lib/xeph_media.h b/lib/xeph_media.h
new file mode 100644
index 0000000000..0a93e649f0
--- /dev/null
+++ b/lib/xeph_media.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: MIT */
+
+#ifndef XEPH_MEDIA_H
+#define XEPH_MEDIA_H
+
+#include <stdint.h>
+#include "surfaceformat.h"
+#include "gen7_media.h"
+
+#define GFXPIPE_XEPH(Pipeline, Opcode, Subopcode) ((3 << 29) | \
+ ((Pipeline) << 27) | \
+ ((Opcode) << 24) | \
+ ((Subopcode) << 18))
+
+#define XEPH_STATE_COMPUTE_MODE GFXPIPE(0, 1, 5)
+#define XEPH_CFE_STATE GFXPIPE_XEPH(2, 2, 0)
+#define XEPH_COMPUTE_WALKER GFXPIPE_XEPH(2, 2, 2)
+
+#define BITRANGE(start, end) (end - start + 1)
+
+struct xeph_interface_descriptor_data {
+ struct {
+ uint32_t pad0: BITRANGE(0, 5);
+ uint32_t kernel_start_pointer: BITRANGE(6, 31);
+ } desc0;
+
+ struct {
+ uint32_t kernel_start_pointer_high: BITRANGE(0, 15);
+ uint32_t pad0: BITRANGE(16, 31);
+ } desc1;
+
+ struct {
+ uint32_t pad0: BITRANGE(0, 6);
+ uint32_t software_exception_enable: BITRANGE(7, 7);
+ uint32_t pad1: BITRANGE(8, 10);
+ uint32_t maskstack_exception_enable: BITRANGE(11, 11);
+ uint32_t pad2: BITRANGE(12, 12);
+ uint32_t illegal_opcode_exception_enable: BITRANGE(13, 13);
+ uint32_t pad3: BITRANGE(14, 15);
+ uint32_t floating_point_mode: BITRANGE(16, 16);
+ uint32_t pad4: BITRANGE(17, 17);
+ uint32_t single_program_flow: BITRANGE(18, 18);
+ uint32_t denorm_mode: BITRANGE(19, 19);
+ uint32_t thread_preemption_disable: BITRANGE(20, 20);
+ uint32_t pad5: BITRANGE(21, 31);
+ } desc2;
+
+ struct {
+ uint32_t pad0: BITRANGE(0, 1);
+ uint32_t sampler_count: BITRANGE(2, 4);
+ uint32_t sampler_state_pointer: BITRANGE(5, 31);
+ } desc3;
+
+ struct {
+ uint32_t binding_table_entry_count: BITRANGE(0, 4);
+ uint32_t binding_table_pointer: BITRANGE(5, 20);
+ uint32_t pad0: BITRANGE(21, 31);
+ } desc4;
+
+ struct {
+ uint32_t num_threads_in_tg: BITRANGE(0, 9);
+ uint32_t pad0: BITRANGE(10, 15);
+ uint32_t shared_local_memory_size: BITRANGE(16, 20);
+ uint32_t barrier_enable: BITRANGE(21, 21);
+ uint32_t rounding_mode: BITRANGE(22, 23);
+ uint32_t pad1: BITRANGE(24, 26);
+ uint32_t thread_group_dispatch_size: BITRANGE(27, 27);
+ uint32_t pad2: BITRANGE(28, 31);
+ } desc5;
+
+ struct {
+ uint32_t pad0;
+ } desc6;
+
+ struct {
+ uint32_t pad0;
+ } desc7;
+};
+
+struct xeph_surface_state {
+ struct {
+ uint32_t cube_pos_z: BITRANGE(0, 0);
+ uint32_t cube_neg_z: BITRANGE(1, 1);
+ uint32_t cube_pos_y: BITRANGE(2, 2);
+ uint32_t cube_neg_y: BITRANGE(3, 3);
+ uint32_t cube_pos_x: BITRANGE(4, 4);
+ uint32_t cube_neg_x: BITRANGE(5, 5);
+ uint32_t media_boundary_pixel_mode: BITRANGE(6, 7);
+ uint32_t render_cache_read_write: BITRANGE(8, 8);
+ uint32_t sampler_l2_bypass_disable: BITRANGE(9, 9);
+ uint32_t vert_line_stride_ofs: BITRANGE(10, 10);
+ uint32_t vert_line_stride: BITRANGE(11, 11);
+ uint32_t tiled_mode: BITRANGE(12, 13);
+ uint32_t horizontal_alignment: BITRANGE(14, 15);
+ uint32_t vertical_alignment: BITRANGE(16, 17);
+ uint32_t surface_format: BITRANGE(18, 26); /**< BRW_SURFACEFORMAT_x */
+ uint32_t astc_enable: BITRANGE(27, 27);
+ uint32_t is_array: BITRANGE(28, 28);
+ uint32_t surface_type: BITRANGE(29, 31); /**< BRW_SURFACE_1D/2D/3D/CUBE */
+ } ss0;
+
+ struct {
+ uint32_t qpitch: BITRANGE(0, 14);
+ uint32_t sample_tap_discard_disable: BITRANGE(15, 15);
+ uint32_t pad0: BITRANGE(16, 16);
+ uint32_t double_fetch_disable: BITRANGE(17, 17);
+ uint32_t corner_texel_mode: BITRANGE(18, 18);
+ uint32_t base_mip_level: BITRANGE(19, 23);
+ uint32_t memory_object_control: BITRANGE(24, 30);
+ uint32_t unorm_path_in_color_pipe: BITRANGE(31, 31);
+ } ss1;
+
+ struct {
+ uint32_t width: BITRANGE(0, 13);
+ uint32_t pad0: BITRANGE(14, 15);
+ uint32_t height: BITRANGE(16, 29);
+ uint32_t pad1: BITRANGE(30, 30);
+ uint32_t depth_stencil_resource: BITRANGE(31, 31);
+ } ss2;
+
+ struct {
+ uint32_t pitch: BITRANGE(0, 17);
+ uint32_t null_probing_enable: BITRANGE(18, 18);
+ uint32_t standard_tiling_mode_ext: BITRANGE(19, 19);
+ uint32_t pad0: BITRANGE(20, 20);
+ uint32_t depth: BITRANGE(21, 31);
+ } ss3;
+
+ struct {
+ uint32_t multisample_position_palette_index: BITRANGE(0, 2);
+ uint32_t num_multisamples: BITRANGE(3, 5);
+ uint32_t multisampled_surface_storage_format: BITRANGE(6, 6);
+ uint32_t render_target_view_extent: BITRANGE(7, 17);
+ uint32_t min_array_element: BITRANGE(18, 28);
+ uint32_t rotation: BITRANGE(29, 30);
+ uint32_t decompress_in_l3: BITRANGE(31, 31);
+ } ss4;
+
+ struct {
+ uint32_t mip_count: BITRANGE(0, 3);
+ uint32_t surface_min_lod: BITRANGE(4, 7);
+ uint32_t mip_tail_start_lod: BITRANGE(8, 11);
+ uint32_t yuv_bpt: BITRANGE(12, 13);
+ uint32_t coherency_type: BITRANGE(14, 15);
+ uint32_t pad0: BITRANGE(16, 17);
+ uint32_t tiled_resource_mode: BITRANGE(18, 19);
+ uint32_t ewa_disable_for_cube: BITRANGE(20, 20);
+ uint32_t y_offset: BITRANGE(21, 23);
+ uint32_t pad1: BITRANGE(24, 24);
+ uint32_t x_offset: BITRANGE(25, 31);
+ } ss5;
+
+ struct {
+ uint32_t pad; /* Multisample Control Surface stuff */
+ } ss6;
+
+ struct {
+ uint32_t resource_min_lod: BITRANGE(0, 11);
+ uint32_t pad0: BITRANGE(12, 13);
+ uint32_t disable_support_for_multigpu_atomics: BITRANGE(14, 14);
+ uint32_t disable_support_for_multigpu_partwrite: BITRANGE(15, 15);
+ uint32_t shader_channel_select_a: BITRANGE(16, 18);
+ uint32_t shader_channel_select_b: BITRANGE(19, 21);
+ uint32_t shader_channel_select_g: BITRANGE(22, 24);
+ uint32_t shader_channel_select_r: BITRANGE(25, 27);
+ uint32_t pad1: BITRANGE(28, 29);
+ uint32_t memory_compression_enable: BITRANGE(30, 30);
+ uint32_t memory_compression_mode: BITRANGE(31, 31);
+ } ss7;
+
+ struct {
+ uint32_t base_addr_lo;
+ } ss8;
+
+ struct {
+ uint32_t base_addr_hi;
+ } ss9;
+
+ struct {
+ uint32_t pad0: BITRANGE(0, 11);
+ uint32_t aux_base_addr_lo: BITRANGE(12, 31);
+ } ss10;
+
+ struct {
+ uint32_t aux_base_addr_hi;
+ } ss11;
+
+ struct {
+ uint32_t compression_format: BITRANGE(0, 4);
+ uint32_t clear_address_lo: BITRANGE(5, 31);
+ } ss12;
+
+ struct {
+ uint32_t clear_address_hi: BITRANGE(0, 15);
+ uint32_t pad0: BITRANGE(16, 31);
+ } ss13;
+
+ struct {
+ uint32_t reserved;
+ } ss14;
+
+ struct {
+ uint32_t reserved;
+ } ss15;
+};
+
+#endif /* XEPH_MEDIA_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [igt-dev] ✗ Fi.CI.BAT: failure for lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
2023-03-27 15:43 [igt-dev] [PATCH i-g-t] lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH Zbigniew Kempczyński
@ 2023-03-27 18:27 ` Patchwork
2023-03-27 18:48 ` Zbigniew Kempczyński
2023-03-28 4:37 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Patchwork @ 2023-03-27 18:27 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 5692 bytes --]
== Series Details ==
Series: lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
URL : https://patchwork.freedesktop.org/series/115672/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12921 -> IGTPW_8688
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_8688 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_8688, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
Participating hosts (37 -> 36)
------------------------------
Missing (1): fi-kbl-soraka
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_8688:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1:
- bat-dg2-8: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1.html
Known issues
------------
Here are the changes found in IGTPW_8688 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][3] -> [ABORT][4] ([i915#7911] / [i915#7913])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-FAIL][5] ([i915#6997] / [i915#7913])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][6] ([i915#7828])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- bat-rpls-1: NOTRUN -> [SKIP][7] ([i915#7828])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-1: NOTRUN -> [SKIP][8] ([i915#1845])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-1/igt@kms_pipe_crc_basic@suspend-read-crc.html
- bat-rpls-2: NOTRUN -> [SKIP][9] ([i915#1845])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-3:
- bat-dg2-11: [PASS][10] -> [INCOMPLETE][11] ([i915#1982] / [i915#7908])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-3.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-3.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: [ABORT][12] ([i915#6687] / [i915#7978]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][14] ([i915#4983] / [i915#7913]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-rpls-2/igt@i915_selftest@live@reset.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-2/igt@i915_selftest@live@reset.html
#### Warnings ####
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][16] ([i915#6367]) -> [DMESG-FAIL][17] ([i915#6367] / [i915#7996])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-rpls-1/igt@i915_selftest@live@slpc.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-1/igt@i915_selftest@live@slpc.html
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7908]: https://gitlab.freedesktop.org/drm/intel/issues/7908
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7221 -> IGTPW_8688
CI-20190529: 20190529
CI_DRM_12921: 3de6040ce9900a94ec626662d5c6a227b37eeb1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8688: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
IGT_7221: 4b77c6d85024d22ca521d510f8eee574128fe04f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
[-- Attachment #2: Type: text/html, Size: 6878 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [igt-dev] ✗ Fi.CI.BAT: failure for lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
2023-03-27 18:27 ` [igt-dev] ✗ Fi.CI.BAT: failure for " Patchwork
@ 2023-03-27 18:48 ` Zbigniew Kempczyński
2023-03-28 5:02 ` Yedireswarapu, SaiX Nandan
0 siblings, 1 reply; 9+ messages in thread
From: Zbigniew Kempczyński @ 2023-03-27 18:48 UTC (permalink / raw)
To: igt-dev, SaiX Nandan Yedireswarapu
On Mon, Mar 27, 2023 at 06:27:18PM +0000, Patchwork wrote:
> Patch Details
>
> Series: lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
> URL: https://patchwork.freedesktop.org/series/115672/
> State: failure
> Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
>
> CI Bug Log - changes from CI_DRM_12921 -> IGTPW_8688
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with IGTPW_8688 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_8688, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in
> CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
>
> Participating hosts (37 -> 36)
>
> Missing (1): fi-kbl-soraka
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in IGTPW_8688:
>
> IGT changes
>
> Possible regressions
>
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1:
> * bat-dg2-8: PASS -> FAIL
Unrelated to the change. May I ask for run shards for it?
--
Zbigniew
>
> Known issues
>
> Here are the changes found in IGTPW_8688 that come from known issues:
>
> IGT changes
>
> Issues hit
>
> * igt@i915_selftest@live@execlists:
>
> * fi-bsw-n3050: PASS -> ABORT (i915#7911 / i915#7913)
> * igt@i915_selftest@live@slpc:
>
> * bat-rpls-2: NOTRUN -> DMESG-FAIL (i915#6997 / i915#7913)
> * igt@kms_chamelium_hpd@common-hpd-after-suspend:
>
> * bat-rpls-2: NOTRUN -> SKIP (i915#7828)
>
> * bat-rpls-1: NOTRUN -> SKIP (i915#7828)
>
> * igt@kms_pipe_crc_basic@suspend-read-crc:
>
> * bat-rpls-1: NOTRUN -> SKIP (i915#1845)
>
> * bat-rpls-2: NOTRUN -> SKIP (i915#1845)
>
> * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-3:
>
> * bat-dg2-11: PASS -> INCOMPLETE (i915#1982 / i915#7908)
>
> Possible fixes
>
> * igt@gem_exec_suspend@basic-s3@smem:
>
> * bat-rpls-1: ABORT (i915#6687 / i915#7978) -> PASS
> * igt@i915_selftest@live@reset:
>
> * bat-rpls-2: ABORT (i915#4983 / i915#7913) -> PASS
>
> Warnings
>
> * igt@i915_selftest@live@slpc:
> * bat-rpls-1: DMESG-FAIL (i915#6367) -> DMESG-FAIL (i915#6367 /
> i915#7996)
>
> Build changes
>
> * CI: CI-20190529 -> None
> * IGT: IGT_7221 -> IGTPW_8688
>
> CI-20190529: 20190529
> CI_DRM_12921: 3de6040ce9900a94ec626662d5c6a227b37eeb1c @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_8688: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
> IGT_7221: 4b77c6d85024d22ca521d510f8eee574128fe04f @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
2023-03-27 15:43 [igt-dev] [PATCH i-g-t] lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH Zbigniew Kempczyński
2023-03-27 18:27 ` [igt-dev] ✗ Fi.CI.BAT: failure for " Patchwork
@ 2023-03-28 4:37 ` Patchwork
2023-03-28 12:02 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-03-28 4:37 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 5309 bytes --]
== Series Details ==
Series: lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
URL : https://patchwork.freedesktop.org/series/115672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12921 -> IGTPW_8688
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
Participating hosts (37 -> 36)
------------------------------
Missing (1): fi-kbl-soraka
Known issues
------------
Here are the changes found in IGTPW_8688 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][1] -> [ABORT][2] ([i915#7911] / [i915#7913])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-FAIL][3] ([i915#6997] / [i915#7913])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][4] ([i915#7828])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- bat-rpls-1: NOTRUN -> [SKIP][5] ([i915#7828])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1:
- bat-dg2-8: [PASS][6] -> [FAIL][7] ([i915#7932])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-1: NOTRUN -> [SKIP][8] ([i915#1845])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-1/igt@kms_pipe_crc_basic@suspend-read-crc.html
- bat-rpls-2: NOTRUN -> [SKIP][9] ([i915#1845])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-3:
- bat-dg2-11: [PASS][10] -> [INCOMPLETE][11] ([i915#1982] / [i915#7908])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-3.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-3.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: [ABORT][12] ([i915#6687] / [i915#7978]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][14] ([i915#4983] / [i915#7913]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-rpls-2/igt@i915_selftest@live@reset.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-2/igt@i915_selftest@live@reset.html
#### Warnings ####
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][16] ([i915#6367]) -> [DMESG-FAIL][17] ([i915#6367] / [i915#7996])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-rpls-1/igt@i915_selftest@live@slpc.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/bat-rpls-1/igt@i915_selftest@live@slpc.html
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7908]: https://gitlab.freedesktop.org/drm/intel/issues/7908
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7221 -> IGTPW_8688
CI-20190529: 20190529
CI_DRM_12921: 3de6040ce9900a94ec626662d5c6a227b37eeb1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8688: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
IGT_7221: 4b77c6d85024d22ca521d510f8eee574128fe04f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
[-- Attachment #2: Type: text/html, Size: 6483 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [igt-dev] ✗ Fi.CI.BAT: failure for lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
2023-03-27 18:48 ` Zbigniew Kempczyński
@ 2023-03-28 5:02 ` Yedireswarapu, SaiX Nandan
0 siblings, 0 replies; 9+ messages in thread
From: Yedireswarapu, SaiX Nandan @ 2023-03-28 5:02 UTC (permalink / raw)
To: Kempczynski, Zbigniew, igt-dev@lists.freedesktop.org
Cc: Marikkar, SanjuX, Veesam, RavitejaX
Hi,
Issue re-reported, https://patchwork.freedesktop.org/series/115672/
Thanks,
Y Sai Nandan
-----Original Message-----
From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
Sent: Tuesday, March 28, 2023 12:19 AM
To: igt-dev@lists.freedesktop.org; Yedireswarapu, SaiX Nandan <saix.nandan.yedireswarapu@intel.com>
Subject: Re: ✗ Fi.CI.BAT: failure for lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
On Mon, Mar 27, 2023 at 06:27:18PM +0000, Patchwork wrote:
> Patch Details
>
> Series: lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
> URL: https://patchwork.freedesktop.org/series/115672/
> State: failure
> Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
>
> CI Bug Log - changes from CI_DRM_12921 -> IGTPW_8688
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with IGTPW_8688 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_8688, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in
> CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
>
> Participating hosts (37 -> 36)
>
> Missing (1): fi-kbl-soraka
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in IGTPW_8688:
>
> IGT changes
>
> Possible regressions
>
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1:
> * bat-dg2-8: PASS -> FAIL
Unrelated to the change. May I ask for run shards for it?
--
Zbigniew
>
> Known issues
>
> Here are the changes found in IGTPW_8688 that come from known issues:
>
> IGT changes
>
> Issues hit
>
> * igt@i915_selftest@live@execlists:
>
> * fi-bsw-n3050: PASS -> ABORT (i915#7911 / i915#7913)
> * igt@i915_selftest@live@slpc:
>
> * bat-rpls-2: NOTRUN -> DMESG-FAIL (i915#6997 / i915#7913)
> * igt@kms_chamelium_hpd@common-hpd-after-suspend:
>
> * bat-rpls-2: NOTRUN -> SKIP (i915#7828)
>
> * bat-rpls-1: NOTRUN -> SKIP (i915#7828)
>
> * igt@kms_pipe_crc_basic@suspend-read-crc:
>
> * bat-rpls-1: NOTRUN -> SKIP (i915#1845)
>
> * bat-rpls-2: NOTRUN -> SKIP (i915#1845)
>
> * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-3:
>
> * bat-dg2-11: PASS -> INCOMPLETE (i915#1982 / i915#7908)
>
> Possible fixes
>
> * igt@gem_exec_suspend@basic-s3@smem:
>
> * bat-rpls-1: ABORT (i915#6687 / i915#7978) -> PASS
> * igt@i915_selftest@live@reset:
>
> * bat-rpls-2: ABORT (i915#4983 / i915#7913) -> PASS
>
> Warnings
>
> * igt@i915_selftest@live@slpc:
> * bat-rpls-1: DMESG-FAIL (i915#6367) -> DMESG-FAIL (i915#6367 /
> i915#7996)
>
> Build changes
>
> * CI: CI-20190529 -> None
> * IGT: IGT_7221 -> IGTPW_8688
>
> CI-20190529: 20190529
> CI_DRM_12921: 3de6040ce9900a94ec626662d5c6a227b37eeb1c @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_8688: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
> IGT_7221: 4b77c6d85024d22ca521d510f8eee574128fe04f @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
2023-03-27 15:43 [igt-dev] [PATCH i-g-t] lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH Zbigniew Kempczyński
2023-03-27 18:27 ` [igt-dev] ✗ Fi.CI.BAT: failure for " Patchwork
2023-03-28 4:37 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-03-28 12:02 ` Patchwork
2023-03-28 13:06 ` [igt-dev] [PATCH i-g-t] " Kamil Konieczny
2023-03-28 13:12 ` Matthew Auld
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-03-28 12:02 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 14885 bytes --]
== Series Details ==
Series: lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
URL : https://patchwork.freedesktop.org/series/115672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12921_full -> IGTPW_8688_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in IGTPW_8688_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2846])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-glk1/igt@gem_exec_fair@basic-deadline.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-glk3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-glk5/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][6] -> [ABORT][7] ([i915#5566])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-glk1/igt@gen9_exec_parse@allowed-single.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-glk2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [PASS][8] -> [ABORT][9] ([i915#4528])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-snb5/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#3886]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-apl1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2346]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][13] -> [FAIL][14] ([i915#2346])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271]) +18 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-glk2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-dp-1:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271]) +76 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-apl6/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-dp-1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-apl3/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][18] ([i915#6268]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-tglu-7/igt@gem_ctx_exec@basic-nohangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-tglu}: [FAIL][20] ([i915#2842]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-tglu-10/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_mmap_offset@clear@smem0:
- {shard-dg1}: [DMESG-WARN][22] ([i915#8304]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-dg1-17/igt@gem_mmap_offset@clear@smem0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-dg1-16/igt@gem_mmap_offset@clear@smem0.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [ABORT][24] ([i915#5566]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-apl6/igt@gen9_exec_parse@allowed-all.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-apl2/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [SKIP][26] ([fdo#109271]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-apl7/igt@i915_pm_dc@dc9-dpms.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-apl3/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- {shard-dg1}: [FAIL][28] ([i915#3591]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-dg1}: [SKIP][30] ([i915#1397]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-dg1-15/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-dg1-14/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [DMESG-FAIL][32] ([i915#5334]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [ABORT][34] ([i915#180]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* {igt@perf@oa-exponents@0-rcs0}:
- shard-glk: [ABORT][36] ([i915#5213]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-glk3/igt@perf@oa-exponents@0-rcs0.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/shard-glk1/igt@perf@oa-exponents@0-rcs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8304]: https://gitlab.freedesktop.org/drm/intel/issues/8304
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7221 -> IGTPW_8688
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12921: 3de6040ce9900a94ec626662d5c6a227b37eeb1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8688: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
IGT_7221: 4b77c6d85024d22ca521d510f8eee574128fe04f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8688/index.html
[-- Attachment #2: Type: text/html, Size: 11262 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
2023-03-27 15:43 [igt-dev] [PATCH i-g-t] lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH Zbigniew Kempczyński
` (2 preceding siblings ...)
2023-03-28 12:02 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
@ 2023-03-28 13:06 ` Kamil Konieczny
2023-03-28 13:12 ` Matthew Auld
4 siblings, 0 replies; 9+ messages in thread
From: Kamil Konieczny @ 2023-03-28 13:06 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
Hi Zbigniew,
On 2023-03-27 at 17:43:59 +0200, Zbigniew Kempczyński wrote:
> From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
>
> Adding xeph_gpgpu_fillfunc to have gpgpu_fill running on XEPH (DG2).
> On XEPH there's no GPGPU_WALK command, it has COMPUTE_WALK what requires
> pipeline creation change.
>
> Shader used in the test was taken from previous generation with
> adding SWSB dependency tracking. SWSB was added using iga64 automatic
> dependency generating:
>
> iga64 -p=12p5 -Xauto-deps shader.asm
>
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
> lib/gen8_media.h | 2 +
> lib/gpgpu_fill.c | 65 +++++
> lib/gpgpu_fill.h | 6 +
> lib/gpu_cmds.c | 251 +++++++++++++++++++
> lib/gpu_cmds.h | 35 +++
> lib/i915/shaders/gpgpu/xeph_gpgpu_kernel.asm | 12 +
> lib/intel_batchbuffer.c | 18 +-
> lib/xeph_media.h | 207 +++++++++++++++
> 8 files changed, 588 insertions(+), 8 deletions(-)
> create mode 100644 lib/i915/shaders/gpgpu/xeph_gpgpu_kernel.asm
> create mode 100644 lib/xeph_media.h
>
> diff --git a/lib/gen8_media.h b/lib/gen8_media.h
> index d2a049a1ec..b5c19e503c 100644
> --- a/lib/gen8_media.h
> +++ b/lib/gen8_media.h
> @@ -23,6 +23,8 @@
> #define GEN8_MEDIA_STATE_FLUSH GFXPIPE(2, 0, 4)
> #define GEN8_MEDIA_OBJECT GFXPIPE(2, 1, 0)
>
> +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC GFXPIPE(3, 1, 25)
> +
> struct gen8_interface_descriptor_data
> {
> struct {
> diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
> index 0f031a5248..5655ec9477 100644
> --- a/lib/gpgpu_fill.c
> +++ b/lib/gpgpu_fill.c
> @@ -99,6 +99,19 @@ static const uint32_t gen12_gpgpu_kernel[][4] = {
> { 0x00040131, 0x00000004, 0x7020700c, 0x10000000 },
> };
>
> +static const uint32_t xeph_gpgpu_kernel[][4] = {
> + { 0x00020061, 0x01050000, 0x00000104, 0x00000000 },
> + { 0x00000069, 0x02058220, 0x02000024, 0x00000004 },
> + { 0x00000061, 0x02250220, 0x000000c4, 0x00000000 },
> + { 0x00030061, 0x04050220, 0x00460005, 0x00000000 },
> + { 0x00011a61, 0x04050220, 0x00220205, 0x00000000 },
> + { 0x00000061, 0x04454220, 0x00000000, 0x0000000f },
> + { 0x00041e61, 0x05050220, 0x00000104, 0x00000000 },
> + { 0x80001901, 0x00010000, 0x00000000, 0x00000000 },
> + { 0x00044031, 0x00000000, 0xc0000414, 0x02a00000 },
> + { 0x00030031, 0x00000004, 0x3000500c, 0x00000000 },
> +};
> +
> /*
> * This sets up the gpgpu pipeline,
> *
> @@ -280,6 +293,47 @@ __gen9_gpgpu_fillfunc(int i915,
> intel_bb_destroy(ibb);
> }
>
> +static void
> +__xeph_gpgpu_fillfunc(int i915,
> + struct intel_buf *buf,
> + unsigned int x, unsigned int y,
> + unsigned int width, unsigned int height,
> + uint8_t color, const uint32_t kernel[][4],
> + size_t kernel_size)
> +{
> + struct intel_bb *ibb;
> + struct xeph_interface_descriptor_data idd;
> + (void) x;
> + (void) y;
> +
> + ibb = intel_bb_create(i915, PAGE_SIZE);
> + intel_bb_add_intel_buf(ibb, buf, true);
> +
> + intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
> +
> + xeph_fill_interface_descriptor(ibb, buf,
> + kernel, kernel_size, &idd);
> +
> + intel_bb_ptr_set(ibb, 0);
> +
> + /* GPGPU pipeline */
> + intel_bb_out(ibb, GEN7_PIPELINE_SELECT | GEN9_PIPELINE_SELECTION_MASK |
> + PIPELINE_SELECT_GPGPU);
> + xeph_emit_state_base_address(ibb);
> + xeph_emit_state_compute_mode(ibb);
> + xeph_emit_state_binding_table_pool_alloc(ibb);
> + xeph_emit_cfe_state(ibb, THREADS);
> + xeph_emit_compute_walk(ibb, width, height, &idd, color);
> +
> + intel_bb_out(ibb, MI_BATCH_BUFFER_END);
> + intel_bb_ptr_align(ibb, 32);
> +
> + intel_bb_exec(ibb, intel_bb_offset(ibb),
> + I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true);
> +
> + intel_bb_destroy(ibb);
> +}
> +
> void gen9_gpgpu_fillfunc(int i915,
> struct intel_buf *buf,
> unsigned x, unsigned y,
> @@ -312,3 +366,14 @@ void gen12_gpgpu_fillfunc(int i915,
> gen12_gpgpu_kernel,
> sizeof(gen12_gpgpu_kernel));
> }
> +
> +void xeph_gpgpu_fillfunc(int i915,
> + struct intel_buf *buf,
> + unsigned int x, unsigned int y,
> + unsigned int width, unsigned int height,
> + uint8_t color)
> +{
> + __xeph_gpgpu_fillfunc(i915, buf, x, y, width, height, color,
> + xeph_gpgpu_kernel,
> + sizeof(xeph_gpgpu_kernel));
> +}
> diff --git a/lib/gpgpu_fill.h b/lib/gpgpu_fill.h
> index 25abe1fa19..15ef147ce0 100644
> --- a/lib/gpgpu_fill.h
> +++ b/lib/gpgpu_fill.h
> @@ -61,4 +61,10 @@ void gen12_gpgpu_fillfunc(int i915,
> unsigned width, unsigned height,
> uint8_t color);
>
> +void
> +xeph_gpgpu_fillfunc(int i915,
> + struct intel_buf *dst,
> + unsigned int x, unsigned int y,
> + unsigned int width, unsigned int height,
> + uint8_t color);
> #endif /* GPGPU_FILL_H */
> diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
> index c31b51f7b4..0abca0a007 100644
> --- a/lib/gpu_cmds.c
> +++ b/lib/gpu_cmds.c
> @@ -262,6 +262,10 @@ gen7_fill_binding_table(struct intel_bb *ibb,
> binding_table[0] = gen7_fill_surface_state(ibb, buf,
> SURFACEFORMAT_R8_UNORM, 1);
>
> + else if (intel_graphics_ver(devid) >= IP_VER(12, 50))
> + binding_table[0] = xeph_fill_surface_state(ibb, buf,
> + SURFACEFORMAT_R8_UNORM, 1);
> +
> else
> binding_table[0] = gen8_fill_surface_state(ibb, buf,
> SURFACEFORMAT_R8_UNORM, 1);
> @@ -773,3 +777,250 @@ gen7_emit_media_objects(struct intel_bb *ibb,
> for (j = 0; j < height / 16; j++)
> gen_emit_media_object(ibb, x + i * 16, y + j * 16);
> }
> +
> +/*
> + * XEPH
> + */
> +void
> +xeph_fill_interface_descriptor(struct intel_bb *ibb,
> + struct intel_buf *dst,
> + const uint32_t kernel[][4],
> + size_t size,
> + struct xeph_interface_descriptor_data *idd)
> +{
> + uint32_t binding_table_offset, kernel_offset;
> +
> + binding_table_offset = gen7_fill_binding_table(ibb, dst);
> + kernel_offset = gen7_fill_kernel(ibb, kernel, size);
> +
> + memset(idd, 0, sizeof(*idd));
> + idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
> +
> + idd->desc2.single_program_flow = 1;
> + idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
> +
> + idd->desc3.sampler_count = 0; /* 0 samplers used */
> + idd->desc3.sampler_state_pointer = 0;
> +
> + idd->desc4.binding_table_entry_count = 0;
> + idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
> +
> + idd->desc5.num_threads_in_tg = 1;
> +}
> +
> +uint32_t
> +xeph_fill_surface_state(struct intel_bb *ibb,
> + struct intel_buf *buf,
> + uint32_t format,
> + int is_dst)
> +{
> + struct xeph_surface_state *ss;
> + uint32_t write_domain, read_domain, offset;
> + uint64_t address;
> +
> + if (is_dst) {
> + write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
> + } else {
> + write_domain = 0;
> + read_domain = I915_GEM_DOMAIN_SAMPLER;
> + }
> +
> + intel_bb_ptr_align(ibb, 64);
> + offset = intel_bb_offset(ibb);
> + ss = intel_bb_ptr(ibb);
> + intel_bb_ptr_add(ibb, 64);
> +
> + ss->ss0.surface_type = SURFACE_2D;
> + ss->ss0.surface_format = format;
> + ss->ss0.render_cache_read_write = 1;
> + ss->ss0.vertical_alignment = 1; /* align 4 */
> + ss->ss0.horizontal_alignment = 1; /* align 4 */
> +
> + if (buf->tiling == I915_TILING_X)
> + ss->ss0.tiled_mode = 2;
> + else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
> + ss->ss0.tiled_mode = 3;
> +
> + address = intel_bb_offset_reloc(ibb, buf->handle,
> + read_domain, write_domain,
> + offset + 4 * 8, 0x0);
> +
> + ss->ss8.base_addr_lo = (uint32_t) address;
> + ss->ss9.base_addr_hi = address >> 32;
> +
> + ss->ss2.height = intel_buf_height(buf) - 1;
> + ss->ss2.width = intel_buf_width(buf) - 1;
> + ss->ss3.pitch = buf->surface[0].stride - 1;
> +
> + ss->ss7.shader_channel_select_r = 4;
> + ss->ss7.shader_channel_select_g = 5;
> + ss->ss7.shader_channel_select_b = 6;
> + ss->ss7.shader_channel_select_a = 7;
> +
> + return offset;
> +}
> +
> +void
> +xeph_emit_cfe_state(struct intel_bb *ibb, uint32_t threads)
> +{
> + bool dfeud = CFE_CAN_DISABLE_FUSED_EU_DISPATCH(ibb->devid);
> +
> + intel_bb_out(ibb, XEPH_CFE_STATE | (6 - 2));
> +
> + /* scratch buffer */
> + intel_bb_out(ibb, 0);
> + intel_bb_out(ibb, 0);
> +
> +#define _LEGACY_MODE (1 << 6)
> + /* number of threads & urb entries */
> + intel_bb_out(ibb, (max_t(threads, threads, 64) - 1) << 16 | (dfeud ? _LEGACY_MODE : 0));
> +
> + intel_bb_out(ibb, 0);
> + intel_bb_out(ibb, 0);
> +}
> +
> +void
> +xeph_emit_state_compute_mode(struct intel_bb *ibb)
> +{
> + intel_bb_out(ibb, XEPH_STATE_COMPUTE_MODE);
> + intel_bb_out(ibb, 0);
> +}
> +
> +void
> +xeph_emit_state_binding_table_pool_alloc(struct intel_bb *ibb)
> +{
> + intel_bb_out(ibb, GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC | 2);
> + intel_bb_emit_reloc(ibb, ibb->handle,
> + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
> + 0, 0, 0x0);
> + intel_bb_out(ibb, 1 << 12);
> +}
> +
> +void
> +xeph_emit_state_base_address(struct intel_bb *ibb)
> +{
> + intel_bb_out(ibb, GEN8_STATE_BASE_ADDRESS | 0x14); //dw0
> +
> + /* general */
> + intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); //dw1-dw2
> + intel_bb_out(ibb, 0);
> +
> + /* stateless data port */
> + intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); //dw3
> +
> + /* surface */
> + intel_bb_emit_reloc(ibb, ibb->handle, I915_GEM_DOMAIN_SAMPLER, //dw4-dw5
> + 0, BASE_ADDRESS_MODIFY, 0x0);
> +
> + /* dynamic */
> + intel_bb_emit_reloc(ibb, ibb->handle, //dw6-dw7
> + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
> + 0, BASE_ADDRESS_MODIFY, 0x0);
> +
> + /* indirect */
> + intel_bb_out(ibb, 0); //dw8-dw9
> + intel_bb_out(ibb, 0);
> +
> + /* instruction */
> + intel_bb_emit_reloc(ibb, ibb->handle,
> + I915_GEM_DOMAIN_INSTRUCTION, //dw10-dw11
> + 0, BASE_ADDRESS_MODIFY, 0x0);
> +
> + /* general state buffer size */
> + intel_bb_out(ibb, 0xfffff000 | 1); //dw12
> + /* dynamic state buffer size */
> + intel_bb_out(ibb, 1 << 12 | 1); //dw13
> + /* indirect object buffer size */
> + intel_bb_out(ibb, 0xfffff000 | 1); //dw14
> + /* intruction buffer size */
> + intel_bb_out(ibb, 1 << 12 | 1); //dw15
> +
> + /* Bindless surface state base address */
> + intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); //dw16
> + intel_bb_out(ibb, 0); //dw17
> + intel_bb_out(ibb, 0xfffff000); //dw18
> +
> + /* Bindless sampler state base address */
> + intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); //dw19
> + intel_bb_out(ibb, 0); //dw20
> + intel_bb_out(ibb, 0); //dw21
> +}
> +
> +void
> +xeph_emit_compute_walk(struct intel_bb *ibb,
> + unsigned int width, unsigned int height,
> + struct xeph_interface_descriptor_data *pidd,
> + uint8_t color)
> +{
> + uint32_t x_dim, y_dim;
> +
> + /*
> + * Simply do SIMD16 based dispatch, so every thread uses
> + * SIMD16 channels.
> + *
> + * Define our own thread group size, e.g 16x1 for every group, then
> + * will have 1 thread each group in SIMD16 dispatch. So thread
> + * width/height/depth are all 1.
> + *
> + * Then thread group X = width / 16 (aligned to 16)
> + * thread group Y = height;
> + */
> + x_dim = (width + 15) / 16;
> + y_dim = height;
> +
> + intel_bb_out(ibb, XEPH_COMPUTE_WALKER | 0x25);
> +
> + intel_bb_out(ibb, 0); /* debug object */ //dw1
> + intel_bb_out(ibb, 0); /* indirect data length */ //dw2
> + intel_bb_out(ibb, 0); /* indirect data offset */ //dw3
> +
> + /* SIMD size */
> + intel_bb_out(ibb, 1 << 30 | 1 << 25); /* SIMD16 | enable inline */ //dw4
> +
> + /* Execution mask */
> + intel_bb_out(ibb, 0xffffffff); //dw5
> +
> + /* x/y/z max */
> + intel_bb_out(ibb, (x_dim << 20) | (y_dim << 10) | 1); //dw6
> +
> + /* x dim */
> + intel_bb_out(ibb, x_dim); //dw7
> +
> + /* y dim */
> + intel_bb_out(ibb, y_dim); //dw8
> +
> + /* z dim */
> + intel_bb_out(ibb, 1); //dw9
> +
> + /* group id x/y/z */
> + intel_bb_out(ibb, 0); //dw10
> + intel_bb_out(ibb, 0); //dw11
> + intel_bb_out(ibb, 0); //dw12
> +
> + /* partition id / partition size */
> + intel_bb_out(ibb, 0); //dw13
> + intel_bb_out(ibb, 0); //dw14
> +
> + /* preempt x/y/z */
> + intel_bb_out(ibb, 0); //dw15
> + intel_bb_out(ibb, 0); //dw16
> + intel_bb_out(ibb, 0); //dw17
> +
> + /* Interface descriptor data */
> + for (int i = 0; i < 8; i++) { //dw18-25
> + intel_bb_out(ibb, ((uint32_t *) pidd)[i]);
> + }
> +
> + /* Postsync data */
> + intel_bb_out(ibb, 0); //dw26
> + intel_bb_out(ibb, 0); //dw27
> + intel_bb_out(ibb, 0); //dw28
> + intel_bb_out(ibb, 0); //dw29
> + intel_bb_out(ibb, 0); //dw30
> +
> + /* Inline data */
> + intel_bb_out(ibb, (uint32_t) color); //dw31
> + for (int i = 0; i < 7; i++) { //dw32-38
> + intel_bb_out(ibb, 0x0);
> + }
> +}
> diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
> index 56f09b6e1e..ac9d4c07c8 100644
> --- a/lib/gpu_cmds.h
> +++ b/lib/gpu_cmds.h
> @@ -30,6 +30,7 @@
> #include "media_fill.h"
> #include "gen7_media.h"
> #include "gen8_media.h"
> +#include "xeph_media.h"
> #include "intel_reg.h"
> #include "drmtest.h"
> #include "intel_batchbuffer.h"
> @@ -107,4 +108,38 @@ void
> gen7_emit_media_objects(struct intel_bb *ibb,
> unsigned int x, unsigned int y,
> unsigned int width, unsigned int height);
> +
> +void
> +xeph_fill_interface_descriptor(struct intel_bb *ibb,
> + struct intel_buf *dst,
> + const uint32_t kernel[][4],
> + size_t size,
> + struct xeph_interface_descriptor_data *idd);
> +
> +uint32_t
> +xeph_fill_surface_state(struct intel_bb *ibb,
> + struct intel_buf *buf,
> + uint32_t format,
> + int is_dst);
> +
> +void
> +xeph_emit_state_compute_mode(struct intel_bb *ibb);
> +
> +void
> +xeph_emit_state_binding_table_pool_alloc(struct intel_bb *ibb);
> +
> +void
> +xeph_emit_cfe_state(struct intel_bb *ibb, uint32_t threads);
> +
> +#define CFE_CAN_DISABLE_FUSED_EU_DISPATCH(devid) (IS_DG2(devid))
> +
> +void
> +xeph_emit_state_base_address(struct intel_bb *ibb);
> +
> +void
> +xeph_emit_compute_walk(struct intel_bb *ibb,
> + unsigned int width, unsigned int height,
> + struct xeph_interface_descriptor_data *pidd,
> + uint8_t color);
> +
> #endif /* GPU_CMDS_H */
> diff --git a/lib/i915/shaders/gpgpu/xeph_gpgpu_kernel.asm b/lib/i915/shaders/gpgpu/xeph_gpgpu_kernel.asm
> new file mode 100644
> index 0000000000..7adfbd0f04
> --- /dev/null
> +++ b/lib/i915/shaders/gpgpu/xeph_gpgpu_kernel.asm
> @@ -0,0 +1,12 @@
> +L0:
> + mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub
> + shl (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud 0x4:ud
> + mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud
> + mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud
> + mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud {I@2}
> + mov (1|M0) r4.2<1>:ud 0xF:ud
> + mov (16|M0) r5.0<1>:ud r1.0<0;1,0>:ud {I@6}
> +(W) sync.nop null {I@1}
> + send.dc1 (16|M0) null r4 null 0x0 0x40A8000 {$0} // wr:2h+0, rd:0, Media Block Write msc:0, to #0
> + send.gtwy (8|M0) null r80 null 0x0 0x02000000 {EOT}
> +L176:
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index da4c238cae..6850f3a864 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -747,16 +747,18 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid)
> {
> igt_fillfunc_t fill = NULL;
>
> - if (IS_GEN7(devid))
> - fill = gen7_gpgpu_fillfunc;
> - else if (IS_GEN8(devid))
> - fill = gen8_gpgpu_fillfunc;
> - else if (IS_GEN9(devid) || IS_GEN10(devid))
> - fill = gen9_gpgpu_fillfunc;
> - else if (IS_GEN11(devid))
> - fill = gen11_gpgpu_fillfunc;
> + if (intel_graphics_ver(devid) >= IP_VER(12, 50))
> + fill = xeph_gpgpu_fillfunc;
> else if (IS_GEN12(devid))
> fill = gen12_gpgpu_fillfunc;
> + else if (IS_GEN11(devid))
> + fill = gen11_gpgpu_fillfunc;
> + else if (IS_GEN9(devid) || IS_GEN10(devid))
> + fill = gen9_gpgpu_fillfunc;
> + else if (IS_GEN8(devid))
> + fill = gen8_gpgpu_fillfunc;
> + else if (IS_GEN7(devid))
> + fill = gen7_gpgpu_fillfunc;
>
> return fill;
> }
> diff --git a/lib/xeph_media.h b/lib/xeph_media.h
> new file mode 100644
> index 0000000000..0a93e649f0
> --- /dev/null
> +++ b/lib/xeph_media.h
> @@ -0,0 +1,207 @@
> +/* SPDX-License-Identifier: MIT */
Please add Copyright here, with that:
Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
--
Kamil
> +
> +#ifndef XEPH_MEDIA_H
> +#define XEPH_MEDIA_H
> +
> +#include <stdint.h>
> +#include "surfaceformat.h"
> +#include "gen7_media.h"
> +
> +#define GFXPIPE_XEPH(Pipeline, Opcode, Subopcode) ((3 << 29) | \
> + ((Pipeline) << 27) | \
> + ((Opcode) << 24) | \
> + ((Subopcode) << 18))
> +
> +#define XEPH_STATE_COMPUTE_MODE GFXPIPE(0, 1, 5)
> +#define XEPH_CFE_STATE GFXPIPE_XEPH(2, 2, 0)
> +#define XEPH_COMPUTE_WALKER GFXPIPE_XEPH(2, 2, 2)
> +
> +#define BITRANGE(start, end) (end - start + 1)
> +
> +struct xeph_interface_descriptor_data {
> + struct {
> + uint32_t pad0: BITRANGE(0, 5);
> + uint32_t kernel_start_pointer: BITRANGE(6, 31);
> + } desc0;
> +
> + struct {
> + uint32_t kernel_start_pointer_high: BITRANGE(0, 15);
> + uint32_t pad0: BITRANGE(16, 31);
> + } desc1;
> +
> + struct {
> + uint32_t pad0: BITRANGE(0, 6);
> + uint32_t software_exception_enable: BITRANGE(7, 7);
> + uint32_t pad1: BITRANGE(8, 10);
> + uint32_t maskstack_exception_enable: BITRANGE(11, 11);
> + uint32_t pad2: BITRANGE(12, 12);
> + uint32_t illegal_opcode_exception_enable: BITRANGE(13, 13);
> + uint32_t pad3: BITRANGE(14, 15);
> + uint32_t floating_point_mode: BITRANGE(16, 16);
> + uint32_t pad4: BITRANGE(17, 17);
> + uint32_t single_program_flow: BITRANGE(18, 18);
> + uint32_t denorm_mode: BITRANGE(19, 19);
> + uint32_t thread_preemption_disable: BITRANGE(20, 20);
> + uint32_t pad5: BITRANGE(21, 31);
> + } desc2;
> +
> + struct {
> + uint32_t pad0: BITRANGE(0, 1);
> + uint32_t sampler_count: BITRANGE(2, 4);
> + uint32_t sampler_state_pointer: BITRANGE(5, 31);
> + } desc3;
> +
> + struct {
> + uint32_t binding_table_entry_count: BITRANGE(0, 4);
> + uint32_t binding_table_pointer: BITRANGE(5, 20);
> + uint32_t pad0: BITRANGE(21, 31);
> + } desc4;
> +
> + struct {
> + uint32_t num_threads_in_tg: BITRANGE(0, 9);
> + uint32_t pad0: BITRANGE(10, 15);
> + uint32_t shared_local_memory_size: BITRANGE(16, 20);
> + uint32_t barrier_enable: BITRANGE(21, 21);
> + uint32_t rounding_mode: BITRANGE(22, 23);
> + uint32_t pad1: BITRANGE(24, 26);
> + uint32_t thread_group_dispatch_size: BITRANGE(27, 27);
> + uint32_t pad2: BITRANGE(28, 31);
> + } desc5;
> +
> + struct {
> + uint32_t pad0;
> + } desc6;
> +
> + struct {
> + uint32_t pad0;
> + } desc7;
> +};
> +
> +struct xeph_surface_state {
> + struct {
> + uint32_t cube_pos_z: BITRANGE(0, 0);
> + uint32_t cube_neg_z: BITRANGE(1, 1);
> + uint32_t cube_pos_y: BITRANGE(2, 2);
> + uint32_t cube_neg_y: BITRANGE(3, 3);
> + uint32_t cube_pos_x: BITRANGE(4, 4);
> + uint32_t cube_neg_x: BITRANGE(5, 5);
> + uint32_t media_boundary_pixel_mode: BITRANGE(6, 7);
> + uint32_t render_cache_read_write: BITRANGE(8, 8);
> + uint32_t sampler_l2_bypass_disable: BITRANGE(9, 9);
> + uint32_t vert_line_stride_ofs: BITRANGE(10, 10);
> + uint32_t vert_line_stride: BITRANGE(11, 11);
> + uint32_t tiled_mode: BITRANGE(12, 13);
> + uint32_t horizontal_alignment: BITRANGE(14, 15);
> + uint32_t vertical_alignment: BITRANGE(16, 17);
> + uint32_t surface_format: BITRANGE(18, 26); /**< BRW_SURFACEFORMAT_x */
> + uint32_t astc_enable: BITRANGE(27, 27);
> + uint32_t is_array: BITRANGE(28, 28);
> + uint32_t surface_type: BITRANGE(29, 31); /**< BRW_SURFACE_1D/2D/3D/CUBE */
> + } ss0;
> +
> + struct {
> + uint32_t qpitch: BITRANGE(0, 14);
> + uint32_t sample_tap_discard_disable: BITRANGE(15, 15);
> + uint32_t pad0: BITRANGE(16, 16);
> + uint32_t double_fetch_disable: BITRANGE(17, 17);
> + uint32_t corner_texel_mode: BITRANGE(18, 18);
> + uint32_t base_mip_level: BITRANGE(19, 23);
> + uint32_t memory_object_control: BITRANGE(24, 30);
> + uint32_t unorm_path_in_color_pipe: BITRANGE(31, 31);
> + } ss1;
> +
> + struct {
> + uint32_t width: BITRANGE(0, 13);
> + uint32_t pad0: BITRANGE(14, 15);
> + uint32_t height: BITRANGE(16, 29);
> + uint32_t pad1: BITRANGE(30, 30);
> + uint32_t depth_stencil_resource: BITRANGE(31, 31);
> + } ss2;
> +
> + struct {
> + uint32_t pitch: BITRANGE(0, 17);
> + uint32_t null_probing_enable: BITRANGE(18, 18);
> + uint32_t standard_tiling_mode_ext: BITRANGE(19, 19);
> + uint32_t pad0: BITRANGE(20, 20);
> + uint32_t depth: BITRANGE(21, 31);
> + } ss3;
> +
> + struct {
> + uint32_t multisample_position_palette_index: BITRANGE(0, 2);
> + uint32_t num_multisamples: BITRANGE(3, 5);
> + uint32_t multisampled_surface_storage_format: BITRANGE(6, 6);
> + uint32_t render_target_view_extent: BITRANGE(7, 17);
> + uint32_t min_array_element: BITRANGE(18, 28);
> + uint32_t rotation: BITRANGE(29, 30);
> + uint32_t decompress_in_l3: BITRANGE(31, 31);
> + } ss4;
> +
> + struct {
> + uint32_t mip_count: BITRANGE(0, 3);
> + uint32_t surface_min_lod: BITRANGE(4, 7);
> + uint32_t mip_tail_start_lod: BITRANGE(8, 11);
> + uint32_t yuv_bpt: BITRANGE(12, 13);
> + uint32_t coherency_type: BITRANGE(14, 15);
> + uint32_t pad0: BITRANGE(16, 17);
> + uint32_t tiled_resource_mode: BITRANGE(18, 19);
> + uint32_t ewa_disable_for_cube: BITRANGE(20, 20);
> + uint32_t y_offset: BITRANGE(21, 23);
> + uint32_t pad1: BITRANGE(24, 24);
> + uint32_t x_offset: BITRANGE(25, 31);
> + } ss5;
> +
> + struct {
> + uint32_t pad; /* Multisample Control Surface stuff */
> + } ss6;
> +
> + struct {
> + uint32_t resource_min_lod: BITRANGE(0, 11);
> + uint32_t pad0: BITRANGE(12, 13);
> + uint32_t disable_support_for_multigpu_atomics: BITRANGE(14, 14);
> + uint32_t disable_support_for_multigpu_partwrite: BITRANGE(15, 15);
> + uint32_t shader_channel_select_a: BITRANGE(16, 18);
> + uint32_t shader_channel_select_b: BITRANGE(19, 21);
> + uint32_t shader_channel_select_g: BITRANGE(22, 24);
> + uint32_t shader_channel_select_r: BITRANGE(25, 27);
> + uint32_t pad1: BITRANGE(28, 29);
> + uint32_t memory_compression_enable: BITRANGE(30, 30);
> + uint32_t memory_compression_mode: BITRANGE(31, 31);
> + } ss7;
> +
> + struct {
> + uint32_t base_addr_lo;
> + } ss8;
> +
> + struct {
> + uint32_t base_addr_hi;
> + } ss9;
> +
> + struct {
> + uint32_t pad0: BITRANGE(0, 11);
> + uint32_t aux_base_addr_lo: BITRANGE(12, 31);
> + } ss10;
> +
> + struct {
> + uint32_t aux_base_addr_hi;
> + } ss11;
> +
> + struct {
> + uint32_t compression_format: BITRANGE(0, 4);
> + uint32_t clear_address_lo: BITRANGE(5, 31);
> + } ss12;
> +
> + struct {
> + uint32_t clear_address_hi: BITRANGE(0, 15);
> + uint32_t pad0: BITRANGE(16, 31);
> + } ss13;
> +
> + struct {
> + uint32_t reserved;
> + } ss14;
> +
> + struct {
> + uint32_t reserved;
> + } ss15;
> +};
> +
> +#endif /* XEPH_MEDIA_H */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
2023-03-27 15:43 [igt-dev] [PATCH i-g-t] lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH Zbigniew Kempczyński
` (3 preceding siblings ...)
2023-03-28 13:06 ` [igt-dev] [PATCH i-g-t] " Kamil Konieczny
@ 2023-03-28 13:12 ` Matthew Auld
2023-03-28 14:46 ` Zbigniew Kempczyński
4 siblings, 1 reply; 9+ messages in thread
From: Matthew Auld @ 2023-03-28 13:12 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Mon, 27 Mar 2023 at 16:44, Zbigniew Kempczyński
<zbigniew.kempczynski@intel.com> wrote:
>
> From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
>
> Adding xeph_gpgpu_fillfunc to have gpgpu_fill running on XEPH (DG2).
> On XEPH there's no GPGPU_WALK command, it has COMPUTE_WALK what requires
> pipeline creation change.
Just a drive-by-comment, what is XEPH? Also in the patch itself. I
have only ever seen XEHP and XELP. Is this a typo? s/PH/HP/ ?
>
> Shader used in the test was taken from previous generation with
> adding SWSB dependency tracking. SWSB was added using iga64 automatic
> dependency generating:
>
> iga64 -p=12p5 -Xauto-deps shader.asm
>
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH
2023-03-28 13:12 ` Matthew Auld
@ 2023-03-28 14:46 ` Zbigniew Kempczyński
0 siblings, 0 replies; 9+ messages in thread
From: Zbigniew Kempczyński @ 2023-03-28 14:46 UTC (permalink / raw)
To: Matthew Auld; +Cc: igt-dev
On Tue, Mar 28, 2023 at 02:12:59PM +0100, Matthew Auld wrote:
> On Mon, 27 Mar 2023 at 16:44, Zbigniew Kempczyński
> <zbigniew.kempczynski@intel.com> wrote:
> >
> > From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> >
> > Adding xeph_gpgpu_fillfunc to have gpgpu_fill running on XEPH (DG2).
> > On XEPH there's no GPGPU_WALK command, it has COMPUTE_WALK what requires
> > pipeline creation change.
>
> Just a drive-by-comment, what is XEPH? Also in the patch itself. I
> have only ever seen XEHP and XELP. Is this a typo? s/PH/HP/ ?
You're right, XEHP should be there.
Don't ask me about rationale with using names instead of versioning
strings - it is out of my decision.
--
Zbigniew
>
> >
> > Shader used in the test was taken from previous generation with
> > adding SWSB dependency tracking. SWSB was added using iga64 automatic
> > dependency generating:
> >
> > iga64 -p=12p5 -Xauto-deps shader.asm
> >
> > Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> > Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-03-28 14:46 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2023-03-27 15:43 [igt-dev] [PATCH i-g-t] lib/gpgpu_fill: Implement gpgpu_fillfunc for XEPH Zbigniew Kempczyński
2023-03-27 18:27 ` [igt-dev] ✗ Fi.CI.BAT: failure for " Patchwork
2023-03-27 18:48 ` Zbigniew Kempczyński
2023-03-28 5:02 ` Yedireswarapu, SaiX Nandan
2023-03-28 4:37 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2023-03-28 12:02 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2023-03-28 13:06 ` [igt-dev] [PATCH i-g-t] " Kamil Konieczny
2023-03-28 13:12 ` Matthew Auld
2023-03-28 14:46 ` Zbigniew Kempczyński
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