* [igt-dev] [PATCH v2 1/7] xe: Update to latest uAPI
2023-05-02 6:55 [igt-dev] [PATCH v2 0/7] IGT updates for upstreaming prep Matthew Brost
@ 2023-05-02 6:55 ` Matthew Brost
2023-05-02 6:55 ` [igt-dev] [PATCH v2 2/7] xe_exec_basic: Add NULL VM bind section Matthew Brost
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Matthew Brost @ 2023-05-02 6:55 UTC (permalink / raw)
To: igt-dev
Includes NULL bindings support.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
include/drm-uapi/xe_drm.h | 27 ++++++++++++++++++---------
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 593b01ba5..27c51946f 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -37,7 +37,7 @@ extern "C" {
*/
/**
- * struct i915_user_extension - Base class for defining a chain of extensions
+ * struct xe_user_extension - Base class for defining a chain of extensions
*
* Many interfaces need to grow over time. In most cases we can simply
* extend the struct and have userspace pass in more data. Another option,
@@ -55,20 +55,20 @@ extern "C" {
*
* .. code-block:: C
*
- * struct i915_user_extension ext3 {
+ * struct xe_user_extension ext3 {
* .next_extension = 0, // end
* .name = ...,
* };
- * struct i915_user_extension ext2 {
+ * struct xe_user_extension ext2 {
* .next_extension = (uintptr_t)&ext3,
* .name = ...,
* };
- * struct i915_user_extension ext1 {
+ * struct xe_user_extension ext1 {
* .next_extension = (uintptr_t)&ext2,
* .name = ...,
* };
*
- * Typically the struct i915_user_extension would be embedded in some uAPI
+ * Typically the struct xe_user_extension would be embedded in some uAPI
* struct, and in this case we would feed it the head of the chain(i.e ext1),
* which would then apply all of the above extensions.
*
@@ -77,7 +77,7 @@ struct xe_user_extension {
/**
* @next_extension:
*
- * Pointer to the next struct i915_user_extension, or zero if the end.
+ * Pointer to the next struct xe_user_extension, or zero if the end.
*/
__u64 next_extension;
/**
@@ -87,7 +87,7 @@ struct xe_user_extension {
*
* Also note that the name space for this is not global for the whole
* driver, but rather its scope/meaning is limited to the specific piece
- * of uAPI which has embedded the struct i915_user_extension.
+ * of uAPI which has embedded the struct xe_user_extension.
*/
__u32 name;
/**
@@ -99,7 +99,7 @@ struct xe_user_extension {
};
/*
- * i915 specific ioctls.
+ * xe specific ioctls.
*
* The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
* [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
@@ -184,7 +184,8 @@ struct drm_xe_query_config {
#define XE_QUERY_CONFIG_VA_BITS 3
#define XE_QUERY_CONFIG_GT_COUNT 4
#define XE_QUERY_CONFIG_MEM_REGION_COUNT 5
-#define XE_QUERY_CONFIG_NUM_PARAM XE_QUERY_CONFIG_MEM_REGION_COUNT + 1
+#define XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY 6
+#define XE_QUERY_CONFIG_NUM_PARAM XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY + 1
__u64 info[];
};
@@ -446,6 +447,14 @@ struct drm_xe_vm_bind_op {
* than differing the MAP to the page fault handler.
*/
#define XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 18)
+ /*
+ * When the NULL flag is set, the page tables are setup with a special
+ * bit which indicates writes are dropped and all reads return zero. The
+ * NULL flags is only valid for XE_VM_BIND_OP_MAP operations, the BO
+ * handle MBZ, and the BO offset MBZ. This flag is intended to implement
+ * VK sparse bindings.
+ */
+#define XE_VM_BIND_FLAG_NULL (0x1 << 19)
/** @reserved: Reserved */
__u64 reserved[2];
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [igt-dev] [PATCH v2 2/7] xe_exec_basic: Add NULL VM bind section
2023-05-02 6:55 [igt-dev] [PATCH v2 0/7] IGT updates for upstreaming prep Matthew Brost
2023-05-02 6:55 ` [igt-dev] [PATCH v2 1/7] xe: Update to latest uAPI Matthew Brost
@ 2023-05-02 6:55 ` Matthew Brost
2023-05-02 6:55 ` [igt-dev] [PATCH v2 3/7] xe_vm: MMAP style VM binds section Matthew Brost
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Matthew Brost @ 2023-05-02 6:55 UTC (permalink / raw)
To: igt-dev
A NULL VM bind results in writes being dropped and reads returning zero,
verify uAPI for NULL VM binds is working as designed.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
tests/xe/xe_exec_basic.c | 33 ++++++++++++++++++++++++++++-----
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/tests/xe/xe_exec_basic.c b/tests/xe/xe_exec_basic.c
index 2a176a5b3..f7ad6aeeb 100644
--- a/tests/xe/xe_exec_basic.c
+++ b/tests/xe/xe_exec_basic.c
@@ -27,6 +27,7 @@
#define BIND_ENGINE (0x1 << 4)
#define DEFER_ALLOC (0x1 << 5)
#define DEFER_BIND (0x1 << 6)
+#define SPARSE (0x1 << 7)
/**
* SUBTEST: once-%s
@@ -67,6 +68,10 @@
* @userptr-rebind: userptr rebind
* @userptr-invalidate: userptr invalidate
* @userptr-invalidate-race: userptr invalidate racy
+ * @null: null
+ * @null-defer-mmap: null defer mmap
+ * @null-defer-bind: null defer bind
+ * @null-rebind: null rebind
* @bindengine: bind engine
* @bindengine-userptr: bind engine userptr description
* @bindengine-rebind: bind engine rebind description
@@ -89,6 +94,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
.syncs = to_user_pointer(sync),
};
uint64_t addr[MAX_N_ENGINES];
+ uint64_t sparse_addr[MAX_N_ENGINES];
uint32_t vm[MAX_N_ENGINES];
uint32_t engines[MAX_N_ENGINES];
uint32_t bind_engines[MAX_N_ENGINES];
@@ -113,8 +119,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
xe_get_default_alignment(fd));
addr[0] = 0x1a0000;
- for (i = 1; i < MAX_N_ENGINES; ++i)
+ sparse_addr[0] = 0x301a0000;
+ for (i = 1; i < MAX_N_ENGINES; ++i) {
addr[i] = addr[i - 1] + (0x1ull << 32);
+ sparse_addr[i] = sparse_addr[i - 1] + (0x1ull << 32);
+ }
if (flags & USERPTR) {
#define MAP_ADDRESS 0x00007fadeadbe000
@@ -163,6 +172,13 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
xe_vm_bind_userptr_async(fd, vm[i], bind_engines[i],
to_user_pointer(data), addr[i],
bo_size, sync, 1);
+ if (flags & SPARSE)
+ __xe_vm_bind_assert(fd, vm[i], bind_engines[i],
+ 0, 0, sparse_addr[i], bo_size,
+ XE_VM_BIND_OP_MAP |
+ XE_VM_BIND_FLAG_ASYNC |
+ XE_VM_BIND_FLAG_NULL, sync,
+ 1, 0, 0);
}
if (flags & DEFER_BIND)
@@ -174,7 +190,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
uint64_t batch_addr = __addr + batch_offset;
uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
- uint64_t sdi_addr = __addr + sdi_offset;
+ uint64_t sdi_addr = (flags & SPARSE ? sparse_addr[i % n_vm] :
+ __addr)+ sdi_offset;
int e = i % n_engines;
b = 0;
@@ -261,9 +278,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
INT64_MAX, 0, NULL));
}
- for (i = (flags & INVALIDATE && n_execs) ? n_execs - 1 : 0;
- i < n_execs; i++)
- igt_assert_eq(data[i].data, 0xc0ffee);
+ if (!(flags & SPARSE)) {
+ for (i = (flags & INVALIDATE && n_execs) ? n_execs - 1 : 0;
+ i < n_execs; i++)
+ igt_assert_eq(data[i].data, 0xc0ffee);
+ }
for (i = 0; i < n_engines; i++) {
syncobj_destroy(fd, syncobjs[i]);
@@ -296,6 +315,10 @@ igt_main
{ "basic-defer-bind", DEFER_ALLOC | DEFER_BIND },
{ "userptr", USERPTR },
{ "rebind", REBIND },
+ { "null", SPARSE },
+ { "null-defer-mmap", SPARSE | DEFER_ALLOC },
+ { "null-defer-bind", SPARSE | DEFER_ALLOC | DEFER_BIND },
+ { "null-rebind", SPARSE | REBIND },
{ "userptr-rebind", USERPTR | REBIND },
{ "userptr-invalidate", USERPTR | INVALIDATE },
{ "userptr-invalidate-race", USERPTR | INVALIDATE | RACE },
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [igt-dev] [PATCH v2 3/7] xe_vm: MMAP style VM binds section
2023-05-02 6:55 [igt-dev] [PATCH v2 0/7] IGT updates for upstreaming prep Matthew Brost
2023-05-02 6:55 ` [igt-dev] [PATCH v2 1/7] xe: Update to latest uAPI Matthew Brost
2023-05-02 6:55 ` [igt-dev] [PATCH v2 2/7] xe_exec_basic: Add NULL VM bind section Matthew Brost
@ 2023-05-02 6:55 ` Matthew Brost
2023-05-02 6:55 ` [igt-dev] [PATCH v2 4/7] xe_vm: Add mmap / munmap sections that split large pages Matthew Brost
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Matthew Brost @ 2023-05-02 6:55 UTC (permalink / raw)
To: igt-dev
GPUVA added support for this let's test it.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
tests/xe/xe_vm.c | 350 ++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 314 insertions(+), 36 deletions(-)
diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
index d4cec104e..038a80600 100644
--- a/tests/xe/xe_vm.c
+++ b/tests/xe/xe_vm.c
@@ -1233,9 +1233,9 @@ static void *hammer_thread(void *tdata)
return NULL;
}
-#define MUNMAP_FLAG_USERPTR (0x1 << 0)
-#define MUNMAP_FLAG_INVALIDATE (0x1 << 1)
-#define MUNMAP_FLAG_HAMMER_FIRST_PAGE (0x1 << 2)
+#define MAP_FLAG_USERPTR (0x1 << 0)
+#define MAP_FLAG_INVALIDATE (0x1 << 1)
+#define MAP_FLAG_HAMMER_FIRST_PAGE (0x1 << 2)
/**
@@ -1327,7 +1327,7 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
bo_size = page_size * bo_n_pages;
- if (flags & MUNMAP_FLAG_USERPTR) {
+ if (flags & MAP_FLAG_USERPTR) {
map = mmap(from_user_pointer(addr), bo_size, PROT_READ |
PROT_WRITE, MAP_SHARED | MAP_FIXED |
MAP_ANONYMOUS, -1, 0);
@@ -1346,7 +1346,7 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
/* Do initial binds */
bind_size = (page_size * bo_n_pages) / n_binds;
for (i = 0; i < n_binds; ++i) {
- if (flags & MUNMAP_FLAG_USERPTR)
+ if (flags & MAP_FLAG_USERPTR)
xe_vm_bind_userptr_async(fd, vm, 0, addr, addr,
bind_size, sync, 1);
else
@@ -1361,7 +1361,7 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
* cause a fault if a rebind occurs during munmap style VM unbind
* (partial VMAs unbound).
*/
- if (flags & MUNMAP_FLAG_HAMMER_FIRST_PAGE) {
+ if (flags & MAP_FLAG_HAMMER_FIRST_PAGE) {
t.fd = fd;
t.vm = vm;
#define PAGE_SIZE 4096
@@ -1420,7 +1420,7 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
data = map + i * page_size;
igt_assert_eq(data->data, 0xc0ffee);
}
- if (flags & MUNMAP_FLAG_HAMMER_FIRST_PAGE) {
+ if (flags & MAP_FLAG_HAMMER_FIRST_PAGE) {
memset(map, 0, PAGE_SIZE / 2);
memset(map + PAGE_SIZE, 0, bo_size - PAGE_SIZE);
} else {
@@ -1470,7 +1470,7 @@ try_again_after_invalidate:
igt_assert_eq(data->data, 0xc0ffee);
}
}
- if (flags & MUNMAP_FLAG_HAMMER_FIRST_PAGE) {
+ if (flags & MAP_FLAG_HAMMER_FIRST_PAGE) {
memset(map, 0, PAGE_SIZE / 2);
memset(map + PAGE_SIZE, 0, bo_size - PAGE_SIZE);
} else {
@@ -1481,7 +1481,7 @@ try_again_after_invalidate:
* The munmap style VM unbind can create new VMAs, make sure those are
* in the bookkeeping for another rebind after a userptr invalidate.
*/
- if (flags & MUNMAP_FLAG_INVALIDATE && !invalidate++) {
+ if (flags & MAP_FLAG_INVALIDATE && !invalidate++) {
map = mmap(from_user_pointer(addr), bo_size, PROT_READ |
PROT_WRITE, MAP_SHARED | MAP_FIXED |
MAP_ANONYMOUS, -1, 0);
@@ -1492,7 +1492,7 @@ try_again_after_invalidate:
/* Confirm unbound region can be rebound */
syncobj_reset(fd, &sync[0].handle, 1);
sync[0].flags |= DRM_XE_SYNC_SIGNAL;
- if (flags & MUNMAP_FLAG_USERPTR)
+ if (flags & MAP_FLAG_USERPTR)
xe_vm_bind_userptr_async(fd, vm, 0,
addr + unbind_n_page_offfset * page_size,
addr + unbind_n_page_offfset * page_size,
@@ -1540,7 +1540,7 @@ try_again_after_invalidate:
igt_assert_eq(data->data, 0xc0ffee);
}
- if (flags & MUNMAP_FLAG_HAMMER_FIRST_PAGE) {
+ if (flags & MAP_FLAG_HAMMER_FIRST_PAGE) {
exit = 1;
pthread_join(t.thread, NULL);
pthread_barrier_destroy(&barrier);
@@ -1555,6 +1555,251 @@ try_again_after_invalidate:
xe_vm_destroy(fd, vm);
}
+/**
+ * SUBTEST: mmap-style-bind-%s
+ * Description: Test mmap style unbind with %arg[1]
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ * arg[1]:
+ *
+ * @all: all
+ * @one-partial: one partial
+ * @either-side-partial: either side partial
+ * @either-side-full: either side full
+ * @either-side-partial-hammer: either side partial hammer
+ * @end: end
+ * @front: front
+ * @many-all: many all
+ * @many-either-side-partial: many either side partial
+ * @many-either-side-partial-hammer: many either side partial hammer
+ * @userptr-all: userptr all
+ * @userptr-one-partial: userptr one partial
+ * @userptr-either-side-partial: userptr either side partial
+ * @userptr-either-side-full: userptr either side full
+ */
+
+static void
+test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
+ int bo_n_pages, int n_binds, int unbind_n_page_offfset,
+ int unbind_n_pages, unsigned int flags)
+{
+ struct drm_xe_sync sync[2] = {
+ { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ };
+ struct drm_xe_exec exec = {
+ .num_batch_buffer = 1,
+ .num_syncs = 2,
+ .syncs = to_user_pointer(sync),
+ };
+ uint64_t addr = 0x1a0000, base_addr = 0x1a0000;
+ uint32_t vm;
+ uint32_t engine;
+ size_t bo_size;
+ uint32_t bo0 = 0, bo1 = 0;
+ uint64_t bind_size;
+ uint64_t page_size = xe_get_default_alignment(fd);
+ struct {
+ uint32_t batch[16];
+ uint64_t pad;
+ uint32_t data;
+ } *data;
+ void *map0, *map1;
+ int i, b;
+ struct thread_data t;
+ pthread_barrier_t barrier;
+ int exit = 0;
+
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ bo_size = page_size * bo_n_pages;
+
+ if (flags & MAP_FLAG_USERPTR) {
+ map0 = mmap(from_user_pointer(addr), bo_size, PROT_READ |
+ PROT_WRITE, MAP_SHARED | MAP_FIXED |
+ MAP_ANONYMOUS, -1, 0);
+ map1 = mmap(from_user_pointer(addr + bo_size),
+ bo_size, PROT_READ | PROT_WRITE, MAP_SHARED |
+ MAP_FIXED | MAP_ANONYMOUS, -1, 0);
+ igt_assert(map0 != MAP_FAILED);
+ igt_assert(map1 != MAP_FAILED);
+ } else {
+ bo0 = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+ map0 = xe_bo_map(fd, bo0, bo_size);
+ bo1 = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+ map1 = xe_bo_map(fd, bo1, bo_size);
+ }
+ memset(map0, 0, bo_size);
+ memset(map1, 0, bo_size);
+
+ engine = xe_engine_create(fd, vm, eci, 0);
+
+ sync[0].handle = syncobj_create(fd, 0);
+ sync[1].handle = syncobj_create(fd, 0);
+
+ /* Do initial binds */
+ bind_size = (page_size * bo_n_pages) / n_binds;
+ for (i = 0; i < n_binds; ++i) {
+ if (flags & MAP_FLAG_USERPTR)
+ xe_vm_bind_userptr_async(fd, vm, 0, addr, addr,
+ bind_size, sync, 1);
+ else
+ xe_vm_bind_async(fd, vm, 0, bo0, i * bind_size,
+ addr, bind_size, sync, 1);
+ addr += bind_size;
+ }
+ addr = base_addr;
+
+ /*
+ * Kick a thread to write the first page continously to ensure we can't
+ * cause a fault if a rebind occurs during munmap style VM unbind
+ * (partial VMAs unbound).
+ */
+ if (flags & MAP_FLAG_HAMMER_FIRST_PAGE) {
+ t.fd = fd;
+ t.vm = vm;
+#define PAGE_SIZE 4096
+ t.addr = addr + PAGE_SIZE / 2;
+ t.eci = eci;
+ t.exit = &exit;
+ t.map = map0 + PAGE_SIZE / 2;
+ t.barrier = &barrier;
+ pthread_barrier_init(&barrier, NULL, 2);
+ pthread_create(&t.thread, 0, hammer_thread, &t);
+ pthread_barrier_wait(&barrier);
+ }
+
+ /* Verify we can use every page */
+ for (i = 0; i < n_binds; ++i) {
+ uint64_t batch_offset = (char *)&data->batch - (char *)data;
+ uint64_t batch_addr = addr + batch_offset;
+ uint64_t sdi_offset = (char *)&data->data - (char *)data;
+ uint64_t sdi_addr = addr + sdi_offset;
+ data = map0 + i * page_size;
+
+ b = 0;
+ data->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+ data->batch[b++] = sdi_addr;
+ data->batch[b++] = sdi_addr >> 32;
+ data->batch[b++] = 0xc0ffee;
+ data->batch[b++] = MI_BATCH_BUFFER_END;
+ igt_assert(b <= ARRAY_SIZE(data[i].batch));
+
+ sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ if (i)
+ syncobj_reset(fd, &sync[1].handle, 1);
+ sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+
+ exec.engine_id = engine;
+ exec.address = batch_addr;
+ xe_exec(fd, &exec);
+
+ addr += page_size;
+ }
+ addr = base_addr;
+
+ /* Bind some of the pages to different BO / userptr */
+ syncobj_reset(fd, &sync[0].handle, 1);
+ sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[1].flags &= ~DRM_XE_SYNC_SIGNAL;
+ if (flags & MAP_FLAG_USERPTR)
+ xe_vm_bind_userptr_async(fd, vm, 0, addr + bo_size +
+ unbind_n_page_offfset * page_size,
+ addr + unbind_n_page_offfset * page_size,
+ unbind_n_pages * page_size, sync, 2);
+ else
+ xe_vm_bind_async(fd, vm, 0, bo1,
+ unbind_n_page_offfset * page_size,
+ addr + unbind_n_page_offfset * page_size,
+ unbind_n_pages * page_size, sync, 2);
+ igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
+ igt_assert(syncobj_wait(fd, &sync[1].handle, 1, INT64_MAX, 0, NULL));
+
+ /* Verify all pages written */
+ for (i = 0; i < n_binds; ++i) {
+ data = map0 + i * page_size;
+ igt_assert_eq(data->data, 0xc0ffee);
+ }
+ if (flags & MAP_FLAG_HAMMER_FIRST_PAGE) {
+ memset(map0, 0, PAGE_SIZE / 2);
+ memset(map0 + PAGE_SIZE, 0, bo_size - PAGE_SIZE);
+ } else {
+ memset(map0, 0, bo_size);
+ memset(map1, 0, bo_size);
+ }
+
+ /* Verify we can use every page */
+ for (i = 0; i < n_binds; ++i) {
+ uint64_t batch_offset = (char *)&data->batch - (char *)data;
+ uint64_t batch_addr = addr + batch_offset;
+ uint64_t sdi_offset = (char *)&data->data - (char *)data;
+ uint64_t sdi_addr = addr + sdi_offset;
+
+ data = map0 + i * page_size;
+ b = 0;
+ data->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+ data->batch[b++] = sdi_addr;
+ data->batch[b++] = sdi_addr >> 32;
+ data->batch[b++] = 0xc0ffee;
+ data->batch[b++] = MI_BATCH_BUFFER_END;
+ igt_assert(b <= ARRAY_SIZE(data[i].batch));
+
+ data = map1 + i * page_size;
+ b = 0;
+ data->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+ data->batch[b++] = sdi_addr;
+ data->batch[b++] = sdi_addr >> 32;
+ data->batch[b++] = 0xc0ffee;
+ data->batch[b++] = MI_BATCH_BUFFER_END;
+ igt_assert(b <= ARRAY_SIZE(data[i].batch));
+
+ sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ if (i)
+ syncobj_reset(fd, &sync[1].handle, 1);
+ sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+
+ exec.engine_id = engine;
+ exec.address = batch_addr;
+ xe_exec(fd, &exec);
+
+ addr += page_size;
+ }
+ addr = base_addr;
+
+ igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
+ igt_assert(syncobj_wait(fd, &sync[1].handle, 1, INT64_MAX, 0, NULL));
+
+ /* Verify all pages written */
+ for (i = 0; i < n_binds; ++i) {
+ uint32_t result = 0;
+
+ data = map0 + i * page_size;
+ result |= data->data;
+
+ data = map1 + i * page_size;
+ result |= data->data;
+
+ igt_assert_eq(result, 0xc0ffee);
+ }
+
+ if (flags & MAP_FLAG_HAMMER_FIRST_PAGE) {
+ exit = 1;
+ pthread_join(t.thread, NULL);
+ pthread_barrier_destroy(&barrier);
+ }
+
+ syncobj_destroy(fd, sync[0].handle);
+ syncobj_destroy(fd, sync[1].handle);
+ xe_engine_destroy(fd, engine);
+ munmap(map0, bo_size);
+ munmap(map1, bo_size);
+ if (bo0)
+ gem_close(fd, bo0);
+ if (bo1)
+ gem_close(fd, bo1);
+ xe_vm_destroy(fd, vm);
+}
+
igt_main
{
struct drm_xe_engine_class_instance *hwe, *hwe_non_copy = NULL;
@@ -1567,55 +1812,74 @@ igt_main
int unbind_n_page_offfset;
int unbind_n_pages;
unsigned int flags;
- } sections[] = {
+ } munmap_sections[] = {
{ "all", 4, 2, 0, 4, 0 },
{ "one-partial", 4, 1, 1, 2, 0 },
{ "either-side-partial", 4, 2, 1, 2, 0 },
{ "either-side-partial-hammer", 4, 2, 1, 2,
- MUNMAP_FLAG_HAMMER_FIRST_PAGE },
+ MAP_FLAG_HAMMER_FIRST_PAGE },
{ "either-side-full", 4, 4, 1, 2, 0 },
{ "end", 4, 2, 0, 3, 0 },
{ "front", 4, 2, 1, 3, 0 },
{ "many-all", 4 * 8, 2 * 8, 0 * 8, 4 * 8, 0 },
{ "many-either-side-partial", 4 * 8, 2 * 8, 1, 4 * 8 - 2, 0 },
{ "many-either-side-partial-hammer", 4 * 8, 2 * 8, 1, 4 * 8 - 2,
- MUNMAP_FLAG_HAMMER_FIRST_PAGE },
+ MAP_FLAG_HAMMER_FIRST_PAGE },
{ "many-either-side-full", 4 * 8, 4 * 8, 1 * 8, 2 * 8, 0 },
{ "many-end", 4 * 8, 4, 0 * 8, 3 * 8 + 2, 0 },
{ "many-front", 4 * 8, 4, 1 * 8 - 2, 3 * 8 + 2, 0 },
- { "userptr-all", 4, 2, 0, 4, MUNMAP_FLAG_USERPTR },
- { "userptr-one-partial", 4, 1, 1, 2, MUNMAP_FLAG_USERPTR },
+ { "userptr-all", 4, 2, 0, 4, MAP_FLAG_USERPTR },
+ { "userptr-one-partial", 4, 1, 1, 2, MAP_FLAG_USERPTR },
{ "userptr-either-side-partial", 4, 2, 1, 2,
- MUNMAP_FLAG_USERPTR },
+ MAP_FLAG_USERPTR },
{ "userptr-either-side-full", 4, 4, 1, 2,
- MUNMAP_FLAG_USERPTR },
- { "userptr-end", 4, 2, 0, 3, MUNMAP_FLAG_USERPTR },
- { "userptr-front", 4, 2, 1, 3, MUNMAP_FLAG_USERPTR },
+ MAP_FLAG_USERPTR },
+ { "userptr-end", 4, 2, 0, 3, MAP_FLAG_USERPTR },
+ { "userptr-front", 4, 2, 1, 3, MAP_FLAG_USERPTR },
{ "userptr-many-all", 4 * 8, 2 * 8, 0 * 8, 4 * 8,
- MUNMAP_FLAG_USERPTR },
+ MAP_FLAG_USERPTR },
{ "userptr-many-either-side-full", 4 * 8, 4 * 8, 1 * 8, 2 * 8,
- MUNMAP_FLAG_USERPTR },
+ MAP_FLAG_USERPTR },
{ "userptr-many-end", 4 * 8, 4, 0 * 8, 3 * 8 + 2,
- MUNMAP_FLAG_USERPTR },
+ MAP_FLAG_USERPTR },
{ "userptr-many-front", 4 * 8, 4, 1 * 8 - 2, 3 * 8 + 2,
- MUNMAP_FLAG_USERPTR },
+ MAP_FLAG_USERPTR },
{ "userptr-inval-either-side-full", 4, 4, 1, 2,
- MUNMAP_FLAG_USERPTR | MUNMAP_FLAG_INVALIDATE },
- { "userptr-inval-end", 4, 2, 0, 3, MUNMAP_FLAG_USERPTR |
- MUNMAP_FLAG_INVALIDATE },
- { "userptr-inval-front", 4, 2, 1, 3, MUNMAP_FLAG_USERPTR |
- MUNMAP_FLAG_INVALIDATE },
+ MAP_FLAG_USERPTR | MAP_FLAG_INVALIDATE },
+ { "userptr-inval-end", 4, 2, 0, 3, MAP_FLAG_USERPTR |
+ MAP_FLAG_INVALIDATE },
+ { "userptr-inval-front", 4, 2, 1, 3, MAP_FLAG_USERPTR |
+ MAP_FLAG_INVALIDATE },
{ "userptr-inval-many-all", 4 * 8, 2 * 8, 0 * 8, 4 * 8,
- MUNMAP_FLAG_USERPTR | MUNMAP_FLAG_INVALIDATE },
+ MAP_FLAG_USERPTR | MAP_FLAG_INVALIDATE },
{ "userptr-inval-many-either-side-partial", 4 * 8, 2 * 8, 1,
- 4 * 8 - 2, MUNMAP_FLAG_USERPTR |
- MUNMAP_FLAG_INVALIDATE },
+ 4 * 8 - 2, MAP_FLAG_USERPTR |
+ MAP_FLAG_INVALIDATE },
{ "userptr-inval-many-either-side-full", 4 * 8, 4 * 8, 1 * 8,
- 2 * 8, MUNMAP_FLAG_USERPTR | MUNMAP_FLAG_INVALIDATE },
+ 2 * 8, MAP_FLAG_USERPTR | MAP_FLAG_INVALIDATE },
{ "userptr-inval-many-end", 4 * 8, 4, 0 * 8, 3 * 8 + 2,
- MUNMAP_FLAG_USERPTR | MUNMAP_FLAG_INVALIDATE },
+ MAP_FLAG_USERPTR | MAP_FLAG_INVALIDATE },
{ "userptr-inval-many-front", 4 * 8, 4, 1 * 8 - 2, 3 * 8 + 2,
- MUNMAP_FLAG_USERPTR | MUNMAP_FLAG_INVALIDATE },
+ MAP_FLAG_USERPTR | MAP_FLAG_INVALIDATE },
+ { NULL },
+ };
+ const struct section mmap_sections[] = {
+ { "all", 4, 2, 0, 4, 0 },
+ { "one-partial", 4, 1, 1, 2, 0 },
+ { "either-side-partial", 4, 2, 1, 2, 0 },
+ { "either-side-full", 4, 4, 1, 2, 0 },
+ { "either-side-partial-hammer", 4, 2, 1, 2,
+ MAP_FLAG_HAMMER_FIRST_PAGE },
+ { "end", 4, 2, 0, 3, 0 },
+ { "front", 4, 2, 1, 3, 0 },
+ { "many-all", 4 * 8, 2 * 8, 0 * 8, 4 * 8, 0 },
+ { "many-either-side-partial", 4 * 8, 2 * 8, 1, 4 * 8 - 2, 0 },
+ { "many-either-side-partial-hammer", 4 * 8, 2 * 8, 1, 4 * 8 - 2,
+ MAP_FLAG_HAMMER_FIRST_PAGE },
+ { "userptr-all", 4, 2, 0, 4, MAP_FLAG_USERPTR },
+ { "userptr-one-partial", 4, 1, 1, 2, MAP_FLAG_USERPTR },
+ { "userptr-either-side-partial", 4, 2, 1, 2, MAP_FLAG_USERPTR },
+ { "userptr-either-side-full", 4, 4, 1, 2, MAP_FLAG_USERPTR },
{ NULL },
};
@@ -1823,7 +2087,7 @@ igt_main
break;
}
- for (const struct section *s = sections; s->name; s++) {
+ for (const struct section *s = munmap_sections; s->name; s++) {
igt_subtest_f("munmap-style-unbind-%s", s->name) {
igt_require_f(hwe_non_copy,
"Requires non-copy engine to run\n");
@@ -1837,6 +2101,20 @@ igt_main
}
}
+ for (const struct section *s = mmap_sections; s->name; s++) {
+ igt_subtest_f("mmap-style-bind-%s", s->name) {
+ igt_require_f(hwe_non_copy,
+ "Requires non-copy engine to run\n");
+
+ test_mmap_style_bind(fd, hwe_non_copy,
+ s->bo_n_pages,
+ s->n_binds,
+ s->unbind_n_page_offfset,
+ s->unbind_n_pages,
+ s->flags);
+ }
+ }
+
igt_fixture {
xe_device_put(fd);
close(fd);
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [igt-dev] [PATCH v2 4/7] xe_vm: Add mmap / munmap sections that split large pages
2023-05-02 6:55 [igt-dev] [PATCH v2 0/7] IGT updates for upstreaming prep Matthew Brost
` (2 preceding siblings ...)
2023-05-02 6:55 ` [igt-dev] [PATCH v2 3/7] xe_vm: MMAP style VM binds section Matthew Brost
@ 2023-05-02 6:55 ` Matthew Brost
2023-05-02 6:55 ` [igt-dev] [PATCH v2 5/7] xe: Update to new VM bind uAPI Matthew Brost
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Matthew Brost @ 2023-05-02 6:55 UTC (permalink / raw)
To: igt-dev
Splitting large pages involves using dma-resv slots for ordering, make
sure this works.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
tests/xe/xe_vm.c | 81 +++++++++++++++++++++++++++++++++++-------------
1 file changed, 60 insertions(+), 21 deletions(-)
diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
index 038a80600..694f829b3 100644
--- a/tests/xe/xe_vm.c
+++ b/tests/xe/xe_vm.c
@@ -1236,7 +1236,8 @@ static void *hammer_thread(void *tdata)
#define MAP_FLAG_USERPTR (0x1 << 0)
#define MAP_FLAG_INVALIDATE (0x1 << 1)
#define MAP_FLAG_HAMMER_FIRST_PAGE (0x1 << 2)
-
+#define MAP_FLAG_LARGE_PAGE (0x1 << 3)
+#define MAP_FLAG_LARGE_PAGE_NO_SPLIT (0x1 << 4)
/**
* SUBTEST: munmap-style-unbind-%s
@@ -1288,12 +1289,16 @@ static void *hammer_thread(void *tdata)
* userptr inval many either side full
* @userptr-inval-many-end: userptr inval many end
* @userptr-inval-many-front: userptr inval many front
+ * @either-side-partial-large-page-hammer:
+ * either side partial large page hammer
+ * @either-side-partial-split-page-hammer:
+ * either side partial split page hammer
*/
static void
test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
int bo_n_pages, int n_binds,
- int unbind_n_page_offfset, int unbind_n_pages,
+ int unbind_n_page_offset, int unbind_n_pages,
unsigned int flags)
{
struct drm_xe_sync sync[2] = {
@@ -1305,7 +1310,7 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
.num_syncs = 2,
.syncs = to_user_pointer(sync),
};
- uint64_t addr = 0x1a0000, base_addr = 0x1a0000;
+ uint64_t addr = 0x1a00000, base_addr = 0x1a00000;
uint32_t vm;
uint32_t engine;
size_t bo_size;
@@ -1323,6 +1328,14 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
struct thread_data t;
pthread_barrier_t barrier;
int exit = 0;
+ int n_page_per_2mb = 0x200000 / xe_get_default_alignment(fd);
+
+ if (flags & MAP_FLAG_LARGE_PAGE) {
+ bo_n_pages *= n_page_per_2mb;
+ unbind_n_pages *= n_page_per_2mb;
+ if (flags & MAP_FLAG_LARGE_PAGE_NO_SPLIT)
+ unbind_n_page_offset *= n_page_per_2mb;
+ }
vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
bo_size = page_size * bo_n_pages;
@@ -1409,7 +1422,7 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
sync[0].flags |= DRM_XE_SYNC_SIGNAL;
sync[1].flags &= ~DRM_XE_SYNC_SIGNAL;
xe_vm_unbind_async(fd, vm, 0, 0,
- addr + unbind_n_page_offfset * page_size,
+ addr + unbind_n_page_offset * page_size,
unbind_n_pages * page_size, sync, 2);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -1438,8 +1451,8 @@ try_again_after_invalidate:
data = map + i * page_size;
addr += page_size;
- if (i < unbind_n_page_offfset ||
- i + 1 > unbind_n_page_offfset + unbind_n_pages) {
+ if (i < unbind_n_page_offset ||
+ i + 1 > unbind_n_page_offset + unbind_n_pages) {
b = 0;
data->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
data->batch[b++] = sdi_addr;
@@ -1464,8 +1477,8 @@ try_again_after_invalidate:
/* Verify all pages still bound written */
for (i = 0; i < n_binds; ++i) {
- if (i < unbind_n_page_offfset ||
- i + 1 > unbind_n_page_offfset + unbind_n_pages) {
+ if (i < unbind_n_page_offset ||
+ i + 1 > unbind_n_page_offset + unbind_n_pages) {
data = map + i * page_size;
igt_assert_eq(data->data, 0xc0ffee);
}
@@ -1494,13 +1507,13 @@ try_again_after_invalidate:
sync[0].flags |= DRM_XE_SYNC_SIGNAL;
if (flags & MAP_FLAG_USERPTR)
xe_vm_bind_userptr_async(fd, vm, 0,
- addr + unbind_n_page_offfset * page_size,
- addr + unbind_n_page_offfset * page_size,
+ addr + unbind_n_page_offset * page_size,
+ addr + unbind_n_page_offset * page_size,
unbind_n_pages * page_size, sync, 1);
else
xe_vm_bind_async(fd, vm, 0, bo,
- unbind_n_page_offfset * page_size,
- addr + unbind_n_page_offfset * page_size,
+ unbind_n_page_offset * page_size,
+ addr + unbind_n_page_offset * page_size,
unbind_n_pages * page_size, sync, 1);
/* Verify we can use every page */
@@ -1577,11 +1590,15 @@ try_again_after_invalidate:
* @userptr-one-partial: userptr one partial
* @userptr-either-side-partial: userptr either side partial
* @userptr-either-side-full: userptr either side full
+ * @either-side-partial-large-page-hammer:
+ * either side partial large page hammer
+ * @either-side-partial-split-page-hammer:
+ * either side partial split page hammer
*/
static void
test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
- int bo_n_pages, int n_binds, int unbind_n_page_offfset,
+ int bo_n_pages, int n_binds, int unbind_n_page_offset,
int unbind_n_pages, unsigned int flags)
{
struct drm_xe_sync sync[2] = {
@@ -1593,7 +1610,7 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
.num_syncs = 2,
.syncs = to_user_pointer(sync),
};
- uint64_t addr = 0x1a0000, base_addr = 0x1a0000;
+ uint64_t addr = 0x1a00000, base_addr = 0x1a00000;
uint32_t vm;
uint32_t engine;
size_t bo_size;
@@ -1610,6 +1627,14 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
struct thread_data t;
pthread_barrier_t barrier;
int exit = 0;
+ int n_page_per_2mb = 0x200000 / xe_get_default_alignment(fd);
+
+ if (flags & MAP_FLAG_LARGE_PAGE) {
+ bo_n_pages *= n_page_per_2mb;
+ unbind_n_pages *= n_page_per_2mb;
+ if (flags & MAP_FLAG_LARGE_PAGE_NO_SPLIT)
+ unbind_n_page_offset *= n_page_per_2mb;
+ }
vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
bo_size = page_size * bo_n_pages;
@@ -1704,13 +1729,13 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
sync[1].flags &= ~DRM_XE_SYNC_SIGNAL;
if (flags & MAP_FLAG_USERPTR)
xe_vm_bind_userptr_async(fd, vm, 0, addr + bo_size +
- unbind_n_page_offfset * page_size,
- addr + unbind_n_page_offfset * page_size,
+ unbind_n_page_offset * page_size,
+ addr + unbind_n_page_offset * page_size,
unbind_n_pages * page_size, sync, 2);
else
xe_vm_bind_async(fd, vm, 0, bo1,
- unbind_n_page_offfset * page_size,
- addr + unbind_n_page_offfset * page_size,
+ unbind_n_page_offset * page_size,
+ addr + unbind_n_page_offset * page_size,
unbind_n_pages * page_size, sync, 2);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
igt_assert(syncobj_wait(fd, &sync[1].handle, 1, INT64_MAX, 0, NULL));
@@ -1809,7 +1834,7 @@ igt_main
const char *name;
int bo_n_pages;
int n_binds;
- int unbind_n_page_offfset;
+ int unbind_n_page_offset;
int unbind_n_pages;
unsigned int flags;
} munmap_sections[] = {
@@ -1818,6 +1843,13 @@ igt_main
{ "either-side-partial", 4, 2, 1, 2, 0 },
{ "either-side-partial-hammer", 4, 2, 1, 2,
MAP_FLAG_HAMMER_FIRST_PAGE },
+ { "either-side-partial-split-page-hammer", 4, 2, 1, 2,
+ MAP_FLAG_HAMMER_FIRST_PAGE |
+ MAP_FLAG_LARGE_PAGE },
+ { "either-side-partial-large-page-hammer", 4, 2, 1, 2,
+ MAP_FLAG_HAMMER_FIRST_PAGE |
+ MAP_FLAG_LARGE_PAGE |
+ MAP_FLAG_LARGE_PAGE_NO_SPLIT },
{ "either-side-full", 4, 4, 1, 2, 0 },
{ "end", 4, 2, 0, 3, 0 },
{ "front", 4, 2, 1, 3, 0 },
@@ -1870,6 +1902,13 @@ igt_main
{ "either-side-full", 4, 4, 1, 2, 0 },
{ "either-side-partial-hammer", 4, 2, 1, 2,
MAP_FLAG_HAMMER_FIRST_PAGE },
+ { "either-side-partial-split-page-hammer", 4, 2, 1, 2,
+ MAP_FLAG_HAMMER_FIRST_PAGE |
+ MAP_FLAG_LARGE_PAGE },
+ { "either-side-partial-large-page-hammer", 4, 2, 1, 2,
+ MAP_FLAG_HAMMER_FIRST_PAGE |
+ MAP_FLAG_LARGE_PAGE |
+ MAP_FLAG_LARGE_PAGE_NO_SPLIT },
{ "end", 4, 2, 0, 3, 0 },
{ "front", 4, 2, 1, 3, 0 },
{ "many-all", 4 * 8, 2 * 8, 0 * 8, 4 * 8, 0 },
@@ -2095,7 +2134,7 @@ igt_main
test_munmap_style_unbind(fd, hwe_non_copy,
s->bo_n_pages,
s->n_binds,
- s->unbind_n_page_offfset,
+ s->unbind_n_page_offset,
s->unbind_n_pages,
s->flags);
}
@@ -2109,7 +2148,7 @@ igt_main
test_mmap_style_bind(fd, hwe_non_copy,
s->bo_n_pages,
s->n_binds,
- s->unbind_n_page_offfset,
+ s->unbind_n_page_offset,
s->unbind_n_pages,
s->flags);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [igt-dev] [PATCH v2 5/7] xe: Update to new VM bind uAPI
2023-05-02 6:55 [igt-dev] [PATCH v2 0/7] IGT updates for upstreaming prep Matthew Brost
` (3 preceding siblings ...)
2023-05-02 6:55 ` [igt-dev] [PATCH v2 4/7] xe_vm: Add mmap / munmap sections that split large pages Matthew Brost
@ 2023-05-02 6:55 ` Matthew Brost
2023-05-02 6:55 ` [igt-dev] [PATCH v2 6/7] xe_exec_compute_mode: All dma-fences as in-syncs to compute execs Matthew Brost
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Matthew Brost @ 2023-05-02 6:55 UTC (permalink / raw)
To: igt-dev
Sync vs. async changes and new error handling.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
include/drm-uapi/xe_drm.h | 79 ++------------
lib/intel_batchbuffer.c | 2 +-
lib/xe/xe_compute.c | 2 +-
lib/xe/xe_ioctl.c | 15 +--
lib/xe/xe_ioctl.h | 2 +-
lib/xe/xe_query.c | 2 +-
tests/xe/xe_create.c | 2 +-
tests/xe/xe_evict.c | 23 +++--
tests/xe/xe_exec_balancer.c | 6 +-
tests/xe/xe_exec_basic.c | 5 +-
tests/xe/xe_exec_compute_mode.c | 6 +-
tests/xe/xe_exec_fault_mode.c | 6 +-
tests/xe/xe_exec_reset.c | 8 +-
tests/xe/xe_exec_threads.c | 122 +++++++---------------
tests/xe/xe_guc_pc.c | 2 +-
tests/xe/xe_huc_copy.c | 2 +-
tests/xe/xe_intel_bb.c | 2 +-
tests/xe/xe_pm.c | 2 +-
tests/xe/xe_vm.c | 178 +++++++-------------------------
tests/xe/xe_waitfence.c | 18 +---
20 files changed, 129 insertions(+), 355 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 27c51946f..cb4debe4e 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -145,10 +145,11 @@ struct drm_xe_engine_class_instance {
#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
#define DRM_XE_ENGINE_CLASS_COMPUTE 4
/*
- * Kernel only class (not actual hardware engine class). Used for
+ * Kernel only classes (not actual hardware engine class). Used for
* creating ordered queues of VM bind operations.
*/
-#define DRM_XE_ENGINE_CLASS_VM_BIND 5
+#define DRM_XE_ENGINE_CLASS_VM_BIND_ASYNC 5
+#define DRM_XE_ENGINE_CLASS_VM_BIND_SYNC 6
__u16 engine_instance;
__u16 gt_id;
@@ -312,39 +313,8 @@ struct drm_xe_gem_mmap_offset {
__u64 reserved[2];
};
-/**
- * struct drm_xe_vm_bind_op_error_capture - format of VM bind op error capture
- */
-struct drm_xe_vm_bind_op_error_capture {
- /** @error: errno that occured */
- __s32 error;
- /** @op: operation that encounter an error */
- __u32 op;
- /** @addr: address of bind op */
- __u64 addr;
- /** @size: size of bind */
- __u64 size;
-};
-
-/** struct drm_xe_ext_vm_set_property - VM set property extension */
-struct drm_xe_ext_vm_set_property {
- /** @base: base user extension */
- struct xe_user_extension base;
-
- /** @property: property to set */
-#define XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS 0
- __u32 property;
-
- /** @value: property value */
- __u64 value;
-
- /** @reserved: Reserved */
- __u64 reserved[2];
-};
-
struct drm_xe_vm_create {
/** @extensions: Pointer to the first extension struct, if any */
-#define XE_VM_EXTENSION_SET_PROPERTY 0
__u64 extensions;
/** @flags: Flags */
@@ -352,7 +322,7 @@ struct drm_xe_vm_create {
#define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0)
#define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1)
-#define DRM_XE_VM_CREATE_ASYNC_BIND_OPS (0x1 << 2)
+#define DRM_XE_VM_CREATE_ASYNC_DEFAULT (0x1 << 2)
#define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3)
/** @vm_id: Returned VM ID */
@@ -417,30 +387,6 @@ struct drm_xe_vm_bind_op {
#define XE_VM_BIND_OP_PREFETCH 0x5
#define XE_VM_BIND_FLAG_READONLY (0x1 << 16)
- /*
- * A bind ops completions are always async, hence the support for out
- * sync. This flag indicates the allocation of the memory for new page
- * tables and the job to program the pages tables is asynchronous
- * relative to the IOCTL. That part of a bind operation can fail under
- * memory pressure, the job in practice can't fail unless the system is
- * totally shot.
- *
- * If this flag is clear and the IOCTL doesn't return an error, in
- * practice the bind op is good and will complete.
- *
- * If this flag is set and doesn't return return an error, the bind op
- * can still fail and recovery is needed. If configured, the bind op that
- * caused the error will be captured in drm_xe_vm_bind_op_error_capture.
- * Once the user sees the error (via a ufence +
- * XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS), it should free memory
- * via non-async unbinds, and then restart all queue'd async binds op via
- * XE_VM_BIND_OP_RESTART. Or alternatively the user should destroy the
- * VM.
- *
- * This flag is only allowed when DRM_XE_VM_CREATE_ASYNC_BIND_OPS is
- * configured in the VM and must be set if the VM is configured with
- * DRM_XE_VM_CREATE_ASYNC_BIND_OPS and not in an error state.
- */
#define XE_VM_BIND_FLAG_ASYNC (0x1 << 17)
/*
* Valid on a faulting VM only, do the MAP operation immediately rather
@@ -455,6 +401,7 @@ struct drm_xe_vm_bind_op {
* VK sparse bindings.
*/
#define XE_VM_BIND_FLAG_NULL (0x1 << 19)
+#define XE_VM_BIND_FLAG_RECLAIM (0x1 << 20)
/** @reserved: Reserved */
__u64 reserved[2];
@@ -702,17 +649,10 @@ struct drm_xe_mmio {
struct drm_xe_wait_user_fence {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
- union {
- /**
- * @addr: user pointer address to wait on, must qword aligned
- */
- __u64 addr;
- /**
- * @vm_id: The ID of the VM which encounter an error used with
- * DRM_XE_UFENCE_WAIT_VM_ERROR. Upper 32 bits must be clear.
- */
- __u64 vm_id;
- };
+ /**
+ * @addr: user pointer address to wait on, must qword aligned
+ */
+ __u64 addr;
/** @op: wait operation (type of comparison) */
#define DRM_XE_UFENCE_WAIT_EQ 0
#define DRM_XE_UFENCE_WAIT_NEQ 1
@@ -724,7 +664,6 @@ struct drm_xe_wait_user_fence {
/** @flags: wait flags */
#define DRM_XE_UFENCE_WAIT_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */
#define DRM_XE_UFENCE_WAIT_ABSTIME (1 << 1)
-#define DRM_XE_UFENCE_WAIT_VM_ERROR (1 << 2)
__u16 flags;
/** @value: compare value */
__u64 value;
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 545d17054..b4a6db566 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -940,7 +940,7 @@ __intel_bb_create(int fd, uint32_t ctx, const intel_ctx_cfg_t *cfg,
ibb->gtt_size = 1ull << xe_va_bits(fd);
if (!ctx)
- ctx = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ ctx = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
ibb->uses_full_ppgtt = true;
ibb->allocator_handle =
diff --git a/lib/xe/xe_compute.c b/lib/xe/xe_compute.c
index 2a3686a1b..e5a8ffcbb 100644
--- a/lib/xe/xe_compute.c
+++ b/lib/xe/xe_compute.c
@@ -406,7 +406,7 @@ static void tgl_compute_exec(int fd, const unsigned char *kernel,
/* Sets Kernel size */
bo_dict[0].size = ALIGN(size, 0x1000);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
engine = xe_engine_create_class(fd, vm, DRM_XE_ENGINE_CLASS_RENDER);
sync.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL;
sync.handle = syncobj_create(fd, 0);
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 66a8393fe..77e6d2d13 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -199,16 +199,8 @@ void xe_vm_unbind_async(int fd, uint32_t vm, uint32_t engine,
static void __xe_vm_bind_sync(int fd, uint32_t vm, uint32_t bo, uint64_t offset,
uint64_t addr, uint64_t size, uint32_t op)
{
- struct drm_xe_sync sync = {
- .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
- .handle = syncobj_create(fd, 0),
- };
-
- __xe_vm_bind_assert(fd, vm, 0, bo, offset, addr, size, op, &sync, 1, 0,
+ __xe_vm_bind_assert(fd, vm, 0, bo, offset, addr, size, op, NULL, 0, 0,
0);
-
- igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL));
- syncobj_destroy(fd, sync.handle);
}
void xe_vm_bind_sync(int fd, uint32_t vm, uint32_t bo, uint64_t offset,
@@ -260,10 +252,11 @@ uint32_t xe_bo_create(int fd, int gt, uint32_t vm, uint64_t size)
return create.handle;
}
-uint32_t xe_bind_engine_create(int fd, uint32_t vm, uint64_t ext)
+uint32_t xe_bind_engine_create(int fd, uint32_t vm, uint64_t ext, bool async)
{
struct drm_xe_engine_class_instance instance = {
- .engine_class = DRM_XE_ENGINE_CLASS_VM_BIND,
+ .engine_class = async ? DRM_XE_ENGINE_CLASS_VM_BIND_ASYNC :
+ DRM_XE_ENGINE_CLASS_VM_BIND_SYNC,
};
struct drm_xe_engine_create create = {
.extensions = ext,
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index 049cd183d..f5d39e81c 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -69,7 +69,7 @@ uint32_t xe_bo_create(int fd, int gt, uint32_t vm, uint64_t size);
uint32_t xe_engine_create(int fd, uint32_t vm,
struct drm_xe_engine_class_instance *instance,
uint64_t ext);
-uint32_t xe_bind_engine_create(int fd, uint32_t vm, uint64_t ext);
+uint32_t xe_bind_engine_create(int fd, uint32_t vm, uint64_t ext, bool async);
uint32_t xe_engine_create_class(int fd, uint32_t vm, uint16_t class);
void xe_engine_destroy(int fd, uint32_t engine);
uint64_t xe_bo_mmap_offset(int fd, uint32_t bo);
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index bd5eb1d18..b3a6c5546 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -300,7 +300,7 @@ bool xe_supports_faults(int fd)
bool supports_faults;
struct drm_xe_vm_create create = {
- .flags = DRM_XE_VM_CREATE_ASYNC_BIND_OPS |
+ .flags = DRM_XE_VM_CREATE_ASYNC_DEFAULT |
DRM_XE_VM_CREATE_FAULT_MODE,
};
diff --git a/tests/xe/xe_create.c b/tests/xe/xe_create.c
index ae841f809..07744753b 100644
--- a/tests/xe/xe_create.c
+++ b/tests/xe/xe_create.c
@@ -54,7 +54,7 @@ static void create_invalid_size(int fd)
uint32_t handle;
int ret;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
xe_for_each_mem_region(fd, memreg, region) {
memregion = xe_mem_region(fd, region);
diff --git a/tests/xe/xe_evict.c b/tests/xe/xe_evict.c
index 5687cce30..d5ddf9003 100644
--- a/tests/xe/xe_evict.c
+++ b/tests/xe/xe_evict.c
@@ -64,15 +64,17 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
fd = drm_open_driver(DRIVER_XE);
xe_device_get(fd);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
if (flags & BIND_ENGINE)
- bind_engines[0] = xe_bind_engine_create(fd, vm, 0);
+ bind_engines[0] = xe_bind_engine_create(fd, vm, 0, true);
if (flags & MULTI_VM) {
- vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
- vm3 = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm3 = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
if (flags & BIND_ENGINE) {
- bind_engines[1] = xe_bind_engine_create(fd, vm2, 0);
- bind_engines[2] = xe_bind_engine_create(fd, vm3, 0);
+ bind_engines[1] = xe_bind_engine_create(fd, vm2, 0,
+ true);
+ bind_engines[2] = xe_bind_engine_create(fd, vm3, 0,
+ true);
}
}
@@ -241,15 +243,16 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
fd = drm_open_driver(DRIVER_XE);
xe_device_get(fd);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS |
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
if (flags & BIND_ENGINE)
- bind_engines[0] = xe_bind_engine_create(fd, vm, 0);
+ bind_engines[0] = xe_bind_engine_create(fd, vm, 0, true);
if (flags & MULTI_VM) {
- vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS |
+ vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
if (flags & BIND_ENGINE)
- bind_engines[1] = xe_bind_engine_create(fd, vm2, 0);
+ bind_engines[1] = xe_bind_engine_create(fd, vm2, 0,
+ true);
}
for (i = 0; i < n_engines; i++) {
diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c
index 2018c8104..7096243d7 100644
--- a/tests/xe/xe_exec_balancer.c
+++ b/tests/xe/xe_exec_balancer.c
@@ -66,7 +66,7 @@ static void test_all_active(int fd, int gt, int class)
if (num_placements < 2)
return;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * num_placements;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
@@ -212,7 +212,7 @@ test_exec(int fd, int gt, int class, int n_engines, int n_execs,
if (num_placements < 2)
return;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
@@ -435,7 +435,7 @@ test_cm(int fd, int gt, int class, int n_engines, int n_execs,
if (num_placements < 2)
return;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS |
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
diff --git a/tests/xe/xe_exec_basic.c b/tests/xe/xe_exec_basic.c
index f7ad6aeeb..98b7252fa 100644
--- a/tests/xe/xe_exec_basic.c
+++ b/tests/xe/xe_exec_basic.c
@@ -113,7 +113,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(n_vm <= MAX_N_ENGINES);
for (i = 0; i < n_vm; ++i)
- vm[i] = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm[i] = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -156,7 +156,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
engines[i] = xe_engine_create(fd, __vm, eci, 0);
if (flags & BIND_ENGINE)
- bind_engines[i] = xe_bind_engine_create(fd, __vm, 0);
+ bind_engines[i] = xe_bind_engine_create(fd, __vm, 0,
+ true);
else
bind_engines[i] = 0;
syncobjs[i] = syncobj_create(fd, 0);
diff --git a/tests/xe/xe_exec_compute_mode.c b/tests/xe/xe_exec_compute_mode.c
index 685193990..750815764 100644
--- a/tests/xe/xe_exec_compute_mode.c
+++ b/tests/xe/xe_exec_compute_mode.c
@@ -116,7 +116,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(n_engines <= MAX_N_ENGINES);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS |
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
@@ -134,7 +134,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
to_user_pointer(&ext));
if (flags & BIND_ENGINE)
bind_engines[i] =
- xe_bind_engine_create(fd, vm, 0);
+ xe_bind_engine_create(fd, vm, 0, true);
else
bind_engines[i] = 0;
};
@@ -170,7 +170,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
to_user_pointer(&ext));
if (flags & BIND_ENGINE)
bind_engines[i] =
- xe_bind_engine_create(fd, vm, 0);
+ xe_bind_engine_create(fd, vm, 0, true);
else
bind_engines[i] = 0;
};
diff --git a/tests/xe/xe_exec_fault_mode.c b/tests/xe/xe_exec_fault_mode.c
index a3ab17270..9950ab542 100644
--- a/tests/xe/xe_exec_fault_mode.c
+++ b/tests/xe/xe_exec_fault_mode.c
@@ -136,7 +136,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(n_engines <= MAX_N_ENGINES);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS |
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
DRM_XE_VM_CREATE_FAULT_MODE, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
@@ -168,7 +168,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
engines[i] = xe_engine_create(fd, vm, eci, 0);
if (flags & BIND_ENGINE)
bind_engines[i] =
- xe_bind_engine_create(fd, vm, 0);
+ xe_bind_engine_create(fd, vm, 0, true);
else
bind_engines[i] = 0;
};
@@ -382,7 +382,7 @@ test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
uint32_t *ptr;
int i, b, wait_idx = 0;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS |
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
DRM_XE_VM_CREATE_FAULT_MODE, 0);
bo_size = sizeof(*data) * n_atomic;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c
index 0d72a3f20..6007bcf6b 100644
--- a/tests/xe/xe_exec_reset.c
+++ b/tests/xe/xe_exec_reset.c
@@ -46,7 +46,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
uint32_t bo = 0;
struct xe_spin *spin;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = sizeof(*spin);
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -192,7 +192,7 @@ test_balancer(int fd, int gt, int class, int n_engines, int n_execs,
if (num_placements < 2)
return;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -393,7 +393,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
xe_device_get(fd);
}
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -571,7 +571,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
xe_device_get(fd);
}
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS |
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c
index 3f2c2de9e..25e9d8990 100644
--- a/tests/xe/xe_exec_threads.c
+++ b/tests/xe/xe_exec_threads.c
@@ -78,7 +78,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
}
if (!vm) {
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
owns_vm = true;
}
@@ -287,7 +287,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
}
if (!vm) {
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS |
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
XE_ENGINE_SET_PROPERTY_COMPUTE_MODE, 0);
owns_vm = true;
}
@@ -475,6 +475,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
};
uint32_t engines[MAX_N_ENGINES];
uint32_t bind_engines[MAX_N_ENGINES];
+ uint32_t restart_engine;
uint32_t syncobjs[MAX_N_ENGINES];
size_t bo_size;
uint32_t bo = 0;
@@ -496,7 +497,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
}
if (!vm) {
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
owns_vm = true;
}
@@ -537,13 +538,15 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
else
engines[i] = xe_engine_create(fd, vm, eci, 0);
if (flags & BIND_ENGINE)
- bind_engines[i] = xe_bind_engine_create(fd, vm, 0);
+ bind_engines[i] = xe_bind_engine_create(fd, vm, 0,
+ true);
else
bind_engines[i] = 0;
syncobjs[i] = syncobj_create(fd, 0);
sync_all[i].flags = DRM_XE_SYNC_SYNCOBJ;
sync_all[i].handle = syncobjs[i];
- };
+ }
+ restart_engine = xe_bind_engine_create(fd, vm, 0, false);
pthread_barrier_wait(&barrier);
@@ -603,17 +606,23 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
if (flags & REBIND && i &&
(!(i & 0x1f) || rebind_error_inject == i)) {
#define INJECT_ERROR (0x1 << 31)
- if (rebind_error_inject == i)
- __xe_vm_bind_assert(fd, vm, bind_engines[e],
- 0, 0, addr, bo_size,
- XE_VM_BIND_OP_UNMAP |
- XE_VM_BIND_FLAG_ASYNC |
- INJECT_ERROR, sync_all,
- n_engines, 0, 0);
- else
+ if (rebind_error_inject == i) {
+ __xe_vm_bind(fd, vm, bind_engines[e],
+ 0, 0, addr, bo_size,
+ XE_VM_BIND_OP_UNMAP |
+ XE_VM_BIND_FLAG_ASYNC |
+ INJECT_ERROR, sync_all,
+ n_engines, 0, 0);
+ __xe_vm_bind_assert(fd, vm, restart_engine,
+ 0, 0, 0, 0,
+ XE_VM_BIND_OP_RESTART |
+ XE_VM_BIND_FLAG_RECLAIM, NULL,
+ 0, 0, 0);
+ } else {
xe_vm_unbind_async(fd, vm, bind_engines[e],
0, addr, bo_size,
sync_all, n_engines);
+ }
sync[0].flags |= DRM_XE_SYNC_SIGNAL;
addr += bo_size;
@@ -687,6 +696,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
if (bind_engines[i])
xe_engine_destroy(fd, bind_engines[i]);
}
+ xe_engine_destroy(fd, restart_engine);
if (bo) {
munmap(data, bo_size);
@@ -746,47 +756,6 @@ static void *thread(void *data)
return NULL;
}
-struct vm_thread_data {
- pthread_t thread;
- struct drm_xe_vm_bind_op_error_capture *capture;
- int fd;
- int vm;
-};
-
-static void *vm_async_ops_err_thread(void *data)
-{
- struct vm_thread_data *args = data;
- int fd = args->fd;
- int ret;
-
- struct drm_xe_wait_user_fence wait = {
- .vm_id = args->vm,
- .op = DRM_XE_UFENCE_WAIT_NEQ,
- .flags = DRM_XE_UFENCE_WAIT_VM_ERROR,
- .mask = DRM_XE_UFENCE_WAIT_U32,
-#define BASICALLY_FOREVER 0xffffffffffff
- .timeout = BASICALLY_FOREVER,
- };
-
- ret = igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait);
-
- while (!ret) {
- struct drm_xe_vm_bind bind = {
- .vm_id = args->vm,
- .num_binds = 1,
- .bind.op = XE_VM_BIND_OP_RESTART,
- };
-
- /* Restart and wait for next error */
- igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_BIND,
- &bind), 0);
- args->capture->error = 0;
- ret = igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait);
- }
-
- return NULL;
-}
-
/**
* SUBTEST: threads-%s
* Description: Run threads %arg[1] test with multi threads
@@ -839,6 +808,10 @@ static void *vm_async_ops_err_thread(void *data)
* shared vm rebind err
* @shared-vm-userptr-rebind-err:
* shared vm userptr rebind err
+ * @rebind-err:
+ * rebind err
+ * @userptr-rebind-err:
+ * userptr rebind err
* @shared-vm-userptr-invalidate:
* shared vm userptr invalidate
* @shared-vm-userptr-invalidate-race:
@@ -855,7 +828,7 @@ static void *vm_async_ops_err_thread(void *data)
* fd userptr invalidate race
* @hang-basic:
* hang basic
- * @hang-userptr:
+ * @hang-userptr:
* hang userptr
* @hang-rebind:
* hang rebind
@@ -873,6 +846,10 @@ static void *vm_async_ops_err_thread(void *data)
* hang shared vm rebind
* @hang-shared-vm-userptr-rebind:
* hang shared vm userptr rebind
+ * @hang-rebind-err:
+ * hang rebind err
+ * @hang-userptr-rebind-err:
+ * hang userptr rebind err
* @hang-shared-vm-rebind-err:
* hang shared vm rebind err
* @hang-shared-vm-userptr-rebind-err:
@@ -1032,8 +1009,6 @@ static void threads(int fd, int flags)
int n_hw_engines = 0, class;
uint64_t i = 0;
uint32_t vm_legacy_mode = 0, vm_compute_mode = 0;
- struct drm_xe_vm_bind_op_error_capture capture = {};
- struct vm_thread_data vm_err_thread = {};
bool go = false;
int n_threads = 0;
int gt;
@@ -1065,28 +1040,13 @@ static void threads(int fd, int flags)
pthread_cond_init(&cond, 0);
if (flags & SHARED_VM) {
- struct drm_xe_ext_vm_set_property ext = {
- .base.next_extension = 0,
- .base.name = XE_VM_EXTENSION_SET_PROPERTY,
- .property =
- XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS,
- .value = to_user_pointer(&capture),
- };
-
vm_legacy_mode = xe_vm_create(fd,
- DRM_XE_VM_CREATE_ASYNC_BIND_OPS,
- to_user_pointer(&ext));
+ DRM_XE_VM_CREATE_ASYNC_DEFAULT,
+ 0);
vm_compute_mode = xe_vm_create(fd,
- DRM_XE_VM_CREATE_ASYNC_BIND_OPS |
+ DRM_XE_VM_CREATE_ASYNC_DEFAULT |
XE_ENGINE_SET_PROPERTY_COMPUTE_MODE,
0);
-
- vm_err_thread.capture = &capture;
- vm_err_thread.fd = fd;
- vm_err_thread.vm = vm_legacy_mode;
- pthread_create(&vm_err_thread.thread, 0,
- vm_async_ops_err_thread, &vm_err_thread);
-
}
xe_for_each_hw_engine(fd, hwe) {
@@ -1213,8 +1173,6 @@ static void threads(int fd, int flags)
if (vm_compute_mode)
xe_vm_destroy(fd, vm_compute_mode);
free(threads_data);
- if (flags & SHARED_VM)
- pthread_join(vm_err_thread.thread, NULL);
pthread_barrier_destroy(&barrier);
}
@@ -1237,9 +1195,8 @@ igt_main
{ "shared-vm-rebind-bindengine", SHARED_VM | REBIND |
BIND_ENGINE },
{ "shared-vm-userptr-rebind", SHARED_VM | USERPTR | REBIND },
- { "shared-vm-rebind-err", SHARED_VM | REBIND | REBIND_ERROR },
- { "shared-vm-userptr-rebind-err", SHARED_VM | USERPTR |
- REBIND | REBIND_ERROR},
+ { "rebind-err", REBIND | REBIND_ERROR },
+ { "userptr-rebind-err", USERPTR | REBIND | REBIND_ERROR},
{ "shared-vm-userptr-invalidate", SHARED_VM | USERPTR |
INVALIDATE },
{ "shared-vm-userptr-invalidate-race", SHARED_VM | USERPTR |
@@ -1263,10 +1220,9 @@ igt_main
{ "hang-shared-vm-rebind", HANG | SHARED_VM | REBIND },
{ "hang-shared-vm-userptr-rebind", HANG | SHARED_VM | USERPTR |
REBIND },
- { "hang-shared-vm-rebind-err", HANG | SHARED_VM | REBIND |
+ { "hang-rebind-err", HANG | REBIND | REBIND_ERROR },
+ { "hang-userptr-rebind-err", HANG | USERPTR | REBIND |
REBIND_ERROR },
- { "hang-shared-vm-userptr-rebind-err", HANG | SHARED_VM |
- USERPTR | REBIND | REBIND_ERROR },
{ "hang-shared-vm-userptr-invalidate", HANG | SHARED_VM |
USERPTR | INVALIDATE },
{ "hang-shared-vm-userptr-invalidate-race", HANG | SHARED_VM |
diff --git a/tests/xe/xe_guc_pc.c b/tests/xe/xe_guc_pc.c
index 5c71ae147..4025bb312 100644
--- a/tests/xe/xe_guc_pc.c
+++ b/tests/xe/xe_guc_pc.c
@@ -59,7 +59,7 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(n_engines <= MAX_N_ENGINES);
igt_assert(n_execs > 0);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
diff --git a/tests/xe/xe_huc_copy.c b/tests/xe/xe_huc_copy.c
index fdac907d6..cff212180 100644
--- a/tests/xe/xe_huc_copy.c
+++ b/tests/xe/xe_huc_copy.c
@@ -118,7 +118,7 @@ test_huc_copy(int fd)
{ .addr = ADDR_BATCH, .size = SIZE_BATCH }, // batch
};
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
engine = xe_engine_create_class(fd, vm, DRM_XE_ENGINE_CLASS_VIDEO_DECODE);
sync.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL;
sync.handle = syncobj_create(fd, 0);
diff --git a/tests/xe/xe_intel_bb.c b/tests/xe/xe_intel_bb.c
index 35d61608e..5e24360c2 100644
--- a/tests/xe/xe_intel_bb.c
+++ b/tests/xe/xe_intel_bb.c
@@ -195,7 +195,7 @@ static void simple_bb(struct buf_ops *bops, bool new_context)
intel_bb_reset(ibb, true);
if (new_context) {
- ctx = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ ctx = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
intel_bb_destroy(ibb);
ibb = intel_bb_create_with_context(xe, ctx, NULL, PAGE_SIZE);
intel_bb_out(ibb, MI_BATCH_BUFFER_END);
diff --git a/tests/xe/xe_pm.c b/tests/xe/xe_pm.c
index 44154143c..97e73e82a 100644
--- a/tests/xe/xe_pm.c
+++ b/tests/xe/xe_pm.c
@@ -238,7 +238,7 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
if (check_rpm)
igt_assert(in_d3(device, d_state));
- vm = xe_vm_create(device.fd_xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(device.fd_xe, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
if (check_rpm)
igt_assert(out_of_d3(device, d_state));
diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
index 694f829b3..f6d71d0e0 100644
--- a/tests/xe/xe_vm.c
+++ b/tests/xe/xe_vm.c
@@ -275,7 +275,7 @@ static void unbind_all(int fd, int n_vmas)
{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
};
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo = xe_bo_create(fd, 0, vm, bo_size);
for (i = 0; i < n_vmas; ++i)
@@ -322,16 +322,6 @@ static void userptr_invalid(int fd)
xe_vm_destroy(fd, vm);
}
-struct vm_thread_data {
- pthread_t thread;
- struct drm_xe_vm_bind_op_error_capture *capture;
- int fd;
- int vm;
- uint32_t bo;
- size_t bo_size;
- bool destroy;
-};
-
/**
* SUBTEST: vm-async-ops-err
* Description: Test VM async ops error
@@ -344,57 +334,6 @@ struct vm_thread_data {
* TODO: change ``'Run type' == FULL`` to a better category
*/
-static void *vm_async_ops_err_thread(void *data)
-{
- struct vm_thread_data *args = data;
- int fd = args->fd;
- uint64_t addr = 0x201a0000;
- int num_binds = 0;
- int ret;
-
- struct drm_xe_wait_user_fence wait = {
- .vm_id = args->vm,
- .op = DRM_XE_UFENCE_WAIT_NEQ,
- .flags = DRM_XE_UFENCE_WAIT_VM_ERROR,
- .mask = DRM_XE_UFENCE_WAIT_U32,
- .timeout = 1000,
- };
-
- igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE,
- &wait), 0);
- if (args->destroy) {
- usleep(5000); /* Wait other binds to queue up */
- xe_vm_destroy(fd, args->vm);
- return NULL;
- }
-
- while (!ret) {
- struct drm_xe_vm_bind bind = {
- .vm_id = args->vm,
- .num_binds = 1,
- .bind.op = XE_VM_BIND_OP_RESTART,
- };
-
- /* VM sync ops should work */
- if (!(num_binds++ % 2)) {
- xe_vm_bind_sync(fd, args->vm, args->bo, 0, addr,
- args->bo_size);
- } else {
- xe_vm_unbind_sync(fd, args->vm, 0, addr,
- args->bo_size);
- addr += args->bo_size * 2;
- }
-
- /* Restart and wait for next error */
- igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_BIND,
- &bind), 0);
- args->capture->error = 0;
- ret = igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait);
- }
-
- return NULL;
-}
-
static void vm_async_ops_err(int fd, bool destroy)
{
uint32_t vm;
@@ -403,99 +342,56 @@ static void vm_async_ops_err(int fd, bool destroy)
.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
};
#define N_BINDS 32
- struct drm_xe_vm_bind_op_error_capture capture = {};
- struct drm_xe_ext_vm_set_property ext = {
- .base.next_extension = 0,
- .base.name = XE_VM_EXTENSION_SET_PROPERTY,
- .property = XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS,
- .value = to_user_pointer(&capture),
- };
- struct vm_thread_data thread = {};
uint32_t syncobjs[N_BINDS];
+ uint32_t restart_engine;
size_t bo_size = 0x1000 * 32;
uint32_t bo;
- int i, j;
+ int i, j = 0;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS,
- to_user_pointer(&ext));
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo = xe_bo_create(fd, 0, vm, bo_size);
-
- thread.capture = &capture;
- thread.fd = fd;
- thread.vm = vm;
- thread.bo = bo;
- thread.bo_size = bo_size;
- thread.destroy = destroy;
- pthread_create(&thread.thread, 0, vm_async_ops_err_thread, &thread);
+ restart_engine = xe_bind_engine_create(fd, vm, 0, false);
for (i = 0; i < N_BINDS; i++)
syncobjs[i] = syncobj_create(fd, 0);
- for (j = 0, i = 0; i < N_BINDS / 4; i++, j++) {
- sync.handle = syncobjs[j];
+ for (i = 0; i < N_BINDS; i++) {
+ sync.handle = syncobjs[i];
#define INJECT_ERROR (0x1 << 31)
- if (i == N_BINDS / 8) /* Inject error on this bind */
- __xe_vm_bind_assert(fd, vm, 0, bo, 0,
- addr + i * bo_size * 2,
- bo_size, XE_VM_BIND_OP_MAP |
- XE_VM_BIND_FLAG_ASYNC |
- INJECT_ERROR, &sync, 1, 0, 0);
- else
- xe_vm_bind_async(fd, vm, 0, bo, 0,
- addr + i * bo_size * 2,
- bo_size, &sync, 1);
- }
+ if ((i == N_BINDS / 8 && destroy) ||
+ (!((i + 1) % (N_BINDS / 8)) && !destroy)) { /* Inject error on this bind */
+ __xe_vm_bind(fd, vm, 0, bo, 0,
+ addr + i * bo_size * 2,
+ bo_size, XE_VM_BIND_OP_MAP |
+ XE_VM_BIND_FLAG_ASYNC | INJECT_ERROR,
+ &sync, 1, 0, 0);
+
+ if (destroy)
+ break;
- for (i = 0; i < N_BINDS / 4; i++, j++) {
- sync.handle = syncobjs[j];
- if (i == N_BINDS / 8)
- __xe_vm_bind_assert(fd, vm, 0, 0, 0,
- addr + i * bo_size * 2,
+ __xe_vm_bind_assert(fd, vm, restart_engine, 0, 0,
+ addr + j++ * bo_size * 2,
bo_size, XE_VM_BIND_OP_UNMAP |
- XE_VM_BIND_FLAG_ASYNC |
- INJECT_ERROR, &sync, 1, 0, 0);
- else
- xe_vm_unbind_async(fd, vm, 0, 0,
- addr + i * bo_size * 2,
- bo_size, &sync, 1);
- }
-
- for (i = 0; i < N_BINDS / 4; i++, j++) {
- sync.handle = syncobjs[j];
- if (i == N_BINDS / 8)
- __xe_vm_bind_assert(fd, vm, 0, bo, 0,
- addr + i * bo_size * 2,
- bo_size, XE_VM_BIND_OP_MAP |
- XE_VM_BIND_FLAG_ASYNC |
- INJECT_ERROR, &sync, 1, 0, 0);
- else
+ XE_VM_BIND_FLAG_RECLAIM,
+ 0, 0, 0, 0);
+ __xe_vm_bind_assert(fd, vm, restart_engine,
+ 0, 0, 0, 0,
+ XE_VM_BIND_OP_RESTART |
+ XE_VM_BIND_FLAG_RECLAIM, NULL,
+ 0, 0, 0);
+ } else {
xe_vm_bind_async(fd, vm, 0, bo, 0,
addr + i * bo_size * 2,
bo_size, &sync, 1);
+ }
}
- for (i = 0; i < N_BINDS / 4; i++, j++) {
- sync.handle = syncobjs[j];
- if (i == N_BINDS / 8)
- __xe_vm_bind_assert(fd, vm, 0, 0, 0,
- addr + i * bo_size * 2,
- bo_size, XE_VM_BIND_OP_UNMAP |
- XE_VM_BIND_FLAG_ASYNC |
- INJECT_ERROR, &sync, 1, 0, 0);
- else
- xe_vm_unbind_async(fd, vm, 0, 0,
- addr + i * bo_size * 2,
- bo_size, &sync, 1);
- }
-
- for (i = 0; i < N_BINDS; i++)
+ for (i = 0; i < (destroy ? (N_BINDS / 8 - 1) : N_BINDS); i++)
igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0,
NULL));
if (!destroy)
xe_vm_destroy(fd, vm);
-
- pthread_join(thread.thread, NULL);
}
/**
@@ -547,7 +443,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
data = malloc(sizeof(*data) * n_bo);
igt_assert(data);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = sizeof(struct shared_pte_page_data);
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -717,7 +613,7 @@ test_bind_engines_independent(int fd, struct drm_xe_engine_class_instance *eci)
} *data;
int i, b;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * N_ENGINES;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -726,7 +622,7 @@ test_bind_engines_independent(int fd, struct drm_xe_engine_class_instance *eci)
for (i = 0; i < N_ENGINES; i++) {
engines[i] = xe_engine_create(fd, vm, eci, 0);
- bind_engines[i] = xe_bind_engine_create(fd, vm, 0);
+ bind_engines[i] = xe_bind_engine_create(fd, vm, 0, true);
syncobjs[i] = syncobj_create(fd, 0);
}
syncobjs[N_ENGINES] = syncobj_create(fd, 0);
@@ -873,7 +769,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
igt_assert(n_execs <= BIND_ARRAY_MAX_N_EXEC);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -882,7 +778,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
data = xe_bo_map(fd, bo, bo_size);
if (flags & BIND_ARRAY_BIND_ENGINE_FLAG)
- bind_engine = xe_bind_engine_create(fd, vm, 0);
+ bind_engine = xe_bind_engine_create(fd, vm, 0, true);
engine = xe_engine_create(fd, vm, eci, 0);
for (i = 0; i < n_execs; ++i) {
@@ -1050,7 +946,7 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
}
igt_assert(n_engines <= MAX_N_ENGINES);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
if (flags & LARGE_BIND_FLAG_USERPTR) {
map = aligned_alloc(xe_get_default_alignment(fd), bo_size);
@@ -1337,7 +1233,7 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
unbind_n_page_offset *= n_page_per_2mb;
}
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = page_size * bo_n_pages;
if (flags & MAP_FLAG_USERPTR) {
@@ -1636,7 +1532,7 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
unbind_n_page_offset *= n_page_per_2mb;
}
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_size = page_size * bo_n_pages;
if (flags & MAP_FLAG_USERPTR) {
diff --git a/tests/xe/xe_waitfence.c b/tests/xe/xe_waitfence.c
index cdfcacdb4..917957442 100644
--- a/tests/xe/xe_waitfence.c
+++ b/tests/xe/xe_waitfence.c
@@ -34,7 +34,7 @@ static void do_bind(int fd, uint32_t vm, uint32_t bo, uint64_t offset,
sync[0].addr = to_user_pointer(&wait_fence);
sync[0].timeline_value = val;
- xe_vm_bind(fd, vm, bo, offset, addr, size, sync, 1);
+ xe_vm_bind_async(fd, vm, 0, bo, offset, addr, size, sync, 1);
}
/**
@@ -52,7 +52,7 @@ test(int fd)
uint32_t bo_6;
uint32_t bo_7;
- uint32_t vm = xe_vm_create(fd, 0, 0);
+ uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
bo_1 = xe_bo_create_flags(fd, vm, 0x40000, MY_FLAG);
do_bind(fd, vm, bo_1, 0, 0x200000, 0x40000, 1);
bo_2 = xe_bo_create_flags(fd, vm, 0x40000, MY_FLAG);
@@ -68,20 +68,6 @@ test(int fd)
bo_7 = xe_bo_create_flags(fd, vm, 0x10000, MY_FLAG);
do_bind(fd, vm, bo_7, 0, 0xeffff0000, 0x10000, 7);
xe_wait_ufence(fd, &wait_fence, 7, NULL, 2000);
- xe_vm_unbind_sync(fd, vm, 0, 0x200000, 0x40000);
- xe_vm_unbind_sync(fd, vm, 0, 0xc0000000, 0x40000);
- xe_vm_unbind_sync(fd, vm, 0, 0x180000000, 0x40000);
- xe_vm_unbind_sync(fd, vm, 0, 0x140000000, 0x10000);
- xe_vm_unbind_sync(fd, vm, 0, 0x100000000, 0x100000);
- xe_vm_unbind_sync(fd, vm, 0, 0xc0040000, 0x1c0000);
- xe_vm_unbind_sync(fd, vm, 0, 0xeffff0000, 0x10000);
- gem_close(fd, bo_7);
- gem_close(fd, bo_6);
- gem_close(fd, bo_5);
- gem_close(fd, bo_4);
- gem_close(fd, bo_3);
- gem_close(fd, bo_2);
- gem_close(fd, bo_1);
}
igt_main
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [igt-dev] [PATCH v2 6/7] xe_exec_compute_mode: All dma-fences as in-syncs to compute execs
2023-05-02 6:55 [igt-dev] [PATCH v2 0/7] IGT updates for upstreaming prep Matthew Brost
` (4 preceding siblings ...)
2023-05-02 6:55 ` [igt-dev] [PATCH v2 5/7] xe: Update to new VM bind uAPI Matthew Brost
@ 2023-05-02 6:55 ` Matthew Brost
2023-05-02 6:55 ` [igt-dev] [PATCH v2 7/7] xe_vm: Add EIO test Matthew Brost
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Matthew Brost @ 2023-05-02 6:55 UTC (permalink / raw)
To: igt-dev
We allow this behavior now, lets test it.
Signed-of-by: Matthew Brost <matthew.brost@intel.com>
---
tests/xe/xe_exec_compute_mode.c | 159 ++++++++++++++++++++++++++++----
1 file changed, 141 insertions(+), 18 deletions(-)
diff --git a/tests/xe/xe_exec_compute_mode.c b/tests/xe/xe_exec_compute_mode.c
index 750815764..750e65b5d 100644
--- a/tests/xe/xe_exec_compute_mode.c
+++ b/tests/xe/xe_exec_compute_mode.c
@@ -30,6 +30,7 @@
#define BIND_ENGINE (0x1 << 4)
#define VM_FOR_BO (0x1 << 5)
#define ENGINE_EARLY (0x1 << 6)
+#define DMA_FENCES_FOR_BINDS (0x1 << 7)
/**
* SUBTEST: twice-%s
@@ -61,6 +62,32 @@
* @bindengine-userptr-rebind: bindengine userptr rebind
* @bindengine-userptr-invalidate: bindengine userptr invalidate
* @bindengine-userptr-invalidate-race: bindengine-userptr invalidate race
+ * @basic-dma-fences:
+ * basic dma fences
+ * @preempt-fence-early-dma-fences:
+ * preempt fence early dma fences
+ * @userptr-dma-fences:
+ * userptr dma fences
+ * @rebind-dma-fences:
+ * rebind dma fences
+ * @userptr-rebind-dma-fences:
+ * userptr rebind dma fences
+ * @userptr-invalidate-dma-fences:
+ * userptr invalidate dma fences
+ * @userptr-invalidate-race-dma-fences:
+ * userptr invalidate race dma fences
+ * @bindengine-dma-fences:
+ * bindengine dma fences
+ * @bindengine-userptr-dma-fences:
+ * bindengine userptr dma fences
+ * @bindengine-rebind-dma-fences:
+ * bindengine rebind dma fences
+ * @bindengine-userptr-rebind-dma-fences:
+ * bindengine userptr rebind dma fences
+ * @bindengine-userptr-invalidate-dma-fences:
+ * bindengine userptr invalidate dma fences
+ * @bindengine-userptr-invalidate-race-dma-fences:
+ * bindengine-userptr invalidate race dma fences
*/
/**
@@ -83,6 +110,28 @@
* @bindengine-rebind: bindengine rebind
* @bindengine-userptr-rebind: bindengine userptr rebind
* @bindengine-userptr-invalidate: bindengine userptr invalidate
+ * @basic-dma-fences:
+ * basic dma fences
+ * @preempt-fence-early-dma-fences:
+ * preempt fence early dma fences
+ * @userptr-dma-fences:
+ * userptr dma fences
+ * @rebind-dma-fences:
+ * rebind dma fences
+ * @userptr-rebind-dma-fences:
+ * userptr rebind dma fences
+ * @userptr-invalidate-dma-fences:
+ * userptr invalidate dma fences
+ * @bindengine-dma-fences:
+ * bindengine dma fences
+ * @bindengine-userptr-dma-fences:
+ * bindengine userptr dma fences
+ * @bindengine-rebind-dma-fences:
+ * bindengine rebind dma fences
+ * @bindengine-userptr-rebind-dma-fences:
+ * bindengine userptr rebind dma fences
+ * @bindengine-userptr-invalidate-dma-fences:
+ * bindengine userptr invalidate dma fences
*/
static void
test_exec(int fd, struct drm_xe_engine_class_instance *eci,
@@ -91,14 +140,21 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
uint32_t vm;
uint64_t addr = 0x1a0000;
#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
+ bool dma_fences = flags & DMA_FENCES_FOR_BINDS;
struct drm_xe_sync sync[1] = {
{ .flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
.timeline_value = USER_FENCE_VALUE },
};
+ struct drm_xe_sync dma_sync[2] = {
+ { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+ .timeline_value = USER_FENCE_VALUE },
+ };
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
- .num_syncs = 1,
- .syncs = to_user_pointer(sync),
+ .num_syncs = dma_fences ? 2 : 1,
+ .syncs = dma_fences ? to_user_pointer(dma_sync) :
+ to_user_pointer(sync),
};
uint32_t engines[MAX_N_ENGINES];
uint32_t bind_engines[MAX_N_ENGINES];
@@ -113,6 +169,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
} *data;
int i, j, b;
int map_fd = -1;
+ uint32_t syncobj;
igt_assert(n_engines <= MAX_N_ENGINES);
@@ -175,17 +232,29 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
bind_engines[i] = 0;
};
- sync[0].addr = to_user_pointer(&data[0].vm_sync);
+ if (dma_fences) {
+ syncobj = syncobj_create(fd, 0);
+ dma_sync[0].handle = syncobj;
+ } else {
+ sync[0].addr = to_user_pointer(&data[0].vm_sync);
+ }
+
if (bo)
xe_vm_bind_async(fd, vm, bind_engines[0], bo, 0, addr,
- bo_size, sync, 1);
+ bo_size, dma_fences ? dma_sync : sync, 1);
else
xe_vm_bind_userptr_async(fd, vm, bind_engines[0],
to_user_pointer(data), addr,
- bo_size, sync, 1);
+ bo_size, dma_fences ? dma_sync : sync,
+ 1);
#define ONE_SEC 1000
- xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
- data[0].vm_sync = 0;
+ if (!dma_fences) {
+ xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL,
+ ONE_SEC);
+ data[0].vm_sync = 0;
+ } else {
+ dma_sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ }
for (i = 0; i < n_execs; i++) {
uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
@@ -202,7 +271,12 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
data[i].batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].addr = addr + (char *)&data[i].exec_sync - (char *)data;
+ if (dma_fences)
+ dma_sync[1].addr = addr +
+ (char *)&data[i].exec_sync - (char *)data;
+ else
+ sync[0].addr = addr +
+ (char *)&data[i].exec_sync - (char *)data;
exec.engine_id = engines[e];
exec.address = batch_addr;
@@ -214,20 +288,31 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
xe_vm_unbind_async(fd, vm, bind_engines[e], 0,
addr, bo_size, NULL, 0);
- sync[0].addr = to_user_pointer(&data[0].vm_sync);
+ if (dma_fences)
+ dma_sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ else
+ sync[0].addr =
+ to_user_pointer(&data[0].vm_sync);
addr += bo_size;
if (bo)
xe_vm_bind_async(fd, vm, bind_engines[e], bo,
- 0, addr, bo_size, sync, 1);
+ 0, addr, bo_size,
+ dma_fences ? dma_sync : sync,
+ 1);
else
xe_vm_bind_userptr_async(fd, vm,
bind_engines[e],
to_user_pointer(data),
- addr, bo_size, sync,
- 1);
- xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE,
- NULL, ONE_SEC);
- data[0].vm_sync = 0;
+ addr, bo_size,
+ dma_fences ? dma_sync :
+ sync, 1);
+ if (!dma_fences) {
+ xe_wait_ufence(fd, &data[0].vm_sync,
+ USER_FENCE_VALUE, NULL, ONE_SEC);
+ data[0].vm_sync = 0;
+ } else {
+ dma_sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ }
}
if (flags & INVALIDATE && i + 1 != n_execs) {
@@ -275,10 +360,21 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
if (flags & INVALIDATE)
usleep(250000);
- sync[0].addr = to_user_pointer(&data[0].vm_sync);
+ if (dma_fences) {
+ syncobj_reset(fd, &syncobj, 1);
+ dma_sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ } else {
+ sync[0].addr = to_user_pointer(&data[0].vm_sync);
+ }
+
xe_vm_unbind_async(fd, vm, bind_engines[0], 0, addr, bo_size,
- sync, 1);
- xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+ dma_fences ? dma_sync : sync, 1);
+ if (dma_fences)
+ igt_assert(syncobj_wait(fd, &syncobj, 1, INT64_MAX, 0,
+ NULL));
+ else
+ xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL,
+ ONE_SEC);
for (i = j; i < n_execs; i++)
igt_assert_eq(data[i].data, 0xc0ffee);
@@ -289,6 +385,9 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
xe_engine_destroy(fd, bind_engines[i]);
}
+ if (dma_fences)
+ syncobj_destroy(fd, syncobj);
+
if (bo) {
munmap(data, bo_size);
gem_close(fd, bo);
@@ -323,6 +422,30 @@ igt_main
INVALIDATE },
{ "bindengine-userptr-invalidate-race", BIND_ENGINE | USERPTR |
INVALIDATE | RACE },
+ { "basic-dma-fences", DMA_FENCES_FOR_BINDS | 0 },
+ { "preempt-fence-early-dma-fences", DMA_FENCES_FOR_BINDS |
+ VM_FOR_BO | ENGINE_EARLY },
+ { "userptr-dma-fences", DMA_FENCES_FOR_BINDS | USERPTR },
+ { "rebind-dma-fences", DMA_FENCES_FOR_BINDS | REBIND },
+ { "userptr-rebind-dma-fences", DMA_FENCES_FOR_BINDS | USERPTR |
+ REBIND },
+ { "userptr-invalidate-dma-fences", DMA_FENCES_FOR_BINDS |
+ USERPTR | INVALIDATE },
+ { "userptr-invalidate-race-dma-fences", DMA_FENCES_FOR_BINDS |
+ USERPTR | INVALIDATE | RACE },
+ { "bindengine-dma-fences", DMA_FENCES_FOR_BINDS | BIND_ENGINE },
+ { "bindengine-userptr-dma-fences", DMA_FENCES_FOR_BINDS |
+ BIND_ENGINE | USERPTR },
+ { "bindengine-rebind-dma-fences", DMA_FENCES_FOR_BINDS |
+ BIND_ENGINE | REBIND },
+ { "bindengine-userptr-rebind-dma-fences", DMA_FENCES_FOR_BINDS |
+ BIND_ENGINE | USERPTR | REBIND },
+ { "bindengine-userptr-invalidate-dma-fences",
+ DMA_FENCES_FOR_BINDS | BIND_ENGINE | USERPTR |
+ INVALIDATE },
+ { "bindengine-userptr-invalidate-race-dma-fences",
+ DMA_FENCES_FOR_BINDS | BIND_ENGINE | USERPTR |
+ INVALIDATE | RACE },
{ NULL },
};
int fd;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [igt-dev] [PATCH v2 7/7] xe_vm: Add EIO test
2023-05-02 6:55 [igt-dev] [PATCH v2 0/7] IGT updates for upstreaming prep Matthew Brost
` (5 preceding siblings ...)
2023-05-02 6:55 ` [igt-dev] [PATCH v2 6/7] xe_exec_compute_mode: All dma-fences as in-syncs to compute execs Matthew Brost
@ 2023-05-02 6:55 ` Matthew Brost
2023-05-02 7:30 ` [igt-dev] ✓ Fi.CI.BAT: success for IGT updates for upstreaming prep (rev2) Patchwork
2023-05-02 8:42 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 10+ messages in thread
From: Matthew Brost @ 2023-05-02 6:55 UTC (permalink / raw)
To: igt-dev
Let's make sure bad input to VM bind doesn't crash the driver or leak
resources.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
lib/xe/xe_ioctl.c | 22 +++++++++++
lib/xe/xe_ioctl.h | 4 ++
tests/xe/xe_vm.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 121 insertions(+)
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 77e6d2d13..b9bfc2e8e 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -70,6 +70,28 @@ void xe_vm_unbind_all_async(int fd, uint32_t vm, uint32_t engine,
sync, num_syncs, 0, 0);
}
+int __xe_vm_bind_array(int fd, uint32_t vm, uint32_t engine,
+ struct drm_xe_vm_bind_op *bind_ops,
+ uint32_t num_bind, struct drm_xe_sync *sync,
+ uint32_t num_syncs)
+{
+ struct drm_xe_vm_bind bind = {
+ .vm_id = vm,
+ .num_binds = num_bind,
+ .vector_of_binds = (uintptr_t)bind_ops,
+ .num_syncs = num_syncs,
+ .syncs = (uintptr_t)sync,
+ .engine_id = engine,
+ };
+
+ igt_assert(num_bind > 1);
+
+ if (igt_ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind))
+ return -errno;
+
+ return 0;
+}
+
void xe_vm_bind_array(int fd, uint32_t vm, uint32_t engine,
struct drm_xe_vm_bind_op *bind_ops,
uint32_t num_bind, struct drm_xe_sync *sync,
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index f5d39e81c..9757aab37 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -56,6 +56,10 @@ void xe_vm_bind_sync(int fd, uint32_t vm, uint32_t bo, uint64_t offset,
uint64_t addr, uint64_t size);
void xe_vm_unbind_sync(int fd, uint32_t vm, uint64_t offset,
uint64_t addr, uint64_t size);
+int __xe_vm_bind_array(int fd, uint32_t vm, uint32_t engine,
+ struct drm_xe_vm_bind_op *bind_ops,
+ uint32_t num_bind, struct drm_xe_sync *sync,
+ uint32_t num_syncs);
void xe_vm_bind_array(int fd, uint32_t vm, uint32_t engine,
struct drm_xe_vm_bind_op *bind_ops,
uint32_t num_bind, struct drm_xe_sync *sync,
diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
index f6d71d0e0..78320fc48 100644
--- a/tests/xe/xe_vm.c
+++ b/tests/xe/xe_vm.c
@@ -294,6 +294,98 @@ static void unbind_all(int fd, int n_vmas)
#define MAP_ADDRESS 0x00007fadeadbe000
+/**
+ * SUBTEST: eio
+ * Description:
+ * Verifies bad input to vm bind is handled correctly and doesn't crash the
+ * driver
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ */
+static void eio(int fd)
+{
+ size_t size = xe_get_default_alignment(fd);
+ struct drm_xe_vm_bind_op bind_ops[2];
+ uint32_t vm;
+ uint32_t bo;
+ uint32_t async_bind_engine;
+ uint32_t sync_bind_engine;
+ int ret, i;
+
+ vm = xe_vm_create(fd, 0, 0);
+ bo = xe_bo_create(fd, 0, vm, size);
+ async_bind_engine = xe_bind_engine_create(fd, vm, 0, true);
+ sync_bind_engine = xe_bind_engine_create(fd, vm, 0, false);
+
+ /* Bad BO */
+ ret = __xe_vm_bind(fd, vm, 0, bo + 1, 0, 0x40000,
+ size, XE_VM_BIND_OP_MAP, NULL, 0, 0, 0);
+ igt_assert(ret == -ENOENT);
+
+ /* Bad BO /w an engine */
+ ret = __xe_vm_bind(fd, vm, sync_bind_engine, bo + 1, 0, 0x40000,
+ size, XE_VM_BIND_OP_MAP, NULL, 0, 0, 0);
+ igt_assert(ret == -ENOENT);
+
+ /* Invalid engine */
+ ret = __xe_vm_bind(fd, vm, sync_bind_engine + async_bind_engine, bo, 0,
+ 0x40000, size, XE_VM_BIND_OP_MAP, NULL, 0, 0, 0);
+ igt_assert(ret == -ENOENT);
+
+ /* Bad BO offset */
+ ret = __xe_vm_bind(fd, vm, 0, bo, xe_get_default_alignment(fd) * 2, 0x40000,
+ size, XE_VM_BIND_OP_MAP, NULL, 0, 0, 0);
+ igt_assert(ret == -EINVAL);
+
+ /* Bad BO offset /w an engine */
+ ret = __xe_vm_bind(fd, vm, sync_bind_engine, bo,
+ xe_get_default_alignment(fd) * 2, 0x40000,
+ size, XE_VM_BIND_OP_MAP, NULL, 0, 0, 0);
+ igt_assert(ret == -EINVAL);
+
+ /* Bad BO 2nd op */
+ memset(bind_ops, 0, sizeof(bind_ops));
+ for (i = 0; i < 2; ++i) {
+ bind_ops[i].obj = bo + i;
+ bind_ops[i].obj_offset = 0;
+ bind_ops[i].range = size;
+ bind_ops[i].addr = 0x40000 * (i + 1);
+ bind_ops[i].op = XE_VM_BIND_OP_MAP;
+ }
+ ret = __xe_vm_bind_array(fd, vm, 0, bind_ops, 2, 0, 0);
+ igt_assert(ret == -ENOENT);
+
+ /* Bad BO /w an engine 2nd op */
+ memset(bind_ops, 0, sizeof(bind_ops));
+ for (i = 0; i < 2; ++i) {
+ bind_ops[i].obj = bo + i;
+ bind_ops[i].obj_offset = 0;
+ bind_ops[i].range = size;
+ bind_ops[i].addr = 0x40000 * (i + 1);
+ bind_ops[i].op = XE_VM_BIND_OP_MAP;
+ }
+ ret = __xe_vm_bind_array(fd, vm, sync_bind_engine, bind_ops, 2, 0, 0);
+ igt_assert(ret == -ENOENT);
+
+ /* userptr_invalid 2nd op */
+ memset(bind_ops, 0, sizeof(bind_ops));
+ for (i = 0; i < 2; ++i) {
+ bind_ops[i].obj = !i ? bo : 0;
+ bind_ops[i].obj_offset = !i ? 0 : MAP_ADDRESS;
+ bind_ops[i].range = size;
+ bind_ops[i].addr = 0x40000 * (i + 1);
+ bind_ops[i].op = !i ? XE_VM_BIND_OP_MAP :
+ XE_VM_BIND_OP_MAP_USERPTR;
+ }
+ ret = __xe_vm_bind_array(fd, vm, sync_bind_engine, bind_ops, 2, 0, 0);
+ igt_assert(ret == -EFAULT);
+
+ xe_engine_destroy(fd, async_bind_engine);
+ xe_engine_destroy(fd, sync_bind_engine);
+ gem_close(fd, bo);
+ xe_vm_destroy(fd, vm);
+}
+
/**
* SUBTEST: userptr-invalid
* Description:
@@ -1847,6 +1939,9 @@ igt_main
igt_subtest("unbind-all-8-vmas")
unbind_all(fd, 8);
+ igt_subtest("eio")
+ eio(fd);
+
igt_subtest("userptr-invalid")
userptr_invalid(fd);
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [igt-dev] ✓ Fi.CI.BAT: success for IGT updates for upstreaming prep (rev2)
2023-05-02 6:55 [igt-dev] [PATCH v2 0/7] IGT updates for upstreaming prep Matthew Brost
` (6 preceding siblings ...)
2023-05-02 6:55 ` [igt-dev] [PATCH v2 7/7] xe_vm: Add EIO test Matthew Brost
@ 2023-05-02 7:30 ` Patchwork
2023-05-02 8:42 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2023-05-02 7:30 UTC (permalink / raw)
To: Matthew Brost; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 2572 bytes --]
== Series Details ==
Series: IGT updates for upstreaming prep (rev2)
URL : https://patchwork.freedesktop.org/series/117177/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13078 -> IGTPW_8893
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/index.html
Participating hosts (38 -> 36)
------------------------------
Missing (2): bat-dg2-9 fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_8893 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][1] -> [DMESG-WARN][2] ([i915#7699])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/bat-dg2-11/igt@i915_selftest@live@migrate.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [PASS][3] -> [DMESG-WARN][4] ([i915#6367])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/bat-rpls-1/igt@i915_selftest@live@slpc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/bat-rpls-1/igt@i915_selftest@live@slpc.html
#### Possible fixes ####
* igt@i915_selftest@live@migrate:
- bat-atsm-1: [DMESG-FAIL][5] ([i915#7699] / [i915#7913]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/bat-atsm-1/igt@i915_selftest@live@migrate.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/bat-atsm-1/igt@i915_selftest@live@migrate.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7277 -> IGTPW_8893
CI-20190529: 20190529
CI_DRM_13078: 59c67d4cf8b737c0c25649091a1a22809d6a06f8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8893: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/index.html
IGT_7277: 1cb3507f3ff28d11bd5cfabcde576fe78ddab571 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+++ 97 lines
--- 5 lines
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/index.html
[-- Attachment #2: Type: text/html, Size: 3299 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread* [igt-dev] ✓ Fi.CI.IGT: success for IGT updates for upstreaming prep (rev2)
2023-05-02 6:55 [igt-dev] [PATCH v2 0/7] IGT updates for upstreaming prep Matthew Brost
` (7 preceding siblings ...)
2023-05-02 7:30 ` [igt-dev] ✓ Fi.CI.BAT: success for IGT updates for upstreaming prep (rev2) Patchwork
@ 2023-05-02 8:42 ` Patchwork
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2023-05-02 8:42 UTC (permalink / raw)
To: Matthew Brost; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 11172 bytes --]
== Series Details ==
Series: IGT updates for upstreaming prep (rev2)
URL : https://patchwork.freedesktop.org/series/117177/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13078_full -> IGTPW_8893_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/index.html
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-rkl0
Known issues
------------
Here are the changes found in IGTPW_8893_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-glk4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-glk9/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#2346])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2346])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271]) +87 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-snb5/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1.html
#### Possible fixes ####
* igt@drm_fdinfo@idle@rcs0:
- {shard-rkl}: [FAIL][8] ([i915#7742]) -> [PASS][9] +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-rkl-7/igt@drm_fdinfo@idle@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-rkl-7/igt@drm_fdinfo@idle@rcs0.html
* igt@gem_barrier_race@remote-request@rcs0:
- {shard-rkl}: [ABORT][10] ([i915#7461] / [i915#8211]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-rkl-7/igt@gem_barrier_race@remote-request@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-rkl-4/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_eio@unwedge-stress:
- {shard-dg1}: [FAIL][12] ([i915#5784]) -> [PASS][13] +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-dg1-18/igt@gem_eio@unwedge-stress.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-dg1-13/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}: [FAIL][14] ([i915#2842]) -> [PASS][15] +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-rkl-4/igt@gem_exec_fair@basic-none@bcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-rkl-4/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_spin_batch@engines@rcs0:
- shard-apl: [FAIL][16] ([i915#2898]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-apl3/igt@gem_spin_batch@engines@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-apl1/igt@gem_spin_batch@engines@rcs0.html
* igt@i915_module_load@reload-no-display:
- shard-snb: [ABORT][18] ([i915#4528] / [i915#8393]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-snb4/igt@i915_module_load@reload-no-display.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-snb5/igt@i915_module_load@reload-no-display.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-tglu}: [FAIL][20] ([i915#3989] / [i915#454]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-tglu-9/igt@i915_pm_dc@dc6-dpms.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-tglu-9/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rps@waitboost:
- {shard-dg1}: [FAIL][22] ([i915#8229]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13078/shard-dg1-18/igt@i915_pm_rps@waitboost.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/shard-dg1-13/igt@i915_pm_rps@waitboost.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8229]: https://gitlab.freedesktop.org/drm/intel/issues/8229
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8393]: https://gitlab.freedesktop.org/drm/intel/issues/8393
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7277 -> IGTPW_8893
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13078: 59c67d4cf8b737c0c25649091a1a22809d6a06f8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8893: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/index.html
IGT_7277: 1cb3507f3ff28d11bd5cfabcde576fe78ddab571 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8893/index.html
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