[igt-dev] [PATCH i-g-t 0/4] Add Meteorlake CCS support

[igt-dev] [PATCH i-g-t 0/4] Add Meteorlake CCS support

[Juha-Pekka Heikkila]

Import fourcc codes from kernel and built support for MTL 4-tile aux ccs type
compression support for render and vebox copy paths.

/Juha-Pekka

Juha-Pekka Heikkila (4):
  drm/fourcc: Import drm_fourcc header from commit c7c12de893f8
    ("drm/fourcc: define Intel Meteorlake related ccs modifiers")
  lib/mtl: Add MTL related tile4 ccs modifiers handling
  tests/i915/kms_ccs: enable mtl aux ccs tests
  tests/kms_getfb: Add meteorlake related ccs modifiers

 include/drm-uapi/drm_fourcc.h | 156 +++++++++++++++++++++++++++++++---
 lib/igt_fb.c                  |  30 +++++--
 lib/intel_aux_pgtable.c       |  79 ++++++++++++-----
 lib/intel_batchbuffer.c       |  15 +++-
 lib/rendercopy.h              |   8 ++
 lib/rendercopy_gen9.c         |  44 +++++++++-
 lib/veboxcopy_gen12.c         |  79 ++++++++---------
 tests/i915/kms_ccs.c          |   6 +-
 tests/kms_getfb.c             |  13 ++-
 9 files changed, 345 insertions(+), 85 deletions(-)

-- 
2.25.1

[igt-dev] [PATCH i-g-t 1/4] drm/fourcc: Import drm_fourcc header from commit c7c12de893f8 ("drm/fourcc: define Intel Meteorlake related ccs modifiers")

[Juha-Pekka Heikkila]

commit c7c12de893f8 ("drm/fourcc: define Intel Meteorlake related ccs modifiers")
Author: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Date:   Sun May 14 21:42:39 2023 +0300

    drm/fourcc: define Intel Meteorlake related ccs modifiers

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 include/drm-uapi/drm_fourcc.h | 156 +++++++++++++++++++++++++++++++---
 1 file changed, 145 insertions(+), 11 deletions(-)

diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index 78bebdea..8db7fd3f 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -88,6 +88,18 @@ extern "C" {
  *
  * The authoritative list of format modifier codes is found in
  * `include/uapi/drm/drm_fourcc.h`
+ *
+ * Open Source User Waiver
+ * -----------------------
+ *
+ * Because this is the authoritative source for pixel formats and modifiers
+ * referenced by GL, Vulkan extensions and other standards and hence used both
+ * by open source and closed source driver stacks, the usual requirement for an
+ * upstream in-kernel or open source userspace user does not apply.
+ *
+ * To ensure, as much as feasible, compatibility across stacks and avoid
+ * confusion with incompatible enumerations stakeholders for all relevant driver
+ * stacks should approve additions.
  */
 
 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
@@ -99,18 +111,42 @@ extern "C" {
 #define DRM_FORMAT_INVALID	0
 
 /* color index */
+#define DRM_FORMAT_C1		fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
+#define DRM_FORMAT_C2		fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
+#define DRM_FORMAT_C4		fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
 #define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
 
-/* 8 bpp Red */
+/* 1 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D1		fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */
+
+/* 2 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D2		fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */
+
+/* 4 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D4		fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */
+
+/* 8 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D8		fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
+
+/* 1 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R1		fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */
+
+/* 2 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R2		fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */
+
+/* 4 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R4		fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */
+
+/* 8 bpp Red (direct relationship between channel value and brightness) */
 #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
 
-/* 10 bpp Red */
+/* 10 bpp Red (direct relationship between channel value and brightness) */
 #define DRM_FORMAT_R10		fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
 
-/* 12 bpp Red */
+/* 12 bpp Red (direct relationship between channel value and brightness) */
 #define DRM_FORMAT_R12		fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
 
-/* 16 bpp Red */
+/* 16 bpp Red (direct relationship between channel value and brightness) */
 #define DRM_FORMAT_R16		fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
 
 /* 16 bpp RG */
@@ -205,7 +241,9 @@ extern "C" {
 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
 
 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_AVUY8888	fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
 #define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XVUY8888	fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */
 #define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
 #define DRM_FORMAT_VUY101010	fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
 
@@ -559,7 +597,7 @@ extern "C" {
  *
  * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
  * and at index 1. The clear color is stored at index 2, and the pitch should
- * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits
  * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
  * by 32 bits. The raw clear color is consumed by the 3d engine and generates
  * the converted clear color of size 64 bits. The first 32 bits store the Lower
@@ -612,13 +650,56 @@ extern "C" {
  * outside of the GEM object in a reserved memory area dedicated for the
  * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
  * main surface pitch is required to be a multiple of four Tile 4 widths. The
- * clear color is stored at plane index 1 and the pitch should be ignored. The
- * format of the 256 bits of clear color data matches the one used for the
- * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
+ * clear color is stored at plane index 1 and the pitch should be 64 bytes
+ * aligned. The format of the 256 bits of clear color data matches the one used
+ * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
  * for details.
  */
 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
 
+/*
+ * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
+ *
+ * The main surface is tile4 and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * tile4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
+
+/*
+ * Intel Color Control Surfaces (CCS) for display ver. 14 media compression
+ *
+ * The main surface is tile4 and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
+
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render
+ * compression.
+ *
+ * The main surface is tile4 and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
@@ -656,6 +737,28 @@ extern "C" {
  */
 #define DRM_FORMAT_MOD_QCOM_COMPRESSED	fourcc_mod_code(QCOM, 1)
 
+/*
+ * Qualcomm Tiled Format
+ *
+ * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
+ * Implementation may be platform and base-format specific.
+ *
+ * Each macrotile consists of m x n (mostly 4 x 4) tiles.
+ * Pixel data pitch/stride is aligned with macrotile width.
+ * Pixel data height is aligned with macrotile height.
+ * Entire pixel data buffer is aligned with 4k(bytes).
+ */
+#define DRM_FORMAT_MOD_QCOM_TILED3	fourcc_mod_code(QCOM, 3)
+
+/*
+ * Qualcomm Alternate Tiled Format
+ *
+ * Alternate tiled format typically only used within GMEM.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_TILED2	fourcc_mod_code(QCOM, 2)
+
+
 /* Vivante framebuffer modifiers */
 
 /*
@@ -696,6 +799,35 @@ extern "C" {
  */
 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
 
+/*
+ * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
+ * the color buffer tiling modifiers defined above. When TS is present it's a
+ * separate buffer containing the clear/compression status of each tile. The
+ * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer
+ * tile size in bytes covered by one entry in the status buffer and s is the
+ * number of status bits per entry.
+ * We reserve the top 8 bits of the Vivante modifier space for tile status
+ * clear/compression modifiers, as future cores might add some more TS layout
+ * variations.
+ */
+#define VIVANTE_MOD_TS_64_4               (1ULL << 48)
+#define VIVANTE_MOD_TS_64_2               (2ULL << 48)
+#define VIVANTE_MOD_TS_128_4              (3ULL << 48)
+#define VIVANTE_MOD_TS_256_4              (4ULL << 48)
+#define VIVANTE_MOD_TS_MASK               (0xfULL << 48)
+
+/*
+ * Vivante compression modifiers. Those depend on a TS modifier being present
+ * as the TS bits get reinterpreted as compression tags instead of simple
+ * clear markers when compression is enabled.
+ */
+#define VIVANTE_MOD_COMP_DEC400           (1ULL << 52)
+#define VIVANTE_MOD_COMP_MASK             (0xfULL << 52)
+
+/* Masking out the extension bits will yield the base modifier. */
+#define VIVANTE_MOD_EXT_MASK              (VIVANTE_MOD_TS_MASK | \
+                                           VIVANTE_MOD_COMP_MASK)
+
 /* NVIDIA frame buffer modifiers */
 
 /*
@@ -802,7 +934,7 @@ extern "C" {
  * which corresponds to the "generic" kind used for simple single-sample
  * uncompressed color formats on Fermi - Volta GPUs.
  */
-static __inline__ __u64
+static inline __u64
 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 {
 	if (!(modifier & 0x10) || (modifier & (0xff << 12)))
@@ -1341,6 +1473,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_TILE_VER_GFX9 1
 #define AMD_FMT_MOD_TILE_VER_GFX10 2
 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
+#define AMD_FMT_MOD_TILE_VER_GFX11 4
 
 /*
  * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
@@ -1356,6 +1489,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
+#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
 
 #define AMD_FMT_MOD_DCC_BLOCK_64B 0
 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
@@ -1422,11 +1556,11 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_PIPE_MASK 0x7
 
 #define AMD_FMT_MOD_SET(field, value) \
-	((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
+	((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
 #define AMD_FMT_MOD_GET(field, value) \
 	(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
 #define AMD_FMT_MOD_CLEAR(field) \
-	(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
+	(~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
 
 #if defined(__cplusplus)
 }
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t 1/4] drm/fourcc: Import drm_fourcc header from commit c7c12de893f8 ("drm/fourcc: define Intel Meteorlake related ccs modifiers")

[Kahola, Mika]

> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Juha-Pekka Heikkila
> Sent: Tuesday, May 16, 2023 6:43 PM
> To: igt-dev@lists.freedesktop.org
> Subject: [igt-dev] [PATCH i-g-t 1/4] drm/fourcc: Import drm_fourcc header from commit c7c12de893f8 ("drm/fourcc: define
> Intel Meteorlake related ccs modifiers")
> 
> commit c7c12de893f8 ("drm/fourcc: define Intel Meteorlake related ccs modifiers")
> Author: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> Date:   Sun May 14 21:42:39 2023 +0300
> 
>     drm/fourcc: define Intel Meteorlake related ccs modifiers
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
>  include/drm-uapi/drm_fourcc.h | 156 +++++++++++++++++++++++++++++++---
>  1 file changed, 145 insertions(+), 11 deletions(-)
> 
> diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h index 78bebdea..8db7fd3f 100644
> --- a/include/drm-uapi/drm_fourcc.h
> +++ b/include/drm-uapi/drm_fourcc.h
> @@ -88,6 +88,18 @@ extern "C" {
>   *
>   * The authoritative list of format modifier codes is found in
>   * `include/uapi/drm/drm_fourcc.h`
> + *
> + * Open Source User Waiver
> + * -----------------------
> + *
> + * Because this is the authoritative source for pixel formats and
> + modifiers
> + * referenced by GL, Vulkan extensions and other standards and hence
> + used both
> + * by open source and closed source driver stacks, the usual
> + requirement for an
> + * upstream in-kernel or open source userspace user does not apply.
> + *
> + * To ensure, as much as feasible, compatibility across stacks and
> + avoid
> + * confusion with incompatible enumerations stakeholders for all
> + relevant driver
> + * stacks should approve additions.
>   */
> 
>  #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ @@ -99,18 +111,42 @@ extern "C" {
>  #define DRM_FORMAT_INVALID	0
> 
>  /* color index */
> +#define DRM_FORMAT_C1		fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight
> pixels/byte */
> +#define DRM_FORMAT_C2		fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> +#define DRM_FORMAT_C4		fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
>  #define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> 
> -/* 8 bpp Red */
> +/* 1 bpp Darkness (inverse relationship between channel value and brightness) */
> +#define DRM_FORMAT_D1		fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight
> pixels/byte */
> +
> +/* 2 bpp Darkness (inverse relationship between channel value and brightness) */
> +#define DRM_FORMAT_D2		fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */
> +
> +/* 4 bpp Darkness (inverse relationship between channel value and brightness) */
> +#define DRM_FORMAT_D4		fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */
> +
> +/* 8 bpp Darkness (inverse relationship between channel value and brightness) */
> +#define DRM_FORMAT_D8		fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
> +
> +/* 1 bpp Red (direct relationship between channel value and brightness) */
> +#define DRM_FORMAT_R1		fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight
> pixels/byte */
> +
> +/* 2 bpp Red (direct relationship between channel value and brightness) */
> +#define DRM_FORMAT_R2		fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */
> +
> +/* 4 bpp Red (direct relationship between channel value and brightness) */
> +#define DRM_FORMAT_R4		fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */
> +
> +/* 8 bpp Red (direct relationship between channel value and brightness)
> +*/
>  #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
> 
> -/* 10 bpp Red */
> +/* 10 bpp Red (direct relationship between channel value and
> +brightness) */
>  #define DRM_FORMAT_R10		fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
> 
> -/* 12 bpp Red */
> +/* 12 bpp Red (direct relationship between channel value and
> +brightness) */
>  #define DRM_FORMAT_R12		fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
> 
> -/* 16 bpp Red */
> +/* 16 bpp Red (direct relationship between channel value and
> +brightness) */
>  #define DRM_FORMAT_R16		fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
> 
>  /* 16 bpp RG */
> @@ -205,7 +241,9 @@ extern "C" {
>  #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
> 
>  #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
> +#define DRM_FORMAT_AVUY8888	fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
>  #define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
> +#define DRM_FORMAT_XVUY8888	fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */
>  #define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
>  #define DRM_FORMAT_VUY101010	fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier
> only */
> 
> @@ -559,7 +597,7 @@ extern "C" {
>   *
>   * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
>   * and at index 1. The clear color is stored at index 2, and the pitch should
> - * be ignored. The clear color structure is 256 bits. The first 128 bits
> + * be 64 bytes aligned. The clear color structure is 256 bits. The
> + first 128 bits
>   * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
>   * by 32 bits. The raw clear color is consumed by the 3d engine and generates
>   * the converted clear color of size 64 bits. The first 32 bits store the Lower @@ -612,13 +650,56 @@ extern "C" {
>   * outside of the GEM object in a reserved memory area dedicated for the
>   * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
>   * main surface pitch is required to be a multiple of four Tile 4 widths. The
> - * clear color is stored at plane index 1 and the pitch should be ignored. The
> - * format of the 256 bits of clear color data matches the one used for the
> - * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
> + * clear color is stored at plane index 1 and the pitch should be 64
> + bytes
> + * aligned. The format of the 256 bits of clear color data matches the
> + one used
> + * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its
> + description
>   * for details.
>   */
>  #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
> 
> +/*
> + * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
> + *
> + * The main surface is tile4 and at plane index 0, the CCS is linear
> +and
> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles
> +in
> + * main surface. In other words, 4 bits in CCS map to a main surface
> +cache
> + * line pair. The main surface pitch is required to be a multiple of
> +four
> + * tile4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
> +
> +/*
> + * Intel Color Control Surfaces (CCS) for display ver. 14 media
> +compression
> + *
> + * The main surface is tile4 and at plane index 0, the CCS is linear
> +and
> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles
> +in
> + * main surface. In other words, 4 bits in CCS map to a main surface
> +cache
> + * line pair. The main surface pitch is required to be a multiple of
> +four
> + * tile4 widths. For semi-planar formats like NV12, CCS planes follow
> +the
> + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
> + * planes 2 and 3 for the respective CCS.
> + */
> +#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
> +
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for display ver.
> +14 render
> + * compression.
> + *
> + * The main surface is tile4 and is at plane index 0 whereas CCS is
> +linear
> + * and at index 1. The clear color is stored at index 2, and the pitch
> +should
> + * be ignored. The clear color structure is 256 bits. The first 128
> +bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> +represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and
> +generates
> + * the converted clear color of size 64 bits. The first 32 bits store
> +the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher
> +Converted
> + * Clear Color value when applicable. The Converted Clear Color values
> +are
> + * consumed by the DE. The last 64 bits are used to store Color Discard
> +Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache
> +line
> + * corresponds to an area of 4x1 tiles in the main surface. The main
> +surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL,
> +15)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> @@ -656,6 +737,28 @@ extern "C" {
>   */
>  #define DRM_FORMAT_MOD_QCOM_COMPRESSED	fourcc_mod_code(QCOM, 1)
> 
> +/*
> + * Qualcomm Tiled Format
> + *
> + * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
> + * Implementation may be platform and base-format specific.
> + *
> + * Each macrotile consists of m x n (mostly 4 x 4) tiles.
> + * Pixel data pitch/stride is aligned with macrotile width.
> + * Pixel data height is aligned with macrotile height.
> + * Entire pixel data buffer is aligned with 4k(bytes).
> + */
> +#define DRM_FORMAT_MOD_QCOM_TILED3	fourcc_mod_code(QCOM, 3)
> +
> +/*
> + * Qualcomm Alternate Tiled Format
> + *
> + * Alternate tiled format typically only used within GMEM.
> + * Implementation may be platform and base-format specific.
> + */
> +#define DRM_FORMAT_MOD_QCOM_TILED2	fourcc_mod_code(QCOM, 2)
> +
> +
>  /* Vivante framebuffer modifiers */
> 
>  /*
> @@ -696,6 +799,35 @@ extern "C" {
>   */
>  #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
> 
> +/*
> + * Vivante TS (tile-status) buffer modifiers. They can be combined with
> +all of
> + * the color buffer tiling modifiers defined above. When TS is present
> +it's a
> + * separate buffer containing the clear/compression status of each
> +tile. The
> + * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color
> +buffer
> + * tile size in bytes covered by one entry in the status buffer and s
> +is the
> + * number of status bits per entry.
> + * We reserve the top 8 bits of the Vivante modifier space for tile
> +status
> + * clear/compression modifiers, as future cores might add some more TS
> +layout
> + * variations.
> + */
> +#define VIVANTE_MOD_TS_64_4               (1ULL << 48)
> +#define VIVANTE_MOD_TS_64_2               (2ULL << 48)
> +#define VIVANTE_MOD_TS_128_4              (3ULL << 48)
> +#define VIVANTE_MOD_TS_256_4              (4ULL << 48)
> +#define VIVANTE_MOD_TS_MASK               (0xfULL << 48)
> +
> +/*
> + * Vivante compression modifiers. Those depend on a TS modifier being
> +present
> + * as the TS bits get reinterpreted as compression tags instead of
> +simple
> + * clear markers when compression is enabled.
> + */
> +#define VIVANTE_MOD_COMP_DEC400           (1ULL << 52)
> +#define VIVANTE_MOD_COMP_MASK             (0xfULL << 52)
> +
> +/* Masking out the extension bits will yield the base modifier. */
> +#define VIVANTE_MOD_EXT_MASK              (VIVANTE_MOD_TS_MASK | \
> +                                           VIVANTE_MOD_COMP_MASK)
> +
>  /* NVIDIA frame buffer modifiers */
> 
>  /*
> @@ -802,7 +934,7 @@ extern "C" {
>   * which corresponds to the "generic" kind used for simple single-sample
>   * uncompressed color formats on Fermi - Volta GPUs.
>   */
> -static __inline__ __u64
> +static inline __u64
>  drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)  {
>  	if (!(modifier & 0x10) || (modifier & (0xff << 12))) @@ -1341,6 +1473,7 @@
> drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)  #define AMD_FMT_MOD_TILE_VER_GFX9 1  #define
> AMD_FMT_MOD_TILE_VER_GFX10 2  #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
> +#define AMD_FMT_MOD_TILE_VER_GFX11 4
> 
>  /*
>   * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical @@ -1356,6 +1489,7 @@
> drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)  #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25  #define
> AMD_FMT_MOD_TILE_GFX9_64K_D_X 26  #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
> +#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
> 
>  #define AMD_FMT_MOD_DCC_BLOCK_64B 0
>  #define AMD_FMT_MOD_DCC_BLOCK_128B 1
> @@ -1422,11 +1556,11 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)  #define
> AMD_FMT_MOD_PIPE_MASK 0x7
> 
>  #define AMD_FMT_MOD_SET(field, value) \
> -	((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
> +	((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
>  #define AMD_FMT_MOD_GET(field, value) \
>  	(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)  #define
> AMD_FMT_MOD_CLEAR(field) \
> -	(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
> +	(~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
> 
>  #if defined(__cplusplus)
>  }
> --
> 2.25.1

[igt-dev] [PATCH i-g-t 2/4] lib/mtl: Add MTL related tile4 ccs modifiers handling

[Juha-Pekka Heikkila]

Add tile4 type ccs modifiers with aux buffer in fb structure

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 lib/igt_fb.c            | 30 +++++++++++++---
 lib/intel_aux_pgtable.c | 79 +++++++++++++++++++++++++++++------------
 lib/intel_batchbuffer.c | 15 ++++++--
 lib/rendercopy.h        |  8 +++++
 lib/rendercopy_gen9.c   | 44 ++++++++++++++++++++++-
 lib/veboxcopy_gen12.c   | 79 +++++++++++++++++++++--------------------
 6 files changed, 186 insertions(+), 69 deletions(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 0fe5b6ad..71a199d4 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -454,6 +454,9 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 			*height_ret = 8;
 		}
 		break;
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
+	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
@@ -572,7 +575,8 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 static bool is_gen12_mc_ccs_modifier(uint64_t modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
-		modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
+		modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS ||
+		modifier == I915_FORMAT_MOD_4_TILED_MTL_MC_CCS;
 }
 
 static bool is_gen12_ccs_modifier(uint64_t modifier)
@@ -581,7 +585,9 @@ static bool is_gen12_ccs_modifier(uint64_t modifier)
 		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
 		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
 		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS ||
-		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
+		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC ||
+		modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS ||
+		modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC;
 }
 
 static bool is_ccs_modifier(uint64_t modifier)
@@ -611,8 +617,9 @@ static bool is_gen12_ccs_plane(const struct igt_fb *fb, int plane)
 
 static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)
 {
-	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
-	    plane == 2)
+	if (plane == 2 &&
+	    (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
+	     fb->modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC))
 		return true;
 
 	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC &&
@@ -706,6 +713,7 @@ static int fb_num_planes(const struct igt_fb *fb)
 		num_planes *= 2;
 
 	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
+	    fb->modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC ||
 	    fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
 		num_planes++;
 
@@ -903,6 +911,11 @@ static unsigned int get_plane_alignment(struct igt_fb *fb, int color_plane)
 
 	alignment = lcm(tile_row_size, 64 * 1024);
 
+	if (is_yuv_semiplanar_plane(fb, color_plane) &&
+	    fb->modifier == I915_FORMAT_MOD_4_TILED_MTL_MC_CCS &&
+	    (alignment & ((1 << 20) - 1)))
+		alignment = 1 << 20;
+
 	return alignment;
 }
 
@@ -989,6 +1002,9 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
 	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
 		return I915_TILING_4;
 	case I915_FORMAT_MOD_Yf_TILED:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2614,7 +2630,8 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
 				 end - fb->offsets[i]);
 	}
 
-	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
+	    fb->modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC)
 		buf->cc.offset = fb->offsets[2];
 
 	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
@@ -4656,10 +4673,13 @@ const char *igt_fb_modifier_name(uint64_t modifier)
 		return "Y-MC_CCS";
 	case I915_FORMAT_MOD_4_TILED:
 		return "4";
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
 		return "4-RC_CCS";
+	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
 	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 		return "4-MC_CCS";
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 		return "4-RC_CCS-CC";
 	default:
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index 946ca60b..7c795213 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -5,6 +5,7 @@
 #include "intel_aux_pgtable.h"
 #include "intel_batchbuffer.h"
 #include "intel_bufops.h"
+#include "intel_chipset.h"
 #include "ioctl_wrappers.h"
 
 #include "i915/gem_mman.h"
@@ -12,22 +13,6 @@
 #define BITMASK(e, s)		((~0ULL << (s)) & \
 				 (~0ULL >> (BITS_PER_LONG_LONG - 1 - (e))))
 
-/* The unit size to which the AUX CCS surface is aligned to. */
-#define AUX_CCS_UNIT_SIZE	64
-/*
- * The block size on the AUX CCS surface which is mapped by one L1 AUX
- * pagetable entry.
- */
-#define AUX_CCS_BLOCK_SIZE	(4 * AUX_CCS_UNIT_SIZE)
-/*
- * The block size on the main surface mapped by one AUX CCS block:
- *   256 bytes per CCS block *
- *   8   bits per byte /
- *   2   bits per main surface CL *
- *   64  bytes per main surface CL
- */
-#define MAIN_SURFACE_BLOCK_SIZE	(AUX_CCS_BLOCK_SIZE * 8 / 2 * 64)
-
 #define GFX_ADDRESS_BITS	48
 
 #define AUX_FORMAT_YCRCB	0x03
@@ -357,14 +342,24 @@ pgt_populate_entries_for_buf(struct pgtable *pgt,
 	uint64_t aux_addr = buf->addr.offset + buf->ccs[surface_idx].offset;
 	uint64_t l1_flags = pgt_get_l1_flags(buf, surface_idx);
 	uint64_t lx_flags = pgt_get_lx_flags();
+	uint64_t aux_ccs_block_size = 1 << pgt->level_info->desc[0].entry_ptr_shift;
+
+	/*
+	 * The block size on the main surface mapped by one AUX CCS block:
+	 *       CCS block size *
+	 *   8   bits per byte /
+	 *   2   bits per main surface CL *
+	 *   64  bytes per main surface CL
+	 */
+	uint64_t main_surface_block_size = aux_ccs_block_size * 8 / 2 * 64;
 
 	igt_assert(!(buf->surface[surface_idx].stride % 512));
 	igt_assert_eq(buf->ccs[surface_idx].stride,
 		      buf->surface[surface_idx].stride / 512 * 64);
 
 	for (; surface_addr < surface_end;
-	     surface_addr += MAIN_SURFACE_BLOCK_SIZE,
-	     aux_addr += AUX_CCS_BLOCK_SIZE) {
+	     surface_addr += main_surface_block_size,
+	     aux_addr += aux_ccs_block_size) {
 		uint64_t table = top_table;
 		int level;
 
@@ -445,7 +440,7 @@ struct intel_buf *
 intel_aux_pgtable_create(struct intel_bb *ibb,
 			 struct intel_buf **bufs, int buf_count)
 {
-	static const struct pgtable_level_desc level_desc[] = {
+	static const struct pgtable_level_desc level_desc_table_tgl[] = {
 		{
 			.idx_shift = 16,
 			.idx_bits = 8,
@@ -458,6 +453,26 @@ intel_aux_pgtable_create(struct intel_bb *ibb,
 			.entry_ptr_shift = 13,
 			.table_size = 32 * 1024,
 		},
+		{
+			.idx_shift = 36,
+			.idx_bits = 12,
+			.entry_ptr_shift = 15,
+			.table_size = 32 * 1024,
+		}
+	};
+	static const struct pgtable_level_desc level_desc_table_mtl[] = {
+		{
+			.idx_shift = 20,
+			.idx_bits = 4,
+			.entry_ptr_shift = 12,
+			.table_size = 8 * 1024,
+		},
+		{
+			.idx_shift = 24,
+			.idx_bits = 12,
+			.entry_ptr_shift = 11,
+			.table_size = 32 * 1024,
+		},
 		{
 			.idx_shift = 36,
 			.idx_bits = 12,
@@ -465,6 +480,9 @@ intel_aux_pgtable_create(struct intel_bb *ibb,
 			.table_size = 32 * 1024,
 		},
 	};
+
+	const struct pgtable_level_desc *level_desc;
+	uint32_t levels;
 	struct pgtable *pgt;
 	struct buf_ops *bops;
 	struct intel_buf *buf;
@@ -472,7 +490,15 @@ intel_aux_pgtable_create(struct intel_bb *ibb,
 	igt_assert(buf_count);
 	bops = bufs[0]->bops;
 
-	pgt = pgt_create(level_desc, ARRAY_SIZE(level_desc), bufs, buf_count);
+	if (IS_METEORLAKE(ibb->devid)) {
+		level_desc = level_desc_table_mtl;
+		levels = ARRAY_SIZE(level_desc_table_mtl);
+	} else {
+		level_desc = level_desc_table_tgl;
+		levels = ARRAY_SIZE(level_desc_table_tgl);
+	}
+
+	pgt = pgt_create(&level_desc[0], levels, bufs, buf_count);
 	pgt->ibb = ibb;
 	pgt->buf = intel_buf_create(bops, pgt->size, 1, 8, 0, I915_TILING_NONE,
 				    I915_COMPRESSION_NONE);
@@ -637,8 +663,17 @@ gen12_create_aux_pgtable_state(struct intel_bb *ibb,
 void
 gen12_emit_aux_pgtable_state(struct intel_bb *ibb, uint32_t state, bool render)
 {
-	uint32_t table_base_reg = render ? GEN12_GFX_AUX_TABLE_BASE_ADDR :
-					   GEN12_VEBOX_AUX_TABLE_BASE_ADDR;
+	uint32_t table_base_reg;
+
+	if (render) {
+		table_base_reg = GEN12_GFX_AUX_TABLE_BASE_ADDR;
+	} else {
+		/* Vebox */
+		if (IS_METEORLAKE(ibb->devid))
+			table_base_reg = 0x380000 + GEN12_VEBOX_AUX_TABLE_BASE_ADDR;
+		else
+			table_base_reg = GEN12_VEBOX_AUX_TABLE_BASE_ADDR;
+	}
 
 	if (!state)
 		return;
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 545d1705..9667c694 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -671,8 +671,10 @@ igt_render_copyfunc_t igt_get_render_copyfunc(int devid)
 		copy = gen9_render_copyfunc;
 	else if (IS_GEN11(devid))
 		copy = gen11_render_copyfunc;
-	else if (HAS_4TILE(devid))
+	else if (HAS_FLATCCS(devid))
 		copy = gen12p71_render_copyfunc;
+	else if (IS_METEORLAKE(devid))
+		copy = mtl_render_copyfunc;
 	else if (IS_GEN12(devid))
 		copy = gen12_render_copyfunc;
 
@@ -691,7 +693,9 @@ igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid)
 
 igt_render_clearfunc_t igt_get_render_clearfunc(int devid)
 {
-	if (IS_DG2(devid)) {
+	if (IS_METEORLAKE(devid)) {
+		return mtl_render_clearfunc;
+	} else if (IS_DG2(devid)) {
 		return gen12p71_render_clearfunc;
 	} else if (IS_GEN12(devid)) {
 		return gen12_render_clearfunc;
@@ -1758,8 +1762,13 @@ __intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf,
 	if (!alignment) {
 		alignment = 0x1000;
 
+		/*
+		 * TODO:
+		 * Find out why MTL need special alignment, spec says 32k
+		 * is enough for MTL.
+		 */
 		if (ibb->gen >= 12 && buf->compression)
-			alignment = 0x10000;
+			alignment = IS_METEORLAKE(ibb->devid) ? 0x100000 : 0x10000;
 
 		/* For gen3 ensure tiled buffers are aligned to power of two size */
 		if (ibb->gen == 3 && buf->tiling) {
diff --git a/lib/rendercopy.h b/lib/rendercopy.h
index 480fdee8..0d81d27f 100644
--- a/lib/rendercopy.h
+++ b/lib/rendercopy.h
@@ -23,6 +23,10 @@ static inline void emit_vertex_normalized(struct intel_bb *ibb,
 	intel_bb_out(ibb, u.ui);
 }
 
+void mtl_render_clearfunc(struct intel_bb *ibb,
+			  struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y,
+			  unsigned int width, unsigned int height,
+			  const float clear_color[4]);
 void gen12p71_render_clearfunc(struct intel_bb *ibb,
 			       struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y,
 			       unsigned int width, unsigned int height,
@@ -31,6 +35,10 @@ void gen12_render_clearfunc(struct intel_bb *ibb,
 			    struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y,
 			    unsigned int width, unsigned int height,
 			    const float clear_color[4]);
+void mtl_render_copyfunc(struct intel_bb *ibb,
+			 struct intel_buf *src, uint32_t src_x, uint32_t src_y,
+			 uint32_t width, uint32_t height,
+			 struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
 void gen12p71_render_copyfunc(struct intel_bb *ibb,
 			      struct intel_buf *src, uint32_t src_x, uint32_t src_y,
 			      uint32_t width, uint32_t height,
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 650d0950..db67b5ee 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -277,7 +277,9 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
 
 			ss->ss12.clear_address = (address + buf->cc.offset) >> 6;
 			ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32;
-		} else if (HAS_FLATCCS(ibb->devid)) {
+		}
+
+		if (HAS_4TILE(ibb->devid)) {
 			ss->ss7.dg2.memory_compression_type = 0;
 			ss->ss7.dg2.memory_compression_enable = 0;
 			ss->ss7.dg2.disable_support_for_multi_gpu_partial_writes = 1;
@@ -1245,6 +1247,27 @@ void gen12p71_render_copyfunc(struct intel_bb *ibb,
 			sizeof(gen12p71_render_copy));
 }
 
+void mtl_render_copyfunc(struct intel_bb *ibb,
+			 struct intel_buf *src,
+			 unsigned int src_x, unsigned int src_y,
+			 unsigned int width, unsigned int height,
+			 struct intel_buf *dst,
+			 unsigned int dst_x, unsigned int dst_y)
+{
+	struct aux_pgtable_info pgtable_info = { };
+
+	gen12_aux_pgtable_init(&pgtable_info, ibb, src, dst);
+
+	_gen9_render_op(ibb, src, src_x, src_y,
+			width, height, dst, dst_x, dst_y,
+			pgtable_info.pgtable_buf,
+			NULL,
+			gen12p71_render_copy,
+			sizeof(gen12p71_render_copy));
+
+	gen12_aux_pgtable_cleanup(ibb, &pgtable_info);
+}
+
 void gen12_render_clearfunc(struct intel_bb *ibb,
 			    struct intel_buf *dst,
 			    unsigned int dst_x, unsigned int dst_y,
@@ -1277,3 +1300,22 @@ void gen12p71_render_clearfunc(struct intel_bb *ibb,
 			gen12p71_render_copy,
 			sizeof(gen12p71_render_copy));
 }
+
+void mtl_render_clearfunc(struct intel_bb *ibb,
+			  struct intel_buf *dst,
+			  unsigned int dst_x, unsigned int dst_y,
+			  unsigned int width, unsigned int height,
+			  const float clear_color[4])
+{
+	struct aux_pgtable_info pgtable_info = { };
+
+	gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst);
+
+	_gen9_render_op(ibb, NULL, 0, 0,
+			width, height, dst, dst_x, dst_y,
+			pgtable_info.pgtable_buf,
+			clear_color,
+			gen12p71_render_copy,
+			sizeof(gen12p71_render_copy));
+	gen12_aux_pgtable_cleanup(ibb, &pgtable_info);
+}
diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c
index aa90939b..4ab6ced3 100644
--- a/lib/veboxcopy_gen12.c
+++ b/lib/veboxcopy_gen12.c
@@ -158,13 +158,36 @@ static bool format_is_interleaved_yuv(int format)
 	return false;
 }
 
+static uint32_t compression_format(int format, struct intel_buf *buf)
+{
+	if (buf->compression == I915_COMPRESSION_NONE)
+		return 0;
+
+	switch (format) {
+	case R8G8B8A8_UNORM:
+		return 0xa;
+	case PLANAR_420_8:
+		return 0xf;
+	case PLANAR_420_16:
+		return 8;
+	case YCRCB_NORMAL:
+		return 3;
+	case PACKED_444A_8:
+		return 9;
+	default:
+		igt_assert(0);
+	}
+}
+
 static void emit_surface_state_cmd(struct intel_bb *ibb,
 				   int surface_id,
-				   int width, int height, int bpp,
-				   int pitch, uint32_t tiling, int format,
-				   uint32_t uv_offset)
+				   int width, int height,
+				   struct intel_buf *buf, int format)
 {
 	struct vebox_surface_state *ss;
+	int pitch = buf->surface[0].stride;
+	uint32_t uv_offset = buf->surface[1].offset;
+	uint32_t tiling = buf->tiling;
 
 	ss = intel_bb_ptr_align(ibb, 4);
 
@@ -185,35 +208,16 @@ static void emit_surface_state_cmd(struct intel_bb *ibb,
 
 	ss->ss4.u_y_offset = uv_offset / pitch;
 
-	if (HAS_FLATCCS(ibb->devid)) {
+	if (HAS_4TILE(ibb->devid)) {
 		/*
-		 * f-tile = 3 (Tile F)
+		 * tile4 = 3
 		 */
 		ss->ss3.dg2.tile_mode = (tiling != I915_TILING_NONE) ? 3 : 0;
 
-		switch (format) {
-		case R8G8B8A8_UNORM:
-			ss->ss7.dg2.compression_format = 0xa;
-			break;
-		case PLANAR_420_8:
-			ss->ss7.dg2.compression_format = 0xf;
-			break;
-		case PLANAR_420_16:
-			ss->ss7.dg2.compression_format = 8;
-			break;
-		case YCRCB_NORMAL:
-			ss->ss7.dg2.compression_format = 3;
-			break;
-		case PACKED_444A_8:
-			ss->ss7.dg2.compression_format = 0x9;
-			break;
-		default:
-			igt_assert(0);
-		}
+		ss->ss7.dg2.compression_format = compression_format(format, buf);
 	} else {
 		ss->ss3.tgl.tile_walk = (tiling == I915_TILING_Y) ||
-			(tiling == I915_TILING_Yf) ||
-			(tiling == I915_TILING_4);
+			(tiling == I915_TILING_Yf);
 		ss->ss3.tgl.tiled_surface = tiling != I915_TILING_NONE;
 	}
 
@@ -246,9 +250,10 @@ static void emit_tiling_convert_cmd(struct intel_bb *ibb,
 	}
 
 	if (HAS_4TILE(ibb->devid))
-		tc->tc1_2.input_mocs_idx = 3;
-	else
-		tc->tc1_2.input_tiled_resource_mode = src->tiling == I915_TILING_Yf;
+		tc->tc1_2.input_mocs_idx = IS_DG2(ibb->devid) ? 3 : 9;
+
+	tc->tc1_2.input_tiled_resource_mode = src->tiling == I915_TILING_Yf;
+
 	reloc_delta = tc->tc1_2_l;
 
 	igt_assert(src->addr.offset == ALIGN(src->addr.offset, 0x1000));
@@ -267,9 +272,9 @@ static void emit_tiling_convert_cmd(struct intel_bb *ibb,
 	}
 
 	if (HAS_4TILE(ibb->devid))
-		tc->tc3_4.output_mocs_idx = 3;
-	else
-		tc->tc3_4.output_tiled_resource_mode = dst->tiling == I915_TILING_Yf;
+		tc->tc3_4.output_mocs_idx = IS_DG2(ibb->devid) ? 3 : 9;
+
+	tc->tc3_4.output_tiled_resource_mode = dst->tiling == I915_TILING_Yf;
 
 	reloc_delta = tc->tc3_4_l;
 
@@ -344,14 +349,12 @@ void gen12_vebox_copyfunc(struct intel_bb *ibb,
 	igt_assert(!src->format_is_yuv_semiplanar ||
 		   (src->surface[1].offset && dst->surface[1].offset));
 	emit_surface_state_cmd(ibb, VEBOX_SURFACE_INPUT,
-			       width, height, src->bpp,
-			       src->surface[0].stride,
-			       src->tiling, format, src->surface[1].offset);
+			       width, height,
+			       src, format);
 
 	emit_surface_state_cmd(ibb, VEBOX_SURFACE_OUTPUT,
-			       width, height, dst->bpp,
-			       dst->surface[0].stride,
-			       dst->tiling, format, dst->surface[1].offset);
+			       width, height,
+			       dst, format);
 
 	emit_tiling_convert_cmd(ibb, src, dst);
 
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t 2/4] lib/mtl: Add MTL related tile4 ccs modifiers handling

[Kahola, Mika]

> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Juha-Pekka Heikkila
> Sent: Tuesday, May 16, 2023 6:43 PM
> To: igt-dev@lists.freedesktop.org
> Subject: [igt-dev] [PATCH i-g-t 2/4] lib/mtl: Add MTL related tile4 ccs modifiers handling
> 
> Add tile4 type ccs modifiers with aux buffer in fb structure
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
>  lib/igt_fb.c            | 30 +++++++++++++---
>  lib/intel_aux_pgtable.c | 79 +++++++++++++++++++++++++++++------------
>  lib/intel_batchbuffer.c | 15 ++++++--
>  lib/rendercopy.h        |  8 +++++
>  lib/rendercopy_gen9.c   | 44 ++++++++++++++++++++++-
>  lib/veboxcopy_gen12.c   | 79 +++++++++++++++++++++--------------------
>  6 files changed, 186 insertions(+), 69 deletions(-)
> 
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 0fe5b6ad..71a199d4 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -454,6 +454,9 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
>  			*height_ret = 8;
>  		}
>  		break;
> +	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
> +	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> @@ -572,7 +575,8 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,  static bool
> is_gen12_mc_ccs_modifier(uint64_t modifier)  {
>  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> -		modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS ||
> +		modifier == I915_FORMAT_MOD_4_TILED_MTL_MC_CCS;
>  }
> 
>  static bool is_gen12_ccs_modifier(uint64_t modifier) @@ -581,7 +585,9 @@ static bool is_gen12_ccs_modifier(uint64_t
> modifier)
>  		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
>  		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
>  		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS ||
> -		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
> +		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC ||
> +		modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS ||
> +		modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC;
>  }
> 
>  static bool is_ccs_modifier(uint64_t modifier) @@ -611,8 +617,9 @@ static bool is_gen12_ccs_plane(const struct igt_fb *fb,
> int plane)
> 
>  static bool is_gen12_ccs_cc_plane(const struct igt_fb *fb, int plane)  {
> -	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
> -	    plane == 2)
> +	if (plane == 2 &&
> +	    (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> +	     fb->modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC))
>  		return true;
> 
>  	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC && @@ -706,6 +713,7 @@ static int
> fb_num_planes(const struct igt_fb *fb)
>  		num_planes *= 2;
> 
>  	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> +	    fb->modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC ||
>  	    fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
>  		num_planes++;
> 
> @@ -903,6 +911,11 @@ static unsigned int get_plane_alignment(struct igt_fb *fb, int color_plane)
> 
>  	alignment = lcm(tile_row_size, 64 * 1024);
> 
> +	if (is_yuv_semiplanar_plane(fb, color_plane) &&
> +	    fb->modifier == I915_FORMAT_MOD_4_TILED_MTL_MC_CCS &&
> +	    (alignment & ((1 << 20) - 1)))
> +		alignment = 1 << 20;
> +
>  	return alignment;
>  }
> 
> @@ -989,6 +1002,9 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
>  	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
>  	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>  	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> +	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
>  		return I915_TILING_4;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -2614,7 +2630,8 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
>  				 end - fb->offsets[i]);
>  	}
> 
> -	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> +	    fb->modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC)
>  		buf->cc.offset = fb->offsets[2];
> 
>  	if (fb->modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC)
> @@ -4656,10 +4673,13 @@ const char *igt_fb_modifier_name(uint64_t modifier)
>  		return "Y-MC_CCS";
>  	case I915_FORMAT_MOD_4_TILED:
>  		return "4";
> +	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
>  	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
>  		return "4-RC_CCS";
> +	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
>  	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>  		return "4-MC_CCS";
> +	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
>  	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>  		return "4-RC_CCS-CC";
>  	default:
> diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index 946ca60b..7c795213 100644
> --- a/lib/intel_aux_pgtable.c
> +++ b/lib/intel_aux_pgtable.c
> @@ -5,6 +5,7 @@
>  #include "intel_aux_pgtable.h"
>  #include "intel_batchbuffer.h"
>  #include "intel_bufops.h"
> +#include "intel_chipset.h"
>  #include "ioctl_wrappers.h"
> 
>  #include "i915/gem_mman.h"
> @@ -12,22 +13,6 @@
>  #define BITMASK(e, s)		((~0ULL << (s)) & \
>  				 (~0ULL >> (BITS_PER_LONG_LONG - 1 - (e))))
> 
> -/* The unit size to which the AUX CCS surface is aligned to. */
> -#define AUX_CCS_UNIT_SIZE	64
> -/*
> - * The block size on the AUX CCS surface which is mapped by one L1 AUX
> - * pagetable entry.
> - */
> -#define AUX_CCS_BLOCK_SIZE	(4 * AUX_CCS_UNIT_SIZE)
> -/*
> - * The block size on the main surface mapped by one AUX CCS block:
> - *   256 bytes per CCS block *
> - *   8   bits per byte /
> - *   2   bits per main surface CL *
> - *   64  bytes per main surface CL
> - */
> -#define MAIN_SURFACE_BLOCK_SIZE	(AUX_CCS_BLOCK_SIZE * 8 / 2 * 64)
> -
>  #define GFX_ADDRESS_BITS	48
> 
>  #define AUX_FORMAT_YCRCB	0x03
> @@ -357,14 +342,24 @@ pgt_populate_entries_for_buf(struct pgtable *pgt,
>  	uint64_t aux_addr = buf->addr.offset + buf->ccs[surface_idx].offset;
>  	uint64_t l1_flags = pgt_get_l1_flags(buf, surface_idx);
>  	uint64_t lx_flags = pgt_get_lx_flags();
> +	uint64_t aux_ccs_block_size = 1 <<
> +pgt->level_info->desc[0].entry_ptr_shift;
> +
> +	/*
> +	 * The block size on the main surface mapped by one AUX CCS block:
> +	 *       CCS block size *
> +	 *   8   bits per byte /
> +	 *   2   bits per main surface CL *
> +	 *   64  bytes per main surface CL
> +	 */
> +	uint64_t main_surface_block_size = aux_ccs_block_size * 8 / 2 * 64;
> 
>  	igt_assert(!(buf->surface[surface_idx].stride % 512));
>  	igt_assert_eq(buf->ccs[surface_idx].stride,
>  		      buf->surface[surface_idx].stride / 512 * 64);
> 
>  	for (; surface_addr < surface_end;
> -	     surface_addr += MAIN_SURFACE_BLOCK_SIZE,
> -	     aux_addr += AUX_CCS_BLOCK_SIZE) {
> +	     surface_addr += main_surface_block_size,
> +	     aux_addr += aux_ccs_block_size) {
>  		uint64_t table = top_table;
>  		int level;
> 
> @@ -445,7 +440,7 @@ struct intel_buf *
>  intel_aux_pgtable_create(struct intel_bb *ibb,
>  			 struct intel_buf **bufs, int buf_count)  {
> -	static const struct pgtable_level_desc level_desc[] = {
> +	static const struct pgtable_level_desc level_desc_table_tgl[] = {
>  		{
>  			.idx_shift = 16,
>  			.idx_bits = 8,
> @@ -458,6 +453,26 @@ intel_aux_pgtable_create(struct intel_bb *ibb,
>  			.entry_ptr_shift = 13,
>  			.table_size = 32 * 1024,
>  		},
> +		{
> +			.idx_shift = 36,
> +			.idx_bits = 12,
> +			.entry_ptr_shift = 15,
> +			.table_size = 32 * 1024,
> +		}
> +	};
> +	static const struct pgtable_level_desc level_desc_table_mtl[] = {
> +		{
> +			.idx_shift = 20,
> +			.idx_bits = 4,
> +			.entry_ptr_shift = 12,
> +			.table_size = 8 * 1024,
> +		},
> +		{
> +			.idx_shift = 24,
> +			.idx_bits = 12,
> +			.entry_ptr_shift = 11,
> +			.table_size = 32 * 1024,
> +		},
>  		{
>  			.idx_shift = 36,
>  			.idx_bits = 12,
> @@ -465,6 +480,9 @@ intel_aux_pgtable_create(struct intel_bb *ibb,
>  			.table_size = 32 * 1024,
>  		},
>  	};
> +
> +	const struct pgtable_level_desc *level_desc;
> +	uint32_t levels;
>  	struct pgtable *pgt;
>  	struct buf_ops *bops;
>  	struct intel_buf *buf;
> @@ -472,7 +490,15 @@ intel_aux_pgtable_create(struct intel_bb *ibb,
>  	igt_assert(buf_count);
>  	bops = bufs[0]->bops;
> 
> -	pgt = pgt_create(level_desc, ARRAY_SIZE(level_desc), bufs, buf_count);
> +	if (IS_METEORLAKE(ibb->devid)) {
> +		level_desc = level_desc_table_mtl;
> +		levels = ARRAY_SIZE(level_desc_table_mtl);
> +	} else {
> +		level_desc = level_desc_table_tgl;
> +		levels = ARRAY_SIZE(level_desc_table_tgl);
> +	}
> +
> +	pgt = pgt_create(&level_desc[0], levels, bufs, buf_count);
>  	pgt->ibb = ibb;
>  	pgt->buf = intel_buf_create(bops, pgt->size, 1, 8, 0, I915_TILING_NONE,
>  				    I915_COMPRESSION_NONE);
> @@ -637,8 +663,17 @@ gen12_create_aux_pgtable_state(struct intel_bb *ibb,  void  gen12_emit_aux_pgtable_state(struct
> intel_bb *ibb, uint32_t state, bool render)  {
> -	uint32_t table_base_reg = render ? GEN12_GFX_AUX_TABLE_BASE_ADDR :
> -					   GEN12_VEBOX_AUX_TABLE_BASE_ADDR;
> +	uint32_t table_base_reg;
> +
> +	if (render) {
> +		table_base_reg = GEN12_GFX_AUX_TABLE_BASE_ADDR;
> +	} else {
> +		/* Vebox */
> +		if (IS_METEORLAKE(ibb->devid))
> +			table_base_reg = 0x380000 + GEN12_VEBOX_AUX_TABLE_BASE_ADDR;
> +		else
> +			table_base_reg = GEN12_VEBOX_AUX_TABLE_BASE_ADDR;
> +	}
> 
>  	if (!state)
>  		return;
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index 545d1705..9667c694 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -671,8 +671,10 @@ igt_render_copyfunc_t igt_get_render_copyfunc(int devid)
>  		copy = gen9_render_copyfunc;
>  	else if (IS_GEN11(devid))
>  		copy = gen11_render_copyfunc;
> -	else if (HAS_4TILE(devid))
> +	else if (HAS_FLATCCS(devid))
>  		copy = gen12p71_render_copyfunc;
> +	else if (IS_METEORLAKE(devid))
> +		copy = mtl_render_copyfunc;
>  	else if (IS_GEN12(devid))
>  		copy = gen12_render_copyfunc;
> 
> @@ -691,7 +693,9 @@ igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid)
> 
>  igt_render_clearfunc_t igt_get_render_clearfunc(int devid)  {
> -	if (IS_DG2(devid)) {
> +	if (IS_METEORLAKE(devid)) {
> +		return mtl_render_clearfunc;
> +	} else if (IS_DG2(devid)) {
>  		return gen12p71_render_clearfunc;
>  	} else if (IS_GEN12(devid)) {
>  		return gen12_render_clearfunc;
> @@ -1758,8 +1762,13 @@ __intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf,
>  	if (!alignment) {
>  		alignment = 0x1000;
> 
> +		/*
> +		 * TODO:
> +		 * Find out why MTL need special alignment, spec says 32k
> +		 * is enough for MTL.
> +		 */
>  		if (ibb->gen >= 12 && buf->compression)
> -			alignment = 0x10000;
> +			alignment = IS_METEORLAKE(ibb->devid) ? 0x100000 : 0x10000;
> 
>  		/* For gen3 ensure tiled buffers are aligned to power of two size */
>  		if (ibb->gen == 3 && buf->tiling) {
> diff --git a/lib/rendercopy.h b/lib/rendercopy.h index 480fdee8..0d81d27f 100644
> --- a/lib/rendercopy.h
> +++ b/lib/rendercopy.h
> @@ -23,6 +23,10 @@ static inline void emit_vertex_normalized(struct intel_bb *ibb,
>  	intel_bb_out(ibb, u.ui);
>  }
> 
> +void mtl_render_clearfunc(struct intel_bb *ibb,
> +			  struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y,
> +			  unsigned int width, unsigned int height,
> +			  const float clear_color[4]);
>  void gen12p71_render_clearfunc(struct intel_bb *ibb,
>  			       struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y,
>  			       unsigned int width, unsigned int height, @@ -31,6 +35,10 @@ void gen12_render_clearfunc(struct
> intel_bb *ibb,
>  			    struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y,
>  			    unsigned int width, unsigned int height,
>  			    const float clear_color[4]);
> +void mtl_render_copyfunc(struct intel_bb *ibb,
> +			 struct intel_buf *src, uint32_t src_x, uint32_t src_y,
> +			 uint32_t width, uint32_t height,
> +			 struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
>  void gen12p71_render_copyfunc(struct intel_bb *ibb,
>  			      struct intel_buf *src, uint32_t src_x, uint32_t src_y,
>  			      uint32_t width, uint32_t height, diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index
> 650d0950..db67b5ee 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -277,7 +277,9 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
> 
>  			ss->ss12.clear_address = (address + buf->cc.offset) >> 6;
>  			ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32;
> -		} else if (HAS_FLATCCS(ibb->devid)) {
> +		}
> +
> +		if (HAS_4TILE(ibb->devid)) {
>  			ss->ss7.dg2.memory_compression_type = 0;
>  			ss->ss7.dg2.memory_compression_enable = 0;
>  			ss->ss7.dg2.disable_support_for_multi_gpu_partial_writes = 1; @@ -1245,6 +1247,27 @@ void
> gen12p71_render_copyfunc(struct intel_bb *ibb,
>  			sizeof(gen12p71_render_copy));
>  }
> 
> +void mtl_render_copyfunc(struct intel_bb *ibb,
> +			 struct intel_buf *src,
> +			 unsigned int src_x, unsigned int src_y,
> +			 unsigned int width, unsigned int height,
> +			 struct intel_buf *dst,
> +			 unsigned int dst_x, unsigned int dst_y) {
> +	struct aux_pgtable_info pgtable_info = { };
> +
> +	gen12_aux_pgtable_init(&pgtable_info, ibb, src, dst);
> +
> +	_gen9_render_op(ibb, src, src_x, src_y,
> +			width, height, dst, dst_x, dst_y,
> +			pgtable_info.pgtable_buf,
> +			NULL,
> +			gen12p71_render_copy,
> +			sizeof(gen12p71_render_copy));
> +
> +	gen12_aux_pgtable_cleanup(ibb, &pgtable_info); }
> +
>  void gen12_render_clearfunc(struct intel_bb *ibb,
>  			    struct intel_buf *dst,
>  			    unsigned int dst_x, unsigned int dst_y, @@ -1277,3 +1300,22 @@ void
> gen12p71_render_clearfunc(struct intel_bb *ibb,
>  			gen12p71_render_copy,
>  			sizeof(gen12p71_render_copy));
>  }
> +
> +void mtl_render_clearfunc(struct intel_bb *ibb,
> +			  struct intel_buf *dst,
> +			  unsigned int dst_x, unsigned int dst_y,
> +			  unsigned int width, unsigned int height,
> +			  const float clear_color[4])
> +{
> +	struct aux_pgtable_info pgtable_info = { };
> +
> +	gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst);
> +
> +	_gen9_render_op(ibb, NULL, 0, 0,
> +			width, height, dst, dst_x, dst_y,
> +			pgtable_info.pgtable_buf,
> +			clear_color,
> +			gen12p71_render_copy,
> +			sizeof(gen12p71_render_copy));
> +	gen12_aux_pgtable_cleanup(ibb, &pgtable_info); }
> diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c index aa90939b..4ab6ced3 100644
> --- a/lib/veboxcopy_gen12.c
> +++ b/lib/veboxcopy_gen12.c
> @@ -158,13 +158,36 @@ static bool format_is_interleaved_yuv(int format)
>  	return false;
>  }
> 
> +static uint32_t compression_format(int format, struct intel_buf *buf) {
> +	if (buf->compression == I915_COMPRESSION_NONE)
> +		return 0;
> +
> +	switch (format) {
> +	case R8G8B8A8_UNORM:
> +		return 0xa;
> +	case PLANAR_420_8:
> +		return 0xf;
> +	case PLANAR_420_16:
> +		return 8;
> +	case YCRCB_NORMAL:
> +		return 3;
> +	case PACKED_444A_8:
> +		return 9;
> +	default:
> +		igt_assert(0);
> +	}
> +}
> +
>  static void emit_surface_state_cmd(struct intel_bb *ibb,
>  				   int surface_id,
> -				   int width, int height, int bpp,
> -				   int pitch, uint32_t tiling, int format,
> -				   uint32_t uv_offset)
> +				   int width, int height,
> +				   struct intel_buf *buf, int format)
>  {
>  	struct vebox_surface_state *ss;
> +	int pitch = buf->surface[0].stride;
> +	uint32_t uv_offset = buf->surface[1].offset;
> +	uint32_t tiling = buf->tiling;
> 
>  	ss = intel_bb_ptr_align(ibb, 4);
> 
> @@ -185,35 +208,16 @@ static void emit_surface_state_cmd(struct intel_bb *ibb,
> 
>  	ss->ss4.u_y_offset = uv_offset / pitch;
> 
> -	if (HAS_FLATCCS(ibb->devid)) {
> +	if (HAS_4TILE(ibb->devid)) {
>  		/*
> -		 * f-tile = 3 (Tile F)
> +		 * tile4 = 3
>  		 */
>  		ss->ss3.dg2.tile_mode = (tiling != I915_TILING_NONE) ? 3 : 0;
> 
> -		switch (format) {
> -		case R8G8B8A8_UNORM:
> -			ss->ss7.dg2.compression_format = 0xa;
> -			break;
> -		case PLANAR_420_8:
> -			ss->ss7.dg2.compression_format = 0xf;
> -			break;
> -		case PLANAR_420_16:
> -			ss->ss7.dg2.compression_format = 8;
> -			break;
> -		case YCRCB_NORMAL:
> -			ss->ss7.dg2.compression_format = 3;
> -			break;
> -		case PACKED_444A_8:
> -			ss->ss7.dg2.compression_format = 0x9;
> -			break;
> -		default:
> -			igt_assert(0);
> -		}
> +		ss->ss7.dg2.compression_format = compression_format(format, buf);
>  	} else {
>  		ss->ss3.tgl.tile_walk = (tiling == I915_TILING_Y) ||
> -			(tiling == I915_TILING_Yf) ||
> -			(tiling == I915_TILING_4);
> +			(tiling == I915_TILING_Yf);
>  		ss->ss3.tgl.tiled_surface = tiling != I915_TILING_NONE;
>  	}
> 
> @@ -246,9 +250,10 @@ static void emit_tiling_convert_cmd(struct intel_bb *ibb,
>  	}
> 
>  	if (HAS_4TILE(ibb->devid))
> -		tc->tc1_2.input_mocs_idx = 3;
> -	else
> -		tc->tc1_2.input_tiled_resource_mode = src->tiling == I915_TILING_Yf;
> +		tc->tc1_2.input_mocs_idx = IS_DG2(ibb->devid) ? 3 : 9;
> +
> +	tc->tc1_2.input_tiled_resource_mode = src->tiling == I915_TILING_Yf;
> +
>  	reloc_delta = tc->tc1_2_l;
> 
>  	igt_assert(src->addr.offset == ALIGN(src->addr.offset, 0x1000)); @@ -267,9 +272,9 @@ static void
> emit_tiling_convert_cmd(struct intel_bb *ibb,
>  	}
> 
>  	if (HAS_4TILE(ibb->devid))
> -		tc->tc3_4.output_mocs_idx = 3;
> -	else
> -		tc->tc3_4.output_tiled_resource_mode = dst->tiling == I915_TILING_Yf;
> +		tc->tc3_4.output_mocs_idx = IS_DG2(ibb->devid) ? 3 : 9;
> +
> +	tc->tc3_4.output_tiled_resource_mode = dst->tiling == I915_TILING_Yf;
> 
>  	reloc_delta = tc->tc3_4_l;
> 
> @@ -344,14 +349,12 @@ void gen12_vebox_copyfunc(struct intel_bb *ibb,
>  	igt_assert(!src->format_is_yuv_semiplanar ||
>  		   (src->surface[1].offset && dst->surface[1].offset));
>  	emit_surface_state_cmd(ibb, VEBOX_SURFACE_INPUT,
> -			       width, height, src->bpp,
> -			       src->surface[0].stride,
> -			       src->tiling, format, src->surface[1].offset);
> +			       width, height,
> +			       src, format);
> 
>  	emit_surface_state_cmd(ibb, VEBOX_SURFACE_OUTPUT,
> -			       width, height, dst->bpp,
> -			       dst->surface[0].stride,
> -			       dst->tiling, format, dst->surface[1].offset);
> +			       width, height,
> +			       dst, format);
> 
>  	emit_tiling_convert_cmd(ibb, src, dst);
> 
> --
> 2.25.1

[igt-dev] [PATCH i-g-t 3/4] tests/i915/kms_ccs: enable mtl aux ccs tests

[Juha-Pekka Heikkila]

Added
I915_FORMAT_MOD_4_TILED_MTL_RC_CCS
I915_FORMAT_MOD_4_TILED_MTL_MC_CCS
I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC
for testing.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 tests/i915/kms_ccs.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/tests/i915/kms_ccs.c b/tests/i915/kms_ccs.c
index 1b3462ea..abe464b4 100644
--- a/tests/i915/kms_ccs.c
+++ b/tests/i915/kms_ccs.c
@@ -101,6 +101,9 @@ static const struct {
 	{I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, "4_tiled_dg2_rc_ccs"},
 	{I915_FORMAT_MOD_4_TILED_DG2_MC_CCS, "4_tiled_dg2_mc_ccs"},
 	{I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC, "4_tiled_dg2_rc_ccs_cc"},
+	{I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, "4_tiled_mtl_rc_ccs"},
+	{I915_FORMAT_MOD_4_TILED_MTL_MC_CCS, "4_tiled_mtl_mc_ccs"},
+	{I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC, "4_tiled_mtl_rc_ccs_cc"},
 };
 
 static bool check_ccs_planes;
@@ -161,7 +164,8 @@ create_fb_prepare_add(int drm_fd, int width, int height,
 static bool is_ccs_cc_modifier(uint64_t modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
-		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
+	       modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC ||
+	       modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC;
 }
 
 /*
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t 3/4] tests/i915/kms_ccs: enable mtl aux ccs tests

[Kahola, Mika]

> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Juha-Pekka Heikkila
> Sent: Tuesday, May 16, 2023 6:43 PM
> To: igt-dev@lists.freedesktop.org
> Subject: [igt-dev] [PATCH i-g-t 3/4] tests/i915/kms_ccs: enable mtl aux ccs tests
> 
> Added
> I915_FORMAT_MOD_4_TILED_MTL_RC_CCS
> I915_FORMAT_MOD_4_TILED_MTL_MC_CCS
> I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC
> for testing.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
>  tests/i915/kms_ccs.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/i915/kms_ccs.c b/tests/i915/kms_ccs.c index 1b3462ea..abe464b4 100644
> --- a/tests/i915/kms_ccs.c
> +++ b/tests/i915/kms_ccs.c
> @@ -101,6 +101,9 @@ static const struct {
>  	{I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, "4_tiled_dg2_rc_ccs"},
>  	{I915_FORMAT_MOD_4_TILED_DG2_MC_CCS, "4_tiled_dg2_mc_ccs"},
>  	{I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC, "4_tiled_dg2_rc_ccs_cc"},
> +	{I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, "4_tiled_mtl_rc_ccs"},
> +	{I915_FORMAT_MOD_4_TILED_MTL_MC_CCS, "4_tiled_mtl_mc_ccs"},
> +	{I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC, "4_tiled_mtl_rc_ccs_cc"},
>  };
> 
>  static bool check_ccs_planes;
> @@ -161,7 +164,8 @@ create_fb_prepare_add(int drm_fd, int width, int height,  static bool is_ccs_cc_modifier(uint64_t
> modifier)  {
>  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> -		modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
> +	       modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC ||
> +	       modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC;
>  }
> 
>  /*
> --
> 2.25.1

[igt-dev] [PATCH i-g-t 4/4] tests/kms_getfb: Add meteorlake related ccs modifiers

[Juha-Pekka Heikkila]

Add meteorlake related ccs modifiers for getfb2-accept-ccs and
getfb-reject-ccs subtests to allow them to run without skipping.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 tests/kms_getfb.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/tests/kms_getfb.c b/tests/kms_getfb.c
index 4adc7eee..f44f4255 100644
--- a/tests/kms_getfb.c
+++ b/tests/kms_getfb.c
@@ -100,10 +100,15 @@ static void get_ccs_fb(int fd, struct drm_mode_fb_cmd2 *ret)
 		size = add.pitches[0] * ALIGN(add.height, 8);
 		size = ALIGN(size, 4096);
 	} else if ((intel_display_ver(devid)) >= 12) {
-		add.modifier[0] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
-		add.modifier[1] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+		add.modifier[0] = IS_METEORLAKE(devid) ?
+			I915_FORMAT_MOD_4_TILED_MTL_RC_CCS :
+			I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
 
-		/* The main surface for TGL is 4x4 tiles aligned
+		add.modifier[1] = IS_METEORLAKE(devid) ?
+			I915_FORMAT_MOD_4_TILED_MTL_RC_CCS :
+			I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+
+		/* The main surface for Gen12+ is 4x4 tiles aligned
 		 * For 32bpp the pitch is 4*4*32 bytes i.e. 512 bytes
 		 */
 		add.pitches[0] = ALIGN(add.width * 4, 4 * 128);
@@ -138,7 +143,7 @@ static void get_ccs_fb(int fd, struct drm_mode_fb_cmd2 *ret)
 	add.handles[0] = gem_buffer_create_fb_obj(fd, size);
 	igt_require(add.handles[0] != 0);
 
-	if (!HAS_FLATCCS(intel_get_drm_devid(fd)))
+	if (!HAS_FLATCCS(devid))
 		add.handles[1] = add.handles[0];
 
 	if (drmIoctl(fd, DRM_IOCTL_MODE_ADDFB2, &add) == 0)
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t 4/4] tests/kms_getfb: Add meteorlake related ccs modifiers

[Kahola, Mika]

> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Juha-Pekka Heikkila
> Sent: Tuesday, May 16, 2023 6:43 PM
> To: igt-dev@lists.freedesktop.org
> Subject: [igt-dev] [PATCH i-g-t 4/4] tests/kms_getfb: Add meteorlake related ccs modifiers
> 
> Add meteorlake related ccs modifiers for getfb2-accept-ccs and getfb-reject-ccs subtests to allow them to run without skipping.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
>  tests/kms_getfb.c | 13 +++++++++----
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/tests/kms_getfb.c b/tests/kms_getfb.c index 4adc7eee..f44f4255 100644
> --- a/tests/kms_getfb.c
> +++ b/tests/kms_getfb.c
> @@ -100,10 +100,15 @@ static void get_ccs_fb(int fd, struct drm_mode_fb_cmd2 *ret)
>  		size = add.pitches[0] * ALIGN(add.height, 8);
>  		size = ALIGN(size, 4096);
>  	} else if ((intel_display_ver(devid)) >= 12) {
> -		add.modifier[0] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> -		add.modifier[1] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> +		add.modifier[0] = IS_METEORLAKE(devid) ?
> +			I915_FORMAT_MOD_4_TILED_MTL_RC_CCS :
> +			I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> 
> -		/* The main surface for TGL is 4x4 tiles aligned
> +		add.modifier[1] = IS_METEORLAKE(devid) ?
> +			I915_FORMAT_MOD_4_TILED_MTL_RC_CCS :
> +			I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> +
> +		/* The main surface for Gen12+ is 4x4 tiles aligned
>  		 * For 32bpp the pitch is 4*4*32 bytes i.e. 512 bytes
>  		 */
>  		add.pitches[0] = ALIGN(add.width * 4, 4 * 128); @@ -138,7 +143,7 @@ static void get_ccs_fb(int fd, struct
> drm_mode_fb_cmd2 *ret)
>  	add.handles[0] = gem_buffer_create_fb_obj(fd, size);
>  	igt_require(add.handles[0] != 0);
> 
> -	if (!HAS_FLATCCS(intel_get_drm_devid(fd)))
> +	if (!HAS_FLATCCS(devid))
>  		add.handles[1] = add.handles[0];
> 
>  	if (drmIoctl(fd, DRM_IOCTL_MODE_ADDFB2, &add) == 0)
> --
> 2.25.1

[igt-dev] ✓ Fi.CI.BAT: success for Add Meteorlake CCS support

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3356 bytes --]

== Series Details ==

Series: Add Meteorlake CCS support
URL   : https://patchwork.freedesktop.org/series/117822/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13153 -> IGTPW_8974
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/index.html

Participating hosts (38 -> 36)
------------------------------

  Missing    (2): fi-kbl-soraka fi-snb-2520m 

Known issues
------------

  Here are the changes found in IGTPW_8974 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@load:
    - bat-adls-5:         [PASS][1] -> [ABORT][2] ([i915#4391])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/bat-adls-5/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/bat-adls-5/igt@i915_module_load@load.html

  * igt@i915_pm_backlight@basic-brightness@edp-1:
    - bat-rplp-1:         NOTRUN -> [ABORT][3] ([i915#7077])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/bat-rplp-1/igt@i915_pm_backlight@basic-brightness@edp-1.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@basic-rte:
    - {bat-mtlp-8}:       [DMESG-WARN][4] -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/bat-mtlp-8/igt@i915_pm_rpm@basic-rte.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/bat-mtlp-8/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@migrate:
    - bat-dg2-11:         [DMESG-WARN][6] ([i915#7699]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/bat-dg2-11/igt@i915_selftest@live@migrate.html

  
#### Warnings ####

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-rplp-1:         [ABORT][8] ([i915#4579] / [i915#8260]) -> [SKIP][9] ([i915#3555] / [i915#4579])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7292 -> IGTPW_8974

  CI-20190529: 20190529
  CI_DRM_13153: 1ceecfa94dd4a059164b23925aecc9db4c4fd3b6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8974: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/index.html
  IGT_7292: 9d9475ffd3b5ae18fd8ec120595385f6c562f249 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+++ 216 lines
--- 0 lines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/index.html

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[igt-dev] ✓ Fi.CI.IGT: success for Add Meteorlake CCS support

[Patchwork]

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== Series Details ==

Series: Add Meteorlake CCS support
URL   : https://patchwork.freedesktop.org/series/117822/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13153_full -> IGTPW_8974_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/index.html

Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts

New tests
---------

  New tests have been introduced between CI_DRM_13153_full and IGTPW_8974_full:

### New IGT tests (108) ###

  * igt@kms_ccs@pipe-a-bad-aux-stride-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-bad-aux-stride-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-bad-aux-stride-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_mtl_rc_ccs:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_mc_ccs:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-bad-aux-stride-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-bad-aux-stride-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-bad-aux-stride-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_mtl_mc_ccs:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_mtl_rc_ccs:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-bad-aux-stride-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-bad-aux-stride-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-bad-aux-stride-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-bad-aux-stride-4_tiled_mtl_mc_ccs:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-bad-aux-stride-4_tiled_mtl_rc_ccs:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-bad-aux-stride-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_mtl_rc_ccs:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_mc_ccs:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-ccs-on-another-bo-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-ccs-on-another-bo-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_mtl_mc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_mtl_rc_ccs:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_mtl_rc_ccs_cc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_8974_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_mm@all-tests:
    - shard-snb:          NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4579]) +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-snb4/igt@drm_mm@all-tests.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][2] ([i915#2842])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-glk8/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-glk:          [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-glk6/igt@gem_exec_fair@basic-pace@vcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-glk6/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-glk:          NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-glk2/igt@gem_huc_copy@huc-copy.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - shard-snb:          [PASS][6] -> [ABORT][7] ([i915#4528] / [i915#8189] / [i915#8213])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-snb6/igt@i915_suspend@basic-s2idle-without-i915.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-snb7/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886]) +3 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-glk3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
    - shard-snb:          NOTRUN -> [SKIP][9] ([fdo#109271]) +155 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-snb7/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * {igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_rc_ccs} (NEW):
    - {shard-dg1}:        NOTRUN -> [SKIP][10] ([i915#5354]) +107 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-dg1-17/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_rc_ccs.html

  * {igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_mtl_rc_ccs} (NEW):
    - {shard-tglu}:       NOTRUN -> [SKIP][11] ([i915#5354]) +104 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-tglu-7/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_mtl_rc_ccs.html

  * {igt@kms_ccs@pipe-d-bad-aux-stride-4_tiled_mtl_mc_ccs} (NEW):
    - shard-glk:          NOTRUN -> [SKIP][12] ([fdo#109271]) +182 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-glk3/igt@kms_ccs@pipe-d-bad-aux-stride-4_tiled_mtl_mc_ccs.html

  * {igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_mc_ccs} (NEW):
    - shard-apl:          NOTRUN -> [SKIP][13] ([fdo#109271]) +110 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-apl2/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_mc_ccs.html

  * {igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_mc_ccs} (NEW):
    - {shard-rkl}:        NOTRUN -> [SKIP][14] ([i915#5354]) +104 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-rkl-2/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_mc_ccs.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          NOTRUN -> [FAIL][15] ([i915#2346])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][16] ([i915#4573]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-glk1/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-glk:          NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-glk3/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-glk:          NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4579]) +9 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-glk9/igt@kms_scaling_modes@scaling-mode-full.html

  
#### Possible fixes ####

  * igt@device_reset@unbind-reset-rebind:
    - {shard-rkl}:        [ABORT][19] ([i915#5507]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-rkl-2/igt@device_reset@unbind-reset-rebind.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-rkl-3/igt@device_reset@unbind-reset-rebind.html
    - shard-apl:          [ABORT][21] ([i915#5507]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-apl1/igt@device_reset@unbind-reset-rebind.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-apl4/igt@device_reset@unbind-reset-rebind.html
    - {shard-tglu}:       [ABORT][23] ([i915#5507]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-tglu-3/igt@device_reset@unbind-reset-rebind.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-tglu-2/igt@device_reset@unbind-reset-rebind.html

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
    - {shard-rkl}:        [FAIL][25] ([i915#7742]) -> [PASS][26] +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html

  * igt@gem_ctx_freq@sysfs:
    - {shard-dg1}:        [FAIL][27] ([i915#6786]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-dg1-12/igt@gem_ctx_freq@sysfs.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-dg1-14/igt@gem_ctx_freq@sysfs.html

  * igt@gem_eio@kms:
    - {shard-dg1}:        [FAIL][29] ([i915#5784]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-dg1-18/igt@gem_eio@kms.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-dg1-17/igt@gem_eio@kms.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][31] ([i915#2842]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - {shard-rkl}:        [FAIL][33] ([i915#2842]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-rkl-7/igt@gem_exec_fair@basic-pace@rcs0.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-rkl-4/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_ppgtt@blt-vs-render-ctx0:
    - shard-snb:          [DMESG-FAIL][35] ([i915#8295]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctx0.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-snb4/igt@gem_ppgtt@blt-vs-render-ctx0.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-apl:          [SKIP][37] ([fdo#109271]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-apl1/igt@i915_pm_dc@dc9-dpms.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-apl6/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rc6_residency@rc6-idle@vecs0:
    - {shard-dg1}:        [FAIL][39] ([i915#3591]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [INCOMPLETE][41] ([i915#7790]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13153/shard-snb2/igt@i915_pm_rps@reset.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/shard-snb6/igt@i915_pm_rps@reset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5507]: https://gitlab.freedesktop.org/drm/intel/issues/5507
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6786]: https://gitlab.freedesktop.org/drm/intel/issues/6786
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
  [i915#8189]: https://gitlab.freedesktop.org/drm/intel/issues/8189
  [i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
  [i915#8295]: https://gitlab.freedesktop.org/drm/intel/issues/8295


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7292 -> IGTPW_8974
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_13153: 1ceecfa94dd4a059164b23925aecc9db4c4fd3b6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8974: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/index.html
  IGT_7292: 9d9475ffd3b5ae18fd8ec120595385f6c562f249 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8974/index.html

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