* [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands
@ 2023-09-26 12:27 sai.gowtham.ch
2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add check to see if blt commands are supported by the platforms sai.gowtham.ch
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: sai.gowtham.ch @ 2023-09-26 12:27 UTC (permalink / raw)
To: igt-dev, karolina.stolarek, Zbigniew.Kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Add copy basic test which exercies mem-se and mem-copy commands, this
patch series involves in following changes:
1. Add copy basic test to exercise blt commands.
2. check if blt commands are supported by the platforms.
3. Add wrappers for batch preparation and submit exec.
3. Add copy commands to blt_cmd_type.
4. Add copy commands MEM_SET_CMD and MEM_COPY_CMD in the lib.
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Sai Gowtham Ch (3):
lib/intel_blt: Add check to see if blt commands are supported by the
platforms
lib/intel_blt: Add wrappers to prepare batch buffers and submit exec
intel/xe_copy_basic: Add copy basic test to exercise blt commands
lib/intel_blt.c | 237 ++++++++++++++++++++++++++++++++++++
lib/intel_blt.h | 45 +++++++
lib/intel_cmds_info.c | 12 ++
lib/intel_cmds_info.h | 7 ++
lib/intel_reg.h | 4 +
tests/intel/xe_copy_basic.c | 206 +++++++++++++++++++++++++++++++
tests/meson.build | 1 +
7 files changed, 512 insertions(+)
create mode 100644 tests/intel/xe_copy_basic.c
--
2.39.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add check to see if blt commands are supported by the platforms 2023-09-26 12:27 [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands sai.gowtham.ch @ 2023-09-26 12:27 ` sai.gowtham.ch 2023-09-27 11:22 ` Zbigniew Kempczyński 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec sai.gowtham.ch ` (4 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: sai.gowtham.ch @ 2023-09-26 12:27 UTC (permalink / raw) To: igt-dev, karolina.stolarek, Zbigniew.Kempczynski, sai.gowtham.ch From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> This commit has following changes: 1. Add check to see if blt commands are supported by the platforms. 2. Add MEM_COPY and MEM_SET instructions 3. Update cmd info for MEM_COPY and MEM_SET 4. Add copy type used for MEM_COPY and MEM_SET. Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> --- lib/intel_blt.c | 32 ++++++++++++++++++++++++++++++++ lib/intel_blt.h | 2 ++ lib/intel_cmds_info.c | 12 ++++++++++++ lib/intel_cmds_info.h | 7 +++++++ 4 files changed, 53 insertions(+) diff --git a/lib/intel_blt.c b/lib/intel_blt.c index 429511920..b55fa9b52 100644 --- a/lib/intel_blt.c +++ b/lib/intel_blt.c @@ -289,6 +289,38 @@ bool blt_has_block_copy(int fd) return blt_supports_command(cmds_info, XY_BLOCK_COPY); } +/** + * blt_has_mem_copy + * @fd: drm fd + * + * Check if mem copy is supported by @fd device + * + * Returns: + * true if it does, false otherwise. + */ +bool blt_has_mem_copy(int fd) +{ + const struct intel_cmds_info *cmds_info = GET_CMDS_INFO(fd); + + return blt_supports_command(cmds_info, MEM_COPY); +} + +/** + * blt_has_mem_set + * @fd: drm fd + * + * Check if mem set is supported by @fd device + * + * Returns: + * true if it does, false otherwise. + */ +bool blt_has_mem_set(int fd) +{ + const struct intel_cmds_info *cmds_info = GET_CMDS_INFO(fd); + + return blt_supports_command(cmds_info, MEM_SET); +} + /** * blt_has_fast_copy * @fd: drm fd diff --git a/lib/intel_blt.h b/lib/intel_blt.h index b8b3d724d..d9c8883c7 100644 --- a/lib/intel_blt.h +++ b/lib/intel_blt.h @@ -175,6 +175,8 @@ bool blt_cmd_has_property(const struct intel_cmds_info *cmds_info, uint32_t prop); bool blt_has_block_copy(int fd); +bool blt_has_mem_copy(int fd); +bool blt_has_mem_set(int fd); bool blt_has_fast_copy(int fd); bool blt_has_xy_src_copy(int fd); bool blt_has_xy_color(int fd); diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c index 366b37f2c..2e51ec081 100644 --- a/lib/intel_cmds_info.c +++ b/lib/intel_cmds_info.c @@ -82,6 +82,16 @@ static const struct blt_cmd_info BIT(T_TILE64), BLT_CMD_EXTENDED); +static const struct blt_cmd_info + pvc_mem_copy = BLT_INFO(MEM_COPY, + BIT(M_LINEAR) | + BIT(M_MATRIX)); + +static const struct blt_cmd_info + pvc_mem_set = BLT_INFO(MEM_SET, + BIT(M_LINEAR) | + BIT(M_MATRIX)); + static const struct blt_cmd_info pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT, BIT(T_LINEAR) | @@ -154,6 +164,8 @@ const struct intel_cmds_info gen12_pvc_cmds_info = { .blt_cmds = { [XY_FAST_COPY] = &pvc_xy_fast_copy, [XY_BLOCK_COPY] = &pvc_xy_block_copy, + [MEM_COPY] = &pvc_mem_copy, + [MEM_SET] = &pvc_mem_set, } }; diff --git a/lib/intel_cmds_info.h b/lib/intel_cmds_info.h index 91d0f15ec..7396215e3 100644 --- a/lib/intel_cmds_info.h +++ b/lib/intel_cmds_info.h @@ -18,8 +18,15 @@ enum blt_tiling_type { __BLT_MAX_TILING }; +enum blt_copy_type { + M_LINEAR, + M_MATRIX, +}; + enum blt_cmd_type { SRC_COPY, + MEM_SET, + MEM_COPY, XY_SRC_COPY, XY_FAST_COPY, XY_BLOCK_COPY, -- 2.39.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add check to see if blt commands are supported by the platforms 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add check to see if blt commands are supported by the platforms sai.gowtham.ch @ 2023-09-27 11:22 ` Zbigniew Kempczyński 0 siblings, 0 replies; 13+ messages in thread From: Zbigniew Kempczyński @ 2023-09-27 11:22 UTC (permalink / raw) To: sai.gowtham.ch; +Cc: igt-dev On Tue, Sep 26, 2023 at 05:57:47PM +0530, sai.gowtham.ch@intel.com wrote: > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> > > This commit has following changes: > > 1. Add check to see if blt commands are supported by the platforms. > 2. Add MEM_COPY and MEM_SET instructions > 3. Update cmd info for MEM_COPY and MEM_SET > 4. Add copy type used for MEM_COPY and MEM_SET. > > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> > --- > lib/intel_blt.c | 32 ++++++++++++++++++++++++++++++++ > lib/intel_blt.h | 2 ++ > lib/intel_cmds_info.c | 12 ++++++++++++ > lib/intel_cmds_info.h | 7 +++++++ > 4 files changed, 53 insertions(+) > > diff --git a/lib/intel_blt.c b/lib/intel_blt.c > index 429511920..b55fa9b52 100644 > --- a/lib/intel_blt.c > +++ b/lib/intel_blt.c > @@ -289,6 +289,38 @@ bool blt_has_block_copy(int fd) > return blt_supports_command(cmds_info, XY_BLOCK_COPY); > } > > +/** > + * blt_has_mem_copy > + * @fd: drm fd > + * > + * Check if mem copy is supported by @fd device > + * > + * Returns: > + * true if it does, false otherwise. > + */ > +bool blt_has_mem_copy(int fd) > +{ > + const struct intel_cmds_info *cmds_info = GET_CMDS_INFO(fd); > + > + return blt_supports_command(cmds_info, MEM_COPY); > +} > + > +/** > + * blt_has_mem_set > + * @fd: drm fd > + * > + * Check if mem set is supported by @fd device > + * > + * Returns: > + * true if it does, false otherwise. > + */ > +bool blt_has_mem_set(int fd) > +{ > + const struct intel_cmds_info *cmds_info = GET_CMDS_INFO(fd); > + > + return blt_supports_command(cmds_info, MEM_SET); > +} > + > /** > * blt_has_fast_copy > * @fd: drm fd > diff --git a/lib/intel_blt.h b/lib/intel_blt.h > index b8b3d724d..d9c8883c7 100644 > --- a/lib/intel_blt.h > +++ b/lib/intel_blt.h > @@ -175,6 +175,8 @@ bool blt_cmd_has_property(const struct intel_cmds_info *cmds_info, > uint32_t prop); > > bool blt_has_block_copy(int fd); > +bool blt_has_mem_copy(int fd); > +bool blt_has_mem_set(int fd); > bool blt_has_fast_copy(int fd); > bool blt_has_xy_src_copy(int fd); > bool blt_has_xy_color(int fd); > diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c > index 366b37f2c..2e51ec081 100644 > --- a/lib/intel_cmds_info.c > +++ b/lib/intel_cmds_info.c > @@ -82,6 +82,16 @@ static const struct blt_cmd_info > BIT(T_TILE64), > BLT_CMD_EXTENDED); > > +static const struct blt_cmd_info > + pvc_mem_copy = BLT_INFO(MEM_COPY, > + BIT(M_LINEAR) | > + BIT(M_MATRIX)); You've decided to pack blt_copy_type to .supported_tiling. I can accept that conditionally (unless someone else will complain). > + > +static const struct blt_cmd_info > + pvc_mem_set = BLT_INFO(MEM_SET, > + BIT(M_LINEAR) | > + BIT(M_MATRIX)); > + > static const struct blt_cmd_info > pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT, > BIT(T_LINEAR) | > @@ -154,6 +164,8 @@ const struct intel_cmds_info gen12_pvc_cmds_info = { > .blt_cmds = { > [XY_FAST_COPY] = &pvc_xy_fast_copy, > [XY_BLOCK_COPY] = &pvc_xy_block_copy, > + [MEM_COPY] = &pvc_mem_copy, > + [MEM_SET] = &pvc_mem_set, > } > }; > > diff --git a/lib/intel_cmds_info.h b/lib/intel_cmds_info.h > index 91d0f15ec..7396215e3 100644 > --- a/lib/intel_cmds_info.h > +++ b/lib/intel_cmds_info.h > @@ -18,8 +18,15 @@ enum blt_tiling_type { > __BLT_MAX_TILING > }; > > +enum blt_copy_type { > + M_LINEAR, > + M_MATRIX, > +}; I would rather call this 'blt_memop_type'. With above minor fixed: Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> -- Zbigniew > + > enum blt_cmd_type { > SRC_COPY, > + MEM_SET, > + MEM_COPY, > XY_SRC_COPY, > XY_FAST_COPY, > XY_BLOCK_COPY, > -- > 2.39.1 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 2/3] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec 2023-09-26 12:27 [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands sai.gowtham.ch 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add check to see if blt commands are supported by the platforms sai.gowtham.ch @ 2023-09-26 12:27 ` sai.gowtham.ch 2023-09-27 11:36 ` Zbigniew Kempczyński 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: Add copy basic test to exercise blt commands sai.gowtham.ch ` (3 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: sai.gowtham.ch @ 2023-09-26 12:27 UTC (permalink / raw) To: igt-dev, karolina.stolarek, Zbigniew.Kempczynski, sai.gowtham.ch From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Adding wrapper for mem-set and mem-copy instructions to prepare batch buffers and submit exec, (blt_mem_copy, blt_set_mem, emit_blt_mem_copy, emit,blt_set_mem) Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> --- lib/intel_blt.c | 205 ++++++++++++++++++++++++++++++++++++++++++++++++ lib/intel_blt.h | 43 ++++++++++ lib/intel_reg.h | 4 + 3 files changed, 252 insertions(+) diff --git a/lib/intel_blt.c b/lib/intel_blt.c index b55fa9b52..99c01265b 100644 --- a/lib/intel_blt.c +++ b/lib/intel_blt.c @@ -13,12 +13,14 @@ #include "igt.h" #include "igt_syncobj.h" #include "intel_blt.h" +#include "intel_mocs.h" #include "xe/xe_ioctl.h" #include "xe/xe_query.h" #include "xe/xe_util.h" #define BITRANGE(start, end) (end - start + 1) #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd)) +#define MEM_COPY_MOCS_SHIFT 25 /* Blitter tiling definitions sanity checks */ static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have to match"); @@ -778,6 +780,14 @@ void blt_copy_init(int fd, struct blt_copy_data *blt) blt->driver = get_intel_driver(fd); } +void blt_mem_init(int fd, struct blt_mem_data *mem) +{ + memset(mem, 0, sizeof(*mem)); + + mem->fd = fd; + mem->driver = get_intel_driver(fd); +} + /** * emit_blt_block_copy: * @fd: drm fd @@ -1412,6 +1422,188 @@ int blt_fast_copy(int fd, return ret; } +void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem, uint32_t col_size) +{ + uint64_t dst_offset, src_offset, alignment; + int i; + uint8_t src_mocs = intel_get_uc_mocs(fd); + uint8_t dst_mocs = src_mocs; + uint32_t size; + struct { + uint32_t batch[12]; + uint32_t data; + } *data; + + alignment = get_default_alignment(fd, mem->driver); + src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment); + dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment); + size = mem->src.size; + + data = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver); + + i = 0; + data->batch[i++] = MEM_COPY_CMD; + data->batch[i++] = size - 1; + data->batch[i++] = col_size - 1; + data->batch[i++] = 0; + data->batch[i++] = 0; + data->batch[i++] = src_offset; + data->batch[i++] = src_offset << 32; + data->batch[i++] = dst_offset; + data->batch[i++] = dst_offset << 32; + data->batch[i++] = src_mocs << MEM_COPY_MOCS_SHIFT | dst_mocs; + data->batch[i++] = MI_BATCH_BUFFER_END; + data->batch[i++] = MI_NOOP; + + igt_assert(i <= ARRAY_SIZE(data->batch)); + + munmap(data, mem->bb.size); +} + +/** + * blt_mem_copy: + * @fd: drm fd + * @ctx: intel_ctx_t context + * @e: blitter engine for @ctx + * @ahnd: allocator handle + * @blt: blitter data for mem-copy. + * + * Function does mem blit between @src and @dst described in @blt object. + * + * Returns: + * execbuffer status. + */ +int blt_mem_copy(int fd, const intel_ctx_t *ctx, + const struct intel_execution_engine2 *e, + uint64_t ahnd, + const struct blt_mem_data *mem, + uint32_t col_size) +{ + struct drm_i915_gem_execbuffer2 execbuf = {}; + struct drm_i915_gem_exec_object2 obj[3] = {}; + uint64_t dst_offset, src_offset, bb_offset, alignment; + int ret; + + alignment = get_default_alignment(fd, mem->driver); + src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment); + dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment); + bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment); + + emit_blt_mem_copy(fd, ahnd, mem, col_size); + + if (mem->driver == INTEL_DRIVER_XE) { + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); + } else { + obj[0].offset = CANONICAL(dst_offset); + obj[1].offset = CANONICAL(src_offset); + obj[2].offset = CANONICAL(bb_offset); + obj[0].handle = mem->dst.handle; + obj[1].handle = mem->src.handle; + obj[2].handle = mem->bb.handle; + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + execbuf.buffer_count = 3; + execbuf.buffers_ptr = to_user_pointer(obj); + execbuf.rsvd1 = ctx ? ctx->id : 0; + execbuf.flags = e ? e->flags : I915_EXEC_BLT; + ret = __gem_execbuf(fd, &execbuf); + put_offset(ahnd, mem->dst.handle); + put_offset(ahnd, mem->src.handle); + put_offset(ahnd, mem->bb.handle); + } + + return ret; +} + +void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem, + uint32_t fill_data, uint32_t height) +{ + uint64_t dst_offset, alignment; + int b; + uint8_t dst_mocs = intel_get_uc_mocs(fd); + uint32_t size; + struct { + uint32_t batch[12]; + uint32_t data; + } *data; + + alignment = get_default_alignment(fd, mem->driver); + dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment); + size = mem->dst.size; + + data = bo_map(fd, mem->dst.handle, mem->dst.size, mem->driver); + + b = 0; + data->batch[b++] = MEM_SET_CMD; + data->batch[b++] = size - 1; + data->batch[b++] = height; + data->batch[b++] = 0; + data->batch[b++] = dst_offset; + data->batch[b++] = dst_offset << 32; + data->batch[b++] = (fill_data << 24) | dst_mocs; + data->batch[b++] = MI_BATCH_BUFFER_END; + data->batch[b++] = MI_NOOP; + + igt_assert(b <= ARRAY_SIZE(data->batch)); + + munmap(data, mem->bb.size); +} + +/** + * blt_mem_set: + * @fd: drm fd + * @ctx: intel_ctx_t context + * @e: blitter engine for @ctx + * @ahnd: allocator handle + * @blt: blitter data for mem-set. + * + * Function does mem set blit in described @blt object. + * + * Returns: + * execbuffer status. + */ +int blt_mem_set(int fd, const intel_ctx_t *ctx, + const struct intel_execution_engine2 *e, + uint64_t ahnd, + const struct blt_mem_data *mem, + uint32_t height, + uint32_t fill_data) +{ + struct drm_i915_gem_execbuffer2 execbuf = {}; + struct drm_i915_gem_exec_object2 obj[2] = {}; + uint64_t dst_offset, bb_offset, alignment; + int ret; + + alignment = get_default_alignment(fd, mem->driver); + dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment); + bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment); + + emit_blt_mem_set(fd, ahnd, mem, fill_data, height); + + if (mem->driver == INTEL_DRIVER_XE) { + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); + } else { + obj[0].offset = CANONICAL(dst_offset); + obj[1].offset = CANONICAL(bb_offset); + obj[0].handle = mem->dst.handle; + obj[1].handle = mem->bb.handle; + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + execbuf.buffer_count = 2; + execbuf.buffers_ptr = to_user_pointer(obj); + execbuf.rsvd1 = ctx ? ctx->id : 0; + execbuf.flags = e ? e->flags : I915_EXEC_BLT; + ret = __gem_execbuf(fd, &execbuf); + put_offset(ahnd, mem->dst.handle); + put_offset(ahnd, mem->bb.handle); + } + + return ret; +} + void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t x_offset, uint16_t y_offset) @@ -1494,6 +1686,19 @@ void blt_set_object(struct blt_copy_object *obj, obj->compression_type = compression_type; } +void blt_set_mem_object(struct blt_mem_object *obj, + uint32_t handle, uint64_t size, uint32_t region, + uint8_t mocs, enum blt_copy_type type, + enum blt_compression compression) +{ + obj->handle = handle; + obj->region = region; + obj->size = size; + obj->mocs = mocs; + obj->type = type; + obj->compression = compression; +} + void blt_set_object_ext(struct blt_block_copy_object_ext *obj, uint8_t compression_format, uint16_t surface_width, uint16_t surface_height, diff --git a/lib/intel_blt.h b/lib/intel_blt.h index d9c8883c7..d10ec954a 100644 --- a/lib/intel_blt.h +++ b/lib/intel_blt.h @@ -93,6 +93,17 @@ struct blt_copy_object { uint32_t plane_offset; }; +struct blt_mem_object { + uint32_t handle; + uint32_t region; + uint64_t size; + uint8_t mocs; + enum blt_copy_type type; + enum blt_compression compression; + uint32_t pitch; + uint32_t *ptr; +}; + struct blt_copy_batch { uint32_t handle; uint32_t region; @@ -112,6 +123,14 @@ struct blt_copy_data { bool print_bb; }; +struct blt_mem_data { + int fd; + enum intel_driver driver; + struct blt_mem_object src; + struct blt_mem_object dst; + struct blt_copy_batch bb; +}; + enum blt_surface_type { SURFACE_TYPE_1D, SURFACE_TYPE_2D, @@ -190,6 +209,7 @@ bool blt_uses_extended_block_copy(int fd); const char *blt_tiling_name(enum blt_tiling_type tiling); void blt_copy_init(int fd, struct blt_copy_data *blt); +void blt_mem_init(int fd, struct blt_mem_data *mem); uint64_t emit_blt_block_copy(int fd, uint64_t ahnd, @@ -231,6 +251,23 @@ int blt_fast_copy(int fd, uint64_t ahnd, const struct blt_copy_data *blt); +void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem, + uint32_t col_size); + +int blt_mem_copy(int fd, const intel_ctx_t *ctx, + const struct intel_execution_engine2 *e, + uint64_t ahnd, + const struct blt_mem_data *mem, + uint32_t col_size); + +void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem, + uint32_t fill_data, uint32_t height); + +int blt_mem_set(int fd, const intel_ctx_t *ctx, + const struct intel_execution_engine2 *e, uint64_t ahnd, + const struct blt_mem_data *mem, uint32_t height, + uint32_t fill_data); + void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t x_offset, uint16_t y_offset); @@ -250,6 +287,12 @@ void blt_set_object(struct blt_copy_object *obj, uint8_t mocs, enum blt_tiling_type tiling, enum blt_compression compression, enum blt_compression_type compression_type); + +void blt_set_mem_object(struct blt_mem_object *obj, + uint32_t handle, uint64_t size, uint32_t region, + uint8_t mocs, enum blt_copy_type type, + enum blt_compression compression); + void blt_set_object_ext(struct blt_block_copy_object_ext *obj, uint8_t compression_format, uint16_t surface_width, uint16_t surface_height, diff --git a/lib/intel_reg.h b/lib/intel_reg.h index 3bf3676dc..eb65da911 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -2586,6 +2586,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define XY_FAST_COPY_COLOR_DEPTH_64 (4 << 24) #define XY_FAST_COPY_COLOR_DEPTH_128 (5 << 24) +/* RAW memory commands */ +#define MEM_COPY_CMD ((0x2 << 29)|(0x5a << 22)|0x8) +#define MEM_SET_CMD ((0x2 << 29)|(0x5b << 22)|0x5) + #define CTXT_NO_RESTORE (1) #define CTXT_PALETTE_SAVE_DISABLE (1<<3) #define CTXT_PALETTE_RESTORE_DISABLE (1<<2) -- 2.39.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/3] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec sai.gowtham.ch @ 2023-09-27 11:36 ` Zbigniew Kempczyński 0 siblings, 0 replies; 13+ messages in thread From: Zbigniew Kempczyński @ 2023-09-27 11:36 UTC (permalink / raw) To: sai.gowtham.ch; +Cc: igt-dev On Tue, Sep 26, 2023 at 05:57:48PM +0530, sai.gowtham.ch@intel.com wrote: > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> > > Adding wrapper for mem-set and mem-copy instructions to prepare > batch buffers and submit exec, (blt_mem_copy, blt_set_mem, > emit_blt_mem_copy, emit,blt_set_mem) > > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> > --- > lib/intel_blt.c | 205 ++++++++++++++++++++++++++++++++++++++++++++++++ > lib/intel_blt.h | 43 ++++++++++ > lib/intel_reg.h | 4 + > 3 files changed, 252 insertions(+) > > diff --git a/lib/intel_blt.c b/lib/intel_blt.c > index b55fa9b52..99c01265b 100644 > --- a/lib/intel_blt.c > +++ b/lib/intel_blt.c > @@ -13,12 +13,14 @@ > #include "igt.h" > #include "igt_syncobj.h" > #include "intel_blt.h" > +#include "intel_mocs.h" > #include "xe/xe_ioctl.h" > #include "xe/xe_query.h" > #include "xe/xe_util.h" > > #define BITRANGE(start, end) (end - start + 1) > #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd)) > +#define MEM_COPY_MOCS_SHIFT 25 > > /* Blitter tiling definitions sanity checks */ > static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have to match"); > @@ -778,6 +780,14 @@ void blt_copy_init(int fd, struct blt_copy_data *blt) > blt->driver = get_intel_driver(fd); > } > > +void blt_mem_init(int fd, struct blt_mem_data *mem) > +{ > + memset(mem, 0, sizeof(*mem)); > + > + mem->fd = fd; > + mem->driver = get_intel_driver(fd); > +} > + > /** > * emit_blt_block_copy: > * @fd: drm fd > @@ -1412,6 +1422,188 @@ int blt_fast_copy(int fd, > return ret; > } > > +void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem, uint32_t col_size) > +{ > + uint64_t dst_offset, src_offset, alignment; > + int i; > + uint8_t src_mocs = intel_get_uc_mocs(fd); > + uint8_t dst_mocs = src_mocs; > + uint32_t size; > + struct { > + uint32_t batch[12]; > + uint32_t data; > + } *data; What for you need this one? Just use: uint32_t *batch; > + > + alignment = get_default_alignment(fd, mem->driver); > + src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment); > + dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment); > + size = mem->src.size; > + > + data = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver); and map it here. > + > + i = 0; > + data->batch[i++] = MEM_COPY_CMD; > + data->batch[i++] = size - 1; > + data->batch[i++] = col_size - 1; > + data->batch[i++] = 0; > + data->batch[i++] = 0; > + data->batch[i++] = src_offset; > + data->batch[i++] = src_offset << 32; > + data->batch[i++] = dst_offset; > + data->batch[i++] = dst_offset << 32; > + data->batch[i++] = src_mocs << MEM_COPY_MOCS_SHIFT | dst_mocs; > + data->batch[i++] = MI_BATCH_BUFFER_END; > + data->batch[i++] = MI_NOOP; MI_NOOP is not necessary at the end. BTW I got hang with above. Leaving BBE it is executing so something wrong is with MEM_COPY_CMD itself. > + > + igt_assert(i <= ARRAY_SIZE(data->batch)); > + > + munmap(data, mem->bb.size); > +} > + > +/** > + * blt_mem_copy: > + * @fd: drm fd > + * @ctx: intel_ctx_t context > + * @e: blitter engine for @ctx > + * @ahnd: allocator handle > + * @blt: blitter data for mem-copy. > + * > + * Function does mem blit between @src and @dst described in @blt object. > + * > + * Returns: > + * execbuffer status. > + */ > +int blt_mem_copy(int fd, const intel_ctx_t *ctx, > + const struct intel_execution_engine2 *e, > + uint64_t ahnd, > + const struct blt_mem_data *mem, > + uint32_t col_size) > +{ > + struct drm_i915_gem_execbuffer2 execbuf = {}; > + struct drm_i915_gem_exec_object2 obj[3] = {}; > + uint64_t dst_offset, src_offset, bb_offset, alignment; > + int ret; > + > + alignment = get_default_alignment(fd, mem->driver); > + src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment); > + dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment); > + bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment); > + > + emit_blt_mem_copy(fd, ahnd, mem, col_size); > + > + if (mem->driver == INTEL_DRIVER_XE) { > + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); > + } else { > + obj[0].offset = CANONICAL(dst_offset); > + obj[1].offset = CANONICAL(src_offset); > + obj[2].offset = CANONICAL(bb_offset); > + obj[0].handle = mem->dst.handle; > + obj[1].handle = mem->src.handle; > + obj[2].handle = mem->bb.handle; > + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + execbuf.buffer_count = 3; > + execbuf.buffers_ptr = to_user_pointer(obj); > + execbuf.rsvd1 = ctx ? ctx->id : 0; > + execbuf.flags = e ? e->flags : I915_EXEC_BLT; > + ret = __gem_execbuf(fd, &execbuf); > + put_offset(ahnd, mem->dst.handle); > + put_offset(ahnd, mem->src.handle); > + put_offset(ahnd, mem->bb.handle); > + } > + > + return ret; > +} > + > +void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem, > + uint32_t fill_data, uint32_t height) > +{ > + uint64_t dst_offset, alignment; > + int b; > + uint8_t dst_mocs = intel_get_uc_mocs(fd); > + uint32_t size; > + struct { > + uint32_t batch[12]; > + uint32_t data; > + } *data; Same here (uint32_t *batch). > + > + alignment = get_default_alignment(fd, mem->driver); > + dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment); > + size = mem->dst.size; > + > + data = bo_map(fd, mem->dst.handle, mem->dst.size, mem->driver); Definitely you're not mapping correct object. I'll back to the review with your new series when mem-copy/set will start to work. -- Zbigniew > + > + b = 0; > + data->batch[b++] = MEM_SET_CMD; > + data->batch[b++] = size - 1; > + data->batch[b++] = height; > + data->batch[b++] = 0; > + data->batch[b++] = dst_offset; > + data->batch[b++] = dst_offset << 32; > + data->batch[b++] = (fill_data << 24) | dst_mocs; > + data->batch[b++] = MI_BATCH_BUFFER_END; > + data->batch[b++] = MI_NOOP; > + > + igt_assert(b <= ARRAY_SIZE(data->batch)); > + > + munmap(data, mem->bb.size); > +} > + > +/** > + * blt_mem_set: > + * @fd: drm fd > + * @ctx: intel_ctx_t context > + * @e: blitter engine for @ctx > + * @ahnd: allocator handle > + * @blt: blitter data for mem-set. > + * > + * Function does mem set blit in described @blt object. > + * > + * Returns: > + * execbuffer status. > + */ > +int blt_mem_set(int fd, const intel_ctx_t *ctx, > + const struct intel_execution_engine2 *e, > + uint64_t ahnd, > + const struct blt_mem_data *mem, > + uint32_t height, > + uint32_t fill_data) > +{ > + struct drm_i915_gem_execbuffer2 execbuf = {}; > + struct drm_i915_gem_exec_object2 obj[2] = {}; > + uint64_t dst_offset, bb_offset, alignment; > + int ret; > + > + alignment = get_default_alignment(fd, mem->driver); > + dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment); > + bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment); > + > + emit_blt_mem_set(fd, ahnd, mem, fill_data, height); > + > + if (mem->driver == INTEL_DRIVER_XE) { > + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); > + } else { > + obj[0].offset = CANONICAL(dst_offset); > + obj[1].offset = CANONICAL(bb_offset); > + obj[0].handle = mem->dst.handle; > + obj[1].handle = mem->bb.handle; > + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + execbuf.buffer_count = 2; > + execbuf.buffers_ptr = to_user_pointer(obj); > + execbuf.rsvd1 = ctx ? ctx->id : 0; > + execbuf.flags = e ? e->flags : I915_EXEC_BLT; > + ret = __gem_execbuf(fd, &execbuf); > + put_offset(ahnd, mem->dst.handle); > + put_offset(ahnd, mem->bb.handle); > + } > + > + return ret; > +} > + > void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch, > int16_t x1, int16_t y1, int16_t x2, int16_t y2, > uint16_t x_offset, uint16_t y_offset) > @@ -1494,6 +1686,19 @@ void blt_set_object(struct blt_copy_object *obj, > obj->compression_type = compression_type; > } > > +void blt_set_mem_object(struct blt_mem_object *obj, > + uint32_t handle, uint64_t size, uint32_t region, > + uint8_t mocs, enum blt_copy_type type, > + enum blt_compression compression) > +{ > + obj->handle = handle; > + obj->region = region; > + obj->size = size; > + obj->mocs = mocs; > + obj->type = type; > + obj->compression = compression; > +} > + > void blt_set_object_ext(struct blt_block_copy_object_ext *obj, > uint8_t compression_format, > uint16_t surface_width, uint16_t surface_height, > diff --git a/lib/intel_blt.h b/lib/intel_blt.h > index d9c8883c7..d10ec954a 100644 > --- a/lib/intel_blt.h > +++ b/lib/intel_blt.h > @@ -93,6 +93,17 @@ struct blt_copy_object { > uint32_t plane_offset; > }; > > +struct blt_mem_object { > + uint32_t handle; > + uint32_t region; > + uint64_t size; > + uint8_t mocs; > + enum blt_copy_type type; > + enum blt_compression compression; > + uint32_t pitch; > + uint32_t *ptr; > +}; > + > struct blt_copy_batch { > uint32_t handle; > uint32_t region; > @@ -112,6 +123,14 @@ struct blt_copy_data { > bool print_bb; > }; > > +struct blt_mem_data { > + int fd; > + enum intel_driver driver; > + struct blt_mem_object src; > + struct blt_mem_object dst; > + struct blt_copy_batch bb; > +}; > + > enum blt_surface_type { > SURFACE_TYPE_1D, > SURFACE_TYPE_2D, > @@ -190,6 +209,7 @@ bool blt_uses_extended_block_copy(int fd); > const char *blt_tiling_name(enum blt_tiling_type tiling); > > void blt_copy_init(int fd, struct blt_copy_data *blt); > +void blt_mem_init(int fd, struct blt_mem_data *mem); > > uint64_t emit_blt_block_copy(int fd, > uint64_t ahnd, > @@ -231,6 +251,23 @@ int blt_fast_copy(int fd, > uint64_t ahnd, > const struct blt_copy_data *blt); > > +void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem, > + uint32_t col_size); > + > +int blt_mem_copy(int fd, const intel_ctx_t *ctx, > + const struct intel_execution_engine2 *e, > + uint64_t ahnd, > + const struct blt_mem_data *mem, > + uint32_t col_size); > + > +void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem, > + uint32_t fill_data, uint32_t height); > + > +int blt_mem_set(int fd, const intel_ctx_t *ctx, > + const struct intel_execution_engine2 *e, uint64_t ahnd, > + const struct blt_mem_data *mem, uint32_t height, > + uint32_t fill_data); > + > void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch, > int16_t x1, int16_t y1, int16_t x2, int16_t y2, > uint16_t x_offset, uint16_t y_offset); > @@ -250,6 +287,12 @@ void blt_set_object(struct blt_copy_object *obj, > uint8_t mocs, enum blt_tiling_type tiling, > enum blt_compression compression, > enum blt_compression_type compression_type); > + > +void blt_set_mem_object(struct blt_mem_object *obj, > + uint32_t handle, uint64_t size, uint32_t region, > + uint8_t mocs, enum blt_copy_type type, > + enum blt_compression compression); > + > void blt_set_object_ext(struct blt_block_copy_object_ext *obj, > uint8_t compression_format, > uint16_t surface_width, uint16_t surface_height, > diff --git a/lib/intel_reg.h b/lib/intel_reg.h > index 3bf3676dc..eb65da911 100644 > --- a/lib/intel_reg.h > +++ b/lib/intel_reg.h > @@ -2586,6 +2586,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. > #define XY_FAST_COPY_COLOR_DEPTH_64 (4 << 24) > #define XY_FAST_COPY_COLOR_DEPTH_128 (5 << 24) > > +/* RAW memory commands */ > +#define MEM_COPY_CMD ((0x2 << 29)|(0x5a << 22)|0x8) > +#define MEM_SET_CMD ((0x2 << 29)|(0x5b << 22)|0x5) > + > #define CTXT_NO_RESTORE (1) > #define CTXT_PALETTE_SAVE_DISABLE (1<<3) > #define CTXT_PALETTE_RESTORE_DISABLE (1<<2) > -- > 2.39.1 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: Add copy basic test to exercise blt commands 2023-09-26 12:27 [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands sai.gowtham.ch 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add check to see if blt commands are supported by the platforms sai.gowtham.ch 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec sai.gowtham.ch @ 2023-09-26 12:27 ` sai.gowtham.ch 2023-09-26 13:49 ` [igt-dev] ✓ Fi.CI.BAT: success for Add copy basic test to exercise blt commands (rev4) Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 13+ messages in thread From: sai.gowtham.ch @ 2023-09-26 12:27 UTC (permalink / raw) To: igt-dev, karolina.stolarek, Zbigniew.Kempczynski, sai.gowtham.ch From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Add copy basic test to exercise copy commands like mem-copy and mem-set. Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> --- tests/intel/xe_copy_basic.c | 206 ++++++++++++++++++++++++++++++++++++ tests/meson.build | 1 + 2 files changed, 207 insertions(+) create mode 100644 tests/intel/xe_copy_basic.c diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c new file mode 100644 index 000000000..d3d072512 --- /dev/null +++ b/tests/intel/xe_copy_basic.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2023 Intel Corporation + * + * Authors: + * Sai Gowtham Ch <sai.gowtham.ch@intel.com> + */ + +#include "igt.h" +#include "lib/igt_syncobj.h" +#include "intel_blt.h" +#include "lib/intel_cmds_info.h" +#include "lib/intel_mocs.h" +#include "lib/intel_reg.h" +#include "xe/xe_ioctl.h" +#include "xe/xe_query.h" +#include "xe/xe_util.h" + +/** + * TEST: Test to validate copy commands on xe + * Category: Software building block + * Sub-category: Copy + * Functionality: blitter + */ + +/** + * SUBTEST: mem-copy-%s + * Description: Test validates MEM_COPY command, it takes various + * parameters needed for the filling batch buffer for MEM_COPY command + * with size %arg[1]. + * Test category: functionality test + * + * arg[1]: + * @0x369: 0x369 + * @0x3fff: 0x3fff + * @0xfd: 0xfd + * @0xffff: 0xffff + */ +static void +igt_mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, + const intel_ctx_t *ctx, uint32_t row_size, + uint32_t col_size, uint32_t region) +{ + struct blt_mem_data mem = {}; + uint64_t bb_size = xe_get_default_alignment(fd); + uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_LOW_TO_HIGH, 0); + uint32_t bb; + int result; + uint8_t src_mocs = intel_get_uc_mocs(fd); + uint8_t dst_mocs = src_mocs; + + bb = xe_bo_create_flags(fd, 0, bb_size, region); + + blt_mem_init(fd, &mem); + blt_set_mem_object(&mem.src, src_handle, row_size, region, src_mocs, + M_LINEAR, COMPRESSION_DISABLED); + blt_set_mem_object(&mem.dst, dst_handle, row_size, region, dst_mocs, + M_LINEAR, COMPRESSION_DISABLED); + mem.src.ptr = xe_bo_map(fd, src_handle, row_size); + mem.dst.ptr = xe_bo_map(fd, dst_handle, row_size); + + blt_set_batch(&mem.bb, bb, bb_size, region); + igt_assert(mem.src.size == mem.dst.size); + + blt_mem_copy(fd, ctx, NULL, ahnd, &mem, col_size); + result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size); + igt_assert_f(!result, "source and destination differ\n"); + + intel_allocator_bind(ahnd, 0, 0); + gem_close(fd, bb); + put_ahnd(ahnd); +} + +/** + * SUBTEST: mem-set-%s + * Description: Test validates MEM_SET command with size %arg[1]. + * Test category: functionality test + * + * arg[1]: + * + * @0x369: 0x369 + * @0x3fff: 0x3fff + * @0xfd: 0xfd + * @0xffff: 0xffff + */ +static void igt_mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, + size_t size, uint32_t height, + uint32_t fill_data, uint32_t region) +{ + struct blt_mem_data mem = {}; + uint64_t bb_size = xe_get_default_alignment(fd); + uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_LOW_TO_HIGH, 0); + uint32_t bb; + int result; + uint8_t dst_mocs = intel_get_uc_mocs(fd); + + bb = xe_bo_create_flags(fd, 0, bb_size, region); + blt_mem_init(fd, &mem); + blt_set_mem_object(&mem.dst, dst_handle, size, region, dst_mocs, + M_LINEAR, COMPRESSION_DISABLED); + blt_set_batch(&mem.bb, bb, bb_size, region); + blt_mem_set(fd, ctx, NULL, ahnd, &mem, height, fill_data); + result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size); + igt_assert_f(!result, "source and destination differ\n"); + + intel_allocator_bind(ahnd, 0, 0); + gem_close(fd, bb); + put_ahnd(ahnd); +} + +static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, + struct drm_xe_engine_class_instance *hwe, uint32_t region) +{ + uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size; + uint32_t bo_size = ALIGN(size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); + uint32_t temp_buffer[bo_size]; + const intel_ctx_t *ctx; + + src_handle = xe_bo_create_flags(fd, 0, bo_size, region); + dst_handle = xe_bo_create_flags(fd, 0, bo_size, region); + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); + exec_queue = xe_exec_queue_create(fd, vm, hwe, 0); + ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0); + + src_size = bo_size; + dst_size = bo_size; + + /* Fill a pattern in the buffer */ + for (int i = 0; i < bo_size; i++) { + temp_buffer[i] = i % 16; + } + + if (cmd == MEM_COPY) { + igt_mem_copy(fd, + src_handle,/*src_handle*/ + dst_handle,/*dst_handle*/ + ctx, + src_size,/*row_size*/ + 1,/*col_size*/ + region); + } else if (cmd == MEM_SET) { + igt_mem_set(fd, + dst_handle, /*dst_handle*/ + ctx, + dst_size,/*width*/ + 1,/*height*/ + temp_buffer[0] & 0xff,/*fill_data*/ + region); + src_size = 1; + } + + gem_close(fd, src_handle); + gem_close(fd, dst_handle); + xe_exec_queue_destroy(fd, exec_queue); + xe_vm_destroy(fd, vm); +} + +igt_main +{ + struct drm_xe_engine_class_instance *hwe; + int fd; + struct igt_collection *set, *regions; + uint32_t region; + uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFF}; + + igt_fixture { + fd = drm_open_driver(DRIVER_XE); + xe_device_get(fd); + set = xe_get_memory_region_set(fd, + XE_MEM_REGION_CLASS_SYSMEM, + XE_MEM_REGION_CLASS_VRAM); + } + + for (int i = 0; i < ARRAY_SIZE(size); i++) { + igt_subtest_f("mem-copy-0x%lx", size[i]) { + igt_require(blt_has_mem_copy(fd)); + for_each_variation_r(regions, 1, set) { + region = igt_collection_get_value(regions, 0); + xe_for_each_hw_engine(fd, hwe) + copy_test(fd, size[i], + MEM_COPY, hwe, + region); + } + } + } + + for (int i = 0; i < ARRAY_SIZE(size); i++) { + igt_subtest_f("mem-set-0x%lx", size[i]) { + igt_require(blt_has_mem_set(fd)); + for_each_variation_r(regions, 1, set) { + region = igt_collection_get_value(regions, 0); + xe_for_each_hw_engine(fd, hwe) + copy_test(fd, size[i], + MEM_SET, hwe, region); + } + } + } + + igt_fixture { + drm_close_driver(fd); + } +} diff --git a/tests/meson.build b/tests/meson.build index 974cb433b..3381fd919 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -274,6 +274,7 @@ intel_xe_progs = [ 'xe_ccs', 'xe_create', 'xe_compute', + 'xe_copy_basic', 'xe_dma_buf_sync', 'xe_debugfs', 'xe_drm_fdinfo', -- 2.39.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add copy basic test to exercise blt commands (rev4) 2023-09-26 12:27 [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands sai.gowtham.ch ` (2 preceding siblings ...) 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: Add copy basic test to exercise blt commands sai.gowtham.ch @ 2023-09-26 13:49 ` Patchwork 2023-09-26 14:16 ` [igt-dev] ✓ CI.xeBAT: " Patchwork 2023-09-27 1:27 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2023-09-26 13:49 UTC (permalink / raw) To: sai.gowtham.ch; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 5389 bytes --] == Series Details == Series: Add copy basic test to exercise blt commands (rev4) URL : https://patchwork.freedesktop.org/series/122615/ State : success == Summary == CI Bug Log - changes from CI_DRM_13681 -> IGTPW_9879 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/index.html Participating hosts (41 -> 40) ------------------------------ Additional (1): bat-dg2-14 Missing (2): fi-kbl-soraka fi-snb-2520m Known issues ------------ Here are the changes found in IGTPW_9879 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s3@smem: - bat-mtlp-6: NOTRUN -> [FAIL][1] ([fdo#103375]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/bat-mtlp-6/igt@gem_exec_suspend@basic-s3@smem.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-mtlp-6: [PASS][4] -> [FAIL][5] ([fdo#103375]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/bat-mtlp-6/igt@i915_suspend@basic-s2idle-without-i915.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/bat-mtlp-6/igt@i915_suspend@basic-s2idle-without-i915.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#1845]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#1845] / [i915#4078]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/bat-mtlp-6/igt@kms_pipe_crc_basic@suspend-read-crc.html #### Warnings #### * igt@gem_exec_suspend@basic-s0@smem: - bat-mtlp-6: [ABORT][8] ([i915#9262]) -> [FAIL][9] ([fdo#103375]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/bat-mtlp-6/igt@gem_exec_suspend@basic-s0@smem.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/bat-mtlp-6/igt@gem_exec_suspend@basic-s0@smem.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [ABORT][10] ([i915#9262]) -> [ABORT][11] ([i915#9414]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/bat-mtlp-8/igt@i915_selftest@live@requests.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/bat-mtlp-8/igt@i915_selftest@live@requests.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608 [i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359 [i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952 [i915#8981]: https://gitlab.freedesktop.org/drm/intel/issues/8981 [i915#9262]: https://gitlab.freedesktop.org/drm/intel/issues/9262 [i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7503 -> IGTPW_9879 CI-20190529: 20190529 CI_DRM_13681: b57407d0de043fc22b000a941a404ab103849e06 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_9879: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/index.html IGT_7503: 7503 Testlist changes ---------------- +igt@xe_copy_basic@mem-copy-0x3fff +igt@xe_copy_basic@mem-copy-0x369 +igt@xe_copy_basic@mem-copy-0xfd +igt@xe_copy_basic@mem-copy-0xffff +igt@xe_copy_basic@mem-set-0x3fff +igt@xe_copy_basic@mem-set-0x369 +igt@xe_copy_basic@mem-set-0xfd +igt@xe_copy_basic@mem-set-0xffff == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/index.html [-- Attachment #2: Type: text/html, Size: 5173 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] ✓ CI.xeBAT: success for Add copy basic test to exercise blt commands (rev4) 2023-09-26 12:27 [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands sai.gowtham.ch ` (3 preceding siblings ...) 2023-09-26 13:49 ` [igt-dev] ✓ Fi.CI.BAT: success for Add copy basic test to exercise blt commands (rev4) Patchwork @ 2023-09-26 14:16 ` Patchwork 2023-09-27 1:27 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2023-09-26 14:16 UTC (permalink / raw) To: sai.gowtham.ch; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 1510 bytes --] == Series Details == Series: Add copy basic test to exercise blt commands (rev4) URL : https://patchwork.freedesktop.org/series/122615/ State : success == Summary == CI Bug Log - changes from XEIGT_7503_BAT -> XEIGTPW_9879_BAT ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (4 -> 3) ------------------------------ Missing (1): bat-pvc-2 Known issues ------------ Here are the changes found in XEIGTPW_9879_BAT that come from known issues: ### IGT changes ### #### Possible fixes #### * {igt@xe_create@create-execqueues-noleak}: - bat-atsm-2: [FAIL][1] ([Intel XE#524]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7503/bat-atsm-2/igt@xe_create@create-execqueues-noleak.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9879/bat-atsm-2/igt@xe_create@create-execqueues-noleak.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [Intel XE#524]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/524 Build changes ------------- * IGT: IGT_7503 -> IGTPW_9879 IGTPW_9879: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/index.html IGT_7503: 7503 xe-396-fc8ec3c56efa5c15b630ddc17c89100440fe03ef: fc8ec3c56efa5c15b630ddc17c89100440fe03ef == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9879/index.html [-- Attachment #2: Type: text/html, Size: 2082 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Add copy basic test to exercise blt commands (rev4) 2023-09-26 12:27 [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands sai.gowtham.ch ` (4 preceding siblings ...) 2023-09-26 14:16 ` [igt-dev] ✓ CI.xeBAT: " Patchwork @ 2023-09-27 1:27 ` Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2023-09-27 1:27 UTC (permalink / raw) To: sai.gowtham.ch; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 94894 bytes --] == Series Details == Series: Add copy basic test to exercise blt commands (rev4) URL : https://patchwork.freedesktop.org/series/122615/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13681_full -> IGTPW_9879_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_9879_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_9879_full, please notify your bug team (lgci.bug.filing@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/index.html Participating hosts (9 -> 9) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_9879_full: ### IGT changes ### #### Possible regressions #### * igt@gem_exec_suspend@basic-s0@smem: - shard-dg2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-1/igt@gem_exec_suspend@basic-s0@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@gem_exec_suspend@basic-s0@smem.html Known issues ------------ Here are the changes found in IGTPW_9879_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@blit-reloc-keep-cache: - shard-rkl: NOTRUN -> [SKIP][3] ([i915#8411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@api_intel_bb@blit-reloc-keep-cache.html * igt@api_intel_bb@object-reloc-purge-cache: - shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8411]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@api_intel_bb@object-reloc-purge-cache.html * igt@debugfs_test@basic-hwmon: - shard-rkl: NOTRUN -> [SKIP][5] ([i915#9318]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@debugfs_test@basic-hwmon.html * igt@device_reset@unbind-cold-reset-rebind: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#7701]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@device_reset@unbind-cold-reset-rebind.html * igt@drm_fdinfo@busy-hang@rcs0: - shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8414]) +11 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@drm_fdinfo@busy-hang@rcs0.html * igt@gem_caching@reads: - shard-mtlp: NOTRUN -> [SKIP][8] ([i915#4873]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-5/igt@gem_caching@reads.html * igt@gem_ccs@ctrl-surf-copy: - shard-mtlp: NOTRUN -> [SKIP][9] ([i915#3555]) +1 other test skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@gem_ccs@ctrl-surf-copy.html * igt@gem_ccs@ctrl-surf-copy-new-ctx: - shard-mtlp: NOTRUN -> [SKIP][10] ([i915#9323]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@gem_ccs@ctrl-surf-copy-new-ctx.html * igt@gem_ccs@suspend-resume: - shard-rkl: NOTRUN -> [SKIP][11] ([i915#9323]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-6/igt@gem_ccs@suspend-resume.html * igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0: - shard-dg2: [PASS][12] -> [INCOMPLETE][13] ([i915#7297]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-11/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0.html * igt@gem_close_race@multigpu-basic-process: - shard-dg2: NOTRUN -> [SKIP][14] ([i915#7697]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@gem_close_race@multigpu-basic-process.html * igt@gem_create@create-ext-cpu-access-big: - shard-mtlp: NOTRUN -> [SKIP][15] ([i915#6335]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@gem_create@create-ext-cpu-access-big.html * igt@gem_ctx_persistence@engines-hostile@vcs0: - shard-mtlp: NOTRUN -> [FAIL][16] ([i915#2410]) +2 other tests fail [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-3/igt@gem_ctx_persistence@engines-hostile@vcs0.html * igt@gem_ctx_persistence@heartbeat-many: - shard-dg2: NOTRUN -> [SKIP][17] ([i915#8555]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@gem_ctx_persistence@heartbeat-many.html * igt@gem_ctx_persistence@saturated-hostile@vecs0: - shard-mtlp: [PASS][18] -> [FAIL][19] ([i915#7816]) +2 other tests fail [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-mtlp-5/igt@gem_ctx_persistence@saturated-hostile@vecs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@gem_ctx_persistence@saturated-hostile@vecs0.html * igt@gem_ctx_persistence@smoketest: - shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#1099]) +1 other test skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-snb1/igt@gem_ctx_persistence@smoketest.html * igt@gem_ctx_sseu@engines: - shard-rkl: NOTRUN -> [SKIP][21] ([i915#280]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-6/igt@gem_ctx_sseu@engines.html * igt@gem_ctx_sseu@mmap-args: - shard-mtlp: NOTRUN -> [SKIP][22] ([i915#280]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@gem_ctx_sseu@mmap-args.html * igt@gem_eio@hibernate: - shard-dg1: [PASS][23] -> [ABORT][24] ([i915#7975] / [i915#8213]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg1-15/igt@gem_eio@hibernate.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-14/igt@gem_eio@hibernate.html * igt@gem_eio@kms: - shard-dg2: [PASS][25] -> [INCOMPLETE][26] ([i915#1982] / [i915#7892]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-6/igt@gem_eio@kms.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@gem_eio@kms.html * igt@gem_exec_balancer@bonded-pair: - shard-mtlp: NOTRUN -> [SKIP][27] ([i915#4771]) +1 other test skip [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@gem_exec_balancer@bonded-pair.html * igt@gem_exec_balancer@bonded-sync: - shard-dg2: NOTRUN -> [SKIP][28] ([i915#4771]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@gem_exec_balancer@bonded-sync.html * igt@gem_exec_balancer@parallel-balancer: - shard-rkl: NOTRUN -> [SKIP][29] ([i915#4525]) +1 other test skip [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@gem_exec_balancer@parallel-balancer.html * igt@gem_exec_capture@capture-invisible@lmem0: - shard-dg2: NOTRUN -> [SKIP][30] ([i915#6334]) +1 other test skip [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@gem_exec_capture@capture-invisible@lmem0.html * igt@gem_exec_fair@basic-none-rrul: - shard-dg1: NOTRUN -> [SKIP][31] ([i915#3539] / [i915#4852]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-18/igt@gem_exec_fair@basic-none-rrul.html - shard-mtlp: NOTRUN -> [SKIP][32] ([i915#4473] / [i915#4771]) +1 other test skip [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@gem_exec_fair@basic-none-rrul.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-rkl: [PASS][33] -> [FAIL][34] ([i915#2842]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-rkl-7/igt@gem_exec_fair@basic-none-share@rcs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-rkl: NOTRUN -> [FAIL][35] ([i915#2842]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][36] -> [FAIL][37] ([i915#2842]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-throttle: - shard-dg2: NOTRUN -> [SKIP][38] ([i915#3539]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@gem_exec_fair@basic-throttle.html * igt@gem_exec_fence@submit3: - shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4812]) +1 other test skip [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@gem_exec_fence@submit3.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-mtlp: NOTRUN -> [SKIP][40] ([i915#3711]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html * igt@gem_exec_flush@basic-uc-ro-default: - shard-dg2: NOTRUN -> [SKIP][41] ([i915#3539] / [i915#4852]) +3 other tests skip [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@gem_exec_flush@basic-uc-ro-default.html * igt@gem_exec_gttfill@multigpu-basic: - shard-mtlp: NOTRUN -> [SKIP][42] ([i915#7697]) +2 other tests skip [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@gem_exec_gttfill@multigpu-basic.html * igt@gem_exec_params@rsvd2-dirt: - shard-dg2: NOTRUN -> [SKIP][43] ([fdo#109283] / [i915#5107]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@gem_exec_params@rsvd2-dirt.html * igt@gem_exec_params@secure-non-master: - shard-mtlp: NOTRUN -> [SKIP][44] ([fdo#112283]) +1 other test skip [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@gem_exec_params@secure-non-master.html * igt@gem_exec_reloc@basic-cpu-read-noreloc: - shard-dg1: NOTRUN -> [SKIP][45] ([i915#3281]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-18/igt@gem_exec_reloc@basic-cpu-read-noreloc.html * igt@gem_exec_reloc@basic-gtt-noreloc: - shard-mtlp: NOTRUN -> [SKIP][46] ([i915#3281]) +14 other tests skip [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-5/igt@gem_exec_reloc@basic-gtt-noreloc.html * igt@gem_exec_reloc@basic-gtt-wc-active: - shard-dg2: NOTRUN -> [SKIP][47] ([i915#3281]) +9 other tests skip [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-1/igt@gem_exec_reloc@basic-gtt-wc-active.html * igt@gem_exec_reloc@basic-write-read: - shard-rkl: NOTRUN -> [SKIP][48] ([i915#3281]) +7 other tests skip [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@gem_exec_reloc@basic-write-read.html * igt@gem_fence_thrash@bo-copy: - shard-dg2: NOTRUN -> [SKIP][49] ([i915#4860]) +3 other tests skip [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@gem_fence_thrash@bo-copy.html * igt@gem_fence_thrash@bo-write-verify-none: - shard-mtlp: NOTRUN -> [SKIP][50] ([i915#4860]) +1 other test skip [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@gem_fence_thrash@bo-write-verify-none.html * igt@gem_fenced_exec_thrash@too-many-fences: - shard-dg1: NOTRUN -> [SKIP][51] ([i915#4860]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-18/igt@gem_fenced_exec_thrash@too-many-fences.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2190]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-apl4/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-rkl: NOTRUN -> [SKIP][53] ([i915#4613]) +2 other tests skip [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@gem_lmem_swapping@parallel-random-verify.html * igt@gem_lmem_swapping@verify-random-ccs: - shard-mtlp: NOTRUN -> [SKIP][54] ([i915#4613]) +6 other tests skip [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@gem_lmem_swapping@verify-random-ccs.html * igt@gem_media_fill@media-fill: - shard-dg2: NOTRUN -> [SKIP][55] ([i915#8289]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-1/igt@gem_media_fill@media-fill.html * igt@gem_mmap_gtt@basic-read-write: - shard-dg2: NOTRUN -> [SKIP][56] ([i915#4077]) +11 other tests skip [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@gem_mmap_gtt@basic-read-write.html * igt@gem_mmap_gtt@coherency: - shard-rkl: NOTRUN -> [SKIP][57] ([fdo#111656]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@gem_mmap_gtt@coherency.html * igt@gem_mmap_gtt@cpuset-medium-copy: - shard-mtlp: NOTRUN -> [SKIP][58] ([i915#4077]) +25 other tests skip [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-3/igt@gem_mmap_gtt@cpuset-medium-copy.html * igt@gem_mmap_wc@read-write: - shard-mtlp: NOTRUN -> [SKIP][59] ([i915#4083]) +8 other tests skip [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-3/igt@gem_mmap_wc@read-write.html * igt@gem_mmap_wc@read-write-distinct: - shard-dg2: NOTRUN -> [SKIP][60] ([i915#4083]) +1 other test skip [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@gem_mmap_wc@read-write-distinct.html * igt@gem_partial_pwrite_pread@writes-after-reads-snoop: - shard-dg1: NOTRUN -> [SKIP][61] ([i915#3282]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-19/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html * igt@gem_pread@snoop: - shard-dg2: NOTRUN -> [SKIP][62] ([i915#3282]) +4 other tests skip [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@gem_pread@snoop.html * igt@gem_pxp@reject-modify-context-protection-off-1: - shard-tglu: NOTRUN -> [SKIP][63] ([i915#4270]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-6/igt@gem_pxp@reject-modify-context-protection-off-1.html * igt@gem_pxp@reject-modify-context-protection-off-2: - shard-dg2: NOTRUN -> [SKIP][64] ([i915#4270]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@gem_pxp@reject-modify-context-protection-off-2.html - shard-dg1: NOTRUN -> [SKIP][65] ([i915#4270]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-18/igt@gem_pxp@reject-modify-context-protection-off-2.html * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume: - shard-rkl: NOTRUN -> [SKIP][66] ([i915#4270]) +2 other tests skip [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-4/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html * igt@gem_pxp@verify-pxp-stale-buf-optout-execution: - shard-mtlp: NOTRUN -> [SKIP][67] ([i915#4270]) +4 other tests skip [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html * igt@gem_readwrite@read-bad-handle: - shard-mtlp: NOTRUN -> [SKIP][68] ([i915#3282]) +8 other tests skip [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@gem_readwrite@read-bad-handle.html * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled: - shard-mtlp: NOTRUN -> [SKIP][69] ([i915#8428]) +10 other tests skip [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-2/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled.html * igt@gem_render_tiled_blits@basic: - shard-dg2: NOTRUN -> [SKIP][70] ([i915#4079]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@gem_render_tiled_blits@basic.html - shard-dg1: NOTRUN -> [SKIP][71] ([i915#4079]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-19/igt@gem_render_tiled_blits@basic.html * igt@gem_set_tiling_vs_blt@tiled-to-untiled: - shard-mtlp: NOTRUN -> [SKIP][72] ([i915#4079]) +2 other tests skip [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html * igt@gem_set_tiling_vs_pwrite: - shard-rkl: NOTRUN -> [SKIP][73] ([i915#3282]) +3 other tests skip [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-4/igt@gem_set_tiling_vs_pwrite.html * igt@gem_softpin@evict-snoop-interruptible: - shard-rkl: NOTRUN -> [SKIP][74] ([fdo#109312]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@gem_softpin@evict-snoop-interruptible.html * igt@gem_tiled_wb: - shard-dg1: NOTRUN -> [SKIP][75] ([i915#4077]) +1 other test skip [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-12/igt@gem_tiled_wb.html * igt@gem_userptr_blits@mmap-offset-banned@gtt: - shard-mtlp: NOTRUN -> [SKIP][76] ([i915#3297]) +6 other tests skip [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-5/igt@gem_userptr_blits@mmap-offset-banned@gtt.html * igt@gem_userptr_blits@unsync-overlap: - shard-dg2: NOTRUN -> [SKIP][77] ([i915#3297]) +2 other tests skip [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@gem_userptr_blits@unsync-overlap.html - shard-rkl: NOTRUN -> [SKIP][78] ([i915#3297]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@gem_userptr_blits@unsync-overlap.html * igt@gen7_exec_parse@chained-batch: - shard-dg2: NOTRUN -> [SKIP][79] ([fdo#109289]) +3 other tests skip [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@gen7_exec_parse@chained-batch.html * igt@gen9_exec_parse@bb-start-out: - shard-rkl: NOTRUN -> [SKIP][80] ([i915#2527]) +1 other test skip [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@gen9_exec_parse@bb-start-out.html * igt@gen9_exec_parse@unaligned-jump: - shard-mtlp: NOTRUN -> [SKIP][81] ([i915#2856]) +5 other tests skip [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@gen9_exec_parse@unaligned-jump.html * igt@gen9_exec_parse@valid-registers: - shard-dg2: NOTRUN -> [SKIP][82] ([i915#2856]) +1 other test skip [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-1/igt@gen9_exec_parse@valid-registers.html * igt@i915_hwmon@hwmon-read: - shard-rkl: NOTRUN -> [SKIP][83] ([i915#7707]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@i915_hwmon@hwmon-read.html * igt@i915_hwmon@hwmon-write: - shard-mtlp: NOTRUN -> [SKIP][84] ([i915#7707]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@i915_hwmon@hwmon-write.html * igt@i915_module_load@load: - shard-mtlp: NOTRUN -> [SKIP][85] ([i915#6227]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@i915_module_load@load.html * igt@i915_module_load@resize-bar: - shard-mtlp: NOTRUN -> [SKIP][86] ([i915#6412]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-4/igt@i915_module_load@resize-bar.html * igt@i915_pm_freq_api@freq-reset-multiple: - shard-rkl: NOTRUN -> [SKIP][87] ([i915#8399]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-4/igt@i915_pm_freq_api@freq-reset-multiple.html * igt@i915_pm_freq_mult@media-freq@gt1: - shard-mtlp: NOTRUN -> [SKIP][88] ([i915#6590]) +1 other test skip [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-2/igt@i915_pm_freq_mult@media-freq@gt1.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-dg1: [PASS][89] -> [FAIL][90] ([i915#3591]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@i915_pm_rpm@dpms-mode-unset-lpsp: - shard-dg2: NOTRUN -> [SKIP][91] ([i915#1397]) +1 other test skip [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-rkl: [PASS][92] -> [SKIP][93] ([i915#1397]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-rkl-2/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html - shard-mtlp: NOTRUN -> [SKIP][94] ([i915#1397]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-5/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-dg1: [PASS][95] -> [SKIP][96] ([i915#1397]) +1 other test skip [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg1-16/igt@i915_pm_rpm@dpms-non-lpsp.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-19/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@i915_pm_rpm@modeset-lpsp-stress: - shard-dg1: NOTRUN -> [SKIP][97] ([i915#1397]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-18/igt@i915_pm_rpm@modeset-lpsp-stress.html * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait: - shard-dg2: [PASS][98] -> [SKIP][99] ([i915#1397]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html * igt@i915_pm_rpm@pc8-residency: - shard-dg2: NOTRUN -> [SKIP][100] ([fdo#109506]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@i915_pm_rpm@pc8-residency.html - shard-mtlp: NOTRUN -> [SKIP][101] ([fdo#109293]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@i915_pm_rpm@pc8-residency.html * igt@i915_pm_rps@basic-api: - shard-mtlp: NOTRUN -> [SKIP][102] ([i915#6621]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@i915_pm_rps@basic-api.html * igt@i915_pm_rps@engine-order: - shard-apl: [PASS][103] -> [FAIL][104] ([i915#6537]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-apl4/igt@i915_pm_rps@engine-order.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-apl2/igt@i915_pm_rps@engine-order.html * igt@i915_pm_rps@thresholds@gt1: - shard-mtlp: NOTRUN -> [SKIP][105] ([i915#8925]) +3 other tests skip [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@i915_pm_rps@thresholds@gt1.html * igt@i915_query@query-topology-coherent-slice-mask: - shard-mtlp: NOTRUN -> [SKIP][106] ([i915#6188]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@i915_query@query-topology-coherent-slice-mask.html - shard-dg2: NOTRUN -> [SKIP][107] ([i915#6188]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@i915_query@query-topology-coherent-slice-mask.html * igt@i915_query@query-topology-known-pci-ids: - shard-dg1: NOTRUN -> [SKIP][108] ([fdo#109303]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-18/igt@i915_query@query-topology-known-pci-ids.html - shard-mtlp: NOTRUN -> [SKIP][109] ([fdo#109303]) [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@i915_query@query-topology-known-pci-ids.html - shard-dg2: NOTRUN -> [SKIP][110] ([fdo#109303]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@i915_query@query-topology-known-pci-ids.html * igt@i915_query@query-topology-unsupported: - shard-dg2: NOTRUN -> [SKIP][111] ([fdo#109302]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@i915_query@query-topology-unsupported.html - shard-dg1: NOTRUN -> [SKIP][112] ([fdo#109302]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-18/igt@i915_query@query-topology-unsupported.html * igt@i915_suspend@sysfs-reader: - shard-snb: NOTRUN -> [DMESG-WARN][113] ([i915#8841]) +2 other tests dmesg-warn [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-snb4/igt@i915_suspend@sysfs-reader.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - shard-mtlp: NOTRUN -> [SKIP][114] ([i915#5190]) [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-x-tiled-legacy: - shard-dg2: NOTRUN -> [SKIP][115] ([i915#4212]) +1 other test skip [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@kms_addfb_basic@basic-x-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - shard-mtlp: NOTRUN -> [SKIP][116] ([i915#4212]) +1 other test skip [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@kms_addfb_basic@tile-pitch-mismatch.html * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs: - shard-rkl: NOTRUN -> [SKIP][117] ([i915#8502]) +3 other tests skip [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs.html * igt@kms_async_flips@crc@pipe-c-hdmi-a-1: - shard-dg1: NOTRUN -> [FAIL][118] ([i915#8247]) +3 other tests fail [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-19/igt@kms_async_flips@crc@pipe-c-hdmi-a-1.html * igt@kms_async_flips@crc@pipe-d-edp-1: - shard-mtlp: NOTRUN -> [FAIL][119] ([i915#8247]) +3 other tests fail [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-3/igt@kms_async_flips@crc@pipe-d-edp-1.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels: - shard-dg2: NOTRUN -> [SKIP][120] ([i915#1769] / [i915#3555]) [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html - shard-dg1: NOTRUN -> [SKIP][121] ([i915#1769] / [i915#3555]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-14/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html * igt@kms_big_fb@4-tiled-32bpp-rotate-270: - shard-dg1: NOTRUN -> [SKIP][122] ([i915#4538] / [i915#5286]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-16/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-rkl: NOTRUN -> [SKIP][123] ([i915#5286]) +1 other test skip [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html * igt@kms_big_fb@linear-64bpp-rotate-270: - shard-mtlp: NOTRUN -> [SKIP][124] ([fdo#111614]) +9 other tests skip [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_big_fb@linear-64bpp-rotate-270.html * igt@kms_big_fb@linear-64bpp-rotate-90: - shard-rkl: NOTRUN -> [SKIP][125] ([fdo#111614] / [i915#3638]) +2 other tests skip [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-6/igt@kms_big_fb@linear-64bpp-rotate-90.html * igt@kms_big_fb@x-tiled-8bpp-rotate-270: - shard-dg2: NOTRUN -> [SKIP][126] ([fdo#111614]) +2 other tests skip [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow: - shard-dg2: NOTRUN -> [SKIP][127] ([i915#5190]) +9 other tests skip [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-tglu: [PASS][128] -> [FAIL][129] ([i915#3743]) +1 other test fail [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-90: - shard-dg2: NOTRUN -> [SKIP][130] ([i915#4538] / [i915#5190]) +4 other tests skip [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-1/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-270: - shard-mtlp: NOTRUN -> [SKIP][131] ([fdo#111615]) +15 other tests skip [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow: - shard-rkl: NOTRUN -> [SKIP][132] ([fdo#111615]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180: - shard-rkl: NOTRUN -> [SKIP][133] ([fdo#110723]) [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-dg1: NOTRUN -> [SKIP][134] ([i915#4538]) [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-19/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_joiner@2x-modeset: - shard-rkl: NOTRUN -> [SKIP][135] ([i915#2705]) [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-4/igt@kms_big_joiner@2x-modeset.html * igt@kms_big_joiner@basic: - shard-dg1: NOTRUN -> [SKIP][136] ([i915#2705]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-16/igt@kms_big_joiner@basic.html - shard-mtlp: NOTRUN -> [SKIP][137] ([i915#2705]) [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-2/igt@kms_big_joiner@basic.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: - shard-dg2: NOTRUN -> [SKIP][138] ([i915#3689] / [i915#3886] / [i915#5354]) +7 other tests skip [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs: - shard-rkl: NOTRUN -> [SKIP][139] ([i915#3886] / [i915#5354] / [i915#6095]) +1 other test skip [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs: - shard-rkl: NOTRUN -> [SKIP][140] ([i915#3734] / [i915#5354] / [i915#6095]) +4 other tests skip [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-4/igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs.html * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_mtl_rc_ccs_cc: - shard-rkl: NOTRUN -> [SKIP][141] ([i915#5354] / [i915#6095]) +8 other tests skip [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_mtl_rc_ccs_cc.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs: - shard-mtlp: NOTRUN -> [SKIP][142] ([i915#5354] / [i915#6095]) +48 other tests skip [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-5/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_ccs: - shard-tglu: NOTRUN -> [SKIP][143] ([i915#3689] / [i915#5354] / [i915#6095]) [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_ccs.html * igt@kms_ccs@pipe-c-missing-ccs-buffer-4_tiled_mtl_mc_ccs: - shard-dg1: NOTRUN -> [SKIP][144] ([i915#5354] / [i915#6095]) +1 other test skip [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-12/igt@kms_ccs@pipe-c-missing-ccs-buffer-4_tiled_mtl_mc_ccs.html * igt@kms_ccs@pipe-c-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc: - shard-rkl: NOTRUN -> [SKIP][145] ([i915#5354]) +17 other tests skip [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@kms_ccs@pipe-c-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc.html * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs: - shard-mtlp: NOTRUN -> [SKIP][146] ([i915#3886] / [i915#5354] / [i915#6095]) +20 other tests skip [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-2/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs: - shard-dg2: NOTRUN -> [SKIP][147] ([i915#3689] / [i915#5354]) +18 other tests skip [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_mc_ccs: - shard-dg1: NOTRUN -> [SKIP][148] ([i915#3689] / [i915#5354] / [i915#6095]) +4 other tests skip [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-17/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_mc_ccs.html * igt@kms_cdclk@mode-transition: - shard-rkl: NOTRUN -> [SKIP][149] ([i915#3742]) +2 other tests skip [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@kms_cdclk@mode-transition.html * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][150] ([i915#4087] / [i915#7213]) +3 other tests skip [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html * igt@kms_cdclk@plane-scaling@pipe-c-edp-1: - shard-mtlp: NOTRUN -> [SKIP][151] ([i915#4087]) +3 other tests skip [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_cdclk@plane-scaling@pipe-c-edp-1.html * igt@kms_chamelium_color@ctm-blue-to-red: - shard-mtlp: NOTRUN -> [SKIP][152] ([fdo#111827]) +3 other tests skip [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@kms_chamelium_color@ctm-blue-to-red.html - shard-tglu: NOTRUN -> [SKIP][153] ([fdo#111827]) [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-4/igt@kms_chamelium_color@ctm-blue-to-red.html * igt@kms_chamelium_edid@hdmi-edid-read: - shard-rkl: NOTRUN -> [SKIP][154] ([i915#7828]) +4 other tests skip [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_chamelium_edid@hdmi-edid-read.html * igt@kms_chamelium_frames@hdmi-crc-fast: - shard-dg2: NOTRUN -> [SKIP][155] ([i915#7828]) +8 other tests skip [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-1/igt@kms_chamelium_frames@hdmi-crc-fast.html * igt@kms_chamelium_frames@hdmi-frame-dump: - shard-dg1: NOTRUN -> [SKIP][156] ([i915#7828]) +1 other test skip [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-12/igt@kms_chamelium_frames@hdmi-frame-dump.html * igt@kms_chamelium_hpd@hdmi-hpd: - shard-mtlp: NOTRUN -> [SKIP][157] ([i915#7828]) +14 other tests skip [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@kms_chamelium_hpd@hdmi-hpd.html * igt@kms_color@deep-color: - shard-rkl: NOTRUN -> [SKIP][158] ([i915#3555]) +4 other tests skip [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_color@deep-color.html * igt@kms_color@deep-color@pipe-b-edp-1-degamma: - shard-mtlp: NOTRUN -> [FAIL][159] ([i915#6892]) +3 other tests fail [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_color@deep-color@pipe-b-edp-1-degamma.html * igt@kms_color@degamma@pipe-a: - shard-mtlp: NOTRUN -> [FAIL][160] ([i915#9257]) +3 other tests fail [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_color@degamma@pipe-a.html * igt@kms_content_protection@atomic-dpms: - shard-dg2: NOTRUN -> [SKIP][161] ([i915#7118]) [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-1/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@dp-mst-lic-type-0: - shard-dg2: NOTRUN -> [SKIP][162] ([i915#3299]) [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@kms_content_protection@dp-mst-lic-type-0.html * igt@kms_content_protection@dp-mst-type-1: - shard-mtlp: NOTRUN -> [SKIP][163] ([i915#3299]) [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@kms_content_protection@dp-mst-type-1.html * igt@kms_content_protection@lic: - shard-mtlp: NOTRUN -> [SKIP][164] ([i915#6944]) +2 other tests skip [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-3/igt@kms_content_protection@lic.html * igt@kms_content_protection@mei_interface: - shard-mtlp: NOTRUN -> [SKIP][165] ([i915#8063]) [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@kms_content_protection@mei_interface.html * igt@kms_content_protection@uevent: - shard-rkl: NOTRUN -> [SKIP][166] ([i915#7118]) [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_content_protection@uevent.html * igt@kms_content_protection@uevent@pipe-a-dp-4: - shard-dg2: NOTRUN -> [FAIL][167] ([i915#1339]) [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html * igt@kms_cursor_crc@cursor-offscreen-512x170: - shard-mtlp: NOTRUN -> [SKIP][168] ([i915#3359]) +1 other test skip [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-3/igt@kms_cursor_crc@cursor-offscreen-512x170.html - shard-dg1: NOTRUN -> [SKIP][169] ([i915#3359]) [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-19/igt@kms_cursor_crc@cursor-offscreen-512x170.html * igt@kms_cursor_crc@cursor-onscreen-32x10: - shard-mtlp: NOTRUN -> [SKIP][170] ([i915#3555] / [i915#8814]) +4 other tests skip [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@kms_cursor_crc@cursor-onscreen-32x10.html * igt@kms_cursor_crc@cursor-onscreen-512x170: - shard-dg2: NOTRUN -> [SKIP][171] ([i915#3359]) [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@kms_cursor_crc@cursor-onscreen-512x170.html - shard-rkl: NOTRUN -> [SKIP][172] ([fdo#109279] / [i915#3359]) [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_cursor_crc@cursor-onscreen-512x170.html * igt@kms_cursor_crc@cursor-random-max-size: - shard-dg2: NOTRUN -> [SKIP][173] ([i915#3555]) +2 other tests skip [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@kms_cursor_crc@cursor-random-max-size.html - shard-dg1: NOTRUN -> [SKIP][174] ([i915#3555]) [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-16/igt@kms_cursor_crc@cursor-random-max-size.html * igt@kms_cursor_crc@cursor-sliding-512x170: - shard-rkl: NOTRUN -> [SKIP][175] ([i915#3359]) [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-512x170.html * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-rkl: NOTRUN -> [SKIP][176] ([fdo#111825]) +5 other tests skip [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-mtlp: NOTRUN -> [SKIP][177] ([i915#3546]) +7 other tests skip [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-mtlp: NOTRUN -> [SKIP][178] ([i915#4213]) +3 other tests skip [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size: - shard-rkl: NOTRUN -> [SKIP][179] ([i915#4103]) +1 other test skip [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-dg2: NOTRUN -> [SKIP][180] ([fdo#109274] / [fdo#111767] / [i915#5354]) [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size: - shard-dg2: NOTRUN -> [SKIP][181] ([fdo#109274] / [i915#5354]) +2 other tests skip [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-glk: [PASS][182] -> [FAIL][183] ([i915#2346]) [182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle: - shard-dg2: NOTRUN -> [SKIP][184] ([i915#4103] / [i915#4213]) [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html * igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-1: - shard-dg2: NOTRUN -> [SKIP][185] ([i915#9227]) [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-1.html * igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-1: - shard-dg2: NOTRUN -> [SKIP][186] ([i915#9226] / [i915#9261]) +1 other test skip [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-1.html * igt@kms_display_modes@extended-mode-basic: - shard-mtlp: NOTRUN -> [SKIP][187] ([i915#3555] / [i915#8827]) [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@kms_display_modes@extended-mode-basic.html * igt@kms_dsc@dsc-with-bpc: - shard-rkl: NOTRUN -> [SKIP][188] ([i915#3555] / [i915#3840]) [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_dsc@dsc-with-bpc.html * igt@kms_dsc@dsc-with-output-formats: - shard-dg2: NOTRUN -> [SKIP][189] ([i915#3555] / [i915#3840]) [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@kms_dsc@dsc-with-output-formats.html - shard-mtlp: NOTRUN -> [SKIP][190] ([i915#3555] / [i915#3840]) [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-2/igt@kms_dsc@dsc-with-output-formats.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-mtlp: [PASS][191] -> [ABORT][192] ([i915#9262]) +2 other tests abort [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-mtlp-5/igt@kms_fbcon_fbt@fbc-suspend.html [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-2/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_fbcon_fbt@psr-suspend: - shard-dg2: NOTRUN -> [SKIP][193] ([i915#3469]) [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@2x-absolute-wf_vblank: - shard-dg2: NOTRUN -> [SKIP][194] ([fdo#109274]) +7 other tests skip [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@kms_flip@2x-absolute-wf_vblank.html * igt@kms_flip@2x-flip-vs-blocking-wf-vblank: - shard-rkl: NOTRUN -> [SKIP][195] ([fdo#111767] / [fdo#111825]) [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html * igt@kms_flip@2x-flip-vs-fences: - shard-mtlp: NOTRUN -> [SKIP][196] ([i915#8381]) +1 other test skip [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@kms_flip@2x-flip-vs-fences.html * igt@kms_flip@2x-flip-vs-rmfb: - shard-mtlp: NOTRUN -> [SKIP][197] ([i915#3637]) +8 other tests skip [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@kms_flip@2x-flip-vs-rmfb.html * igt@kms_flip@flip-vs-suspend-interruptible@d-edp1: - shard-mtlp: NOTRUN -> [DMESG-WARN][198] ([i915#9262]) +2 other tests dmesg-warn [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-4/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode: - shard-rkl: NOTRUN -> [SKIP][199] ([i915#2672]) +1 other test skip [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][200] ([i915#2672]) +5 other tests skip [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode: - shard-dg2: NOTRUN -> [SKIP][201] ([i915#2672]) +2 other tests skip [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html - shard-dg1: NOTRUN -> [SKIP][202] ([i915#2587] / [i915#2672]) [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-18/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][203] ([i915#3555] / [i915#8810]) +1 other test skip [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-dg1: NOTRUN -> [SKIP][204] ([i915#8708]) +1 other test skip [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-mtlp: NOTRUN -> [SKIP][205] ([i915#8708]) +10 other tests skip [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff: - shard-dg2: [PASS][206] -> [FAIL][207] ([i915#6880]) [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt: - shard-mtlp: NOTRUN -> [SKIP][208] ([i915#1825]) +63 other tests skip [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt: - shard-tglu: NOTRUN -> [SKIP][209] ([fdo#109280]) [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbc-tiling-y: - shard-dg2: NOTRUN -> [SKIP][210] ([i915#5460]) [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-tiling-y.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff: - shard-dg1: NOTRUN -> [SKIP][211] ([fdo#111825]) +5 other tests skip [211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt: - shard-rkl: NOTRUN -> [SKIP][212] ([fdo#111825] / [i915#1825]) +22 other tests skip [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt: - shard-dg2: NOTRUN -> [SKIP][213] ([i915#8708]) +14 other tests skip [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt: - shard-tglu: NOTRUN -> [SKIP][214] ([fdo#110189]) [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-rte: - shard-rkl: NOTRUN -> [SKIP][215] ([i915#3023]) +14 other tests skip [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-rte.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt: - shard-dg2: NOTRUN -> [SKIP][216] ([i915#5354]) +41 other tests skip [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary: - shard-dg2: NOTRUN -> [SKIP][217] ([i915#3458]) +18 other tests skip [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html - shard-dg1: NOTRUN -> [SKIP][218] ([i915#3458]) +4 other tests skip [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html * igt@kms_hdr@invalid-hdr: - shard-rkl: NOTRUN -> [SKIP][219] ([i915#3555] / [i915#8228]) [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-6/igt@kms_hdr@invalid-hdr.html * igt@kms_hdr@static-toggle: - shard-dg2: NOTRUN -> [SKIP][220] ([i915#3555] / [i915#8228]) +2 other tests skip [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@kms_hdr@static-toggle.html * igt@kms_hdr@static-toggle-suspend: - shard-mtlp: NOTRUN -> [SKIP][221] ([i915#3555] / [i915#8228]) [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_hdr@static-toggle-suspend.html * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes: - shard-rkl: NOTRUN -> [SKIP][222] ([fdo#109289]) +4 other tests skip [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1: - shard-apl: [PASS][223] -> [INCOMPLETE][224] ([i915#180] / [i915#9392]) [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html * igt@kms_plane_lowres@tiling-4@pipe-c-edp-1: - shard-mtlp: NOTRUN -> [SKIP][225] ([i915#3582]) +3 other tests skip [225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_plane_lowres@tiling-4@pipe-c-edp-1.html * igt@kms_plane_lowres@tiling-y: - shard-mtlp: NOTRUN -> [SKIP][226] ([i915#8821]) [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@kms_plane_lowres@tiling-y.html * igt@kms_plane_scaling@intel-max-src-size: - shard-glk: NOTRUN -> [SKIP][227] ([fdo#109271]) [227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-glk9/igt@kms_plane_scaling@intel-max-src-size.html - shard-rkl: NOTRUN -> [SKIP][228] ([i915#6953]) [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-6/igt@kms_plane_scaling@intel-max-src-size.html - shard-dg1: NOTRUN -> [SKIP][229] ([i915#6953]) [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-14/igt@kms_plane_scaling@intel-max-src-size.html - shard-tglu: NOTRUN -> [SKIP][230] ([i915#6953]) [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-5/igt@kms_plane_scaling@intel-max-src-size.html - shard-mtlp: NOTRUN -> [SKIP][231] ([i915#6953]) [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@kms_plane_scaling@intel-max-src-size.html * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-dp-4: - shard-dg2: NOTRUN -> [SKIP][232] ([i915#5176]) +7 other tests skip [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-dp-4.html * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-1: - shard-dg1: NOTRUN -> [SKIP][233] ([i915#5176]) +23 other tests skip [233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-19/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-1.html * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-2: - shard-rkl: NOTRUN -> [SKIP][234] ([i915#5176]) +5 other tests skip [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-2.html * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-2: - shard-rkl: NOTRUN -> [SKIP][235] ([i915#5235]) +3 other tests skip [235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-2.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-4: - shard-dg1: NOTRUN -> [SKIP][236] ([i915#5235]) +7 other tests skip [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-15/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-4.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1: - shard-mtlp: NOTRUN -> [SKIP][237] ([i915#5235]) +19 other tests skip [237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2: - shard-dg2: NOTRUN -> [SKIP][238] ([i915#5235]) +11 other tests skip [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html * igt@kms_prime@basic-modeset-hybrid: - shard-tglu: NOTRUN -> [SKIP][239] ([i915#6524]) [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-9/igt@kms_prime@basic-modeset-hybrid.html - shard-mtlp: NOTRUN -> [SKIP][240] ([i915#6524]) [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_prime@basic-modeset-hybrid.html * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf: - shard-rkl: NOTRUN -> [SKIP][241] ([i915#658]) +1 other test skip [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-6/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html * igt@kms_psr2_su@frontbuffer-xrgb8888: - shard-mtlp: NOTRUN -> [SKIP][242] ([i915#4348]) +1 other test skip [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_psr2_su@frontbuffer-xrgb8888.html * igt@kms_psr2_su@page_flip-p010: - shard-rkl: NOTRUN -> [SKIP][243] ([fdo#111068] / [i915#658]) [243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-4/igt@kms_psr2_su@page_flip-p010.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-dg2: NOTRUN -> [SKIP][244] ([i915#658]) +3 other tests skip [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr@no_drrs: - shard-dg2: NOTRUN -> [SKIP][245] ([i915#1072]) +3 other tests skip [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@kms_psr@no_drrs.html - shard-dg1: NOTRUN -> [SKIP][246] ([i915#1072]) [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-17/igt@kms_psr@no_drrs.html * igt@kms_psr@primary_render: - shard-rkl: NOTRUN -> [SKIP][247] ([i915#1072]) +6 other tests skip [247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@kms_psr@primary_render.html * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: - shard-dg2: NOTRUN -> [SKIP][248] ([i915#5461] / [i915#658]) [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html * igt@kms_rotation_crc@bad-pixel-format: - shard-snb: NOTRUN -> [SKIP][249] ([fdo#109271]) +111 other tests skip [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-snb4/igt@kms_rotation_crc@bad-pixel-format.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270: - shard-dg2: NOTRUN -> [SKIP][250] ([i915#4235] / [i915#5190]) [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270: - shard-mtlp: NOTRUN -> [SKIP][251] ([i915#4235]) +1 other test skip [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0: - shard-dg2: NOTRUN -> [SKIP][252] ([i915#4235]) [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html * igt@kms_setmode@invalid-clone-single-crtc-stealing: - shard-rkl: NOTRUN -> [SKIP][253] ([i915#3555] / [i915#4098]) [253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@kms_setmode@invalid-clone-single-crtc-stealing.html - shard-mtlp: NOTRUN -> [SKIP][254] ([i915#3555] / [i915#8809]) [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-5/igt@kms_setmode@invalid-clone-single-crtc-stealing.html * igt@kms_tiled_display@basic-test-pattern: - shard-mtlp: NOTRUN -> [SKIP][255] ([i915#8623]) [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@kms_tiled_display@basic-test-pattern.html - shard-rkl: NOTRUN -> [SKIP][256] ([i915#8623]) [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@kms_tiled_display@basic-test-pattern.html * igt@kms_universal_plane@cursor-fb-leak-pipe-a: - shard-snb: [PASS][257] -> [FAIL][258] ([i915#9196]) [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-snb5/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-snb4/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html * igt@kms_universal_plane@cursor-fb-leak-pipe-b: - shard-tglu: [PASS][259] -> [FAIL][260] ([i915#9196]) +1 other test fail [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html * igt@kms_universal_plane@cursor-fb-leak-pipe-d: - shard-mtlp: NOTRUN -> [FAIL][261] ([i915#9196]) [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@kms_universal_plane@cursor-fb-leak-pipe-d.html * igt@kms_universal_plane@universal-plane-pipe-d-functional: - shard-rkl: NOTRUN -> [SKIP][262] ([i915#4070] / [i915#533] / [i915#6768]) +2 other tests skip [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-2/igt@kms_universal_plane@universal-plane-pipe-d-functional.html * igt@kms_vblank@pipe-c-ts-continuation-modeset-hang: - shard-mtlp: [PASS][263] -> [DMESG-WARN][264] ([i915#2017]) [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-mtlp-4/igt@kms_vblank@pipe-c-ts-continuation-modeset-hang.html [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-2/igt@kms_vblank@pipe-c-ts-continuation-modeset-hang.html * igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm: - shard-rkl: NOTRUN -> [SKIP][265] ([i915#4070] / [i915#6768]) +3 other tests skip [265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-4/igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-mtlp: NOTRUN -> [ABORT][266] ([i915#9262]) +7 other tests abort [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html * igt@kms_writeback@writeback-invalid-parameters: - shard-mtlp: NOTRUN -> [SKIP][267] ([i915#2437]) [267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-3/igt@kms_writeback@writeback-invalid-parameters.html * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-mtlp: NOTRUN -> [SKIP][268] ([fdo#109289]) +7 other tests skip [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-3/igt@perf@gen8-unprivileged-single-ctx-counters.html * igt@perf@global-sseu-config: - shard-dg2: NOTRUN -> [SKIP][269] ([i915#7387]) [269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@perf@global-sseu-config.html * igt@perf@mi-rpc: - shard-dg2: NOTRUN -> [SKIP][270] ([i915#2434]) [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-10/igt@perf@mi-rpc.html * igt@perf@unprivileged-single-ctx-counters: - shard-tglu: NOTRUN -> [SKIP][271] ([fdo#109289]) [271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-8/igt@perf@unprivileged-single-ctx-counters.html * igt@perf_pmu@busy-double-start@vecs1: - shard-dg2: NOTRUN -> [FAIL][272] ([i915#4349]) +3 other tests fail [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-3/igt@perf_pmu@busy-double-start@vecs1.html * igt@perf_pmu@cpu-hotplug: - shard-mtlp: NOTRUN -> [SKIP][273] ([i915#8850]) [273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-4/igt@perf_pmu@cpu-hotplug.html * igt@perf_pmu@event-wait@rcs0: - shard-rkl: NOTRUN -> [SKIP][274] ([fdo#112283]) +1 other test skip [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@perf_pmu@event-wait@rcs0.html - shard-mtlp: NOTRUN -> [SKIP][275] ([i915#8807]) [275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@perf_pmu@event-wait@rcs0.html * igt@perf_pmu@frequency@gt0: - shard-dg2: [PASS][276] -> [FAIL][277] ([i915#6806]) [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-2/igt@perf_pmu@frequency@gt0.html [277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@perf_pmu@frequency@gt0.html - shard-dg1: [PASS][278] -> [FAIL][279] ([i915#6806]) [278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg1-17/igt@perf_pmu@frequency@gt0.html [279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-15/igt@perf_pmu@frequency@gt0.html * igt@perf_pmu@module-unload: - shard-dg2: NOTRUN -> [FAIL][280] ([i915#5793]) [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@perf_pmu@module-unload.html * igt@prime_udl: - shard-mtlp: NOTRUN -> [SKIP][281] ([fdo#109291]) [281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@prime_udl.html * igt@prime_vgem@basic-fence-read: - shard-mtlp: NOTRUN -> [SKIP][282] ([i915#3708]) +1 other test skip [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-8/igt@prime_vgem@basic-fence-read.html * igt@prime_vgem@basic-gtt: - shard-mtlp: NOTRUN -> [SKIP][283] ([i915#3708] / [i915#4077]) [283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-7/igt@prime_vgem@basic-gtt.html * igt@prime_vgem@basic-write: - shard-rkl: NOTRUN -> [SKIP][284] ([fdo#109295] / [i915#3291] / [i915#3708]) [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@prime_vgem@basic-write.html * igt@sysfs_preempt_timeout@timeout@vecs0: - shard-mtlp: NOTRUN -> [ABORT][285] ([i915#8521] / [i915#8865]) [285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@sysfs_preempt_timeout@timeout@vecs0.html * igt@tools_test@sysfs_l3_parity: - shard-mtlp: NOTRUN -> [SKIP][286] ([i915#4818]) [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-4/igt@tools_test@sysfs_l3_parity.html * igt@v3d/v3d_perfmon@create-perfmon-exceed: - shard-dg1: NOTRUN -> [SKIP][287] ([i915#2575]) +1 other test skip [287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-19/igt@v3d/v3d_perfmon@create-perfmon-exceed.html * igt@v3d/v3d_submit_cl@bad-multisync-extension: - shard-apl: NOTRUN -> [SKIP][288] ([fdo#109271]) +50 other tests skip [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-apl2/igt@v3d/v3d_submit_cl@bad-multisync-extension.html * igt@v3d/v3d_submit_cl@bad-multisync-in-sync: - shard-rkl: NOTRUN -> [SKIP][289] ([fdo#109315]) +10 other tests skip [289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@v3d/v3d_submit_cl@bad-multisync-in-sync.html * igt@v3d/v3d_submit_cl@bad-multisync-out-sync: - shard-dg2: NOTRUN -> [SKIP][290] ([i915#2575]) +11 other tests skip [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@v3d/v3d_submit_cl@bad-multisync-out-sync.html * igt@v3d/v3d_submit_cl@bad-multisync-pad: - shard-mtlp: NOTRUN -> [SKIP][291] ([i915#2575]) +19 other tests skip [291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-6/igt@v3d/v3d_submit_cl@bad-multisync-pad.html * igt@v3d/v3d_submit_csd@bad-flag: - shard-tglu: NOTRUN -> [SKIP][292] ([fdo#109315] / [i915#2575]) +1 other test skip [292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-3/igt@v3d/v3d_submit_csd@bad-flag.html * igt@vc4/vc4_mmap@mmap-bo: - shard-dg2: NOTRUN -> [SKIP][293] ([i915#7711]) +8 other tests skip [293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@vc4/vc4_mmap@mmap-bo.html * igt@vc4/vc4_purgeable_bo@mark-purgeable-twice: - shard-mtlp: NOTRUN -> [SKIP][294] ([i915#7711]) +11 other tests skip [294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@vc4/vc4_purgeable_bo@mark-purgeable-twice.html * igt@vc4/vc4_tiling@get-bad-modifier: - shard-rkl: NOTRUN -> [SKIP][295] ([i915#7711]) +6 other tests skip [295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-1/igt@vc4/vc4_tiling@get-bad-modifier.html * igt@vc4/vc4_wait_bo@used-bo-1ns: - shard-dg1: NOTRUN -> [SKIP][296] ([i915#7711]) +1 other test skip [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-17/igt@vc4/vc4_wait_bo@used-bo-1ns.html #### Possible fixes #### * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [FAIL][297] ([i915#7742]) -> [PASS][298] +1 other test pass [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html [298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@drm_fdinfo@most-busy-check-all@rcs0.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-rkl: [FAIL][299] ([i915#6268]) -> [PASS][300] [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html * igt@gem_exec_endless@dispatch@vcs1: - shard-tglu: [TIMEOUT][301] ([i915#3778]) -> [PASS][302] [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-tglu-2/igt@gem_exec_endless@dispatch@vcs1.html [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-6/igt@gem_exec_endless@dispatch@vcs1.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglu: [FAIL][303] ([i915#2842]) -> [PASS][304] [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-tglu-6/igt@gem_exec_fair@basic-flow@rcs0.html [304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-9/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [FAIL][305] ([i915#2842]) -> [PASS][306] [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html [306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_flush@basic-batch-kernel-default-uc: - shard-mtlp: [DMESG-FAIL][307] ([i915#8962]) -> [PASS][308] [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-mtlp-4/igt@gem_exec_flush@basic-batch-kernel-default-uc.html [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-1/igt@gem_exec_flush@basic-batch-kernel-default-uc.html * igt@gem_lmem_swapping@smem-oom@lmem0: - shard-dg2: [TIMEOUT][309] ([i915#5493]) -> [PASS][310] [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html [310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@gem_lmem_swapping@smem-oom@lmem0.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-dg2: [SKIP][311] ([i915#1397]) -> [PASS][312] [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-10/igt@i915_pm_rpm@dpms-non-lpsp.html [312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-6/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@i915_pm_rps@reset: - shard-dg1: [FAIL][313] -> [PASS][314] [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg1-12/igt@i915_pm_rps@reset.html [314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-17/igt@i915_pm_rps@reset.html * igt@i915_suspend@basic-s2idle-without-i915: - shard-dg1: [DMESG-WARN][315] ([i915#4391] / [i915#4423]) -> [PASS][316] [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg1-17/igt@i915_suspend@basic-s2idle-without-i915.html [316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-16/igt@i915_suspend@basic-s2idle-without-i915.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-tglu: [FAIL][317] ([i915#3743]) -> [PASS][318] +1 other test pass [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-tglu-10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html [318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-apl: [FAIL][319] ([i915#2346]) -> [PASS][320] [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: - shard-dg2: [FAIL][321] ([i915#6880]) -> [PASS][322] +2 other tests pass [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html [322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt: - shard-snb: [SKIP][323] ([fdo#109271]) -> [PASS][324] +1 other test pass [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-snb1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt.html [324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-snb1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt.html * {igt@kms_pm_dc@dc6-dpms}: - shard-tglu: [FAIL][325] ([i915#9295]) -> [PASS][326] [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-tglu-4/igt@kms_pm_dc@dc6-dpms.html [326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-9/igt@kms_pm_dc@dc6-dpms.html * {igt@kms_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a}: - shard-rkl: [SKIP][327] ([i915#1937]) -> [PASS][328] [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html [328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@kms_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90: - shard-rkl: [INCOMPLETE][329] ([i915#8875]) -> [PASS][330] +1 other test pass [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-rkl-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html [330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html * igt@kms_universal_plane@cursor-fb-leak-pipe-b: - shard-mtlp: [FAIL][331] ([i915#9196]) -> [PASS][332] [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-mtlp-3/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html [332]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-mtlp-3/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-apl: [INCOMPLETE][333] ([i915#180] / [i915#9392]) -> [PASS][334] [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [334]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-apl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt@perf_pmu@frequency@gt0: - shard-apl: [SKIP][335] ([fdo#109271]) -> [PASS][336] [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-apl7/igt@perf_pmu@frequency@gt0.html [336]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-apl7/igt@perf_pmu@frequency@gt0.html - shard-glk: [SKIP][337] ([fdo#109271]) -> [PASS][338] [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-glk9/igt@perf_pmu@frequency@gt0.html [338]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-glk1/igt@perf_pmu@frequency@gt0.html #### Warnings #### * igt@i915_module_load@reload-with-fault-injection: - shard-dg2: [DMESG-WARN][339] ([i915#8617]) -> [WARN][340] ([i915#7356]) [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-11/igt@i915_module_load@reload-with-fault-injection.html [340]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_pm_rps@reset: - shard-tglu: [FAIL][341] -> [INCOMPLETE][342] ([i915#8320]) [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-tglu-2/igt@i915_pm_rps@reset.html [342]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-tglu-8/igt@i915_pm_rps@reset.html * igt@i915_suspend@debugfs-reader: - shard-snb: [DMESG-WARN][343] ([i915#8841]) -> [DMESG-FAIL][344] ([fdo#103375]) [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-snb7/igt@i915_suspend@debugfs-reader.html [344]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-snb7/igt@i915_suspend@debugfs-reader.html * igt@kms_content_protection@mei_interface: - shard-dg2: [SKIP][345] ([i915#7118]) -> [SKIP][346] ([i915#7118] / [i915#7162]) [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg2-6/igt@kms_content_protection@mei_interface.html [346]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg2-11/igt@kms_content_protection@mei_interface.html * igt@kms_force_connector_basic@force-load-detect: - shard-rkl: [SKIP][347] ([fdo#109285] / [i915#4098]) -> [SKIP][348] ([fdo#109285]) [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-rkl-2/igt@kms_force_connector_basic@force-load-detect.html [348]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt: - shard-dg1: [SKIP][349] ([i915#4423] / [i915#8708]) -> [SKIP][350] ([i915#8708]) [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html [350]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_multipipe_modeset@basic-max-pipe-crc-check: - shard-rkl: [SKIP][351] ([i915#4816]) -> [SKIP][352] ([i915#4070] / [i915#4816]) [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html [352]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html * igt@kms_psr@cursor_plane_move: - shard-dg1: [SKIP][353] ([i915#1072]) -> [SKIP][354] ([i915#1072] / [i915#4078]) [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg1-14/igt@kms_psr@cursor_plane_move.html [354]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-12/igt@kms_psr@cursor_plane_move.html * igt@kms_psr@sprite_plane_onoff: - shard-dg1: [SKIP][355] ([i915#1072] / [i915#4078]) -> [SKIP][356] ([i915#1072]) [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/shard-dg1-12/igt@kms_psr@sprite_plane_onoff.html [356]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/shard-dg1-19/igt@kms_psr@sprite_plane_onoff.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#1339]: https://gitlab.freedesktop.org/drm/intel/issues/1339 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 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https://gitlab.freedesktop.org/drm/intel/issues/9227 [i915#9257]: https://gitlab.freedesktop.org/drm/intel/issues/9257 [i915#9261]: https://gitlab.freedesktop.org/drm/intel/issues/9261 [i915#9262]: https://gitlab.freedesktop.org/drm/intel/issues/9262 [i915#9293]: https://gitlab.freedesktop.org/drm/intel/issues/9293 [i915#9295]: https://gitlab.freedesktop.org/drm/intel/issues/9295 [i915#9298]: https://gitlab.freedesktop.org/drm/intel/issues/9298 [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318 [i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323 [i915#9337]: https://gitlab.freedesktop.org/drm/intel/issues/9337 [i915#9392]: https://gitlab.freedesktop.org/drm/intel/issues/9392 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7503 -> IGTPW_9879 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_13681: b57407d0de043fc22b000a941a404ab103849e06 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_9879: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/index.html IGT_7503: 7503 piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9879/index.html [-- Attachment #2: Type: text/html, Size: 115216 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands
@ 2023-10-16 18:07 sai.gowtham.ch
2023-10-16 18:07 ` [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: " sai.gowtham.ch
0 siblings, 1 reply; 13+ messages in thread
From: sai.gowtham.ch @ 2023-10-16 18:07 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, karolina.stolarek, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Add copy basic test which exercies mem-se and mem-copy commands, this
patch series involves in following changes:
1. Add copy basic test to exercise blt commands.
2. Add wrappers for batch preparation and submit exec.
3. Add copy commands MEM_SET_CMD and MEM_COPY_CMD in the lib.
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Sai Gowtham Ch (3):
lib/intel_blt: Add wrappers to prepare batch buffers and submit exec
lib/intel_cmds_info: Add M_MATRIX in mem_copy as it is supported for
PVC
intel/xe_copy_basic: Add copy basic test to exercise blt commands
lib/intel_blt.c | 200 ++++++++++++++++++++++++++++++++++++
lib/intel_blt.h | 39 +++++++
lib/intel_cmds_info.c | 3 +-
lib/intel_reg.h | 4 +
tests/intel/xe_copy_basic.c | 192 ++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
6 files changed, 438 insertions(+), 1 deletion(-)
create mode 100644 tests/intel/xe_copy_basic.c
--
2.39.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: Add copy basic test to exercise blt commands 2023-10-16 18:07 [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands sai.gowtham.ch @ 2023-10-16 18:07 ` sai.gowtham.ch 2023-10-17 9:00 ` Zbigniew Kempczyński 0 siblings, 1 reply; 13+ messages in thread From: sai.gowtham.ch @ 2023-10-16 18:07 UTC (permalink / raw) To: igt-dev, zbigniew.kempczynski, karolina.stolarek, sai.gowtham.ch From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Add copy basic test to exercise copy commands like mem-copy and mem-set. Cc: Karolina Stolarek <karolina.stolarek@intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> --- tests/intel/xe_copy_basic.c | 192 ++++++++++++++++++++++++++++++++++++ tests/meson.build | 1 + 2 files changed, 193 insertions(+) create mode 100644 tests/intel/xe_copy_basic.c diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c new file mode 100644 index 000000000..253631102 --- /dev/null +++ b/tests/intel/xe_copy_basic.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2023 Intel Corporation + * + * Authors: + * Sai Gowtham Ch <sai.gowtham.ch@intel.com> + */ + +#include "igt.h" +#include "lib/igt_syncobj.h" +#include "intel_blt.h" +#include "lib/intel_cmds_info.h" +#include "lib/intel_mocs.h" +#include "lib/intel_reg.h" +#include "xe/xe_ioctl.h" +#include "xe/xe_query.h" +#include "xe/xe_util.h" + +#define MEM_FILL 0x8b + +/** + * TEST: Test to validate copy commands on xe + * Category: Software building block + * Sub-category: Copy + * Functionality: blitter + */ + +/** + * SUBTEST: mem-copy-linear-%s + * Description: Test validates MEM_COPY command, it takes various + * parameters needed for the filling batch buffer for MEM_COPY command + * with size %arg[1]. + * Test category: functionality test + * + * arg[1]: + * @0x369: 0x369 + * @0x3fff: 0x3fff + * @0xfd: 0xfd + * @0xfffe: 0xfffe + */ +static void +mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, + const intel_ctx_t *ctx, uint32_t size, uint32_t width, + uint32_t height, uint32_t region) +{ + struct blt_mem_data mem = {}; + uint64_t bb_size = xe_get_default_alignment(fd); + uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_LOW_TO_HIGH, 0); + uint32_t bb; + int result; + uint8_t src_mocs = intel_get_uc_mocs_index(fd); + uint8_t dst_mocs = src_mocs; + + bb = xe_bo_create_flags(fd, 0, bb_size, region); + + blt_mem_init(fd, &mem); + blt_set_mem_object(&mem.src, src_handle, size, 0, width, height, + region, src_mocs, M_LINEAR, COMPRESSION_DISABLED); + blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height, + region, dst_mocs, M_LINEAR, COMPRESSION_DISABLED); + mem.src.ptr = xe_bo_map(fd, src_handle, size); + mem.dst.ptr = xe_bo_map(fd, dst_handle, size); + + blt_set_batch(&mem.bb, bb, bb_size, region); + igt_assert(mem.src.width == mem.dst.width); + + blt_mem_copy(fd, ctx, NULL, ahnd, &mem); + result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size); + igt_assert_f(!result, "source and destination differ\n"); + + intel_allocator_bind(ahnd, 0, 0); + munmap(mem.src.ptr, size); + munmap(mem.dst.ptr, size); + gem_close(fd, bb); + put_ahnd(ahnd); +} + +/** + * SUBTEST: mem-set-linear-%s + * Description: Test validates MEM_SET command with size %arg[1]. + * Test category: functionality test + * + * arg[1]: + * + * @0x369: 0x369 + * @0x3fff: 0x3fff + * @0xfd: 0xfd + * @0xfffe: 0xfffe + */ +static void mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, + uint32_t size, uint32_t width, uint32_t height, + uint8_t fill_data, uint32_t region) +{ + struct blt_mem_data mem = {}; + uint64_t bb_size = xe_get_default_alignment(fd); + uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_LOW_TO_HIGH, 0); + uint32_t bb; + uint8_t *result; + uint8_t dst_mocs = intel_get_uc_mocs_index(fd); + + bb = xe_bo_create_flags(fd, 0, bb_size, region); + blt_mem_init(fd, &mem); + blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height, region, + dst_mocs, M_LINEAR, COMPRESSION_DISABLED); + mem.dst.ptr = xe_bo_map(fd, dst_handle, size); + blt_set_batch(&mem.bb, bb, bb_size, region); + blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data); + + result = (uint8_t *)mem.dst.ptr; + + igt_assert(result[0] == fill_data); + igt_assert(result[width - 1] == fill_data); + igt_assert(result[width] != fill_data); + + intel_allocator_bind(ahnd, 0, 0); + munmap(mem.dst.ptr, size); + gem_close(fd, bb); + put_ahnd(ahnd); +} + +static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region) +{ + struct drm_xe_engine_class_instance inst = { + .engine_class = DRM_XE_ENGINE_CLASS_COPY, + }; + uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size; + uint32_t bo_size = ALIGN(size, xe_get_default_alignment(fd)); + const intel_ctx_t *ctx; + + src_handle = xe_bo_create_flags(fd, 0, bo_size, region); + dst_handle = xe_bo_create_flags(fd, 0, bo_size, region); + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); + exec_queue = xe_exec_queue_create(fd, vm, &inst, 0); + ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0); + + src_size = bo_size; + dst_size = bo_size; + + if (cmd == MEM_COPY) + mem_copy(fd, src_handle, dst_handle, ctx, src_size, size, 1, region); + else if (cmd == MEM_SET) + mem_set(fd, dst_handle, ctx, dst_size, size, 1, MEM_FILL, region); + + gem_close(fd, src_handle); + gem_close(fd, dst_handle); + xe_exec_queue_destroy(fd, exec_queue); + xe_vm_destroy(fd, vm); +} + +igt_main +{ + int fd; + struct igt_collection *set, *regions; + uint32_t region; + uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFE}; + + igt_fixture { + fd = drm_open_driver(DRIVER_XE); + xe_device_get(fd); + set = xe_get_memory_region_set(fd, + XE_MEM_REGION_CLASS_SYSMEM, + XE_MEM_REGION_CLASS_VRAM); + } + + for (int i = 0; i < ARRAY_SIZE(size); i++) { + igt_subtest_f("mem-copy-linear-0x%lx", size[i]) { + igt_require(blt_has_mem_copy(fd)); + for_each_variation_r(regions, 1, set) { + region = igt_collection_get_value(regions, 0); + copy_test(fd, size[i], MEM_COPY, region); + } + } + } + + for (int i = 0; i < ARRAY_SIZE(size); i++) { + igt_subtest_f("mem-set-linear-0x%lx", size[i]) { + igt_require(blt_has_mem_set(fd)); + for_each_variation_r(regions, 1, set) { + region = igt_collection_get_value(regions, 0); + copy_test(fd, size[i], MEM_SET, region); + } + } + } + + igt_fixture { + drm_close_driver(fd); + } +} diff --git a/tests/meson.build b/tests/meson.build index 2c2e1ca9a..5b19994f7 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -275,6 +275,7 @@ intel_xe_progs = [ 'xe_ccs', 'xe_create', 'xe_compute', + 'xe_copy_basic', 'xe_dma_buf_sync', 'xe_debugfs', 'xe_drm_fdinfo', -- 2.39.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: Add copy basic test to exercise blt commands 2023-10-16 18:07 ` [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: " sai.gowtham.ch @ 2023-10-17 9:00 ` Zbigniew Kempczyński 0 siblings, 0 replies; 13+ messages in thread From: Zbigniew Kempczyński @ 2023-10-17 9:00 UTC (permalink / raw) To: sai.gowtham.ch; +Cc: igt-dev On Mon, Oct 16, 2023 at 11:37:16PM +0530, sai.gowtham.ch@intel.com wrote: > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> > > Add copy basic test to exercise copy commands like mem-copy and mem-set. > > Cc: Karolina Stolarek <karolina.stolarek@intel.com> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> > --- > tests/intel/xe_copy_basic.c | 192 ++++++++++++++++++++++++++++++++++++ > tests/meson.build | 1 + > 2 files changed, 193 insertions(+) > create mode 100644 tests/intel/xe_copy_basic.c > > diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c > new file mode 100644 > index 000000000..253631102 > --- /dev/null > +++ b/tests/intel/xe_copy_basic.c > @@ -0,0 +1,192 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2023 Intel Corporation > + * > + * Authors: > + * Sai Gowtham Ch <sai.gowtham.ch@intel.com> > + */ > + > +#include "igt.h" > +#include "lib/igt_syncobj.h" > +#include "intel_blt.h" > +#include "lib/intel_cmds_info.h" > +#include "lib/intel_mocs.h" > +#include "lib/intel_reg.h" > +#include "xe/xe_ioctl.h" > +#include "xe/xe_query.h" > +#include "xe/xe_util.h" > + > +#define MEM_FILL 0x8b > + > +/** > + * TEST: Test to validate copy commands on xe > + * Category: Software building block > + * Sub-category: Copy > + * Functionality: blitter > + */ > + > +/** > + * SUBTEST: mem-copy-linear-%s > + * Description: Test validates MEM_COPY command, it takes various > + * parameters needed for the filling batch buffer for MEM_COPY command > + * with size %arg[1]. > + * Test category: functionality test > + * > + * arg[1]: > + * @0x369: 0x369 > + * @0x3fff: 0x3fff > + * @0xfd: 0xfd > + * @0xfffe: 0xfffe > + */ > +static void > +mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, > + const intel_ctx_t *ctx, uint32_t size, uint32_t width, > + uint32_t height, uint32_t region) Here I got objections about formatting. > +{ > + struct blt_mem_data mem = {}; > + uint64_t bb_size = xe_get_default_alignment(fd); > + uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, > + INTEL_ALLOCATOR_SIMPLE, > + ALLOC_STRATEGY_LOW_TO_HIGH, 0); > + uint32_t bb; > + int result; > + uint8_t src_mocs = intel_get_uc_mocs_index(fd); > + uint8_t dst_mocs = src_mocs; > + > + bb = xe_bo_create_flags(fd, 0, bb_size, region); > + > + blt_mem_init(fd, &mem); > + blt_set_mem_object(&mem.src, src_handle, size, 0, width, height, > + region, src_mocs, M_LINEAR, COMPRESSION_DISABLED); > + blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height, > + region, dst_mocs, M_LINEAR, COMPRESSION_DISABLED); > + mem.src.ptr = xe_bo_map(fd, src_handle, size); > + mem.dst.ptr = xe_bo_map(fd, dst_handle, size); > + > + blt_set_batch(&mem.bb, bb, bb_size, region); > + igt_assert(mem.src.width == mem.dst.width); > + > + blt_mem_copy(fd, ctx, NULL, ahnd, &mem); > + result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size); > + igt_assert_f(!result, "source and destination differ\n"); > + > + intel_allocator_bind(ahnd, 0, 0); > + munmap(mem.src.ptr, size); > + munmap(mem.dst.ptr, size); > + gem_close(fd, bb); > + put_ahnd(ahnd); > +} > + > +/** > + * SUBTEST: mem-set-linear-%s > + * Description: Test validates MEM_SET command with size %arg[1]. > + * Test category: functionality test > + * > + * arg[1]: > + * > + * @0x369: 0x369 > + * @0x3fff: 0x3fff > + * @0xfd: 0xfd > + * @0xfffe: 0xfffe > + */ > +static void mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, > + uint32_t size, uint32_t width, uint32_t height, > + uint8_t fill_data, uint32_t region) And here. -- Zbigniew > +{ > + struct blt_mem_data mem = {}; > + uint64_t bb_size = xe_get_default_alignment(fd); > + uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, > + INTEL_ALLOCATOR_SIMPLE, > + ALLOC_STRATEGY_LOW_TO_HIGH, 0); > + uint32_t bb; > + uint8_t *result; > + uint8_t dst_mocs = intel_get_uc_mocs_index(fd); > + > + bb = xe_bo_create_flags(fd, 0, bb_size, region); > + blt_mem_init(fd, &mem); > + blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height, region, > + dst_mocs, M_LINEAR, COMPRESSION_DISABLED); > + mem.dst.ptr = xe_bo_map(fd, dst_handle, size); > + blt_set_batch(&mem.bb, bb, bb_size, region); > + blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data); > + > + result = (uint8_t *)mem.dst.ptr; > + > + igt_assert(result[0] == fill_data); > + igt_assert(result[width - 1] == fill_data); > + igt_assert(result[width] != fill_data); > + > + intel_allocator_bind(ahnd, 0, 0); > + munmap(mem.dst.ptr, size); > + gem_close(fd, bb); > + put_ahnd(ahnd); > +} > + > +static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region) > +{ > + struct drm_xe_engine_class_instance inst = { > + .engine_class = DRM_XE_ENGINE_CLASS_COPY, > + }; > + uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size; > + uint32_t bo_size = ALIGN(size, xe_get_default_alignment(fd)); > + const intel_ctx_t *ctx; > + > + src_handle = xe_bo_create_flags(fd, 0, bo_size, region); > + dst_handle = xe_bo_create_flags(fd, 0, bo_size, region); > + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); > + exec_queue = xe_exec_queue_create(fd, vm, &inst, 0); > + ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0); > + > + src_size = bo_size; > + dst_size = bo_size; > + > + if (cmd == MEM_COPY) > + mem_copy(fd, src_handle, dst_handle, ctx, src_size, size, 1, region); > + else if (cmd == MEM_SET) > + mem_set(fd, dst_handle, ctx, dst_size, size, 1, MEM_FILL, region); > + > + gem_close(fd, src_handle); > + gem_close(fd, dst_handle); > + xe_exec_queue_destroy(fd, exec_queue); > + xe_vm_destroy(fd, vm); > +} > + > +igt_main > +{ > + int fd; > + struct igt_collection *set, *regions; > + uint32_t region; > + uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFE}; > + > + igt_fixture { > + fd = drm_open_driver(DRIVER_XE); > + xe_device_get(fd); > + set = xe_get_memory_region_set(fd, > + XE_MEM_REGION_CLASS_SYSMEM, > + XE_MEM_REGION_CLASS_VRAM); > + } > + > + for (int i = 0; i < ARRAY_SIZE(size); i++) { > + igt_subtest_f("mem-copy-linear-0x%lx", size[i]) { > + igt_require(blt_has_mem_copy(fd)); > + for_each_variation_r(regions, 1, set) { > + region = igt_collection_get_value(regions, 0); > + copy_test(fd, size[i], MEM_COPY, region); > + } > + } > + } > + > + for (int i = 0; i < ARRAY_SIZE(size); i++) { > + igt_subtest_f("mem-set-linear-0x%lx", size[i]) { > + igt_require(blt_has_mem_set(fd)); > + for_each_variation_r(regions, 1, set) { > + region = igt_collection_get_value(regions, 0); > + copy_test(fd, size[i], MEM_SET, region); > + } > + } > + } > + > + igt_fixture { > + drm_close_driver(fd); > + } > +} > diff --git a/tests/meson.build b/tests/meson.build > index 2c2e1ca9a..5b19994f7 100644 > --- a/tests/meson.build > +++ b/tests/meson.build > @@ -275,6 +275,7 @@ intel_xe_progs = [ > 'xe_ccs', > 'xe_create', > 'xe_compute', > + 'xe_copy_basic', > 'xe_dma_buf_sync', > 'xe_debugfs', > 'xe_drm_fdinfo', > -- > 2.39.1 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands
@ 2023-10-17 14:05 sai.gowtham.ch
2023-10-17 14:05 ` [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: " sai.gowtham.ch
0 siblings, 1 reply; 13+ messages in thread
From: sai.gowtham.ch @ 2023-10-17 14:05 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, karolina.stolarek, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Add copy basic test which exercies mem-se and mem-copy commands, this
patch series involves in following changes:
1. Add copy basic test to exercise blt commands.
2. Add wrappers for batch preparation and submit exec.
3. Add copy commands MEM_SET_CMD and MEM_COPY_CMD in the lib.
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Sai Gowtham Ch (3):
lib/intel_blt: Add wrappers to prepare batch buffers and submit exec
lib/intel_cmds_info: Add M_MATRIX in mem_copy as it is supported for
PVC
intel/xe_copy_basic: Add copy basic test to exercise blt commands
lib/intel_blt.c | 200 ++++++++++++++++++++++++++++++++++++
lib/intel_blt.h | 39 +++++++
lib/intel_cmds_info.c | 3 +-
lib/intel_reg.h | 4 +
tests/intel/xe_copy_basic.c | 191 ++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
6 files changed, 437 insertions(+), 1 deletion(-)
create mode 100644 tests/intel/xe_copy_basic.c
--
2.39.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: Add copy basic test to exercise blt commands 2023-10-17 14:05 [igt-dev] [PATCH i-g-t 0/3] " sai.gowtham.ch @ 2023-10-17 14:05 ` sai.gowtham.ch 2023-10-18 10:53 ` Zbigniew Kempczyński 0 siblings, 1 reply; 13+ messages in thread From: sai.gowtham.ch @ 2023-10-17 14:05 UTC (permalink / raw) To: igt-dev, zbigniew.kempczynski, karolina.stolarek, sai.gowtham.ch From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Add copy basic test to exercise copy commands like mem-copy and mem-set. Cc: Karolina Stolarek <karolina.stolarek@intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> --- tests/intel/xe_copy_basic.c | 191 ++++++++++++++++++++++++++++++++++++ tests/meson.build | 1 + 2 files changed, 192 insertions(+) create mode 100644 tests/intel/xe_copy_basic.c diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c new file mode 100644 index 000000000..c26336ae3 --- /dev/null +++ b/tests/intel/xe_copy_basic.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2023 Intel Corporation + * + * Authors: + * Sai Gowtham Ch <sai.gowtham.ch@intel.com> + */ + +#include "igt.h" +#include "lib/igt_syncobj.h" +#include "intel_blt.h" +#include "lib/intel_cmds_info.h" +#include "lib/intel_mocs.h" +#include "lib/intel_reg.h" +#include "xe/xe_ioctl.h" +#include "xe/xe_query.h" +#include "xe/xe_util.h" + +#define MEM_FILL 0x8b + +/** + * TEST: Test to validate copy commands on xe + * Category: Software building block + * Sub-category: Copy + * Functionality: blitter + */ + +/** + * SUBTEST: mem-copy-linear-%s + * Description: Test validates MEM_COPY command, it takes various + * parameters needed for the filling batch buffer for MEM_COPY command + * with size %arg[1]. + * Test category: functionality test + * + * arg[1]: + * @0x369: 0x369 + * @0x3fff: 0x3fff + * @0xfd: 0xfd + * @0xfffe: 0xfffe + */ +static void +mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx, + uint32_t size, uint32_t width, uint32_t height, uint32_t region) +{ + struct blt_mem_data mem = {}; + uint64_t bb_size = xe_get_default_alignment(fd); + uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_LOW_TO_HIGH, 0); + uint32_t bb; + int result; + uint8_t src_mocs = intel_get_uc_mocs_index(fd); + uint8_t dst_mocs = src_mocs; + + bb = xe_bo_create_flags(fd, 0, bb_size, region); + + blt_mem_init(fd, &mem); + blt_set_mem_object(&mem.src, src_handle, size, 0, width, height, + region, src_mocs, M_LINEAR, COMPRESSION_DISABLED); + blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height, + region, dst_mocs, M_LINEAR, COMPRESSION_DISABLED); + mem.src.ptr = xe_bo_map(fd, src_handle, size); + mem.dst.ptr = xe_bo_map(fd, dst_handle, size); + + blt_set_batch(&mem.bb, bb, bb_size, region); + igt_assert(mem.src.width == mem.dst.width); + + blt_mem_copy(fd, ctx, NULL, ahnd, &mem); + result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size); + igt_assert_f(!result, "source and destination differ\n"); + + intel_allocator_bind(ahnd, 0, 0); + munmap(mem.src.ptr, size); + munmap(mem.dst.ptr, size); + gem_close(fd, bb); + put_ahnd(ahnd); +} + +/** + * SUBTEST: mem-set-linear-%s + * Description: Test validates MEM_SET command with size %arg[1]. + * Test category: functionality test + * + * arg[1]: + * + * @0x369: 0x369 + * @0x3fff: 0x3fff + * @0xfd: 0xfd + * @0xfffe: 0xfffe + */ +static void +mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, uint32_t size, + uint32_t width, uint32_t height, uint8_t fill_data, uint32_t region) +{ + struct blt_mem_data mem = {}; + uint64_t bb_size = xe_get_default_alignment(fd); + uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_LOW_TO_HIGH, 0); + uint32_t bb; + uint8_t *result; + uint8_t dst_mocs = intel_get_uc_mocs_index(fd); + + bb = xe_bo_create_flags(fd, 0, bb_size, region); + blt_mem_init(fd, &mem); + blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height, region, + dst_mocs, M_LINEAR, COMPRESSION_DISABLED); + mem.dst.ptr = xe_bo_map(fd, dst_handle, size); + blt_set_batch(&mem.bb, bb, bb_size, region); + blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data); + + result = (uint8_t *)mem.dst.ptr; + + igt_assert(result[0] == fill_data); + igt_assert(result[width - 1] == fill_data); + igt_assert(result[width] != fill_data); + + intel_allocator_bind(ahnd, 0, 0); + munmap(mem.dst.ptr, size); + gem_close(fd, bb); + put_ahnd(ahnd); +} + +static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region) +{ + struct drm_xe_engine_class_instance inst = { + .engine_class = DRM_XE_ENGINE_CLASS_COPY, + }; + uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size; + uint32_t bo_size = ALIGN(size, xe_get_default_alignment(fd)); + const intel_ctx_t *ctx; + + src_handle = xe_bo_create_flags(fd, 0, bo_size, region); + dst_handle = xe_bo_create_flags(fd, 0, bo_size, region); + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0); + exec_queue = xe_exec_queue_create(fd, vm, &inst, 0); + ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0); + + src_size = bo_size; + dst_size = bo_size; + + if (cmd == MEM_COPY) + mem_copy(fd, src_handle, dst_handle, ctx, src_size, size, 1, region); + else if (cmd == MEM_SET) + mem_set(fd, dst_handle, ctx, dst_size, size, 1, MEM_FILL, region); + + gem_close(fd, src_handle); + gem_close(fd, dst_handle); + xe_exec_queue_destroy(fd, exec_queue); + xe_vm_destroy(fd, vm); +} + +igt_main +{ + int fd; + struct igt_collection *set, *regions; + uint32_t region; + uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFE}; + + igt_fixture { + fd = drm_open_driver(DRIVER_XE); + xe_device_get(fd); + set = xe_get_memory_region_set(fd, + XE_MEM_REGION_CLASS_SYSMEM, + XE_MEM_REGION_CLASS_VRAM); + } + + for (int i = 0; i < ARRAY_SIZE(size); i++) { + igt_subtest_f("mem-copy-linear-0x%lx", size[i]) { + igt_require(blt_has_mem_copy(fd)); + for_each_variation_r(regions, 1, set) { + region = igt_collection_get_value(regions, 0); + copy_test(fd, size[i], MEM_COPY, region); + } + } + } + + for (int i = 0; i < ARRAY_SIZE(size); i++) { + igt_subtest_f("mem-set-linear-0x%lx", size[i]) { + igt_require(blt_has_mem_set(fd)); + for_each_variation_r(regions, 1, set) { + region = igt_collection_get_value(regions, 0); + copy_test(fd, size[i], MEM_SET, region); + } + } + } + + igt_fixture { + drm_close_driver(fd); + } +} diff --git a/tests/meson.build b/tests/meson.build index 14b5bfda2..5afcd8cbb 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -275,6 +275,7 @@ intel_xe_progs = [ 'xe_ccs', 'xe_create', 'xe_compute', + 'xe_copy_basic', 'xe_dma_buf_sync', 'xe_debugfs', 'xe_drm_fdinfo', -- 2.39.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: Add copy basic test to exercise blt commands 2023-10-17 14:05 ` [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: " sai.gowtham.ch @ 2023-10-18 10:53 ` Zbigniew Kempczyński 0 siblings, 0 replies; 13+ messages in thread From: Zbigniew Kempczyński @ 2023-10-18 10:53 UTC (permalink / raw) To: sai.gowtham.ch; +Cc: igt-dev On Tue, Oct 17, 2023 at 07:35:30PM +0530, sai.gowtham.ch@intel.com wrote: > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> > > Add copy basic test to exercise copy commands like mem-copy and mem-set. > > Cc: Karolina Stolarek <karolina.stolarek@intel.com> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> > --- > tests/intel/xe_copy_basic.c | 191 ++++++++++++++++++++++++++++++++++++ > tests/meson.build | 1 + > 2 files changed, 192 insertions(+) > create mode 100644 tests/intel/xe_copy_basic.c > > diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c > new file mode 100644 > index 000000000..c26336ae3 > --- /dev/null > +++ b/tests/intel/xe_copy_basic.c > @@ -0,0 +1,191 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2023 Intel Corporation > + * > + * Authors: > + * Sai Gowtham Ch <sai.gowtham.ch@intel.com> > + */ > + > +#include "igt.h" > +#include "lib/igt_syncobj.h" > +#include "intel_blt.h" > +#include "lib/intel_cmds_info.h" > +#include "lib/intel_mocs.h" > +#include "lib/intel_reg.h" > +#include "xe/xe_ioctl.h" > +#include "xe/xe_query.h" > +#include "xe/xe_util.h" > + > +#define MEM_FILL 0x8b > + > +/** > + * TEST: Test to validate copy commands on xe > + * Category: Software building block > + * Sub-category: Copy > + * Functionality: blitter > + */ > + > +/** > + * SUBTEST: mem-copy-linear-%s > + * Description: Test validates MEM_COPY command, it takes various > + * parameters needed for the filling batch buffer for MEM_COPY command > + * with size %arg[1]. > + * Test category: functionality test > + * > + * arg[1]: > + * @0x369: 0x369 > + * @0x3fff: 0x3fff > + * @0xfd: 0xfd > + * @0xfffe: 0xfffe > + */ > +static void > +mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx, > + uint32_t size, uint32_t width, uint32_t height, uint32_t region) > +{ > + struct blt_mem_data mem = {}; > + uint64_t bb_size = xe_get_default_alignment(fd); > + uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, > + INTEL_ALLOCATOR_SIMPLE, > + ALLOC_STRATEGY_LOW_TO_HIGH, 0); > + uint32_t bb; > + int result; > + uint8_t src_mocs = intel_get_uc_mocs_index(fd); > + uint8_t dst_mocs = src_mocs; For better look unitialized values should be last in this block (bb and result). > + > + bb = xe_bo_create_flags(fd, 0, bb_size, region); > + > + blt_mem_init(fd, &mem); > + blt_set_mem_object(&mem.src, src_handle, size, 0, width, height, > + region, src_mocs, M_LINEAR, COMPRESSION_DISABLED); > + blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height, > + region, dst_mocs, M_LINEAR, COMPRESSION_DISABLED); > + mem.src.ptr = xe_bo_map(fd, src_handle, size); > + mem.dst.ptr = xe_bo_map(fd, dst_handle, size); > + > + blt_set_batch(&mem.bb, bb, bb_size, region); > + igt_assert(mem.src.width == mem.dst.width); > + > + blt_mem_copy(fd, ctx, NULL, ahnd, &mem); > + result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size); > + igt_assert_f(!result, "source and destination differ\n"); You have result here, so to avoid keeping resources migrate assert after cleanup. > + > + intel_allocator_bind(ahnd, 0, 0); > + munmap(mem.src.ptr, size); > + munmap(mem.dst.ptr, size); > + gem_close(fd, bb); > + put_ahnd(ahnd); I mean here. > +} > + > +/** > + * SUBTEST: mem-set-linear-%s > + * Description: Test validates MEM_SET command with size %arg[1]. > + * Test category: functionality test > + * > + * arg[1]: > + * > + * @0x369: 0x369 > + * @0x3fff: 0x3fff > + * @0xfd: 0xfd > + * @0xfffe: 0xfffe > + */ > +static void > +mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, uint32_t size, > + uint32_t width, uint32_t height, uint8_t fill_data, uint32_t region) > +{ > + struct blt_mem_data mem = {}; > + uint64_t bb_size = xe_get_default_alignment(fd); > + uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, > + INTEL_ALLOCATOR_SIMPLE, > + ALLOC_STRATEGY_LOW_TO_HIGH, 0); > + uint32_t bb; > + uint8_t *result; > + uint8_t dst_mocs = intel_get_uc_mocs_index(fd); Same like above. > + > + bb = xe_bo_create_flags(fd, 0, bb_size, region); > + blt_mem_init(fd, &mem); > + blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height, region, > + dst_mocs, M_LINEAR, COMPRESSION_DISABLED); > + mem.dst.ptr = xe_bo_map(fd, dst_handle, size); > + blt_set_batch(&mem.bb, bb, bb_size, region); > + blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data); > + > + result = (uint8_t *)mem.dst.ptr; > + > + igt_assert(result[0] == fill_data); > + igt_assert(result[width - 1] == fill_data); > + igt_assert(result[width] != fill_data); Keep those asserts here at cost of some mess. > + > + intel_allocator_bind(ahnd, 0, 0); > + munmap(mem.dst.ptr, size); > + gem_close(fd, bb); > + put_ahnd(ahnd); > +} > + > +static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region) > +{ > + struct drm_xe_engine_class_instance inst = { > + .engine_class = DRM_XE_ENGINE_CLASS_COPY, > + }; > + uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size; > + uint32_t bo_size = ALIGN(size, xe_get_default_alignment(fd)); > + const intel_ctx_t *ctx; > + > + src_handle = xe_bo_create_flags(fd, 0, bo_size, region); > + dst_handle = xe_bo_create_flags(fd, 0, bo_size, region); > + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0); > + exec_queue = xe_exec_queue_create(fd, vm, &inst, 0); > + ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0); > + > + src_size = bo_size; > + dst_size = bo_size; > + > + if (cmd == MEM_COPY) > + mem_copy(fd, src_handle, dst_handle, ctx, src_size, size, 1, region); > + else if (cmd == MEM_SET) > + mem_set(fd, dst_handle, ctx, dst_size, size, 1, MEM_FILL, region); > + > + gem_close(fd, src_handle); > + gem_close(fd, dst_handle); > + xe_exec_queue_destroy(fd, exec_queue); > + xe_vm_destroy(fd, vm); free(ctx); Address those nits and merge: Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> -- Zbigniew > +} > + > +igt_main > +{ > + int fd; > + struct igt_collection *set, *regions; > + uint32_t region; > + uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFE}; > + > + igt_fixture { > + fd = drm_open_driver(DRIVER_XE); > + xe_device_get(fd); > + set = xe_get_memory_region_set(fd, > + XE_MEM_REGION_CLASS_SYSMEM, > + XE_MEM_REGION_CLASS_VRAM); > + } > + > + for (int i = 0; i < ARRAY_SIZE(size); i++) { > + igt_subtest_f("mem-copy-linear-0x%lx", size[i]) { > + igt_require(blt_has_mem_copy(fd)); > + for_each_variation_r(regions, 1, set) { > + region = igt_collection_get_value(regions, 0); > + copy_test(fd, size[i], MEM_COPY, region); > + } > + } > + } > + > + for (int i = 0; i < ARRAY_SIZE(size); i++) { > + igt_subtest_f("mem-set-linear-0x%lx", size[i]) { > + igt_require(blt_has_mem_set(fd)); > + for_each_variation_r(regions, 1, set) { > + region = igt_collection_get_value(regions, 0); > + copy_test(fd, size[i], MEM_SET, region); > + } > + } > + } > + > + igt_fixture { > + drm_close_driver(fd); > + } > +} > diff --git a/tests/meson.build b/tests/meson.build > index 14b5bfda2..5afcd8cbb 100644 > --- a/tests/meson.build > +++ b/tests/meson.build > @@ -275,6 +275,7 @@ intel_xe_progs = [ > 'xe_ccs', > 'xe_create', > 'xe_compute', > + 'xe_copy_basic', > 'xe_dma_buf_sync', > 'xe_debugfs', > 'xe_drm_fdinfo', > -- > 2.39.1 > ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-10-18 10:53 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-09-26 12:27 [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands sai.gowtham.ch 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add check to see if blt commands are supported by the platforms sai.gowtham.ch 2023-09-27 11:22 ` Zbigniew Kempczyński 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec sai.gowtham.ch 2023-09-27 11:36 ` Zbigniew Kempczyński 2023-09-26 12:27 ` [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: Add copy basic test to exercise blt commands sai.gowtham.ch 2023-09-26 13:49 ` [igt-dev] ✓ Fi.CI.BAT: success for Add copy basic test to exercise blt commands (rev4) Patchwork 2023-09-26 14:16 ` [igt-dev] ✓ CI.xeBAT: " Patchwork 2023-09-27 1:27 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2023-10-16 18:07 [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands sai.gowtham.ch 2023-10-16 18:07 ` [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: " sai.gowtham.ch 2023-10-17 9:00 ` Zbigniew Kempczyński 2023-10-17 14:05 [igt-dev] [PATCH i-g-t 0/3] " sai.gowtham.ch 2023-10-17 14:05 ` [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: " sai.gowtham.ch 2023-10-18 10:53 ` Zbigniew Kempczyński
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