* [igt-dev] [PATCH i-g-t] tests/intel/kms_flip_scaled_crc: Add support for FP16 format of MTL compressed modifier
@ 2023-10-11 9:55 Melanie Lobo
2023-10-11 13:15 ` Kamil Konieczny
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Melanie Lobo @ 2023-10-11 9:55 UTC (permalink / raw)
To: igt-dev; +Cc: juha-pekka.heikkila
MTL supports new FP16 format which is a binary floating-point computer
number format that occupies 16 bits in computer memory.
Change-Id: I7fa8169d54cbd9e6dcdf765065659e541a31e481
Signed-off-by: Melanie Lobo <melanie.lobo@intel.com>
---
lib/intel_aux_pgtable.c | 5 +++++
tests/intel/kms_flip_scaled_crc.c | 16 ++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index 7c79521344de..a612df407692 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -21,6 +21,7 @@
#define AUX_FORMAT_AYUV 0x09
#define AUX_FORMAT_ARGB_8B 0x0A
#define AUX_FORMAT_NV12_21 0x0F
+#define AUX_FORMAT_XRGB16161616_64B 0x10
struct pgtable_level_desc {
int idx_shift;
@@ -305,6 +306,10 @@ static uint64_t pgt_get_l1_flags(const struct intel_buf *buf, int surface_idx)
entry.e.format = AUX_FORMAT_ARGB_8B;
entry.e.depth = bpp_to_depth_val(32);
break;
+ case 64:
+ entry.e.format = AUX_FORMAT_XRGB16161616_64B;
+ entry.e.depth = bpp_to_depth_val(64);
+ break;
default:
igt_assert(0);
}
diff --git a/tests/intel/kms_flip_scaled_crc.c b/tests/intel/kms_flip_scaled_crc.c
index 2997b63fac40..0d5e994af2b7 100644
--- a/tests/intel/kms_flip_scaled_crc.c
+++ b/tests/intel/kms_flip_scaled_crc.c
@@ -590,6 +590,22 @@ const struct {
0.5,
1.0,
},
+ {
+ "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-upscaling",
+ "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-downscaling",
+ "Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F,
+ 1.0,
+ 2.0,
+ },
};
static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width,
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] tests/intel/kms_flip_scaled_crc: Add support for FP16 format of MTL compressed modifier
2023-10-11 9:55 [igt-dev] [PATCH i-g-t] tests/intel/kms_flip_scaled_crc: Add support for FP16 format of MTL compressed modifier Melanie Lobo
@ 2023-10-11 13:15 ` Kamil Konieczny
2023-10-12 6:54 ` Lobo, Melanie
2023-10-12 7:43 ` [igt-dev] intel/kms_flip_scaled_crc.c : Add support for FP16 compressed formats in MTL Melanie Lobo
2023-10-12 8:08 ` [igt-dev] [PATCH] [PATCH i-g-t] " Melanie Lobo
2 siblings, 1 reply; 5+ messages in thread
From: Kamil Konieczny @ 2023-10-11 13:15 UTC (permalink / raw)
To: igt-dev; +Cc: juha-pekka.heikkila
Hi Melanie,
please subscribe to igt-dev mailinglist.
On 2023-10-11 at 15:25:20 +0530, Melanie Lobo wrote:
> MTL supports new FP16 format which is a binary floating-point computer
> number format that occupies 16 bits in computer memory.
>
> Change-Id: I7fa8169d54cbd9e6dcdf765065659e541a31e481
- ^^^^^^^^^
Drop this line.
Regards,
Kamil
> Signed-off-by: Melanie Lobo <melanie.lobo@intel.com>
> ---
> lib/intel_aux_pgtable.c | 5 +++++
> tests/intel/kms_flip_scaled_crc.c | 16 ++++++++++++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
> index 7c79521344de..a612df407692 100644
> --- a/lib/intel_aux_pgtable.c
> +++ b/lib/intel_aux_pgtable.c
> @@ -21,6 +21,7 @@
> #define AUX_FORMAT_AYUV 0x09
> #define AUX_FORMAT_ARGB_8B 0x0A
> #define AUX_FORMAT_NV12_21 0x0F
> +#define AUX_FORMAT_XRGB16161616_64B 0x10
>
> struct pgtable_level_desc {
> int idx_shift;
> @@ -305,6 +306,10 @@ static uint64_t pgt_get_l1_flags(const struct intel_buf *buf, int surface_idx)
> entry.e.format = AUX_FORMAT_ARGB_8B;
> entry.e.depth = bpp_to_depth_val(32);
> break;
> + case 64:
> + entry.e.format = AUX_FORMAT_XRGB16161616_64B;
> + entry.e.depth = bpp_to_depth_val(64);
> + break;
> default:
> igt_assert(0);
> }
> diff --git a/tests/intel/kms_flip_scaled_crc.c b/tests/intel/kms_flip_scaled_crc.c
> index 2997b63fac40..0d5e994af2b7 100644
> --- a/tests/intel/kms_flip_scaled_crc.c
> +++ b/tests/intel/kms_flip_scaled_crc.c
> @@ -590,6 +590,22 @@ const struct {
> 0.5,
> 1.0,
> },
> + {
> + "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-upscaling",
> + "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
> + I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
> + I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F,
> + 0.5,
> + 1.0,
> + },
> + {
> + "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-downscaling",
> + "Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
> + I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
> + I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F,
> + 1.0,
> + 2.0,
> + },
> };
>
> static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width,
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] tests/intel/kms_flip_scaled_crc: Add support for FP16 format of MTL compressed modifier
2023-10-11 13:15 ` Kamil Konieczny
@ 2023-10-12 6:54 ` Lobo, Melanie
0 siblings, 0 replies; 5+ messages in thread
From: Lobo, Melanie @ 2023-10-12 6:54 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev@lists.freedesktop.org
> -----Original Message-----
> From: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Sent: Wednesday, October 11, 2023 6:46 PM
> To: igt-dev@lists.freedesktop.org
> Cc: Lobo, Melanie <melanie.lobo@intel.com>; Heikkila, Juha-pekka <juha-
> pekka.heikkila@intel.com>
> Subject: Re: [igt-dev] [PATCH i-g-t] tests/intel/kms_flip_scaled_crc: Add
> support for FP16 format of MTL compressed modifier
>
> Hi Melanie,
>
> please subscribe to igt-dev mailinglist.
>
> On 2023-10-11 at 15:25:20 +0530, Melanie Lobo wrote:
> > MTL supports new FP16 format which is a binary floating-point computer
> > number format that occupies 16 bits in computer memory.
> >
> > Change-Id: I7fa8169d54cbd9e6dcdf765065659e541a31e481
> - ^^^^^^^^^
> Drop this line.
>
> Regards,
> Kamil
>
Hi Kamil,
Thank you for your reply. I have subscribed to igt-dev mailing list. I will remove the Change-Id and float the next revision.
Regards,
Melanie Lobo
> > Signed-off-by: Melanie Lobo <melanie.lobo@intel.com>
> > ---
> > lib/intel_aux_pgtable.c | 5 +++++
> > tests/intel/kms_flip_scaled_crc.c | 16 ++++++++++++++++
> > 2 files changed, 21 insertions(+)
> >
> > diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index
> > 7c79521344de..a612df407692 100644
> > --- a/lib/intel_aux_pgtable.c
> > +++ b/lib/intel_aux_pgtable.c
> > @@ -21,6 +21,7 @@
> > #define AUX_FORMAT_AYUV 0x09
> > #define AUX_FORMAT_ARGB_8B 0x0A
> > #define AUX_FORMAT_NV12_21 0x0F
> > +#define AUX_FORMAT_XRGB16161616_64B 0x10
> >
> > struct pgtable_level_desc {
> > int idx_shift;
> > @@ -305,6 +306,10 @@ static uint64_t pgt_get_l1_flags(const struct
> intel_buf *buf, int surface_idx)
> > entry.e.format = AUX_FORMAT_ARGB_8B;
> > entry.e.depth = bpp_to_depth_val(32);
> > break;
> > + case 64:
> > + entry.e.format = AUX_FORMAT_XRGB16161616_64B;
> > + entry.e.depth = bpp_to_depth_val(64);
> > + break;
> > default:
> > igt_assert(0);
> > }
> > diff --git a/tests/intel/kms_flip_scaled_crc.c
> > b/tests/intel/kms_flip_scaled_crc.c
> > index 2997b63fac40..0d5e994af2b7 100644
> > --- a/tests/intel/kms_flip_scaled_crc.c
> > +++ b/tests/intel/kms_flip_scaled_crc.c
> > @@ -590,6 +590,22 @@ const struct {
> > 0.5,
> > 1.0,
> > },
> > + {
> > + "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-upscaling",
> > + "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress
> CD clock programming",
> > + I915_FORMAT_MOD_4_TILED,
> DRM_FORMAT_XRGB16161616F,
> > + I915_FORMAT_MOD_4_TILED_MTL_RC_CCS,
> DRM_FORMAT_XRGB16161616F,
> > + 0.5,
> > + 1.0,
> > + },
> > + {
> > + "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-downscaling",
> > + "Flip from 64bpp non scaled fb to 32bpp downscaled fb to
> stress CD clock programming",
> > + I915_FORMAT_MOD_4_TILED,
> DRM_FORMAT_XRGB16161616F,
> > + I915_FORMAT_MOD_4_TILED_MTL_RC_CCS,
> DRM_FORMAT_XRGB16161616F,
> > + 1.0,
> > + 2.0,
> > + },
> > };
> >
> > static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t
> > width,
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 5+ messages in thread
* [igt-dev] intel/kms_flip_scaled_crc.c : Add support for FP16 compressed formats in MTL
2023-10-11 9:55 [igt-dev] [PATCH i-g-t] tests/intel/kms_flip_scaled_crc: Add support for FP16 format of MTL compressed modifier Melanie Lobo
2023-10-11 13:15 ` Kamil Konieczny
@ 2023-10-12 7:43 ` Melanie Lobo
2023-10-12 8:08 ` [igt-dev] [PATCH] [PATCH i-g-t] " Melanie Lobo
2 siblings, 0 replies; 5+ messages in thread
From: Melanie Lobo @ 2023-10-12 7:43 UTC (permalink / raw)
To: igt-dev; +Cc: juha-pekka.heikkila
MTL supports FP16 format which is a binary floating-point computer
number format that occupies 16 bits in computer memory.In this test
platform shall render compression in display engine to receive
FP16 compressed formats.
Signed-off-by: Melanie Lobo <melanie.lobo@intel.com>
---
lib/intel_aux_pgtable.c | 5 +++++
tests/intel/kms_flip_scaled_crc.c | 16 ++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index 7c79521344de..a612df407692 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -21,6 +21,7 @@
#define AUX_FORMAT_AYUV 0x09
#define AUX_FORMAT_ARGB_8B 0x0A
#define AUX_FORMAT_NV12_21 0x0F
+#define AUX_FORMAT_XRGB16161616_64B 0x10
struct pgtable_level_desc {
int idx_shift;
@@ -305,6 +306,10 @@ static uint64_t pgt_get_l1_flags(const struct intel_buf *buf, int surface_idx)
entry.e.format = AUX_FORMAT_ARGB_8B;
entry.e.depth = bpp_to_depth_val(32);
break;
+ case 64:
+ entry.e.format = AUX_FORMAT_XRGB16161616_64B;
+ entry.e.depth = bpp_to_depth_val(64);
+ break;
default:
igt_assert(0);
}
diff --git a/tests/intel/kms_flip_scaled_crc.c b/tests/intel/kms_flip_scaled_crc.c
index 2997b63fac40..0d5e994af2b7 100644
--- a/tests/intel/kms_flip_scaled_crc.c
+++ b/tests/intel/kms_flip_scaled_crc.c
@@ -590,6 +590,22 @@ const struct {
0.5,
1.0,
},
+ {
+ "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-upscaling",
+ "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-downscaling",
+ "Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F,
+ 1.0,
+ 2.0,
+ },
};
static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width,
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [igt-dev] [PATCH] [PATCH i-g-t] intel/kms_flip_scaled_crc.c : Add support for FP16 compressed formats in MTL
2023-10-11 9:55 [igt-dev] [PATCH i-g-t] tests/intel/kms_flip_scaled_crc: Add support for FP16 format of MTL compressed modifier Melanie Lobo
2023-10-11 13:15 ` Kamil Konieczny
2023-10-12 7:43 ` [igt-dev] intel/kms_flip_scaled_crc.c : Add support for FP16 compressed formats in MTL Melanie Lobo
@ 2023-10-12 8:08 ` Melanie Lobo
2 siblings, 0 replies; 5+ messages in thread
From: Melanie Lobo @ 2023-10-12 8:08 UTC (permalink / raw)
To: igt-dev; +Cc: juha-pekka.heikkila
MTL supports FP16 format which is a binary floating-point computer
number format that occupies 16 bits in computer memory.In this test
platform shall render compression in display engine to receive
FP16 compressed formats.
Signed-off-by: Melanie Lobo <melanie.lobo@intel.com>
---
lib/intel_aux_pgtable.c | 5 +++++
tests/intel/kms_flip_scaled_crc.c | 16 ++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index 7c79521344de..a612df407692 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -21,6 +21,7 @@
#define AUX_FORMAT_AYUV 0x09
#define AUX_FORMAT_ARGB_8B 0x0A
#define AUX_FORMAT_NV12_21 0x0F
+#define AUX_FORMAT_XRGB16161616_64B 0x10
struct pgtable_level_desc {
int idx_shift;
@@ -305,6 +306,10 @@ static uint64_t pgt_get_l1_flags(const struct intel_buf *buf, int surface_idx)
entry.e.format = AUX_FORMAT_ARGB_8B;
entry.e.depth = bpp_to_depth_val(32);
break;
+ case 64:
+ entry.e.format = AUX_FORMAT_XRGB16161616_64B;
+ entry.e.depth = bpp_to_depth_val(64);
+ break;
default:
igt_assert(0);
}
diff --git a/tests/intel/kms_flip_scaled_crc.c b/tests/intel/kms_flip_scaled_crc.c
index 2997b63fac40..0d5e994af2b7 100644
--- a/tests/intel/kms_flip_scaled_crc.c
+++ b/tests/intel/kms_flip_scaled_crc.c
@@ -590,6 +590,22 @@ const struct {
0.5,
1.0,
},
+ {
+ "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-upscaling",
+ "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-downscaling",
+ "Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F,
+ 1.0,
+ 2.0,
+ },
};
static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width,
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
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2023-10-11 9:55 [igt-dev] [PATCH i-g-t] tests/intel/kms_flip_scaled_crc: Add support for FP16 format of MTL compressed modifier Melanie Lobo
2023-10-11 13:15 ` Kamil Konieczny
2023-10-12 6:54 ` Lobo, Melanie
2023-10-12 7:43 ` [igt-dev] intel/kms_flip_scaled_crc.c : Add support for FP16 compressed formats in MTL Melanie Lobo
2023-10-12 8:08 ` [igt-dev] [PATCH] [PATCH i-g-t] " Melanie Lobo
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