[igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands

[igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Add copy basic test which exercies mem-se and mem-copy commands, this
patch series involves in following changes:

1. Add copy basic test to exercise blt commands.
2. Add wrappers for batch preparation and submit exec.
3. Add copy commands MEM_SET_CMD and MEM_COPY_CMD in the lib.

Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (3):
  lib/intel_blt: Add wrappers to prepare batch buffers and submit exec
  lib/intel_cmds_info: Add M_MATRIX in mem_copy as it is supported for
    PVC
  intel/xe_copy_basic: Add copy basic test to exercise blt commands

 lib/intel_blt.c             | 200 ++++++++++++++++++++++++++++++++++++
 lib/intel_blt.h             |  39 +++++++
 lib/intel_cmds_info.c       |   3 +-
 lib/intel_reg.h             |   4 +
 tests/intel/xe_copy_basic.c | 192 ++++++++++++++++++++++++++++++++++
 tests/meson.build           |   1 +
 6 files changed, 438 insertions(+), 1 deletion(-)
 create mode 100644 tests/intel/xe_copy_basic.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Adding wrapper for mem-set and mem-copy instructions to prepare
batch buffers and submit exec, (blt_mem_copy, blt_mem_set,
emit_blt_mem_copy, emit_blt_set_mem)

Cc: Karolina Stolarek <karolina.stolarek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_blt.c | 200 ++++++++++++++++++++++++++++++++++++++++++++++++
 lib/intel_blt.h |  39 ++++++++++
 lib/intel_reg.h |   4 +
 3 files changed, 243 insertions(+)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index a76c7a404..b77625ce5 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -13,12 +13,14 @@
 #include "igt.h"
 #include "igt_syncobj.h"
 #include "intel_blt.h"
+#include "intel_mocs.h"
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "xe/xe_util.h"
 
 #define BITRANGE(start, end) (end - start + 1)
 #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
+#define MEM_COPY_MOCS_SHIFT                     25
 
 /* Blitter tiling definitions sanity checks */
 static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have to match");
@@ -1577,6 +1579,187 @@ int blt_fast_copy(int fd,
 	return ret;
 }
 
+/**
+ * blt_mem_init:
+ * @fd: drm fd
+ * @mem: structure for initialization
+ *
+ * Function is zeroing @mem and sets fd and driver fields (INTEL_DRIVER_I915 or
+ * INTEL_DRIVER_XE).
+ */
+void blt_mem_init(int fd, struct blt_mem_data *mem)
+{
+	memset(mem, 0, sizeof(*mem));
+
+	mem->fd = fd;
+	mem->driver = get_intel_driver(fd);
+}
+
+static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem)
+{
+	uint64_t dst_offset, src_offset, alignment;
+	int i;
+	uint32_t *batch;
+	uint32_t optype;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+
+	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
+	optype = mem->src.type == M_MATRIX ? 1 << 17 : 0;
+
+	i = 0;
+	batch[i++] = MEM_COPY_CMD | (1 << 19) | optype;
+	batch[i++] = mem->src.width - 1;
+	batch[i++] = mem->src.height - 1;
+	batch[i++] = mem->src.pitch - 1;
+	batch[i++] = mem->dst.pitch - 1;
+	batch[i++] = src_offset;
+	batch[i++] = src_offset << 32;
+	batch[i++] = dst_offset;
+	batch[i++] = dst_offset << 32;
+	batch[i++] = mem->src.mocs_index << MEM_COPY_MOCS_SHIFT | mem->dst.mocs_index;
+	batch[i++] = MI_BATCH_BUFFER_END;
+
+	munmap(batch, mem->bb.size);
+}
+
+/**
+ * blt_mem_copy:
+ * @fd: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @blt: blitter data for mem-copy.
+ *
+ * Function does mem blit between @src and @dst described in @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_mem_copy(int fd, const intel_ctx_t *ctx,
+		 const struct intel_execution_engine2 *e,
+		 uint64_t ahnd,
+		 const struct blt_mem_data *mem)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	uint64_t dst_offset, src_offset, bb_offset, alignment;
+	int ret;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
+
+	emit_blt_mem_copy(fd, ahnd, mem);
+
+	if (mem->driver == INTEL_DRIVER_XE) {
+		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+	} else {
+		obj[0].offset = CANONICAL(dst_offset);
+		obj[1].offset = CANONICAL(src_offset);
+		obj[2].offset = CANONICAL(bb_offset);
+		obj[0].handle = mem->dst.handle;
+		obj[1].handle = mem->src.handle;
+		obj[2].handle = mem->bb.handle;
+		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+			EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		execbuf.buffer_count = 3;
+                execbuf.buffers_ptr = to_user_pointer(obj);
+		execbuf.rsvd1 = ctx ? ctx->id : 0;
+		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+		ret = __gem_execbuf(fd, &execbuf);
+		put_offset(ahnd, mem->dst.handle);
+		put_offset(ahnd, mem->src.handle);
+		put_offset(ahnd, mem->bb.handle);
+	}
+
+	return ret;
+}
+
+static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem,
+			     uint8_t fill_data)
+{
+	uint64_t dst_offset, alignment;
+	int b;
+	uint32_t *batch;
+	uint32_t value;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+
+	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
+	value = (uint32_t)fill_data << 24;
+
+	b = 0;
+	batch[b++] = MEM_SET_CMD;
+	batch[b++] = mem->dst.width - 1;
+	batch[b++] = mem->dst.height - 1;
+	batch[b++] = mem->dst.pitch - 1;
+	batch[b++] = dst_offset;
+	batch[b++] = dst_offset << 32;
+	batch[b++] = value | mem->dst.mocs_index;
+	batch[b++] = MI_BATCH_BUFFER_END;
+
+	munmap(batch, mem->bb.size);
+
+}
+/**
+ * blt_mem_set:
+ * @fd: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @blt: blitter data for mem-set.
+ *
+ * Function does mem set blit in described @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_mem_set(int fd, const intel_ctx_t *ctx,
+		const struct intel_execution_engine2 *e,
+		uint64_t ahnd,
+		const struct blt_mem_data *mem,
+		uint8_t fill_data)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[2] = {};
+	uint64_t dst_offset, bb_offset, alignment;
+	int ret;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
+
+	emit_blt_mem_set(fd, ahnd, mem, fill_data);
+
+	if (mem->driver == INTEL_DRIVER_XE) {
+		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+	} else {
+		obj[0].offset = CANONICAL(dst_offset);
+		obj[1].offset = CANONICAL(bb_offset);
+		obj[0].handle = mem->dst.handle;
+		obj[1].handle = mem->bb.handle;
+		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+						    EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		execbuf.buffer_count = 2;
+		execbuf.buffers_ptr = to_user_pointer(obj);
+		execbuf.rsvd1 = ctx ? ctx->id : 0;
+		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+		ret = __gem_execbuf(fd, &execbuf);
+		put_offset(ahnd, mem->dst.handle);
+		put_offset(ahnd, mem->bb.handle);
+	}
+
+	return ret;
+}
+
 void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
 		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
 		  uint16_t x_offset, uint16_t y_offset)
@@ -1659,6 +1842,23 @@ void blt_set_object(struct blt_copy_object *obj,
 	obj->compression_type = compression_type;
 }
 
+void blt_set_mem_object(struct blt_mem_object *obj,
+			uint32_t handle, uint64_t size, uint32_t pitch,
+			uint32_t width, uint32_t height, uint32_t region,
+			uint8_t mocs_index, enum blt_memop_type type,
+			enum blt_compression compression)
+{
+	obj->handle = handle;
+	obj->region = region;
+	obj->size = size;
+	obj->mocs_index = mocs_index;
+	obj->type = type;
+	obj->compression = compression;
+	obj->width = width;
+	obj->height = height;
+	obj->pitch = pitch;
+}
+
 void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
 			uint8_t compression_format,
 			uint16_t surface_width, uint16_t surface_height,
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index 7b4271620..01a7e117a 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -93,6 +93,19 @@ struct blt_copy_object {
 	uint32_t plane_offset;
 };
 
+struct blt_mem_object {
+	uint32_t handle;
+	uint32_t region;
+	uint64_t size;
+	uint8_t mocs_index;
+	enum blt_memop_type type;
+	enum blt_compression compression;
+	uint32_t width;
+	uint32_t height;
+	uint32_t pitch;
+	uint32_t *ptr;
+};
+
 struct blt_copy_batch {
 	uint32_t handle;
 	uint32_t region;
@@ -112,6 +125,14 @@ struct blt_copy_data {
 	bool print_bb;
 };
 
+struct blt_mem_data {
+	int fd;
+	enum intel_driver driver;
+	struct blt_mem_object src;
+	struct blt_mem_object dst;
+	struct blt_copy_batch bb;
+};
+
 enum blt_surface_type {
 	SURFACE_TYPE_1D,
 	SURFACE_TYPE_2D,
@@ -231,6 +252,17 @@ int blt_fast_copy(int fd,
 		  uint64_t ahnd,
 		  const struct blt_copy_data *blt);
 
+void blt_mem_init(int fd, struct blt_mem_data *mem);
+
+int blt_mem_copy(int fd, const intel_ctx_t *ctx,
+			 const struct intel_execution_engine2 *e,
+			 uint64_t ahnd,
+			 const struct blt_mem_data *mem);
+
+int blt_mem_set(int fd, const intel_ctx_t *ctx,
+			const struct intel_execution_engine2 *e, uint64_t ahnd,
+			const struct blt_mem_data *mem, uint8_t fill_data);
+
 void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
 		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
 		  uint16_t x_offset, uint16_t y_offset);
@@ -250,6 +282,13 @@ void blt_set_object(struct blt_copy_object *obj,
 		    uint8_t mocs_index, enum blt_tiling_type tiling,
 		    enum blt_compression compression,
 		    enum blt_compression_type compression_type);
+
+void blt_set_mem_object(struct blt_mem_object *obj,
+			uint32_t handle, uint64_t size, uint32_t pitch,
+			uint32_t width, uint32_t height, uint32_t region,
+			uint8_t mocs_index, enum blt_memop_type type,
+			enum blt_compression compression);
+
 void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
 			uint8_t compression_format,
 			uint16_t surface_width, uint16_t surface_height,
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ea463376b..a8190d683 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2588,6 +2588,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define   XY_FAST_COPY_COLOR_DEPTH_64			(4  << 24)
 #define   XY_FAST_COPY_COLOR_DEPTH_128			(5  << 24)
 
+/* RAW memory commands */
+#define MEM_COPY_CMD                    ((0x2 << 29)|(0x5a << 22)|0x8)
+#define MEM_SET_CMD                     ((0x2 << 29)|(0x5b << 22)|0x5)
+
 #define CTXT_NO_RESTORE			(1)
 #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
 #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
-- 
2.39.1

Re: [igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec

[Zbigniew Kempczyński]

On Mon, Oct 16, 2023 at 11:37:14PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Adding wrapper for mem-set and mem-copy instructions to prepare
> batch buffers and submit exec, (blt_mem_copy, blt_mem_set,
> emit_blt_mem_copy, emit_blt_set_mem)
> 
> Cc: Karolina Stolarek <karolina.stolarek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  lib/intel_blt.c | 200 ++++++++++++++++++++++++++++++++++++++++++++++++
>  lib/intel_blt.h |  39 ++++++++++
>  lib/intel_reg.h |   4 +
>  3 files changed, 243 insertions(+)
> 
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index a76c7a404..b77625ce5 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -13,12 +13,14 @@
>  #include "igt.h"
>  #include "igt_syncobj.h"
>  #include "intel_blt.h"
> +#include "intel_mocs.h"
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_util.h"
>  
>  #define BITRANGE(start, end) (end - start + 1)
>  #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
> +#define MEM_COPY_MOCS_SHIFT                     25
>  
>  /* Blitter tiling definitions sanity checks */
>  static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have to match");
> @@ -1577,6 +1579,187 @@ int blt_fast_copy(int fd,
>  	return ret;
>  }
>  
> +/**
> + * blt_mem_init:
> + * @fd: drm fd
> + * @mem: structure for initialization
> + *
> + * Function is zeroing @mem and sets fd and driver fields (INTEL_DRIVER_I915 or
> + * INTEL_DRIVER_XE).
> + */
> +void blt_mem_init(int fd, struct blt_mem_data *mem)
> +{
> +	memset(mem, 0, sizeof(*mem));
> +
> +	mem->fd = fd;
> +	mem->driver = get_intel_driver(fd);
> +}
> +
> +static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem)
> +{
> +	uint64_t dst_offset, src_offset, alignment;
> +	int i;
> +	uint32_t *batch;
> +	uint32_t optype;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +
> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
> +	optype = mem->src.type == M_MATRIX ? 1 << 17 : 0;
> +
> +	i = 0;
> +	batch[i++] = MEM_COPY_CMD | (1 << 19) | optype;
> +	batch[i++] = mem->src.width - 1;
> +	batch[i++] = mem->src.height - 1;
> +	batch[i++] = mem->src.pitch - 1;
> +	batch[i++] = mem->dst.pitch - 1;
> +	batch[i++] = src_offset;
> +	batch[i++] = src_offset << 32;
> +	batch[i++] = dst_offset;
> +	batch[i++] = dst_offset << 32;
> +	batch[i++] = mem->src.mocs_index << MEM_COPY_MOCS_SHIFT | mem->dst.mocs_index;
> +	batch[i++] = MI_BATCH_BUFFER_END;
> +
> +	munmap(batch, mem->bb.size);
> +}
> +
> +/**
> + * blt_mem_copy:
> + * @fd: drm fd
> + * @ctx: intel_ctx_t context
> + * @e: blitter engine for @ctx
> + * @ahnd: allocator handle
> + * @blt: blitter data for mem-copy.
> + *
> + * Function does mem blit between @src and @dst described in @blt object.
> + *
> + * Returns:
> + * execbuffer status.
> + */
> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
> +		 const struct intel_execution_engine2 *e,
> +		 uint64_t ahnd,
> +		 const struct blt_mem_data *mem)

I thought it is improperly indented, forget about my comment on cover
letter.

> +{
> +	struct drm_i915_gem_execbuffer2 execbuf = {};
> +	struct drm_i915_gem_exec_object2 obj[3] = {};
> +	uint64_t dst_offset, src_offset, bb_offset, alignment;
> +	int ret;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
> +
> +	emit_blt_mem_copy(fd, ahnd, mem);
> +
> +	if (mem->driver == INTEL_DRIVER_XE) {
> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
> +	} else {
> +		obj[0].offset = CANONICAL(dst_offset);
> +		obj[1].offset = CANONICAL(src_offset);
> +		obj[2].offset = CANONICAL(bb_offset);
> +		obj[0].handle = mem->dst.handle;
> +		obj[1].handle = mem->src.handle;
> +		obj[2].handle = mem->bb.handle;
> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +			EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		execbuf.buffer_count = 3;
> +                execbuf.buffers_ptr = to_user_pointer(obj);

Eh, I've missed this last time -> above line is not properly
indented with tabs.

I've asked about debugging info similar to block-copy and other.
Please add this before merging.

--
Zbigniew

> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +		ret = __gem_execbuf(fd, &execbuf);
> +		put_offset(ahnd, mem->dst.handle);
> +		put_offset(ahnd, mem->src.handle);
> +		put_offset(ahnd, mem->bb.handle);
> +	}
> +
> +	return ret;
> +}
> +
> +static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem,
> +			     uint8_t fill_data)
> +{
> +	uint64_t dst_offset, alignment;
> +	int b;
> +	uint32_t *batch;
> +	uint32_t value;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +
> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
> +	value = (uint32_t)fill_data << 24;
> +
> +	b = 0;
> +	batch[b++] = MEM_SET_CMD;
> +	batch[b++] = mem->dst.width - 1;
> +	batch[b++] = mem->dst.height - 1;
> +	batch[b++] = mem->dst.pitch - 1;
> +	batch[b++] = dst_offset;
> +	batch[b++] = dst_offset << 32;
> +	batch[b++] = value | mem->dst.mocs_index;
> +	batch[b++] = MI_BATCH_BUFFER_END;
> +
> +	munmap(batch, mem->bb.size);
> +
> +}
> +/**
> + * blt_mem_set:
> + * @fd: drm fd
> + * @ctx: intel_ctx_t context
> + * @e: blitter engine for @ctx
> + * @ahnd: allocator handle
> + * @blt: blitter data for mem-set.
> + *
> + * Function does mem set blit in described @blt object.
> + *
> + * Returns:
> + * execbuffer status.
> + */
> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
> +		const struct intel_execution_engine2 *e,
> +		uint64_t ahnd,
> +		const struct blt_mem_data *mem,
> +		uint8_t fill_data)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf = {};
> +	struct drm_i915_gem_exec_object2 obj[2] = {};
> +	uint64_t dst_offset, bb_offset, alignment;
> +	int ret;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
> +
> +	emit_blt_mem_set(fd, ahnd, mem, fill_data);
> +
> +	if (mem->driver == INTEL_DRIVER_XE) {
> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
> +	} else {
> +		obj[0].offset = CANONICAL(dst_offset);
> +		obj[1].offset = CANONICAL(bb_offset);
> +		obj[0].handle = mem->dst.handle;
> +		obj[1].handle = mem->bb.handle;
> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +						    EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		execbuf.buffer_count = 2;
> +		execbuf.buffers_ptr = to_user_pointer(obj);
> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +		ret = __gem_execbuf(fd, &execbuf);
> +		put_offset(ahnd, mem->dst.handle);
> +		put_offset(ahnd, mem->bb.handle);
> +	}
> +
> +	return ret;
> +}
> +
>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>  		  uint16_t x_offset, uint16_t y_offset)
> @@ -1659,6 +1842,23 @@ void blt_set_object(struct blt_copy_object *obj,
>  	obj->compression_type = compression_type;
>  }
>  
> +void blt_set_mem_object(struct blt_mem_object *obj,
> +			uint32_t handle, uint64_t size, uint32_t pitch,
> +			uint32_t width, uint32_t height, uint32_t region,
> +			uint8_t mocs_index, enum blt_memop_type type,
> +			enum blt_compression compression)
> +{
> +	obj->handle = handle;
> +	obj->region = region;
> +	obj->size = size;
> +	obj->mocs_index = mocs_index;
> +	obj->type = type;
> +	obj->compression = compression;
> +	obj->width = width;
> +	obj->height = height;
> +	obj->pitch = pitch;
> +}
> +
>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>  			uint8_t compression_format,
>  			uint16_t surface_width, uint16_t surface_height,
> diff --git a/lib/intel_blt.h b/lib/intel_blt.h
> index 7b4271620..01a7e117a 100644
> --- a/lib/intel_blt.h
> +++ b/lib/intel_blt.h
> @@ -93,6 +93,19 @@ struct blt_copy_object {
>  	uint32_t plane_offset;
>  };
>  
> +struct blt_mem_object {
> +	uint32_t handle;
> +	uint32_t region;
> +	uint64_t size;
> +	uint8_t mocs_index;
> +	enum blt_memop_type type;
> +	enum blt_compression compression;
> +	uint32_t width;
> +	uint32_t height;
> +	uint32_t pitch;
> +	uint32_t *ptr;
> +};
> +
>  struct blt_copy_batch {
>  	uint32_t handle;
>  	uint32_t region;
> @@ -112,6 +125,14 @@ struct blt_copy_data {
>  	bool print_bb;
>  };
>  
> +struct blt_mem_data {
> +	int fd;
> +	enum intel_driver driver;
> +	struct blt_mem_object src;
> +	struct blt_mem_object dst;
> +	struct blt_copy_batch bb;
> +};
> +
>  enum blt_surface_type {
>  	SURFACE_TYPE_1D,
>  	SURFACE_TYPE_2D,
> @@ -231,6 +252,17 @@ int blt_fast_copy(int fd,
>  		  uint64_t ahnd,
>  		  const struct blt_copy_data *blt);
>  
> +void blt_mem_init(int fd, struct blt_mem_data *mem);
> +
> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
> +			 const struct intel_execution_engine2 *e,
> +			 uint64_t ahnd,
> +			 const struct blt_mem_data *mem);
> +
> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
> +			const struct intel_execution_engine2 *e, uint64_t ahnd,
> +			const struct blt_mem_data *mem, uint8_t fill_data);
> +
>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>  		  uint16_t x_offset, uint16_t y_offset);
> @@ -250,6 +282,13 @@ void blt_set_object(struct blt_copy_object *obj,
>  		    uint8_t mocs_index, enum blt_tiling_type tiling,
>  		    enum blt_compression compression,
>  		    enum blt_compression_type compression_type);
> +
> +void blt_set_mem_object(struct blt_mem_object *obj,
> +			uint32_t handle, uint64_t size, uint32_t pitch,
> +			uint32_t width, uint32_t height, uint32_t region,
> +			uint8_t mocs_index, enum blt_memop_type type,
> +			enum blt_compression compression);
> +
>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>  			uint8_t compression_format,
>  			uint16_t surface_width, uint16_t surface_height,
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index ea463376b..a8190d683 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2588,6 +2588,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  #define   XY_FAST_COPY_COLOR_DEPTH_64			(4  << 24)
>  #define   XY_FAST_COPY_COLOR_DEPTH_128			(5  << 24)
>  
> +/* RAW memory commands */
> +#define MEM_COPY_CMD                    ((0x2 << 29)|(0x5a << 22)|0x8)
> +#define MEM_SET_CMD                     ((0x2 << 29)|(0x5b << 22)|0x5)
> +
>  #define CTXT_NO_RESTORE			(1)
>  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
>  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
> -- 
> 2.39.1
> 

Re: [igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec

[Ch, Sai Gowtham]

>-----Original Message-----
>From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
>Sent: Tuesday, October 17, 2023 2:29 PM
>To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
>Cc: igt-dev@lists.freedesktop.org; Stolarek, Karolina
><karolina.stolarek@intel.com>
>Subject: Re: [PATCH i-g-t 1/3] lib/intel_blt: Add wrappers to prepare batch buffers
>and submit exec
>
>On Mon, Oct 16, 2023 at 11:37:14PM +0530, sai.gowtham.ch@intel.com wrote:
>> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>>
>> Adding wrapper for mem-set and mem-copy instructions to prepare batch
>> buffers and submit exec, (blt_mem_copy, blt_mem_set,
>> emit_blt_mem_copy, emit_blt_set_mem)
>>
>> Cc: Karolina Stolarek <karolina.stolarek@intel.com>
>> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>> ---
>>  lib/intel_blt.c | 200
>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>  lib/intel_blt.h |  39 ++++++++++
>>  lib/intel_reg.h |   4 +
>>  3 files changed, 243 insertions(+)
>>
>> diff --git a/lib/intel_blt.c b/lib/intel_blt.c index
>> a76c7a404..b77625ce5 100644
>> --- a/lib/intel_blt.c
>> +++ b/lib/intel_blt.c
>> @@ -13,12 +13,14 @@
>>  #include "igt.h"
>>  #include "igt_syncobj.h"
>>  #include "intel_blt.h"
>> +#include "intel_mocs.h"
>>  #include "xe/xe_ioctl.h"
>>  #include "xe/xe_query.h"
>>  #include "xe/xe_util.h"
>>
>>  #define BITRANGE(start, end) (end - start + 1)  #define
>> GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
>> +#define MEM_COPY_MOCS_SHIFT                     25
>>
>>  /* Blitter tiling definitions sanity checks */
>> static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have
>> to match"); @@ -1577,6 +1579,187 @@ int blt_fast_copy(int fd,
>>  	return ret;
>>  }
>>
>> +/**
>> + * blt_mem_init:
>> + * @fd: drm fd
>> + * @mem: structure for initialization
>> + *
>> + * Function is zeroing @mem and sets fd and driver fields
>> +(INTEL_DRIVER_I915 or
>> + * INTEL_DRIVER_XE).
>> + */
>> +void blt_mem_init(int fd, struct blt_mem_data *mem) {
>> +	memset(mem, 0, sizeof(*mem));
>> +
>> +	mem->fd = fd;
>> +	mem->driver = get_intel_driver(fd);
>> +}
>> +
>> +static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct
>> +blt_mem_data *mem) {
>> +	uint64_t dst_offset, src_offset, alignment;
>> +	int i;
>> +	uint32_t *batch;
>> +	uint32_t optype;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size,
>alignment);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>> +alignment);
>> +
>> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
>> +	optype = mem->src.type == M_MATRIX ? 1 << 17 : 0;
>> +
>> +	i = 0;
>> +	batch[i++] = MEM_COPY_CMD | (1 << 19) | optype;
>> +	batch[i++] = mem->src.width - 1;
>> +	batch[i++] = mem->src.height - 1;
>> +	batch[i++] = mem->src.pitch - 1;
>> +	batch[i++] = mem->dst.pitch - 1;
>> +	batch[i++] = src_offset;
>> +	batch[i++] = src_offset << 32;
>> +	batch[i++] = dst_offset;
>> +	batch[i++] = dst_offset << 32;
>> +	batch[i++] = mem->src.mocs_index << MEM_COPY_MOCS_SHIFT |
>mem->dst.mocs_index;
>> +	batch[i++] = MI_BATCH_BUFFER_END;
>> +
>> +	munmap(batch, mem->bb.size);
>> +}
>> +
>> +/**
>> + * blt_mem_copy:
>> + * @fd: drm fd
>> + * @ctx: intel_ctx_t context
>> + * @e: blitter engine for @ctx
>> + * @ahnd: allocator handle
>> + * @blt: blitter data for mem-copy.
>> + *
>> + * Function does mem blit between @src and @dst described in @blt object.
>> + *
>> + * Returns:
>> + * execbuffer status.
>> + */
>> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
>> +		 const struct intel_execution_engine2 *e,
>> +		 uint64_t ahnd,
>> +		 const struct blt_mem_data *mem)
>
>I thought it is improperly indented, forget about my comment on cover letter.
>
>> +{
>> +	struct drm_i915_gem_execbuffer2 execbuf = {};
>> +	struct drm_i915_gem_exec_object2 obj[3] = {};
>> +	uint64_t dst_offset, src_offset, bb_offset, alignment;
>> +	int ret;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size,
>alignment);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>alignment);
>> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size,
>> +alignment);
>> +
>> +	emit_blt_mem_copy(fd, ahnd, mem);
>> +
>> +	if (mem->driver == INTEL_DRIVER_XE) {
>> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
>> +	} else {
>> +		obj[0].offset = CANONICAL(dst_offset);
>> +		obj[1].offset = CANONICAL(src_offset);
>> +		obj[2].offset = CANONICAL(bb_offset);
>> +		obj[0].handle = mem->dst.handle;
>> +		obj[1].handle = mem->src.handle;
>> +		obj[2].handle = mem->bb.handle;
>> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
>> +			EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		obj[1].flags = EXEC_OBJECT_PINNED |
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		obj[2].flags = EXEC_OBJECT_PINNED |
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		execbuf.buffer_count = 3;
>> +                execbuf.buffers_ptr = to_user_pointer(obj);
>
>Eh, I've missed this last time -> above line is not properly indented with tabs.
>
Corrected the indentation. Will be mering all the three patch series at once.
>I've asked about debugging info similar to block-copy and other.
Will be adding this as an enhancement in different series. As I've to merge this patch series first.

----
Sai Gowtham Ch
>Please add this before merging.
>
>--
>Zbigniew
>
>> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
>> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
>> +		ret = __gem_execbuf(fd, &execbuf);
>> +		put_offset(ahnd, mem->dst.handle);
>> +		put_offset(ahnd, mem->src.handle);
>> +		put_offset(ahnd, mem->bb.handle);
>> +	}
>> +
>> +	return ret;
>> +}
>> +
>> +static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct
>blt_mem_data *mem,
>> +			     uint8_t fill_data)
>> +{
>> +	uint64_t dst_offset, alignment;
>> +	int b;
>> +	uint32_t *batch;
>> +	uint32_t value;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>> +alignment);
>> +
>> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
>> +	value = (uint32_t)fill_data << 24;
>> +
>> +	b = 0;
>> +	batch[b++] = MEM_SET_CMD;
>> +	batch[b++] = mem->dst.width - 1;
>> +	batch[b++] = mem->dst.height - 1;
>> +	batch[b++] = mem->dst.pitch - 1;
>> +	batch[b++] = dst_offset;
>> +	batch[b++] = dst_offset << 32;
>> +	batch[b++] = value | mem->dst.mocs_index;
>> +	batch[b++] = MI_BATCH_BUFFER_END;
>> +
>> +	munmap(batch, mem->bb.size);
>> +
>> +}
>> +/**
>> + * blt_mem_set:
>> + * @fd: drm fd
>> + * @ctx: intel_ctx_t context
>> + * @e: blitter engine for @ctx
>> + * @ahnd: allocator handle
>> + * @blt: blitter data for mem-set.
>> + *
>> + * Function does mem set blit in described @blt object.
>> + *
>> + * Returns:
>> + * execbuffer status.
>> + */
>> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
>> +		const struct intel_execution_engine2 *e,
>> +		uint64_t ahnd,
>> +		const struct blt_mem_data *mem,
>> +		uint8_t fill_data)
>> +{
>> +	struct drm_i915_gem_execbuffer2 execbuf = {};
>> +	struct drm_i915_gem_exec_object2 obj[2] = {};
>> +	uint64_t dst_offset, bb_offset, alignment;
>> +	int ret;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>alignment);
>> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size,
>> +alignment);
>> +
>> +	emit_blt_mem_set(fd, ahnd, mem, fill_data);
>> +
>> +	if (mem->driver == INTEL_DRIVER_XE) {
>> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
>> +	} else {
>> +		obj[0].offset = CANONICAL(dst_offset);
>> +		obj[1].offset = CANONICAL(bb_offset);
>> +		obj[0].handle = mem->dst.handle;
>> +		obj[1].handle = mem->bb.handle;
>> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
>> +
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		obj[1].flags = EXEC_OBJECT_PINNED |
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		execbuf.buffer_count = 2;
>> +		execbuf.buffers_ptr = to_user_pointer(obj);
>> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
>> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
>> +		ret = __gem_execbuf(fd, &execbuf);
>> +		put_offset(ahnd, mem->dst.handle);
>> +		put_offset(ahnd, mem->bb.handle);
>> +	}
>> +
>> +	return ret;
>> +}
>> +
>>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>>  		  uint16_t x_offset, uint16_t y_offset) @@ -1659,6 +1842,23 @@
>void
>> blt_set_object(struct blt_copy_object *obj,
>>  	obj->compression_type = compression_type;  }
>>
>> +void blt_set_mem_object(struct blt_mem_object *obj,
>> +			uint32_t handle, uint64_t size, uint32_t pitch,
>> +			uint32_t width, uint32_t height, uint32_t region,
>> +			uint8_t mocs_index, enum blt_memop_type type,
>> +			enum blt_compression compression)
>> +{
>> +	obj->handle = handle;
>> +	obj->region = region;
>> +	obj->size = size;
>> +	obj->mocs_index = mocs_index;
>> +	obj->type = type;
>> +	obj->compression = compression;
>> +	obj->width = width;
>> +	obj->height = height;
>> +	obj->pitch = pitch;
>> +}
>> +
>>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>>  			uint8_t compression_format,
>>  			uint16_t surface_width, uint16_t surface_height, diff --
>git
>> a/lib/intel_blt.h b/lib/intel_blt.h index 7b4271620..01a7e117a 100644
>> --- a/lib/intel_blt.h
>> +++ b/lib/intel_blt.h
>> @@ -93,6 +93,19 @@ struct blt_copy_object {
>>  	uint32_t plane_offset;
>>  };
>>
>> +struct blt_mem_object {
>> +	uint32_t handle;
>> +	uint32_t region;
>> +	uint64_t size;
>> +	uint8_t mocs_index;
>> +	enum blt_memop_type type;
>> +	enum blt_compression compression;
>> +	uint32_t width;
>> +	uint32_t height;
>> +	uint32_t pitch;
>> +	uint32_t *ptr;
>> +};
>> +
>>  struct blt_copy_batch {
>>  	uint32_t handle;
>>  	uint32_t region;
>> @@ -112,6 +125,14 @@ struct blt_copy_data {
>>  	bool print_bb;
>>  };
>>
>> +struct blt_mem_data {
>> +	int fd;
>> +	enum intel_driver driver;
>> +	struct blt_mem_object src;
>> +	struct blt_mem_object dst;
>> +	struct blt_copy_batch bb;
>> +};
>> +
>>  enum blt_surface_type {
>>  	SURFACE_TYPE_1D,
>>  	SURFACE_TYPE_2D,
>> @@ -231,6 +252,17 @@ int blt_fast_copy(int fd,
>>  		  uint64_t ahnd,
>>  		  const struct blt_copy_data *blt);
>>
>> +void blt_mem_init(int fd, struct blt_mem_data *mem);
>> +
>> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
>> +			 const struct intel_execution_engine2 *e,
>> +			 uint64_t ahnd,
>> +			 const struct blt_mem_data *mem);
>> +
>> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
>> +			const struct intel_execution_engine2 *e, uint64_t ahnd,
>> +			const struct blt_mem_data *mem, uint8_t fill_data);
>> +
>>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>>  		  uint16_t x_offset, uint16_t y_offset); @@ -250,6 +282,13 @@
>void
>> blt_set_object(struct blt_copy_object *obj,
>>  		    uint8_t mocs_index, enum blt_tiling_type tiling,
>>  		    enum blt_compression compression,
>>  		    enum blt_compression_type compression_type);
>> +
>> +void blt_set_mem_object(struct blt_mem_object *obj,
>> +			uint32_t handle, uint64_t size, uint32_t pitch,
>> +			uint32_t width, uint32_t height, uint32_t region,
>> +			uint8_t mocs_index, enum blt_memop_type type,
>> +			enum blt_compression compression);
>> +
>>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>>  			uint8_t compression_format,
>>  			uint16_t surface_width, uint16_t surface_height, diff --
>git
>> a/lib/intel_reg.h b/lib/intel_reg.h index ea463376b..a8190d683 100644
>> --- a/lib/intel_reg.h
>> +++ b/lib/intel_reg.h
>> @@ -2588,6 +2588,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
>THE SOFTWARE.
>>  #define   XY_FAST_COPY_COLOR_DEPTH_64			(4  << 24)
>>  #define   XY_FAST_COPY_COLOR_DEPTH_128			(5  << 24)
>>
>> +/* RAW memory commands */
>> +#define MEM_COPY_CMD                    ((0x2 << 29)|(0x5a << 22)|0x8)
>> +#define MEM_SET_CMD                     ((0x2 << 29)|(0x5b << 22)|0x5)
>> +
>>  #define CTXT_NO_RESTORE			(1)
>>  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
>>  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
>> --
>> 2.39.1
>>

[igt-dev] [PATCH i-g-t 2/3] lib/intel_cmds_info: Add M_MATRIX in mem_copy as it is supported for PVC

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Adding M_MATRIX copy type in MEM_COPY as it is supported for PVC

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 lib/intel_cmds_info.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c
index 1bf13fdc1..2e51ec081 100644
--- a/lib/intel_cmds_info.c
+++ b/lib/intel_cmds_info.c
@@ -84,7 +84,8 @@ static const struct blt_cmd_info
 
 static const struct blt_cmd_info
 		pvc_mem_copy = BLT_INFO(MEM_COPY,
-					BIT(M_LINEAR));
+					BIT(M_LINEAR) |
+					BIT(M_MATRIX));
 
 static const struct blt_cmd_info
 		pvc_mem_set = BLT_INFO(MEM_SET,
-- 
2.39.1

Re: [igt-dev] [PATCH i-g-t 2/3] lib/intel_cmds_info: Add M_MATRIX in mem_copy as it is supported for PVC

[Zbigniew Kempczyński]

On Mon, Oct 16, 2023 at 11:37:15PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Adding M_MATRIX copy type in MEM_COPY as it is supported for PVC
> 
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  lib/intel_cmds_info.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c
> index 1bf13fdc1..2e51ec081 100644
> --- a/lib/intel_cmds_info.c
> +++ b/lib/intel_cmds_info.c
> @@ -84,7 +84,8 @@ static const struct blt_cmd_info
>  
>  static const struct blt_cmd_info
>  		pvc_mem_copy = BLT_INFO(MEM_COPY,
> -					BIT(M_LINEAR));
> +					BIT(M_LINEAR) |
> +					BIT(M_MATRIX));
>  
>  static const struct blt_cmd_info
>  		pvc_mem_set = BLT_INFO(MEM_SET,
> -- 
> 2.39.1
> 

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

[igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: Add copy basic test to exercise blt commands

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Add copy basic test to exercise copy commands like mem-copy and mem-set.

Cc: Karolina Stolarek <karolina.stolarek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 tests/intel/xe_copy_basic.c | 192 ++++++++++++++++++++++++++++++++++++
 tests/meson.build           |   1 +
 2 files changed, 193 insertions(+)
 create mode 100644 tests/intel/xe_copy_basic.c

diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
new file mode 100644
index 000000000..253631102
--- /dev/null
+++ b/tests/intel/xe_copy_basic.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ *
+ * Authors:
+ *      Sai Gowtham Ch <sai.gowtham.ch@intel.com>
+ */
+
+#include "igt.h"
+#include "lib/igt_syncobj.h"
+#include "intel_blt.h"
+#include "lib/intel_cmds_info.h"
+#include "lib/intel_mocs.h"
+#include "lib/intel_reg.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include "xe/xe_util.h"
+
+#define MEM_FILL 0x8b
+
+/**
+ * TEST: Test to validate copy commands on xe
+ * Category: Software building block
+ * Sub-category: Copy
+ * Functionality: blitter
+ */
+
+/**
+ * SUBTEST: mem-copy-linear-%s
+ * Description: Test validates MEM_COPY command, it takes various
+ *              parameters needed for the filling batch buffer for MEM_COPY command
+ *              with size %arg[1].
+ * Test category: functionality test
+ *
+ * arg[1]:
+ * @0x369: 0x369
+ * @0x3fff: 0x3fff
+ * @0xfd: 0xfd
+ * @0xfffe: 0xfffe
+ */
+static void
+mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle,
+		 const intel_ctx_t *ctx, uint32_t size, uint32_t width,
+		 uint32_t height, uint32_t region)
+{
+	struct blt_mem_data mem = {};
+	uint64_t bb_size = xe_get_default_alignment(fd);
+	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
+						  INTEL_ALLOCATOR_SIMPLE,
+						  ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+	uint32_t bb;
+	int result;
+	uint8_t src_mocs = intel_get_uc_mocs_index(fd);
+	uint8_t dst_mocs = src_mocs;
+
+	bb = xe_bo_create_flags(fd, 0, bb_size, region);
+
+	blt_mem_init(fd, &mem);
+	blt_set_mem_object(&mem.src, src_handle, size, 0, width, height,
+			   region, src_mocs, M_LINEAR, COMPRESSION_DISABLED);
+	blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height,
+			   region, dst_mocs, M_LINEAR, COMPRESSION_DISABLED);
+	mem.src.ptr = xe_bo_map(fd, src_handle, size);
+	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
+
+	blt_set_batch(&mem.bb, bb, bb_size, region);
+	igt_assert(mem.src.width == mem.dst.width);
+
+	blt_mem_copy(fd, ctx, NULL, ahnd, &mem);
+	result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size);
+	igt_assert_f(!result, "source and destination differ\n");
+
+	intel_allocator_bind(ahnd, 0, 0);
+	munmap(mem.src.ptr, size);
+	munmap(mem.dst.ptr, size);
+	gem_close(fd, bb);
+	put_ahnd(ahnd);
+}
+
+/**
+ * SUBTEST: mem-set-linear-%s
+ * Description: Test validates MEM_SET command with size %arg[1].
+ * Test category: functionality test
+ *
+ * arg[1]:
+ *
+ * @0x369: 0x369
+ * @0x3fff: 0x3fff
+ * @0xfd: 0xfd
+ * @0xfffe: 0xfffe
+ */
+static void mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx,
+			uint32_t size, uint32_t width, uint32_t height,
+			uint8_t fill_data, uint32_t region)
+{
+	struct blt_mem_data mem = {};
+	uint64_t bb_size = xe_get_default_alignment(fd);
+	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
+						  INTEL_ALLOCATOR_SIMPLE,
+						  ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+	uint32_t bb;
+	uint8_t *result;
+	uint8_t dst_mocs = intel_get_uc_mocs_index(fd);
+
+	bb = xe_bo_create_flags(fd, 0, bb_size, region);
+	blt_mem_init(fd, &mem);
+	blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height, region,
+			   dst_mocs, M_LINEAR, COMPRESSION_DISABLED);
+	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
+	blt_set_batch(&mem.bb, bb, bb_size, region);
+	blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data);
+
+	result = (uint8_t *)mem.dst.ptr;
+
+	igt_assert(result[0] == fill_data);
+	igt_assert(result[width - 1] == fill_data);
+	igt_assert(result[width] != fill_data);
+
+	intel_allocator_bind(ahnd, 0, 0);
+	munmap(mem.dst.ptr, size);
+	gem_close(fd, bb);
+	put_ahnd(ahnd);
+}
+
+static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region)
+{
+	struct drm_xe_engine_class_instance inst = {
+		.engine_class = DRM_XE_ENGINE_CLASS_COPY,
+	};
+	uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size;
+	uint32_t bo_size = ALIGN(size, xe_get_default_alignment(fd));
+	const intel_ctx_t *ctx;
+
+	src_handle = xe_bo_create_flags(fd, 0, bo_size, region);
+	dst_handle = xe_bo_create_flags(fd, 0, bo_size, region);
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+	exec_queue = xe_exec_queue_create(fd, vm, &inst, 0);
+	ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0);
+
+	src_size = bo_size;
+	dst_size = bo_size;
+
+	if (cmd == MEM_COPY)
+		mem_copy(fd, src_handle, dst_handle, ctx, src_size, size, 1, region);
+	else if (cmd == MEM_SET)
+		mem_set(fd, dst_handle, ctx, dst_size, size, 1, MEM_FILL, region);
+
+	gem_close(fd, src_handle);
+	gem_close(fd, dst_handle);
+	xe_exec_queue_destroy(fd, exec_queue);
+	xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+	int fd;
+	struct igt_collection *set, *regions;
+	uint32_t region;
+	uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFE};
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_XE);
+		xe_device_get(fd);
+		set = xe_get_memory_region_set(fd,
+					       XE_MEM_REGION_CLASS_SYSMEM,
+					       XE_MEM_REGION_CLASS_VRAM);
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(size); i++) {
+		igt_subtest_f("mem-copy-linear-0x%lx", size[i]) {
+			igt_require(blt_has_mem_copy(fd));
+			for_each_variation_r(regions, 1, set) {
+				region = igt_collection_get_value(regions, 0);
+				copy_test(fd, size[i], MEM_COPY, region);
+			}
+		}
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(size); i++) {
+		igt_subtest_f("mem-set-linear-0x%lx", size[i]) {
+			igt_require(blt_has_mem_set(fd));
+			for_each_variation_r(regions, 1, set) {
+				region = igt_collection_get_value(regions, 0);
+				copy_test(fd, size[i], MEM_SET, region);
+			}
+		}
+	}
+
+	igt_fixture {
+		drm_close_driver(fd);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 2c2e1ca9a..5b19994f7 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -275,6 +275,7 @@ intel_xe_progs = [
 	'xe_ccs',
 	'xe_create',
 	'xe_compute',
+	'xe_copy_basic',
 	'xe_dma_buf_sync',
 	'xe_debugfs',
 	'xe_drm_fdinfo',
-- 
2.39.1

Re: [igt-dev] [PATCH i-g-t 3/3] intel/xe_copy_basic: Add copy basic test to exercise blt commands

[Zbigniew Kempczyński]

On Mon, Oct 16, 2023 at 11:37:16PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Add copy basic test to exercise copy commands like mem-copy and mem-set.
> 
> Cc: Karolina Stolarek <karolina.stolarek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  tests/intel/xe_copy_basic.c | 192 ++++++++++++++++++++++++++++++++++++
>  tests/meson.build           |   1 +
>  2 files changed, 193 insertions(+)
>  create mode 100644 tests/intel/xe_copy_basic.c
> 
> diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
> new file mode 100644
> index 000000000..253631102
> --- /dev/null
> +++ b/tests/intel/xe_copy_basic.c
> @@ -0,0 +1,192 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + *
> + * Authors:
> + *      Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> + */
> +
> +#include "igt.h"
> +#include "lib/igt_syncobj.h"
> +#include "intel_blt.h"
> +#include "lib/intel_cmds_info.h"
> +#include "lib/intel_mocs.h"
> +#include "lib/intel_reg.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include "xe/xe_util.h"
> +
> +#define MEM_FILL 0x8b
> +
> +/**
> + * TEST: Test to validate copy commands on xe
> + * Category: Software building block
> + * Sub-category: Copy
> + * Functionality: blitter
> + */
> +
> +/**
> + * SUBTEST: mem-copy-linear-%s
> + * Description: Test validates MEM_COPY command, it takes various
> + *              parameters needed for the filling batch buffer for MEM_COPY command
> + *              with size %arg[1].
> + * Test category: functionality test
> + *
> + * arg[1]:
> + * @0x369: 0x369
> + * @0x3fff: 0x3fff
> + * @0xfd: 0xfd
> + * @0xfffe: 0xfffe
> + */
> +static void
> +mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle,
> +		 const intel_ctx_t *ctx, uint32_t size, uint32_t width,
> +		 uint32_t height, uint32_t region)

Here I got objections about formatting.

> +{
> +	struct blt_mem_data mem = {};
> +	uint64_t bb_size = xe_get_default_alignment(fd);
> +	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
> +						  INTEL_ALLOCATOR_SIMPLE,
> +						  ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> +	uint32_t bb;
> +	int result;
> +	uint8_t src_mocs = intel_get_uc_mocs_index(fd);
> +	uint8_t dst_mocs = src_mocs;
> +
> +	bb = xe_bo_create_flags(fd, 0, bb_size, region);
> +
> +	blt_mem_init(fd, &mem);
> +	blt_set_mem_object(&mem.src, src_handle, size, 0, width, height,
> +			   region, src_mocs, M_LINEAR, COMPRESSION_DISABLED);
> +	blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height,
> +			   region, dst_mocs, M_LINEAR, COMPRESSION_DISABLED);
> +	mem.src.ptr = xe_bo_map(fd, src_handle, size);
> +	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
> +
> +	blt_set_batch(&mem.bb, bb, bb_size, region);
> +	igt_assert(mem.src.width == mem.dst.width);
> +
> +	blt_mem_copy(fd, ctx, NULL, ahnd, &mem);
> +	result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size);
> +	igt_assert_f(!result, "source and destination differ\n");
> +
> +	intel_allocator_bind(ahnd, 0, 0);
> +	munmap(mem.src.ptr, size);
> +	munmap(mem.dst.ptr, size);
> +	gem_close(fd, bb);
> +	put_ahnd(ahnd);
> +}
> +
> +/**
> + * SUBTEST: mem-set-linear-%s
> + * Description: Test validates MEM_SET command with size %arg[1].
> + * Test category: functionality test
> + *
> + * arg[1]:
> + *
> + * @0x369: 0x369
> + * @0x3fff: 0x3fff
> + * @0xfd: 0xfd
> + * @0xfffe: 0xfffe
> + */
> +static void mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx,
> +			uint32_t size, uint32_t width, uint32_t height,
> +			uint8_t fill_data, uint32_t region)

And here.

--
Zbigniew
> +{
> +	struct blt_mem_data mem = {};
> +	uint64_t bb_size = xe_get_default_alignment(fd);
> +	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
> +						  INTEL_ALLOCATOR_SIMPLE,
> +						  ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> +	uint32_t bb;
> +	uint8_t *result;
> +	uint8_t dst_mocs = intel_get_uc_mocs_index(fd);
> +
> +	bb = xe_bo_create_flags(fd, 0, bb_size, region);
> +	blt_mem_init(fd, &mem);
> +	blt_set_mem_object(&mem.dst, dst_handle, size, 0, width, height, region,
> +			   dst_mocs, M_LINEAR, COMPRESSION_DISABLED);
> +	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
> +	blt_set_batch(&mem.bb, bb, bb_size, region);
> +	blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data);
> +
> +	result = (uint8_t *)mem.dst.ptr;
> +
> +	igt_assert(result[0] == fill_data);
> +	igt_assert(result[width - 1] == fill_data);
> +	igt_assert(result[width] != fill_data);
> +
> +	intel_allocator_bind(ahnd, 0, 0);
> +	munmap(mem.dst.ptr, size);
> +	gem_close(fd, bb);
> +	put_ahnd(ahnd);
> +}
> +
> +static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region)
> +{
> +	struct drm_xe_engine_class_instance inst = {
> +		.engine_class = DRM_XE_ENGINE_CLASS_COPY,
> +	};
> +	uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size;
> +	uint32_t bo_size = ALIGN(size, xe_get_default_alignment(fd));
> +	const intel_ctx_t *ctx;
> +
> +	src_handle = xe_bo_create_flags(fd, 0, bo_size, region);
> +	dst_handle = xe_bo_create_flags(fd, 0, bo_size, region);
> +	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> +	exec_queue = xe_exec_queue_create(fd, vm, &inst, 0);
> +	ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0);
> +
> +	src_size = bo_size;
> +	dst_size = bo_size;
> +
> +	if (cmd == MEM_COPY)
> +		mem_copy(fd, src_handle, dst_handle, ctx, src_size, size, 1, region);
> +	else if (cmd == MEM_SET)
> +		mem_set(fd, dst_handle, ctx, dst_size, size, 1, MEM_FILL, region);
> +
> +	gem_close(fd, src_handle);
> +	gem_close(fd, dst_handle);
> +	xe_exec_queue_destroy(fd, exec_queue);
> +	xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> +	int fd;
> +	struct igt_collection *set, *regions;
> +	uint32_t region;
> +	uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFE};
> +
> +	igt_fixture {
> +		fd = drm_open_driver(DRIVER_XE);
> +		xe_device_get(fd);
> +		set = xe_get_memory_region_set(fd,
> +					       XE_MEM_REGION_CLASS_SYSMEM,
> +					       XE_MEM_REGION_CLASS_VRAM);
> +	}
> +
> +	for (int i = 0; i < ARRAY_SIZE(size); i++) {
> +		igt_subtest_f("mem-copy-linear-0x%lx", size[i]) {
> +			igt_require(blt_has_mem_copy(fd));
> +			for_each_variation_r(regions, 1, set) {
> +				region = igt_collection_get_value(regions, 0);
> +				copy_test(fd, size[i], MEM_COPY, region);
> +			}
> +		}
> +	}
> +
> +	for (int i = 0; i < ARRAY_SIZE(size); i++) {
> +		igt_subtest_f("mem-set-linear-0x%lx", size[i]) {
> +			igt_require(blt_has_mem_set(fd));
> +			for_each_variation_r(regions, 1, set) {
> +				region = igt_collection_get_value(regions, 0);
> +				copy_test(fd, size[i], MEM_SET, region);
> +			}
> +		}
> +	}
> +
> +	igt_fixture {
> +		drm_close_driver(fd);
> +	}
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index 2c2e1ca9a..5b19994f7 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -275,6 +275,7 @@ intel_xe_progs = [
>  	'xe_ccs',
>  	'xe_create',
>  	'xe_compute',
> +	'xe_copy_basic',
>  	'xe_dma_buf_sync',
>  	'xe_debugfs',
>  	'xe_drm_fdinfo',
> -- 
> 2.39.1
> 

[igt-dev] ✓ CI.xeBAT: success for Add copy basic test to exercise blt commands (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3458 bytes --]

== Series Details ==

Series: Add copy basic test to exercise blt commands (rev7)
URL   : https://patchwork.freedesktop.org/series/122615/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7541_BAT -> XEIGTPW_10008_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_10008_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1:
    - bat-adlp-7:         [PASS][1] -> [FAIL][2] ([Intel XE#480])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7541/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10008/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
    - bat-adlp-7:         [FAIL][3] ([i915#2346]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7541/bat-adlp-7/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10008/bat-adlp-7/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
    - bat-adlp-7:         [FAIL][5] ([Intel XE#480]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7541/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10008/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html

  * {igt@xe_create@create-execqueues-noleak}:
    - bat-adlp-7:         [FAIL][7] ([Intel XE#524]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7541/bat-adlp-7/igt@xe_create@create-execqueues-noleak.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10008/bat-adlp-7/igt@xe_create@create-execqueues-noleak.html

  * igt@xe_exec_reset@virtual-close-fd-no-exec:
    - bat-pvc-2:          [DMESG-WARN][9] ([Intel XE#696]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7541/bat-pvc-2/igt@xe_exec_reset@virtual-close-fd-no-exec.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10008/bat-pvc-2/igt@xe_exec_reset@virtual-close-fd-no-exec.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480
  [Intel XE#524]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/524
  [Intel XE#696]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/696
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346


Build changes
-------------

  * IGT: IGT_7541 -> IGTPW_10008
  * Linux: xe-435-ab7cd1b4af95baba2d6ce5487d35ffda523e895d -> xe-436-9471d9e9efb920d70538445ffa07193d603b8cdb

  IGTPW_10008: 10008
  IGT_7541: fcddb77c3f8a77020f7f3b2660a66cae27cfaa2b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-435-ab7cd1b4af95baba2d6ce5487d35ffda523e895d: ab7cd1b4af95baba2d6ce5487d35ffda523e895d
  xe-436-9471d9e9efb920d70538445ffa07193d603b8cdb: 9471d9e9efb920d70538445ffa07193d603b8cdb

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10008/index.html

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[igt-dev] ✗ Fi.CI.BAT: failure for Add copy basic test to exercise blt commands (rev7)

[Patchwork]

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== Series Details ==

Series: Add copy basic test to exercise blt commands (rev7)
URL   : https://patchwork.freedesktop.org/series/122615/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13762 -> IGTPW_10008
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_10008 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_10008, please notify your bug team (lgci.bug.filing@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/index.html

Participating hosts (33 -> 34)
------------------------------

  Additional (1): bat-dg2-9 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_10008:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - bat-dg2-11:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13762/bat-dg2-11/igt@gem_exec_suspend@basic-s3@smem.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-11/igt@gem_exec_suspend@basic-s3@smem.html

  
Known issues
------------

  Here are the changes found in IGTPW_10008 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - bat-jsl-3:          [PASS][3] -> [INCOMPLETE][4] ([i915#9275])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13762/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_mmap@basic:
    - bat-dg2-9:          NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-dg2-9:          NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@gem_mmap_gtt@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-dg2-9:          NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@gem_render_tiled_blits@basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg2-9:          NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@mman:
    - bat-rpls-1:         [PASS][9] -> [TIMEOUT][10] ([i915#6794] / [i915#7392])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13762/bat-rpls-1/igt@i915_selftest@live@mman.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-rpls-1/igt@i915_selftest@live@mman.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - bat-rpls-1:         [PASS][11] -> [WARN][12] ([i915#8747])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13762/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-jsl-3:          [PASS][13] -> [FAIL][14] ([fdo#103375])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13762/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-dg2-9:          NOTRUN -> [SKIP][15] ([i915#5190])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg2-9:          NOTRUN -> [SKIP][16] ([i915#4215] / [i915#5190])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
    - bat-dg2-9:          NOTRUN -> [SKIP][17] ([i915#4212]) +6 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - bat-dg2-9:          NOTRUN -> [SKIP][18] ([i915#4212] / [i915#5608])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-dg2-9:          NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-dg2-9:          NOTRUN -> [SKIP][20] ([fdo#109285])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-dg2-9:          NOTRUN -> [SKIP][21] ([i915#5274])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
    - bat-rplp-1:         [PASS][22] -> [ABORT][23] ([i915#8668])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13762/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-dg2-9:          NOTRUN -> [SKIP][24] ([i915#1072]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-dg2-9:          NOTRUN -> [SKIP][25] ([i915#3555] / [i915#4098])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg2-9:          NOTRUN -> [SKIP][26] ([i915#3708])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-dg2-9:          NOTRUN -> [SKIP][27] ([i915#3708] / [i915#4077]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
    - bat-dg2-9:          NOTRUN -> [SKIP][28] ([i915#3291] / [i915#3708]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/bat-dg2-9/igt@prime_vgem@basic-write.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
  [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8747]: https://gitlab.freedesktop.org/drm/intel/issues/8747
  [i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7541 -> IGTPW_10008

  CI-20190529: 20190529
  CI_DRM_13762: 5f3d2f483aa4182d5d6e6629d56f46a1f38168c4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_10008: 10008
  IGT_7541: fcddb77c3f8a77020f7f3b2660a66cae27cfaa2b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@xe_copy_basic@mem-copy-linear-0x3fff
+igt@xe_copy_basic@mem-copy-linear-0x369
+igt@xe_copy_basic@mem-copy-linear-0xfd
+igt@xe_copy_basic@mem-copy-linear-0xfffe
+igt@xe_copy_basic@mem-set-linear-0x3fff
+igt@xe_copy_basic@mem-set-linear-0x369
+igt@xe_copy_basic@mem-set-linear-0xfd
+igt@xe_copy_basic@mem-set-linear-0xfffe
-igt@kms_closefb@closefb-ioctl

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10008/index.html

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Re: [igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands

[Zbigniew Kempczyński]

On Mon, Oct 16, 2023 at 11:37:13PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Add copy basic test which exercies mem-se and mem-copy commands, this
> patch series involves in following changes:
> 
> 1. Add copy basic test to exercise blt commands.
> 2. Add wrappers for batch preparation and submit exec.
> 3. Add copy commands MEM_SET_CMD and MEM_COPY_CMD in the lib.

May you check your patches with checkpatch? I see there's mixing
of spaces and tabs indentation as well as function arguments are
not aligned properly.

--
Zbigniew

> 
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Sai Gowtham Ch (3):
>   lib/intel_blt: Add wrappers to prepare batch buffers and submit exec
>   lib/intel_cmds_info: Add M_MATRIX in mem_copy as it is supported for
>     PVC
>   intel/xe_copy_basic: Add copy basic test to exercise blt commands
> 
>  lib/intel_blt.c             | 200 ++++++++++++++++++++++++++++++++++++
>  lib/intel_blt.h             |  39 +++++++
>  lib/intel_cmds_info.c       |   3 +-
>  lib/intel_reg.h             |   4 +
>  tests/intel/xe_copy_basic.c | 192 ++++++++++++++++++++++++++++++++++
>  tests/meson.build           |   1 +
>  6 files changed, 438 insertions(+), 1 deletion(-)
>  create mode 100644 tests/intel/xe_copy_basic.c
> 
> -- 
> 2.39.1
> 

[igt-dev] [PATCH i-g-t 0/3] Add copy basic test to exercise blt commands

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Add copy basic test which exercies mem-se and mem-copy commands, this
patch series involves in following changes:

1. Add copy basic test to exercise blt commands.
2. Add wrappers for batch preparation and submit exec.
3. Add copy commands MEM_SET_CMD and MEM_COPY_CMD in the lib.

Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (3):
  lib/intel_blt: Add wrappers to prepare batch buffers and submit exec
  lib/intel_cmds_info: Add M_MATRIX in mem_copy as it is supported for
    PVC
  intel/xe_copy_basic: Add copy basic test to exercise blt commands

 lib/intel_blt.c             | 200 ++++++++++++++++++++++++++++++++++++
 lib/intel_blt.h             |  39 +++++++
 lib/intel_cmds_info.c       |   3 +-
 lib/intel_reg.h             |   4 +
 tests/intel/xe_copy_basic.c | 191 ++++++++++++++++++++++++++++++++++
 tests/meson.build           |   1 +
 6 files changed, 437 insertions(+), 1 deletion(-)
 create mode 100644 tests/intel/xe_copy_basic.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 1/3] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Adding wrapper for mem-set and mem-copy instructions to prepare
batch buffers and submit exec, (blt_mem_copy, blt_mem_set,
emit_blt_mem_copy, emit_blt_set_mem)

Cc: Karolina Stolarek <karolina.stolarek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_blt.c | 200 ++++++++++++++++++++++++++++++++++++++++++++++++
 lib/intel_blt.h |  39 ++++++++++
 lib/intel_reg.h |   4 +
 3 files changed, 243 insertions(+)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index a76c7a404..28dc9e96b 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -13,12 +13,14 @@
 #include "igt.h"
 #include "igt_syncobj.h"
 #include "intel_blt.h"
+#include "intel_mocs.h"
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "xe/xe_util.h"
 
 #define BITRANGE(start, end) (end - start + 1)
 #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
+#define MEM_COPY_MOCS_SHIFT                     25
 
 /* Blitter tiling definitions sanity checks */
 static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have to match");
@@ -1577,6 +1579,187 @@ int blt_fast_copy(int fd,
 	return ret;
 }
 
+/**
+ * blt_mem_init:
+ * @fd: drm fd
+ * @mem: structure for initialization
+ *
+ * Function is zeroing @mem and sets fd and driver fields (INTEL_DRIVER_I915 or
+ * INTEL_DRIVER_XE).
+ */
+void blt_mem_init(int fd, struct blt_mem_data *mem)
+{
+	memset(mem, 0, sizeof(*mem));
+
+	mem->fd = fd;
+	mem->driver = get_intel_driver(fd);
+}
+
+static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem)
+{
+	uint64_t dst_offset, src_offset, alignment;
+	int i;
+	uint32_t *batch;
+	uint32_t optype;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+
+	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
+	optype = mem->src.type == M_MATRIX ? 1 << 17 : 0;
+
+	i = 0;
+	batch[i++] = MEM_COPY_CMD | (1 << 19) | optype;
+	batch[i++] = mem->src.width - 1;
+	batch[i++] = mem->src.height - 1;
+	batch[i++] = mem->src.pitch - 1;
+	batch[i++] = mem->dst.pitch - 1;
+	batch[i++] = src_offset;
+	batch[i++] = src_offset << 32;
+	batch[i++] = dst_offset;
+	batch[i++] = dst_offset << 32;
+	batch[i++] = mem->src.mocs_index << MEM_COPY_MOCS_SHIFT | mem->dst.mocs_index;
+	batch[i++] = MI_BATCH_BUFFER_END;
+
+	munmap(batch, mem->bb.size);
+}
+
+/**
+ * blt_mem_copy:
+ * @fd: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @blt: blitter data for mem-copy.
+ *
+ * Function does mem blit between @src and @dst described in @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_mem_copy(int fd, const intel_ctx_t *ctx,
+		 const struct intel_execution_engine2 *e,
+		 uint64_t ahnd,
+		 const struct blt_mem_data *mem)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	uint64_t dst_offset, src_offset, bb_offset, alignment;
+	int ret;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
+
+	emit_blt_mem_copy(fd, ahnd, mem);
+
+	if (mem->driver == INTEL_DRIVER_XE) {
+		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+	} else {
+		obj[0].offset = CANONICAL(dst_offset);
+		obj[1].offset = CANONICAL(src_offset);
+		obj[2].offset = CANONICAL(bb_offset);
+		obj[0].handle = mem->dst.handle;
+		obj[1].handle = mem->src.handle;
+		obj[2].handle = mem->bb.handle;
+		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+			       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		execbuf.buffer_count = 3;
+		execbuf.buffers_ptr = to_user_pointer(obj);
+		execbuf.rsvd1 = ctx ? ctx->id : 0;
+		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+		ret = __gem_execbuf(fd, &execbuf);
+		put_offset(ahnd, mem->dst.handle);
+		put_offset(ahnd, mem->src.handle);
+		put_offset(ahnd, mem->bb.handle);
+	}
+
+	return ret;
+}
+
+static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem,
+			     uint8_t fill_data)
+{
+	uint64_t dst_offset, alignment;
+	int b;
+	uint32_t *batch;
+	uint32_t value;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+
+	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
+	value = (uint32_t)fill_data << 24;
+
+	b = 0;
+	batch[b++] = MEM_SET_CMD;
+	batch[b++] = mem->dst.width - 1;
+	batch[b++] = mem->dst.height - 1;
+	batch[b++] = mem->dst.pitch - 1;
+	batch[b++] = dst_offset;
+	batch[b++] = dst_offset << 32;
+	batch[b++] = value | mem->dst.mocs_index;
+	batch[b++] = MI_BATCH_BUFFER_END;
+
+	munmap(batch, mem->bb.size);
+
+}
+/**
+ * blt_mem_set:
+ * @fd: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @blt: blitter data for mem-set.
+ *
+ * Function does mem set blit in described @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_mem_set(int fd, const intel_ctx_t *ctx,
+		const struct intel_execution_engine2 *e,
+		uint64_t ahnd,
+		const struct blt_mem_data *mem,
+		uint8_t fill_data)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[2] = {};
+	uint64_t dst_offset, bb_offset, alignment;
+	int ret;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
+
+	emit_blt_mem_set(fd, ahnd, mem, fill_data);
+
+	if (mem->driver == INTEL_DRIVER_XE) {
+		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+	} else {
+		obj[0].offset = CANONICAL(dst_offset);
+		obj[1].offset = CANONICAL(bb_offset);
+		obj[0].handle = mem->dst.handle;
+		obj[1].handle = mem->bb.handle;
+		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+						    EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		execbuf.buffer_count = 2;
+		execbuf.buffers_ptr = to_user_pointer(obj);
+		execbuf.rsvd1 = ctx ? ctx->id : 0;
+		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+		ret = __gem_execbuf(fd, &execbuf);
+		put_offset(ahnd, mem->dst.handle);
+		put_offset(ahnd, mem->bb.handle);
+	}
+
+	return ret;
+}
+
 void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
 		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
 		  uint16_t x_offset, uint16_t y_offset)
@@ -1659,6 +1842,23 @@ void blt_set_object(struct blt_copy_object *obj,
 	obj->compression_type = compression_type;
 }
 
+void blt_set_mem_object(struct blt_mem_object *obj,
+			uint32_t handle, uint64_t size, uint32_t pitch,
+			uint32_t width, uint32_t height, uint32_t region,
+			uint8_t mocs_index, enum blt_memop_type type,
+			enum blt_compression compression)
+{
+	obj->handle = handle;
+	obj->region = region;
+	obj->size = size;
+	obj->mocs_index = mocs_index;
+	obj->type = type;
+	obj->compression = compression;
+	obj->width = width;
+	obj->height = height;
+	obj->pitch = pitch;
+}
+
 void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
 			uint8_t compression_format,
 			uint16_t surface_width, uint16_t surface_height,
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index 7b4271620..01a7e117a 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -93,6 +93,19 @@ struct blt_copy_object {
 	uint32_t plane_offset;
 };
 
+struct blt_mem_object {
+	uint32_t handle;
+	uint32_t region;
+	uint64_t size;
+	uint8_t mocs_index;
+	enum blt_memop_type type;
+	enum blt_compression compression;
+	uint32_t width;
+	uint32_t height;
+	uint32_t pitch;
+	uint32_t *ptr;
+};
+
 struct blt_copy_batch {
 	uint32_t handle;
 	uint32_t region;
@@ -112,6 +125,14 @@ struct blt_copy_data {
 	bool print_bb;
 };
 
+struct blt_mem_data {
+	int fd;
+	enum intel_driver driver;
+	struct blt_mem_object src;
+	struct blt_mem_object dst;
+	struct blt_copy_batch bb;
+};
+
 enum blt_surface_type {
 	SURFACE_TYPE_1D,
 	SURFACE_TYPE_2D,
@@ -231,6 +252,17 @@ int blt_fast_copy(int fd,
 		  uint64_t ahnd,
 		  const struct blt_copy_data *blt);
 
+void blt_mem_init(int fd, struct blt_mem_data *mem);
+
+int blt_mem_copy(int fd, const intel_ctx_t *ctx,
+			 const struct intel_execution_engine2 *e,
+			 uint64_t ahnd,
+			 const struct blt_mem_data *mem);
+
+int blt_mem_set(int fd, const intel_ctx_t *ctx,
+			const struct intel_execution_engine2 *e, uint64_t ahnd,
+			const struct blt_mem_data *mem, uint8_t fill_data);
+
 void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
 		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
 		  uint16_t x_offset, uint16_t y_offset);
@@ -250,6 +282,13 @@ void blt_set_object(struct blt_copy_object *obj,
 		    uint8_t mocs_index, enum blt_tiling_type tiling,
 		    enum blt_compression compression,
 		    enum blt_compression_type compression_type);
+
+void blt_set_mem_object(struct blt_mem_object *obj,
+			uint32_t handle, uint64_t size, uint32_t pitch,
+			uint32_t width, uint32_t height, uint32_t region,
+			uint8_t mocs_index, enum blt_memop_type type,
+			enum blt_compression compression);
+
 void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
 			uint8_t compression_format,
 			uint16_t surface_width, uint16_t surface_height,
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ea463376b..a8190d683 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2588,6 +2588,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define   XY_FAST_COPY_COLOR_DEPTH_64			(4  << 24)
 #define   XY_FAST_COPY_COLOR_DEPTH_128			(5  << 24)
 
+/* RAW memory commands */
+#define MEM_COPY_CMD                    ((0x2 << 29)|(0x5a << 22)|0x8)
+#define MEM_SET_CMD                     ((0x2 << 29)|(0x5b << 22)|0x5)
+
 #define CTXT_NO_RESTORE			(1)
 #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
 #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
-- 
2.39.1