* [igt-dev] [PATCH v3 i-g-t] tests/amd_security: add secure write test for gfx
@ 2023-10-31 2:40 Jesse Zhang
2023-10-31 3:29 ` [igt-dev] ✓ CI.xeBAT: success for tests/amd_security: add secure write test for gfx (rev4) Patchwork
2023-10-31 3:35 ` [igt-dev] ✗ Fi.CI.BAT: failure " Patchwork
0 siblings, 2 replies; 3+ messages in thread
From: Jesse Zhang @ 2023-10-31 2:40 UTC (permalink / raw)
To: igt-dev; +Cc: Tim Huang, Luben Tuikov, Alex Deucher, Christian Koenig
To verify writes in Trusted Memory Zone(TMZ),
add secure writing and verify the results of gfx.
V3:
- Improve description and coding style.
Encoding using helpers for high and low 32 bits (Kamil)
- Add i-g-t for the subject and
replace the "_" with spaces in igt_describe(Kamil)
- rename new method 'atomic' to 'write_linear_atomic'(Vitaly)
- use macro 'lower_32_bits' based Kamil's suggestion (Vitaly)
Cc: Vitaly Prosyak <vitaly.prosyak@amd.com>
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
lib/amdgpu/amd_command_submission.c | 9 +-
lib/amdgpu/amd_ip_blocks.c | 187 ++++++++++++++++------------
lib/amdgpu/amd_ip_blocks.h | 1 +
tests/amdgpu/amd_security.c | 13 +-
4 files changed, 118 insertions(+), 92 deletions(-)
diff --git a/lib/amdgpu/amd_command_submission.c b/lib/amdgpu/amd_command_submission.c
index b674ba640..c5e900b0c 100644
--- a/lib/amdgpu/amd_command_submission.c
+++ b/lib/amdgpu/amd_command_submission.c
@@ -165,20 +165,19 @@ void amdgpu_command_submission_write_linear_helper(amdgpu_device_handle device,
r = ip_block->funcs->compare(ip_block->funcs, ring_context, 1);
igt_assert_eq(r, 0);
} else if (ip_block->type == AMDGPU_HW_IP_GFX) {
- ip_block->funcs->write_linear(ip_block->funcs, ring_context, &ring_context->pm4_dw);
-
+ ip_block->funcs->write_linear_atomic(ip_block->funcs, ring_context, &ring_context->pm4_dw);
amdgpu_test_exec_cs_helper(device, ip_block->type, ring_context, 0);
-
} else if (ip_block->type == AMDGPU_HW_IP_DMA) {
/* restore the bo_cpu to compare */
ring_context->bo_cpu_origin = ring_context->bo_cpu[0];
- ip_block->funcs->write_linear(ip_block->funcs, ring_context, &ring_context->pm4_dw);
+ ip_block->funcs->write_linear_atomic(ip_block->funcs, ring_context, &ring_context->pm4_dw);
amdgpu_test_exec_cs_helper(device, ip_block->type, ring_context, 0);
+ igt_assert_neq(ring_context->bo_cpu[0], ring_context->bo_cpu_origin);
/* restore again, here dest_data should be */
ring_context->bo_cpu_origin = ring_context->bo_cpu[0];
- ip_block->funcs->write_linear(ip_block->funcs, ring_context, &ring_context->pm4_dw);
+ ip_block->funcs->write_linear_atomic(ip_block->funcs, ring_context, &ring_context->pm4_dw);
amdgpu_test_exec_cs_helper(device, ip_block->type, ring_context, 0);
/* here bo_cpu[0] should be unchanged, still is 0x12345678, otherwise failed*/
diff --git a/lib/amdgpu/amd_ip_blocks.c b/lib/amdgpu/amd_ip_blocks.c
index 96130ccd5..58a037ac0 100644
--- a/lib/amdgpu/amd_ip_blocks.c
+++ b/lib/amdgpu/amd_ip_blocks.c
@@ -18,6 +18,7 @@
#include "amdgpu_asic_addr.h"
#include "amd_family.h"
#include "amd_gfx_v8_0.h"
+#include "ioctl_wrappers.h"
/*
* SDMA functions:
@@ -34,48 +35,58 @@ sdma_ring_write_linear(const struct amdgpu_ip_funcs *func,
i = 0;
j = 0;
- if (ring_context->secure == false) {
- if (func->family_id == AMDGPU_FAMILY_SI)
- ring_context->pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0,
- ring_context->write_length);
- else
- ring_context->pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
- SDMA_WRITE_SUB_OPCODE_LINEAR,
- ring_context->secure ? SDMA_ATOMIC_TMZ(1) : 0);
+ if (func->family_id == AMDGPU_FAMILY_SI)
+ ring_context->pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0,
+ ring_context->write_length);
+ else
+ ring_context->pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
+ SDMA_WRITE_SUB_OPCODE_LINEAR,
+ ring_context->secure ? SDMA_ATOMIC_TMZ(1) : 0);
+
+ ring_context->pm4[i++] = lower_32_bits(ring_context->bo_mc);
+ ring_context->pm4[i++] = upper_32_bits(ring_context->bo_mc);
+ if (func->family_id >= AMDGPU_FAMILY_AI)
+ ring_context->pm4[i++] = ring_context->write_length - 1;
+ else
+ ring_context->pm4[i++] = ring_context->write_length;
- ring_context->pm4[i++] = 0xfffffffc & ring_context->bo_mc;
- ring_context->pm4[i++] = (0xffffffff00000000 & ring_context->bo_mc) >> 32;
- if (func->family_id >= AMDGPU_FAMILY_AI)
- ring_context->pm4[i++] = ring_context->write_length - 1;
- else
- ring_context->pm4[i++] = ring_context->write_length;
+ while (j++ < ring_context->write_length)
+ ring_context->pm4[i++] = func->deadbeaf;
- while (j++ < ring_context->write_length)
- ring_context->pm4[i++] = func->deadbeaf;
- } else {
- memset(ring_context->pm4, 0, ring_context->pm4_size * sizeof(uint32_t));
+ *pm4_dw = i;
+
+ return 0;
+}
+
+static int
+sdma_ring_atomic(const struct amdgpu_ip_funcs *func,
+ const struct amdgpu_ring_context *ring_context,
+ uint32_t *pm4_dw)
+{
+ uint32_t i = 0;
+
+ memset(ring_context->pm4, 0, ring_context->pm4_size * sizeof(uint32_t));
/* atomic opcode for 32b w/ RTN and ATOMIC_SWAPCMP_RTN
* loop, 1-loop_until_compare_satisfied.
* single_pass_atomic, 0-lru
*/
- ring_context->pm4[i++] = SDMA_PACKET(SDMA_OPCODE_ATOMIC,
- 0,
- SDMA_ATOMIC_LOOP(1) |
- SDMA_ATOMIC_TMZ(1) |
- SDMA_ATOMIC_OPCODE(TC_OP_ATOMIC_CMPSWAP_RTN_32));
- ring_context->pm4[i++] = 0xfffffffc & ring_context->bo_mc;
- ring_context->pm4[i++] = (0xffffffff00000000 & ring_context->bo_mc) >> 32;
- ring_context->pm4[i++] = 0x12345678;
- ring_context->pm4[i++] = 0x0;
- ring_context->pm4[i++] = func->deadbeaf;
- ring_context->pm4[i++] = 0x0;
- ring_context->pm4[i++] = 0x100;
- }
-
+ ring_context->pm4[i++] = SDMA_PACKET(SDMA_OPCODE_ATOMIC,
+ 0,
+ SDMA_ATOMIC_LOOP(1) |
+ (ring_context->secure ? SDMA_ATOMIC_TMZ(1) : SDMA_ATOMIC_TMZ(0)) |
+ SDMA_ATOMIC_OPCODE(TC_OP_ATOMIC_CMPSWAP_RTN_32));
+ ring_context->pm4[i++] = lower_32_bits(ring_context->bo_mc);
+ ring_context->pm4[i++] = upper_32_bits(ring_context->bo_mc);
+ ring_context->pm4[i++] = 0x12345678;
+ ring_context->pm4[i++] = 0x0;
+ ring_context->pm4[i++] = func->deadbeaf;
+ ring_context->pm4[i++] = 0x0;
+ ring_context->pm4[i++] = 0x100;
*pm4_dw = i;
return 0;
+
}
static int
@@ -89,14 +100,14 @@ sdma_ring_const_fill(const struct amdgpu_ip_funcs *func,
if (func->family_id == AMDGPU_FAMILY_SI) {
context->pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI,
0, 0, 0, context->write_length / 4);
- context->pm4[i++] = 0xfffffffc & context->bo_mc;
+ context->pm4[i++] = lower_32_bits(context->bo_mc);
context->pm4[i++] = 0xdeadbeaf;
- context->pm4[i++] = (0xffffffff00000000 & context->bo_mc) >> 16;
+ context->pm4[i++] = upper_32_bits(context->bo_mc) >> 16;
} else {
context->pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
SDMA_CONSTANT_FILL_EXTRA_SIZE(2));
- context->pm4[i++] = 0xffffffff & context->bo_mc;
- context->pm4[i++] = (0xffffffff00000000 & context->bo_mc) >> 32;
+ context->pm4[i++] = lower_32_bits(context->bo_mc);
+ context->pm4[i++] = upper_32_bits(context->bo_mc);
context->pm4[i++] = func->deadbeaf;
if (func->family_id >= AMDGPU_FAMILY_AI)
@@ -121,10 +132,10 @@ sdma_ring_copy_linear(const struct amdgpu_ip_funcs *func,
context->pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI,
0, 0, 0,
context->write_length);
- context->pm4[i++] = 0xffffffff & context->bo_mc;
- context->pm4[i++] = (0xffffffff00000000 & context->bo_mc) >> 32;
- context->pm4[i++] = 0xffffffff & context->bo_mc2;
- context->pm4[i++] = (0xffffffff00000000 & context->bo_mc2) >> 32;
+ context->pm4[i++] = lower_32_bits(context->bo_mc);
+ context->pm4[i++] = upper_32_bits(context->bo_mc);
+ context->pm4[i++] = lower_32_bits(context->bo_mc2);
+ context->pm4[i++] = upper_32_bits(context->bo_mc2);
} else {
context->pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY,
SDMA_COPY_SUB_OPCODE_LINEAR,
@@ -134,10 +145,10 @@ sdma_ring_copy_linear(const struct amdgpu_ip_funcs *func,
else
context->pm4[i++] = context->write_length;
context->pm4[i++] = 0;
- context->pm4[i++] = 0xffffffff & context->bo_mc;
- context->pm4[i++] = (0xffffffff00000000 & context->bo_mc) >> 32;
- context->pm4[i++] = 0xffffffff & context->bo_mc2;
- context->pm4[i++] = (0xffffffff00000000 & context->bo_mc2) >> 32;
+ context->pm4[i++] = lower_32_bits(context->bo_mc);
+ context->pm4[i++] = upper_32_bits(context->bo_mc);
+ context->pm4[i++] = lower_32_bits(context->bo_mc2);
+ context->pm4[i++] = upper_32_bits(context->bo_mc2);
}
*pm4_dw = i;
@@ -163,37 +174,45 @@ gfx_ring_write_linear(const struct amdgpu_ip_funcs *func,
i = 0;
j = 0;
- if (ring_context->secure == false) {
- ring_context->pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + ring_context->write_length);
- ring_context->pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
- ring_context->pm4[i++] = 0xfffffffc & ring_context->bo_mc;
- ring_context->pm4[i++] = (0xffffffff00000000 & ring_context->bo_mc) >> 32;
- while (j++ < ring_context->write_length)
- ring_context->pm4[i++] = func->deadbeaf;
- } else {
- memset(ring_context->pm4, 0, ring_context->pm4_size * sizeof(uint32_t));
+ ring_context->pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + ring_context->write_length);
+ ring_context->pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+ ring_context->pm4[i++] = lower_32_bits(ring_context->bo_mc);
+ ring_context->pm4[i++] = upper_32_bits(ring_context->bo_mc);
+ while (j++ < ring_context->write_length)
+ ring_context->pm4[i++] = func->deadbeaf;
+
+ *pm4_dw = i;
+ return 0;
+}
+
+static int
+gfx_ring_atomic(const struct amdgpu_ip_funcs *func,
+ const struct amdgpu_ring_context *ring_context,
+ uint32_t *pm4_dw)
+{
+ uint32_t i = 0;
+
+ memset(ring_context->pm4, 0, ring_context->pm4_size * sizeof(uint32_t));
ring_context->pm4[i++] = PACKET3(PACKET3_ATOMIC_MEM, 7);
- /* atomic opcode for 32b w/ RTN and ATOMIC_SWAPCMP_RTN
- * command, 1-loop_until_compare_satisfied.
- * single_pass_atomic, 0-lru
- * engine_sel, 0-micro_engine
- */
- ring_context->pm4[i++] = (TC_OP_ATOMIC_CMPSWAP_RTN_32 |
- ATOMIC_MEM_COMMAND(1) |
- ATOMIC_MEM_CACHEPOLICAY(0) |
- ATOMIC_MEM_ENGINESEL(0));
- ring_context->pm4[i++] = 0xfffffffc & ring_context->bo_mc;
- ring_context->pm4[i++] = (0xffffffff00000000 & ring_context->bo_mc) >> 32;
- ring_context->pm4[i++] = 0x12345678;
- ring_context->pm4[i++] = 0x0;
- ring_context->pm4[i++] = 0xdeadbeaf;
- ring_context->pm4[i++] = 0x0;
- ring_context->pm4[i++] = 0x100;
- }
+ /* atomic opcode for 32b w/ RTN and ATOMIC_SWAPCMP_RTN
+ * command, 1-loop_until_compare_satisfied.
+ * single_pass_atomic, 0-lru
+ * engine_sel, 0-micro_engine
+ */
+ ring_context->pm4[i++] = (TC_OP_ATOMIC_CMPSWAP_RTN_32 |
+ ATOMIC_MEM_COMMAND(1) |
+ ATOMIC_MEM_CACHEPOLICAY(0) |
+ ATOMIC_MEM_ENGINESEL(0));
+ ring_context->pm4[i++] = lower_32_bits(ring_context->bo_mc);
+ ring_context->pm4[i++] = upper_32_bits(ring_context->bo_mc);
+ ring_context->pm4[i++] = 0x12345678;
+ ring_context->pm4[i++] = 0x0;
+ ring_context->pm4[i++] = 0xdeadbeaf;
+ ring_context->pm4[i++] = 0x0;
+ ring_context->pm4[i++] = 0x100;
*pm4_dw = i;
-
return 0;
}
@@ -212,8 +231,8 @@ gfx_ring_const_fill(const struct amdgpu_ip_funcs *func,
PACKET3_DMA_DATA_SI_DST_SEL(0) |
PACKET3_DMA_DATA_SI_SRC_SEL(2) |
PACKET3_DMA_DATA_SI_CP_SYNC;
- ring_context->pm4[i++] = 0xffffffff & ring_context->bo_mc;
- ring_context->pm4[i++] = (0xffffffff00000000 & ring_context->bo_mc) >> 32;
+ ring_context->pm4[i++] = lower_32_bits(ring_context->bo_mc);
+ ring_context->pm4[i++] = upper_32_bits(ring_context->bo_mc);
ring_context->pm4[i++] = ring_context->write_length;
} else {
ring_context->pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
@@ -223,8 +242,8 @@ gfx_ring_const_fill(const struct amdgpu_ip_funcs *func,
PACKET3_DMA_DATA_CP_SYNC;
ring_context->pm4[i++] = func->deadbeaf;
ring_context->pm4[i++] = 0;
- ring_context->pm4[i++] = 0xfffffffc & ring_context->bo_mc;
- ring_context->pm4[i++] = (0xffffffff00000000 & ring_context->bo_mc) >> 32;
+ ring_context->pm4[i++] = lower_32_bits(ring_context->bo_mc);
+ ring_context->pm4[i++] = upper_32_bits(ring_context->bo_mc);
ring_context->pm4[i++] = ring_context->write_length;
}
*pm4_dw = i;
@@ -242,14 +261,14 @@ gfx_ring_copy_linear(const struct amdgpu_ip_funcs *func,
i = 0;
if (func->family_id == AMDGPU_FAMILY_SI) {
context->pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4);
- context->pm4[i++] = 0xfffffffc & context->bo_mc;
+ context->pm4[i++] = lower_32_bits(context->bo_mc);
context->pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) |
PACKET3_DMA_DATA_SI_DST_SEL(0) |
PACKET3_DMA_DATA_SI_SRC_SEL(0) |
PACKET3_DMA_DATA_SI_CP_SYNC |
- (0xffff00000000 & context->bo_mc) >> 32;
- context->pm4[i++] = 0xfffffffc & context->bo_mc2;
- context->pm4[i++] = (0xffffffff00000000 & context->bo_mc2) >> 32;
+ upper_32_bits(context->bo_mc);
+ context->pm4[i++] = lower_32_bits(context->bo_mc2);
+ context->pm4[i++] = upper_32_bits(context->bo_mc2);
context->pm4[i++] = context->write_length;
} else {
context->pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
@@ -257,10 +276,10 @@ gfx_ring_copy_linear(const struct amdgpu_ip_funcs *func,
PACKET3_DMA_DATA_DST_SEL(0) |
PACKET3_DMA_DATA_SRC_SEL(0) |
PACKET3_DMA_DATA_CP_SYNC;
- context->pm4[i++] = 0xfffffffc & context->bo_mc;
- context->pm4[i++] = (0xffffffff00000000 & context->bo_mc) >> 32;
- context->pm4[i++] = 0xfffffffc & context->bo_mc2;
- context->pm4[i++] = (0xffffffff00000000 & context->bo_mc2) >> 32;
+ context->pm4[i++] = lower_32_bits(context->bo_mc);
+ context->pm4[i++] = upper_32_bits(context->bo_mc);
+ context->pm4[i++] = lower_32_bits(context->bo_mc2);
+ context->pm4[i++] = upper_32_bits(context->bo_mc2);
context->pm4[i++] = context->write_length;
}
@@ -311,6 +330,7 @@ static struct amdgpu_ip_funcs gfx_v8_x_ip_funcs = {
.deadbeaf = 0xdeadbeaf,
.pattern = 0xaaaaaaaa,
.write_linear = gfx_ring_write_linear,
+ .write_linear_atomic = gfx_ring_atomic,
.const_fill = gfx_ring_const_fill,
.copy_linear = gfx_ring_copy_linear,
.compare = x_compare,
@@ -325,6 +345,7 @@ static struct amdgpu_ip_funcs sdma_v3_x_ip_funcs = {
.deadbeaf = 0xdeadbeaf,
.pattern = 0xaaaaaaaa,
.write_linear = sdma_ring_write_linear,
+ .write_linear_atomic = sdma_ring_atomic,
.const_fill = sdma_ring_const_fill,
.copy_linear = sdma_ring_copy_linear,
.compare = x_compare,
diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index 7f6fb3fb4..aef433e7f 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -70,6 +70,7 @@ struct amdgpu_ip_funcs {
uint32_t pattern;
/* functions */
int (*write_linear)(const struct amdgpu_ip_funcs *func, const struct amdgpu_ring_context *context, uint32_t *pm4_dw);
+ int (*write_linear_atomic)(const struct amdgpu_ip_funcs *func, const struct amdgpu_ring_context *context, uint32_t *pm4_dw);
int (*const_fill)(const struct amdgpu_ip_funcs *func, const struct amdgpu_ring_context *context, uint32_t *pm4_dw);
int (*copy_linear)(const struct amdgpu_ip_funcs *func, const struct amdgpu_ring_context *context, uint32_t *pm4_dw);
int (*compare)(const struct amdgpu_ip_funcs *func, const struct amdgpu_ring_context *context, int div);
diff --git a/tests/amdgpu/amd_security.c b/tests/amdgpu/amd_security.c
index 1a7eba9eb..d1146a7ce 100644
--- a/tests/amdgpu/amd_security.c
+++ b/tests/amdgpu/amd_security.c
@@ -351,17 +351,22 @@ igt_main
igt_skip_on(!is_security_tests_enable(device, &gpu_info, major, minor));
}
- igt_describe("amdgpu_security_alloc_buf_test");
+ igt_describe("amdgpu security alloc buf test");
igt_subtest("amdgpu-security-alloc-buf-test")
amdgpu_security_alloc_buf_test(device);
- igt_describe("amdgpu_command_submission_write_linear_helper");
- igt_subtest("write-linear-helper-secure")
+ igt_describe("amdgpu sdma command submission write linear helper");
+ igt_subtest("sdma-write-linear-helper-secure")
amdgpu_command_submission_write_linear_helper(device,
get_ip_block(device, AMDGPU_HW_IP_DMA), is_secure);
+ igt_describe("amdgpu gfx command submission write linear helper");
+ igt_subtest("gfx-write-linear-helper-secure")
+ amdgpu_command_submission_write_linear_helper(device,
+ get_ip_block(device, AMDGPU_HW_IP_GFX), is_secure);
+
/* dynamic test based on sdma_info.available rings */
- igt_describe("amdgpu_secure_bounce");
+ igt_describe("amdgpu secure bounce");
igt_subtest("amdgpu-secure-bounce")
amdgpu_secure_bounce(device, fd, &sdma_info, get_ip_block(device,
AMDGPU_HW_IP_DMA), is_secure);
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [igt-dev] ✓ CI.xeBAT: success for tests/amd_security: add secure write test for gfx (rev4)
2023-10-31 2:40 [igt-dev] [PATCH v3 i-g-t] tests/amd_security: add secure write test for gfx Jesse Zhang
@ 2023-10-31 3:29 ` Patchwork
2023-10-31 3:35 ` [igt-dev] ✗ Fi.CI.BAT: failure " Patchwork
1 sibling, 0 replies; 3+ messages in thread
From: Patchwork @ 2023-10-31 3:29 UTC (permalink / raw)
To: Jesse Zhang; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 4920 bytes --]
== Series Details ==
Series: tests/amd_security: add secure write test for gfx (rev4)
URL : https://patchwork.freedesktop.org/series/125534/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7566_BAT -> XEIGTPW_10091_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in XEIGTPW_10091_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-dg2-oem2: [PASS][1] -> [FAIL][2] ([Intel XE#480]) +1 other test fail
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7566/bat-dg2-oem2/igt@kms_flip@basic-flip-vs-wf_vblank.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10091/bat-dg2-oem2/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-dg2-oem2: [PASS][3] -> [INCOMPLETE][4] ([Intel XE#282] / [Intel XE#749])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7566/bat-dg2-oem2/igt@kms_pipe_crc_basic@hang-read-crc.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10091/bat-dg2-oem2/igt@kms_pipe_crc_basic@hang-read-crc.html
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-3:
- bat-dg2-oem2: [PASS][5] -> [INCOMPLETE][6] ([Intel XE#282] / [Intel XE#545])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7566/bat-dg2-oem2/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-3.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10091/bat-dg2-oem2/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-3.html
#### Possible fixes ####
* {igt@xe_evict_ccs@evict-ccs-overcommit-parallel-nofree-samefd}:
- bat-dg2-oem2: [FAIL][7] -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7566/bat-dg2-oem2/igt@xe_evict_ccs@evict-ccs-overcommit-parallel-nofree-samefd.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10091/bat-dg2-oem2/igt@xe_evict_ccs@evict-ccs-overcommit-parallel-nofree-samefd.html
#### Warnings ####
* igt@kms_frontbuffer_tracking@basic:
- bat-adlp-7: [DMESG-FAIL][9] ([Intel XE#282] / [i915#2017]) -> [FAIL][10] ([Intel XE#616] / [Intel XE#750])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7566/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10091/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12:
- bat-dg2-oem2: [FAIL][11] ([Intel XE#400] / [Intel XE#616]) -> [TIMEOUT][12] ([Intel XE#430] / [Intel XE#530])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7566/bat-dg2-oem2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10091/bat-dg2-oem2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-dp-3:
- bat-dg2-oem2: [FAIL][13] ([Intel XE#400] / [Intel XE#616]) -> [TIMEOUT][14] ([Intel XE#530])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7566/bat-dg2-oem2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-dp-3.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10091/bat-dg2-oem2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-dp-3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#282]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/282
[Intel XE#400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/400
[Intel XE#430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/430
[Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480
[Intel XE#524]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/524
[Intel XE#530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/530
[Intel XE#545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/545
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#749]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/749
[Intel XE#750]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/750
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
Build changes
-------------
* IGT: IGT_7566 -> IGTPW_10091
* Linux: xe-456-d7eb9a5c3acda8d87699bc82add7e8d88f5f4700 -> xe-457-1e652bcf7cc139244f4f8c0cd1fc184029240050
IGTPW_10091: 10091
IGT_7566: 7566
xe-456-d7eb9a5c3acda8d87699bc82add7e8d88f5f4700: d7eb9a5c3acda8d87699bc82add7e8d88f5f4700
xe-457-1e652bcf7cc139244f4f8c0cd1fc184029240050: 1e652bcf7cc139244f4f8c0cd1fc184029240050
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10091/index.html
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^ permalink raw reply [flat|nested] 3+ messages in thread
* [igt-dev] ✗ Fi.CI.BAT: failure for tests/amd_security: add secure write test for gfx (rev4)
2023-10-31 2:40 [igt-dev] [PATCH v3 i-g-t] tests/amd_security: add secure write test for gfx Jesse Zhang
2023-10-31 3:29 ` [igt-dev] ✓ CI.xeBAT: success for tests/amd_security: add secure write test for gfx (rev4) Patchwork
@ 2023-10-31 3:35 ` Patchwork
1 sibling, 0 replies; 3+ messages in thread
From: Patchwork @ 2023-10-31 3:35 UTC (permalink / raw)
To: Jesse Zhang; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 13099 bytes --]
== Series Details ==
Series: tests/amd_security: add secure write test for gfx (rev4)
URL : https://patchwork.freedesktop.org/series/125534/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13814 -> IGTPW_10091
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_10091 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_10091, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/index.html
Participating hosts (35 -> 36)
------------------------------
Additional (4): bat-kbl-2 bat-dg2-9 bat-mtlp-8 bat-jsl-3
Missing (3): bat-atsm-1 fi-snb-2520m fi-pnv-d510
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_10091:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@reset:
- fi-hsw-4770: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/fi-hsw-4770/igt@i915_selftest@live@reset.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/fi-hsw-4770/igt@i915_selftest@live@reset.html
Known issues
------------
Here are the changes found in IGTPW_10091 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#9318])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
- bat-jsl-3: NOTRUN -> [SKIP][4] ([i915#9318])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-jsl-3/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1849])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-kbl-2/igt@fbdev@info.html
* igt@gem_exec_suspend@basic-s0@lmem0:
- bat-dg2-9: NOTRUN -> [INCOMPLETE][6] ([i915#9275])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@gem_exec_suspend@basic-s0@lmem0.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-3: NOTRUN -> [SKIP][7] ([i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-jsl-3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-jsl-3: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-jsl-3/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][9] ([fdo#109271]) +39 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-dg2-9: NOTRUN -> [SKIP][11] ([i915#4083])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@gem_mmap@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4083])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-9: NOTRUN -> [SKIP][13] ([i915#4077]) +2 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@gem_mmap_gtt@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4077]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@gem_mmap_gtt@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-9: NOTRUN -> [SKIP][15] ([i915#4079]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@gem_render_tiled_blits@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#4079]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-9: NOTRUN -> [SKIP][17] ([i915#6621])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@i915_pm_rps@basic-api.html
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#6621])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#6645])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][20] ([i915#5190])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][21] ([i915#5190])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][22] ([i915#4215] / [i915#5190])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][23] ([i915#4212]) +8 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9: NOTRUN -> [SKIP][24] ([i915#4212]) +6 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9: NOTRUN -> [SKIP][25] ([i915#4212] / [i915#5608])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3: NOTRUN -> [SKIP][26] ([i915#4103]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-jsl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-dg2-9: NOTRUN -> [SKIP][27] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][28] ([i915#4213]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][29] ([i915#3555] / [i915#3840] / [i915#9159])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-3: NOTRUN -> [SKIP][30] ([fdo#109285])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-jsl-3/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg2-9: NOTRUN -> [SKIP][31] ([fdo#109285])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-8: NOTRUN -> [SKIP][32] ([fdo#109285])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9: NOTRUN -> [SKIP][33] ([i915#5274])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-mtlp-8: NOTRUN -> [SKIP][34] ([i915#5274])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][35] -> [FAIL][36] ([IGT#3])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg2-9: NOTRUN -> [SKIP][37] ([i915#1072]) +3 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-3: NOTRUN -> [SKIP][38] ([i915#3555]) +1 other test skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-jsl-3/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-9: NOTRUN -> [SKIP][39] ([i915#3555] / [i915#4098])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html
- bat-mtlp-8: NOTRUN -> [SKIP][40] ([i915#3555] / [i915#8809])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-9: NOTRUN -> [SKIP][41] ([i915#3708])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-9: NOTRUN -> [SKIP][42] ([i915#3708] / [i915#4077]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html
- bat-mtlp-8: NOTRUN -> [SKIP][43] ([i915#3708] / [i915#4077]) +1 other test skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][44] ([i915#3708]) +2 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-write:
- bat-dg2-9: NOTRUN -> [SKIP][45] ([i915#3291] / [i915#3708]) +2 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/bat-dg2-9/igt@prime_vgem@basic-write.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
[i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7566 -> IGTPW_10091
CI-20190529: 20190529
CI_DRM_13814: b560681c6bf623db41064ac486dd148d6c103e53 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_10091: 10091
IGT_7566: 7566
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10091/index.html
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^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-10-31 3:35 UTC | newest]
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2023-10-31 2:40 [igt-dev] [PATCH v3 i-g-t] tests/amd_security: add secure write test for gfx Jesse Zhang
2023-10-31 3:29 ` [igt-dev] ✓ CI.xeBAT: success for tests/amd_security: add secure write test for gfx (rev4) Patchwork
2023-10-31 3:35 ` [igt-dev] ✗ Fi.CI.BAT: failure " Patchwork
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