[igt-dev] [PATCH i-g-t] tests/intel/xe_exec_store: Add cachelines and page-sized subtests.

[igt-dev] [PATCH i-g-t] tests/intel/xe_exec_store: Add cachelines and page-sized subtests.

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Intension of these subtests is to verify that each capable engine can store a
dword to different cachelines/pages of a buffer object.

Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 tests/intel/xe_exec_store.c | 106 ++++++++++++++++++++++++++++++++++++
 1 file changed, 106 insertions(+)

diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
index 14f7c9bec..0929a7717 100644
--- a/tests/intel/xe_exec_store.c
+++ b/tests/intel/xe_exec_store.c
@@ -105,6 +105,100 @@ static void store(int fd)
 	xe_vm_destroy(fd, vm);
 }
 
+#define PAGES 1
+#define NCACHELINES (4096/64)
+/**
+ * SUBTEST: %s
+ * Description: Verify that each capable engine can store a dword to different
+ * 		%arg[1] of a buffer object.
+ * Test category: functionality test
+ *
+ * arg[1]:
+ *
+ * @cachelines: cachelines
+ * @page-sized: page-sized
+ */
+static void store_cachelines(int fd, int gt, int class, unsigned int flags)
+{
+	uint32_t vm;
+	uint64_t ahnd;
+	struct drm_xe_sync sync[2] = {
+		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = flags & PAGES ? NCACHELINES + 1 : 2,
+		.num_syncs = 2,
+		.syncs = to_user_pointer(&sync),
+	};
+	uint32_t value[NCACHELINES], delta;
+	uint32_t bo[exec.num_batch_buffer];
+	uint64_t dst_offset[exec.num_batch_buffer];
+	struct drm_xe_engine_class_instance eci[exec.num_batch_buffer];
+	struct drm_xe_engine_class_instance *hwe;
+	uint32_t syncobjs[exec.num_batch_buffer], exec_queues[exec.num_batch_buffer];
+	struct data *data;
+	int i, num_placements = 0;
+
+	sync[0].handle = syncobj_create(fd, 0);
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
+
+	xe_for_each_hw_engine(fd, hwe) {
+		if (hwe->engine_class != class || hwe->gt_id != gt)
+			continue;
+		eci[num_placements++] = *hwe;
+	}
+
+	for (i = 0; i < exec.num_batch_buffer ; i++) {
+		struct drm_xe_exec_queue_create create = {
+			.vm_id = vm,
+			.width = 1,
+			.num_placements = num_placements,
+			.instances = to_user_pointer(eci),
+		};
+
+		igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE,
+					&create), 0);
+		exec_queues[i] = create.exec_queue_id;
+		syncobjs[i] = syncobj_create(fd, 0);
+		bo[i] = xe_bo_create_flags(fd, vm, 4096,
+					   visible_vram_if_possible(fd, hwe->gt_id));
+		dst_offset[i] = intel_allocator_alloc_with_strategy(ahnd, bo[i],
+								    4096, 0,
+								    ALLOC_STRATEGY_LOW_TO_HIGH);
+	}
+	data = xe_bo_map(fd, bo[i-1], 4096);
+
+	for (unsigned n = 0; n < NCACHELINES; n++) {
+		delta = 4 * (n * 16 + n % 16);
+		value[n] = n | ~n << 16;
+		store_dword_batch(data, dst_offset[n] + delta, value[n]);
+		xe_vm_bind_async(fd, vm, hwe->gt_id, bo[n], 0, dst_offset[n] + delta, 4096, sync, 1);
+		exec.address = dst_offset[n] + delta;
+		exec.exec_queue_id = exec_queues[n];
+		sync[0].flags &= DRM_XE_SYNC_SIGNAL;
+		sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+		sync[1].handle = syncobjs[i];
+		xe_exec(fd, &exec);
+
+		igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0, NULL));
+	}
+
+	for (unsigned n = 0; n < NCACHELINES; n++) {
+		igt_assert_eq(data[n].data, value[n]);
+	}
+
+	for (unsigned n = 0; n < exec.num_batch_buffer; n++) {
+		syncobj_destroy(fd, syncobjs[n]);
+		xe_exec_queue_destroy(fd, exec_queues[n]);
+		gem_close(fd, bo[n]);
+	}
+	munmap(data, 4096);
+	put_ahnd(ahnd);
+	xe_vm_destroy(fd, vm);
+}
+
 /**
  * SUBTEST: basic-all
  * Description: Test to verify store dword on all available engines.
@@ -211,6 +305,18 @@ igt_main
 				store_all(fd, gt, class);
 	}
 
+	igt_subtest("cachelines") {
+		xe_for_each_gt(fd, gt)
+			xe_for_each_hw_engine_class(class)
+				store_cachelines(fd, gt, class, 0);
+	}
+
+	igt_subtest("page-sized") {
+		xe_for_each_gt(fd, gt)
+			xe_for_each_hw_engine_class(class)
+				store_cachelines(fd, gt, class, PAGES);
+	}
+
 	igt_fixture {
 		xe_device_put(fd);
 		close(fd);
-- 
2.39.1

Re: [igt-dev] [PATCH i-g-t] tests/intel/xe_exec_store: Add cachelines and page-sized subtests.

[Kamil Konieczny]

Hi Sai,

remove dot from end of subject line:

[PATCH i-g-t] tests/intel/xe_exec_store: Add cachelines and page-sized subtests.
-------------------------------------------------------------------------------^
s/subtests./subtests/

Few more nits follow below.

On 2023-09-15 at 10:48:32 +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Intension of these subtests is to verify that each capable engine can store a
> dword to different cachelines/pages of a buffer object.
> 
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  tests/intel/xe_exec_store.c | 106 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 106 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
> index 14f7c9bec..0929a7717 100644
> --- a/tests/intel/xe_exec_store.c
> +++ b/tests/intel/xe_exec_store.c
> @@ -105,6 +105,100 @@ static void store(int fd)
>  	xe_vm_destroy(fd, vm);
>  }
>  
> +#define PAGES 1
> +#define NCACHELINES (4096/64)
> +/**
> + * SUBTEST: %s
> + * Description: Verify that each capable engine can store a dword to different
> + * 		%arg[1] of a buffer object.
> + * Test category: functionality test
> + *
> + * arg[1]:
> + *
> + * @cachelines: cachelines
> + * @page-sized: page-sized
> + */
> +static void store_cachelines(int fd, int gt, int class, unsigned int flags)
> +{
> +	uint32_t vm;
> +	uint64_t ahnd;
> +	struct drm_xe_sync sync[2] = {
> +		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
> +		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = flags & PAGES ? NCACHELINES + 1 : 2,
> +		.num_syncs = 2,
> +		.syncs = to_user_pointer(&sync),
> +	};
> +	uint32_t value[NCACHELINES], delta;
> +	uint32_t bo[exec.num_batch_buffer];
> +	uint64_t dst_offset[exec.num_batch_buffer];
> +	struct drm_xe_engine_class_instance eci[exec.num_batch_buffer];
> +	struct drm_xe_engine_class_instance *hwe;
> +	uint32_t syncobjs[exec.num_batch_buffer], exec_queues[exec.num_batch_buffer];
> +	struct data *data;
> +	int i, num_placements = 0;
> +
> +	sync[0].handle = syncobj_create(fd, 0);
> +	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
> +
> +	xe_for_each_hw_engine(fd, hwe) {
> +		if (hwe->engine_class != class || hwe->gt_id != gt)
> +			continue;
> +		eci[num_placements++] = *hwe;
> +	}
> +
> +	for (i = 0; i < exec.num_batch_buffer ; i++) {
> +		struct drm_xe_exec_queue_create create = {
> +			.vm_id = vm,
> +			.width = 1,
> +			.num_placements = num_placements,
> +			.instances = to_user_pointer(eci),
> +		};
> +
> +		igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE,
> +					&create), 0);
> +		exec_queues[i] = create.exec_queue_id;
> +		syncobjs[i] = syncobj_create(fd, 0);
> +		bo[i] = xe_bo_create_flags(fd, vm, 4096,
> +					   visible_vram_if_possible(fd, hwe->gt_id));
> +		dst_offset[i] = intel_allocator_alloc_with_strategy(ahnd, bo[i],
> +								    4096, 0,
> +								    ALLOC_STRATEGY_LOW_TO_HIGH);
> +	}
> +	data = xe_bo_map(fd, bo[i-1], 4096);
> +
> +	for (unsigned n = 0; n < NCACHELINES; n++) {
> +		delta = 4 * (n * 16 + n % 16);
> +		value[n] = n | ~n << 16;
> +		store_dword_batch(data, dst_offset[n] + delta, value[n]);
> +		xe_vm_bind_async(fd, vm, hwe->gt_id, bo[n], 0, dst_offset[n] + delta, 4096, sync, 1);
> +		exec.address = dst_offset[n] + delta;
> +		exec.exec_queue_id = exec_queues[n];
> +		sync[0].flags &= DRM_XE_SYNC_SIGNAL;
> +		sync[1].flags |= DRM_XE_SYNC_SIGNAL;
> +		sync[1].handle = syncobjs[i];
> +		xe_exec(fd, &exec);
> +
> +		igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0, NULL));
> +	}
> +
> +	for (unsigned n = 0; n < NCACHELINES; n++) {
> +		igt_assert_eq(data[n].data, value[n]);
> +	}
> +
> +	for (unsigned n = 0; n < exec.num_batch_buffer; n++) {
> +		syncobj_destroy(fd, syncobjs[n]);
> +		xe_exec_queue_destroy(fd, exec_queues[n]);
> +		gem_close(fd, bo[n]);
> +	}
> +	munmap(data, 4096);
> +	put_ahnd(ahnd);
> +	xe_vm_destroy(fd, vm);
> +}
> +
>  /**
>   * SUBTEST: basic-all
>   * Description: Test to verify store dword on all available engines.
> @@ -211,6 +305,18 @@ igt_main
>  				store_all(fd, gt, class);
>  	}
>  
> +	igt_subtest("cachelines") {
---------------- ^
imho better:
	igt_subtest("cachelines-basic") {

Or some other suffix name? See below.

> +		xe_for_each_gt(fd, gt)
> +			xe_for_each_hw_engine_class(class)
> +				store_cachelines(fd, gt, class, 0);
> +	}
> +
> +	igt_subtest("page-sized") {
---------------- ^
imho better to use prefix here:

	igt_subtest("cachelines-page-size") {

Regards,
Kamil

> +		xe_for_each_gt(fd, gt)
> +			xe_for_each_hw_engine_class(class)
> +				store_cachelines(fd, gt, class, PAGES);
> +	}
> +
>  	igt_fixture {
>  		xe_device_put(fd);
>  		close(fd);
> -- 
> 2.39.1
> 

Re: [igt-dev] [PATCH i-g-t] tests/intel/xe_exec_store: Add cachelines and page-sized subtests.

[Zbigniew Kempczyński]

On Fri, Sep 15, 2023 at 10:48:32AM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Intension of these subtests is to verify that each capable engine can store a
> dword to different cachelines/pages of a buffer object.
> 
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  tests/intel/xe_exec_store.c | 106 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 106 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
> index 14f7c9bec..0929a7717 100644
> --- a/tests/intel/xe_exec_store.c
> +++ b/tests/intel/xe_exec_store.c
> @@ -105,6 +105,100 @@ static void store(int fd)
>  	xe_vm_destroy(fd, vm);
>  }
>  
> +#define PAGES 1
> +#define NCACHELINES (4096/64)
> +/**
> + * SUBTEST: %s
> + * Description: Verify that each capable engine can store a dword to different
> + * 		%arg[1] of a buffer object.
> + * Test category: functionality test
> + *
> + * arg[1]:
> + *
> + * @cachelines: cachelines
> + * @page-sized: page-sized
> + */
> +static void store_cachelines(int fd, int gt, int class, unsigned int flags)
> +{
> +	uint32_t vm;
> +	uint64_t ahnd;
> +	struct drm_xe_sync sync[2] = {
> +		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
> +		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = flags & PAGES ? NCACHELINES + 1 : 2,
> +		.num_syncs = 2,
> +		.syncs = to_user_pointer(&sync),
> +	};
> +	uint32_t value[NCACHELINES], delta;
> +	uint32_t bo[exec.num_batch_buffer];
> +	uint64_t dst_offset[exec.num_batch_buffer];
> +	struct drm_xe_engine_class_instance eci[exec.num_batch_buffer];
> +	struct drm_xe_engine_class_instance *hwe;
> +	uint32_t syncobjs[exec.num_batch_buffer], exec_queues[exec.num_batch_buffer];
> +	struct data *data;
> +	int i, num_placements = 0;
> +
> +	sync[0].handle = syncobj_create(fd, 0);
> +	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
> +
> +	xe_for_each_hw_engine(fd, hwe) {
> +		if (hwe->engine_class != class || hwe->gt_id != gt)
> +			continue;
> +		eci[num_placements++] = *hwe;
> +	}
> +
> +	for (i = 0; i < exec.num_batch_buffer ; i++) {
> +		struct drm_xe_exec_queue_create create = {
> +			.vm_id = vm,
> +			.width = 1,
> +			.num_placements = num_placements,
> +			.instances = to_user_pointer(eci),
> +		};
> +
> +		igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE,
> +					&create), 0);
> +		exec_queues[i] = create.exec_queue_id;
> +		syncobjs[i] = syncobj_create(fd, 0);
> +		bo[i] = xe_bo_create_flags(fd, vm, 4096,
> +					   visible_vram_if_possible(fd, hwe->gt_id));
> +		dst_offset[i] = intel_allocator_alloc_with_strategy(ahnd, bo[i],
> +								    4096, 0,
> +								    ALLOC_STRATEGY_LOW_TO_HIGH);
> +	}
> +	data = xe_bo_map(fd, bo[i-1], 4096);
> +
> +	for (unsigned n = 0; n < NCACHELINES; n++) {
> +		delta = 4 * (n * 16 + n % 16);
> +		value[n] = n | ~n << 16;
> +		store_dword_batch(data, dst_offset[n] + delta, value[n]);
> +		xe_vm_bind_async(fd, vm, hwe->gt_id, bo[n], 0, dst_offset[n] + delta, 4096, sync, 1);
> +		exec.address = dst_offset[n] + delta;
> +		exec.exec_queue_id = exec_queues[n];
> +		sync[0].flags &= DRM_XE_SYNC_SIGNAL;
> +		sync[1].flags |= DRM_XE_SYNC_SIGNAL;
> +		sync[1].handle = syncobjs[i];
> +		xe_exec(fd, &exec);
> +
> +		igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0, NULL));
> +	}

Assuming you're porting gem_exec_store@store_cachelines():

1. Original test prepares single batch with many mi-store-dword writing
   to n-buffers or single buffer, depending on flags (PAGES). Engine
   is passed as an argument to store_cachelines(..., e, ...).
2. Your test synchronously iterates over all engine classes
   (syncobj_wait()) passed as an argument (class).
3. Bind all objects before starting to execute - original test calls
   execbuf() once, not many times.

I would use original pattern - use xe_for_each_hw_engine() creating
separate dynamic subtests for each exec queue.

--
Zbigniew

> +
> +	for (unsigned n = 0; n < NCACHELINES; n++) {
> +		igt_assert_eq(data[n].data, value[n]);
> +	}
> +
> +	for (unsigned n = 0; n < exec.num_batch_buffer; n++) {
> +		syncobj_destroy(fd, syncobjs[n]);
> +		xe_exec_queue_destroy(fd, exec_queues[n]);
> +		gem_close(fd, bo[n]);
> +	}
> +	munmap(data, 4096);
> +	put_ahnd(ahnd);
> +	xe_vm_destroy(fd, vm);
> +}
> +
>  /**
>   * SUBTEST: basic-all
>   * Description: Test to verify store dword on all available engines.
> @@ -211,6 +305,18 @@ igt_main
>  				store_all(fd, gt, class);
>  	}
>  
> +	igt_subtest("cachelines") {
> +		xe_for_each_gt(fd, gt)
> +			xe_for_each_hw_engine_class(class)
> +				store_cachelines(fd, gt, class, 0);
> +	}
> +
> +	igt_subtest("page-sized") {
> +		xe_for_each_gt(fd, gt)
> +			xe_for_each_hw_engine_class(class)
> +				store_cachelines(fd, gt, class, PAGES);
> +	}
> +
>  	igt_fixture {
>  		xe_device_put(fd);
>  		close(fd);
> -- 
> 2.39.1
> 

[igt-dev] [PATCH i-g-t] tests/intel/xe_exec_store: Add cachelines and page-sized subtests

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Intension of these subtests is to verify that each capable engine can store a
dword to different cachelines/pages of a buffer object.

Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 tests/intel/xe_exec_store.c | 107 ++++++++++++++++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
index 90684b8cb..d393da224 100644
--- a/tests/intel/xe_exec_store.c
+++ b/tests/intel/xe_exec_store.c
@@ -105,6 +105,104 @@ static void store(int fd)
 	xe_vm_destroy(fd, vm);
 }
 
+#define PAGES 1
+#define NCACHELINES (4096/64)
+/**
+ * SUBTEST: %s
+ * Description: Verify that each capable engine can store a dword to different
+ * 		%arg[1] of a buffer object.
+ * Test category: functionality test
+ *
+ * arg[1]:
+ *
+ * @cachelines: cachelines
+ * @page-sized: page-sized
+ */
+static void store_cachelines(int fd, struct drm_xe_engine_class_instance *eci, unsigned int flags)
+{
+	struct drm_xe_sync sync[2] = {
+		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }
+	};
+
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 2,
+		.syncs = to_user_pointer(&sync),
+	};
+
+	int count = flags & PAGES ? NCACHELINES + 1 : 2;
+	int i, object_index, b = 0;
+	uint64_t dst_offset[count];
+	uint32_t exec_queues, vm, syncobjs;
+	uint32_t bo[count], *bo_map[count];
+	uint32_t value[NCACHELINES], *ptr[NCACHELINES], delta;
+	uint64_t offset[NCACHELINES];
+	uint64_t ahnd;
+	uint32_t *batch_map;
+	size_t bo_size = 4096;
+
+	bo_size = ALIGN(bo_size , xe_get_default_alignment(fd));
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
+	exec_queues = xe_exec_queue_create(fd, vm, eci, 0);
+	syncobjs = syncobj_create(fd, 0);
+	sync[0].handle = syncobj_create(fd, 0);
+
+	for (i = 0; i < count; i++) {
+		bo[i] = xe_bo_create_flags(fd, vm, bo_size,
+					       visible_vram_if_possible(fd, eci->gt_id));
+		bo_map[i] = xe_bo_map(fd, bo[i], bo_size);
+		dst_offset[i] = intel_allocator_alloc_with_strategy(ahnd, bo[i],
+								    bo_size, 0,
+								    ALLOC_STRATEGY_LOW_TO_HIGH);
+		xe_vm_bind_async(fd, vm, eci->gt_id, bo[i], 0, dst_offset[i], bo_size, sync, 1);
+	}
+
+	batch_map = xe_bo_map(fd, bo[i-1], bo_size);
+	exec.address = dst_offset[i-1];
+
+	for (unsigned n = 0; n < NCACHELINES; n++) {
+		delta = 4 * (n * 16 + n % 16);
+		value[n] = n | ~n << 16;
+		offset[n] = dst_offset[n % (count - 1)] + delta;
+
+		batch_map[b++] = MI_STORE_DWORD_IMM_GEN4;
+		batch_map[b++] = offset[n];
+		batch_map[b++] = offset[n] >> 32;
+		batch_map[b++] = value[n];
+	}
+	batch_map[b++] = MI_BATCH_BUFFER_END;
+	sync[0].flags &= DRM_XE_SYNC_SIGNAL;
+	sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+	sync[1].handle = syncobjs;
+	exec.exec_queue_id = exec_queues;
+	xe_exec(fd, &exec);
+	igt_assert(syncobj_wait(fd, &syncobjs, 1, INT64_MAX, 0, NULL));
+
+	for (unsigned n = 0; n < NCACHELINES; n++) {
+		delta = 4 * (n * 16 + n % 16);
+		value[n] = n | ~n << 16;
+		object_index = n % (count - 1);
+		ptr[n]  = bo_map[object_index] + delta / 4;
+
+		igt_assert(*ptr[n] == value[n]);
+	}
+
+	for ( i = 0; i < count; i++) {
+		munmap(bo_map[i], bo_size);
+		xe_vm_unbind_async(fd, vm, 0, 0, dst_offset[i], bo_size, sync, 1);
+		gem_close(fd, bo[i]);
+	}
+
+	munmap(batch_map, bo_size);
+	put_ahnd(ahnd);
+	syncobj_destroy(fd, sync[0].handle);
+	syncobj_destroy(fd, syncobjs);
+	xe_exec_queue_destroy(fd, exec_queues);
+	xe_vm_destroy(fd, vm);
+}
+
 /**
  * SUBTEST: basic-all
  * Description: Test to verify store dword on all available engines.
@@ -195,6 +293,7 @@ static void store_all(int fd, int gt, int class)
 
 igt_main
 {
+	struct drm_xe_engine_class_instance *hwe;
 	int fd, class, gt;
 
 	igt_fixture {
@@ -211,6 +310,14 @@ igt_main
 				store_all(fd, gt, class);
 	}
 
+	igt_subtest("cachelines")
+		xe_for_each_hw_engine(fd, hwe)
+			store_cachelines(fd, hwe, 0);
+
+	igt_subtest("page-sized")
+		xe_for_each_hw_engine(fd, hwe)
+			store_cachelines(fd, hwe, PAGES);
+
 	igt_fixture {
 		xe_device_put(fd);
 		close(fd);
-- 
2.39.1

[igt-dev] ✓ CI.xeBAT: success for tests/intel/xe_exec_store: Add cachelines and page-sized subtests

[Patchwork]

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== Series Details ==

Series: tests/intel/xe_exec_store: Add cachelines and page-sized subtests
URL   : https://patchwork.freedesktop.org/series/125889/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7568_BAT -> XEIGTPW_10100_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_10100_BAT that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@kms_frontbuffer_tracking@basic:
    - bat-adlp-7:         [DMESG-FAIL][1] ([Intel XE#282] / [i915#2017]) -> [FAIL][2] ([Intel XE#616] / [Intel XE#750])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7568/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10100/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#282]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/282
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#750]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/750
  [Intel XE#855]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/855
  [i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017


Build changes
-------------

  * IGT: IGT_7568 -> IGTPW_10100
  * Linux: xe-459-76bba03c4f90371e7b2da536b966a49c68d589b0 -> xe-465-34a82567688cfe0c7e63e9cda15b6da4b449abfe

  IGTPW_10100: 10100
  IGT_7568: 9e3c3791e7e0297f277211b19a3388a1ee87f3d0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-459-76bba03c4f90371e7b2da536b966a49c68d589b0: 76bba03c4f90371e7b2da536b966a49c68d589b0
  xe-465-34a82567688cfe0c7e63e9cda15b6da4b449abfe: 34a82567688cfe0c7e63e9cda15b6da4b449abfe

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10100/index.html

[-- Attachment #2: Type: text/html, Size: 2595 bytes --]

[igt-dev] ✗ Fi.CI.BAT: failure for tests/intel/xe_exec_store: Add cachelines and page-sized subtests

[Patchwork]

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== Series Details ==

Series: tests/intel/xe_exec_store: Add cachelines and page-sized subtests
URL   : https://patchwork.freedesktop.org/series/125889/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13828 -> IGTPW_10100
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_10100 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_10100, please notify your bug team (lgci.bug.filing@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/index.html

Participating hosts (35 -> 36)
------------------------------

  Additional (3): fi-kbl-soraka bat-kbl-2 bat-dg1-5 
  Missing    (2): bat-mtlp-8 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_10100:

### IGT changes ###

#### Possible regressions ####

  * igt@dmabuf@all-tests@dma_fence_chain:
    - fi-hsw-4770:        NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/fi-hsw-4770/igt@dmabuf@all-tests@dma_fence_chain.html

  
Known issues
------------

  Here are the changes found in IGTPW_10100 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@info:
    - bat-kbl-2:          NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1849])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-kbl-2/igt@fbdev@info.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-kbl-2:          NOTRUN -> [SKIP][5] ([fdo#109271]) +39 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_mmap@basic:
    - bat-dg1-5:          NOTRUN -> [SKIP][6] ([i915#4083])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@gem_mmap@basic.html

  * igt@gem_tiled_blits@basic:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][7] ([fdo#109271]) +18 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/fi-bsw-n3050/igt@gem_tiled_blits@basic.html
    - bat-dg1-5:          NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-dg1-5:          NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg1-5:          NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][11] ([i915#1886])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
    - bat-dg1-5:          NOTRUN -> [SKIP][12] ([i915#4212]) +7 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg1-5:          NOTRUN -> [SKIP][13] ([i915#4215])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][14] ([fdo#109271]) +9 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-dg1-5:          NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-dg1-5:          NOTRUN -> [SKIP][16] ([i915#3555] / [i915#3840])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-dg1-5:          NOTRUN -> [SKIP][17] ([fdo#109285])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-kbl-guc:         [PASS][18] -> [FAIL][19] ([IGT#3])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13828/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
    - fi-bsw-n3050:       NOTRUN -> [FAIL][20] ([IGT#3])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/fi-bsw-n3050/igt@kms_hdmi_inject@inject-audio.html
    - bat-dg1-5:          NOTRUN -> [SKIP][21] ([i915#433])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_psr@primary_page_flip:
    - bat-dg1-5:          NOTRUN -> [SKIP][22] ([i915#1072] / [i915#4078]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@kms_psr@primary_page_flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-dg1-5:          NOTRUN -> [SKIP][23] ([i915#3555])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
    - bat-dg1-5:          NOTRUN -> [SKIP][24] ([i915#3708]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-gtt:
    - bat-dg1-5:          NOTRUN -> [SKIP][25] ([i915#3708] / [i915#4077]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-dg1-5/igt@prime_vgem@basic-gtt.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@perf:
    - fi-hsw-4770:        [INCOMPLETE][26] -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13828/fi-hsw-4770/igt@i915_selftest@live@perf.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/fi-hsw-4770/igt@i915_selftest@live@perf.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
    - bat-rplp-1:         [ABORT][28] ([i915#8668]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13828/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7568 -> IGTPW_10100

  CI-20190529: 20190529
  CI_DRM_13828: 03d8fa0115d6531bf0ea276f13f9b685296bc38b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_10100: 10100
  IGT_7568: 9e3c3791e7e0297f277211b19a3388a1ee87f3d0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@xe_exec_store@cachelines
+igt@xe_exec_store@page-sized
-igt@kms_pipe_crc_basic@darkscreen-read-crc
-igt@kms_pipe_crc_basic@negative-darkscreen-read-crc

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10100/index.html

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[igt-dev] [PATCH i-g-t] tests/intel/xe_exec_store: Add cachelines and page-sized subtests

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Intension of these subtests is to verify that each capable engine
can store a dword to different cachelines/pages of a buffer object.

Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 tests/intel/xe_exec_store.c | 107 ++++++++++++++++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
index 90684b8cb..4ca76b43a 100644
--- a/tests/intel/xe_exec_store.c
+++ b/tests/intel/xe_exec_store.c
@@ -105,6 +105,104 @@ static void store(int fd)
 	xe_vm_destroy(fd, vm);
 }
 
+#define PAGES 1
+#define NCACHELINES (4096/64)
+/**
+ * SUBTEST: %s
+ * Description: Verify that each engine can store a dword to different %arg[1] of a object.
+ * Test category: functionality test
+ *
+ * arg[1]:
+ *
+ * @cachelines: cachelines
+ * @page-sized: page-sized
+ */
+static void store_cachelines(int fd, struct drm_xe_engine_class_instance *eci,
+			     unsigned int flags)
+{
+	struct drm_xe_sync sync[2] = {
+		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }
+	};
+
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 2,
+		.syncs = to_user_pointer(&sync),
+	};
+
+	int count = flags & PAGES ? NCACHELINES + 1 : 2;
+	int i, object_index, b = 0;
+	uint64_t dst_offset[count];
+	uint32_t exec_queues, vm, syncobjs;
+	uint32_t bo[count], *bo_map[count];
+	uint32_t value[NCACHELINES], *ptr[NCACHELINES], delta;
+	uint64_t offset[NCACHELINES];
+	uint64_t ahnd;
+	uint32_t *batch_map;
+	size_t bo_size = 4096;
+
+	bo_size = ALIGN(bo_size, xe_get_default_alignment(fd));
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
+	exec_queues = xe_exec_queue_create(fd, vm, eci, 0);
+	syncobjs = syncobj_create(fd, 0);
+	sync[0].handle = syncobj_create(fd, 0);
+
+	for (i = 0; i < count; i++) {
+		bo[i] = xe_bo_create_flags(fd, vm, bo_size,
+					       visible_vram_if_possible(fd, eci->gt_id));
+		bo_map[i] = xe_bo_map(fd, bo[i], bo_size);
+		dst_offset[i] = intel_allocator_alloc_with_strategy(ahnd, bo[i],
+								    bo_size, 0,
+								    ALLOC_STRATEGY_LOW_TO_HIGH);
+		xe_vm_bind_async(fd, vm, eci->gt_id, bo[i], 0, dst_offset[i], bo_size, sync, 1);
+	}
+
+	batch_map = xe_bo_map(fd, bo[i-1], bo_size);
+	exec.address = dst_offset[i-1];
+
+	for (unsigned int n = 0; n < NCACHELINES; n++) {
+		delta = 4 * (n * 16 + n % 16);
+		value[n] = n | ~n << 16;
+		offset[n] = dst_offset[n % (count - 1)] + delta;
+
+		batch_map[b++] = MI_STORE_DWORD_IMM_GEN4;
+		batch_map[b++] = offset[n];
+		batch_map[b++] = offset[n] >> 32;
+		batch_map[b++] = value[n];
+	}
+	batch_map[b++] = MI_BATCH_BUFFER_END;
+	sync[0].flags &= DRM_XE_SYNC_SIGNAL;
+	sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+	sync[1].handle = syncobjs;
+	exec.exec_queue_id = exec_queues;
+	xe_exec(fd, &exec);
+	igt_assert(syncobj_wait(fd, &syncobjs, 1, INT64_MAX, 0, NULL));
+
+	for (unsigned int n = 0; n < NCACHELINES; n++) {
+		delta = 4 * (n * 16 + n % 16);
+		value[n] = n | ~n << 16;
+		object_index = n % (count - 1);
+		ptr[n]  = bo_map[object_index] + delta / 4;
+
+		igt_assert(*ptr[n] == value[n]);
+	}
+
+	for (i = 0; i < count; i++) {
+		munmap(bo_map[i], bo_size);
+		xe_vm_unbind_async(fd, vm, 0, 0, dst_offset[i], bo_size, sync, 1);
+		gem_close(fd, bo[i]);
+	}
+
+	munmap(batch_map, bo_size);
+	put_ahnd(ahnd);
+	syncobj_destroy(fd, sync[0].handle);
+	syncobj_destroy(fd, syncobjs);
+	xe_exec_queue_destroy(fd, exec_queues);
+	xe_vm_destroy(fd, vm);
+}
+
 /**
  * SUBTEST: basic-all
  * Description: Test to verify store dword on all available engines.
@@ -195,6 +293,7 @@ static void store_all(int fd, int gt, int class)
 
 igt_main
 {
+	struct drm_xe_engine_class_instance *hwe;
 	int fd, class, gt;
 
 	igt_fixture {
@@ -211,6 +310,14 @@ igt_main
 				store_all(fd, gt, class);
 	}
 
+	igt_subtest("cachelines")
+		xe_for_each_hw_engine(fd, hwe)
+			store_cachelines(fd, hwe, 0);
+
+	igt_subtest("page-sized")
+		xe_for_each_hw_engine(fd, hwe)
+			store_cachelines(fd, hwe, PAGES);
+
 	igt_fixture {
 		xe_device_put(fd);
 		close(fd);
-- 
2.39.1

Re: [igt-dev] [PATCH i-g-t] tests/intel/xe_exec_store: Add cachelines and page-sized subtests

[Kumar, Janga Rahul]

> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of
> sai.gowtham.ch@intel.com
> Sent: Thursday, November 2, 2023 5:36 PM
> To: igt-dev@lists.freedesktop.org; Ch, Sai Gowtham
> <sai.gowtham.ch@intel.com>
> Subject: [igt-dev] [PATCH i-g-t] tests/intel/xe_exec_store: Add cachelines and
> page-sized subtests
> 
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Intension of these subtests is to verify that each capable engine can store a
> dword to different cachelines/pages of a buffer object.
> 
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  tests/intel/xe_exec_store.c | 107 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 107 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c index
> 90684b8cb..4ca76b43a 100644
> --- a/tests/intel/xe_exec_store.c
> +++ b/tests/intel/xe_exec_store.c
> @@ -105,6 +105,104 @@ static void store(int fd)
>  	xe_vm_destroy(fd, vm);
>  }
> 
> +#define PAGES 1
> +#define NCACHELINES (4096/64)
> +/**
> + * SUBTEST: %s
> + * Description: Verify that each engine can store a dword to different
> %arg[1] of a object.
> + * Test category: functionality test
> + *
> + * arg[1]:
> + *
> + * @cachelines: cachelines
> + * @page-sized: page-sized
> + */
> +static void store_cachelines(int fd, struct drm_xe_engine_class_instance
> *eci,
> +			     unsigned int flags)
> +{
> +	struct drm_xe_sync sync[2] = {
> +		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
> +		{ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }
> +	};
> +
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.num_syncs = 2,
> +		.syncs = to_user_pointer(&sync),
> +	};
> +
> +	int count = flags & PAGES ? NCACHELINES + 1 : 2;
> +	int i, object_index, b = 0;
> +	uint64_t dst_offset[count];
> +	uint32_t exec_queues, vm, syncobjs;
> +	uint32_t bo[count], *bo_map[count];
> +	uint32_t value[NCACHELINES], *ptr[NCACHELINES], delta;
> +	uint64_t offset[NCACHELINES];
> +	uint64_t ahnd;
> +	uint32_t *batch_map;
> +	size_t bo_size = 4096;
> +
> +	bo_size = ALIGN(bo_size, xe_get_default_alignment(fd));
> +	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
> +	exec_queues = xe_exec_queue_create(fd, vm, eci, 0);
> +	syncobjs = syncobj_create(fd, 0);
> +	sync[0].handle = syncobj_create(fd, 0);
> +
> +	for (i = 0; i < count; i++) {
> +		bo[i] = xe_bo_create_flags(fd, vm, bo_size,
> +					       visible_vram_if_possible(fd, eci-
> >gt_id));
> +		bo_map[i] = xe_bo_map(fd, bo[i], bo_size);
> +		dst_offset[i] = intel_allocator_alloc_with_strategy(ahnd,
> bo[i],
> +								    bo_size, 0,
> +
> ALLOC_STRATEGY_LOW_TO_HIGH);
> +		xe_vm_bind_async(fd, vm, eci->gt_id, bo[i], 0, dst_offset[i],
> bo_size, sync, 1);
> +	}
> +
> +	batch_map = xe_bo_map(fd, bo[i-1], bo_size);
> +	exec.address = dst_offset[i-1];
> +
> +	for (unsigned int n = 0; n < NCACHELINES; n++) {
> +		delta = 4 * (n * 16 + n % 16);
> +		value[n] = n | ~n << 16;
> +		offset[n] = dst_offset[n % (count - 1)] + delta;
> +
> +		batch_map[b++] = MI_STORE_DWORD_IMM_GEN4;
> +		batch_map[b++] = offset[n];
> +		batch_map[b++] = offset[n] >> 32;
> +		batch_map[b++] = value[n];
> +	}
> +	batch_map[b++] = MI_BATCH_BUFFER_END;
> +	sync[0].flags &= DRM_XE_SYNC_SIGNAL;
> +	sync[1].flags |= DRM_XE_SYNC_SIGNAL;
> +	sync[1].handle = syncobjs;
> +	exec.exec_queue_id = exec_queues;
> +	xe_exec(fd, &exec);
> +	igt_assert(syncobj_wait(fd, &syncobjs, 1, INT64_MAX, 0, NULL));
> +
> +	for (unsigned int n = 0; n < NCACHELINES; n++) {
> +		delta = 4 * (n * 16 + n % 16);
> +		value[n] = n | ~n << 16;
> +		object_index = n % (count - 1);
> +		ptr[n]  = bo_map[object_index] + delta / 4;
> +
> +		igt_assert(*ptr[n] == value[n]);
> +	}
> +
> +	for (i = 0; i < count; i++) {
> +		munmap(bo_map[i], bo_size);
> +		xe_vm_unbind_async(fd, vm, 0, 0, dst_offset[i], bo_size, sync,
> 1);
> +		gem_close(fd, bo[i]);
> +	}
> +
> +	munmap(batch_map, bo_size);
> +	put_ahnd(ahnd);
> +	syncobj_destroy(fd, sync[0].handle);
> +	syncobj_destroy(fd, syncobjs);
> +	xe_exec_queue_destroy(fd, exec_queues);
> +	xe_vm_destroy(fd, vm);
> +}
> +
>  /**
>   * SUBTEST: basic-all
>   * Description: Test to verify store dword on all available engines.
> @@ -195,6 +293,7 @@ static void store_all(int fd, int gt, int class)
> 
>  igt_main
>  {
> +	struct drm_xe_engine_class_instance *hwe;
>  	int fd, class, gt;
> 
>  	igt_fixture {
> @@ -211,6 +310,14 @@ igt_main
>  				store_all(fd, gt, class);
>  	}
> 
> +	igt_subtest("cachelines")
> +		xe_for_each_hw_engine(fd, hwe)
> +			store_cachelines(fd, hwe, 0);
> +
> +	igt_subtest("page-sized")
> +		xe_for_each_hw_engine(fd, hwe)
> +			store_cachelines(fd, hwe, PAGES);
> +
>  	igt_fixture {
>  		xe_device_put(fd);
>  		close(fd);
> --
> 2.39.1

LGTM,
Reviewed-by: Janga Rahul Kumar<janga.rahul.kumar@intel.com>